Product Brief HIRes

The
Product Brief
Oct 2007
Ver. 1.4
Group
DN9002K10PCI
XilinxVirtex-5 Based ASIC Prototyping Engine with Dual FPGAs
Features
• PCI-hosted logic prototyping system with 1-2
Xilinx Virtex-5 FPGA's in FF1760 package
(slowest to fastest):
- XC5VLX110-1,-2,-3
- XC5VLX220-1,-2
- XC5VLX330-1,-2
• 100% FPGA resources available for user
application
• Nearly 4M ASIC gates (LSI measure) with 2
LX330’s
• FPGA to FPGA interconnect is single-ended or
LVDS
- 450Mhz DDR LVDS (900Mb/s) chip to chip,
or 225 MHz single-ended
- Reference designs for integrated I/O pad
ISERDES/OSERDES
• 10x pin multiplexing per LVDS pair
- Greatly simplified logic partitioning
- Source synchronous clocking for LVDS
• Main Bus (MB) – 40 signals
- Single-ended
- Connects to both FPGAs and Config FPGA
• Auspy models to aid automatic partitioning
• DDR2 SODIMM (200MHz) on FPGA B
- 64-bit data width, 200MHz operation
- PC2-3200/PC2-4200
- Addressing/power to support 4GB in each socket
- DDR2 Verilog/VHDL reference design
provided (no charge)
- DDR2 SODIMM data transfer rate: 25.6Gb/s
- Alternate pin compatible memory cards
available (consult factory for availability):
• QDR SSRAM, FLASH, SSRAM,
RLDRAM, Mictor, DDR1, DDR3
• 3 board-level global clock networks (GCLK0,
GCLK1, GCLK2)
- Separate programmable synthesizers for each
network
• User configurable via Compact Flash or USB
- Global clocks networks distributed differentially
and balanced
- Single-step clocking available on each global
clock network
• Flexible customization via daughter cards
- 2, 400-pin Meg-Array connectors (FCI)
- 93 LVDS pairs + clocks (or 186 single-ended)
with LX330
- 450MHz on all signals with LVDS
- Signal voltage set by daughter card
- Reset, presence detect
- Supplied power rails (fused):
• +12v (24W max)
• +5V (10W max)
• +3.3V (10W max)
- Pin multiplexing to/from daughter cards using
ISERDES/OSERDES and LVDS (up to 10x)
• Fast and Painless FPGA configuration
- Compact FLASH, PCI, and/or USB
- Integrated sanity checks on configuration files
• Full support for embedded logic analyzers via
JTAG interface
- ChipScope, ChipScope Pro
- Accelerated configuration readback
• Enough status LED’s to blind four, slightly
confused Pacific Northwest tree octopi
(Octopus paxarbolis)
Description
Overview
Virtex5
1
51,840
34,560
17,280
207,360
138,240
69,120
Max
(100% util)*
(1000's)
3,320
2,210
1,110
Practical
(60% util)*
(1000's)
1,990
1,330
670
1,200
800
800
10
10
10
Multipliers
(25x18)
-1,-2
-1,-2,-3
-1,-2,-3
FF's
FF’s in I/O
pad
LX330
LX220
LX110
Gate Estimate
Slices or
LE's
fastest)
Max I/O’s
FPGA
Speed
Grades
(slowest to
fastest)
The DN9002k10PCI is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype
logic and memory designs for a fraction of the cost of existing solutions. The DN9002k10PCI is hosted on a
32/64-bit, 33/66MHz PCI bus, or can be used stand-alone and configured via USB or Compact FLASH. A single
DN9002k10PCI stuffed with 2 Xilinx Virtex-5, XC5VLX330’s can emulate up to 4 million gates of logic as
measured by LSI (or at least how LSI used to measure ASIC gates when they manufactured ASIC’s). This number
does not include the embedded memories and multipliers resident in each FPGA, all of which are 100% available
to user application. The DN9002k10PCI achieves high gate density and allows for fast target clock frequencies by
utilizing FPGA's from Xilinx's Virtex-5 FPGA family for logic and memory. All FPGA resources are available for
the target application. Any subset of FPGA’s can be stuffed.
192
128
64
Memory
Blocks
(18kbits)
Total
(kbits)
Total
(kbytes)
576
384
256
10,368
6,912
4,608
1,296
864
576
Used in
Model
DN9000k10PCI
DN9002k10PCI
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DN9002K10PCI Xilinx Virtex-5 Based ASIC Prototype Engine with Dual FPGAs
Block Diagram
JTAG
ALL FPGAs
RJ45
MICTOR
RS232
DRAM, SRAM,
FLASH, RLDRAM
ALL FPGAs
10/100/1000
ETHERNET
(VSC8601)
DDR2 SODIMM
(4GB Max)
64
12
COMPACT
FLASH
config
Configuration
FPGA
36
32
Spartan 3
MB [35:0]
sma
64 @ 75MHz
Global Clocks
25
MHz
ICS
8442
GCLK0
14.318
MHz
ICS
8442
GCLK1
Step
CLK_FB
64
ICS
8442
48MHz
188
31 62
62
FPGA B
Virtex 5
LX110, LX220 or
LX330
(FF1760)
34
MICTOR
31
31
62
62
MEG Array Expansion
connector (400-pin)
MEG Array Expansion
connector (400-pin)
+1.8V, +2.5V, +3.3V
+1.8V, +2.5V, +3.3V
64 @ 66MHz
EXT1
Daughtercard
B (BOT)
188
125
MHz
QL5064
GCLK2
EXT0
sma
450MHz (900Mb/s)
31
PCI Controller
Daughtercard A
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64
75 Mhz PCICLK
(from FPGA A)
16.0
MHz
160
Virtex 5
LX110, LX220 or
LX330
(FF1760)
clock config
Step
160
FPGA A
uP Config
Control
RS232
64 @ 250MHz
32
Config
USB 2.0
(480 Mb/s)
8 @ 250MHz
ALL FPGAs
66 MHz / 64-bit PCI
+3.3V/5V
32/64 Bit
33/66Mhz
= LVDS when paired, but can be run single-ended
= LX330 only
MB48CLK
2
DN9002K10PCI Xilinx Virtex-5 Based ASIC Prototype Engine with Dual FPGAs
Virtex-5 FPGA’s from Xilinx
The DN9002k10 uses high I/O-count, 1760-pin, flip-chip BGA packages. Abundant fixed interconnects (either
differential or single-ended) are provided between the FPGA's. All pins of all banks of both FPGA are utilized.
FPGA to FPGA busses are routed and tested LVDS, run source synchronously at 450MHz+ but can be used
single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin
multiplexing are included. A 36-pin main bus (MB) is connected to both FPGA’s including the Spartan
configuration FPGA, allowing for data movement via USB.
Daughter Cards
Two separate 400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from
these cards are routed differentially, and can run at the limit of the FPGA: 450MHz. Clocks, resets, and presence
detection, along with abundant power are included in each connector.
Memory
A single DDR2 SODIMM socket is stuffed and is connected to FPGA B. The socket is tested to 250MHz with a
DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM’s (PC2-3200/PC2-4200) work nicely and we can
provide these for a small charge. We have developed alternative SODIMM’s that can be stuffed into these
positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, mictors,
DDR1, and others.
Easy Configuration Via Compact FLASH or USB
The configuration bit files for the FPGA's are copied onto a Compact FLASH card (provided) and an on-board
Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via
the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are
performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration
occurs at the fastest possible SelectMap frequency - 48MHz. Multiple LED's provide instant status and operational
feedback.
Other Cool Stuff
Many FPGA-controlled LEDs provide for visual status. Although no laboratory testing was performed, statistical
animal models are showing this to be enough illumination to blind four very rare, endangered, slightly confused
Pacific Northwest tree octopi (Octopus paxarbolis) A Mictor connector, which has 34 FPGA signals, enables
observation via logic analyzers from Tektronix and HP.
3
the DINI group
DN9002K10PCI Xilinx Virtex-5 Based ASIC Prototype Engine with Dual FPGAs
Included Accessories:
The
For technical applications and sales support, call 858.454.3419
Group
1010 Pearl Street, Suite #6
La Jolla, CA 92037-5165
Phone: 858.454.3419
Fax: 858.454.1728
E-Mail: [email protected]
Web: http://www.dinigroup.com
The DINI Group reserves the right to make changes to the product(s) or information contained herein without notice. No liability is
assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
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