iPORT NTx-GigE IP Core Package
Transcription
iPORT NTx-GigE IP Core Package
D ata S h e e t iPORT NTx-GigE IP Core Package Integrate custom logic with Pleora’s GigE Vision IP core onto a single FPGA Develop Your Own FPGA Loads The iPORT™ NTx-GigE Intellectual Property (IP) Core Package allows system and camera manufacturers to create a custom FPGA (field-programmable gate array) load by integrating their logic with Pleora’s iPORT NTx-GigE IP core. With this package, manufacturers can achieve significant design flexibility, while shortening time-to-market, reducing development and deployment risk, and lowering costs. Typically, integrating multiple functions into a single FPGA load results in boards with lower power consumption, less heat generation, smaller footprints, and lower component costs. Many logic functions can be integrated with the NTx-GigE IP core, including pixel correction, color space conversion, and specialized transformation or analysis tasks. The NTx-GigE IP core package is compatible with the GigE Vision™ and GenICam™ standards, enabling FPGAs produced with the package to interoperate seamlessly with other equipment in a multi-vendor environment. The iPORT NTx-GigE IP Core Package contains: • Pleora’s encrypted IP cores; • Pleora’s Hardware Description Language (HDL) reference design; • Gigabit Ethernet Media Access Controller (MAC); and • Device configuration scripts, which facilitate automation of the programming process during production. Manufacturers can pair the custom FPGA load with Pleora’s offthe-shelf iPORT NTx-GigE Embedded Video Interface hardware, or use the iPORT NTx-GigE Hardware Reference Design to develop customized hardware. HDL Reference Design UART/USRT/I2C Top-Level Interconnect QSYS System PT_BULK_PLC (Pleora Encrypted IP Core) User Logic GPIO Altera DMA Controller Flash Altera Nios II Altera DDR Controller DDR Pixel Bus GigE PHY PT_GEV_STACK (Pleora Encrypted IP Core) For more information, visit www.pleora.com PT_FRAME_GRABBER (Pleora Encrypted IP Core) User Logic User Logic D ata s h e e t iPORT NTx-GigE IP Core Package Benefits of a Custom FPGA Load NTx-GigE IP Core Package Feature Summary Combining Pleora’s and your own custom logic onto a single FPGA can provide a multitude of benefits—lower power consumption, lower heat generation, smaller product size, lower cost, and higher reliability. You can create a single FPGA load that can perform custom pixel correction, color space conversion, or other transformation or analysis, before sending images to Pleora’s NTx-GigE IP core. Your custom logic can communicate with other external devices by making use of the UART or BULK serial data links, which connect your logic to the network using the GigE Vision standard. If a simpler communication method is desired, a GPIO (General Purpose Inputs and Outputs) interface is also provided with the IP Core Package. Feature Description Default User Circuitry Interface •De-serialized Camera Link® (Pixel Bus) FPGA Supported by IP Core •Altera Cyclone V (A4/A5/A7*) *Before using the A7 version, contact Pleora Technologies. FPGA Load •Pixel bus to GigE load provided by Pleora •User defined to GigE Vision load created by customer based on the Pleora IP Core Package •Backup and main loads provided by Pleora •FPGA load licensable with iPORT Authorizer HDL Reference Design •Top-level project files: •Quartus II project files •Scripts •Top-level FPGA interconnect •Qsys System •Encrypted IP cores •Allows for insertion of custom image preprocessing logic •DDR3 and flash sharing •Upgradeable over GigE Embedded Software Library •C++ API •Customizable GenICam feature integration Image Buffer (DDR3) • 16-bit wide • 120 MB DDR3 RAM Network Interface •Compatible with GigE Vision v2.0 GigE PHY •Marvell 88E1510 Persistent Memory •Serial flash •128 Mbit: Winbond W25Q128FVEIG GPIO Inputs/Outputs • 4 x Inputs • 4 x Outputs Camera Control Outputs •4 Serial communication •Routed to the User Circuitry Interface, 2.5 V LVTTL/LVCMOS •3 x UART/USRT or •2 x UART/USRT and 1 x I2C In addition to the FPGA, you can choose to share the same Flash memory or non-volatile memory used by Pleora’s IP core. Pleora’s HDL Reference Design helps speed time-to-market even further by providing pin mappings for the key external interfaces, when you use an Altera Cyclone V FPGA (5CEFA4U19). FPGA Resource Consumption An example of the FPGA resources consumed by the GVSP Stack IP core block in the NTx-GigE IP Core Package (including HDL Reference Design) is shown in the table below: FPGA Grade ALMs Memory PLLs blocks DSP Blocks (Multipliers) (M10k) Cyclone V 5CEFA4U19 C8 16441 Pleora Technologies Inc. 340 Terry Fox Drive, Suite 300 Kanata, Ontario Canada, K2K 3A2 106 2 11 Tel:+1.613.270.0625 Fax:+1.613.270.1425 Email: [email protected] © 2016 Pleora Technologies Inc. iPORT, eBUS, and AutoGEV are trademarks of Pleora Technologies Inc. Information in this document is provided in connection with Pleora Technologies products. No license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted by this document. Pleora may make changes to specifications and product descriptions at any time, without notice. Other names and brands may be claimed as the property of others. EX002-010-0009 Rev 5.0 20/05/2016