Design Guide VT82C694X Apollo Pro133A with VT82C686A South

Transcription

Design Guide
VT82C694X
Apollo Pro133A
with VT82C686A
South Bridge
Preliminary Revision 0.5
November 19, 1999
VIA TECHNOLOGIES, INC.
Copyright Notice:
Copyright © 1999 VIA Technologies Incorporated. Printed in the United States. ALL RIGHTS RESERVED.
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VT82C585, VT82C586B, VT82C587, VT82C590, VT82C595, VT82C596B, VT82C597, VT82C598, VT82C680,
VT82C685, VT82C686B, VT82687, VT82C691, VT82C693, VT82C693A, VT82C694, VT82C694X, VT8501, VT8601,
Super South, Apollo VP, Apollo VPX, Apollo VP2, Apollo VP3, Apollo MVP3, Apollo MVP4, Apollo P6, Apollo Pro,
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Design Guide - VT82C694X Apollo Pro133 with VT82C686A
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REVISION HISTORY
Document
Release
0.5
Date
Revision
Initials
11/19/99
Initial Release (Modified from DG694X&596BR070 and DG693A&686AR060)
VL, JY,
VH, RC,
SS
Preliminary Revision 0.5, November 19, 1999
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TABLE OF CONTENTS
Revision History ............................................................................................................................................i
Table of Contents ..........................................................................................................................................i
List of Figures ...............................................................................................................................................i
List of Tables.................................................................................................................................................i
Introduction ................................................................................................................................................. 1
1.1 About This Design Guide ................................................................................................................................1
1.2 Apollo Pro133A Chipset Overview .................................................................................................................2
1.2.1 VT82C694X Apollo Pro133A North Bridge Features .................................................................................................. 2
1.2.2 Super South (VT82C686A) Chipset Features............................................................................................................... 3
1.2.3 System Block Diagram................................................................................................................................................ 4
1.3 System Design Recommendations ...................................................................................................................5
Motherboard Design Guidelines .................................................................................................................. 7
2.1 Ballout Assignment..........................................................................................................................................7
2.1.1 Apollo Pro133A North Bridge Ballout Assignment...................................................................................................... 7
2.1.2 "Super South" South Bridge Ballout Assignment ......................................................................................................... 8
2.2 Motherboard Description................................................................................................................................9
2.2.1 Slot-1 Motherboard Placement and Routing................................................................................................................. 9
2.2.1.1 ATX Form Factor for Slot-1 System ................................................................................................................... 10
2.2.1.2 Micro ATX Form Factor for Slot-1 System......................................................................................................... 11
2.2.2 Socket-370 Motherboard Placement and Routing....................................................................................................... 12
2.2.2.1 ATX Form Factor for Socket-370 System ........................................................................................................... 13
2.2.2.2 Micro ATX Form Factor for Socket-370 System................................................................................................. 14
2.2.3 Printed Circuit Board Description.............................................................................................................................. 15
2.2.3.1 Four-Layer Board............................................................................................................................................... 15
2.2.3.2 Six-Layer Board................................................................................................................................................. 16
2.2.4 On Board Power Regulation...................................................................................................................................... 17
2.2.5 Capacitive Decoupling .............................................................................................................................................. 17
2.2.5.1 Single Slot-1 Processor Capacitive Decoupling................................................................................................... 18
2.2.5.2 Single Socket-370 Processor Capacitive Decoupling........................................................................................... 19
2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling................................................................................................. 20
2.2.5.4 DRAM Module Capacitive Decoupling .............................................................................................................. 20
2.2.6 Power Plane Partitions .............................................................................................................................................. 21
2.2.6.1 Power Plane Partitions for Slot-1 Motherboard ................................................................................................... 21
2.2.6.2 Power Plane Partitions for Socket-370 Motherboard ........................................................................................... 23
2.2.7 Chipset Power and Ground Layout Recommendations ............................................................................................... 25
2.2.8 Power Up Configuration ........................................................................................................................................... 27
2.2.8.1 VT82C694X Power Up Strappings ..................................................................................................................... 28
2.2.8.2 VT82C686A Power Up Strappings ..................................................................................................................... 28
2.3 General Layout and Routing Guidelines ......................................................................................................29
2.3.1 Trace Attribute Recommendations............................................................................................................................. 29
2.3.2 Apollo Pro133A Clock Layout Recommendations ..................................................................................................... 30
2.3.2.1 Clock Requirements ........................................................................................................................................... 30
2.3.2.2 Clocking Scheme ............................................................................................................................................... 31
2.3.2.3 Clock Routing Considerations ............................................................................................................................ 32
2.3.2.4 System Clock Combinations............................................................................................................................... 33
2.3.2.5 Host CPU Clock and SDRAM Clock Signals...................................................................................................... 34
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2.3.2.6 AGP Clock Signals............................................................................................................................................. 36
2.3.2.7 PCI Clock Signals .............................................................................................................................................. 37
2.3.2.8 Miscellaneous Clock Signals .............................................................................................................................. 37
2.3.2.9 Clock Trace Length Calculation.......................................................................................................................... 38
2.3.3 Routing Styles and Topology..................................................................................................................................... 40
2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines ....................................................................41
2.4.1 Host CPU Interface Layout and Routing Guidelines .................................................................................................. 41
2.4.1.1 Slot-1 Host Interface to North Bridge.................................................................................................................. 41
2.4.1.2 Socket-370 Host Interface to North Bridge.......................................................................................................... 42
2.4.1.3 CPU Host Interface to South Bridge ................................................................................................................... 44
2.4.2 Memory Subsystem Layout and Routing Guidelines.................................................................................................. 46
2.4.2.1 DRAM Routing Guidelines ................................................................................................................................ 46
2.4.2.2 DRAM Reference Layout ................................................................................................................................... 50
2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines ........................................................................................ 52
2.4.3.1 General Layout and Routing Recommendations.................................................................................................. 52
2.4.3.2 Vref Characteristics for AGP 4X Mode............................................................................................................... 53
2.4.3.3 AGP VDDQ Power Delivery .............................................................................................................................. 53
2.4.3.4 AGP VDDQ Power Plane Partition..................................................................................................................... 55
2.4.3.5 Optimized Layout and Routing Recommendations.............................................................................................. 56
2.4.4 PCI Interface Layout and Routing Guidelines ............................................................................................................ 58
2.5 Super South (VT82C686A) Layout and Routing Guidelines .......................................................................59
2.5.1 USB controller.......................................................................................................................................................... 59
2.5.2 AC’97 Link and Game/MIDI Ports............................................................................................................................ 61
2.5.2.1 AC'97 Link ........................................................................................................................................................ 61
2.5.2.2 Game/MIDI ports ............................................................................................................................................... 62
2.5.3 Hardware Monitoring................................................................................................................................................ 63
2.5.4 Integrated Super IO Controller .................................................................................................................................. 64
2.5.5 System Management Bus Interface............................................................................................................................ 65
2.5.6 IDE........................................................................................................................................................................... 66
2.5.7 Suspend to DRM....................................................................................................................................................... 70
2.5.7.1 Suspend DRAM Refresh .................................................................................................................................... 70
2.5.7.2 STR Power Plane Control................................................................................................................................... 71
Timing Analysis and Simulation ................................................................................................................ 73
3.1 SDRAM Timing.............................................................................................................................................73
Electrical Specifications............................................................................................................................. 75
4.1 Absolute Maximum Ratings..........................................................................................................................75
4.2 Recommended Operating Ranges .................................................................................................................75
4.3 DC Characteristics ........................................................................................................................................76
4.4 Power Dissipation ..........................................................................................................................................76
Signal Connectivity and Design Checklist.................................................................................................. 77
5.1 Overview ........................................................................................................................................................77
5.2 VT82C694X Apollo Pro133A North Bridge .................................................................................................78
5.3 "Super South" South Bridge Controller.......................................................................................................81
5.4 Apollo Pro-133A Design Checklist ................................................................................................................90
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
General Layout Considerations Checklist .................................................................................................................. 90
Major Components Checklist .................................................................................................................................... 90
Decoupling Recommendations Checklist................................................................................................................... 91
Clock Trace Checklist ............................................................................................................................................... 92
Clock Trace Length Calculation ................................................................................................................................ 92
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5.4.6 Signal Trace Attribute Checklist................................................................................................................................ 94
Appendices ................................................................................................................................................. 95
Appendix A - SPKR Strapping Application Circuits..........................................................................................97
Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines ...............................................................99
B.1 Introduction ................................................................................................................................................................ 99
B.2 Layout Recommendations ......................................................................................................................................... 100
B.2.1 Component Placement ........................................................................................................................................ 100
B.2.2 Ground and Power Planes: .................................................................................................................................. 103
B.2.3 Routing Guidelines............................................................................................................................................. 105
Appendix C - Apollo Pro133A Reference Design Schematics...........................................................................109
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LIST OF FIGURES
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge ............................................................ 4
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View) ............................................................ 7
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)................................................ 8
Figure 2-3. ATX Placement and Routing Example for Slot-1 System........................................................................................... 10
Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System ................................................................................ 11
Figure 2-5. ATX Placement and Routing Example for Socket-370 System................................................................................... 13
Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System ........................................................................ 14
Figure 2-7. Four-Layer Stack-up with 2 Signal Layers and 2 Power Planes ............................................................................... 15
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes .................................................................................. 16
Figure 2-9. Example of Via Location ......................................................................................................................................... 17
Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor................................................................................ 18
Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor ........................................................................ 19
Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A ..................................................................... 20
Figure 2-13. Decoupling Capacitor Placements for DRAM Modules.......................................................................................... 20
Figure 2-14. ATX Power Plane Partitions for Slot-1 System....................................................................................................... 21
Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System ............................................................................................ 22
Figure 2-16. ATX Power Plane Partitions for Socket-370 System............................................................................................... 23
Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System .................................................................................... 24
Figure 2-18. VT82C694X Power and Ground Layout ................................................................................................................ 25
Figure 2-19. VT82C686A Power and Ground Layout ................................................................................................................ 26
Figure 2-20. A Typical Example of a 3-pin Jumper Strapping Circuit......................................................................................... 27
Figure 2-21. System Clock Connections..................................................................................................................................... 30
Figure 2-22. Apollo Pro133A Chip Clocking Scheme................................................................................................................. 31
Figure 2-23. Clock Trace Spacing Guidelines............................................................................................................................ 32
Figure 2-24. Effect of Ground Plane to a Clock Signal .............................................................................................................. 32
Figure 2-25. Series Termination for Multiple Clock Loads......................................................................................................... 32
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System ........................................................... 34
Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems.................................................. 35
Figure 2-28. AGP Clock Layout Recommendations.................................................................................................................... 36
Figure 2-29. PCI Clock Layout Recommendations..................................................................................................................... 37
Figure 2-30. Daisy Chain Routing Example............................................................................................................................... 40
Figure 2-31. Point-to-Point and Multi-Drop Topology Examples ............................................................................................... 40
Figure 2-32. Alternate Multi-Drop Topology Example............................................................................................................... 40
Figure 2-33. Slot-1 Host Interface Topology Example................................................................................................................ 41
Figure 2-34. Socket-370 Host Interface Topology Example........................................................................................................ 42
Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X .................................................................... 43
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing....................................................... 44
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU...................................................................... 45
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU.............................................................. 45
Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots................................................................................................ 47
Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots .............................................................................................. 48
Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots....................................................................................................... 49
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots................................................................................................. 50
Figure 2-43. DRAM Placement for 133MHz Timing Consideration............................................................................................ 50
Figure 2-44. Layout Example of Three-DRAM DIMM Slots ....................................................................................................... 51
Figure 2-45. General Layout Recommendations of AGP 4X Interface ........................................................................................ 52
Figure 2-46. AGP 2X and 4X Mode Sharing Circuit .................................................................................................................. 53
Figure 2-47. VDDQ Voltage-Switching Application Circuit ....................................................................................................... 54
Figure 2-48. VDDQ Voltage-Switching Application Circuit (II) ................................................................................................. 54
Figure 2-49. AGP VDDQ Power Plane Partition Example......................................................................................................... 55
Figure 2-50. AGP 4X Interface Layout Example ......................................................................................................................... 57
Figure 2-51. Topology Example of AGP and PCI Interface......................................................................................................... 58
Figure 2-52. USB Over-Current Scan Logic .............................................................................................................................. 59
Figure 2-53. USB Differential Signal Routing Example .............................................................................................................. 60
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Figure 2-54. AC'97 Link Example.............................................................................................................................................. 62
Figure 2-55. MIDI/Game Port Application Circuit .................................................................................................................... 62
Figure 2-56. Hardware Monitoring Application Circuit............................................................................................................. 63
Figure 2-57. System Management Bus Interface ........................................................................................................................ 65
Figure 2-58. ISA Bus SA[15:0] / SDD[15:0] Sharing Circuitry.................................................................................................. 66
Figure 2-59. IDE Interfaces Layout Guidelines.......................................................................................................................... 67
Figure 2-60. Ultra DMA/66 Placement and Routing Example.................................................................................................... 68
Figure 2-61. Ultra DMA/66 Application Circuit ......................................................................................................................... 69
Figure 2-62. Suspend DRAM Refresh Application Circuit .......................................................................................................... 70
Figure 2-63. STR State Power Plane Control Application Circuit .............................................................................................. 71
Figure 3-1. CPU Read from SDRAM (SL=2) ............................................................................................................................. 73
Figure 3-2. CPU Post Write to SDRAM (SL=2) ......................................................................................................................... 74
Figure A-1. VT82C686A SPKR Pin Transistor Driver Solution (I) ............................................................................................. 97
Figure A-2. VT82C686A SPKR Pin Inverter Driver Solution (II)................................................................................................ 97
Figure B-1. AC’97 Audio Codec and Game/MIDI Port Block Diagram...................................................................................... 99
Figure B-2. AC’97 Audio Codec and GAME/MIDI Port Placement Example ........................................................................... 100
Figure B-3. Ground Layer Layout Example ............................................................................................................................. 103
Figure B-4. Power Layer Layout Example ............................................................................................................................... 104
Figure B-5. Component Layer Layout Example ....................................................................................................................... 106
Figure B-6. Solder Layer Layout Example ............................................................................................................................... 106
Figure C-1. Apollo Pro133A Reference Component Placement ................................................................................................ 110
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LIST OF TABLES
Table 2-1. Different Board Size Lists for Slot-1 System ................................................................................................................ 9
Table 2-2. Different Board Size Lists for Socket-370 System....................................................................................................... 12
Table 2-3. High Frequency and Bulk Decoupling Capacitor Distribution around Socket-370 ..................................................... 19
Table 2-4. Power-Up Configuration for VT82C694X ................................................................................................................. 28
Table 2-5. Power-Up Configuration for VT82C686A ................................................................................................................. 28
Table 2-6. Recommended Trace Width and Spacing................................................................................................................... 29
Table 2-7. Apollo Pro133A Clock Synthesizer Requirements ...................................................................................................... 30
Table 2-8. Apollo Pro133A System Clock Combinations ............................................................................................................ 33
Table 2-9. Host Control Signals to South Bridge........................................................................................................................ 44
Table 2-10. Memory Subsystem Signals ..................................................................................................................................... 46
Table 2-11. VT82C694X AGP 4X Signal Groups ....................................................................................................................... 52
Table 2-12 Universal Serial Bus (USB) Signals ......................................................................................................................... 59
Table 2-13. Signal Description of AC'97 Link and Game/MIDI Ports......................................................................................... 61
Table 2-14. Resume Events Supported in Different Power States................................................................................................ 71
Table 4-1. Absolute Maximum Ratings....................................................................................................................................... 75
Table 4-2. Recommended Operating Ranges.............................................................................................................................. 75
Table 4-3. DC Characteristics................................................................................................................................................... 76
Table 4-4. Maximum Power Dissipation .................................................................................................................................... 76
Table 5-1. VT82C694X North Bridge Connectivity..................................................................................................................... 78
Table 5-2. VT82C686A South Bridge Connectivity..................................................................................................................... 81
Table 5-3. Recommended Trace Width and Spacing................................................................................................................... 90
Table 5-4. Maximum Accumulated Trace Length ....................................................................................................................... 94
Table B-1. Decoupling Capacitor List ..................................................................................................................................... 101
Table B-2. AC-Coupling Capacitors for Audio Input Signals.................................................................................................... 101
Table B-3. AC-Coupling Capacitors for Audio Input Signals.................................................................................................... 102
Table B-4. Signal Groups Associated with Their Audio Ground Plane...................................................................................... 104
Table B-5. Routing Guidelines for Signal Nets ......................................................................................................................... 107
Table B-6. Routing Guidelines for Power and Ground Nets ..................................................................................................... 107
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INTRODUCTION
This document provides design guidelines for motherboard manufacturers on developing single Slot-1 or Socket-370 processor
and Apollo Pro133A (VT82C694X) based systems. All the major underlying subsystems, especially Host Interface and Memory
subsystems, related to the motherboard design are described in detail. General layouts, routing guidelines and power requirements
of each subsystem are presented.
1.1 About This Design Guide
A brief description of each chapter is given below:
Chapter 1: Introduction.
An overview of Apollo Pro133A reference design features is given in this chapter along with general recommendations on
Pro133A system design.
Chapter 2: Motherboard Design Guidelines.
General design schemes and recommended layout rules are shown in chapter 2. It begins with the 510-pin BGA ballout
assignment. The following sections contain placement and routing of a motherboard, PCB stack-up information and power
requirements for a desktop or a mobile system. Detailed placement, layout, and routing guidelines for each bus or subsystem
(Host bus, Memory subsystem, AGP bus and PCI bus) are described in section 2.4.
Chapter 3: Timing Diagram Analysis.
133 MHz timing analyses for memory read/write cycles are discussed in Chapter 3.
Chapter 4: Electrical Specifications.
The electrical specifications for the VT82C694X North Bridge are listed in this chapter.
Chapter 5: Signal Connectivity and Design Checklist.
The final chapter provides signal connection tables as a brief reference for hardware design engineers who are experienced in PC
motherboard design. Also design checklists are included that can be used for reviewing Pro133A system designs.
Appendices: Reference Design Schematics.
Appendix A shows two power-up strapping circuits for the VT82C686A SPKR pin which determines the function of the
Secondary IDE disk data bus pins (SDD[15..0]) to be either SDD[15..0] (SPKR strapped low) or Audio/Game port functions
(SPKR strapped high).
Appendix B describes the Printed Circuit Board (PCB) layout recommendations for VIA VT1611A (AC’97 audio codec) and
Game/MIDI port in a motherboard design.
Reference schematics for an Apollo Pro133A system design with VT82C686A South Bridge are shown in Appendix C.
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1.2 Apollo Pro133A Chipset Overview
The Apollo Pro133A chip set consists of the VT82C694X system controller (510-pin BGA) and the VT82C686A PCI to ISA
bridge (352-pin BGA). The features for both chips are listed below and a typical system block diagram is shown in this section.
1.2.1 VT82C694X Apollo Pro133A North Bridge Features
Apollo Pro133A (VT82C694X) is a Slot-1 and Socket-370 system logic north bridge with the addition of 133 MHz capability for
both the CPU and SDRAM interfaces. Apollo Pro133A may be used to implement both desktop and notebook personal computer
systems from 66MHz to 133MHz based on 64-bit Slot-1 (Intel Pentium-II) and Socket-370 (Intel and Celeron) processors. The
primary features of the Apollo Pro133A-North Bridge are:
•
•
•
•
•
•
Slot-1 or Socket-370 CPU (Front Side Bus) Interface (66 / 100 / 133MHz)
DRAM Memory Interface (66 / 100 / 133MHz)
AGP Bus Interface (66MHz)
PCI Bus Interface (33MHz)
Mobile Power Management
510-pin BGA Package
The DRAM interface supports eight banks of DRAMs (4 DIMM sockets) although VIA recommends implementation of three
DIMMs maximum for operation of the memory interface at 133 MHz. Total memory supported is 1.5 GB independent of the
number of DIMMs implemented. The DRAM controller supports standard Fast Page Mode (FPM) DRAM, EDO-DRAM,
Synchronous DRAM (SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous
DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability separately selectable
on a bank-by-bank basis. The DRAM controller can run synchronous with the host CPU bus (66 /100 /133 MHz) or synchronous /
pseudo-synchronous with the AGP bus (66 / 133 MHz) with built-in PLL timing control. The DRAM interface can also run either
slower or faster than the CPU interface (both combinations of 66 / 100 MHz or both combinations of 100 / 133 MHz).
The AGP controller supports full AGP v2.0 capability for maximum bus utilization including 2x and 4X mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four level post-write
request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for deep pipelined
and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP / PCI remapping
control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and Windows-98 /
NT5 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable multimedia accelerators.
The VT82C694X supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five
levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are
also implemented for further improvement of overall system performance.
For sophisticated power management, the Apollo Pro133A provides independent clock stop control for the CPU / SDRAM, PCI,
and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented for
the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C686A south bridge chip, a complete
power conscious PC main board can be implemented with no external TTLs.
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1.2.2 Super South (VT82C686A) Chipset Features
The VT82C686A Super-IO PCI Integrated Peripheral Controller (PSIPC) is a high integration, high performance, power efficient
and high compatibility device that supports Intel and non-Intel based processors plus PCI bus bridge functionality to make a
complete Microsoft PC98-compliant PCI/ISA system. In addition to complete ISA extension bus functionality, the VT82C686A
includes the following standard intelligent peripheral controllers:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel commands
4-Port Universal Serial Bus (USB) controller that is USB v1.1 and Universal HCI v1.1 compliant
Keyboard controller with PS2 mouse support
Real Time Clock (RTC) with 256 bytes extended CMOS
Power management (PM) functionality compliant with ACPI and legacy APM requirements
Hardware monitoring subsystem for managing system/motherboard voltage levels, temperatures, and fan speed
Full System Management Bus (SMBus) interface
Two 16550-compatible serial I/O ports with infrared communication port option
Integrated PCI-mastering dual full-duplex direct-sound AC97-link-compatible sound system.
Two game ports and one MIDI port
ECP/EPP-capable parallel port
Standard Floppy Disk Drive (FDD) interface
Distributed DMA capability for support of ISA legacy DMA over the PCI bus. Serial IRQ is also supported for docking
and non-docking applications
Plug and play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA channels to
any interrupt channel
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1.2.3 System Block Diagram
A block diagram of a typical Apollo Pro133A based system with a VT82C686A South Bridge is shown in Figure 1-1. The Apollo
Pro133A supports a single processor including 64-bit Slot-1 (Intel Pentium II TM) or Socket-370 (Intel Celeron TM) CPUs at 66
MHz, 100 MHz or the maximum 133MHz system bus frequency.
Single Slot-1 CPU
Single
Socket-370
CPU
or
HOST BUS
AGP Slot or
3D Graphics
Controller
AGP(4X) BUS
DRAM Interface
Main
Memory
(DRAM)
VT82C694X
PCI5
PCI4
PCI3
PCI2
PCI1
PCI BUS
Hardware
Monitoring
Keyboard
& Mouse
AC'97
Codec
VT82C686A
USB x4
IDE x2
PM Control,
GPIO, Reset
Super IO
BOOT
ROM
ISA2
ISA1
Serial Port x2
Infrared Port x1
Parallel Port x1
FDD x2
ISA BUS
Figure 1-1. Apollo Pro133A System Block Diagram Using the VT82C686A South Bridge
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1.3 System Design Recommendations
The VT82C694X Apollo Pro133A north bridge and VT82C686A south bridge form one of VIA's most optimized chipset
combinations for single Slot-1or Socket-370 based PC systems. On an ATX form factor, for example, the optimized system
specification for such a combination is listed below:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single Slot-1 or Socket-370 CPU (66 / 100 / 133MHz)
Apollo Pro133A single chip clock synthesizer
Apollo Pro133A North Bridge (Host/PCI) Controller
VT82C686A South Bridge (PCI/ISA) Controller
Four DIMM Slots (maximum 2 GB and 133MHz memory frequency)
One AGP Slot (66MHz)
Two PCI Slots (33MHz)
One ISA Slots (8/16MHz)
One AMR Slot (24.576MHz)
One 2MB Flash ROM for system BIOS
One AC’97 Codec Chip (VT1611) to cooperate with an AC’97 Link Controller
Four Universal Serial Bus Ports
PS2 Keyboard/Mouse Support
Two Enhanced IDE Interfaces supporting both ATA-33 and ATA-66
One Floppy Drive Interface
One Infrared Interface
Various Hardware Monitoring functions supporting 5 positive voltages, 3 temperatures, and 2 fan-speed inputs
One Parallel Port and Two Serial Ports
Three Audio Jacks including Audio In, Audio Out and Mic In
One MIDI Port
One Game Port
For the rest of this document, the specification above will be used as a reference example for component placement and PCB
layout.
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MOTHERBOARD DESIGN GUIDELINES
This chapter describes general design schemes and recommended layout rules. It begins with the 510-pin BGA (Pro133A north
bridge) and 352-pin BGA (south bridge) ballout assignments. The following section contains the placement and routing of a
motherboard, PCB stack-up information and power requirements for a desktop system. Detailed placement, layout, and routing
guidelines for each bus or subsystem (Host bus, Memory subsystem, AGP bus and PCI bus) are described in section 2.4.
2.1 Ballout Assignment
Basically, the chipset ballout plays an important role in motherboard designs. It can determine the quality of the Printed Circuit
Board (PCB) layout. The reliability of a motherboard partially depends on the ballout of both the North Bridge and the South
Bridge. To achieve a cost effective and compact 4-layer motherboard, the ballouts should be well defined because they have an
inseparable relationship with component placement and PCB layout.
2.1.1 Apollo Pro133A North Bridge Ballout Assignment
Ballout of the Apollo Pro133A North Bridge is designed to minimize the number of crossover signals. Figure 2-1 shows the four
major signal group quadrants of the Apollo Pro133A Ballout. They are Host, Memory, AGP and PCI interfaces. Please refer to
the VT82C694X datasheet for more details on ball assignments.
1
PCI
A
Host
Apollo Pro-133A
VT82C694X
AGP
510-PIN BGA
Memory
(Top View)
Figure 2-1. Major Signal Group Distributions of the Apollo Pro133A Ballout (Top View)
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2.1.2 "Super South" South Bridge Ballout Assignment
Ballout of the VIA "Super South" South Bridge is designed to minimize the number of crossover signals. Similarly to Figure 2-1,
the major signal group quadrants are shown in Figure 2-2. They are PCI, ISA, Hardware Monitoring, IDE1, IDE2 (shared with
Audio/Game), Super IO (including FDC, COM, LPT, and Infrared interface (not shown) ), USB, Keyboard & Mouse, and a group
of Power Control, GPIO & Reset. Please refer to the VT82C686A datasheet for more details on these ball assignments.
Keyboard
& Mouse
USB
FDC
COM
LPT
1
A
PCI
ISA
SUPER SOUTH
VT82C686A
352-PIN BGA
IDE1
Power Control,
GPIO & Reset
Hardware
Monitoring
IDE2
(Audio/Game)
(Top View)
Figure 2-2. Major Signal Group Distributions of "Super South" South Bridge Ballout (Top View)
Package Information:
•
•
The VIA VT82C694X Apollo Pro133A North Bridge is a 510-pin Ball Grid Array (BGA) package. The package size is
35mm x 35mm and the grid matrix is 26x26.
The VIA "Super South" South Bridge (VT82C686A) is a 352-pin BGA package. The package size is 27mm x 27mm and
the grid matrix is 20x20.
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2.2 Motherboard Description
This section illustrates proposed component placements for an Apollo Pro133A based motherboard with different system
configurations to achieve maximum optimization. The description of the Printed Circuit Board (PCB) for a motherboard is also
given.
2.2.1 Slot-1 Motherboard Placement and Routing
For Slot-1 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the two
most popular form factors (ATX and micro-ATX) are shown in figures 2-3 and 2-4 respectively. Detailed layout guidelines and
signal routings for the Pro133 chipset will be addressed later in section 2.4.
Each figure shows a full size of its respective form factor. The empty area at the bottom of each placement diagram can be
eliminated to reduce the board size. Table 2-1 shows the full size and the suggested compact size for each form factor
implementation.
Table 2-1. Different Board Size Lists for Slot-1 System
Form Factor Type
Full size
ATX
12" x 9.6" (30.5cm x 24.5cm)
Micro-ATX
9.6" x 9.6" (24.5cm x 24.5cm)
Compact Size
12" x 7.9" (30.5cm x 20cm)
9.6" x 7.9" (24.5cm x 20cm)
9
Specification
1 AGP, 5 PCI, 1 ISA, 1 AMR, 3 DIMM
1 AGP, 2 PCI, 1 ISA, 1 AMR, 2 DIMM
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2.2.1.1 ATX Form Factor for Slot-1 System
A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in
Figure 2-3. The major components on the board are single Slot-1 CPU, five PCI slots, one AMR, one ISA slot and three DIMM
slots. This figure shows an ATX motherboard placement as a reference only. The placement should be re-evaluated if a different
combination of AGP, PCI and ISA slots and other motherboard peripherals is desired.
0"
Back Panel Area
1"
2"
3"
Host
PCI
AGP
4"
VT82C
694X
CLK
GEN.
5"
DRAM
6"
VT82C
686A
ISA
IDE
7"
IDE1
IDE2
FDC
8"
9"
9.6"
Figure 2-3. ATX Placement and Routing Example for Slot-1 System
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2.2.1.2 Micro ATX Form Factor for Slot-1 System
A proposed component placement and signal group routings for an Apollo Pro133A micro-ATX system design is illustrated in
Figure 2-4. The major components on the board are single Slot-1 CPU, two PCI slots, one AMR, one ISA slot and two DIMM
slots. This figure shows a reference only micro-ATX motherboard placement. The placement should be re-evaluated if a different
combination of AGP, PCI and ISA slots and other motherboard peripherals is desired.
0"
Back Panel Area
1"
2"
3"
Host
PCI
AGP
VT82C
694X
4"
5"
CLK
GEN.
DRAM
ISA
6"
VT82C
686A
7"
IDE1
IDE
IDE2
FDC
8"
9"
9.6"
Figure 2-4. Micro-ATX Placement and Routing Example for Slot-1 System
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2.2.2 Socket-370 Motherboard Placement and Routing
For Socket-370 CPU and Apollo Pro133A PC motherboard designs, two proposed placements and group signal routings for the
two most popular form factors (ATX and micro-ATX) are shown in figures 2-5 and 2-6 respectively. Detailed layout guidelines
and signal routings for the Pro133A chipset will be addressed later in section 2.4.
Each figure shows a full size of its respective form factor. The empty area at the bottom of each placement diagram can be
eliminated to reduce the board size. Table 2-2 shows the full size and the suggested compact size for each form factor
implementation.
Table 2-2. Different Board Size Lists for Socket-370 System
Form Factor Type
Full size
Compact Size
ATX
12" x 9.6" (30.5cm x 24.5cm) 12" x 8.3" (30.5cm x 21cm)
Micro-ATX
9.6" x 9.6" (24.5cm x 24.5cm) 9.6" x 8.3" (24.5cm x 21cm)
12
Specification
1 AGP, 5 PCI, 1 AMR, 1 ISA, 3 DIMM
1 AGP, 2 PCI, 1 AMR, 1 ISA, 2 DIMM
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2.2.2.1 ATX Form Factor for Socket-370 System
A proposed component placement and signal group routing for an Apollo Pro133A ATX form factor system design is illustrated in
Figure 2-5. The major components on the board are single Socket-370 CPU, five PCI slots, one AMR, one ISA slot and three
DIMM slots. This figure shows an ATX motherboard placement as a reference only. The placement should be re-evaluated if a
different combination of AGP, PCI and ISA slots and other motherboard peripherals is desired.
0"
Back Panel Area
1"
Socket 370
37
1
A
2"
3"
AN
Host
PCI
AGP
4"
VT82C
694X
CLK
GEN.
5"
DRAM
ISA
6"
VT82C
686A
IDE
7"
IDE1
FDC
IDE2
8"
9"
9.6"
Figure 2-5. ATX Placement and Routing Example for Socket-370 System
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2.2.2.2 Micro ATX Form Factor for Socket-370 System
A proposed component placement and signal group routing for an Apollo Pro133A micro-ATX system design is illustrated in
Figure 2-6. The major components on the board are single Socket-370 CPU, two PCI slots, one AMR, one ISA slot and two
DIMM slots. This figure shows a reference only micro-ATX motherboard placement. The placement should be re-evaluated if a
different combination of AGP, PCI and ISA slots and other motherboard peripherals is desired.
0"
Back Panel Area
1"
Socket 370
37
1
A
3"
AN
Host
PCI
AGP
2"
VT82C
694X
4"
5"
CLK
GEN.
DRAM
ISA
6"
VT82C
686A
7"
IDE1
IDE
IDE2
FDC
8"
9"
9.6"
Figure 2-6. Micro-ATX Placement and Routing Example for Socket-370 System
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2.2.3 Printed Circuit Board Description
A brief description of the Printed Circuit Board (PCB) for an Apollo Pro133A based system is provided in this section. From a
cost-effectiveness point of view, a four-layer board is recommended for the motherboard design. For better quality, a six-layer
board is preferred. These two types of boards will be discussed below:
2.2.3.1 Four-Layer Board
A four-layer stack-up with 2 signal layers and 2 power planes is shown in Figure 2-7. The two signal layers are referred to as the
component layer and the solder layer. The two power planes are the power layer and the ground layer. The sequence of
component layer-ground layer-power layer-solder layer is the most common stack-up arrangement from top to bottom. It is
recommended to place a 5~6 mil substrate between the solder layer and the power plane and between the component layer and the
ground plane, with a 42~45 mil substrate between the power and ground planes. Dielectric constant, Er, should be 4.5 for all
substrate materials.
Routing any signal trace on the power planes, either on the power layer or on the ground layer, is not recommended. If a signal
must be routed on the power planes, then it should be routed as short as possible on the power layer, not on the ground layer. The
impedance of all signal layers is to be in the range between 55 ohms and 75 ohms. Lower trace impedance providing better signal
quality is preferred over higher trace impedance for clock signals.
Component layer (0.5 oz. Copper)
Ground layer (1 oz. Copper)
5~6 mils
42~45 mils
Power layer (1 oz. Copper)
Solder layer (0.5 oz. Copper)
5~6 mils
Figure 2-7. Four-Layer Stack-up with 2 Signal Layers and 2 Power Planes
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2.2.3.2 Six-Layer Board
Figure 2-8 illustrates an example of a six-layer stack-up with 4 signal layers and 2 power planes. The layer sequence of
component-ground-internal1-internal2-power-solder is the most common stack-up arrangement from top to bottom. It is
recommended to place a 5~6 mil substrate between the signal layer and the power plane and place 30~35 mil substrate between
two internal layers. A 7-mil substrate must be placed between the power plane and the internal layer. Dielectric constant, Er,
should be 4.5 for all substrate materials.
In order to reduce crosstalk effects between layers, signal traces on the two internal layers should be orthogonal. Routing any
signal trace on the power planes, either on the power layer or on the ground layer, is also not recommended on a six-layer board.
As an exception, if a signal has been routed on the power layer, then it should be routed as short as possible. In any case, routing
on the ground layer is not allowed. The impedance of all signal layers is to be in the range between 55 ohms and 75 ohms. Lower
trace impedance providing better signal quality is preferred over higher trace impedance for clock signals.
Component layer (0.5 oz. Copper)
Ground layer (1 oz. Copper)
5~6 mils
Internal layer #1 (1 oz. Copper)
7 mils
30~35 mils
Internal layer #2 (1 oz. Copper)
Power layer (1 oz. Copper)
7 mils
Solder layer (0.5 oz. Copper)
5~6 mils
Figure 2-8. Six-Layer Stack-up with 4 Signal Layers and 2 Power Planes
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2.2.4 On Board Power Regulation
Currently, the voltage range of the Slot-1 processor core voltage (VCC_CORE) is between 2.1V and 3.3V. And the voltage range
of the Socket-370 processor core voltage is between 1.3V to 2.05V. Local regulation of VCC_CORE is recommended. That is, a
local DC-to-DC converter, placed as close to the CPU as possible, converts a higher voltage to a lower voltage using a linear or
switching (preferred) regulator. Bulk decoupling capacitors (greater than 10uF, Electrolytic or Tantalum) are used to prevent
power supply droop. The closer to the load the capacitor is placed, the more inductance is bypassed.
2.2.5 Capacitive Decoupling
This section describes issues related to the capacitive decoupling of a Slot-1 CPU, Socket-370 CPU, Apollo Pro133A chipsets and
DRAM Modules. It is well known that appropriate decoupling capacitors are required to provide a stable power source to the
CPU, the ASIC and all other components on a motherboard. Moreover, details about capacitor type and placement on a
motherboard are also given.
Decoupling capacitors are required to provide a stable power source to a CPU on a motherboard. Usually, low ESR and low ESL
capacitors are preferred for decoupling. High frequency decoupling capacitors (less than 10uF, ceramic) are used to provide
adequate decouplings. For example, 0.1uF, 1uF and 4.7uF capacitors can be treated as high frequency decoupling capacitors. It is
recommended to keep vias for decoupling capacitors (SMD type) as close to the capacitor pads as possible (see Figure 2-9).
Figure 2-9. Example of Via Location
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2.2.5.1 Single Slot-1 Processor Capacitive Decoupling
Figure 2-10 shows a suggested decoupling capacitor placement for the Slot-1 CPU. The isolation region between any two of the
VCC_CORE (Core voltage 2.1V~3.3V) island, the VCC3 (I/O voltage 3.3V) island, the VTT (GTL+ termination voltage 1.5V)
island and the VCC5 (5V) should be at least 30 mil wide. An island can be an entire power plane or a portion of a power plane
that has been divided. The high frequency decoupling capacitors (0.1uF and 1.0uF) should be located as close to the power and
ground pins of the Slot-1 as possible.
Figure 2-10. Decoupling Capacitor Placement for Single Slot-1 Processor
Notes:
1. The white round dot represents the power pin of the specified power island. For example, there are four VTT power pins on the
VTT island. (Slot-1 CPU power pins: VCC_CORE x 19, VTT x 4, VCC3 x 3 and VCC5 x 1)
2. Recommended numbers of the decoupling capacitors for each power plane are shown in Figure 2-10.
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2.2.5.2 Single Socket-370 Processor Capacitive Decoupling
A suggested decoupling capacitor placement for the Socket-370 CPU is shown in Figure 2-11. The high frequency decoupling
capacitors (0.1uF and 1uF) should be located as close to the power and ground pins of the Socket-370 as possible. One hundred
and twelve 56 ohm termination resistors are required for the GTL+ bus (HD[63:0], HA[31:3] and 19 host control signals) on the
motherboard. There are at least 28 R-packs (4 resistors for a discrete R-pack) for the VTT termination. It is recommended to
place one 1uF decoupling capacitor for each two R-packs. There are also four 1000uF capacitors for GTL+ termination voltage
(VTT) located at the four corners of the Socket-370 in Figure 2-11. Most of the high frequency decoupling capacitors are located
in Socket-370 cavity. The recommended distribution of these high frequency and bulk decoupling capacitors for various voltage
power pins is listed in Table 2-3.
Figure 2-11. Decoupling Capacitor Placement for Single Socket-370 Processor
Table 2-3. High Frequency and Bulk Decoupling Capacitor Distribution around Socket-370
Power Pin Name
VCORE x 59
(CPU Core Voltage)
VREF x 8
(GTL+ Reference Voltage)
VCC15 x 1
(GTL+ Termination Voltage)
VCCCMOS x 1
(CMOS Interface Voltage)
VCC25 x 1
Voltage Level
2.0V or
1.55V (future)
1.0V
(2/3 VCC15)
1.5V
2.5V or
1.5V(future)
2.5V
Decoupling & Bulk Capacitor
4.7uF x 10, 1uF x 23, 0.1uF x 21
1000uF x 6 (4 for switching regular)
0.1uF x 6
1uF x 1, 0.1uF x 1
1uF x 1
1000uF x 4
1uF x 1
Location
Socket-370 inner block
3 at upper middle and 3 at lower middle
Socket-370 inner block
Around Socket-370
Around Socket-370
Four corners of the Socket-370
Around Socket-370
1uF x 1
Around Socket-370
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2.2.5.3 Apollo Pro133A Chipset Capacitive Decoupling
Decoupling capacitors for the VT82C694X and VT82C686A are shown in Figure 2-12. It is recommended to place decoupling
capacitors as close to the chips as possible and evenly distribute these capacitors around them. In most cases, the value of these
decoupling capacitors is 1uF, but 0.1uF capacitors are also acceptable. Similarly, this kind of placement can apply on other ASIC
chips, slots or sockets.
Figure 2-12. Decoupling Capacitor Placements for VT82C694X and VT82C686A
2.2.5.4 DRAM Module Capacitive Decoupling
The capacitive decoupling for SDRAM modules should be taken good care of since SDRAM modules running at 133MHz clock
consume much more power (about 1.76A for each double side DIMM module at maximum). Figure 2-13 shows a placement
example for SDRAM module decoupling.
Figure 2-13. Decoupling Capacitor Placements for DRAM Modules
Note: North Bridge controller (VT82C694X) is located at the north side of these DIMM Slots.
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2.2.6 Power Plane Partitions
The required voltage sources in an Apollo Pro133A system design are: +/-12V, +/-5V, CPU core voltage (1.3V~3.3V defined by
the five voltage identification pins of the Slot-1 or Socket-370 CPU), 3.3V, 2.5V and 1.5V. The power layer is partitioned into
several power islands with five major power sources: VCC_CORE (CPU core voltage), VCC3 (3.3V), VTT (1.5V GTL+
termination voltage), VDDQ (3.3V for AGP 2X mode or 1.5V for AGP 4X mode) and VCC5 (+5V). The remaining power
sources will have their own small power islands or be routed as power traces 20-50 mils wide.
2.2.6.1 Power Plane Partitions for Slot-1 Motherboard
Figure 2-14 shows the power plane partitions on a typical ATX form factor. The island associated with VCC_CORE covers
almost half the area of the Pentium-II socket for the Slot-1 CPU. The VCC3 island covers an area, which contains the North
Bridge chip, the South Bridge chip, all DIMM slots and a half of the AGP slot. The VDDQ island occupies most AGP signal
routing area. The rest of the power layer belongs to VCC5. Different power plane partitions for Micro-ATX form factor are
shown in Figure 2-15. The distribution of power islands is almost the same between ATX and Micro-ATX, except the smaller
VCC5 island on the power layer of the Micro-ATX.
Back Panel Area
VCC5 Island
VCC_CORE Island
VCC5 Island
VCC3 Island
VTT Island
694X
VDDQ Island
VT82C
686A
510-PIN
CLK
GEN.
VCC3 Island
IDE1
IDE2
FDC
VCC5 Island
VCC5 Island
Figure 2-14. ATX Power Plane Partitions for Slot-1 System
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Back Panel Area
VCC5 Island
VCC5 Island
VCC_CORE Island
VCC3 Island
VTT Island
694X
VDDQ Island
510-PIN
CLK
GEN.
VCC3 Island
VT82C
686A
IDE1
IDE2
VCC5 Island
FDC
VCC5 Island
Figure 2-15. Micro-ATX Power Plane Partitions for Slot-1 System
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2.2.6.2 Power Plane Partitions for Socket-370 Motherboard
Figure 2-16 shows the power plane partitions on a typical ATX form factor. The island associated with VCC_CORE covers the
whole area of the PPGA socket for the Socket-370 CPU. The VCC3 island covers an area that contains the North Bridge chip, the
South Bridge chip, all DIMM slots and a half of the AGP slot. The VDDQ island occupies most AGP signal routing area. The
rest of the power layer belongs to VCC5. Different power plane partitions for Micro-ATX form factor are shown in Figure 2-17.
The distribution of power islands is almost the same between ATX and Micro-ATX, except the smaller VCC5 island on the power
layer of the Micro-ATX.
Back Panel Area
VCC5 Island
VCC5 Island
37
Socket 370
VCC_CORE
Island
1
A
AN
VCC3 Island
694X
VDDQ Island
VT82C
686A
CLK
GEN.
510-PIN
VCC3 Island
IDE1
IDE2
VCC5 Island
FDC
VCC5 Island
Figure 2-16. ATX Power Plane Partitions for Socket-370 System
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Back Panel Area
VCC_CORE
Island
VCC5 Island
37
Socket 370
VCC5 Island
1
A
AN
VCC3 Island
694X
VDDQ Island
CLK
GEN.
510-PIN
VCC3 Island
VT82C
686A
IDE1
IDE2
VCC5 Island
FDC
VCC5 Island
Figure 2-17. Micro-ATX Power Plane Partitions for Socket-370 System
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2.2.7 Chipset Power and Ground Layout Recommendations
This section shows the recommended layout of the power plane and the ground plane on each layer for the two VIA BGA chips
(VT82C694X and VT82C686A). Appropriate power and ground distributions for component, ground, power and solder layers can
provide a better power and ground circuit to the chip. Two examples of power and ground layout and signal routings for both
VT82C694X and VT82C686A are shown in Figures 2-18 and 2-19 respectively.
(a) Component Layer
(b) Ground Layer
(c) Power Layer
(d) Solder Layer
Figure 2-18. VT82C694X Power and Ground Layout
Notes:
1. In Figure 2-18 (b) and (c), a black round dot represents a via with no connection to the specified layer and a white round dot
represents a via with a connection to the specified layer. For example, the white round dots in Figure 2-18 (b) are ground
connection vias and the white round dots in Figure 2-18 (c) can be VDDQ or VCC3 connection vias.
2. The square-like rail in the center area of the VT82C694X chip on the component layer in Figure 2-18 (a) connects to ground.
The center square-like block representing an unused routing area connects to ground in Figure 2-18 (d).
3. Pin A1 of the VT82C694X chip is located at the upper-left corner.
4. The left area surrounded by the isolation (black line) is the AGP VDDQ power plane in Figure 2-18 (c).
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(a) Component Layer
(b) Ground Layer
(c) Power Layer
(d) Solder Layer
Figure 2-19. VT82C686A Power and Ground Layout
Notes:
1. In Figure 2-19 (b) and (c), a black round dot represents a via with no connection to the specified layer and a white round dot
represents a via with a connection to the specified layer. For example, the white round dots in Figure 2-19 (b) are ground
connection vias and the white round dots in Figure 2-19 (c) are VCC3 connection vias.
2. The square-like rail in the center area of the VT82C686A chip on the component layer in Figure 2-19 (a) connects to ground.
The center square-like block representing an unused routing area connects to ground in Figure 2-19 (d).
3. Pin A1 of the VT82C686A chip is located at the upper-left corner.
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2.2.8 Power Up Configuration
During system restart and power up, system configuration information is latched at the rising edge of the RESET# signal. All
signals used to select power-up strap options are connected to either internal pull-up or pull-down resistors of minimum 50K ohms
(maximum is 150K ohm). These internal resistors select a default mode on the signal during reset. To enable different modes,
external pull-ups or pull-downs (the opposite of the internal pull-up or pull-down) of approximately 10K ohm can be connected to
particular signals. These pull-ups or pull-downs should be connected to the relative (e.g. 3.3V) power supply. For example, a 3pin jumper is used to select a pull-up (1-2) or pull-down (2-3) strapping as shown in Figure 2-20. The strapping state of logical 1
or logical 0 can be selected by using a jumper (shortage between pins).
VT82C686A
VCC3
(South Bridge)
JCONF
ROMCS#
C1
1
2
4.7~10K
ohm
3
JCONF
1-2
2-3
CPU Configuration
Slot-1 or Socket-370
Socket-7
Header 1x3
Figure 2-20. A Typical Example of a 3-pin Jumper Strapping Circuit
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2.2.8.1 VT82C694X Power Up Strappings
Internal configuration registers of Apollo Pro133A digital core logic are based on the status of memory address lines
(MAB[12:11]#, MAB10, MAB[9:6]#) and Host address lines (A15# and A7#). These memory address signals are pulled up or
pulled down with internal resistors on their I/O buffers to determine the default configurations. If the default configuration setting
is acceptable, no external pulled down resistors are necessary. However, the existence of an external pull-up or pull-down will
insure that the correct configuration is detected. These memory address signals may be pulled up or pulled down with external
resistors to determine the desired configurations. Please refer to Table 2-4 for the power up configuration of all strapping signals.
Table 2-4. Power-Up Configuration for VT82C694X
Signal Name
MAB12#
MAB11#
MAB10
MAB9#
MAB8#
MAB7#
MAB6#
A15#
A7#
Pin #
Strapping Description
AD21 CPU Bus Frequency Select: 0 = 66MHz, 1 = 100MHz
AE21 In Order Queue Depth (IOQD) Enable:
0 = Non-Pipelined, 1 = Maximum Queue Depth Enabled
AB20 Quick Start Select (Mobile only):
0 = Enable Standard Stop Clock Mode, 1 = Enable Quick Start Mode
AC20 AGP Enable: 0 = Enable AGP Function, 1 = Disable AGP Function
AF20 CPU Frequency Select 1: 0 = 66/100MHz, 1 = 133MHz
AB19 Memory Module Configuration:
AB18 Mobile Buffers Enable: 0 = Use Desktop Buffers, 1 = Use Mobile Buffers
E22 Quick Start Select (Mobile only):
0 = Enable Quick Start Mode, 1 = Enable Standard Stop Clock Mode
G24 IOQD Status: 0 = 1, 1 = IOQD set to Maximum
Note
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,3
1,3
Notes:
1. "0" represents the logical state is "low". An external or internal pull-down resistor is required. Conversely, "1" represents the
logical state is "high". An external or internal pull-up resistor is required.
2. MAB11# is connected to an internal 100K ohm pull-up resistor. MAB12#, MAB10, MAB[9:6]# are connected to internal 100K
ohm pull-down resistors.
3. The A15# and A7# are terminated on the CPU bus with GTL+ termination (pull-up resistors).
2.2.8.2 VT82C686A Power Up Strappings
The power up configuration for the VT82C686A South Bridge is shown in Table 2-5 below. The strapping of SPKR (pin V5 of
the VT82C686A) is sampled during reset to determine the usage of the Secondary Disk Data (SDD) pins. When connecting the
SPKR signal to a speaker, the strapping circuit of SPKR is slightly different from the regular strapping circuit. Two application
circuits for SPKR strapping are shown in Appendix A.
Table 2-5. Power-Up Configuration for VT82C686A
Signal Name
SPKR
ROMCS#
Pin #
V5
C1
Strapping Description
Selection for Secondary IDE data bus or Audio/GAME function:
1 = Audio/GAME (Audio/Game uses SDD bus and SA[15:0] can also function as SDD bus).
0 = Secondary IDE data bus (Primary IDE and Secondary IDE have their own data buses).
Selection of Socket-7 configuration or Slot-1 configuration:
1 = Slot-1 for Pentium II or Socket-370 (also called “Socket-9”) for Celeron
0 = Socket-7
Note
1
1
Note:
1. “ 0” represents the logical state is “low”. An external or internal pull-down resistor is required. Conversely, “ 1” represent
the local state is “ high”. An external or internal pull-up resistor is required.
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2.3 General Layout and Routing Guidelines
This section provides general layout rules and routing guidelines for designing Apollo Pro133A motherboards.
2.3.1 Trace Attribute Recommendations
For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised. To reduce
trace inductance, minimum power trace width is set at 30 mils. As a quick reference, recommended trace width and spacing for
different trace types are listed in Table 2-6.
Table 2-6. Recommended Trace Width and Spacing
Trace Type
Signal
Clock
Power
Trace Width (mils)
5 or wider
15 or wider
30 or wider
Spacing (mils)
10 or wider
15 or wider
20 or wider
In high-speed bus design, general rules for minimizing crosswalk are listed below:
•
•
•
•
Maximize the distance between traces. Maintain a minimum 10 mils space between traces wherever possible.
Avoid parallelism between traces on adjacent layers.
Select a board stack-up that minimizes coupling between adjacent traces.
The recommended motherboard impedance should be in the range of 65 ohm +/- 5 ohm.
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2.3.2 Apollo Pro133A Clock Layout Recommendations
2.3.2.1 Clock Requirements
The requirements of the system clock synthesizer for an Apollo Pro133A based system design are listed in Table 2-7.
Table 2-7. Apollo Pro133A Clock Synthesizer Requirements
Clock Signal Type
CPU Clock
SDRAM Clock
SDRAM Clock In
PCI Clock
USB Clock
Super I/O Clock
IOAPIC Clock
Reference Clock
Frequency (MHz) Quantity
Connections
66/75/83/95/
3
Connect to CPU (1), Apollo Pro133A (1) and ITP Debug Port (1)
100/124/133
66/100/133
17
Connect to four SDRAM slots (16) and Apollo Pro133A (1)
66/100/133
1
Connect to Apollo Pro133A (1)
33
7
Connect to Apollo Pro133A (1), South Bridge (1), and PCI slots (5)
48
1
Connect to South Bridge (1)
24
1
Connect to Super I/O (1) if an external Super I/O is used
14.31818
1
Connect to Slot-1 or Socket-370 CPU
14.31818
2
Connect to South Bridge (1) and ISA slots (1)
Note: The voltage level for CPU and IOAPIC clock signals is 2.5V. The voltage level for the remaining clocks is 3.3V.
Figure 2-21 shows clock connections of the system clock synthesizers to their respective destinations.
P
C
I
IOAPIC CLK
PCLK (5)
PCICLK(1)
USBCLK
VT82C686A
Reference CLK
CPUCLK
CPUCLK(1)
System
Clock
Synthesizer
SDCLK
DCLKO
VT82C694X
PCICLK(1)
Super I/O CLK
I
S
A
Slot-1 or
Socket-370
CPU
Super I/O
(If used)
Reference CLK
SDCLK[16:0]
DIMM
Figure 2-21. System Clock Connections
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2.3.2.2 Clocking Scheme
The 17 (66 / 100 / 133MHz) SDRAM clocks are generated from a clock buffer inside the system clock synthesizer. They are
controlled by the SDRAM clock output (DCLKO) provided by the Apollo Pro133A North Bridge. The VT82C694X (North
Bridge) has a built-in de-skew Phase Lock Loop (PLL) circuitry for optimal skew control within and between clocking regions.
For more details, refer to Figure 2-22.
DIMM1
4 SDCLKs to
each DIMM
HCLK
CCLK
DIMM2
External Clock
Synthesizer
with SDRAM
Clock Buffer
DCLK
DIMM3
DCLKO
DRAM Clock
De-skew PLL
DIMM4
DCLK
DCLKI
Clock
Synthesizers
GCLK
GCLKO
GCLK
AGP Clock
De-skew PLL
22 ohm
GCLKO
to AGP slot
22 ohm
GCLKI
GCLK4XI
HCLK:
CCLK:
DCLK:
GCLK:
GCLK4XI:
VT82C694X (North Bridge)
External Host clock - 66MHz / 100MHz / 133MHz
Internal Host clock - 66MHz / 100MHz / 133MHz
Memory (SDRAM) clock - 66MHz / 100MHz / 133MHz
AGP clock - 66MHz only
AGP 4X clock - 266MHz
Figure 2-22. Apollo Pro133A Chip Clocking Scheme
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2.3.2.3 Clock Routing Considerations
Clock routing guidelines are listed below:
•
•
•
•
•
•
The recommended range of a clock trace width is between 15 mils and 20 mils.
The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment
of a clock trace to other segments of the same clock trace is two times of the clock width. That is, more space is needed
from one clock trace to others or its own trace to avoid signal coupling (see Figure 2-23).
Clock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of
its reference ground plane (see Figure 2-24).
Series terminations (damping resistors) are needed for all clock signals (typically 10 ohms to 33 ohms). When two loads
are driven by one clock signal, the series termination layout is shown in Figure 2-25. When multiple loads (more than
two) are applied, a clock buffer solution is preferred.
Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 20 mils to 50
mils) are preferred.
No clock traces on the internal layer if a six-layer board is used.
Clock trace
15 mils
Clock
Synthesizer
Two times of the width
of the clock segment
Clock
Segment
Figure 2-23. Clock Trace Spacing Guidelines
Clock trace
Another
ground
plane
Another
ground
plane
Clock trace
Relative
ground
plane
Relative
ground
plane
RECOMMENDED
NOT RECOMMENDED
Figure 2-24. Effect of Ground Plane to a Clock Signal
Damping resistors
Clock Load
Clock Source
Clock Load
In equal length
In equal length
Figure 2-25. Series Termination for Multiple Clock Loads
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2.3.2.4 System Clock Combinations
The major clock combinations for an Apollo Pro133A based system are listed in Table 8. Clock frequencies for the AGP clock
and PCI clock are 66MHz and 33MHz respectively. Various clock combinations for the CPU clock and the SDRAM clock are
determined by power-up strap options on MAB12# and MAB8#.
Table 2-8. Apollo Pro133A System Clock Combinations
CPU CLOCK
133 MHz
100 MHz
66 MHz
SDRAM CLOCK
133 MHz
100 MHz
133 MHz
100 MHz
66 MHz
100 MHz
66 MHz
AGP CLOCK
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
33
PCI CLOCK
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
CPU/PCI RATIO
4
4
3
3
3
2
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2.3.2.5 Host CPU Clock and SDRAM Clock Signals
Layout recommendations for host clocks and SDRAM clocks for Slot-1 and Socket-370 CPUs are shown in Figure 2-26 and 2-27
respectively. 22 ohm and 10 ohm series terminations are recommended for all host clocks and all SDRAM clocks respectively. It
is also recommended that bypass capacitors be added to all clock signals on the clock synthesizer side. Different values of series
terminations and bypass capacitors are needed for a better clock transmission and alignment on the final PCB layout. In other
words, it is best to observe the actual clock waveform and experimentally determine the optimal values for series termination and
bypass capacitors. For clock alignment considerations, trace lengths of all clocks should match the longest one.
0 ~ 33
ohm
10 ~ 33 pF
LCPU
Slot-1 CPU
LCPU + 3"
VT82C694X
CPUCLK
HCLK
HCLK
LDOUT
0 ~ 33
ohm
DCLKO
SDCLKIN
(as short as possible)
LSD + 4.5"
10 ~ 33 pF
(near the chip)
DCLKWR
SDCLK_F
System
Clock
Synthesizer
10 ~ 33 pF
(near the chip)
LSD
DIMM1
CK0
CK1
CK2
CK3
LSD
DIMM2
CK0
CK1
CK2
CK3
LSD
DIMM3
CK0
CK1
CK2
CK3
LSD
DIMM4
CK0
CK1
CK2
CK3
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDCLK4
SDCLK5
SDCLK6
SDCLK7
SDCLK8
SDCLK9
SDCLK10
SDCLK11
SDCLK12
SDCLK13
SDCLK14
SDCLK15
Figure 2-26. Host Clock and SDRAM Clock Layout Recommendations for Slot-1 System
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0 ~ 33
ohm
10 ~ 33 pF
Socket-370
CPU
LNB
CPUCLK
VT82C694X
LNB
HCLK
HCLK
LDOUT
0 ~ 33
ohm
DCLKO
SDCLKIN
LSD + 4.5"
10 ~ 33 pF
(near the chip)
DCLKWR
SDCLK_F
System
Clock
Synthesizer
10 ~ 33 pF
(near the chip)
LSD
DIMM1
CK0
CK1
CK2
CK3
LSD
DIMM2
CK0
CK1
CK2
CK3
LSD
DIMM3
CK0
CK1
CK2
CK3
LSD
DIMM4
CK0
CK1
CK2
CK3
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDCLK4
SDCLK5
SDCLK6
SDCLK7
SDCLK8
SDCLK9
SDCLK10
SDCLK11
SDCLK12
SDCLK13
SDCLK14
SDCLK15
Figure 2-27. Host Clock and SDRAM Clock Layout Recommendations for Socket-370 Systems
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2.3.2.6 AGP Clock Signals
Layout recommendations for the AGP clock are shown in Figure 2-28. Typically, 22 ohm series terminations are recommended
for the AGP clock. A typical 22 pF bypass capacitor is also required for the AGP clock (GCLKO) to the AGP slot. Depending on
how the system is designed, the value of the bypass capacitors for the PCI clocks may vary. For clock alignment considerations, 3
more inches than that of the AGP clock trace to the AGP slot are added to the feedback AGP clock trace length. (Note: the 3
inches represents the estimated distance from the GCLK pin of a AGP slot to the GCLK pin of the VGA chip on an AGP video
card.) Some layout guidelines for the AGP clock are listed below:
•
•
The trace length of the two separate GCLKO signals from pin N4 of the VT82C694X chip to the damping resistors
should be equal and less than 1 inch.
Both C1 and C2, which should be placed very close to the VT82C694X chip and the AGP slot respectively, are used to
control the AGP clock alignment. (See Figure 2-28).
VT82C694X
(North Bridge)
GCLKO
AGP Slot
0 ~ 33
ohm
N4
LGOUT
LGOUT + 3"
GCLK
B7
GCLK
C2
0 ~ 33 pF
(near the slot)
N5
C1
0 ~ 33 pF
(near the chip)
Figure 2-28. AGP Clock Layout Recommendations
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2.3.2.7 PCI Clock Signals
Layout recommendations for the PCI clocks are shown in Figure 2-29. Typically, 22 ohm series terminations are recommended
for all PCI clocks. A typical 22 pF bypass capacitor is also required for each PCI clock. Depending on how the system is
designed, the value of the bypass capacitors for the PCI clocks may vary. For clock alignment considerations, trace lengths of all
PCI clocks should match the longest one.
0 ~ 33
ohm
10 ~ 33
pF
L5 + 3" (LNB)
VT82C694X
L5 + 3" ( LSB )
VT82C686A
NPCLK
(North Bridge)
System
Clock
Synthesizer
SPCLK
(South Bridge)
L5 ( L1 )
PCLK0
P
C
I
2
L5 ( L2 )
PCLK1
L5 ( L3 )
PCLK2
P
C
I
4
L5 ( L4 )
PCLK3
L5
PCLK4
( Assume L5 > L1 , L2 and the rest )
P
C
I
1
P
C
I
3
P
C
I
5
Figure 2-29. PCI Clock Layout Recommendations
2.3.2.8 Miscellaneous Clock Signals
22 ohm series terminations are recommended for clock signals such as the USB clock (48 MHz), Super I/O clock (typically 24
MHz), IOAPIC clock (14.31818MHz, 2.5V interface) and reference clock (14.31818 MHz, 3.3V interface) which are generated
from the system clock synthesizer. The trace width for the clocks above should be at least 15 mils. To reduce crosstalk impact,
trace spacing between these clocks and other signals should be maintained at a minimum of 15 mils. In order to maintain the
clock signal quality, the trace length of these clock signals, especially USBCLK, should be as short as possible or less than 9
inches.
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2.3.2.9 Clock Trace Length Calculation
The calculation is based on the recommended placements shown in sections 2.2.1 and 2.2.2. A different component placement
may result in a different calculation for the clock trace length.
CPU Clock Trace Length Calculation for Slot-1 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Slot-1
CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of the
longest one (usually CPUCLK around 3700 mils). Please refer to the component placements in figures 2-3 and 2-4. A calculation
example is shown below.
Clock Trace
Shortest
Length
LCPU
LNB
Clock chip à CPU
Clock chip à VT82C694X (NB)
Desired
Length
LCPU
LCPU + 3"
Allowable
Difference
0.5"
Allowable
Range
1"~9"
4"~12"
Note: Here, the 3" represents the estimated trace length added into HCLK for CPU clock alignment.
CPU Clock Trace Length Calculation for Socket-370 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Socket370 CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of
the longest one (usually HCLK around 5500 mils). Please refer to the component placements in figures 2-5 and 2-6. A calculation
example is shown below.
Clock Trace
Shortest
Length
LCPU
LNB
Clock chip à CPU
Desired
Length
LNB
LNB
Allowable
Difference
0.5"
-
Allowable
Range
1"~9"
1"~9"
SDRAM Clock Trace Length Calculation
Pre-route SDRAM clock traces (SDCLK0~SDCLK11) from the system clock synthesizer to the DIMM slots as short as possible.
The length of all SDRAM clocks will be based on the longest one (LSD). The length of DCLKWR (LDIN) should be the same as
that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Clock Trace
Clock chip à SDCLK[15:0]
DCLKWR (Clock chip à NB)
DCLKO (NB à Clock chip)
Shortest
Length
LSD
LDIN (assume < LSD +3")
LDOUT
Desired
Length
LSD
LSD + 4.5"
LDOUT
Allowable
Difference
0.5"
0.5"
-
Allowable
Range
1"~4"
4"~7"
1"~9"
Note: Here, the 4.5” represents the estimated trace length added into DCLKI for SDRAM clock alignment.
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AGP Clock Trace Length Calculation
Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length
for the signal GCLK should be the GCLKO trace length plus 3 inches.
Clock Trace
GCLKOUT (NB à AGP Slot)
GCLKIN (NB à NB)
Shortest
Length
LGOUT
LGIN
Desired
Length
LGOUT
LGOUT + 3"
Allowable
Difference
0.5"
Allowable
Range
1"~9"
4"~12"
Note: Here, the 3" represents the estimated trace length added into GCLKI for AGP clock alignment.
PCI Clock Trace Length Calculation
Pre-route PCI clock traces from the system clock synthesizer to the VT82C694X (NPCLK) and VT82C686A (SPCLK) as short as
possible. Then pre-route PCI clock traces PCLK0~PCLK4 from the system clock synthesizer to all PCI slots as short as possible.
The length of these clocks will be based on the longest one (L5 ). Usually PCI5 is the farthest PCI slot from the North Bridge chip.
A calculation example is shown below.
Clock Trace
Clock chip à VT82C686A (SB)
Clock chip à PCI1
Clock chip à PCI2
Clock chip à PCI3
Clock chip à PCI4
Clock chip à PCI5
Shortest
Length
LNB
LSB
L1
L2
L3
L4
L5 ( > the others)
Desired
Length
L5 + 3"
L5 + 3"
L5
L5
L5
L5
L5
Allowable
Difference
1"
1"
1"
1"
1"
1"
-
Allowable
Range
4"~15"
4"~15"
1"~12"
1"~12"
1"~12"
1"~12"
1"~12"
Note: Here, the 3" represents the estimated trace length added into NPCLKI and SPCLK for PCI clock alignment.
Notes for the length calculation of all clock traces:
1. Shortest length means the minimum routable trace length between both clock ends.
2. Desired length means the real length of the clock traces on PCB layout.
3. Allowable difference means the maximum length difference between clock traces of the same type.
4. Allowable range means the acceptable clock length range for the specific clock.
5. The location of the system clock chip can affect the length of all clock traces. To optimize the clock alignment, place the clock
chip at an appropriate location.
6. In addition, the trace impedance of all clock traces should be in the range of 40 ohms and 55 ohms.
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2.3.3 Routing Styles and Topology
High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising edge caused by the high
impedance of the output buffer in the high state. In order to maintain better signal quality, transmission stubs should be kept under
1.5 inches. Therefore, daisy chain style routing is strongly recommended for these signals. Figure 2-30 below shows an example
of a daisy chain routing.
Trace Length
ASIC
ASIC
Short Stub
ASIC
or
Connector
ASIC
or
Connector
Figure 2-30. Daisy Chain Routing Example
Topology is the physical connectivity of a net or a group of nets. Basically, there are two types of topologies for a motherboard
layout: point-to-point and multi-drop. An example of these topologies is shown in Figure 2-31.
Multi-Drop
ASIC
ASIC
Point-to-Point
ASIC
or
Connector
ASIC
or
Connector
Figure 2-31. Point-to-Point and Multi-Drop Topology Examples
If daisy chain routing is not allowed in some circumstances, different routings may be considered. An alternative topology is
shown in Figure 2-32. The branch point in this case is somewhere between both ends. It may be near the source or near the loads.
Being close to the load side is best. The separated traces should be equal length.
ASIC
or
Connector
ASIC
Equal Length
Somewhere in
the middle
ASIC
or
Connector
Figure 2-32. Alternate Multi-Drop Topology Example
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2.4 VT82C694X Apollo Pro133A Layout and Routing Guidelines
2.4.1 Host CPU Interface Layout and Routing Guidelines
The GTL+ signals (host address bus, host data bus and host control signals) are typical point-to-point connections between CPU
and North Bridge in a Slot-1 or Socket-370 system design. VTT (1.5V) terminations are required for GTL+ signals. Except for
FERR#, all host control signals from the VT82C686A South Bridge to Slot-1 or Socket-370 CPU are open drain (OD) signals.
2.5V pull-ups are required for those open drain signals on the VT82C686A chip side. The routing topology for both signal groups
from VT82C694X and VT82C686A uses point-to-point connections. Recommended layout guidelines and routing examples for
GTL+ and OD signals are given in the following sections.
2.4.1.1 Slot-1 Host Interface to North Bridge
The recommended topology for Slot-1 host signals to the North Bridge (VT82C694X) is shown in Figure 2-33. For signal quality
considerations, the trace length of the host address bus should be minimized. No VTT terminations are required for a Slot-1
system since they are built in to both the Slot-1 CPU and the VT82C694X.
•
It is recommended to route all host signals to the VT82C694X in equal length and as short as possible. A minimum of 5
mils in width and a minimum of 10 mils in spacing are required for those host signals. The trace length of those signals
should be less than 4.5 inches.
VT82C694X
(North Bridge)
Total Trace Length (L) < 4.5"
Slot-1 CPU
L
A[31..3]
A[31..3]
D[63..0]
D[63..0]
DBSY#
DRDY#
HIT#
HITM#
REQ[4..0]#
TRDY#
RS[2..0]#
DBSY#
DRDY#
HIT#
HITM#
HREQ[4..0]#
HTRDY#
RS[2..0]#
BPRI#
BREQ0#
DEFER#
CPURST#
BPRI#
BR0#
DEFER#
RESET#
LOCK#
HLOCK#
Figure 2-33. Slot-1 Host Interface Topology Example
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2.4.1.2 Socket-370 Host Interface to North Bridge
The recommended topology for the Socket-370 host signals to North Bridge (VT82C694X) is shown in Figure 2-34. For signal
quality considerations, the trace length of the host signals should be minimized. 56 ohm pull-ups to VTT near the Socket-370
CPU are required.
•
•
•
It is recommended to route all host signals to VT82C694X in equal length and as short as possible. A minimum of 5 mils
in width and a minimum of 10 mils in spacing are required for those host signals. Wide traces for VTT pull-ups are
recommended.
There is no stub before traces L1 and L2. Two traces directly come out the pin of the Socket-370. The location of these
56 ohm resistor networks should be as close to Socket-370 CPU as possible.
The most qualified range of the L1 trace length is between 1.5 inches and 4.5 inches. The trace length of L2 should be
less than 2 inches.
VTT
56 ohm
L2 < 2"
VT82C694X
(North Bridge)
Socket-370
CPU
1.5 < L1 < 4.5"
L1
A[31..3]
A[31..3]
D[63..0]
D[63..0]
ADS#
BNR#
DBSY#
DRDY#
HIT#
HITM#
HREQ[4..0]#
HTRDY#
RS[2..0]#
ADS#
BNR#
DBSY#
DRDY#
HIT#
HITM#
REQ[4..0]#
TRDY#
RS[2..0]#
BPRI#
BREQ0#
DEFER#
CPURST#
BPRI#
BR0#
DEFER#
RESET#
HLOCK#
LOCK#
Figure 2-34. Socket-370 Host Interface Topology Example
A layout example for the host interface between the Socket-370 CPU and the VT82C694X chip is shown in Figure 2-35. The
VTT rail (a minimum of 200 mils wide) covering three sides of the Socket-370 on the component layer can provide a sufficient
GTL+ termination voltage supply path in Figure 2-35 (a).
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(a) Component Side
(b) Solder Side
Figure 2-35. Host Interface Layout Example between Socket-370 and VT82C694X
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2.4.1.3 CPU Host Interface to South Bridge
The host control signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed in Table 2-9. Except for
FERR#, all signals are open drain (OD). 2.5V pull-ups are required for those open drain signals on the VT82C686A chip side.
Table 2-9. Host Control Signals to South Bridge
Signal Name
A20M#
CPURST
FERR#
IGNNE#
INIT
INTR
NMI
SLP#
STPCLK#
SMI#
I/O
OD
OD
I
OD
OD
OD
OD
OD
OD
OD
South Bridge -- CPU
Description
A20 Mask
CPU Reset
Numerical Coprocessor Error
Ignore Numerical Error
Initialization
CPU Interrupt
Non-Maskable Interrupt
Sleep
Stop Clock
System Management Interrupt
In a Slot-1 system design, pins A20M#, IGNNE#, INTR (LINT0) and NMI (LINT1) are shared with the external CPU clock ratio
straps. The schematic for this pin sharing is shown in Figure 2-36. These pins strap the setting of the CPU clock ratio during reset
and two clocks beyond the end of the RESET# pulse. Afterwards, the functionality of these signals will work as their names are
defined. (Note: This ratio select logic is also required in the Q-Spec Socket-370 system design.)
VCC3
4.7K
ohm
JUMPER
1
2
3
5
4
6
7
8
VCC2_5
U1
VT82C686A
2
4
(South Bridge)
6
8
11
13
A20M#
IGNNE#
INTR
NMI
15
17
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
330
ohm
18
16
14
12
U2
9
7
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
5
3
VCC3
VCC3
10K
ohm
1
19
OE0#
OE1#
Slot-1
CPU
LVT07
20
LVT244
CRESET#
From
VT82C694X
U3
NC7S04
Note: LVT244, LVT07 and NC7S04 operate at the 3.3 volt interface.
Figure 2-36. Schematic Example for Slot-1 CPU Internal/External Clock Ratio Pin Sharing
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A layout example for the remaining control signals between the VT82C686A chip and the Slot-1 CPU is shown in Figure 2-37.
VCC2_5
330
ohm
VT82C686A
Slot-1
CPU
(South Bridge)
INIT
SLP#
SMI#
STOPCLK#
INIT
SLP#
SMI#
STOPCLK#
FERR#
FERR#
CPURST
Layout these traces
as short as possible
No Connect
Figure 2-37. Layout Example of Control Signal from South Bridge to Slot-1 CPU
No sharing circuitry is required in an S-Spec Socket-370 system design because the S-Spec Socket-370 CPU runs at marked ratio
only. A layout example for all control signals between the VT82C686A chip and the Socket-370 CPU is shown in Figure 2-38.
Currently, the voltage level of VCC_CMOS is 2.5V.
VCC_CMOS
330
ohm
VT82C686A
(South Bridge)
A20M#
IGNNE#
INTR
NMI
INIT
SLP#
SMI#
STOPCLK#
Socket-370
CPU
A20M#
IGNNE#
INTR(LINT0)
NMI(LINT1)
INIT
SLP#
SMI#
STOPCLK#
FERR#
FERR#
Layout these traces as short as possible
CPURST
No Connect
Figure 2-38. Layout Example of Control Signal from South Bridge to Socket-370 CPU
The layout guidelines for these signals from the Slot-1 or Socket-370 CPU to the south bridge (VT82C686A) are listed below.
•
•
•
Each south bridge Open Drain (OD) output control signal to the CPU needs a 150 ~ 450 ohm pull-up which should be
placed as close to the VT82C686A chip as possible.
A minimum of 5 mils in width and a minimum of 10 mils in spacing are sufficient for good signal quality.
No specific limitation of the trace length for these control signals is required.
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2.4.2 Memory Subsystem Layout and Routing Guidelines
2.4.2.1 DRAM Routing Guidelines
Most DRAM signals are multi-drop connections. A brief description of the memory subsystem signals is provided in Table 2-10
below.
Table 2-10. Memory Subsystem Signals
Signal Name
MAA[14:0]
MAB[14:11]#, MAB10, MAB[9:0]#
MD[63:0]
MECC[7:0]
RASA[5:0]#
RASB[5:0]#
CASA[7:0]#
CASB5#, CASB1#
SRASA#
SRASB#
SCASA#
SCASB#
SWEA#
SWEB#
North Bridge -- DRAM
I/O
Description
O Memory Address for the group A
O Memory Address for the group B
IO Memory Data for all four DIMM modules
IO DRAM ECC or EC Data for all four DIMM modules
O Row Address Strobe of each bank
O Row Address Strobe of each bank
O Column Address Strobe of each byte lane for the group A
O Column Address Strobe of each byte lane for the group B
O Row Address Command Indicator for the group A
O Row Address Command Indicator for the group B
O Column Address Command Indicator for the group A
O Column Address Command Indicator for the group B
O Write Enable Command Indicator for the group A
O Write Enable Command Indicator for the group B
Note: Group A represents the first two DIMM modules and group B represents the remaining (one or two) modules. CASA[7:6,
4:2, 0]# can also be connected to the DIMM modules of group B.
The maximum DRAM installation is four DIMM slots. Three layout examples (Daisy Chain Ordering) for all DRAM buses and
control signals between the Apollo Pro133A North Bridge and four, three or two DRAM DIMM slots are shown in Figure 2-39, 240 and 2-42 respectively. One T-Style layout example for DRAM signals, such as MD[63:0] and MECC[7:0], between the Apollo
Pro133A North Bridge and three DRAM DIMM slots is shown in Figure 2-41. Routing recommendations for the DRAM interface
are listed below.
•
•
•
•
Traces for all DRAM signals should be a minimum of 5 mils in width and 10 mils in spacing. The accumulated trace
length for all signals should be under 4 inches to meet 133 MHz timing requirements. The length difference among traces
should be minimized.
The DRAM interface damping resistors are no longer needed.
For daisy chain routing, traces of MD[63:0], CASA[7:0]# and MECC[7:0] should be connected to the DIMM modules in
order of DIMM4, DIMM3, DIMM2 and DIMM1 (see Figure 2-39). DIMM4 is the closest DIMM slot to the
VT82C694X chip.
It is recommended to make segments L2, L3 and L4 as short as possible in Figure 2-39.
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VT82C694X
DIMM4
(North Bridge)
2" < L1 < 2.5"
DIMM3
0.4" < L2 < 0.5"
DIMM2
DIMM1
0.4" < L4 < 0.5"
0.4" < L3 < 0.5"
MD[63:0]
MECC[7:0]
CASA[7,6,4:2,0]#
2" < L5 < 3"
MAA[14:0]
SWEA#
SRASA#
SCASA#
CASA[5,1]#
2" < L6 < 3.5"
MAB[14:0]#
SWEB#
SRASB#
SCASB#
CASB[5,1]#
RASA[1:0]#
RASB[1:0]#
2" < L7 < 4"
RASA[3:2]#
RASB[3:2]#
RASA[5:4]#
RASB[5:4]#
RASA[7:6]#
RASB[7:6]#
(Group B)
(Group A)
Note: MAB[14:0]# represents MAB[14:11]#, MAB10 and MAB[9:0]#.
Figure 2-39. Daisy Chain Routing for Four-DRAM DIMM Slots
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VT82C694X
DIMM3
(North Bridge)
2" < L1 < 3"
DIMM2
0.4" < L2 < 0.5"
DIMM1
0.4" < L3 < 0.5"
MD[63:0]
MECC[7:0]
CASA[7,6,4:2,0]#
2" < L4 < 3.5"
MAA[14:0]
SWEA#
SRASA#
SCASA#
CASA[5,1]#
2" < L5 < 4"
MAB[14:0]#
SWEB#
SRASB#
SCASB#
CASB[5,1]#
RASA[1:0]#
RASB[1:0]#
RASA[3:2]#
RASB[3:2]#
RASA[5:4]#
RASB[5:4]#
RASA[7:6]#
RASB[7:6]#
No Connet
(Group B)
(Group A)
Figure 2-40. Daisy Chain Routing for Three-DRAM DIMM Slots
Note: Comparing to T-Style routings in Figure 2-41, the advantages of Daisy Chain Ordering routings are lower crosstalk
between traces, easier layout.
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DIMM3
VT82C694X
DIMM2
DIMM1
(North Bridge)
0.4" < L2 < 0.5"
0.4" < L3 < 0.5"
2" < L1 < 3.5"
MD[63:0]
MECC[7:0]
CASA[7,6,4:2,0]#
2" < L4 < 3.5"
0.4" < L5 < 0.5"
MAA[14:0]
SWEA#
SRASA#
SCASA#
CASA[5,1]#
2" < L6 < 4"
MAB[14:0]#
SWEB#
SRASB#
SCASB#
CASB[5,1]#
RASA[1:0]#
RASB[1:0]#
RASA[3:2]#
RASB[3:2]#
RASA[5:4]#
RASB[5:4]#
RASA[7:6]#
RASB[7:6]#
No Connet
(Group B)
(Group A)
Figure 2-41. T-Style Routing for Three-DRAM DIMM Slots
Note: Comparing to Daisy Chain Ordering routings in Figure 2-40, the advantage of T-Style routings is less signal reflection on
traces.
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VT82C694X
DIMM2
(North Bridge)
2" < L1 < 3.5"
DIMM1
0.4" < L2 < 0.5"
MD[63:0]
MECC[7:0]
CASA[7:0]#
MAA[14:0]
SWEA#
SRASA#
SCASA#
RASA[1:0]#
RASB[1:0]#
2" < L3 < 4"
RASA[3:2]#
RASB[3:2]#
(Group A)
MAB[14:0]#
No Connet
SWEB#
SRASB#
SCASB#
No Connet
CASB[5,1]#
No Connet
RASA[5:4]#
RASB[5:4]#
No Connet
RASA[7:6]#
RASB[7:6]#
No Connet
Figure 2-42. Daisy Chain Routing for Two-DRAM DIMM Slots
2.4.2.2 DRAM Reference Layout
Maintaining DRAM trace length less than 4 inches is required to fulfill 133 MHz DRAM timing requirements. A placement
example of the VT82C694X chip and 3 DIMM slots is shown in Figure 2-43. The VT82C694X chip is located at the top of the
middle of 3 DIMM slots. The distance between the chip and the closest DIMM slot (DIMM3) is 0.55 inch. The distance between
the centers of two adjacent DIMM slots is 0.4 inch.
VT82C
694X
0.55"
DIMM3
DIMM2
DIMM1
0.4"
Figure 2-43. DRAM Placement for 133MHz Timing Consideration
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The reference layout for three-DRAM DIMM slots is shown in Figure 2-44 below. In this layout example, no DRAM trace is over
4 inches long and those traces are also evenly distributed.
(a) Component Side
(b) Solder Side
Figure 2-44. Layout Example of Three-DRAM DIMM Slots
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2.4.3 AGP (4X Mode) Interface Layout and Routing Guidelines
This section describes layout and routing guidelines to insure a robust AGP 4X mode interface design. The following guidelines
will help insure that the AGP specification can be met. The system designer should do appropriate analysis and simulation to
verify that the design fulfills AGP specification requirements.
2.4.3.1 General Layout and Routing Recommendations
There are three major groups of AGP control, data and their associated strobe signals listed in Table 2-11. The remaining AGP
signals include AGPVREF (AGP reference voltage input), GCLK and GCLKO (AGP clock input and output), VDDQ/GND
(power/ground) and NCOMP and PCOMP (digital compensation).
Table 2-11. VT82C694X AGP 4X Signal Groups
AGP Signal Groups
Data / Strobe
Control
VT82C694X (4X mode)
Group 1: GD[15:0], GBE[1:0]# / GDS0 and GDS0#
Group 2: GD[31:16], GBE[3:2]# / GDS1 and GDS1#
Group 3: SBA[7:0] / SBS and SBS#
GFRM#, GIRDY#, GTRDY#, GSTOP#, GDSEL#, GPIPE#, GRBF#,
ST[2:0], GREQ#, GGNT#, GPAR and GWBF# (14 signals)
Note: The AGP signal naming convention here (and in the VT82C694X datasheet) is slightly different from that in the AGP
Specification.
General routing guidelines for the connections between the VT82C694X chip and the AGP slot are shown in Figure 2-45. These
guidelines were created to give freedom to designs by making tradeoffs between signal coupling and line length. However, AGP
signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface
specification.
VT82C694X
AGP 4X
Graphics
Card
(North Bridge)
Total trace length (L)
(Data, Strobe and Control)
AGP Slot
(Universal)
Guidelines:
1. Data and Control (width:Spacing) Routings are (1:3) in the range of 1" < L < 4".
2. Strobe Routings are (1:4) to Strobe and (1:6) to other signals.
3. The recommended motherboard impedance for AGP 4X is 65 ohm +/- 5 ohm.
Figure 2-45. General Layout Recommendations of AGP 4X Interface
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2.4.3.2 Vref Characteristics for AGP 4X Mode
Vref is a DC voltage reference signal used to set the input sense level on the AGP bus. Vref is set at 0.5 x VDDQ (between 0.48 x
VDDQ and 0.52 x VDDQ) for AGP 4X mode. Referring to Figure 2-46 for an AGP 4X mode implementation, two unidirectional
Vref pins are provided in the connector. These pins connect Vref between the add-in card graphics chip and the VT82C694X chip.
Typical values of the resistors and capacitors in the voltage divider network are shown in the figure. The Vref resistor divider
network must be placed away from critical and noisy signals, especially 3.3V swing signals. Guard (ground) trace should be
implemented if adjacent to 3.3V swing signal cannot be avoided. To avoid signal crosstalk from other signal lines, the trace to the
Vref input pin should be kept away from other noisy traces in the board layout. Decoupling capacitors should not be implemented
directly on Vref for better tracking between VDDQ and Vref.
AGP Add-in Card
Motherboard
AGP (4X)
Connector
VDDQ
Graphics
Chip
560 pF
1K ohm
Vref
(0.5 x VDDQ)
75 ohm
B66
1K ohm
VDDQ
560 pF
560 pF
75 ohm
75 ohm
VT82C694X
(North Bridge)
75 ohm
(0.4 x
VDDQ)
1K ohm
A66
(0.5 x VDDQ)
A2
VoltageSwitching
Circuit
Vref
Vref
1K ohm
560 pF
TYPEDET#
VDDQ
Note: TYPEDET# provided by the AGP add-in card is used to determine the VDDQ (1.5V or 3.3V)
through a switching or linear regulator.
Figure 2-46. AGP 2X and 4X Mode Sharing Circuit
2.4.3.3 AGP VDDQ Power Delivery
AGP 2X (or 1X) mode can operate in either 3.3V interface or 1.5V interface. However, AGP 4X mode uses only 1.5V interface.
For sharing of both AGP interfaces, switching between two different voltage supplies (3.3V and 1.5V) for the AGP slot should be
taken into account. Refer to Figure 2-46 above for the AGP 2X and 4X mode sharing circuit. Pin A2 (TYPEDET#) of the AGP
slot is used to determine the AGP operating voltage (VDDQ) through the voltage switching circuit. For example, the AGP
interface is 1.5V if the TYPEDET# is shorted to ground (or activated to low) on the add-in card side. However, when TYPEDET#
is open (not connected to any power rail or signal), the voltage switching circuit outputs 3.3V VDDQ. At the same time, Vref of
0.4 x VDDQ for 3.3V signaling is internally generated in VT82C694X and external Vref of 0.5 x VDDQ for 1.5V signaling on
board is disconnected.
In the case of a universal 1.5V / 3.3V signaling system, an on-board voltage regulator is preferred. The voltage level of the
regulator is controlled by the TYPEDET# signal which is controlled by the add-in card.
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Figure 2-47 shows an application example for the VDDQ Voltage-Switching circuit shown in Figure 2-46. Signal TYPEDET# is
used to determine the VDDQ voltage level (1.5V or 3.3V) for the AGP interface. When TYPEDET# is high, Q1 is always turned
on. The VDDQ output voltage is provided directly by the VCC3 (3.3V). When TYPEDET# is low, the VDDQ output voltage is
1.5V by regulating the VCC3 power source through the SC1105 switching regulator.
VCC3
+12V
6
3
TYPEDET#
(from pin A2 of AGP slot)
2
1
+12V
DH
4
CE1
.1uF
1500uF
VDDQ
4uH
NC
D1
BYV118
VCC
PGND
CB3
CE2
CE3
.1uF
1500uF
1500uF
7
VOSENSE
CGND
CB2
L1
TYPEDET#
CB4
.1uF
Q1
IR3103S
5
CGND
8
GND
SC1105
Figure 2-47. VDDQ Voltage-Switching Application Circuit
Figure 2-48 shows another application example for the VDDQ Voltage-Switching circuit. When TYPEDET# is low, Q1 is turned
off and a fixed 1.5V output is generated by the CS5257A-1GDP5 linear regulator (U1) to VDDQ. When TYPEDET# is high, Q1
is always turned on. The VDDQ output voltage is provided directly by the VCC3 (3.3V). At the same time, U1 is shut down due
to a higher output voltage (3.3V VDDQ > fixed 1.5V output).
VCC3
CE1
1000uF
VDDQ
Q1
8
D
7
D
6
D
5
D
VCC
+12V
1
S
2
S
3
S
4
G
R1
4.7K
Q2
3904
FDS4410
R2
4.7K
R3
1K
U1
-TYPEDET
04
(from pin A2 of AGP slot)
U2
5
VIN
VOUT
SENSE
3
VDDQ
1
R4
100 1%
VCC
4
CT1
10u/16V
CTRL
ADJ
CE2
CE3
1000uF
1000uF
2
CB1
CS5257A-1GDP5
.1uF
R5
20 1%
Figure 2-48. VDDQ Voltage-Switching Application Circuit (II)
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2.4.3.4 AGP VDDQ Power Plane Partition
By referring to the power plane partition examples in figures 2-15 to 2-16, the power plane for the AGP slot should be separated
from the remaining power planes on the motherboard. A VDDQ Island (selected area) will cover most of the AGP signal routing
area. The detailed VDDQ power plane partition is shown in Figure 2-49.
Figure 2-49. AGP VDDQ Power Plane Partition Example
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2.4.3.5 Optimized Layout and Routing Recommendations
It is strongly recommended to maintain the trace length of all AGP (especially Data and Strobe) signals less than 4 inches. It is
always best to reduce line mismatch to add to the timing margin. In other words, a balanced topology can match trace lengths
within the groups to minimize skew. To minimize signal crosstalk, wider spacing is recommended wherever possible between
traces. A layout example of the AGP interface between the VT82C694X and the AGP Slot is shown in Figure 2-50. Optimized
layout and routing recommendations are listed below:
•
•
•
•
•
•
Except strobe signals, traces for other AGP signals in Table 2-11 should be a minimum of 5 mils in width and 15 mils in
spacing. The trace width of these six strobe signals should be 5 mils. The spacing for each strobe signal should be a
minimum of 20 mils to other strobe signals and a minimum of 30 mils to non-strobe signals. Refer to Figure 2-51 for
more detail on layout.
The trace width of AGP clock signals (GCLKI and GCLKO) is at least 10 mils. The spacing for any AGP clock signal
should follow the spacing requirements of its adjacent (Data, Strobe or Control) signal to limit signal coupling.
The accumulated trace length for all signals in Table 2-11 should be less than 6 inches to limit signal coupling between
traces. Trace length mismatch in any Data/Strobe group should be maintained within 0.5 inch.
An impedance of 65 ohm ± 5 ohm is strongly recommended for AGP 4X. Otherwise, signal integrity requirements may
be violated.
Five extra decoupling capacitors is required for VDDQ power plane. These decoupling capacitors are mounted
right beneath the inner AGP quadrant of BGA area on the solder layer. The combination of these decoupling
capacitors is one 1uF in 1206 size, two 1uF capacitors in 0805 size, one 0.1uF capacitor in 0805 size and one 0.01uF
capacitor in 0805 size.
AGP signals GREQ#, GGNT#, GFRAME#, GTRDY#, GIRDY#, GDEVSEL#, GSTOP#, GSERR#, GPERR#, GPAR,
GRBF#, GPIPE#, GDS[1:0], SBS and GWBF# require discrete pull-up resistors (not R-packs) to be installed on the
motherboard. These signals must be pulled up to VDDQ using 8.2K~10K ohm pull-up resistors. It is recommended to
keep the stub length as short as possible. Similarly, AGP signals GDS0#, GDS1# and SBS# require discrete 8.2K~10K
ohm pull-down resistors to be installed on the motherboard.
(a) Component Side
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(b) Solder Side
Figure 2-50. AGP 4X Interface Layout Example
Notes:
1. Most Decoupling capacitors are placed on the left-hand side of the AGP slot in Figure 2-50 (a).
2. Discrete pull-up resistors are located very near their associated pins for the short stub limitation in Figure 2-50 (a).
3. Each Strobe signal is centered within its group to minimize the signal to strobe skew.
4. The serpentine bold trace near the VT82C694X chip represents the AGP clock feedback (GCLKI) signal in Figure 2-50 (b).
5. There are five SMD ceramic capacitors located in the inner AGP quadrant of BGA area in Figure 2-50 (b).
6. In order to prevent couplings from or to other signal groups (e.g. PCI), a surrounding ground plane is applied near the AGP
universal (2X or 4X) slot on either the component layer or the solder layer.
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2.4.4 PCI Interface Layout and Routing Guidelines
It is recommended that the VT82C694X and VT82C686A be placed at both ends of the PCI bus for better signal termination. A
topology example of the AGP and PCI buses on an ATX form factor is shown in Figure 2-51 below. PCI signal traces may be
placed on either the component layer or the solder layer. Most AGP signal traces should be placed on the component layer.
PCI1
PCI2
PCI3
PCI4
PCI5
VT82C694X
North Bridge
AGP
VT82C686A
South Bridge
Figure 2-51. Topology Example of AGP and PCI Interface
Each of the following signals IRDY#, TRDY#, DEVSEL#, STOP#, LOCK#, PERR#, SERR#, FRAME#, INTA#, INTB#, INTC#,
and INTD# for the PCI interface requires a 4.7K ohm pull-up to VCC5. The REQ# signals need 2.2K ohm pull-ups to VCC5. The
GNT# signals need 2.2K ohm pull-ups to VCC3.
The layout guidelines for PCI signals are listed below:
• Maintain 5 mil trace width and 10 mil clearance to its adjacent signals.
•
Route to minimum trace length wherever possible.
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2.5 Super South (VT82C686A) Layout and Routing Guidelines
2.5.1 USB controller
The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial interface for adding
external peripheral devices such as game controllers, communication devices, and input devices on a single bus. Brief descriptions
of the USB signals of the VT82C686A are listed in Table 2-12. The VT82C686A provides four USB ports. Only port 0 and port
1 have over-current detect pins (OC0# and OC3#), however, the over current status of port 2 and port 3 can still be sensed for
implementing 4 USB ports. The VT82C686A will scan SD[3:0] during the ISA refresh period as OC[3:0]# of the USB ports. If
this over-current scan logic is implemented, pins OC0# and OC1# may be left open or used for alternative functions. A schematic
drawing for four over-current scans is illustrated in Figure 2-52 below.
Table 2-12 Universal Serial Bus (USB) Signals
Signal Name
USBP0+
USBP0OC0#
USBP1+
USBP1OC1#
USBP2+
USBP2USBP3+
USBP3USBCLK
I/O
IO
IO
I
IO
IO
I
IO
IO
IO
IO
I
Description
USB Port 0 Data +
USB Port 0 Data USB Port 0 Over Current Detect. Port 2 is disabled if this input is low.
USB Port 1 Data +
USB Port 1 Data USB Port 1 Over Current Detect. Port 1 is disabled if this input is low.
USB Port 2 Data +
USB Port 2 Data USB Port 3 Data +
USB Port 3 Data USB clock. Connected to a 48MHz clock output of the system clock synthesizer.
U1
2
4
OC0#
OC1#
OC2#
OC3#
6
8
11
13
(From USB Ports)
15
17
1
RFSH#
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
18
16
14
12
SD0
SD1
SD2
SD3
SD[7..0]
(To VT82C686A)
9
7
5
3
VCC
19
(From VT82C686A)
74F244
Figure 2-52. USB Over-Current Scan Logic
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The layout guidelines for USB are listed below.
•
•
Each pair of USB data signals is required to be parallel to each other with the same trace length.
Each pair of USB data signals is required to be parallel to a respective ground plane.
A routing example of two pairs of USB data buses is shown in figure 2-53 below.
VT82C686A
Recommended
USB0
Connector
(South Bridge)
USBP0+
USBP0Not recommended
USBP1+
USB1
Connector
USBP1-
Figure 2-53. USB Differential Signal Routing Example
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2.5.2 AC’97 Link and Game/MIDI Ports
Table 2-13 shows a brief description of the signals of AC'97 Link Controller and Game Ports. All those signals are multi-function
pins with the second IDE channel bus. To enable both functions, the power up strapping of SPKR (pin V5 of the VT82C686A)
must be pulled up to VCC3 with a 4.7K~10K ohm resistor.
Table 2-13. Signal Description of AC'97 Link and Game/MIDI Ports
Signal Name
BITCLK (SDD0)
SDIN (SDD1)
SDIN2 (SDD2)
SYNC (SDD3)
SDOUT (SDD4)
ACRST (SDD5)
JBY (SDD6)
JBX (SDD7)
JAY (SDD8)
JAX (SDD9)
JAB2 (SDD10)
JAB1 (SDD11)
JBB2 (SDD12)
JBB1 (SDD13)
MSO (SDD14)
MSI (SDD15)
I/O
I
I
I
O
O
O
I
I
I
I
I
I
I
I
O
I
Description
AC'97 Bit Clock
AC'97 Serial Data In
AC'97 Serial Data In 2 (reserved)
AC'97 Sync
AC'97 Serial Data Out
AC'97 Reset
Game Port Joystick B Y-axis
Game Port Joystick B X-axis
Game Port Joystick A Y-axis
Game Port Joystick A X-axis
Game Port Joystick A Button 2
Game Port Joystick A Button 1
Game Port Joystick B Button 2
Game Port Joystick B Button 1
MIDI Serial Out
MIDI Serial In
2.5.2.1 AC'97 Link
An AC'97 Controller is integrated in the VT82C686A and currently supports only one Codec. One Primary Codec (ID 00) is
completely compatible with existing AC'97 definitions and extensions. The Codec ID functions as a chip set select. For more
details, refer to the AC'97 Component Specification Revision 2.1.
AC-link is a digital serial link between the AC'97 Controller and AC'97 devices. AC-link signals are multi-function pins with the
Second IDE channel bus (SDD[0..5]). A linking example between the AC'97 Controller and one AC'97 Codec is shown in figure
2-54. A complete schematic for implementing the VIA VT1611A AC'97 Audio Codec is shown in Appendix B.
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VT1611A
VT82C686A
(Audio Codec)
(South Bridge)
22 ohm
BITCLK
SDIN
SDIN2
BITCLK
SDATA_IN
10K
ohm
10K ohm
22 ohm
ACRST#
SYNC
SDOUT
RESET#
SYNC
SDATA_OUT
AC'97 Codec
AC'97 CONTROLLER
Figure 2-54. AC'97 Link Example
2.5.2.2 Game/MIDI ports
The VT82C686A supports two direct game ports (Joystick A and Joystick B) and one MIDI port interface. An application circuit
of MIDI/Game port is shown in Figure 2-55. It is recommended to place all these RC components near the D-SUB connector.
VCC
MIDI/Game Port
VCC
VT82C686A
Ferrite Bead
RP
4.7K ohm
(South Bridge)
1
D-SUB
8
9
(15-pin, 2-row)
15
12
MSI
MSO
2
3
JAB1
JAX
JAY
JAB2
6
7
RD
2K ohm
JBB1
JBX
JBY
JBB2
10
11
13
14
Connector
MIDI Serial
Input/Output
Game Port
Joystick A
Game Port
Joystick B
4
CP
1000pF
MIDI/Game Port Controller
CP
0.02uF
5
Ferrite Bead
Figure 2-55. MIDI/Game Port Application Circuit
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2.5.3 Hardware Monitoring
The hardware monitoring interface includes five positive voltage sensing inputs (four external and one internal), three temperature
sensing inputs (two external and one internal), two fan-speed monitoring inputs and one chassis intrusion detection input.
Programmable control, status, monitor and alarm are supported by the VT82C686A for flexible desktop management. The
following sections provide detailed descriptions for each hardware monitor subsystem. An application circuit for hardware
monitoring is shown in Figure 2.56. In order to achieve a stable VCC3 input to the Hardware Monitoring Subsystem, a 0.1uF
decoupling capacitor should be placed as close to the Hardware Monitoring power and ground pins as possible.
VCC2
VCCI
+5V
+12V
16K
ohm
VT82C686A
(South Bridge)
53K
ohm
10K
ohm
VSENS
VSENS
VSENS
VSENS
VCC3
VCC3
10K
ohm
10K
ohm
4.7K
ohm
4.7K
ohm
+12V
CHASSIS
FAN
Mechanical Switch
FAN1
FAN
FAN2
VCC3
VCCHWM
Ferrite Bead
GNDHWM
0.1uF
10uF
GNDHWM
Ferrite Bead
TSEN1
VREF
TSEN2
10K ohm 1%
10K ohm
Thermister
Ferrite Bead
10K ohm
Thermister
Ferrite Bead
10K ohm 1%
Figure 2-56. Hardware Monitoring Application Circuit
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Voltage Monitoring
Typically VCC2 (core voltage of the CPU), VCCI (2.5V, core voltage of the VT82C694X), VCC3 (3.3V), 5V, and +12V are the
five monitored voltage inputs. VCC2 and VCCI can be directly connected to the inputs. The +5V and 12V inputs should be
attenuated with external resistors to any desired value within the input range. VCC3 is internally connected to the hardware
monitoring system voltage detection circuitry for 3.3V monitoring. An alarm will issue when any monitored voltage level is out of
range. Layout and grounding guidelines are listed below:
•
•
These voltage inputs will provide better accuracy when referred to their respective ground (GNDHWM) which is
separated from digital common ground (GND). Please refer to the application circuit above.
Voltage dividers should be located physically as close to the voltage input pins as possible.
Temperature Sensing
One internal thermal sensor is located inside the VT82C686A chip. Two external thermisters for two temperature sensing inputs
are used to directly contact the device whose temperature will be monitored. Layout and grounding guidelines are listed below:
•
•
The thermister should be placed very near a measured object. For example, a thermister can be placed right beside of a
Slot-1 CPU or under a Socket-370 CPU.
The other end of a thermister should be connected to ground through a ferrite bead.
Fan-Speed Monitoring
Fan speed inputs are provided for signals from fans equipped with tachometer outputs. One fan-speed-monitoring pin can be used
to measure the CPU fan speed. The other can be an auxiliary one. A programmable fan-speed control can be implemented in the
following three steps.
•
•
•
Speed Monitoring: The fan speed value is measured by a fan-speed monitoring pin
Temperature Sensing: The temperature value is measured by a temperature sensing pin
Speed Controlling: The fan speed is controlled by a dedicated General Purpose Output (GPO) pin
Chassis Intrusion Detection
The detection is an active high interrupt from any chassis intrusion violation. It could be accomplished mechanically, optically, or
electrically. Circuitry external to the chassis intrusion detect pin is expected to latch the event.
2.5.4 Integrated Super IO Controller
In the VT82C686A, an integrated Super IO Controller supports two UARTs for complete serial ports, one dedicated IR port, one
multi-mode parallel port, and one floppy drive controller function. Refer to the Apollo Pro-133 Reference Design Schematics in
Appendix C for more details on application circuits.
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2.5.5 System Management Bus Interface
The I2C bus signal pair of the VT82C686A will handle all I2C buses to other on-board devices such as the Clock Synthesizer and
the three DIMM slots. A block diagram of System Management Bus Interfaces is shown in Figure 2-57. It is recommended to
place both pull-ups at the end of the I2C bus.
•
Adding 68pF capacitors in Figure 2-57 for the pair at the end device is essential since the I2C bus travels a long way and
might pick up noise along the route.
VCC3
VT82C686A
(South Bridge)
2.2K
ohm
2.2K
ohm
68 pF
68 pF
SMBCLK
SMBDATA
Clock
Synthesizer
DRAM
DIMMs
TV
Encoder
TV
Decoder
The end
Device
Figure 2-57. System Management Bus Interface
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2.5.6 IDE
Both Primary and secondary IDE channels have their own control signals. The Primary IDE channel has a dedicated data bus.
However, the secondary IDE data bus is multiplexed with an Audio/Game port or it can share ISA address bus SA[15:0] as
SDD[15:0]. The two options are listed below for selecting the secondary IDE data bus.
•
•
Option 1: The secondary IDE data bus uses its own bus SDD[15:0] sharing with an Audio/Game port when the SPKR pin
is strapped low. No Audio/Game port is supported in this case since these functions are shared with the SDD[15..0] pins.
Option 2: The secondary IDE data bus shares ISA address bus SA[15:0] as SDD[15:0] through two 74F245 transceivers
when the SPKR pin is strapped high. The sharing circuitry is shown in Figure 2-58. Audio/Game port functions are
enabled on the SDD[15:0] pins.
U1
SDD[15..0]
(From VT82C686A
& to Secondary IDE)
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
2
3
4
5
6
7
8
9
19
-SOE
1
(From VT82C686A)
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA[15..0]
(To ISA slots)
OE#
DIR
74F245
U2
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
2
3
4
5
6
7
8
9
19
1
-MASTER
(From VT82C686A)
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
OE#
DIR
74F245
Note: These 74F245 Transceivers are optional if ISA bus load is not a concern.
Figure 2-58. ISA Bus SA[15:0] / SDD[15:0] Sharing Circuitry
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Dual channel master mode PCI supports four Enhanced IDE devices. The transfer rate for each device can support up 33 MB/sec
to cover PIO mode 4, multi-word DMA mode 2 drives, and UltraDMA-33 interface. Transmission line effects and signal crosstalk
emerge in the IDE related signals. To eliminate ringing and reflection caused by the transmission line effect, trace length and
impedance match must be taken into account. An example IDE layout is shown in Figure 2-59. Recommended layout rules for
both primary and second IDE ports are listed below:
•
•
•
•
•
•
•
•
The trace attribute of all primary IDE signals is in a minimum of 6 mils wide and 9 mils between two adjacent traces. The
recommended trace length is less than 6 inches.
All ATA signals in Figure 2-59 require series termination resistors. The series resistors (RA) should be placed within 1
inch of the VT82C686A chip. The series resistors (RB) should be placed within 1 inch of the primary IDE connector.
Signal DD7 needs a 10K pull-down on the VT82C686A chip side of series termination
Signal DREQ needs a 5.6K pull-down on the connector side of the series termination
Signal IRQ14 (or IRQ15) needs a 10K pull-down or pull-up (preferred) on the connector side of the series termination
Signal IORDY# needs a 1K pull-up on the connector side of the series termination
Pin 28 of the IDE connectors should be tied to ground with a 470 ohm serial resistor.
It is recommended to layout the following signals to each IDE connector in equal length. They are signals DD[15..0],
IOR#, IOW#, and IORDY#.
Primary
IDE
Connector
VT82C686A
(South Bridge)
F04
RA
Trace length (L1) < 6"
33 ohm
L1
RSTDRV
1
PDIOW#
23
IOW#
PDIOR#
25
IOR#
PDDACK#
29
DACK#
PDCS1#
33
CS1#
PDCS3#
38
CS3#
IDERST#
DA[2..0]
PDA[2..0]
DD[15..0]
DD[15..0]
10K ohm
(note 1)
RB
Trace length (L2) < 6"
82 ohm
L2
VCC
10K ohm
IRQ14
31
IRQ14
27
IORDY#
21
DREQ
28
SPSYNC:CSEL
VCC
1K ohm
PIORDY#
PDDREQ
5.6K ohm
470 ohm
Note 1: 10K ohm resistor pull-down for DD7 only
Figure 2-59. IDE Interfaces Layout Guidelines
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Ultra DMA/66 Interface Layout Guidelines
VT82C686A supports Ultra DMA/66 IDE interfaces on both Primary IDE channel (IDE1) and Secondary IDE channel (IDE2). A
Micro-ATX component placement example for implementing the Ultra DMA/66 interface (option 2) is shown in Figure 2-60. The
detailed placement for the VT82C686A chip and two IDE connectors is illustrated in the lower left corner of the figure. The major
difference from the former placement is the shorter distance between VT82C686A and primary IDE and Secondary IDE
connectors. The shorter length for both IDE data buses is required because this bus is running at a high speed (66MHz). In order
to fulfill this requirement, the VT82C686A chip can be lowered and both IDE connectors can be shifted to the left. Recommended
layout guidelines are listed below.
AN
A
1
37
Back
Panel
VT82C
694X
VT82C
686A
Socket 370
For IDE1
2
4
5
IDE1
IDE2
FDC
CLK
GEN.
2
4
5
For IDE2 data bus
Figure 2-60. Ultra DMA/66 Placement and Routing Example
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The application circuit of the ultra DMA/66 IDE interface is shown in Figure 2-61. The 80-conductor cable, required by the ultra
DMA/66 IDE interface, is the major difference from the 40-conductor cable of the current IDE interface. For the detection of the
80-conductor cable, pin 34 (CBLID) of IDE connector may be used to provide a signal state from an ultra DMA/66 device to a
GPI pin of the South Bridge Controller. The detection can be done in an alternative hardware solution too.
Layout rules for the IDE interface in the former section can be adapted for ultra DMA/66 use unless some of them are modified in
the following layout guidelines.
•
•
•
The trace attribute of all primary IDE signals is in a minimum of 6 mils wide and 9 mils between two adjacent traces.
All signals for primary IDE and Secondary IDE require 33 ohm series termination resistors.
terminations as close (less than 1 inch) to the VT82C686A as possible.
Place these series
Data and strobe lines should be routed as a bus. The total trace length of these signals should be shorter than 4.5 inches.
The maximum trace length difference among them must be less than 1 inch. Other lines should be as short as possible.
Primary
IDE
Connector
VT82C686A
(South Bridge)
F04
RA
Trace length (L1) < 3.5"
33 ohm
L1
RSTDRV
1
PDIOW#
23
IOW#
PDIOR#
25
IOR#
PDDACK#
29
DACK#
PDCS1#
33
CS1#
PDCS3#
38
CS3#
PDA[2..0]
IDERST#
DA[2..0]
DD[15..0]
DD[15..0]
10K ohm
(note 1)
Trace length (L2) < 3.5"
RB
33 ohm
L2
VCC
10K ohm
IRQ14
31
IRQ14
27
IORDY#
34
PDIAG#
21
DREQ
28
SPSYNC:CSEL
VCC
1K ohm
PIORDY#
VCC
10K ohm
GPI
(note 2)
PDDREQ
5.6K ohm
470 ohm
Notes
1. 10K ohm resistor pull-down for DD7 only.
2. Pin 34 of primary IDE connector is connected to one of GPI pins from VT82C686A.
Figure 2-61. Ultra DMA/66 Application Circuit
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2.5.7 Suspend to DRM
Power-on-suspend (POS), Suspend-to-RAM (STR) and Suspend-to-Disk (STD) or so called Soft-off are three different suspend
states supported by the VT82C686A. These suspend functions are implemented not only in a notebook PC design but also in a
desktop PC design. And the STR function is specially described in this section.
2.5.7.1 Suspend DRAM Refresh
During STR state, power is removed from most of the system except the system DRAM and the power management section of
VT82C686A. Power is supplied to the suspend refresh logic of the VT82C694X (VSUS) and the suspend logic of the
VT82C686A (VCCSUS). One additional suspend status indicator (SUSST1#) is provided to inform the north bridge and the rest
of the system of the processor and system suspend states. SUSST1# is asserted to tell the north bridge to switch to “Suspend
DRAM Refresh” mode. SUSST1# is asserted when the system enters the suspend state or the processor enters the suspend (C3)
state. SUSST1# is connected to the north bridge to switch between normal and suspend-DRAM-refresh modes The Suspend
DRAM Refresh application circuit is shown in Figure 2-62.
V_DIMM
VT82C694X
(North Bridge)
Main Memory
CKE0/FENA
CKE1/GCKE#
AC22
AF23
128
63
115
111
DIMM1
(Group A)
27
48
CKE2/CSB6#
CKE3/CSB7#
SRASA#
SCASA#
SWEA#
CKE4/CSA6#
CKE5/CSA#
SRASB#
SCASB#
SWEB#
AE24
AD23
128
63
AF164
AF12
115
111
AE12
27
48
AC23
AF24
128
63
AA17
AB13
115
111
AC12
27
48
3V3SB
VSUS
SUSSAT#
3V3SB
AD4
DIMM2
(Group A)
V_DIMM
DIMM3
(Group B)
V_DIMM
3V3SB
VT82C686A
(South Bridge)
10K
ohm
AC4
V_DIMM
T17
SUSST1
VCCSUS
VCCSUS
R16
L16
Notes:
1. During STR state, all VT82C694X and VT82C686A signals are powered by 3.3V suspend power.
2. Main memory is also powered by 3.3V suspend power through V_DIMM.
Figure 2-62. Suspend DRAM Refresh Application Circuit
Suspend DRAM refresh state (self refresh mode for DRAM modules) is entered by having CKE[0:5], SRAS[A:B}#, SCAS[A:B]#
held low with SW[A:B]# high at the rising edge of the SDRAM clock.
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2.5.7.2 STR Power Plane Control
VT82C686A controls the system entering the various suspend states through the suspend control signals listed in Table 2-14.
Three power plane control signals (SUSA#, SUSB# and SUSC#) are provided to turn off more system power planes as the system
moves to deeper power-down states from normal operation to POS (only SUSA# asserted), to STR (both SUSA# and SUSB#
asserted), and to STD (all three SUS# signals asserted).
Table 2-14. Resume Events Supported in Different Power States
Power State
On
POS
STR
STD / Soft-off
Mechanical off
RSMRST#
1
1
1
1
0
SUSST1#
0
0
0
0
0
SUSA#
1
0
0
0
0
SUSB#
1
1
0
0
0
SUSC#
1
1
1
0
0
Upon initiation of suspend, VT82C686A will assert the SUSST1# and SUS[A:C]# signals in a plane defined sequence to switch
the system into the desired power state. The SUSA#, SUSB# and SUSC# signals can be used to control various power planes in
the system. For example, SUSC# is typically connected to PS-ON (pin 14) of the ATX power supply connector through an
inverter to control the remote-off function.
Figure 2-63 shows an application circuit example on STR power plane control. When SUSB# is not asserted, Q1 is turned on and
Q2 is turned off. And V_DIMM power source is supplied by VCC3 in normal operation. When SUSB# is asserted, Q1 is turned
off and Q2 is turned on. And V_DIMM power source is supplied by 3V3SB (3.3V suspend power) during STR state.
+12V
-RSMRST
PW_GOOD
1
U1A
1
3
2
R2
4.7K
3
2
AHC08
AHC00
3V3SB
U2A
D
U4
P
D
Q2 G
NDC632P
P-MOSFET
Q
Q3
S
R1 1K
Q
C
AHCT74
MMBT3904
G
-SUSB
-SUSC
4
5
U1B
6
AHC00
1
2
U3A
VCC3
3
Q1 S
FDS6670A
N-MOSFET
D
V_DIMM
AHC32
Notes:
1. Components U1, U2, U3 and U4 are powered by +5V standby power source.
2. V_DIMM represents the power source to DIMM modules.
3. RDS(ON) of Q1 (N-channel MOSFET) should be as low as possible. RDS(ON)= 0.008 ohm at VGS=10V for FDS6670A.
Figure 2-63. STR State Power Plane Control Application Circuit
Note that these signals are associated with a particular type of suspend mode and power plane for descriptive purposes in this
section. Using these signals, the system designer can control any type of function desired.
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TIMING ANALYSIS AND SIMULATION
The 133 MHz timing analysis here will provide a basis for the concept of trace length limitation for some high speed buses and
control signals such as the CPU address bus (A[31:3]). A brief analysis is given for each diagram. 133 MHz system frequency is
assumed where one clock (1T) represents 7.5 ns. Reasons for the limited lengths of some signals (referring to Section 2.3) are
described in the timing analyses.
3.1 SDRAM Timing
Timing diagrams for CPU Read from SDRAM and CPU Post Write to SDRAM are illustrated in Figures 3-1 and 3-2. Timing
analyses for SDRAM read and write cycles are listed below:
•
•
The clock skew between the CPU clock and the SDRAM clocks will affect the setup time and hold time of SDRAM
command signals and MD[63..0] because the CPU reads or writes the data out of or into the SDRAM. Therefore, clock
alignment between the CPU clock and the SDRAM clocks should be maintained.
According to the cycles below, the timing is critical. In order to increase the timing margin of the cycle, one of the best
solutions is to minimize the propagation delay of the MD[63..0] and SDRAM control signals on the PCB. Therefore, the
length of MD[63..0] and the SDRAM control signals should be limited because there is only one clock between assertion
of the SDRAM control signals and data input or output.
CCLK
ADS#
HREQ#
HA#
RS#
DBSY#
DRDY#
HTRDY#
HD
CS#
SRAS#
SCAS#
SWE#
MD#
cccccccccccccccccccccccccccccccccccc
hhfrhfrhfrhhhhhhhhhhhhhhhhhhhhhhhhhh
zznxonxonxozzzzzzzzzzzzzzzzzzzzzzzzz
zzzzzzzzzznozznozznozzzzzzzzzzzzzzzz
hhhhhhhhhhfllrfllrfllrhhhhhhhhhhhhhh
hhhhhhhhhhflllllllllllrhhhhhhhhhhhhh
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
zzzzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzz
hhhhfrfrhhfrhhfrhhhhhhhhhhhhhhhhhhhh
hhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
hhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhhhhh
hhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh
zzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzzz
Consideration:
A: Be careful of the MD data length
B: Be careful of the CPU data length
C: Be careful of the CPU address length
D: Be careful of the CPU control signal length
Figure 3-1. CPU Read from SDRAM (SL=2)
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CCLK
ADS#
HREQ#
HA#
RS#
DBSY#
DRDY#
HTRDY#
HD
CS#
SRAS#
SCAS#
SWE#
DQM#
MD#
cccccccccccccccccccccccccccccccccccc
hhfrhfrhfrhhhhhhhhhhhhhhhhhhhhhhhhhh
zzzzzzzznozznozznozzzzzzzzzzzzzzzzzz
hhhhhhhfllrfllrfllrhhhhhhhhhhhhhhhhh
hhhhhhhflllllllllllrhhhhhhhhhhhhhhhh
hhhhhflrflrflrhhhhhhhhhhhhhhhhhhhhhh
zzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzzzz
hhhhhhhfrfrhhfrhhfrhhhhhhhhhhhhhhhhh
hhhhhhhfrhhhhhhhhhhhhhhhhhhhhhhhhhhh
hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh
hhhhhhhhhfrhhfrhhfrhhhhhhhhhhhhhhhhh
hhhhhhhhhflllllllllllrhhhhhhhhhhhhhh
zzzzzzzzznxxxxxxxxxxxozzzzzzzzzzzzzz
Consideration:
A: Be careful of the MD data length
B: Be careful of the CPU data length
C: Be careful of the CPU address length
D: Be careful of the CPU control signal length
Figure 3-2. CPU Post Write to SDRAM (SL=2)
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ELECTRICAL SPECIFICATIONS
This section describes the electrical specifications of the VT82C694X.
4.1 Absolute Maximum Ratings
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation is not implied
under the ratings listed in Table 4-1.
Table 4-1. Absolute Maximum Ratings
Symbol
TA
TS
VIN
VOUT
Parameter
Ambient Operating Temperature
Storage Temperature
Input Voltage
Output Voltage
Min
0
-55
-0.5
-0.5
Max
70
125
VRAIL + 10%
VRAIL + 10%
Unit
0
C
0
C
Volts
Volts
Notes
1
1
1,2
1,2
Notes:
1. Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be
restricted to the conditions described under operating conditions.
2. VRAIL is defined as the VCC level of the respective rail. The CPU interface can be 3.3V or 1.5V. The Memory interfaces must be
3.3V only. The PCI and AGP interfaces can be 3.3V or 5.0V.
4.2 Recommended Operating Ranges
Functional operation of the VT82C694X is guaranteed if the values of voltage and temperature are within the limits defined in
Table 4-2.
Table 4-2. Recommended Operating Ranges
Symbol
TA
VTT
VCC3
VCC5
Parameter
Ambient Operating Temperature
1.5V Power (GTL bus)
3.3V Power to (IO Buffer)
+5V Power
Min
0 0C
1.425 V
3.135 V
4.75 V
75
Max
70 0C
1.575 V
3.465 V
5.25 V
Notes
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4.3 DC Characteristics
DC characteristics of the VT82C694X are shown in Table 4-3.
Table 4-3. DC Characteristics
Symbol
VIL
VIH
VOL
VOH
IIL
IOZ
ICC1_5
ICC3
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Tristate Leakage Current
Power Supply Current (GTL)
Power Supply Current
Min
-0.5
+2.0
2.4
-
Max
+0.8
VCC+0.5
0.45
+/-10
+/-20
Unit
V
V
V
V
uA
uA
mA
mA
Condition
Note 1
IOL = 4.0 mA
IOH = 1.0 mA
0 < VIN < VCC
0.45 < VOUT < VCC
Note 2
Note 3
Notes:
1. VCC refers to the voltage being applied to VCC during functional operation.
2. VTT = 1.5 V - The maximum power supply current must be taken into account when designing a power supply.
3. VCC3 = 3.3 V - The maximum power supply current must be taken into account when designing a power supply.
4.4 Power Dissipation
Table 4-4 contains the maximum power dissipation of the VT82C694X during different system frequencies.
Table 4-4. Maximum Power Dissipation
Supply Voltage
1.5V
66MHz
W
(VTT = mA)
3.3V
W
(VCC3 = mA)
Total power consumption W
100MHz
W
(VTT = mA)
W
(VCC3 = mA)
W
76
133MHz
W
(VTT = mA)
W
(VCC3 = mA)
W
Conditions
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SIGNAL CONNECTIVITY AND DESIGN CHECKLIST
5.1 Overview
The Apollo Pro133A North Bridge, and VT82C686A South Bridge are the two major components in a VIA Apollo Pro133A based
PC system. Two signal connectivity tables for both North Bridge and South Bridge and a design checklist are given in the
following sections. Pin connections may vary in different circuit designs. Some pins have been repeatedly described for different
functions in different sub-tables.
The signal connectivity table provides board designers a quick reference of signal connections. And it can be used to review
schematics of an Apollo Pro133A system. The design checklist can provide a quick way to review the PCB layout of an Apollo
Pro133A system.
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Signal Connectivity and Design Checklist
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5.2 VT82C694X Apollo Pro133A North Bridge
The connectivity for each signal of the VT82C694X North Bridge is listed in Table 5-1. Motherboard designers can use this table
as a quick reference to review their schematics.
Table 5-1. VT82C694X North Bridge Connectivity
CPU INTERFACE
Signal Name
ADS#
BNR#
BPRI#
BREQ0#
CPURST#
DBSY#
DEFER#
DRDY#
HA[31:3]#
HD[63:0]#
HIT#
HITM#
HLOCK#
HREQ[4:0]#
HTRDY#
RS[2:0]#
I/O
IO (GTL+)
IO (GTL+)
IO (GTL+)
O (GTL+)
O (GTL+)
IO (GTL+)
IO (GTL+)
IO (GTL+)
IO (GTL+)
IO (GTL+)
IO (GTL+)
I (GTL+)
I (GTL+)
IO (GTL+)
IO (GTL+)
IO (GTL+)
Signal Name
MAA[14:0]
MAB[13:11]#, MAB10,
MAB[9:0]#
MD[63:0]
MECC[7:0]
RASA[5:0]# / CSA[5:0]#
RASB[5:0]# / CSB[5:0]#
CASA[7:0]# / DQMA[7:0]#
CASB5# / DQMB5#
CASB1# / DQMB1#
SRASA#
SCASA#
SWEA# / MWEA#
SRASB#
SCASB#
SWEB# / MWEB#
CKE[5:4] / CSA[7:6]#
CKE[3:2] / CSB[7:6]#
CKE1 / GCKE#
CKE0 / FENA
Connection
Connect to Slot-1 CPU. Or connected to Socket-370 CPU with 56 ohm termination to VTT.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
DRAM INTERFACE
I/O
Connection
O Connect to DIMM1 and DIMM2.
O Connect to DIMM3 for 3-DIMM case. Or connect to DIMM3 and DIMM4 for 4-DIMM
case.
IO Connect to each DIMM.
IO Same as the above.
O Connect to DIMM1, DIMM2 and DIMM3. (two to each)
O Same as the above.
O Connect to each DIMM.
case.
O Connect to DIMM1 and DIMM2.
case.
O CKE[5:4] connected to DIMM3 for 3-DIMM case. CSA[7:6]# connected to DIMM4 for 4DIMM case.
O CKE[3:2] connected to DIMM2 for 3-DIMM case. CSB[7:6]# connected to DIMM4 for 4DIMM case.
O CKE1 connected to DIMM1 for 3-DIMM case.
O CKE0 connected to DIMM1 for 3-DIMM case.
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PCI BUS INTERFACE
Signal Name
CBE[3:0]#
AD[31:0]
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
SERR#
LOCK#
PAR
PREQ#
PGNT#
REQ[4:0]#
GNT[4:0]#
WSC#
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
O
I
O
O
Signal Name
GBE[3:0]#
GD[31:0]
SBA[7:0]
ST[2:0]
GFRM#
GIRDY#
GTRDY#
GSTOP#
GDSEL#
GDS0
GDS1
SBS
GPIPE#
GRBF#
GREQ#
GGNT#
GGNT#
GWBF#
GDS0#
GDS1#
SBS#
NCOMP
PCOMP
GPAR / GCKRUN#
I/O
IO
IO
I
O
IO
IO
IO
IO
IO
IO
IO
I
I
I
I
O
O
I
IO
IO
I
I
I
IO/O
Connection
Connect to VT82C686A and PCI slots.
Same as the above.
Connect between VT82C694X, PCI slots, and VT82C686A. 2.7K ohm pull-up to VCC5.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connect between VT82C694X and PCI slots. 2.7K ohm pull-up to VCC5.
Connect to VT82C686A and PCI slots.
Connect to VT82C686A. 10K ohm pull-up to VCC3.
Connect to corresponding PCI slots. 2.7K ohm pull-up to VCC5.
Connect to corresponding PCI slots. 2.7K ohm pull-up to VCC3.
No connect.
AGP BUS INTERFACE
Connection
Connect to AGP slot.
Same as the above.
Same as the above.
Same as the above.
Connect to AGP slot. 8.2K ohm pull-up to VDDQ.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connect to AGP slot. 8.2K ohm pull-down to ground.
Same as the above.
Same as the above.
Connected to VDDQ through a 60 ohm resistor.
Connected to ground through a 60 ohm resistor.
Connect to AGP slot. Then connected to ground through a 100K ohm serial resistor.
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Signal Name
HCLK
DCLKO
DCLKWR
GCLKO
GCLK
PCLK
RESET#
PWROK
GCKRUN# / GPAR
SUSCLK
SUSTAT#
CPURSTI#
CLKRUN#
I/O
I
O
I
O
I
I
I
I
O/IO
I
I
I
I
CLOCK AND RESET CONTROL
Connection
Connect to the CPU clock output of the system clock synthesizer.
Connect to the SDRAM clock input of the system clock synthesizer.
Connect to the SDRAM clock output of the system clock synthesizer.
Connected to the AGP clock input of the AGP slot through a 22 ohm resistor.
Connected to the GCLKO of VT82C694X through a 22 ohm resistor.
Connect to the PCI clock output of the system clock synthesizer.
Connected to VT82C686A through a 74F240 inverter.
Connect to VT82C686A and Power Good circuitry.
Connected to VT82C686A and the system clock synthesizer if the function is applied.
Connect to the MUX circuitry of the CPU strapping signals. 10K ohm pull-up to VCC3.
Connected to VT82C686A and the system clock synthesizer if the function is applied.
Otherwise, connect to VT82C686A then through a 100 ohm serial resistor to ground.
MISCELLANEOUS
Signal Name
VCC
GND
VCCA
GNDA
VSUS
VCCQ
VCCQQ
GNDQQ
VTT
GTLREF
AGPREF
TESTIN#
I/O
P
P
P
P
P
P
P
P
P
P
P
I
Connection
Connect to VCC3.
Connect to ground.
Connect to VCC3.
Connect to ground.
Connect to 3.3V standby power source.
Connect to VDDQ (1.5V or 3.3V).
Connect to VDDQ (1.5V or 3.3V).
Connect to ground.
Connect to GTL threshold voltage (1.5V).
Connect to GTL Buffer reference voltage (1.0V) circuitry.
Connect to AGP reference voltage (1.32V) circuitry.
8.2K ohm pull-up to VCC3.
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5.3 "Super South" South Bridge Controller
The connectivity for each signal of VT82C686A South Bridge is listed in Table 5-2. Motherboard designers can use this table as a
quick reference to review their schematics. Some pins have been repeatedly described for different functions in different subtables, please be careful in using the following table.
Table 5-2. VT82C686A South Bridge Connectivity
Signal Name
PCLK
AD[31:0]
C/BE[3..0]#
FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
SERR#
PAR
IDSEL
PIRQ[D:A]#
I/O
I
IO
IO
IO
IO
IO
IO
IO
I
IO
I
I
PREQ#
PGNT#
PCKRUN#
O
I
IO
Signal Name
A20M#
CPURST
IGNNE#
INIT
INTR
NMI
SMI#
STPCLK#
FERR#
SLP#/GPO7
I/O
OD
OD
OD
OD
OD
OD
OD
OD
I
OD
PCI BUS INTERFACE
Connection
Connect to the PCI clock output of an external Clock Synthesizer.
Connect to VT82C694X and PCI slots.
Connect between VT82C694X, PCI slots, and VT82C686A. 10K ohm pull-up to VCC.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connect to AD18 with a series 100 ohm resistor.
Connect to pins INT[D..A]# of each PCI slot as follows:
PIRQA#
PIRQB#
PIRQC# PIRQD#
PCI slot 1
INTA#
INTB#
INTC#
INTD#
PCI slot 2
INTB#
INTC#
INTD#
INTA#
PCI slot 3
INTC#
INTD#
INTA#
INTB#
PCI slot 4
INTD#
INTA#
INTB#
INTC#
Connect one of these pins to pin INTA# of VT82C694X.
Connect to VT82C694X.
Connect to VT82C694X.
Connect to ground with a series 100 ohm resistor if the function is not applied.
CPU INTERFACE
Connection
Connect to CPU. 4.7K ohm pull-up to VCC3.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connect to Slot-1 CPU only if the function is applied. 4.7K ohm pull-up to VCC3.
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Signal Name
SA[19:16]
SA[15:0]/SDD[15:0]
LA[23:20]
SD[15:0]
SBHE#
IOR#
IOW#
MEMR#
MEMW#
SMEMR#
SMEMW
BALE
IOCS16#
MCS16#
IOCHCK#/GPI0
IOCHRDY
RFSH#
AEN
IRQ1/MSCK
IRQ[5:3]
IRQ6/
GPI4/
SLPBTN#
IRQ7
IRQ8#/GPI1
IRQ[11:9]
IRQ12/MSDT
IRQ[15:14]
DRQ[1:0]
DRQ2/
SERIRQ/
GPIOE/
OC1#
DRQ3
DRQ[7:5]
DACK[1:0]#
DACK2#/
GPIOF/
OC0#
DACK3#
DACK[7:5]#
TC
SPKR
ISA BUS INTERFACE
I/O
Connection
IO Connect to ISA slots and BIOS ROM. 4.7K ohm pull-up to VCC. Connect SA[19:17] also
to LA{19:17}.
IO Connect to ISA slots and BIOS ROM. 4.7K ohm pull-up to VCC. And connected to
secondary IDE connector through two 74F245 ICs.
IO Connect to ISA slots. 4.7K ohm pull-up to VCC.
IO Connect to ISA slots and a 74F245 transceiver. 4.7K ohm pull-up to VCC.
IO Connect to ISA slots. 4.7K ohm pull-up to VCC.
O Connect to ISA slots.
I Connect to ISA slots. 330 ohm pull-up to VCC.
I Connect to ISA slots. 330 ohm pull-up to VCC.
I Connect to ISA slots. 4.7K ohm pull-up to VCC.
I Connect to ISA slots. 4.7K ohm pull-up to VCC.
IO Connect to ISA slots. 330 ohm pull-up to VCC.
I/IO No connect.
I Connect to ISA slots. 4.7K ohm pull-up to VCC and 68pF capacitor to ground.
I
I
I No connect.
I/IO No connect.
I Connect to ISA slots and IDE connectors. 4.7K ohm pull-up to VCC and 68pF capacitor to
ground. Both passive components should be placed near the slots.
I Connect to ISA slots. 5.6K ohm pull-down.
I
IO
I
I Connect to ISA slots.
IO
I
O Connect to ISA slots. 68pF capacitor to ground
O Connected to speaker circuitry or AC'97 CODEC through a series 100 ohm resistor. 4.7K
ohm pull-up to VCC3 for assigning SDD bus to Audio/Game or 4.7K ohm pull-down for
unchanging SDD bus function.
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USBCLK
USB INTERFACE
I/O
Connection
IO Connect to USB(0) connector. 47pF capacitor to ground with 27 ohm resistor, and then
15K ohm resistor to ground. These passive components should be placed as close to
VT82C686A as possible
I Connect to the corresponding USB(0) over-current detection voltage divider.
I
IO
I Connect to the corresponding USB(1) over-current detection voltage divider.
I
IO
I
I Connect to a 48MHz clock output of the system clock synthesizer.
Signal Name
SMBCLK,
SMBDATA
SMBALRT/GPI6
SYSTEM MANAGEMENT BUS INTERFACE
I/O
Connection
IO Connect to all devices on SMBus (I2C bus) except for the VGA port. 2.2K ohm pull-up to
VCC3. This resistor value is varied based on the bus loading.
I 10K ohm pull-up to 3VSB (3.3V stand-by power source).
Signal Name
USBP0+,
USBP0OC0#/
DACK2#/
GPIOF
USBP1+,
USBP1OC1#/
DRQ2/
GPIOF/
SERIRQ
USBP2+,
USBP2USBP3+,
USBP3-
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Signal Name
PDIOR#
PDIOW#
PDDACK#
PDCS1#
PDCS3#
PDA[2:0]
PDDRQ
PDRDY#
DD[15:0]
/PDD[15:0]
SDIOR#
SDIOW#
SDDACK#
SDCS1#
SDCS3#
SDA[2:0]
SDDRQ
SDRDY#
SDD15/MSI
SDD14/MSO
SDD13/JBB1
SDD12/JBB2
SDD11/JAB1
SDD10/JAB2
SDD9/JAX
SDD8/JAY
SDD7/JBX
SDD6/JBY
SDD5/ACRST
SDD4/SDOUT
SDD3/SYNC
SDD2/SDIN2
SDD1/SDIN
SDD0/BITCLK
ULTRA DMA-66 ENHANCED IDE INTERFACE
Connection
Connected to primary IDE connector through a 33 ohm series resistor.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connected to primary IDE connector through a 33 ohm series resistor. 5.6K ohm pulldown on the connector side of the series resistor.
I Connected to primary IDE connector through a 33 ohm series resistor. 1K ohm pull-up to
VCC on the connector side of the series resistor.
IO Connected to primary IDE connector through 33 ohm series resistors or also connected to
secondary IDE connector through 33 ohm series resistors if SPKR is pulled up to VCC3.
10K ohm pull-down on the VT82C686A side of the series resistor.
O Connected to secondary IDE connector through a 33 ohm series resistor.
I Connected to secondary IDE connector through a 33 ohm series resistor. 5.6K ohm pulldown on the connector side of the series resistor.
I Connected to secondary IDE connector through a 33 ohm series resistor. 1K ohm pull-up
to VCC on the connector side of the series resistor.
IO/I Connected to secondary IDE connector through 33 ohm series resistors when pin SPEAK
IO/O is strapped to low. Otherwise, Connected to Audio/Game port instead when pin SPEAK is
IO/I strapped to high.
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/O
IO/O
IO/O
IO/I
IO/I
IO/I
I/O
O
O
O
O
O
O
I
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AUTOFD#
PINIT#
SLCTIN#
STROBE#
ACK#
BUSY
ERROR#
PE
SLCT
PARALLEL PORT INTERFACE
I/O
Connection
IO Connect to the printer connector. 4.7K ohm pull-up to VCC and a 180pF decoupling
capacitor to ground. These passive components should be placed near the connector.
I Same as the above.
Signal Name
DRVEN0
DRVEN1
DIR#
DS0#
DS1#
HDSEL#
MTR0#
MTR1#
STEP#
WDATA
WGATE#
DSKCHG#
INDEX#
RDATA#
TRK00#
WRTPRT#
I/O
OD
OD
OD
OD
OD
OD
OD
OD
OD
OD
OD
I
I
I
I
I
Signal Name
PD[7:0]
FLOPPY DISK INTERFACE
Connection
Connect to primary floppy drive connector.
Connect to secondary floppy drive connector if it is installed. Otherwise, no connect.
Connect to the floppy drive connector.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Connect to the floppy drive connector. 1K ohm pull-up to VCC.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
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RXD2
RTS2#
CTS2#
DTR2#
DSR2#
DCD2#
RI2#
IRTX/GPO14
IRRX/GPO15
SERIAL PORTS AND INFRARED INTERFACE
I/O
Connection
O Connected to a corresponding 9-pin serial connector (usually COM1) through a serial
RS232 interface buffer and a 330pF decoupling capacitor to ground.
O Connected to a corresponding 9-pin serial connector (usually COM2) through a serial
RS232 interface buffer and a 330pF decoupling capacitor to ground.
O Connect to an Infrared connector. 4.7K ohm pull-up to VCC.
IO Connect to an Infrared connector.
Signal Name
SERIRQ/
GPIOE/
OC1#
DRQ2
SERIAL IRQ
I/O
I 4.7K ohm pull-up to VCC3.
IO
I
I
Signal Name
TXD1
RXD1
RTS1#
CTS1#
DTR1#
DSR1#
DCD1#
RI1#
TXD2
Signal Name
KBCK/A20GATE
KBDT/KBRC
MSCK/IRQ1
MSDT/IRQ12
Connection
INTERNAL KEYBOARD CONTROLLER
I/O
Connection
IO/I Connected to a keyboard connector through a 4.7K ohm pull-up to VCC, a 47pF capacitor
to ground, and a series ferrite bead.
IO/I Same as the above.
IO/I Connected to a mouse connector through a 4.7K ohm pull-up to VCC, a 47pF capacitor to
ground, and a series ferrite bead.
IO/I Same as the above.
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Signal Name
GPI0/IOCHCK#
GPI1/IRQ8#
GPI2/BATLOW#
GPI3/LID
GPI4/IRQ6/
SLPBTN#
GPI5/PME#/THRM
GPI6/SMBALRT#
GPI7/RING#
GPI8/GPO8/GPIOA/G
POWE#
GPI9/GPO9/GPIOB/
FAN2
GPI10/GPO10/GPIOC/
CHAS
GPI11/GPO11/
GPIOD
I/O
I
I
I
I
I
GENERAL PURPOSE INPUTS
Connection
4.7K ohm pull-up to VCC3 if no multiplexed function is applied.
10K ohm pull-up to 3VSB if its function is applied. Same, if not applied.
4.7K ohm pull-up to VCC3 if no multiplexed function is applied.
Same as the above.
Same as the above.
I
I
I
IO
Same as the above.
Same as the above.
Same as the above.
Same as the above.
IO
Same as the above.
IO
Same as the above.
IO
Same as the above.
Signal Name
GPO0
GPO1/SUSA#
GPO2/SUSB#
GPO3/SDD2/SDIN2
GPO4/CPUSTP#
GPO5/PCISTP#
GPO6/SUSST1#
GPO7/SLP#
GPO8/GP18/GPIOA/
GPOWE#
GPO9/GPI9/GPIOB/
FAN2
GPO10/GPI10/GPIOC/
CHAS
GPO11/GPI11/GPIOD
GPO12/XDIR/PCS0#
GPO13/SOE#/MCCS#
GPO14/IRTX
GPO15/IRRX
GPOWE#/GPIOA/
GPIO8
I/O
O
IO
IO
O
O
O
O
IO
IO
GENERAL PURPOSE OUTPUTS
Connection
10K ohm pull-up to 3VSB if its function is applied. Otherwise, no connect.
No connect if no multiplexed function is applied.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
IO
Same as the above.
IO
Same as the above.
IO
O
O
O
IO
IO
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
Same as the above.
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Signal Name
GPIOA(GPIO8)
GPIOB(GPIO9)/FAN2
GPIOC(GPIO10)/
CHAS
GPIOD(GPIO11)
GPIOE/
OC1/
SERIRQ/
DRQ2
GPIOF/
OC0/
DACK2#
GENERAL PURPOSE I/O
I/O
Connection
IO 4.7K ohm pull-up to VCC3 if no multiplexed function is applied.
IO
IO
I
I
I
IO
I
I
Same as the above.
Same as the above.
Same as the above.
HARDWARE MONITORING
Signal Name
I/O
Connection
I Connected to a monitored voltage (usually VCC2) through a voltage divider circuitry.
VSENS1
I Connected to a monitored voltage (usually 2.5V) through a voltage divider circuitry.
VSENS2
I Connected to a monitored voltage (usually VCC) through a voltage divider circuitry.
VSENS3
I Connected to a monitored voltage (usually +12V) through a voltage divider circuitry.
VSENS4
I Connect to a thermister that is near the sensed component or device.
TMPSENS1
TMPSENS2
P Connected to each thermister through a 10K ohm (1%) series resistor.
VREF
I Connect to a fan tachometer output
FAN1
FAN2/GPIOB(GPIO9)
CHAS/GPIOC(GPIO10) IO Connect to chassis intrusion circuitry.
Signal Name
XDIR/PCS0#/GPO12
SOE#/MCCS#/GPO13
XD INTERFACE
I/O
Connection
O Connect to the direction control of a 74F245 transceiver that buffers the X-Bus data and
ISA Bus data.
O Connect to the output enable control of two 74F245 transceivers that buffers the secondary
IDE data bus data and ISA address bus when the audio function is enabled.
CHIP SELECTS
Signal Name
PCS0#/GPO12/XDIR
MCCS#/GPO13/
SOE#
ROMCS#/KBCS#
I/O
O
O
O
Connection
Connect to addressed devices which drive data to the SD pins if XDIR and SOE# are
disabled and the X-Bus is not implemented.
Connect to the chip enable control of a micro-controller chip if XDIR and SOE# are
disabled and the X-Bus is not implemented.
Connect to the chip enable control of BIOS ROM. 4.7K ohm pull-down for Socket-7
configuration or 4.7K ohm pull-up to VCC3 for Slot-1 configuration.
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POWER MANAGEMENT
Signal Name
I/O
Connection
PME#/THRM/GPI5
10K ohm pull-up to 3VSB if the function is not applied.
I
PWRBTN#
Connect to Power Button circuitry.
I
SLPBTN#/IRQ6/GPI4
10K ohm pull-up to VCC3 if the function is not applied.
I
RSMRST
Connect to Resume Reset circuitry.
I
EXTSMI#
IOD 10K ohm pull-up to 3VSB if the function is not applied.
SMBALRT#/GPI6
I
LID/GP13
I
RING#/GP17
Connected to external modem circuitry to allow the system to be re-activated by a received
I
phone call. 10K ohm pull-up to 3VSB.
BATLOW#/GP12
I
CPUSTP#/GPO4
Connect to the system clock synthesizer to disable the CPU clock outputs if the function is
O
applied. Otherwise, no connect.
PCISTP#/GPO5
Connect to the system clock synthesizer to disable the PCI clock outputs if the function is
O
applied. Otherwise, no connect.
SUSA#/GPO1
O
SUSB#/GPO2
O
Connect to ATX Power On circuitry.
SUSC#
O
SUSST1#/GPO6
Connect to VT82C694X. 10K ohm pull-up to 3VSB.
O
10K ohm pull-up to 3VSB
SUSCLK
O
Signal Name
PWRGD
PCIRST#
RSTDRV
OSC
BCLK
RTCX1
RTCX2
Signal Name
VCC
VCCSUS
VCCHWM
GNDHWM
VCCUSB
GNDUSB
VBAT
GND
I/O
I
O
O
I
O
I
O
I/O
P
P
P
P
P
P
P
P
RESET AND CLOCKS
Connection
Connect to VT82C694X and Power Good circuitry.
Connect to PCI slots and PCI devices.
Connected to VT82C694X and IDE connectors through a 74F240 inverter IC. And direct
connect to ISA slots not through inverter.
Connect to the 14.318MHz clock output of the system clock synthesizer.
Connected to ISA slots through corresponding 33 ohm series resistors.
Connect to a 32.768KHz (RTC) crystal circuitry.
Connect to a 32.768KHz (RTC) crystal circuitry.
POWER AND GROUND
Connection
Connect to VCC3.
Connect to 3VSB.
Connected to VCC3 through a ferrite bead.
Connected to ground through a ferrite bead.
Connected to VCC3 through a ferrite bead.
Connected to ground through a ferrite bead.
Connect to battery circuitry.
Connect to digital ground
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5.4 Apollo Pro-133A Design Checklist
This Apollo Pro-133A (VT82C694X and VT82C686A) design checklist provides six checkup lists as a brief layout reference for
implementing most layout requirements.
5.4.1 General Layout Considerations Checklist
For most signal traces on an Apollo Pro133A motherboard layout, 5-mil trace width and 10-mil spacing are advised. To reduce
trace inductance, minimum power trace width is set at 30 mils. As a quick reference, recommended trace width and spacing for
different trace types are listed in Table 5-3.
Table 5-3. Recommended Trace Width and Spacing
Trace Type
Signal
Clock
Power
Trace Width (mils)
5 or wider
15 or wider
30 or wider
Spacing (mils)
10 or wider
15 or wider
20 or wider
In high-speed bus design, general rules for minimizing crosswalk are listed below:
•
•
•
•
Maximize the distance between traces. Maintain a minimum 10 mils space between traces wherever possible.
Avoid parallelism between traces on adjacent layers.
Select a board stack-up that minimizes coupling between adjacent traces.
The recommended impedance should be in the range of 65 ohm +/- 5 ohm.
5.4.2 Major Components Checklist
Major components for the Apollo Pro-133A based system are listed below:
•
•
•
•
•
•
Processor selection: Single Slot-1 CPU or Single Socket-370 CPU
Apollo Pro-133 A chipset combination: VT82C694X and VT82C686A
Apollo Pro-133A dedicate system clock synthesizers: ICS9248-39, PLL52C66-23 or IC Works W144
Maximum DRAM DIMM slots: 4 (Maximum 8 banks up to 2GB DRAM)
Maximum AGP slot: 1 only
Maximum PCI slots: 5
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5.4.3 Decoupling Recommendations Checklist
The high frequency and bulk decoupling capacitor distributions for major components are described in this section. Here, the high
frequency decoupling capacitors include 0.1uF (0603), 1uF (0805) and 4.7uF (1206) SMD ceramic capacitors. The bulk
decoupling capacitors include 10uF, 100uF and 1000uF electrolytic capacitors. The amount of bulk capacitors listed below is used
as reference. More capacitor distributions are recommended. These decoupling capacitors should be located as close to the
associated power and ground pins as possible.
For Slot-1 CPU, the decoupling capacitor requirements are listed below:
•
VCC_CORE: 0.1uF x 9, 1uF x 10 and 1000uF x 6
•
VTT: 0.1uF x 1, 1uF x1 and 100uF x 1
•
VCC3: 0.1uF x 2, 1uF x 2 and 1000uF x 2
•
VCC5: 0.1uF x 1, 1uF x 1
For Socket-370 CPU, the decoupling capacitor requirements are listed below:
•
VCC_CORE: 0.1uF x 21, 1uF x 23, 4.7uF x 10 and 1000uF x 6
•
VCC15: 0.1uF x 1, 1uF x1 and 1000uF x 4
•
VREF: 0.1uF x 6, 1uF x 2 and 10uF x 1
•
VCC25: 0.1uF x 1, 1uF x 1
•
VCCCOMS: 0.1uF x 1, 1uF x 1
For Chipsets, the decoupling capacitor requirements are listed below:
•
VT82C694X: 0.1uF x 8 or 1uF x 8
•
VT82C686A: 0.1uF x 8 or 1uF x 8
For DIMM modules, the decoupling capacitor requirements are listed below:
•
Two DIMM modules: 0.1uF x 9, 1uF x 10 and 1000uF x 2
•
Three DIMM modules: 0.1uF x 12, 1uF x 15 and 1000uF x 4
•
Four DIMM modules: 0.1uF x 16, 1uF x 20 and 1000uF x 5
For AGP slot, the decoupling capacitor requirements are listed below:
•
+12V: 0.1uF x 1, 1uF x 1 and 10uF x 1
•
•
•
VDDQ (1.5V or 3.3V): 0.1uF x 11, 1uF x 11 and 1000uF x 2
Note: The capacitor of adjusting the SDRAM clock skew should be placed very near the ball AD25 (DCLKWR) of VT82C694X.
Its capacitance is dependent on the SDRAM clock layout.
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5.4.4 Clock Trace Checklist
The general clock routing guidelines are listed below:
•
•
•
•
•
•
The recommended range of a clock trace width is between 15 mils and 20 mils.
The minimum space between one clock trace and adjacent clock traces is 15 mils. The minimum space from one segment
of a clock trace to other segments of the same clock trace is two times of the clock width. That is, more space is needed
from one clock trace to others or its own trace to avoid signal coupling.
Clock traces should be parallel to their reference ground planes. That is, a clock trace should be right beneath or on top of
its reference ground plane.
Series terminations (damping resistors) are needed for all clock signals (typically 10 ohms to 33 ohms). When two loads
are driven by one clock signal, separate series terminations are required. When multiple loads (more than two) are
applied, a clock buffer solution is preferred.
Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically 20 mils to 50
mils) are preferred.
No clock traces on the internal layer if a six-layer board is used.
5.4.5 Clock Trace Length Calculation
The trace length calculations for different clock signal groups are described in this section. A different component placement may
result in a different calculation for the clock trace length. The trace length of those clock signals not mentioned in this section
should be as short as possible or less than 9 inches.
CPU Clock Trace Length Calculation for Slot-1 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Slot-1
CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of the
longest one (usually CPUCLK). A calculation example is shown below.
Clock Trace
Clock chip à CPU
Shortest
Length
LCPU
LNB
Desired
Length
LCPU
LCPU + 3"
Allowable
Difference
0.5"
Allowable
Range
1"~9"
4"~12"
Note: Here, the 3" represents the estimated trace length added into HCLK for CPU clock alignment.
CPU Clock Trace Length Calculation for Socket-370 System
Before routing any other signals on the board, pre-route every CPU clock trace from the system clock synthesizer to the Socket370 CPU (CPUCLK) and North Bridge (HCLK) as short as possible. All high frequency clock alignment will be on the basis of
the longest one (usually HCLK). A calculation example is shown below.
Clock Trace
Clock chip à CPU
Shortest
Length
LCPU
LNB
Desired
Length
LNB
LNB
92
Allowable
Difference
0.5"
-
Allowable
Range
1"~9"
1"~9"
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SDRAM Clock Trace Length Calculation
Pre-route SDRAM clock traces (SDCLK0~SDCLK15) from the system clock synthesizer to the DIMM slots as short as possible.
The length of all SDRAM clocks will be based on the longest one (LSD). The length of DCLKWR (LDIN) should be the same as
that of the SDCLKs. The DCLKO clock trace should be as short as possible. A calculation example is shown below.
Clock Trace
Clock chip à SDCLK[15:0]
DCLKWR (Clock chip à NB)
DCLKO (NB à Clock chip)
Shortest
Length
LSD
LDIN (assume < LSD +3")
LDOUT
Desired
Length
LSD
LSD + 4.5"
LDOUT
Allowable
Difference
0.5"
0.5"
-
Allowable
Range
1"~4"
5.5"~8.5"
1"~9"
Note: Here, the 4.5" represents the estimated trace length added into DCLKI for SDRAM clock alignment.
AGP Clock Trace Length Calculation
Pre-route AGP clock traces from the pin GCLKO of the VT82C694X to the AGP slot as short as possible. Then the trace length
for the signal GCLK should be the GCLKO trace length plus 3 inches.
Clock Trace
GCLKOUT (NB à AGP Slot)
GCLKIN (NB à NB)
Shortest
Length
LGOUT
LGIN
Desired
Length
LGOUT
LGOUT + 3"
Allowable
Difference
0.5"
Allowable
Range
1"~9"
4"~12"
Note: Here, the 3" represents the estimated trace length added into GCLKI for AGP clock alignment.
PCI Clock Trace Length Calculation
Pre-route PCI clock traces from the system clock synthesizer to the VT82C694X (NPCLK) and VT82C686A (SPCLK) as short as
possible. Then pre-route PCI clock traces PCLK0~PCLK4 from the system clock synthesizer to all PCI slots as short as possible.
The length of these clocks will be based on the longest one (L5 ). A calculation example is shown below.
Clock Trace
Clock chip à VT82C686A (SB)
Clock chip à PCI1
Clock chip à PCI2
Clock chip à PCI3
Clock chip à PCI4
Clock chip à PCI5
Shortest
Length
LNB
LSB
L1
L2
L3
L4
L5 ( > the others)
Desired
Length
L5 + 3"
L5 + 3"
L5
L5
L5
L5
L5
Allowable
Difference
1"
1"
1"
1"
1"
1"
-
Allowable
Range
4"~15"
4"~15"
1"~12"
1"~12"
1"~12"
1"~12"
1"~12"
Note: Here, the 3" represents the estimated trace length added into NPCLK and SPCLK for PCI clock alignment.
Notes for the length calculation of all clock traces:
1. Shortest length means the minimum routable trace length between both clock ends. Desired length means the real length of the
clock traces on PCB layout. Allowable difference means the maximum difference between clock traces of the same type.
Allowable range means the acceptable clock length range for the specific clock.
2. The location of the system clock chip can affect the length of all clock traces. To optimize the clock alignment, place the clock
chip at an appropriate location.
3. In addition, the trace impedance of all clock traces should be in the range between 40 ohms and 55 ohms.
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5.4.6 Signal Trace Attribute Checklist
The maximum accumulated trace length as a brief layout reference for high-speed or critical signal groups (e.g. host and memory)
is listed in Table 5-4. The accumulated trace length represents the total trace length or the length sum of two traces before and
after a damping resistor. It is recommended to route the same signal groups in equal length and as short as possible. A minimum
of 5 mils in width and a minimum of 10 mils in spacing are required for all these signals.
Table 5-4. Maximum Accumulated Trace Length
Signal Group
Host Address
Host Data
Host Control
Host Compatibility (from VT82C686A)
Memory Address
Memory Data
Memory Control
AGP Address / Data
AGP Strobe
AGP Control
PCI Address / Data
PCI Control
USB Data
System Management Bus
IDE Data
IDE Control
Maximum accumulated trace length
4.5”
4.5”
4.5”
As short as possible.
4”
4”
6”
6”
6”
6”
4.5”
4.5”
Note
1
1
1
2
3
3
3
4
4
5
6
7
7
Notes:
1. When using Socket-370 CPU, VTT termination stub for the host interface should be less than 2”. Both the VTT termination stub
and the trace connected to VT82C694X (NB) directly come out the pin of the Socket-370. The location of these termination (56
ohm) resistor networks should be placed as close to Socket-370 CPU as possible. No VTT termination is needed for a Slot-1
CPU based system.
2. Each VT82C686A south bridge Open Drain (OD) output control signal to the CPU needs a 150 ~ 450 ohm pull-up which should
be placed as close to the VT82C686A chip as possible.
3. The trace width of six strobe lines (GDS[1:0], GDS[1:0]#, SBS and SBS#) is 5 mils. Trace length mismatch in any Data/Strobe
group should be maintained within 0.5 inch. The maximum pull-up stub trace length on strobe lines and other traces should be
less than 0.5 inch. Instead of R-packs, discrete pull-up resistors should be used. It is strongly recommended to keep the stub
length as short as possible and maintain the trace length of all AGP (especially Data and Strobe) signals less than 6 inches. It
is always best to reduce line mismatch to add to the timing margin. In other words, a balanced topology will match trace
lengths within the groups to minimize skew. To minimize signal crosstalk, wider spacing is recommended wherever possible
between traces.
4. The VT82C694X and VT82C686A should be placed at both ends of the PCI bus for better signal termination.
5. Each pair of USB data signals is required to be parallel to each other with the same trace length. Each pair of USB data
signals is required to be parallel to a relative ground plane.
6. Adding 68pF capacitors to the system management bus at the end device is essential since the I2C bus travels a long way and
might pick up noise along the route.
7. All signals for primary IDE and Secondary IDE require 33 ohm series termination resistors. These series terminations should
be placed as close as possible (less than 1 inch) to the VT82C686A. Data and strobe lines (DD[15..0], IOR#, IOW#, and
IORDY#) should be routed as a bus. The total trace length of these signals should be shorter than 4.5 inches. The maximum
trace length difference among them must be less than 1 inch. Other lines should be as short as possible. Signal DD7 needs a
10K pull-down on the VT82C686A chip side of the series termination. Signal DREQ needs a 5.6K pull-down on the connector
side of the series termination. Signal IRQ14 (and IRQ15) needs a 10K pull-down or pull-up (preferred) on the connector side of
the series termination. Signal IORDY# needs a 1K pull-up on the connector side of the series termination. Pin 28 of the IDE
connectors should be tied to ground with a 470 ohm serial resistor.
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APPENDICES
The following schematics are provides "as is" with no warranties whatsoever, including any warranty of merchantability, fitness of
any particular purpose, or any warranty otherwise arising out of proposal, specification or sample. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights are granted herein. VIA Technologies, Inc. disclaims all liability,
including liability for infringement of any proprietary rights, relating to use of information in this specification. VIA
Technologies, Inc. does not warrant or represent that such use will not infringe such rights. Third-party brands and names are the
property of their respective owners.
Copyright © VIA Technologies Incorporated. 1999
Appendix A - Application Circuits of SPKR Strapping
Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines
Appendix C - Apollo Pro133A Reference Design Schematics
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Appendix A - SPKR Strapping Application Circuits
Power-up strapping for the VT82C686A SPKR pin (pin V5) determines the function of the Secondary IDE disk data bus pins
(SDD[15..0]) to be either SDD[15..0] (SPKR strapped low) or Audio/Game port functions (SPKR strapped high). The speaker
drive circuit commonly used in PC motherboards uses a fairly small base resister (on the order of 22 ohms) into the base of a
transistor driver. This circuit, however, results in too low a voltage on the SPKR pin for the strap pullup resistor to overcome. In
this case, power up reset will always detect a low signal. Therefore, either of the two application circuits shown below in figures
A-1 or A-2 should be used to insure that both high and low strap levels are detected properly.
JSPEAK
SDD Function
1-2
Audio/Game
2-3
SDD[15..0]
Jumper Strapping circuit
VCC3
JSPEAK
1
SPKR
V5
VCC
1K ohm
2
4.7K ohm
3
100 ohm
Header
1X3
VT82C686A
Speaker
(South Bridge)
2K ohm
Q1
3904
Speaker circuit
Figure A-1. VT82C686A SPKR Pin Transistor Driver Solution (I)
Jumper Strapping circuit
VT82C686A
VCC3
(South Bridge)
JSPEAK
1
SPKR
V5
1K
2
4.7K
3
Header
1X3
Speaker
2K
JSPEAK
SDD Function
1-2
Audio/Game
2-3
SDD[15..0]
1
2
22
74HCT05
Speaker circuit
Figure A-2. VT82C686A SPKR Pin Inverter Driver Solution (II)
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Appendix B - Audio Codec and Game/MIDI Port Layout Guidelines
B.1 Introduction
This document describes the Printed Circuit Board (PCB) layout recommendations for VIA VT1611A (AC’97 audio codec) and
Game/MIDI port in a motherboard design. The main focus is on how to improve the audio quality. Electromagnetic interference
(EMI) issues are not considered in the document. The layout guidelines of component placement, power and ground planes and
signal routing for VT1611A and Game/MIDI port (using a stacked LINE_OUT, LINE_IN, MIC_IN and Game/MIDI IO
connector) on a motherboard are described in detail in the following sections.
VIA VT1611A 18-bit Σ∆ audio codec conforms to the AC’97 2.1 specification with excellent analog performance. Refer to
VT1611A datasheet for more detail. Figure B-1 shows a typical single audio codec function block diagram and the direct
connections between the VT82C686A south bridge controller and the Game/MIDI port. Audio input/output signals are processed
by VT1611A audio codec. Through the AC’97 link, VT1611A audio codec is controlled by VIA VT82C686A south bridge
controller.
Audio Output
Audio
Amplifier
Audio Input
VIA
VT1611A
AC'97 Link
(Audio Codec)
LINE_OUT
LINE_IN
MIC_IN
CD_IN
Header
Game/MIDI
VIA
A
M
R
VT82C686A
(South Bridge)
Game/MIDI
Figure B-1. AC’97 Audio Codec and Game/MIDI Port Block Diagram
Reference AC’97 audio codec and Game/MIDI port schematic is shown in the end page of this appendix. The reference schematic
shows an applicable AC’97 audio codec circuit. Five audio input circuits and one audio output circuit are applied. The
connections between VT82C686A and the Game/MIDI port are also shown in the schematic.
Guidelines
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Appendix B - Audio Codec and Game/MIDI Port Layout
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B.2 Layout Recommendations
In this section, the layout recommendations on component placement, ground and power plane partitions and routing guidelines
are described in detail. The PCB layer sequence used here is Signal (Component)-Ground-Power-Signal (Solder).
B.2.1 Component Placement
AC’97 Audio Codec and Audio Amplifier
AC’97 audio codec (VT1611A) and audio amplifier (TPA122) are two major components in the audio codec circuitry. An
example placement for AC’97 audio codec and audio amplifier on either ATX or micro-ATX form factor is shown in Figure B-2.
To limit the audio analog grounding area (GND_AUD), it is not recommended to place the audio codec far from the LINE_OUT,
LINE_IN and MIC_IN audio jacks. And the audio amplifier should be located right beside the LINE_OUT audio jack because the
audio line out signals are very sensitive to noise from any other signals.
Figure B-2. AC’97 Audio Codec and GAME/MIDI Port Placement Example
VDD/VSS Capacitive Decoupling
There are analog power signals (two pairs of AVDD/AVSS signals) and digital power signals (two pairs of DVDD/DVSS signals)
on VT1611A audio codec. Local regulation converting from +12V power for analog power supply to VT1611A is strongly
recommended. No local regulation is required for DVDD power supply to VT1611A. Directly using on-board +5V power can
already provide adequate digital power supply to VT1611A through a ferrite bead.
All high frequency AVDD5 decoupling capacitors (less than 10uF, ceramic) should be placed very close to the AVDD/AVSS pins
of VT1611A and the connection from codec pin to capacitor pad should be routed on the same layer with a short and wide trace (or
a small power plane). That is, there should be no vias connecting the decoupling capacitor to the device pin. All high frequency
DVDD5 decoulping capacitors should have short wide traces connecting to DVDD/DVSS to decrease ground bounce and other
noise coupling caused from digital switching. These high frequency DVDD5 decoupling capacitors should be placed very close to
the DVDD/DVSS pins of VT1611A. All high frequency AVDD decoupling capacitors should use the same way described above.
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These high frequency decoupling capacitors should be routed on the component layer with wide traces to reduce impedance and
placed on their respective ground plane.
Low frequency decoupling capacitors (basically greater than or equal to 10uF, Electrolytic or Tantalum) are used to prevent power
supply droop during load transient. These large 10uF low frequency VDD (AVDD or DVDD) decoupling capacitors do not need
to be placed close to the codec, but do need to be placed over the proper ground plane. That is, the DVDD decoupling capacitors
should be placed over digital ground and the AVDD decoupling capacitors should be placed over analog ground. See ground and
power planes section for more information. The low frequency decoupling for the +12V input to the regulator are also over the
digital plane.
Referring to Figure B-2, high frequency decoupling capacitors CM1 and CB4 are placed very near the one pair of AVDD and
AVSS pins (pins 25 and 26) and the other pair of AVDD and AVSS (pins 38 and 42) respectively. The location of low frequency
decoupling capacitors CT5 and CT6 are also close to analog power and ground pins. Similarly, decoupling capacitors CB1, CM2
and CT10 are located very near the digital power and ground (DVDD and DVSS) pins. Decoupling capacitors CB6, and CT3 are
located very near the analog power and ground (VAA and GND) pins of audio amplifier.
Table B-1. Decoupling Capacitor List
Power plane
AVDD5
DVDD5
AVDD
High Frequency Capacitors
CB4, CM1
CB1, CM2
CB6
Low Frequency Capacitors
CT5, CT6
CT10
CT3
Ferrite Bead
L5, L1
L2
L6
Note
Voltage Reference Bypass and Filter Capacitors
All high frequency decoupling capacitors for the voltage reference should be placed close to the VT1611A chip and routed on the
component layer with wide traces to reduce impedance. The filter capacitors on the VREF, VREFOUT, AFILT1 and AFILT2 pins
should also be top routed and laid close to the codec pins.
Referring to Figure B-2, high frequency decoupling capacitors CB3, C25, C28 and C29 are placed very near the pins VREF,
VREFOUT, AFILT1 and AFILT2 (pins 27, 28, 29 and 30 respectively).
AC-Coupling Capacitors
It is recommended to place all ac-coupling capacitors as close to the device receiving the signal as possible even though they are
not critical. Table B-2 and Table B-3 respectively list the ac-coupling capacitors for audio input and output signals in the example
schematics. When an audio function is not used, the ac-coupling capacitors for it are no longer needed. That is, take away the accoupling capacitors and leave the pins open, such as MIC_IN_2.
Table B-2. AC-Coupling Capacitors for Audio Input Signals
Audio Input Signals
CD_L
CD_R
CD_GND
LINE_IN_L
LINE_IN_R
PC_BEEP
MIC_IN_1
MIC_IN_2
AUX_IN_L
AUX_IN_R
VIDEO_L
VIDEO_R
Guidelines
C13
C12
C14
C15
C16
C24
C23
None
None
None
None
None
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1
1
1
1
1
1
1
1,2
1,2
1,2
1,2
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Table B-3. AC-Coupling Capacitors for Audio Input Signals
Audio Output Signals
LINE_OUT_L
LINE_OUT_R
MONO_OUT
LNLVL_OUT_L
LNLVL_OUT_R
C17
C18
None
None
None
Note
1
1
1,2
1,2
1,2
Notes
1. Use all ac-coupling capacitors in 1206 package.
2. Use the same ac-coupling mechanism when the function is applied.
These audio input ac-coupling capacitors in Table B-2 should be placed near the audio codec. For example, C13, C12, and C14
should be placed near pins CD_L, CD_R and CD_GND of the audio codec respectively since they take their CD-in signal from the
CD_IN header.
The line-out signals are delivered from the audio codec to the LINE_OUT jack through the audio amplifier. Therefore, these audio
output ac-coupling capacitors in Table B-3 should be placed near the audio amplifier. C17 and C18 should be placed near pins
INB and INA of the audio amplifier respectively since they receive the line-out signal from the audio codec. This audio amplifier
should be placed close to the LINE_OUT jack from preventing any noise coupling.
Referring to Figure B-2, C15, C16 and C23 are close to the audio codec since they take their signal from the LINE_IN and
MIC_IN jacks. The ac-coupling capacitors C13, C12 and C14 are close to the audio codec since they take their signal from the onboard CD_IN header. The ac-coupling capacitor C24 is close to the audio codec since it receives the speaker signal from the
VT82C686A south bridge controller.
Voltage Regulators
The DC-DC voltage regulator supplies the 5V analog power to the audio codec from +12V system power. In this manner, noise
form other digital powers can be isolated by the regular and a quiet analog power can be obtained through a ferrite bead. The
+12V input and 5V output (VDD5) routings should be made over the digital ground plane. The 5V output is set close the analog
section of the codec through a ferrite bead. The analog 5V routing (AVDD5) should be over the analog ground plane. See Section
B.2.2 for more information on digital and analog ground planes.
Referring to Figure B-2, the regulator locating on the upper-left side of the audio codec can provide the shortest power path to the
audio codec.
On-board Audio Connectors
CD_IN headers and other on-board audio connectors such as telephony audio can be placed anywhere over the analog ground
plane. That is, they do not need to be close to the codec, but do need to be enclosed by a ground plane. The analog ground plane
is chosen since it is the quietest ground.
Referring to Figure B-2, the CD_IN header was placed close to the codec and the ac-coupling capacitors C12, C13 and C14 as well
as resistors R12, R13, R14, and R15 were laid between the codec and header to keep the layout tight to reduce noise coupling and
DC offsets.
Guidelines
102
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We Connect
B.2.2 Ground and Power Planes:
It is recommended to include partitioned digital and analog power planes directly over their respective ground planes. The powerground sandwich with a substrate separation can provide an extremely effective, low ESR & ESL bypass capacitance. The audio
IC leads will have pads and vias that go directly to the appropriate plane for power and ground. All digital components are
mounted over the digital power/ground plane sandwich and all analog components over the analog power/ground sandwich. This
doesn't avoid the need for additional ceramic bypass capacitors at the IC pins as mentioned above. The importance and
effectiveness of ground planes cannot be over emphasized to optimize the performance of the codec.
Ground planes
VIA recommends having separate analog and digital ground planes on the PCB ground layer (2nd layer in our case). All digital
pins of the codec and all digital support components should be over the digital ground. All analog pins and analog support
components should be over the analog ground plane. Three analog ground planes (GND_AUD, GND_LOUT and GND_MIDI)
and one digital ground plane (GND) are shown in Figure B-3. Table B-4 lists the audio signals covered by different ground
planes. The line out circuit should refer to its own analog ground partition (GND_LOUT) instead of GND_AUD for better signal
consideration.
All digital routing should not run over the analog plane. If it is necessary to route a digital signal over the analog plane the trace
length should be short and the digital signal should be static. All analog routing should be over the analog plane. When analog
signals need to cross the gap in the ground plane (when connecting the jacks for example) components such as ferrite beads or 0
ohm shorts should be used. Signal traces should never cross the gap between the ground planes.
The analog ground and digital ground planes should be connected through only one ferrite bead (preferred) or a series 0 ohm
resistor. The recommended location for the ferrite bead or the 0-ohm resistor is on the quietest area where have no signals passing
around.
Figure B-3. Ground Layer Layout Example
Guidelines
103
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We Connect
Table B-4. Signal Groups Associated with Their Audio Ground Plane
Ground Planes
GND_AUD
GND_LOUT
GND_MIDI
Digital Ground
Audio Signals
Audio input signals: AUX_L. AUX_R, VIDEO_L, VIDEO_L, VIDEO_R, CD_L. CD_R,
CD_GND, LINE_IN_L, LINE_IN_OUT, MIC1, MIC2, PHONE_IN
Audio reference signals: MONO_OUT, VREFOUT, VREF, AFILT1 and AFILT2
Analog Power signals: AVDD1, AVDD2, AVSS1 and AVSS2
Audio output signals: LINE_OUT_L, LINE_OUT_R, LNLVL_OUT_L and LNLVL_OUT_R
Game/MIDI port signals: JAB1, JBB1, JACX, JACB, MSO, JBCY, JACY, JBB2, JAB2
Digital power signals: DVDD1, DVDD2, DVSS1 and DVSS2
AC link signals: SYNC, SDIN, SDOUT, -ACRST, and BIT_CLK
Miscellaneous signals: XTL_IN, XTL_OUT, PC_BEEP, EAPD, ID1 and ID0
Note
Power planes
Referring to Figure B-4, no analog power plane partitions on the PCB power layer (3rd layer in our case) is required since all audio
signals had been laid on the component layer. These signals can directly refer to their respective ground plane. The power planes
represented on the component or solder layer should be placed directly over their respective ground plane. For example, the
AVDD5 power plane should not be outside of the GND_AUD (analog ground) plane.
All analog power supply connections and routing on the component layer should be over the analog ground planes and all of the
digital power connections and routing on the component layer should be over digital ground planes. The +12V input voltage to the
regulator should be a wide trace that routes over the digital ground plane. +12V routing over digital planes and located near the
edge of the board. Analog section is well bounded making it easy to create power/ground sandwich.
Figure B-4. Power Layer Layout Example
Guidelines
104
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B.2.3 Routing Guidelines
Routing to VDD, VREF, AFILT and FILT capacitors
All high frequency decoupling, reference high frequency decoupling and filter capacitors must be routed on the same layer as the
codec. This is done to reduce inductance in the supply, reference and filter networks. Inductive loops in these networks can be a
coupling mechanism for high frequency noise. High frequency noise can then be aliased down into the audio band during the A/D
or D/A process.
Audio Input/Output Routing
Keeping traces short can decrease inductance and help avoiding magnetic coupling. This allows a straight-line route and also
allows for shielding with ground traces. Regions between analog signal traces should be filled with copper; the copper fill should
be shorted to the analog ground plane. This will help to reduce high frequency interference by creating a capacitance coupling
mechanism from signal to ground.
AC’97 Link Routing
The AC’97 link signals should be as short as possible. If the signal traces need to be long certain pre-cautions should be made to
reduce ringing and signal reflections. Clock signal such as BIT_CLK should have a series resistor close to the codec. Other
clocks like the 24.576MHz clock should have series resistor by the clock source. If a 24.576MHz crystal is used series resistance
is not required. This series resistance in the clock lines will help to reduce reflections. A shunt capacitor should also be used on
these clock lines to help reduce ringing. Preferably the capacitors should be placed close to the clock source but should be
electrically connected to the opposite side of the series resistor. It is also recommended to place series resistors on the SDATA_IN
and SDATA_OUT lines. The resistors should be placed close to the signal source.
The use of ground trace shields may also help to reduce noise coupling and radiation from the digital link. Therefore, regions
between digital signal traces should be filled with copper. The copper fill should be shorted to the digital ground plane. Therefore,
excellent shielding through capacitive coupling can be achieved.
Referring to Figure B-5, the AC’97 link signals should come in from the lower side of the audio codec to keep them far from the
analog signals.
Game/MID Signals Routing
The Game/MIDI resistor-capacitor components should be placed on the analog Game/MIDI ground (GND_MIDI) and as close to
the Game/MIDI port as possible.
Referring to Figure B-6, the Game/MIDI signals should come in from the lower side of the Game/MIDI port to keep them far from
other analog signals.
Guidelines
105
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Figure B-5. Component Layer Layout Example
Figure B-6. Solder Layer Layout Example
Guidelines
106
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Table B-5 and Table B-6 show the layout guideline summary for signal and power/ground nets respectively in the reference
schematic.
Table B-5. Routing Guidelines for Signal Nets
Net Name
SYNC, SDIN,
SDOUT, -ACRST
BITCLK
PC_BEEP, ID1,
ID0, EAPD
XTLI, XTIO
CDL, CDR
CDGND
MICIN
LINE_L, LINE_R
AFILT1, AFILT2,
VREF, VREFOUT
LINEOUTL,
LINEOUTR
Routing Guidelines
Maintain 8 mil trace width and 12 mil spacing
Note
1
Maintain at least 10 mil trace width and 20 mil spacing
1
1
1
1
1
1
1
1
Maintain 10 mil trace width and 20 mil spacing all the way through audio amplifier to
LINE_OUT jack.
1
Note: Wherever possible, keep the spacing as wide as possible for all signals.
Table B-6. Routing Guidelines for Power and Ground Nets
Net Name
AVCC5
AVDD5
DVDD5
AVDD
GND_AUD, GND_LOUT,
GND_MIDI
Routing Guidelines
Maintain small power island (plane) or short and wide (as wide as possible) trace to
ferrite bead L5 before providing power to AVDD5
pins AVDD1 and AVDD2 of VT1611A
pins DVDD1 and DVDD2 of VT1611A
pin VAA of TPA122 audio amplifier
Maintain 20 mil trace width on the component layer through a ferrite bead and then
multiple vias to digital ground
Note
1
1
1
1
2
Notes:
1. Refer to power planes A, B, C and D in Figure B-5 and Figure B-6 for AVCC5, AVDD5, DVDD5 and AVDD respectively.
2. Refer to analog ground planes in Figure 3 for GND_AUD, GND_LOUT and GND_MIDI and ground plane E for GND_LOUT
in Figure B-5 and Figure B-6.
Guidelines
107
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Guidelines
108
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Apollo Pro133A Reference design schematics are shown in the following 20 pages. The component placement for this reference
design is shown in Figure C-1. The system specification for this motherboard design is listed below:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ATX Form Factor
Single Slot-1 CPU (66-133 MHz)
Apollo Pro133A single chip clock synthesizer
VT82C694X Apollo Pro133A North Bridge (CPU/AGP/PCI bridge with integrated DRAM controller)
VT82C686A South Bridge (PCI-to-ISA bridge with integrated I/O controllers)
Three DIMM Slots (maximum 1.5GB and 133 MHz memory frequency)
One AGP Slot (66MHz)
Two PCI Slots (33MHz)
One ISA Slot (8/16MHz)
One AMR slot
Two Enhanced IDE (up to 66MHz) Interfaces
Four USB (48MHz) Ports
PS2 Keyboard/Mouse Support
Ring In, Modem Wake up and LAN Wake up circuitry
One AC’97 Link Controller (to cooperate with a AC’97 Codec chip)
One Floppy Drive Interface
One Infrared Interface
Various Hardware Monitoring (support 5 positive voltage, 3 temperature, and 2 fan-speed monitoring)
One parallel Port and Two Serial Ports
One MIDI/GAME Port
One 2MB Flash ROM
109
Technologies, Inc.
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Figure C-1. Apollo Pro133A Reference Component Placement
110
1
2
3
4
VIA Preliminary Customer Reference Schematics
MODEL:VT5228C
A
(SLOT 1+VT82C694A/X+VT82C686A+AGP2X/4X MODE+STR FUNCTION)
VER:0.1
A
TITLE
SHEET
COVER SHEET
1
SLOT-1 PROCESSOR
2
NORTH BRIDGE (VT82C694A/X)
3,4
SOUTH BRIDGE (VT82C686A)
5,6
USB2,3 & FREQUENCY RATIO
7
SDRAM & LAN,MODEM WAKE UP FUNCTION
8,9
PCI SLOTS
10
AGP SLOT & AGP 2X/4X OPTION CIRCUITS
11
ISA SLOTS
12
IDE & PANEL
13
CLOCK SYNTHESIZER & KEYBOARD WAKE UP FUNCTION
14
ATX POWER CONNECTOR & BYPASS CAPACITORS
15
DC-DC CONVERTER
16
B
B
C
C
PRINTER / COM PORT
17
AUDIO CODEC & AUDIO PORT & JOSTICK PORT
18
AMR SLOT
19
STR OPTION CIRCUITS
20
|LINK
| 2.SCH
| 3.SCH
| 4.SCH
| 5.SCH
| 6.SCH
| 7.SCH
| 8.SCH
| 9.SCH
| 10.SCH
| 11.SCH
| 12.SCH
| 13.SCH
| 14.SCH
| 15.SCH
| 16.SCH
| 17.SCH
| 18.SCH
| 19.SCH
| 20.SCH
D
D
VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS
IN DRAWING THESE SCHEMATICS. THESE SCHEMATICS ARE SUBJECT
TO CHANGE AT ANY TIME WITHOUT NOTICE.
Title
COVER SHEET
COPYRIGHT 1999 VIA TECHNOLOGIES INCORPORATED.
1
2
3
Size
C
Document Number
VT5228C (Preliminary)
Date:
Wednesday, November 24, 1999
Rev
0.1
4
Sheet
1
of
20
1
2
3
4
SLOT1
PENTIUM-II
-CPUINIT
-CPURST
INTR
NMI
-SMI
-STPCLK
-SLP
R96
330
-CPUINIT
-CPURST
CPUCLK
A75
AP0
AP1
AERR
GTL
BPRI
BNR
LOCK
ADS
DRDY
DBSY
TRDY
HIT
HITM
DEFER
RP
RSP
DEP0
DEP1
DEP2
DEP3
DEP4
DEP5
DEP6
DEP7
RS0
RS1
RS2
BPM0
BPM1
BP2
BP3
FERR
IGNNE
A20M
PICD0
PICD1
PICCCLK
GTL
PWRGOOD
2.5V
BCLK
2.5V
GTL
PREQ
PRDY
GTL
BERR
BINIT
IERR
FRCERR
2.5V
GTL
2.5V
INTR/LINT0
NMI/LINT1
SMI
STPCLK
SLP
FLUSH
INIT
RESET
VID0
VID1
VID2
VID3
VID4
VID0
VID1
VID2
VID3
VID4
2.5V
TCK
TDI
TDO
TMS
TRST
2.5V
THERMTRIP
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
BSEL0
BSEL1
Short
Short
Jumper function
A
Bus freq. auto
detected by CPU.
Open
Short
Test 66/100 MHz CPU
run 100/133 MHz.
(north bridge divide host clock by 3)
Short
Open
Test 100 MHz CPU
run 133 MHz.
(north bridge divide host clock by 4)
A117
B116
B118
B
A76
B75
-BREQ0
-BREQ0
A103
A101
B106
-BPRI
-BNR
-HLOCK
-BPRI
-BNR
-HLOCK
A115
-ADS
-ADS
B102
B103
A107
A108
B104
-HREQ0
-HREQ1
-HREQ2
-HREQ3
-HREQ4
B107
A111
A104
-DRDY
-DBSY
-HTRDY
-DRDY
-DBSY
-HTRDY
B110
A109
A105
-HIT
-HITM
-DEFER
-HIT
-HITM
-DEFER
-HREQ[0..4]
B114
B115
B108
A112
B111
C
-RS0
-RS1
-RS2
-RS[0..2]
A23
B24
B19
A21
VCC2_5
R91
A20
B23
330
A77
A24
A4
B76
VCC2_5
R95
330
B7
A9
A11
B10
B11
VCC2_5
A15
R93
330
D
Title
VCC2_5
R94
1
BREQ0
BREQ1
REQ0
REQ1
REQ2
REQ3
REQ4
B120
A120
A119
B119
A121
CPUCLK
A17
B16
B3
B6
B8
B2
B4
B74
A12
VCCP_GD
D
A19
B22
B18
B109
B98
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
B79
A79
A80
B78
EMI
EMI
EMI
EMI
EMI
SLOTOC#
VCC2_5
INTR
NMI
-SMI
-STPCLK
-SLP
APICD0
APICD1
APICLK
VCC
B113
B117
B121
BSEL0
BSEL1
APICLK
VCC3
A1
A3
B5
B9
B1
B100
B41
B61
B81
B101
470
470
A7
A8
A5
VTT
B13
B17
B25
B29
B33
B37
B45
B49
B53
B57
B65
B69
B73
B77
B85
B89
B93
B97
B105
B21
A14
R92
R89
-FERR
-IGNNE
-A20M
VCCP
A2
A6
A10
A18
A22
A26
A30
A34
A38
A42
A46
A50
A54
A58
A62
A66
A70
A74
A78
A82
A86
A90
A94
A98
A102
A106
A110
A114
A118
TESTHI
-FERR
-IGNNE
-A20M
VCC2_5
GTL
GND
RESERVED
RESVERED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
A25
A27
B26
A28
B27
A29
A31
B28
C
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
P6 KLAMATH SLOT
A13
B
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
B12
B20
A16
A47
A88
A113
A116
B112
B15
B14
A
B72
A73
B71
A72
B70
A71
B68
B67
A69
A68
A65
A64
B66
A63
A67
B64
A61
B63
B60
B59
B62
A60
B58
A59
A57
B56
B55
A56
B52
B54
A55
A53
B51
A51
B48
A52
B46
A49
B50
A45
B47
B42
A43
A48
B44
A44
A39
B43
B39
A40
B35
A41
B40
A36
B36
A33
B34
A37
B31
B38
A35
A32
B30
B32
VID0
VID1
VID2
VID3
VID4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
2
4.7K
BSEL1
2
BSEL0
2
SLOT 1
1
1
BSEL1
BSEL0
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
2
of
20
1
2
3
4
M21
M22
U6
W21
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCIRST
PREQ0
PREQ1
PREQ2
PREQ3
PREQ4
PGNT0
PGNT1
PGNT2
PGNT3
PGNT4
C_BE0
C_BE1
C_BE2
C_BE3
R117
75 1%
K6
K2
K4
K3
K5
J1
J2
H2
H1
J5
H3
H5
H4
G1
G2
G4
D1
D3
D2
C1
A2
C3
B3
D4
E5
A4
D5
B4
B5
A5
E6
C6
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_D16
A_D17
A_D18
A_D19
A_D20
A_D21
A_D22
A_D23
A_D24
A_D25
A_D26
A_D27
A_D28
A_D29
A_D30
A_D31
E1
F3
E2
F5
F4
F2
B6
D6
G5
F1
-FRAME
-DEVSEL
-IRDY
-TRDY
-STOP
-PLOCK
-PCIREQ
-PCIGNT
PAR
-SERR
-FRAME
-DEVSEL
-IRDY
-TRDY
-STOP
-PLOCK
-PCIREQ
-PCIGNT
PAR
-SERR
A6
A3
C7
F10
D8
D10
-PCIRST
-REQ0
-REQ1
-REQ2
-REQ3
-REQ4
-PCIRST
-REQ0
-REQ1
-REQ2
-REQ3
-REQ4
E7
D7
E10
E8
E9
-GNT0
-GNT1
-GNT2
-GNT3
-GNT4
-GNT0
-GNT1
-GNT2
-GNT3
-GNT4
J4
G3
E4
C4
C_-BE0
C_-BE1
C_-BE2
C_-BE3
C_-BE0
C_-BE1
C_-BE2
C_-BE3
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_D16
A_D17
A_D18
A_D19
A_D20
A_D21
A_D22
A_D23
A_D24
A_D25
A_D26
A_D27
A_D28
A_D29
A_D30
A_D31
GTLVREFB
C103
.1u
A
VTT
R153
75 1%
GTLVREFA
VTTA
VTTB
GTLVREFA
GTLVREFB
CRESET
PCLKIN
HCLKIN
PWROK
*VSUS
*SUSTAT
B
M25
R143
8.2K
C
VTT
M24
F17
M23
E16
GTLVREFA
GTLVREFB
M26
-CRESET
B2
N23
NPCLK
HCLK
AF3
AA11
AA12
PW_GOOD
PW_GOOD
-SUSST
-SUSST
-CRESET
NPCLK
HCLK
VCC3_SB
AE3
VCCA
VCCA
VCCA
VCCA
WSC
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A[3..31]
R152
150 1%
C133
.1u
VT82C694X-A
HCLK
D
R116
150 1%
VCC3
TESTIN
N21
N22
V6
Y21
ADS
BNR
BPRI
HDBSY
DEFER
HDRDY
HIT
HITM
HLOCK
HREQ0
HREQ1
HREQ2
HREQ3
HREQ4
HTRDY
RS0
RS1
RS2
CPURST
BREQ0
VSSA
VSSA
VSSA
VSSA
K21
H24
H26
L23
J26
K23
L24
L22
K22
J22
J23
K24
K25
J25
H25
K26
L26
L25
B23
B26
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
-ADS
-BNR
-BPRI
-DBSY
-DEFER
-DRDY
-HIT
-HITM
-HLOCK
-HREQ0
-HREQ1
-HREQ2
-HREQ3
-HREQ4
-HTRDY
-RS0
-RS1
-RS2
-CPURST
-BREQ0
U19
FRAME
DEVSEL
IRDY
TRDY
STOP
PLOCK
PHOLD
PHLDA
PAR
SERR
G25
H22
G23
H23
G24
F26
G26
G22
F22
F23
F24
F25
E23
E26
E25
D25
D26
B25
C26
A25
C25
A24
D24
C23
B24
C24
A23
E22
D23
-ADS
-BNR
-BPRI
-DBSY
-DEFER
-DRDY
-HIT
-HITM
-HLOCK
-HREQ0
-HREQ1
-HREQ2
-HREQ3
-HREQ4
-HTRDY
-RS0
-RS1
-RS2
-CPURST
-BREQ0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
C
B22
D22
E21
A22
D21
C21
A21
C20
B21
E20
A20
E19
B20
E18
D20
D19
D18
C19
B19
A18
A19
B18
C17
E17
D17
B17
C16
A17
C15
B16
D16
A16
B15
A15
D14
D15
B13
C14
E14
D13
A13
D12
B12
B14
C13
E13
D11
A12
B11
A11
B7
C12
C8
B10
A10
A9
A7
E11
D9
C11
C10
B8
A8
B9
B1
G6
J6
F7
F9
L11
N11
M12
L13
L14
M15
L16
N16
F18
F20
G21
J21
C2
B
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A
D[0..63]
P22
N13
A14
M14
N14
E15
L15
N15
M16
C18
F19
F21
H21
H6
F6
C5
J3
A1
C22
J24
E3
M13
N12
L12
E12
M11
C9
F8
E24
A26
K1
N24
VTT
D[0..63]
TP1
*near to chip
D
VCC3
A[3..31]
Title
NORTH BRIDGE VT82C694A/X-A
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
3
of
20
1
2
3
MD[32..63]
4
MD[32..63]
VCC3
Y7
Y8
N7
P3
P7
Y3
AE23
AB15
AD9
R11
P12
T12
AB12
P13
R13
AF13
P14
R14
P15
T15
R16
AD18
AA19
AA6
AA8
AF26
P26
AB25
AB24
V24
AD22
R22
AA21
AF1
AF4
AE4
AF5
AD6
AE6
AB7
AC7
AF7
AB8
AB9
AC9
AE9
AB10
AC10
AF10
AD11
Y24
Y25
W23
W24
W26
W25
V26
U24
U23
T22
T23
T26
R24
R25
P23
N25
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
A
R207
330
A
U19B
R208
BSEL0
10K
*For 100/66 MHz selection
MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7
AE14
AC14
AA22
AA24
AD13
AC13
AC25
AB26
AD14
AE13
-SRASA
-SRASB
AF16
AA17
-SCASA
-SCASB
AF12
AB13
-SWEA
-SWEB
AE12
AC12
MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7
AF11
AD12
AA25
Y22
AE11
AA10
AA23
AA26
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
AC22
AF23
AE24
AD23
AC23
AF24
GCLKIN
GCLK
DCLKWR
TP3
TP4
TP5
GND
GND
ST0
ST1
ST2
PIPE
RBF
WBF
AD_STB0
AD_STB0
AD_STB1
AD_STB1
SB_STB
SB_STB
SRASA
SRASB
SCASA
SCASB
WEA
WEB
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
AGPREF
CKE0
CKE1
CKE2/CSA6
CKE3/CSA7
CKE4/CSB6
CKE5/CSB7
GCLKIN
GCLKOUT
DCLKO
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
DCLKO
TP2
GND
GND
GND
GND
GND
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
DQMB1
DQMB5
AC5
AE5
AB6
AC6
AF6
AD7
AE7
AC8
AD8
AF8
AE8
AF9
AD10
AE10
AB11
AC11
Y23
Y26
W22
V22
V23
V25
U22
U25
U26
T24
T25
U21
R23
R26
P24
P25
D
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GREQ
GGNT
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-DQMB1
-DQMB5
GFRAME
GDEVSEL
GIRDY
GTRDY
GSTOP
GPAR
CSB0
CSB1
CSB2
CSB3
CSB4
CSB5
DCLKWR
*GND
*GND
-SWEA
-SWEB
AE25
AD24
AD26
AC24
AC26
AB23
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE0
GC_BE1
GC_BE2
GC_BE3
NCOMP
PCOMP
-SCASA
-SCASB
-CSB0
-CSB1
-CSB2
-CSB3
-CSB4
-CSB5
CSA0
CSA1
CSA2
CSA3
CSA4
CSA5
*VSSQQ
AB5
AE1
AD3
AD2
AC2
AC3
AC1
AB4
AB1
AA5
AB2
AA4
AA2
AA1
AD1
W4
V2
V1
U4
U3
T4
W1
U1
T2
R5
U2
T1
R4
V3
R2
P6
R1
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GD16
GD17
GD18
GD19
GD20
GD21
GD22
GD23
GD24
GD25
GD26
GD27
GD28
GD29
GD30
GD31
GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GD16
GD17
GD18
GD19
GD20
GD21
GD22
GD23
GD24
GD25
GD26
GD27
GD28
GD29
GD30
GD31
AB3
Y4
V5
T3
-GBE0
-GBE1
-GBE2
-GBE3
-GBE0
-GBE1
-GBE2
-GBE3
W2
W5
W3
Y2
V4
Y1
-GFRAME
-GDEVSEL
-GIRDY
-GTRDY
-GSTOP
GPAR
-GFRAME
-GDEVSEL
-GIRDY
-GTRDY
-GSTOP
GPAR
L5
L3
-GREQ
-GGNT
-GREQ
-GGNT
L4
L1
M4
ST0
ST1
ST2
ST0
ST1
ST2
M3
N6
M6
-PIPE
-RBF
-WBF
-PIPE
-RBF
-WBF
Y5
U5
T6
T5
N3
M5
L2
M2
M1
N2
P4
P5
P2
P1
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
N1
AGPVREF
N5
N4
GCLKIN
GCLK
AB21
R212
330
R211
MAB8
10K (OPT)
BSEL1
*For 133/100MHz selection
PCI1 66/33 MHz support.
MAB5
R354
10K (OPT)
B
Install for CPU quick start.
VCC3
R210
MAB10
10K (OPT)
Install for IOQ = 1
R209
MAB11
10K (OPT)
C
* FOR TEST
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
AGPVREF
C135
.1u
AGPVREF
22
DCLKWR
AD5
C156
10P
R154
R155
DCLKO
22
22
GCLKO
GCLKO
DCLKO
DCLKWR
D
Title
VCC3
VDDQ
NORTH BRIDGE VT82C694A/X-B
R189
MD[0..31]
2
R166
VCC3
AD_STB0
-AD_STB0
AD_STB1
-AD_STB1
SB_STB
-SB_STB
AD25
60 1%
VDDQ
1
AD_STB0
-AD_STB0
AD_STB1
-AD_STB1
SB_STB
-SB_STB
BSEL0
VT82C694X-B
K7
U7
-SRASA
-SRASB
AB14
AF15
AE15
AC15
AD15
AE16
AE2
AF2
C
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-DQMB1
-DQMB5
-CSA0
-CSA1
-CSA2
-CSA3
-CSA4
-CSA5
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
*VCCQQ
*VCCQ
*GND
*GND
-CSB0
-CSB1
-CSB2
-CSB3
-CSB4
-CSB5
AD16
AC16
AD17
AB17
AE18
AD19
AB18
AB19
AF20
AC20
AB20
AE21
AD21
AF22
AE22
AD4
W6
AC4
Y6
-CSA0
-CSA1
-CSA2
-CSA3
-CSA4
-CSA5
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
*VCCQ
*VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
B
AF17
AB16
AE17
AC17
AF18
AE19
AF19
AC18
AC19
AE20
AD20
AF21
AC21
AF25
AB22
AA9
T16
AA18
AA20
V21
N26
AE26
P16
R15
AF14
T14
T13
R12
T11
P11
L7
R7
L6
R3
R6
AA3
AA7
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
MAB12
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
MD[0..31]
R197
60 1%
3
Size
C
Document Number
VT5228C (Prelimonary)
Date:
Rev
0.1
4
Sheet
4
of
20
1
2
3
4
U20
A
PD_A0
PD_A1
PD_A2
-PDCS_1
-PDCS_3
-DDACK_A
DDREQ_A
-DIOR_A
-DIOW_A
HDRDY_A
A_D[0..31]
B
C_-BE[0..3]
C
-FRAME
-IRDY
-TRDY
-STOP
-DEVSEL
-SERR
PAR
A_D18
-PCIREQ
-PCIGNT
-PCIRST
-INTR_A
-INTR_B
-INTR_C
-INTR_D
PD_A0
PD_A1
PD_A2
-PDCS_1
-PDCS_3
-DDACK_A
DDREQ_A
-DIOR_A
-DIOW_A
HDRDY_A
M17
M19
M18
L20
M16
M20
N19
N17
N18
N16
A_D0
A_D1
A_D2
A_D3
A_D4
A_D5
A_D6
A_D7
A_D8
A_D9
A_D10
A_D11
A_D12
A_D13
A_D14
A_D15
A_D16
A_D17
A_D18
A_D19
A_D20
A_D21
A_D22
A_D23
A_D24
A_D25
A_D26
A_D27
A_D28
A_D29
A_D30
A_D31
L17
L16
K20
K19
K18
K17
K16
J20
J18
J17
J16
H20
H19
H18
H17
H16
F16
E20
E19
E18
E17
D20
D19
D18
B20
A20
A19
B19
A18
B18
C18
A17
C_-BE0
C_-BE1
C_-BE2
C_-BE3
J19
G20
F17
C19
-FRAME
-IRDY
-TRDY
-STOP
-DEVSEL
-SERR
PAR
A_D18
-PCIREQ
-PCIGNT
-PCIRST
F18
F19
F20
G17
G16
G18
G19
C20
L18
L19
B16
-INTR_A
-INTR_B
-INTR_C
-INTR_D
A16
D17
C17
B17
E16
W5
VCC3_SB
R9
R10
PDA0
PDA1
PDA2
PDCS1
PDCS3
PDDACK
PDDREQ
PDIOR
PDIOW
PDRDY
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE0
C_BE1
C_BE2
C_BE3
FRAME
IRDY
TRDY
STOP
DEVSEL
SERR
PAR
IDSEL
REQ
GNT
PCIRST
*:VSUS
SDD0/BITCLK
*SDD1/SDIN
*SDD2/SDIN2
SDD3/SYNC
SDD4/SDOUT
SDD5/-ACRST
SDD6/JBY
SDD7/JBX
SDD8/JAY
SDD9/JAX
SDD10/JAB2
SDD11/JAB1
SDD12/JBB2
SDD13/JBB1
SDD14/MSO
SDD15/MSI
SDA0
SDA1
SDA2
SDCS1
SDCS3
SDDACK
SDDREQ
SDIOR
SDIOW
SDRDY
A20M
CPURST
FERR
IGNNE
INIT
INTR
NMI
SLP/GPO7
SMI
STPCLK
CPUSTP/GPO4
PCISTP/GPO5
CLKRUN
SPKR
GPIOA/GPIO8
GPIOD
*PWRGD
*SMBCLK
*SMBDATA
*GPO0
*SUSST1/GPO6
*SUSCLK
*EXTSMI
*RING/GPI7
*PME/GPI5/THRM
*BATLOW/GPI2
*PWRBTN
*RSMRST
*GPI1/IRQ8
*LID/APICREQ/GPI3
*SMBALT/GPI6
*SUSA/APICACK/GPO1
*SUSB/APICCS/GPO2
*SUSC
CX1
D8
CB47
D
.1u
10p
1N5819
D6
JBAT1
1
1N5819
2
V_BAT
Y6
3
R301
1K
CT49
C168
10u
.1u
R302
1K
VCC3
BAT1
H15
J15
K15
M15
N15
R7
R8
R11
R14
R57
R105
R99
R264
R265
R266
JBCY
JBCX
JACY
JACX
JAB2
JAB1
JBB2
JBB1
MSO
MSI
22
22
22
22
22
22
BITCLK
U19
V18
U20
U17
U18
V19
Y20
W19
W20
V20
SD_A0
SD_A1
SD_A2
-SDCS_1
-SDCS_3
-DDACK_B
DDREQ_B
-DIOR_B
-DIOW_B
HDRDY_B
Y7
V8
V7
Y8
T6
W8
U7
T7
U6
W7
-A20M_
-A20M_
-FERR
-IGNNE_
-CPUINIT
INTR_
NMI_
-SLP
-SMI
-STPCLK
-FERR
-IGNNE_
-CPUINIT
INTR_
NMI_
-SLP
-SMI
-STPCLK
Y12
V12
R267
R285
W12
V5
-CLKRUN
SPEAK_
VCC3
SDIN
SDIN2
SYNC
SDOUT
-ACRST
JBCY
JBCX
JACY
JACX
JAB2
JAB1
JBB2
JBB1
MSO
MSI
-A20M_
R340
4.7K
-IGNNE_
R318
4.7K
INTR_
R317
4.7K
NMI_
R339
4.7K
-PCIGNT
R232
10K
-PCIREQ
R235
10K
-CLKRUN
R284
100
VCC3_SB
VCC2_5
-SUSST
R338
SUS_CLK
-CPUINIT
SD_A0
SD_A1
SD_A2
-SDCS_1
-SDCS_3
-DDACK_B
DDREQ_B
-DIOR_B
-DIOW_B
HDRDY_B
R319
-FERR
R342
4.7K
-STPCLK
R341
4.7K
-SMI
R320
4.7K
-SLP
R321
R311
-EXTSMI
4.7K
10K
10K
R335
A
10K
-BATLOW
R309
10K
-SMBALT
R336
10K
-SUSA
R310
10K
-SUSB
R337
10K
-RI
R304
10K
4.7K
PD_80P
R306
SD_80P
10K
R312
10K
I2CD1
R315
4.7K
I2CD2
R314
4.7K
J2
VCC3_SB
1
SDIN
2
SDIN_A
J1
R308
10K
1
2
3
4
BITCLK_A
R307
BITCLK
-PME_
-PME
VCC3
BITCLK_R
B
0 (OPT)
10K
10K
J2
J1
AC97
1-2
1-2
MC97
OPEN
3-4
AC97
+
MC97
1-2
AMR
OPEN
VCC3
VCC3_SB
T14
U8
W6
U9
T9
R263
10K
R316
GPIOD
PW_GOOD
I2CD1
I2CD2
10K
R305
4.7K
-PWRBTN
PW_GOOD
I2CD1
I2CD2
T8
V10
T10
R313
10K
-SUSST
SUS_CLK
Y10
V11
T11
U11
Y11
V6
W11
U10
W10
-EXTSMI
-RI
-PME_
-BATLOW
-PWRBTN
-RSMRST
PD_80P
SD_80P
-SMBALT
V9
W9
Y9
-SUSA
-SUSB
-SUSC
R334
C174
PW_BN
68
1-2
3-4
.1u
VCC3_SB
-SUSST
3-4
-EXTSMI
-RI
J5
-RSMRST
PD_80P
SD_80P
1
2
3
4
5
IR
IRRX
IRRX
IRTX
IRTX
C
-SUSB
-SUSC
+12V
GND
GND
GND
GND
GND
PINTA
PINTB
PINTC
PINTD
IN12
IN5
PCICLK
IN2A
RTCX1
IN2B
X3
32.768KHz
VCC3_SB
W18
V17
Y17
V16
Y16
U15
W15
U14
Y15
V15
T15
W16
U16
W17
Y18
Y19
CHAS/GPIOC/GPIO10
RTCX2
TSEN1
VCCSUS
VCCSUS
VREF
VBAT
TSEN2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FAN1
FAN2/GPIOB/GPIO9
VCC3
F15
G15
L15
P15
R15
VCC3
SPEAK_
R290
10K
VCCP
R295
53K 1%
C170
.1u
R292
16K 1%
R268
2K
NOTE: SECOND IDE BUS IS
ASSIGNED TO AUDIO/GAME
VCC2_5
C169
.1u
R294
Y14
10K 1%
W14
U13
CM41
1u
V13
CM43
1u
V14
R291
W13
10K 1%
SPEAK_
0(OPT)
L27
RT1
R121
10K 1%
R224
10K 1%
T13
Y13
103JT-025
103JT-025
CPUFAN1
CPUFAN1
U12
CPUFAN2
CPUFAN2
HM_GND
2
4
SPEAK
U12
* Isolated from AMR,avoied
strapping error.
NC7SZ125
L33
RT2
T12
VCC3
R293
t
Y5
10p
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
t
1
SPCLK
2
SPCLK
CX2
P16
P18
P20
R17
R19
T16
T18
T20
T19
T17
R20
R18
R16
P19
P17
N20
5
1
PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_D[0..15]
D
Place RT1 under CPU
VCC3
VCCHWM
GNDHWM
R12
R13
CB46
CT50
.1u
10u
L34
FB
L35
FB
Place RT2 near NB
Title
SOUTH BRIDGE VT82C686A-A
VT82C686A-A
Size
C
Document Number
Date:
Rev
0.1
HM_GND
1
2
3
4
Sheet
5
of
20
1
2
SA[0..23]
SD[0..15]
B
-DACK0
-DACK1
-DACK3
-DACK5
-DACK6
-DACK7
DREQ0
DREQ1
DREQ3
DREQ5
DREQ6
DREQ7
AEN
BALE
-SBHE
-REFRESH
-IOR
-IOW
-MEMR
-MEMW
-SMEMR
-SMEMW
-IOCS16
-MEMCS16
IOCHRDY
-IOCHCK
TC
SIO_RES
SIO_OSC
SYS_CLK
IRRX
IRTX
VCC3
IRQ3
IRQ4
IRQ5
R126
10K
R127
2
0 (OPT)
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
W1
V2
V1
U3
U2
U1
T4
T3
T2
T1
R5
R4
R3
R2
R1
P5
P4
P3
K2
K1
J5
J4
J3
J2
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
Y1
Y2
W2
Y3
W3
V3
Y4
W4
L5
M2
M4
N1
N3
N5
P1
P2
-DACK0
-DACK1
-DACK3
-DACK5
-DACK6
-DACK7
L2
E1
D2
L4
M3
N2
DREQ0
DREQ1
DREQ3
DREQ5
DREQ6
DREQ7
L3
E2
D3
M1
M5
N4
AEN
BALE
-SBHE
-REFRESH
-IOR
-IOW
-MEMR
-MEMW
-SMEMR
-SMEMW
-IOCS16
-MEMCS16
IOCHRDY
-IOCHCK
TC
B2
H2
F2
E3
D1
C2
U4
V4
A1
B1
F3
F1
A2
F4
H1
J1
SIO_OSC
R128
33
E4
H5
IRRX
IRTX
D12
E12
IRQ3
IRQ4
IRQ5
G4
G3
G2
G1
F5
H4
K3
K4
L1
K5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
SLP1
T5
U5
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
LA20
LA21
LA22
LA23
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
DACK0
DACK1
DACK3
DACK5
DACK6
DACK7
DRQ0
DRQ1
DRQ3
DRQ5
DRQ6
DRQ7
AEN
BALE
SBHE
REFRESH
IOR
IOW
MEMR
MEMW
SMEMR
SMEMW
IOCS16
MEMCS16
IOCHRDY
IOCHK/GPI0
TC
RSTDRV
OSC
BCLK
IRRX/GPO15
IRTX/GPO14
IRQ3
IRQ4
IRQ5
IRQ6/SLPBTN
IRQ7
IRQ9
IRQ10
IRQ11
IRQ14
IRQ15
XDIR/PCS0/GPO12
XOE/GPO13
1
D
4
U20B
A
C
3
VCC3
F7
F10
F12
F13
F14
H6
J6
K6
M6
N6
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PRD0
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7
ACK
BUSY
PE
SLCT
ERROR
PINIT
AUTOFD
SLCTIN
STROBE
TXD1
DTR1
RTS1
CTS1
DSR1
DCD1
RI1
RXD1
TXD2
DTR2
RTS2
CTS2
DSR2
DCD2
RI2
RXD2
VCCUSB
B15
D15
A14
B14
C14
D14
E14
A13
P_PRD0
P_PRD1
P_PRD2
P_PRD3
P_PRD4
P_PRD5
P_PRD6
P_PRD7
USBCLK
USBP0+
USBP0USBP1+
USBP1DRQ2/OC1/SERIRQ/GPIOE
DACK2/OC0/GPIOF
USBP2+
USBP2USBP3+
USBP3KBCK
KBDT/KBRC
MSCK/IRQ1
MSDT/IRQ12
ROMCS
DRVDEN0
DRVDEN1
INDEX
MTR0
DS1
DS0
MTR1
DIR
STEP
WDATA
WGATE
TRAK00
WRTPRT
RDATA
HDSEL
DSKCHG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FS1
FUSE
.001u
A11
D11
B11
C11
C12
A12
E11
B12
TXD1
DTR1
RTS1
CTS1
DSR1
DCD1
RI1
RXD1
TXD1
DTR1
RTS1
CTS1
DSR1
DCD1
RI1
RXD1
D10
B9
E10
A9
C10
A10
C9
B10
TXD2
DTR2
RTS2
CTS2
DSR2
DCD2
RI2
RXD2
TXD2
DTR2
RTS2
CTS2
DSR2
DCD2
RI2
RXD2
F9
USB_VCC
L17
FB
CM3
CM4
1u
1u
OVER_C1
470K
R54
560K
L16
FB
OVER_C1
C80
.001u
A
USB1
USBDT0USBDT0+
R12
R14
C21
USB_D0+
0 (OPT)
5
6
7
8
0
0
1
2
3
4
R13
R15
USBDT1USBDT1+
0
0
C23
C22
R22
CT10
C16
C15
CT9
100uF
.1u
.1u
100uF
.1u(OPT)
.1u(OPT)
.1u(OPT)
L2
C24
.1u(OPT)
R43
USB_D1+
FB
R23
0 (OPT)
USB_GND1
USB_D0-
R44
0 (OPT)
USB_D10 (OPT)
USB_DT0USB_DT0+
R25
R27
27
27
USBDT0USBDT0+
USB_DT1USB_DT1+
R46
R48
27
27
USBDT1USBDT1+
VCC3
L32
FB
L30
FB
CP4
CP3
CP2
CP1
47p
47p
47p
47p
R47
15K
R45
15K
R26
15K
R24
15K
B
CT41
F8
.1u
USB_GND
C3
A3
B3
C4
D4
H3
G5
USBCLK
USB_DT0+
USB_DT0USB_DT1+
USB_DT1OVER_C1
OVER_C0
USBCLK
KB_CLK
KB_DATA
MS_CLK
KB_CLK
KB_DATA
MS_CLK
10u
A4
B4
B5
E6
E5
A5
D5
C5
C1
-ROMCS
D9
D6
D7
E9
A8
B8
C8
D8
E8
A7
B7
E7
A6
B6
C7
C6
F6
F11
G6
J9
J10
J11
J12
K9
K10
K11
K12
L6
L9
L10
L11
L12
M9
M10
M11
M12
P6
R6
R125
0(OPT)
J4
-ROMCS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
MS_DATA
3
IRQ12
2
VCC3
R225
4.7K
*Set INIT low active.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
C
FDD1
RN23
1K 8P4R
7
5
3
1
R200
VCC
8
6
4
2
1K
D
Title
SOUTH BRIDGE VT82C686A-B
VT82C686A-B
1
R53
470K
R42
560K
C72
P_ACK
P_BUSY
P_PE
P_SLCT
P_ERROR
P_INIT
P_AUTOFD
P_SLCTIN
P_STROBE
FS3
FUSE
R41
OVER_C0
OVER_C0
B13
C13
D13
E13
A15
C15
C16
E15
D16
CB19
GNDUSB
P_PRD[0..7]
2
3
Size
C
Document Number
VT5228C (Prelimonary)
Date:
Rev
0.1
4
Sheet
6
of
20
1
2
3
4
VCC2_5
A
1
3
5
7
A
RN31
10K 8P4R
1
3
5
7
-A20M
U11
2
4
6
8
JFREQ1
2
4
6
8
2
4
6
8
11
13
15
17
RATIO0
RATIO1
RATIO2
RATIO3
-A20M_
-IGNNE_
INTR_
NMI_
VCC3
1
19
R298
10K
A0
A1
A2
A3
A4
A5
A6
A7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
18
16
14
12
9
7
5
3
-IGNNE
INTR
NMI
VCC2_5
OE0
OE1
V
20
LV244A
Fraction
/Ratio
2
3
4
5
5/2
7/2
9/2
11/2
-CRESET
1
U18A
2
F04
B
R299
1K
JFREQ1
1-2,3-4,5-6,7-8
1-2,5-6,7-8
3-4,5-6,7-8
5-6,7-8
1-2,3-4,7-8
1-2,7-8
3-4,7-8
7-8
B
R324
2K
U21
SD0
SD1
SD2
SD3
BSEL0
R352
10K
2
C
JA
11
1
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
2
5
6
9
12
15
16
19
RATIO0
RATIO1
RATIO2
RATIO3
C
CLK
CLR
1
GPIOD
3
4
7
8
13
14
17
18
74F273
C176
10u
* Auto mode:
Remove the BSEL0 and BSEL1 jumper,
install JA jumper.
* OPTION
D10
1N4148
-SERR
RST_SW
C177
47u
1
5
D
4
D
2
U22
NC7SZ125
For jumper-less circuit
C178
47u
Title
USB2,3 / FREQ. RATIO
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
7
of
20
1
2
3
4
MD[0..63]
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
A
B
QS0/DQS0
RFU/DQS1
QS2/DQS2
RFU/DQS3
QS1/DQS4
RFU/DQS5
QS3/DQS6
RFU/DQS7
RFU/DQS8
DIMM1
DU/OE0
DU/OE2
RAS0/S0
RAS1/S1
RAS2/S2
RAS3/S3
CAS0/DQMB0
CAS1/DQMB1
CAS2/DQMB2
CAS3/DQMB3
CAS4/DQMB4
CAS5/DQMB5
CAS6/DQMB6
CAS7/DQMB7
WE0
WE2/DU
DU/CAS
DU/RAS
31
44
30
114
45
129
28
29
46
47
112
113
130
131
27
48
111
115
-CSA0
-CSA1
-CSB0
-CSB1
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-SWEA
-SCASA
-SRASA
-CSA0
-CSA1
-CSB0
-CSB1
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-SWEA
-SCASA
-SRASA
DIMM_16M*64
24
25
50
51
108
109
135
81
134
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
NC
NC
NC
REGE
21
22
52
53
105
106
136
137
61
80
145
164
147
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
6
18
26
40
41
49
59
73
84
90
102
110
124
133
143
157
168
I2CD2
I2CD1
B
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
I2CD2
I2CD1
CKE0
CKE1
DU/VREF
DU/VREF
CK0
CK1
CK2
CK3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 (AP)
A11 (BS0)
A12 (BS1)
A13
DU/A14
DU/A15
128
63
62
146
42
125
79
163
33
117
34
118
35
119
36
120
37
121
38
122
39
123
126
132
SDA
SCL
SA0
SA1
SA2
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
82
83
165
166
167
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
A
V_DIM
CKE_0
CKE_1
V_DIM
MPD[0..7]
DCLK5
DCLK6
DCLK7
DCLK8
V_DIM
V_DIM
QS0/DQS0
RFU/DQS1
QS2/DQS2
RFU/DQS3
QS1/DQS4
RFU/DQS5
QS3/DQS6
RFU/DQS7
RFU/DQS8
24
25
50
51
108
109
135
81
134
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
NC
NC
NC
REGE
21
22
52
53
105
106
136
137
61
80
145
164
147
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
6
18
26
40
41
49
59
73
84
90
102
110
124
133
143
157
168
CKE0
CKE1
DU/VREF
DU/VREF
CK0
CK1
CK2
CK3
I2CD2
I2CD1
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
I2CD2
I2CD1
128
63
62
146
42
125
79
163
82
83
165
166
167
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 (AP)
A11 (BS0)
A12 (BS1)
A13
DU/A14
DU/A15
SDA
SCL
SA0
SA1
SA2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
33
117
34
118
35
119
36
120
37
121
38
122
39
123
126
132
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14
C
DIMM2
DU/OE0
DU/OE2
RAS0/S0
RAS1/S1
RAS2/S2
RAS3/S3
CAS0/DQMB0
CAS1/DQMB1
CAS2/DQMB2
CAS3/DQMB3
CAS4/DQMB4
CAS5/DQMB5
CAS6/DQMB6
CAS7/DQMB7
WE0
WE2/DU
DU/CAS
DU/RAS
31
44
30
114
45
129
28
29
46
47
112
113
130
131
27
48
111
115
-CSA2
-CSA3
-CSB2
-CSB3
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-SWEA
-SCASA
-SRASA
-CSA2
-CSA3
-CSB2
-CSB3
-DQMA0
-DQMA1
-DQMA2
-DQMA3
-DQMA4
-DQMA5
-DQMA6
-DQMA7
-SWEA
C
-SCASA
-SRASA
DIMM_16M*64
V_DIM
CKE_2
CKE_3
DCLK1
DCLK2
DCLK3
DCLK4
D
D
Title
SDRAM
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
8
of
20
1
2
3
4
MD[0..63]
2
3
4
5
7
8
9
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
A
QS0/DQS0
RFU/DQS1
QS2/DQS2
RFU/DQS3
QS1/DQS4
RFU/DQS5
QS3/DQS6
RFU/DQS7
RFU/DQS8
DU/OE0
DU/OE2
RAS0/S0
RAS1/S1
RAS2/S2
RAS3/S3
CAS0/DQMB0
CAS1/DQMB1
CAS2/DQMB2
CAS3/DQMB3
CAS4/DQMB4
CAS5/DQMB5
CAS6/DQMB6
CAS7/DQMB7
WE0
WE2/DU
DU/CAS
DU/RAS
31
44
30
114
45
129
28
29
46
47
112
113
130
131
27
48
111
115
-CSA4
-CSA5
-CSB4
-CSB5
-DQMA0
-DQMB1
-DQMA2
-DQMA3
-DQMA4
-DQMB5
-DQMA6
-DQMA7
-SWEB
-CSA4
-CSA5
-CSB4
-CSB5
-DQMA0
-DQMB1
-DQMA2
-DQMA3
-DQMA4
-DQMB5
-DQMA6
-DQMA7
-SWEB
-SCASB
-SRASB
-SCASB
-SRASB
DIMM_16M*64
24
25
50
51
108
109
135
81
134
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
NC
NC
NC
REGE
0 (OPT)
21
22
52
53
105
106
136
137
61
80
145
164
147
R206
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0 (OPT)
6
18
26
40
41
49
59
73
84
90
102
110
124
133
143
157
168
R205
82
83
165
166
167
MAB14
CKE0
CKE1
DU/VREF
DU/VREF
CK0
CK1
CK2
CK3
*For VT82C694X
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 (AP)
A11 (BS0)
A12 (BS1)
A13
DU/A14
DU/A15
128
63
62
146
42
125
79
163
33
117
34
118
35
119
36
120
37
121
38
122
39
123
126
132
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
SDA
SCL
SA0
SA1
SA2
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
DIMM3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
A
*For VT82C694A
MAA14
I2CD2
I2CD1
V_DIM
B
MPD7
MPD6
MPD5
MPD4
MPD3
MPD2
MPD1
MPD0
I2CD2
I2CD1
V_DIM
CKE_4
CKE_5
V_DIM
B
MPD[0..7]
DCLK9
DCLK10
DCLK11
DCLK12
D1
1N4148
R328
R344
B
Q15
-RI
MMBT3904
D9
R329
2K
1N4148
C
-RI
1K
10K
C175
10u
-XRI1
-XRI1
-XRI2
-XRI2
D2
1N4148
E
RING IN
JWOL
5V_SB 1
R343
B
C
2
3
Q14
MMBT3904
C
100
LAN
WAKE UP
E
5V_SB
R327
B
Q13
C
WAKE_CONN
10K
MMBT3904
R326
100K
JWOM
1
2
C
E
3
C172
1000p
WAKE_CONN
MODEM
WAKE UP
D
D
Title
SDRAM/LAN,MODEM WAKE UP FUNCTION
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
9
of
20
1
2
3
4
PCI1
-12V
VCC3
-INTR_C
-INTR_A
-INTR_C
-INTR_A
A
PCICLK1
-REQ0
-REQ0
A_D31
A_D29
A_D31
A_D29
A_D27
A_D25
A_D27
A_D25
C_-BE3
A_D23
C_-BE3
A_D23
A_D21
A_D19
A_D21
A_D19
A_D17
C_-BE2
A_D17
C_-BE2
-IRDY
-IRDY
B
-DEVSEL
-DEVSEL
-PLOCK
-PERR
-PLOCK
-PERR
-SERR
-SERR
C_-BE1
A_D14
C_-BE1
A_D14
A_D12
A_D10
A_D12
A_D10
A_D8
A_D7
A_D8
A_D7
A_D5
A_D3
A_D5
A_D3
A_D1
A_D1
-P1ACK64
-P1ACK64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
+12V
PCI2
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+5V(I/O)
RESERVED
GND
GND
3.3VAUX
RST#
+5V(I/O)
GNT
GND
PME#
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V
C/BE#0
+3.3V
AD6
AD4
GND
AD2
AD0
+5V(I/O)
REQ64#
+5V
+5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
+12V
-12V
VCC3
VCC3
-INTR_B
-INTR_D
-INTR_B
-INTR_D
-INTR_D
-INTR_B
VCC3_SB
-PCIRST
-PCIRST
PCICLK2
-GNT0
-GNT0
-PME
A_D30
-PME
A_D30
A_D28
A_D26
A_D28
A_D26
A_D24
A_D19
A_D24
A_D19
A_D22
A_D20
A_D22
A_D20
A_D18
A_D16
A_D18
A_D16
-FRAME
-FRAME
-TRDY
-TRDY
-REQ1
-STOP
-REQ1
A_D31
A_D29
A_D27
A_D25
C_-BE3
A_D23
A_D21
A_D19
A_D17
C_-BE2
-IRDY
-DEVSEL
-STOP
-PLOCK
-PERR
-SERR
PAR
A_D15
PAR
A_D15
A_D13
A_D11
A_D13
A_D11
A_D9
A_D9
C_-BE0
C_-BE0
A_D6
A_D4
A_D6
A_D4
A_D2
A_D0
A_D2
A_D0
-P1REQ64
C_-BE1
A_D14
A_D12
A_D10
100
102
104
106
108
110
112
114
116
118
120
A_D8
A_D7
A_D5
A_D3
A_D1
-P1REQ64
-P2ACK64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
-P2ACK64
PCI_CON_32BIT
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT#1
RESERVED
PRSNT#2
GND
GND
RESERVED
GND
CLK
GND
REQ#
+5V(I/O)
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE#3
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE#2
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE#1
AD14
GND
AD12
AD10
GND
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+5V(I/O)
RESERVED
GND
GND
3.3VAUX
RST#
+5V(I/O)
GNT
GND
PME#
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V(I/O)
ACK64#
+5V
+5V
C/BE#0
+3.3V
AD6
AD4
GND
AD2
AD0
+5V(I/O)
REQ64#
+5V
+5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
VCC3
99
101
103
105
107
109
111
113
115
117
119
-INTR_C
-INTR_A
A
VCC3_SB
-PCIRST
-GNT1
-GNT1
-PME
A_D30
-PME
A_D28
A_D26
A_D24
A_D20
A_D20
A_D22
A_D20
A_D18
A_D16
-FRAME
-TRDY
B
-STOP
PAR
A_D15
A_D13
A_D11
A_D9
C_-BE0
A_D6
A_D4
A_D2
A_D0
-P2REQ64
-P2REQ64
PCI_CON_32BIT
C
C
-TRDY
-DEVSEL
-STOP
-SERR
1
3
5
7
-GNT0
-GNT1
-GNT2
-GNT3
-GNT4
RN20
2
4
6
8
-GNT0
-GNT1
-GNT2
-GNT3
-GNT4
R79
R97
R73
R83
R77
8.2K
8.2K
8.2K
8.2K
8.2K
-P1REQ64
-P2REQ64
-P1REQ64
-P2REQ64
R193
R183
-REQ2
-REQ0
-REQ3
-REQ1
-REQ4
2.2K
2.2K
-REQ2
-REQ0
-REQ3
-REQ1
-REQ4
R72
R84
R78
R98
R74
2.2K
2.2K
2.2K
2.2K
2.2K
4.7K 8P4R
D
-PERR
-PLOCK
-FRAME
-IRDY
1
3
5
7
-INTR_D
-INTR_C
RN21
2
4
6
8
R85
R80
2.2K
2.2K
-P1ACK64
VCC3
-P2ACK64
R182
2.2K
R194
2.2K
D
-P1ACK64
-P2ACK64
4.7K 8P4R
-INTR_B
-INTR_A
1
R81
R86
2.2K
2.2K
Title
PCI SLOT
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
10
of
20
1
2
3
4
VDDQ
VCC3
-GDEVSEL
R168
-GSTOP
R180
8.2K
-GSERR
R186
8.2K
-GPERR
R181
8.2K
USB_D0+
GPAR
R185
8.2K
-RBF
R119
8.2K
-INTR_B
GCLKO
-GREQ
-PIPE
R111
8.2K
-WBF
R120
8.2K
-GREQ
R109
8.2K
R104
R124
8.2K
AD_STB1
R144
8.2K
AD_STB0
R192
8.2K
-GFRAME
R156
8.2K
-GTRDY
R167
8.2K
R158
-GIRDY
ST0
ST2
-RBF
SBA0
8.2K
SB_STB
SBA2
SB_STB
SBA4
SBA6
GD31
GD29
8.2K
GD27
GD25
VDDQ
C158
.1u
C125
.1u
AD_STB1
GD23
B
C106
.1u
C136
.1u
C153
.1u
C108
GD21
GD19
GD17
-GBE2
-GIRDY
.1u
-SB_STB
R131
8.2K
-AD_STB1
R157
8.2K
-AD_STB0
R187
8.2K
-GDEVSEL
GD14
GD12
GD10
GD8
VDDQ
C161
AD_STB0
GD7
560P
R198
1K 1%
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
USB_D0+
-INTR_B
GCLKO
-GREQ
ST0
ST2
-RBF
SBA0
SBA2
SB_STB
SBA4
SBA6
GD31
GD29
GD27
GD25
AD_STB1
GD23
GD21
GD19
GD17
-GBE2
-GIRDY
-GDEVSEL
-GPERR
-GSERR
-GBE1
C
VCC3
R103
10K
+12V
AGP1
A
-GGNT
VDDQ
VDDQ
8.2K
GD5
GD3
R214
75 1%
GD1
AGP_VREF
-GSERR
-GBE1
GD14
GD12
GD10
GD8
AD_STB0
GD7
GD5
GD3
GD1
OVRCNT#
+5V
+5V
USB+
GND
INTB#
CLK
REQ#
VCC3.3
ST0
ST2
RBF#
GND
RESERVED
SBA0
VCC3.3
SBA2
SB_STB
GND
SBA4
SBA6
RESERVED
GND
RESERVED
VCC3.3
AD31
AD29
VCC3.3
AD27
AD25
GND
AD_STB1
AD23
VDDQ
AD21
AD19
GND
AD17
C/BE#2
VDDQ
IRDY#
RESERVED
GND
RESERVED
VCC3.3
DEVEL#
VDDQ
PERR#
GND
SERR#
C/BE1#
VDDQ
AD14
AD12
GND
AD10
AD8
VDDQ
AD_STB0
AD7
GND
AD5
AD3
VDDQ
AD1
RESERVED
+12V
TYPEDET#
RESERVED
USBGND
INTA#
RST#
GNT#
VCC3.3
ST1
RESERVED
PIPE#
GND
WBF#
SBA1
VCC3.3
SBA3
SB_STB#
GND
SBA5
SBA7
RESERVED
GND
RESERVED
VCC3.3
AD30
AD28
VCC3.3
AD26
AD24
GND
AD_STB1#
C/BE3#
VDDQ
AD22
AD20
GND
AD18
AD16
VDDQ
FRAME#
RESERVED
GND
RESERVED
VCC3.3
TRDY#
STOP#
PME#
GND
PAR
AD15
VDDQ
AD13
AD11
GND
AD9
C/BE0#
VDDQ
AD_STB0#
AD6
GND
AD4
AD2
VDDQ
AD0
RESERVED
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
-TYPEDET
USB_D0-
USB_D0-
-INTR_A
-PCIRST
-GGNT
-INTR_A
-PCIRST
-GGNT
ST1
-PIPE
-WBF
SBA1
SBA3
-SB_STB
A
ST1
-PIPE
-WBF
SBA1
VCC3
R136
0 (OPT)
SBA5
SBA7
SBA5
SBA7
R123
0 (OPT)
R110
0 (OPT)
GD30
GD28
GD30
GD28
R135
0 (OPT)
GD26
GD24
GD26
GD24
-AD_STB1
-GBE3
-AD_STB1
-GBE3
GD22
GD20
GD22
GD20
GD18
GD16
GD18
GD16
-GFRAME
-GTRDY
-GSTOP
B
-GFRAME
R190
VREF_2X
0 (OPT)
AGPVREF
-GTRDY
-GSTOP
GPAR
GD15
GPAR
GD15
GD13
GD11
GD13
GD11
For AGP 2X mode only
GD9
-GBE0
GD9
-GBE0
-AD_STB0
GD6
-AD_STB0
GD6
GD4
GD2
GD4
GD2
GD0
VREF_4X
GD0
VCC3
C
R191
150 1%
AGP_SLOT_UNIVERSAL
R213
1K 1%
VDDQ
SBA3
-SB_STB
R199
75 1%
VREF_2X
C160
R196
100 1%
C157
.1u
560P
VCC3
U7
C120
.1u
2
3
-TYPEDET
NC
TYPEDET#
PGND
GND
VOSENSE
12V
DH
VDDQ
C162
.1u
7
+12V
CT46
1000u/6.3V
U9
Q10
NDP6030L
G
5
3
U18B
4
VDDQ
L31
SC1105
F04
4uH
1
2
1
G2
S2
D2
D2
G1
S1
D1
D1
5
6
VREF_2X
7
8
VREF_4X
C152
.1u
NDS8936
CT40
2
D
4
3
-TYPEDET
6
S
4
VCC
8
D
1
CT39
CT45
AGPVREF
D
3
1000u
D4
BYV118
Title
AGP SLOT & AGP 2X/4X MODE OPTION CIRCUIT
For AGP 2X/4X mode
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
11
of
20
1
2
3
4
SL1
RES_DRV
IRQ9
RES_DRV
IRQ9
DREQ2
-5V
-12V
-0WS
+12V
A
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REFRESH
SYS_CLK
IRQ7
IRQ5
IRQ4
IRQ3
TC
BALE
ISA_OSC
B
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DREQ3
-DACK1
DREQ1
-REFRESH
SYS_CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
TC
BALE
ISA_OSC
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DREQ0
-DACK5
DREQ5
-DACK6
DREQ6
-DACK7
DREQ7
-MASTER
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
-IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-SBHE
SA23
SA22
SA21
SA20
SA19
SA18
SA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
-SBHE
SA23
SA22
SA21
SA20
SA19
SA18
SA17
-MEMR
-MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
A
SA14
SA15
SA12
SA13
SA11
SA10
SA9
IRQ7
SA7
SA6
SA5
SA4
RN14
4.7K 8P4R
RN15
4.7K 8P4R
RN17
4.7K 8P4R
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
1
3
5
7
2
4
6
8
-REFRESH
R115
-MEMCS16
R170
330
-IOCS16
R159
330
-MASTER
R239
330
IOCHRDY
SA3
SA2
SA1
SA0
SA16
SA22
SA23
SA21
SA20
SA17
SA19
SA18
RN18
4.7K 8P4R
RN19
4.7K 8P4R
RN22
4.7K 8P4R
-0WS
330
R88
1K
R75
1K
4.7K
R169
-SBHE
B
SL2
SD4
SD5
SD6
SD7
SD3
SD2
SD1
SD0
C
RN1
1
3
5
7
1
3
5
7
RN7
4.7K 8P4R
2
4
6
8
2
4
6
8
RN13
1
3
5
7
4.7K 8P4R
2
4
6
8
-IOCHCK
R21
4.7K
-MEMW
R217
4.7K
-MEMR
R216
4.7K
IRQ10
IRQ11
IRQ12
IRQ5
4.7K 8P4R
IRQ9
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
IRQ4
SA8
IRQ5
IRQ6
IRQ3
IRQ12
D
R219
R220
R221
R223
R227
R228
R240
R238
RN16
4.7K 8P4R
7
5
3
1
R137
R195
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
DREQ0
R215
4.7K
DREQ5
R218
4.7K
DREQ6
R222
4.7K
DREQ7
R226
4.7K
DREQ2
DREQ1
DREQ3
8
6
4
2
R68
R114
R102
IRQ11
R188
IRQ10
R184
4.7K
4.7K
4.7K
TC
4.7K
R52
IRQ9
-SMEMW
-SMEMR
-IOW
-IOR
C154
68p
C155
68p
C159
68p
C107
68p
C79
68p
C
4.7K
4.7K
C121
68p
4.7K
4.7K
D
Title
ISA SLOT
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
12
of
20
1
2
R345
SIO_RES
SIO_RES
PW_LED
3
9
U18D
8
11
F04
U18E
10
300
A
U18C
6
5
33
R325
4
RES_DRV
F04
R323
A
-IDERST
33
F04
PW_BN
PW_BN
PW-BT
-EXTSMI
-EXTSMI
EXTSMI
R333
100
SPEAK
22
R332
C
2
4
6
8
10
12
14
16
18
20
HD_LED1
R330
HD-LED
1K
RST_SW
R331
C173
.1uF
BQ16
3904
SPEAK
2K
E
PANEL1
1
3
5
7
9
11
13
15
17
19
PW_LED
PW-LED
RESET
IDE1
B
PD_D[0..15]
SD[0..7]
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
-ROMCS
-MEMR
-MEMW
C
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
-ROMCS
-MEMR
-MEMW
22
24
31
U17
FROM-128K*8
13
A0
D0
14
A1
D1
15
A2
D2 17
A3
D3 18
A4
D4
19
A5
D5 20
A6
D6 21
A7
D7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
CE
OE
WE
VP
PD_D7
PD_D8
PD_D6
PD_D9
PD_D0
PD_D14
PD_D12
PD_D3
PD_D10
PD_D4
PD_D11
PD_D5
PD_D15
PD_D2
PD_D13
PD_D1
PD_D7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
R262
10K
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
PDD7
PDD8
PDD6
PDD9
PDD0
PDD14
PDD12
PDD3
PDD10
PDD4
PDD11
PDD5
PDD15
PDD2
PDD13
PDD1
RN29
33 8P4R
R279
5.6K
RN26
33 8P4R
RN27
33 8P4R
R276
1K
DDREQA
-DIOWA
-DIORA
HDRDYA
-DDACKA
RN24
33 8P4R
IRQ14
R273
R272
-DIOW_A
-DIOR_A
-DDACK_A
HDRDY_A
DDREQ_A
1
R243
R241
R234
33
33
33
R231
R242
82
82
82
10K
PDA1
PDA0
-PDCS1
-DIOWA
-DIORA
-DDACKA
R271
4.7K
HDRDYA
DDREQA
-DASP0
R300
4.7K
R236
R229
-PDCS_1
-PDCS_3
33
33
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
-IDERST
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
-PDCS1
-PDCS3
-DASP1
D5
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA2
-PDCS3
PD_80P
1N4148
HD_LED1
D7
C
1N4148
IDE2
SA[0..15]
SA3
SA2
SA1
SA0
SA7
SA6
SA5
SA4
SA11
SA10
SA9
SA8
SA15
SA14
SA13
SA12
SA7
R256
10K
D
SD_A2
SD_A1
SD_A0
PD_A2
PD_A1
PD_A0
SD_A2
SD_A1
SD_A0
PD_A2
PD_A1
PD_A0
R260
R281
R259
R233
R237
R230
33
33
33
33
33
33
SDA2
SDA1
SDA0
-DDACK_B
-DIOW_B
-DIOR_B
HDRDY_B
DDREQ_B
PDA2
PDA1
PDA0
7
5
3
1
7
5
3
1
1
3
5
7
1
3
5
7
R278
5.6K
SDD3
SDD2
SDD1
SDD0
SDD7
SDD6
SDD5
SDD4
SDD11
SDD10
SDD9
SDD8
SDD15
SDD14
SDD13
SDD12
R282
R283
R289
33
33
33
R280
R288
82
82
R258
R261
33
33
R277
1K
RN25
33 8P4R
DDREQB
-DIOWB
-DIORB
HDRDYB
RN28
33 8P4R
RN30
33 8P4R
-DDACKB
IRQ15
R275
82
R274
10K
SDA1
SDA0
-SDCS1
-DASP1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDA2
-SDCS3
SD_80P
RN32
33 8P4R
D
-DDACKB
-DIOWB
-DIORB
HDRDYB
DDREQB
Title
IDE/PANEL
-SDCS_1
-SDCS_3
1
8
6
4
2
8
6
4
2
2
4
6
8
2
4
6
8
-IDERST
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
2
-SDCS_1
-SDCS_3
-SDCS1
-SDCS3
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
13
of
20
1
2
3
R141
4
10K
DCLK6
DCLK5
DCLK7
DCLK8
C142
C144
C126
C128
10p
10p
10p
10p
DCLK1
DCLK2
DCLK4
DCLK3
C143
C151
C139
C127
10p
10p
10p
10p
DCLK11
DCLK12
DCLK9
DCLK10
C137
C138
C145
C149
10p
10p
10p
10p
CPUCLK
HCLK
DCLKO
C122
C123
C141
10p
10p
10p
NPCLK
SPCLK
C124
C150
10p
10p
PCICLK1
PCICLK2
C132
C131
10p
10p
VCC3
L29
CK_VDD1
FB
C117
.1u
A
C116
.1u
C130
.1u
VCC2_5
C140
.1u
C129
.1u
C146
.1u
C148
.1u
L28
CK_VDD2
FB
12p
C111
.1u
C113
.1u
I2CD2
I2CD1
C112
.1u
I2CD2
I2CD1
2
C115
3
9
16
22
33
39
45
23
24
4
5
14.31818MHZ
VDD1
VDD2
VDD2
VDD3
VDD3
VDD3
VDD4
VDDL1
VDDL2
MODE/PCI_F
PCI0
PCI1
PCI2
PCI3
PCI4
BUFFER IN
IOAPIC
GND
GND
GND
GND
GND
GND
GND
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
SDRAM10/PCISP
SDRAM11/CPUSP
SDRAM12
SDRAM13
SDATA
SCLK
X1
X2
1
X2
U8
1
6
14
19
30
36
27
48
42
C114
B
12p
USBCLK
SIO_OSC
ISA_OSC
USBCLK
SIO_OSC
ISA_OSC
R173
R140
R132
22
22
22
FS1
FS0
FS2
25
26
2
46
24M/FS1
48M/FS0
REF0
REF1/FS2
CPU0
CPU1
7
8
10
11
12
13
A
MODE
FS3
R177
R142
R150
R151
22
22
22
22
SPCLK
NPCLK
PCICLK2
PCICLK1
SPCLK
NPCLK
PCICLK2
PCICLK1
15
47
R163
R134
47
22
DCLKO
APICLK
DCLKO
APICLK
38
37
35
34
32
31
29
28
21
20
18
17
40
41
R146
R149
R147
R160
R161
R162
R171
R175
R179
R178
R164
R165
R148
22
22
22
22
22
22
22
22
22
22
22
22
22
DCLK7
DCLK8
DCLK3
DCLK4
DCLK11
DCLK12
DCLK9
DCLK10
DCLK2
DCLK1
DCLK6
DCLK5
DCLKWR
DCLK7
DCLK8
DCLK3
DCLK4
DCLK11
DCLK12
DCLK9
DCLK10
DCLK2
DCLK1
DCLK6
DCLK5
DCLKWR
44
43
R138
R139
22
22
CPUCLK
HCLK
CPUCLK
HCLK
B
ICS9148-26/-39/IC WORKS-W144
VCC3
JCK1
1
2
R174
10K
FS0
R172
10K
FS1
APICLK
SIO_OSC
C110
C118
10p
10p
USBCLK
C147
10p
ISA_OSC
C109
10p
3
5V_SB
JCK2
2
1
L4
3
FB
FS2
FUSE
1A
FS3
VCC3_SB
3
L5
VCC3
FB
JKB1
CB4
2
R133
10K
FS2
-EXTSMI
-EXTSMI
3
C
1-2:NORMAL
2-3:KEYBOARD WAKE UP
1
5
.1u
JCK4
1
C20
.1u
1
10K
2
R176
2
VCCE
3
JCK3
1
4
RN8
KB_CLK
MS_CLK
MS_DATA
KB_DATA
2
2
4
6
8
4.7K 8P4R
1
3
5
7
C
U5
NC7SZ125
CN1
S2
L22
JCK2
JCK1
CPU FREQ.
2-3
2-3
1-2
1-2
66.8MHz
33.3MHz
1-2
2-3
1-2
1-2
100.2MHz
33.3MHz
1-2
2-3
1-2
2-3
133MHz
44.4MHz
2
3
2N7002
C93
47pF
S4
KB_CK
PCI
1
3
2-3
1-2
112MHz
37.3MHz
2-3
2-3
2-3
103MHz
34.3MHz
1-2
1-2
1-2
1-2
133MHz
33.3MHz
1-2
1-2
1-2
2-3
124MHz
31MHz
1-2
1-2
2-3
1-2
150MHz
37.5MHz
1-2
1-2
2-3
2-3
140MHz
35MHz
MS_DATA
7
8
9
10
11
12
MS_DT
D
2-3
1-2
G
G
G
13
14
15
VCCE
Q5
1-2
KBDAT
NC
KBGND
KBVCC
KBCLK
NC
S3
1
JCK3
S1
1
1
C91
47pF
JCK4
Q3
2
KB_CLK
L23
KB_CLK
1
2
3
4
5
6
KB_DT
2
KB_DATA
2
KB_DATA
L15
MS_DATA
DP_KB/MS
L6
MS_CLK
MS_CLK
MSDAT
NC
MSGND
MSVCC
MSCLK
NC
G
G
16
17
L7
GNDE
MS_CK
C71
47pF
C70
47pF
D
KEYBOARD WAKE UP
*For ICS 9148-39/IC WORKS-144
Title
CLOCK SYNTHESIZER/KB WAKE UP FUNCTION
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
14
of
20
1
2
3
4
VTT
VCC3
CB15
.1u
CB18
.1u
CM19
1u
CT34
1500u
C134
1u
CT37
1000u
CM26
1u
CM32
1u
CM39
1u
CM33
1u
CM27
1u
CM25
1u
CM20
1u
CM21
1u
CM38
1u
CM37
1u
CM36
1u
CM42
1u
CT48
1500u
VDDQ
CM35
1u
A
CM28
1u
CM31
1u
CT38
1500U
CT44
1500u
CM34
1u
CT24
1500u
CM40
1u
CM18
1u
CM30
1u
CM29
1u
CM23
1u
A
VCCP
V_DIM
CM17
1u
CM11
1u
CM10
1u
CM16
1u
CM15
1u
CM12
1u
CM9
1u
CM14
1u
CM13
1u
CB33
.1u
CB20
.1u
CB28
.1u
CB30
.1u
CB38
.1u
CB23
.1u
CB41
.1u
CB26
.1u
CB34
.1u
CB36
.1u
CB21
.1u
CB29
.1u
CB39
.1u
CB24
.1u
CB14
.1u
CM8
1u
CT33
1000u
CT32
1000u
CB31
.1u
CB32
.1u
CB40
.1u
CB25
.1u
CB37
.1u
CB22
.1u
CT31
1000u
VCC3
CB42
.1u
CB27
.1u
CB35
.1u
CB43
.1u
R145
4.7K
B
B
+12V
FAN1
1
+12V
CT27
3
VCC3
CT43
1500u
CB13
.1uF
CT28
R303
4.7K
FAN2
1
+12V
CT42
1500u
CPUFAN1
2
CPU_FAN
CM7
1u
CT36
10u/25V
CPUFAN2
2
3
-12V
VCC3
CASE_FAN
5V_SB
R63
4.7K
CT23
10u/25V
POWER1
11
12
13
14
15
16
17
18
19
20
-5V
1
C
R82
4.7K
R90
Q6
3904
B
PWRON
1K
JT1
2
PWRON
E
C
RST_SW
3.3V
-12V
GND
PS-ON
GND
GND
GND
-5V
5V
5V
3.3V
3.3V
GND
5V
GND
5V
GND
PW-OK
5VSB
12V
1
2
3
4
5
6
7
8
9
10
R66
22
R64
PWGD
R67
100
1K
R65
2.7K
5V_SB
C90
.1u
PW_GOOD
CT21
10u
C
ATX POWER CON
CB10
.1u
CT19
10u
CT20
10u/25V
-12V
-5V
CT25
10u/25V
+12V
CT22
.1uF
CB11
CT6
10u/25V
CT26
CT5
CB48
CT16
10u
CB9
.1U
CM5
CB12
1u
.1U
CM6
1u
CT29
10u/25V
10u/25V
CT18
D
D
VIA TECHNOLOGIEA, INC.
Title
POWER CONNECTOR / BYPASS CAPACITORS
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
15
of
20
VID0
VID1
VID2
VID3
VID4
4.7K
L20
D
1uH
C89
1000u
3uH
C94
.001u
C96
1000u
L24
R76
3.3K
Q2
NDP6030L
G
C97
1000u
C102
1000u
C101
1000u
C100
1000u
C99
1000u
C98
1000u
CT30
1000u
S
C84
1000u
4
VCCP
Q4
NDP6030L
S
A
R70
10
DIODE
.1u
SEN/NC
1
16
GND
17
LGATE
13
PHASE
BOOT/NC
UGATE
2
V12
OCSET
10
C87
.002u
PWGD
OVP
19
CT/RT
20
VID0
4
VID1
5
6
8
VID2
R59
(OPT)
0
B
C82
.1u
V_FB
C81
.01u
VID3
C83
.1U
R61
R60
1.33K
U6
SS
VID4
3
R56
15
GND/NC
7
11
15
C92
14
D3
18
+12V
A
R71
10
12
R69
VID0
VID1
VID2
VID3
VID4
3
G
RN9
4.7K 8P4R
1
2
3
4
5
6
7
8
2
D
1
5V/COMP
R55
20K
9
C86
(OPT)
HIP6004/US3011
VCC2_5
R62
B
P_GND
VID0
VID1
VID2
VID3
VID4
20K
C95
(OPT)
VCCP_GD
C88
.01u
Q7
AMS1117-3.3
IN
CT35
.1u
10u
VCC3_SB
VOUT
OUT
VTT
Q8
VOUT
CB16
.1u
2
R118
100 1%
VCC3
3
GND
CB17
VIN
GND
5V_SB
VIN
ADJ
1
+ C104
1000u/6.3V
LT1587
C119
1000u/6.3V
CM22
1u
R122
20 1%
C
C
VCC2_5
Q9
VOUT
2
R130
100 1%
3
VIN
ADJ
1
+ C105
1000u/6.3V
LT1587
CM24
1u
R129
100 1%
D
D
Title
DC-DC CONVERTER
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
16
of
20
1
2
3
4
COM1, COM2 AND IR
with Bipolar drivers and receivers
VCC
U1
20
TXD1
RTS1
DTR1
DCD1
RXD1
DSR1
CTS1
RI1
A
16
15
13
19
18
17
14
12
TXD1
RTS1
DTR1
DCD1
RXD1
DSR1
CTS1
RI1
11
VCC
VCC1
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA5
GND
VCC2
1
+12V
5
6
8
2
3
4
7
9
10
CN2B
26
27
28
29
30
-12V
C32
100p
C28
+12V
20
TXD2
RTS2
DTR2
DCD2
RXD2
DSR2
CTS2
RI2
TXD2
RTS2
DTR2
DCD2
RXD2
DSR2
CTS2
RI2
16
15
13
19
18
17
14
12
11
VCC
VCC1
DA1
DA2
DA3
RY1
RY2
RY3
RY4
RY5
DY1
DY2
DY3
RA1
RA2
RA3
RA4
RA5
GND
VCC2
1
C26
100p
100p
100p
+12V
5
6
8
2
3
4
7
9
10
CN2C
35
36
37
38
39
-12V
C52
C53
C73
GD75232
B
C31
C34
C25
100p
100p
U4
C27
100p
100p
VCC
-XRI1
COM9A
C29
-12V
GD75232
A
COM1
31
32
33
34
100p
C74
100p
C75
100p
100p
COM2
40
41
42
43
-XRI2
COM9B
C47
B
100p
100p
C76
C45
100p
100p
1
3
5
7
RN2
8P4R 2K
PRINTER
2
4
6
8
RN3
8P4R 2K
2
4
6
8
RN4
8P4R 2K
2
4
6
8
2
4
6
8
RN5
8P4R 2K
1
3
5
7
1
3
5
7
1
3
5
7
VCC
R28
2K
C
C
P_ERROR
CN2A
1
3
5
7
P_STROBE
P_AUTOFD
1
2
3
4
5
6
7
8
9
10
11
12
13
RN11
2
4
6
8
8P4R 33
P_SLCTIN
P_INIT
P_PRD0
P_PRD1
P_PRD2
P_PRD3
P_PRD5
P_PRD6
P_PRD7
P_PRD4
1
3
5
7
RN10
2
4
6
8
ACK
8P4R 33
BSY
RN12
2
4
6
8
PE
14
15
16
17
18
19
20
21
22
23
24
25
PRINT PORT
P_PRD0
P_PRD1
P_PRD2
P_PRD3
P_PRD5
P_PRD6
P_PRD7
P_PRD4
1
3
5
7
SCLT
C50
180PF
C49
180PF
C41
180PF
C43
180PF
C51
180PF
C38
180PF
C40
180PF
C35
180PF
C30
180PF
8P4R 33
D
D
P_ACK
P_BUSY
P_PE
P_SLCT
C46
180PF
C48
C44
C42
180PF
180PF
180PF
C37
C39
C36
180PF
180PF
180PF
C33
180PF
Title
PRINTER / COM PORT
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
17
of
20
1
2
3
4
CD_IN1
R18
1
2
3
4
CD_IN
C19
4.7K
CD_IN_CONN
C14
1u
CDR
AVDD5
1
9
FB
1u
CDGND
CT17
CB7
10u
.1u
CT14
CB6
CM2
47u
.1u
1u
DVDD1
DVDD2
4
7
(1206)
0 (ADI)
VDD5
U2
L19
R17
4.7K
C18
GND_AUD
A
CDL
(1206)
R16
4.7K
R7
1u
(1206)
R9
4.7K
DVSS1
DVSS2
L1
25
38
AVDD1
AVDD2
26
42
AVSS1
AVSS2
CM1
CB1
CT3
CT2
1u
.1u
10u
10u
FB
L14
A
FB
GND_AUD
SYNC
SDIN_A
SDOUT
-ACRST
BITCLK_A
CN3C
LIR
26
24
LIL
22
LINE_IN
LININ
R3
1K
C12
1u
(1206)
R4
1K
4.7K (ADI)
30K (VIA)
C13
1u
(1206)
R8
LINE_R
R38
10
8
5
11
6
22
R40
22
SYNC
SDATA_IN
SDATA_OUT
RESET
BIT_CLK
LINE_OUT_L
R39
10K
14
15
R5
4.7K (ADI)
30K (VIA)
AUX_L
AUX_R
VIDEO_L
VIDEO_R
GND_AUD
SPEAK
SPEAK
R37
C67
1u
PC_BEEP
R36
4.7K
C66
1000p
CDL
CDR
CDGND
18
20
19
LINE_L
LINE_R
23
24
VDD5
B
R34
CN3B
1K (VIA)
MIR
20
18
MIL
16
MIC_IN
R33
0 (ADI)
L3
PC_BEEP
MICIN
12
21
22
13
PHONE
PHONE
1u
R6
CT1
C6
C17
1000p (ADI)
C65
CT7
R35
2.2K (VIA)
GND_AUD
XMICIN
.1u (VIA)
GND_AUD
CB2
CT4
.1u
47u
C8
C9
39
40
41
43
44
GND_AUD
.047u (ADI)
(0805)
.1u (ADI)
GND_AUD
B
29
30
C5
3
XTL_OUT
1
X1
10u (VIA)
1000p (VIA)
4.7K (ADI)
10u (VIA)
1u (ADI)
1u (ADI)
C7
560p (ADI)
270p (VIA)
(0805)
ADI1881/VT1661A
MICIN
L13
LINEOUTR
31
32
33
34
AFILT1
AFILT2
XTL_IN
36
VDD5
27
NC
NC
NC
NC
NC
PC_BEEP
MIC1
MIC2
PHONE_IN
2
C11
XMICIN
FB(ADI)
0(VIA)
MIC_IN
FB
R11
1K (VIA)
LINEOUTL
C3
FILT_R/NC
FILT_L/NC
RX3D/NC
CX3D/NC
LINE_IN_L
LINE_IN_R
GND_AUD
35
28
VREFOUT
CD_L
CD_R
CD_GND
GND_AUD
R19
4.7K (VIA)
R10
4.7K (VIA)
37
VREF
1K
SPEAK_IN
LINE_OUT_R
MONO_OUT
16
17
4.7K
46
45
CS1/ID1
CS0/ID0
LINE_L
R20
47
48
EAPD
CHAIN_CLK/NC
C4
560p (ADI)
270p (VIA)
(0805)
GND_AUD
2
24.576MHz
C69
C68
22p
22p
AVDD
R49
C77
20K 1%
L18
100p
CT11
U3
LINE_OUT
(1206)
C1
LINEOUTR
C2
1u
(1206)
LINEOUTL
C
C10
1u
1u
R1
20K 1%
R2
20K 1%
2
5
3
6
FB
47u
INA
SDN
BYPASS
INB
OUTA
VAA
GND
OUTB
1
8
4
7
CT12
CT13
CB5
(1206)
GND_LOUT
TPA122
C78
100p
R50
20K 1%
.1u
CN3D
L9
220uF
LOR
32
30
LOL
28
FB
L10
220uF
FB
C55
C
C54
470p
470p
LINOUT
FB
L8
GND_LOUT
GND_LOUT
2
4
6
8
GAME PORT
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
MSO
D
JBCY
JACY
JBB2
JAB2
MSI
JAB1
JBB1
JACX
JBCX
R32
R31
2K
2K
JACX_
JBCX_
MSO
R30
R29
JBCY
JACY
JBB2
JAB2
MSI
L12
C63
C64
C58
C57
100p
2K
2K
JBCY_
JACY_
C62
C61
C60
C59
.01u
AVDD
.1u
CT15
CB8
10u
.1u
VIN
VOUT
OUT
CB3
CT8
.1u
10u
AVDD5
R351
0 (OPT)
R350
0 (OPT)
D
GND_LOUT
C56
VDD5
Q1
AMS1117-5.0
IN
GND
VCC_JOY
FB
JAB1
JBB1
JACX
JBCX
+12V
CN3A
L11
GND
RN6
4.7K 8P4R
1
3
5
7
R51
4.7K
GND_AUD
GAME_PORT
* For test audio quality
Title
AC97 AUDIO CODEC & AUDIO PORTS
FB
GND_MIDI
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
18
of
20
1
2
3
4
A
A
AMR1
B
SPEAK
AMR_AGND
J3
-12V
1
2
+12V
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
AUDIO_MUTE
GND
MONO_OUT/PC_BEEP
RESERVED
RESERVED
PRIMARY_DN
-12V
GND
+12V
GND
+5VD
AUDIO_PWRDN
MONO_PHONE
RESERVED
RESERVED
RESERVED
GND
+5VDUAL/+5VSB
USB_OC
GND
USB+
USB-
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
R58
C85
B
0 (OPT)
PHONE
1u
AMR_VCC3
L26
VCC3_SB
AMR_VCC
5V_SB
L25
AMR_VCC
FB
FB
OVER_C1
USB_D1+
USB_D1-
L21
FB
VCC3
SDOUT
-ACRST
SDOUT
-ACRST
R113
0 (OPT)
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
GND
RESERVED
RESERVED
+3.3VD
GND
AC97_SDATA_OUT
AC97_RESET
AC97_SDATA_IN3
GND
AC97_SDATA_IN2
GND
AC97_MSTRCLK
GND
S/P-DIF_IN
GND
+3.3VDUAL/+3.3VSB
GND
AC97_SYNC
GND
AC97_SDATA_IN1
GND
AC97_SDATA_IN0
GND
AC97_BITCLK
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
R87
AMR_VCC3
AMR_AGND
0 (OPT)
SYNC
SYNC
R101
22
SDIN2
SDIN2
R107
22
SDIN
SDIN
R112
22
BITCLK
BITCLK_R
AMR_SLOT
AMR_AGND
R100
10K (OPT)
C
R106
10K (OPT)
C
R108
10K (OPT)
D
D
Title
AMR SLOT
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
19
of
20
1
2
3
4
For STR function
5V_SB
-RSMRST
A
9
14
4
-RSMRST
V_DIM
14
5V_SB
V3SB
10
6
8
A
5
5V_SB
1
2
3
5V_SB
8
U13C
F00
12
D
11
Q
C
Q
8
74
14
3
2
U15B
F02
12
13
1000u
1-2
2-3
DISABLE
ENABLE
B
U15D
F02
14
4
V3SB
OUT
CB44
1000u
2
5V_SB
3
PW_BN
GND
.1u
C163
D
P
C
U16A
Q
5
Q
6
R322
C
R297
R251
R248
R252
R246
R204
R201
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
-RSMRST
1.5K
R296
74
1
VOUT
GND
C164
1000u
PWRON
11
U13A
F00
10u
C165
1000u
14
14
3
.1u
C166
5V_SB
2
CT47
-STR
5V_SB
STR FUNCTION:
CB45
8
7
6
5
C
4
5
5V_SB
VIN
D
D
D
D
Q12
MMBT3904
B
1
Q11
AMS1117-3.3
S
S
S
G
FDS6670A
J6
1
IN
1
2
3
4
E
6
14
14
3
U15A
F02
5V_SB
10K
U14
5V_SB
2
1
R286
1K
5V_SB
-SUSB
B
V_DIM
VCC3
11
U13D
F00
6
5
4
+12V
9
R287
13
-SUSC
S
D
S
U16B
P
13
5V_SB
12
D
D
G
NDC632P
10
14
10
-STR
U13B
F00
14
9
PW_GOOD
U10
U15C
F02
3.3K
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
CKE_0
CKE_1
CKE_2
CKE_3
CKE_4
CKE_5
C171
C
5V_SB
10K
1u
VCC3_SB
VCC3
R269
22K (OPT)
V_DIM
R255
0 (OPT)
R254
0 (OPT)
R245
0 (OPT)
R244
0 (OPT)
R257
0 (OPT)
V_DIM
R250
R249
R253
R247
R203
R202
-RSMRST
C167
1u (OPT)
-SUSC
D
R270
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
0 (OPT)
CKE_0
CKE_1
CKE_2
CKE_3
CKE_4
CKE_5
PWRON
D
For NON-STR function
Title
STR OPTION CIRCUIT
1
2
3
Size
C
Document Number
Date:
Rev
0.1
4
Sheet
20
of
20

Design Guide VT82C694X Apollo Pro133A with VT82C686A South

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