Novel Transistors – Beyond the Planar Silicon MOSFET

Transcription

45th European Solid-State Device Research Conference
TUTORIAL
Novel Transistors –
Beyond the Planar Silicon MOSFET
Organizer:
Max Lemme
University of Siegen, Germany
Conference Venue:
Messe Congress Graz, Austria
September 18, 2015
Conference Organization:
JOANNEUM RESEARCH Foschungsgesellschaft mbH
Graz, Austria
Technical Co-Sponsorship
Novel Transistors –
Beyond the Planar Silicon MOSFET
Organizer: Max Lemme, University of Siegen, Germany
The aim of this tutorial is to present – in a didactic format – novel and emerging transistor options
for More Moore and More Than Moore applications. Even though industry is approaching the end
of physical gate length scaling, the quest for new transistor designs and materials is far from over. In
fact, the options for future transistors appear to be as wide as or wider than they have ever been.
The speakers of this tutorial have been carefully chosen to reflect the multitude of approaches pursued in research and development today. The target audience is PhD students with various backgrounds and industry engineers, but also aims to peak the interest researchers working in related
fields. The presentations will provide a thorough introduction to the respective topics and aim to
give an outlook on circuit design implications. The latter is intended to also address attendants of the
sister conference, the European Solid-State Circuits Conference (ESSCIRC).
Agenda:
13:00 Thin Channel Silicon Transistors
Geert Eneman, IMEC, Leuven (Belgium)
Page 3
14:00 Coffee Break
14:30 Tunnel FETs
Joachim Knoch, RWTH-Aachen, Aachen (Germany) 15:30 Compound Semiconductor Devices
Suman Datta, Penn State, State College (USA)
Page xx
16:30 Coffee Break
17:00 2D Channel Devices
Jörg Appenzeller, Purdue, West Lafayette (USA)
Page XX
18:00 Graphene FET Models for Circuit Design
Sebastien Fregonese, University of Bordeaux, Bordeaux (France)
2
ESSDERC 2015 Tutorial:
Thin Channel Silicon Transistors
Geert Eneman
E-Mail: [email protected]
© IMEC 2015
Outline
 Intro: Scaling and Thin Channel MOSFETs
 Silicon-on-Insulator
 FinFETs
 Nanowires
 Conclusions
© IMEC 2015
GEERT ENEMAN
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3
Outline
 FinFETs
 Nanowires
 Conclusions
© IMEC 2015
GEERT ENEMAN
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The power of scaling
Scaling  more and faster transistors on chip
Year
1971
2015
ratio
Transistors
2.300
1.900.000.000
~ 800.000
Speed (Hz)
10.800
3.800.000.000
~ 360.000
Gate length (nm)
10.000
~20
~ 1/500
12
133
~ 11
Area (mm2)
>40 years of scaling
Intel 4004
Intel Core i7
Broadwell-U
© IMEC 2015
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MOSFET transistors
MOSFET’s: the basic component of digital logic
applications
Top-view
Side-view
=
Ideal transistor
= switch
Wanted:
• High on-current
“On-current”
Switching time τ :
“Off-current”=0
Source-to-drain current
Transistor channel
0
τ~
VDS=1
CVDD
I on
Source
Drain
n+
region
Silicon
n+
region
pregion
Substrate
Log ISourcedrain
Drain
=
Gate
Substrate
Drain
Source
Gate
Source
Isolation
oxide
Gate
A “real” transistor
“On-current”
VDS=1
“Off-current”
• Low off-current
Static power consumption:
VT
1V
GS
© IMEC 2015
PStatic ~ I Off ⋅ VDD
0
VT
1
GEERT ENEMAN
VGS
5
Planar Si technology
Poly-Si gate
SiO2 spacer
Silicide
Essentially a 2D device: different
SiO
active layers are thin
isolation
2
• Only upper surface layer of Si is active
• Thin gate insulator
• Thin gate electrodes
Si substrate
SiO2 gate insulator
100nm
Low-topography structure: limited
strain on patterning (lithography)
Intel’s 32nm planar technology
(top-view)
Process:
• Layer depositions  thickness control
• Lithography lateral dimension
control
 Billions of transistors on one
substrate
© IMEC 2015
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SiO2
Si
Gate
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5
MOSFET Scaling
•
Scaling has been very successful until 130nm node
Below 130nm node: “simple scaling” becomes
problematic
•
Gate leakage
Source-to-drain leakage
Scaling:
Scaling
Oncurrent
Offcurrent
0
Offcurrent
1
Scaling
Oncurrent
0
VGS
1
VGS
• Loss of channel control  offcurrent increases
• Increase of doping  less oncurrent improvement
• Higher on-current
• Same off-current
© IMEC 2015
What we get:
Log ID/W
Log ID/W
What we want:
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MOSFET Scaling
Specified vs. actual scaling of LG and TOx
100
200
300
Technology node (nm)
1999
2002
2004
4
ITRS spec
3.5
T scaling
Ox
3
Slower
2.5 than
2 ITRS
1.5
1
0.5
0
100
200
Technology node (nm)
2007
1999
G
Gate oxide (Tox) scaling
Oxide thickness (nm)
ITRS spec
L scaling
2002
350
300
250
200
150
100
50
0
0
2013
2010
2007
2004
Gate length (nm)
Gate length (LG) scaling
Scaling: slowed down due to short-channel
control issues, and gate leakage
© IMEC 2015
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Short-channel effects
Long-channel transistors: build-up of
inversion layer at the gate interface
Band structure along cutline
NFET
Gate
Gate
P-
Dielectric
N+
Cutline
N+
Drain
Electrons
-----
Conduction
band
+++
Source
NFET in on-state
Holes
Valence
band
Well-behaved transistors: inversion carriers
only close to gate  good gate control
© IMEC 2015
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Long-channel transistors: build-up of
inversion layer at the gate interface
Band structure along cutline
Gate
Electrons
-----
PFET in on-state
Conduction
band
Holes
Valence
band
Gate
Gate
P-
Dielectric
N+
Cutline
N+
Drain
+++
Source
NFET in on-state
Conduction
+++
+
+
NFET
- - - band
Valence
band
Well-behaved transistors: inversion carriers
only close to gate  good gate control
© IMEC 2015
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N+
N+
Path for electrons,
far from the gate
Gate
Space charge
region of n+
source/drain
NFET in on-state
-- - -
++
NFET
Log ISourcedrain
Short-channel effects: channel is influenced by
source/ drain regions  short-circuit from source
to drain
Poor shortchannel control
Well-behaved
transistor
SS
P-
0
VGS
Leakage paths in the substrate lead to poor shortchannel control, e.g. poor Subthreshold Swing (SS)
 increased off-state current
© IMEC 2015
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N+
N+
Punchthrough
leakage
Path for electrons,
far from the gate
Gate
Space charge
region of n+
source/drain
NFET in on-state
-- - -
++
NFET
Log ISourcedrain
Short-channel effects: channel is influenced by
source/ drain regions  short-circuit from source
to drain
Well-behaved
transistor
SS
P-
0
VGS
Leakage paths in the substrate lead to poor shortchannel control, e.g. poor Subthreshold Swing (SS)
 increased off-state current
© IMEC 2015
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N+
N+
Gate
Smaller space
charge region
of n+
source/drain
NFET in on-state
--
+ ++ +
NFET
P+
Log ISourcedrain
Solution: increase substrate doping (Well /
halo implants, ground-plane)
Leakage?
With increased
substrate doping
SS
0
VGS
Increased substrate doping  better short-channel
control. However, increased doping  more
junction leakage and lower mobility
© IMEC 2015
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N+
N+
Gate
Silicon-oxide
=insulator
--
Oxide
NFET in on-state
++
NFET
Log ISourcedrain
Solution: Silicon-on-Insulator (SOI). UltraThin Body SOI (UTBSOI).
Series
resistance?
SOI
SS
0
VGS
Insulator cuts off source-drain leakage path.
Issues: thin Si channel  defects, series resistance,
body bias control, process control
© IMEC 2015
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Solution: Strain-relaxed buffers: band energies are
material-dependent  band offset between channel
and SRB
NFET in on-state
N+
“QuantumWell”
N+
Gate
Strainrelaxed
buffer
Wanted band offset
--
SRB
Band offset
+ ++
NFET
SRB’s band offset can improve or degrade short-channel
effects / scalability.
Less band offset than SOI  SRBs: easier to manufacture
© IMEC 2015
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Solution: Strain-relaxed buffers: band energies are
material-dependent  band offset between channel
and SRB
NFET in on-state
--
SRB
Unwanted band offset
“Quantumbarrier”
Band offset
Gate
N+
Gate
N+
“QuantumWell”
+ ++
Strainrelaxed
buffer
Wanted band offset
SRB
-- --
+ ++
NFET
SRB’s band offset can improve or degrade short-channel
effects / scalability.
Less band offset than SOI  SRBs: easier to manufacture
© IMEC 2015
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Solution: FinFETs: a thin ‘fin’ channel that is
controlled from 3 sides by the gate
Gate
Gate
-- ---
Oxide
NFinFET in on-state
SOI FinFET
Si
BOX
Insulator cuts off source-drain leakage path.
© IMEC 2015
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Solution: Gate-All-Around / Nanowire:
gate around channel  excellent
electrostatic control
NFinFET in on-state
Nanowire
Gate
Gate
-- ---
Drain
Gate
Source
© IMEC 2015
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Physical limits in scaling Si MOSFET
The MOSFET can be thought of as consisting of two wells
(source and drain) separated by a barrier (channel).
Thermionic
emission
E CB
E VB
Source
QM
tunneling
Sum = Ioff
channel
leakage
BTB
tunneling
unneling
Lgate
Drain
 Planar gate: limited electrostatic control of the channel
When the channel length reduces, no effective barrier is formed between
the source and drain and the transistor “OFF” current increases.
Devices with an improved electrostatic control over the channel are needed.
© IMEC 2015
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Natural channel length λ
“A device will be free of short-channel effects if the gate length
is at least 4 to 6 times longer than the natural length λ.”
Short-channel effects in MOSFETs can be
minimized by:
- Decreasing the gate oxide thickness dox
- Increasing the dielectric constant εox of the gate oxide
material. I.e. decreasing the ‘effective oxide thickness’.
- Decreasing the channel thickness dchannel  SOI,
FinFETs and nanowires
© IMEC 2015
GEERT ENEMAN
I. Ferain et al, Nature Vol. 479, 310 (2011)
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Multigate MOSFETs
The value of the natural length is given by:
λ1 =
ε Si
tox t Si
ε ox
λ2 =
ε Si
tox t Si in a double-gate MOSFET
2ε ox
λ4 =
in a gate-all-around
ε Si
tox t Si (quadruple-gate)
4ε ox
in a single-gate MOSFET
MOSFET
εox: electrical permittivity of the gate oxide
εSi: electrical permittivity of the channel
tox: gate oxide thickness
tSi: channel thickness
© IMEC 2015
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Multigate MOSFETs
The most interesting information that can be extracted from the
calculation of the natural length for the different gate configurations is
that:
and
It has been shown, using extensive numerical simulations, that the
natural length for a tri-gate device is given by:
The concept of an ‘effective gate number’, N, can thus be defined, and
the generalized relationship for the natural length can be written as
follows:
λN =
ε Si
tox t Si
Nε ox
© IMEC 2015
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Multigate MOSFETs
F. Boeuf, ST, IEDM short course, 2013
© IMEC 2015
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Outline
• Properties, advantages and challenges
• Wafer fabrication
• Strain
• Circuit implications
 FinFETs
 Nanowires
 Conclusions
© IMEC 2015
GEERT ENEMAN
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SOI devices
Conventional bulk
MOSFET
SOI MOSFET
Silicon channel
Silicon dioxide
Silicon substrate
Silicon substrate
Silicon-On-Insulator
(SOI): thin channel on
top of SiO2 on top of
Si substrate
© IMEC 2015
T. Hook, IBM,
FDSOI Workshop,
San Francisco,
California (2012)
GEERT ENEMAN
Conventional bulk
MOSFET
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SOI devices
Drain-Induced Barrier Lowering
O. Weber et al,
Leti / ST, ECS
Trans. 22(1),
78, 2009
Silicon substrate
SOI MOSFET
Silicon dioxide
Silicon substrate
© IMEC 2015
SOI advantage #1: Improved scalability,
especially for thin channels (small tSi)
 Allows shorter transistors, and lowvoltage operation
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SOI devices
Conventional bulk
MOSFET
SOI MOSFET
Si:
ε=11.7
Silicon substrate
SiO2:
ε=3.9
Silicon dioxide
Silicon substrate
SOI advantage #2-#3:
• Lower junction leakage  reduced static power
• Lower junction capacitance  increased speed
© IMEC 2015
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Classification of SOI devices
Conventional
MOSFET
Partially depleted
SOI MOSFET
Floating body
Silicon substrate
Silicon dioxide
Silicon substrate
Partially-depleted SOI:
• Silicon film thickness greater than bulk depletion width
(i.e. >40-80nm)
• Risk for kink effects
• Similar device operation as conventional MOSFETs
© IMEC 2015
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Classification of SOI devices
Conventional
MOSFET
Partially depleted
SOI MOSFET
Fully depleted SOI
MOSFET
Floating body
Silicon dioxide
Silicon dioxide
Silicon substrate
Silicon substrate
Silicon substrate
Fully-depleted SOI:
• Silicon film thickness lower than bulk depletion width
• Channel parameters depend on substrate bias
© IMEC 2015
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SOI devices
Bulk transistors
“Latch-up is the inadvertent
creation of a low-impedance path
between the power supply rails of
a MOSFET circuit, triggering a
parasitic structure which disrupts
proper functioning of the part”
SOI transistors
UTBSOI advantage #4-#5:
• No parasitic bipolar/ thyristor 
no latch-up
• Isolation from substrate  good
radiation hardness
http://www.analog.com/library/analogDialogue/archives/35-05/latchup/index.html
© IMEC 2015
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Back biasing of SOI devices
Fully depleted SOI
MOSFET
ION/IOFF for SOI NFET
Varying substrate bias
Silicon dioxide
Q. Liu et al,
IEDM Proc.,
pp. 228 (2013)
Silicon substrate
Fully-depleted SOI:
• Silicon film thickness lower than bulk depletion width
• Channel parameters depend on substrate bias
 SOI advantage #6: back bias can be used for VT tuning.
High-performance, low-leakage, ... device flavors
© IMEC 2015
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SOI: Channel Doping and Variability
Threshold voltage (VT)
vs channel thickness
Channel doping (cm-3):
1e18
7.5e17
• Thick channels:VT can be
tuned by channel doping.
Similar to bulk FETs.
5e17
2.5e17
1e17
• Thin channels:VT
independent of doping
 No channel doping
required in UTBSOI
H. Van Meer, PhD Thesis, KU Leuven, 2002
© IMEC 2015
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18
SOI: Channel Doping and Variability
VT mismatch
Threshold voltage (VT)
vs channel thickness
Channel doping (cm-3):
1e18
7.5e17
5e17
2.5e17
1e17
H. Van Meer, PhD Thesis, KU Leuven, 2002
© IMEC 2015
O. Weber, ECS Trans. 22(1), pp 71 (2009)
Random dopant fluctuations are an
important source of variability
 SOI advantage #7: low channel
doping  low VT variability, high
mobility
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SOI: Access Resistance
Thin source/drain portions under the
channel are a concern for access resistance
Raised Si/SiGe
source/drains
grown by epi
Silicon dioxide
Silicon substrate
Careful junction design, thin spacers and
epitaxial source/drains are a must for UTBSOI.
Series resistance reduction is more critical
than for bulk technologies
© IMEC 2015
GEERT ENEMAN
T. Hook, IBM, FDSOI Workshop, San Francisco, California (2012)
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Outline
• Properties, advantages and challenges
• Wafer fabrication
• Strain
 FinFETs
 Nanowires
 Conclusions
© IMEC 2015
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SOI devices: Substrate
Fabrication
SOI substrate techniques
•
•
SIMOX (Separation by IMplanted OXygen)
•
Smart-Cut®
•
BESOI (Bond and Etch-back SOI)
ELTRAN® (Epitaxial Layer TRANsfer)
•
SOS (Silicon-On-Sapphire)
•
...
© IMEC 2015
G. Celler et al, Appl. Phys. Rev.
93(9), 4955, 2003
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SOI devices: Substrate
Fabrication
SOI substrate techniques
•
•
SIMOX (Separation by IMplanted OXygen)
•
Smart-Cut®
•
BESOI (Bond and Etch-back SOI)
ELTRAN® (Epitaxial Layer TRANsfer)
•
SOS (Silicon-On-Sapphire)
•
...
© IMEC 2015
G. Celler et al, Appl. Phys. Rev.
93(9), 4955, 2003
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SOI Formation: SIMOX Process
1. Initial silicon
2. Oxygen implant
3. Anneal
SiO2
Si
Si
•
•
© IMEC 2015
Oxygen
profile
Energy 120-200 keV
Dose ~0.3-1.8e18 cm-2
GEERT ENEMAN
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Si
>1300°C, 3-6 hours
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SOI Formation: SMART-CUT® Process
(Soitec, CEA-Leti)
1. Initial silicon
5. SmartCut splitting at 500°C
A
A
2. Oxidation
B
3. Smart-Cut implant
6. Annealing 1100°C + CMP
SOI wafer
H+ ions 5x1016 cm-2
4. Cleaning and bonding
7. Wafer A becomes B
A
New A
Wet clean or plasma treated bonding
A→B
B
© IMEC 2015
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SOI: What about Strained Channels?
Mechanical strain is a performance booster for
planar FETs since the 90nm node
• Global strain: e.g. virtual buffers
Planar technology
Strained Si
channel
σ
Gate
σ
σ
SiGe virtual
substrate
© IMEC 2015
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• Global strain: e.g. virtual buffers
Strained SOI wafers (SOITEC)
Planar technology
Strained Si
channel
σ
σ
Gate
σ
SiGe virtual
substrate
SOI technology
Strained Si
channel
σ
σ
Gate
σ
SiO2
Silicon
Global stress techniques compatible with SOI technology
© IMEC 2015
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•
Strained
CESL
• Local strain: Contact etch-stop layers (CESL), source/drain
(S/D) stressors
SOI technology
Planar technology
Strained
CESL
A. Thean, VLSI
Symp., 2006
CESL compatible with SOI technology
© IMEC 2015
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•
•
SiGe S/D
Strained
CESL
• Local strain: Contact etch-stop layers (CESL), source/drain
(S/D) stressors
SOI technology
Planar technology
Strained
CESL
A. Thean, VLSI
Symp., 2006
Si1-x Gex
Si1-x Gex
SiO2
??
CESL compatible with SOI technology
SiGe S/D stressor: no S/D etch possible  not optimal
© IMEC 2015
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SOI: More Design Considerations
 Lower S/D cap, lower parasitics to ground  Improved frequency
response
 Reduced latch-up, improved substrate immunity
 Improved high-T operation (due to lower leakage)
• Passive components can be different:
•
•
•
SOI well resistor has no parasitic diode, lower capacitance to ground
No well capacitance in SOI
Inductors have higher Q factor (high-resistive substrate)
 No conventional diodes available. Gated diodes are an alternative.
 Floating body effects (PDSOI)
 Poor thermal response (buried oxide). Self heating.
Bulk
SOI
A. Marshall & S. Natarajan, “SOI
Design: Analog, Memory and Digital
Techniques”, Springer, ISBN 0-79237640-4
© IMEC 2015
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Outline
 FinFETs
• Properties and advantages
• Access resistance and junctions
• Effective width and mobility
• Strain
 Nanowires
 Conclusions
© IMEC 2015
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SOI and FinFETs
L. Geppert, IEEE Spectrum, pp
28, Oct. 2008
SOI and FinFETs both get their excellent
scalability from an ultra-thin channel
SOI
© IMEC 2015
FinFETs
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FinFETs / Tri-Gate FETs
FinFET cross-sections
Cross-section parallel to Fin
© IMEC 2015
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Cross-section perpendicular to FIN
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FinFETs can be fabricated on SOI or bulk
substrates
SOI-FinFET
Si fin
Bulk-FinFET
Si fin
SiO2
Shallowtrench
isolation
SiO2
Si sub
Si sub
Bulk-FinFETs can use standard wafers (cost)
Parvais et al., VLSI-TSA, 2009
© IMEC 2015
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FinFETs can be fabricated on SOI or bulk
substrates
Bulk-FinFET
Si fin
IOFF vs gate length
Shallowtrench
isolation
SiO2
Si sub
Bulk-FinFETs can use standard wafers (cost),
but require isolation of the substrate (well
doping, barrier layer, ...)
Manoj et al., IEEE T-ED 55(2), pp. 609, 2008
© IMEC 2015
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FinFETs have similar advantages as SOI FETs
Subthreshold slope vs
gate length
 Excellent scalability
© IMEC 2015
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Gate
oxide
Gate
Si
P+
HDD
P+
HDD
BOX
Junction
cap
STI
Inverter delay vs fin height
High-resistive path to
substrate 
 Low junction leakage
 Low junction capacitance
 Robust against latch-up
and radiation
© IMEC 2015
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Gate
oxide
Gate
Si
P+
HDD
P+
HDD
BOX
Junction
cap
STI
Inverter delay vs fin height
substrate 
and radiation
• Back bias for VT tuning?
© IMEC 2015
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Threshold voltage vs fin width
0.5
0.4
[V]
0.3
L
=50 mV
DS
poly
=10 µm
0.2
Tlin
V
V
0.1
increased fin
doping
0
no fin doping
-0.1
-0.2
0.01
0.1
W
fin
Narrow fins: Fully
depleted.VT weakly
dependent on channel
doping
© IMEC 2015
1
[µm]
10
Wide fins: similar to
planar.VT depends
strongly on fin doping
substrate 
and radiation
 Lowly-doped channels 
reduced random-dopant
fluctuation, good mobility
N. Collaert et al., VLSI Symp. 2005
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Outline
 FinFETs
• Strain
 Nanowires
 Conclusions
© IMEC 2015
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FinFETs: Access resistance
Current travels from source 
drain. In the extension it passes
through a fin which is lightlydoped and not gate-controlled
 High extension resistance
Nitride/oxide spacers
Drain
Source
Gate
Extension region:
under the spacer
spacer
Fins
HM
Source
Drain
poly
SOI FinFET
Gate
© IMEC 2015
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FinFETs: Junctions
Implanted dopants may lead to non-uniform
source/drains (S/D)
Top-Only S/D
Conformal S/D
IDS –VGS Comparison
1.E-02
Gate
Gate
1.E-03
1.E-04
Drive current
Isat (uA/um)
1.E-05
1.E-06
Top-Only Extension
Conformal Extension
1.E-07
1.E-08
Fin width=35nm
Fin height=60nm
VDD=1.2V
1.E-09
1.E-10
1.E-11
1.E-12
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Vg (V)
Conformal extensions result in up to 2 x
Idrive increase !
Junction design is critical for fins.
Source/drains need to be conformally doped
© IMEC 2015
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FinFETs: Junctions
ION/IOFF Comparison
1.E-04
nFET
VDD=1V
Tilt =10deg
1.E-05
IOFF [A/um]
1.E-06
1.E-07
1.E-08
45deg
1.E-09
1.E-10
1.E-11
0
100
200
300
400
500
600
700
800
ION [uA/um]
Strong dependence of performance
on implant angle
 High angles required for uniform
fin doping... but high angle
implants can not be used in high
density circuits
© IMEC 2015
GEERT ENEMAN
57
FinFETs: Junctions
‘Shadowing’ of implants due to neighboring
fins and resist
Cross-section of the fin
Implant direction
β
α
Fin
Resist
Fin
Fin
In dense layouts (e.g. SRAM),
high-angle implants are
shadowed by neighboring
fins or resist
© IMEC 2015
GEERT ENEMAN
58
31
FinFET Access
Resistance: Extensions
E.g. plasma doping as alternative:
1,E-02
BF3 PLAD - ST Pulsed Plasma DC
1015/cm2
pMOS
Ioff (A/µm)
1,E-04
1,E-06
500V - P1
15%
1,E-08
500V - P2
500V - P3
500V - P2 - dilution
500V - 1.5E15/cm2
1,E-10
750V - P1
10° tilt I2 reference
1,E-12
0
200
400
600
800
1000
1200
1400
Ion (µA/µm)
D. Lenoble et al., VLSI Symp. 2006
© IMEC 2015
GEERT ENEMAN
59
Dual epi raised S/D for non-planar tri-gate
Blanket epitaxial
raised S/D growth
Selective undercut
Etch pMOS regions
In-situ doped
p+ SiGe epitaxy
Epi-grown S/D requires to reduce access resistance
J. Kavalieros et al, Intel, VLSI 2006
© IMEC 2015
GEERT ENEMAN
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32
Outline
 FinFETs
• Strain
 Nanowires
 Conclusions
© IMEC 2015
GEERT ENEMAN
61
FinFETs and Effective Width
Top channel
Side channel
(cut along
gate)
(omitting
gate)
Top channel
Side channel
Total channel width
𝑊𝑊𝑊𝑊𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸𝐸
𝐼𝐼𝐼𝐼 ≈ 𝐶𝐶𝐶𝐶𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂
� 𝜇𝜇𝜇𝜇 � 𝑉𝑉𝑉𝑉𝐺𝐺𝐺𝐺𝐺𝐺𝐺𝐺 − 𝑉𝑉𝑉𝑉𝑇𝑇𝑇𝑇
𝐿𝐿𝐿𝐿
𝛼𝛼𝛼𝛼
FinFETs: Conduction through top and side of channel
Can offer higher drive current than planar
(depending on distance between fins, fin height, etc...)
© IMEC 2015
GEERT ENEMAN
62
33
A channel is formed at the top and sidewalls of the fin
Electrical vs. physical FET width (Fin-Effect)
𝐿𝐿𝐿𝐿
𝛼𝛼𝛼𝛼
© IMEC 2015
GEERT ENEMAN
63
𝐿𝐿𝐿𝐿
𝛼𝛼𝛼𝛼
Carrier mobility
(cut along
gate)
(omitting
gate)
Top channel
Top channel (100)/<110>
Side channel
(110)/<110>
Fin top and side are different
crystallographic planes and
have different carrier mobilities
• Fin top: (100)/<110> plane
• Fin side: (110)/<110> plane
Side channel
© IMEC 2015
GEERT ENEMAN
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34
FinFETs: Orientation-Dependent Mobility
Experimental work, SiON dielectric, long channels
Electrons
Holes
Fin side
Fin top
Fin top
Fin side
Mobility at NINV=1e13cm-2
Silicon
cm2/Vs
Electrons
Holes
(100)/<110>
237
58
(110)/<110>
88
168
(110)/<100>
107
106
(111)/<112>
154
92
© IMEC 2015
Yang et al, IBM, TED 53(5), 965 (2006)
GEERT ENEMAN
65
Fins: What about Strained Channels?
Channel stress along fin sidewall
Stress (MPa)
Planar technology
Strained Si
channel
σ
σ
Gate
σ
SiGe virtual
substrate
Perpendicular
STI
Channel
Longitudinal
Virtual substrate
Fin technology
Fin height 30nm
0
Perp.
-1000 stress
Longit.
stress
Eneman et al.,
IEDM pp. 131
(2012)
-2000
10
100
1000
Fin width (nm)
For realistic fin widths (W<30nm), perpendicular
channel stress is negligible
Virtual substrates are uniaxial stressors in FinFETs
(planar MOSFETs: biaxial stress)
Most stressors are compatible with (bulk) fins, with
different channel stress
© IMEC 2015
GEERT ENEMAN
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35
FinFETs: More Design Considerations
Similarities to planar SOI:
 Lower S/D cap, lower parasitics to ground  Improved
frequency response
SOI-FF well resistors have no parasitic diode, lower capacitance
to ground
No well capacitance in SOI-FF
•
•
•
 No conventional diodes available in SOI-FF. Gated diodes are an
alternative.
 Poor thermal response (SOI-FF). Self heating.
© IMEC 2015
GEERT ENEMAN
67
FinFETs: More Design Considerations
 Potentially higher drive current per area than planar
 Fin pitch (Pfin) and fin height are fixed by process
 Discrete number of fins  quantized ‘device width’
 Gate-to-S/D parallel plate transistor  higher gateto-source/drain (Miller) capacitance
 Using back-bias for multi-VT is difficult
Fin
Fin
King Liu, VLSI Tech.
Short course, 2012
© IMEC 2015
Metal
contact
GEERT ENEMAN
J. Warnock et al,
ISPD 2013
68
36
Outline
 FinFETs
 Nanowires
• Properties, advantages and disadvantages
• Fabrication
• Design considerations
 Conclusions
© IMEC 2015
GEERT ENEMAN
69
Evolution of transistors towards devices
with improved electrostatic control
J.P. Colinge, Tyndall
© IMEC 2015
GEERT ENEMAN
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37
Comparison of Planar vs Nanowire
Architecture
Heike Riel, IBM, Sinano Workshop, Seville (2010)
© IMEC 2015
GEERT ENEMAN
71
Comparison of Planar vs Nanowire
Architecture
Heike Riel, IBM, Sinano Workshop, Seville (2010)
© IMEC 2015
GEERT ENEMAN
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38
Nanowires
Nanowire advantages
Subthreshold slope vs gate length
Nanowire
FinFET
Si
 Excellent scalability, better
than fins or planar SOI
substrate 
 Robust against latch-up and
radiation
 Lowly-doped channels 
reduced random-dopant
fluctuation, good mobility
C. Hobbs, Sematech Symposium, 2011
© IMEC 2015
GEERT ENEMAN
73
Nanowires: Disadvantages
• Series resistance: more challenging than fins or SOI
• Current scales down with wire cross-section 
stacked wires required to have enough drive
• Processing: controlled etching of wires required.Topto-bottom wire variation?
• Can the channels be stressed?
• New sources of variability
Wire
Variability in Si nanowires
LExt,wire
Wire
radius
Gate
Source
Drain
Gate work
function
Spacer
Current
J. Zhuge, IEDM, p.61 ,
2009
Substrate
High-resistance
region
© IMEC 2015
GEERT ENEMAN
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39
Outline
 FinFETs
 Nanowires
• Properties, advantages and disadvantages
• Fabrication
• Design considerations
 Conclusions
© IMEC 2015
GEERT ENEMAN
75
Nanowire Fabrication
© IMEC 2015
GEERT ENEMAN
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40
Stacking nanowires helps increase total drive current to meet ITRS targets.
C. Hobbs, Sematech Symposium, 2011
© IMEC 2015
GEERT ENEMAN
77
© IMEC 2015
GEERT ENEMAN
78
41
Wires: More Design Considerations
Similarities to FinFETs:
 Lower S/D cap, lower parasitics to ground  Improved frequency
response
•
•
•
SOI-wires well resistors have no parasitic diode, lower capacitance
to ground
No well capacitance in SOI-wires
 No conventional diodes available in SOI-wires. Gated diodes are
an alternative.
 Poorer thermal response than fins. Self heating.
Bulk
SOI
A. Marshall & S. Natarajan, “SOI
Design: Analog, Memory and Digital
Techniques”, Springer, ISBN 0-79237640-4
© IMEC 2015
GEERT ENEMAN
79
Wires: More Design Considerations
 Potentially higher drive current per area than
planar
 Wire pitch (Pfin) and # of stacked wires are fixed
by process
 Discrete number of wires  quantized ‘device width’
 Gate-to-S/D parallel plate transistor worse than
fins  higher gate-to-source/drain (Miller)
capacitance
 Using back-bias for multi-VT is difficult
Ru Huang, WIMNACT
© IMEC 2015
GEERT ENEMAN
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42
Outline
 FinFETs
 Nanowires
 Conclusions
© IMEC 2015
GEERT ENEMAN
81
Conclusions
An overview is given of SOI, FinFET and
nanowire technologies and their difference
with planar FETs
Trade-off between scalability, better substrate
isolation/variability  wafer cost, process
complexity, access resistance, etc.
Circuit design with SOI/fins: similar to bulk,
however optimization is required between
technologies
Post-28nm nodes use UTB-SOI and FinFETs.
Post-14nm nodes: nanowires?
Thank you for your attention!
© IMEC 2015
GEERT ENEMAN
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43
© IMEC 2015
GEERT ENEMAN
83
44
Suman Datta, Penn State University
COMPOUND
SEMICONDUCTOR DEVICES
Conference Sponsors:
COMPUTATION PER KW-HR
2 X energy efficiency
increase every 1.5 years
Computing gets cheaper and energy efficient
45
VOLTAGE SCALING
I on = C gate veff (Vdd − Vth )
I off = I o10 −Vth / SS
Constant field scaling worked before
Recent years, voltage scaling has slowed down
CHALLENGES
I on = C gate veff (Vdd − Vth )
•
•
I off = I o10 −Vth / SS
increase veff
reduce SS
46
Drain Current, IDS [µA/µm]
SI CMOS
Intel 22nm
Simulation
1000
100
10 PMOS
NMOS
1
C. Auth et al VLSI 2012
0.1
Open Symbol: VDS=0.05V
Closed Symbol: VDS=0.8V
L =26nm
0.01 G
EOT=0.9nm
1E-3
-0.8
-0.4
0.0
0.4
0.8
Chipworks
Gate Voltage, VGS [V]
3D Continuum model (modified drift-diffusion and quantum corrected density
gradient approximation) captures Id-Vg
NMOS
PMOS
0.6
0.5
0.4
0.3
0.2
0.1
0.3
0.4
0.5
0.6
0.7
0.8
VCC [V]
Injection Velocity, vinj [x107cm/s]
Injection Velocity, vinj [x107cm/s]
INJECTION VELOCITY IN SI CMOS
0.6
0.5
0.4
0.3
0.2
NMOS
PMOS
0.1
2
4
Injection velocity in the range of 4 to 6 x106 cm/s
Carrier density in the range of 6 to 8 x1012 /cm2
47
6
8
Sheet Charge, ns [x1012 cm-2]
Quasi Ballistic FETs
High-k
High-k
“0.5V FETs with High Velocity Carriers at Low Field”
Quasi Ballistic FETs
48
III-V ON SI
Challenge: Lattice Mismatch
Solution: Metamorphic buffer architecture with large
effective bandgap
Device layers
III-V HEMTs on Silicon
Fully relaxed metamorphic buffer layer used for
epitaxial growth of In0.7Ga0.3As quantum well on
Silicon
M. Hudait, S. Datta et al, IEDM 2007
49
MOTIVATION
 Vinj for III-V devices higher than Si state-of-the-art
 Vinj for In0.53Ga0.47As FinFET device lower than HEMT
 Mulit-gate architecture required to maintain electrostatics
[1], [2] D H Kim et al, IEDM 2009 (MIT) [3] M Radosavljevic et al, IEDM 2011 (Intel) [4]
A Khakifirooz et al, TED 2008 [5] C Auth et al, VLSI 2012 (Intel 22nm Silicon)
But.……HEMTs are not scalable
SG-HEMT
SG-HEMT
Double gate is the only scalable option
50
Multi-Gate III-V FET
In0.53Ga0.47As
Channel
Au/Pd
Barrier
QW
Barrier
40nm
High-k
InP
In0.52Al0.48As
In0.7Ga0.3As
δ-doping
In0.52Al0.48As
In0.52Al0.48As Buffer
InP Substrate
High-k
Strained In0.7Ga0.3As
QW
M. Radosavljevic et al, IEDM 2011 (Intel)
D
L. Lu, S. Datta et al, IEDM 2010 (Penn St)
III-V FinFET combining superior transport with acceptable
short channel effects
MULTI-GATE III-V FET
Planar to multi-gate:
1. Side wall interface states (DIT): SS and Coulombic scattering
2. Etch induced side wall roughness: scattering
3. Quantum confinement: m* change
A V Thathachary et al, Nano Lett. 2014
51
SIDEWALL ROUGHNESS
 Side wall scattering dominates transport at lower fin width
III-V FF MOBILITY
 Gated Hall measurements show μ reduces with fin width for
multi-gate III-V devices
 Rate of mobility roll-off depends on composition and channel
architecture
52
INXGA1-XAS CHANNEL ARCHITECTURE
5 nm n+ In0.70Ga0.3As
10 nm n+ In0.53Ga0.47As
2nm InP
5 nm n++ In0.70Ga0.3As
5 nm n++ In0.70Ga0.3As
10 nm n+ In0.53Ga0.47As
10 nm n+ In0.53Ga0.47As
10 nm In0.53Ga0.47As
10 nm In0.70Ga0.3As
InP
InP
2nm InP
40 nm In0.53Ga0.47As
InP
2nm InP
n+ cap
InP
In0.53Ga0.47As Channel
In0.7Ga0.3As QW
In0.53Ga0.47As QW
 Three channel architectures chosen to study effect of
In % change and confinement
EFFECT OF VOLUME INVERSION
WFin = 40nm
WFin = 8nm
In0.53Ga0.47As
Bulk FinFET
In0.53Ga0.47As
QW FinFET
In0.53Ga0.47As
BulkFinFET
In0.53Ga0.47As
QWFinFET
In0.7Ga0.3As
QW FinFET
In0.7Ga0.3As
QWFinFET
 Majority inversion charge forms near the surface for
In0.53Ga0.47As Bulk FinFET at higher overdrive
 Volume inversion expected to significantly improve QW
channel performance
53
PROCESS FLOW
Drain
Channel
Drain
Source
n+ cap
channel
Buffer
S
GATE
D
Source
WFin
Fin patterning
n+ cap recess
(wet etch)
Drain
Source
1nmAl2O3/2.5nmHfO2
Gate metal lift-off
ALD High-k
S/D contact
REDUCING DIT: IN-SITU PLASMA NITRIDE
PASSIVATION
3 min clean in10:1 Buffered HF
+ DI rinse
In-situ plasma pre-clean and
passivation @ 250C
N2 plasma/TMA pulsing:
5 cycles + 10 cycles H2O pulsing
Ni
Gate
0.3 nm
AlOxNy
Interfacial
layer
In0.53Ga0.47As
Channel
1nm Al2O3 + 2.5nm HfO2 grown
@ 250C using
Thermal ALD process
70nm thermal Nickel
evaporation for gate metal
350C FGA for 20 mins
4nm
 Plasma AlOxNy passivation layer realized on InxGa1-xAs
54
PLANAR MOS CV
Thermal ALD
Plasma nitride passivation
+ thermal ALD
 CET of 1.3 nm measured at 1MHz
 Reduced frequency dispersion with FGA
MULTI-FIN SPLIT CV MEASUREMENT
 CET of 1.4nm measured for multi-fin split CV structure
55
EQUIVALENT CIRCUIT MODEL
 Measured conductance and capacitance fitted
iteratively using the equivalent circuit impedance
 Model self-consistently extracts distribution of DIT
A . Ali et al, IEEE TED 2010
DIT : EQUIVALENT CIRCUIT MODEL
 Equivalent circuit method used to extract DIT
56
EXTRACTED DIT
 Mid-gap DIT reduced to 1012/cm2/eV
 Fin sidewall DIT higher in conduction band
FINFET FABRICATON: XTEM
Ni Gate
1μm
20nm
In0.53Ga0.47As
38 nm
In0.52Al0.48As
Buffer
40 nm
120 nm
85 nm
 Chemical component of RIE enhanced
 Fin taper changed to 70ᵒ from 85ᵒ
57
High-k
LONG CHANNEL FINFET PERFORMANCE
Symbol: experiment
Line: simulation
Wfin = 40nm; LG = 1μm; 10 fins/μm
 SS improved from 180mV/dec to 100mV/dec
 DIT = 8x1012 estimated from calibrations and 2x1012
from equivalent circuit model
OUTPUT CHARACTERISTICS
Wfin = 40nm; LG = 1μm; 10 fins/μm
 Drive current increases with increasing In % and
quantum confinement
58
FIN MOBILITY
FinFET
Channel Type
Mobility
[cm2/Vs]
ns = 1x1012
cm-2
Bulk
In0.53Ga0.47As
1500
QW
In0.53Ga0.47As
2500
QW
In0.7Ga0.3As
3600
 Improved high-k interface with InxGa1-xAs allows
acurate estimation of charge
SHORT CHANNEL DEVICES: SEM
S
GATE
GATE
D
S
D
LG
LG =
120nm
InxGa1-xAs channel
n+ cap layer
Ni S/D metal
 Short channel devices with gate recess opening
down to 120nm realized
59
SHORT CHANNEL PERFORMANCE
Symbol: experiment
Line: simulation
Wfin = 40nm; LG = 120nm; 10 fins/μm
 New gate stack implemented on short channel devices
 Significant improvement in SS from >200mV/dec to
around 110mV/dec at Lg = 120nm
OUTPUT CHARACTERISTICS
Wfin = 40nm; LG = 120nm; 10 fins/μm
 Drive current measured at 75μA/fin at VG – VT = 0.6V for
In0.7Ga0.3As QW FinFET
60
TRANSCONDUCTANCE
FinFET
Channel Type
Peak gm
[μS/μm]
Bulk
In0.53Ga0.47As
490
QW
In0.53Ga0.47As
1012
QW
In0.7Ga0.3As
1786
Peak gm normalized
to 10 fins/μm
 Peak gm enhancement of 3.6x observed for QW In0.7Ga0.3As
Slide 33
FinFET over bulk In0.53Ga0.47As FinFET
SHORT CHANNEL SUMMARY
ION @
VG – VT = 0.6V
μA/μm
SS
VDS = 0.05V
mV/dec
gm peak
DIBL
In0.53Ga0.47As
Bulk
250
105
0.490
221
In0.53Ga0.47As
QW
In0.7Ga0.3As
QW
405
117
1.012
103
760
114
1.786
106
61
mS/μm
mV/V
GM VS. SS BENCHMARKING
[1] C Auth et al, VLSI 2012 (Intel) [2] M Radosavljevic et al, IEDM 2011 (Intel) [3] T W kim et al, IEDM
2013 (sematech) [4] S H Kim et al, IEDM 2013 [5] JJ Gu et al, IEDM 2012 [6] J Lin et al, IEDM 2012 [7] S
W Chang et al, IEDM 2013 (TSMC)
 Q factor improves with higher In % and quantum confinement
 Q = 15 measured for In0.7Ga0.3As QW FinFET
[1] C Auth et al, VLSI 2012 (Intel) [2] M Radosavljevic et al, IEDM 2011 (Intel) [3] T W kim et al, IEDM
2013 (sematech) [4] S H Kim et al, IEDM 2013 [5] JJ Gu et al, IEDM 2012 [6] J Lin et al, IEDM 2012 [7] S
W Chang et al, IEDM 2013 (TSMC)
62
G. Doornbos, M. Passlack
IEEE EDL 2010
[1] C Auth et al, VLSI 2012 (Intel) [2] M Radosavljevic et al, IEDM 2011 (Intel) [3]
T W kim et al, IEDM 2013 (sematech) [4] S H Kim et al, IEDM 2013 [5] JJ Gu et
al, IEDM 2012 [6] J Lin et al, IEDM 2012 [7] S W Chang et al, IEDM 2013 (TSMC)
INJECTION VELOCITY
 Vinj at virtual source extracted from simulations after
calibration to experiments
 Vinj estimated at 1.4x107 cm/sec for In0.7Ga0.3As QW short
channel FF at LG = 120nm
Planar HEMT: D H Kim et al, IEDM 2009 (MIT) Si FF: C Auth et al, VLSI 2012 (Intel)
63
PROJECTION: 7NM NODE
In0.53Ga0.47As Bulk
In0.53Ga0.47As QW
In0.7Ga0.3As QW
2.5x
Silicon FinFET
20
ID [µA/fin]
15
10
7nm Tech. Node
5 LG=16nm
WFIN=5nm
0
0.00
0.25
VG [V]
VDS=0.5V
0.50
 Drive current projected to be 2.5x higher for In0.7Ga0.3As QW FinFET
compared to silicon FF at VDS = 0.5V and fixed IOFF = 1nA/fin
Compound Semiconductor CMOS Challenge
Integrate III-V layers on large Silicon wafers
Develop reliable high-K dielectric compatible with III-V
Determine PFET (Ge) to go with NFET
Insertion at 7nm node or beyond. Meet LG < 15 nm and gate
pitch less than 45nm with Wfin < 5nm
III-V ballistic FETs will have to simultaneously meet multiple
requirements to be serious contenders as replacement for
today’s state of art strained Si, Hi-K/MG, Tri-Gate transistors
64
2D Channel Devices
Low-Dimensional Systems for Device Applications
J. Appenzeller
Purdue University & Birck Nanotechnology Center
West Lafayette, IN 47907
Conference Sponsors:
ESSDERC 2015, September 14, 2015 - Tutorial
1
Nano is not just small …
Some general observations on the topic of Nano Electronics:
Normally people hunt for high mobility values …
… that is why carbon nanotubes and later graphene
attracted so much attention!
Nano Electronics seems to still mainly focus on field-effect
transistors!
Understanding the unique properties of transport in nanosystems is “less catchy”!
2
65
Material
Bulk
Mobility
cm2/Vs
Bandgap
Effective
Mass
eV
m*/mo
GaN
Si
Ge
2,000
1,400
3,900
3.47
1.12
0.661
0.2
0.19
0.082
GaAs
InGaAs
InAs
InSb
8,500
12,000
40,000
70,000
1.424
0.74
0.354
0.17
0.067
0.041
0.023
0.014
graphene
100,000
0
0
( The numbers above are approximations that describe the trend - I do not claim them to be exact! )
3
effective mass
band gap
(off-state)
mobility
(on-state)
carrier concentration
(on-state)
4
66
Geometric screening
and Schottky barriers
5
Geometric screening
డమ థ ௫ǡ௬
డ௫ మ
+
డమ థ ௫ǡ௬
డ௬ మ
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ఘ
ఌ್೚೏೤
߶௚
Note that:
߶௚ = ߶௙ ൅
ொೄ
஼೚ೣ
y
߶௙
and
assume:
x
డథ ௫ǡ௬
డ௬
|y=0 = 0
߶ ‫ݔ‬ǡ ‫ ݕ‬ൌ ‫ܥ‬଴ ‫ ݔ‬+ ‫ܥ‬ଵ ‫ ݔ‬ήy + ‫ܥ‬ଶ ‫ ݔ‬ή ‫ ݕ‬ଶ
ߝ௕௢ௗ௬ ή ‫ܧ‬ௌ = ܳௌ
డథ ௫ǡ௬
డ௬
డమ థ ௫ǡ௬
డ௬ మ
ൌ ‫ܥ‬ଵ ‫ ݔ‬+ ʹ‫ܥ‬ଶ ‫ ݔ‬ή y = ʹ‫ܥ‬ଶ ‫ ݔ‬ή y
ൌ ʹ‫ܥ‬ଶ ‫ݔ‬
6
67
Geometric screening
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��
��
��
��
� � �� + �� ∙ y = �� ∙ y
� ��
��
7
Geometric screening
��
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��
��
+
��
|� �
��
� ��
=
�� ∙ �� =
��
��
��
��
-
=
��
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��
��
��
��
��
∙
�
=-
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∙
∙
��
��
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��
��
�� ∙��
=-
�
��
assume:
��
��
with
68
x
��
��
|y=0 = 0
� �� + �� ∙y + �� ∙ � �
��
��
��
y
��
� � �� + �� ∙ y = �� ∙ y
� ��
��
�� ∙ �� ∙
��
��
8
Geometric screening
Another way to see the relevance of  for device scaling
�� ∙
��
�∙��
��
> �� ∙
�� > �
��
�� ∙ �� ∙
�∙��
��
screening in bulk:
��
��
��
�� ∙ �� ∙
��
��
9
Geometric screening
Another way to see the relevance of  for device scaling
Consider:
tox=5nm, body=12, and ox=4:
��
�� ∙ �� ∙
tbody=1nm
��
��
��
�� ∙ �� ∙
��
��
ND�1�18cm‐3  WDM�25nm
UTB � 4nm
BULK � 20nm
UTB materials allow for aggressive channel length scaling!
69
10
Schottky barrier diodes
A simplified picture …
Assuming a perfect contact from the source and no
significant scattering contribution from the channel
11
Two back-to-back diodes result in “source limited” carrier
injection for large Vd and non-linear Id-Vd characteristics for
small Vd
70
12
��
Tunneling through SBs
was ignored since BULK
is too large
��
�� ∙ �� ∙
��
��
13
A simplified picture … to illustrate the difference between
BULK and UTB for device applications
Tunneling through SBs
is the distinguishing
aspect in nano-devices
since UTB is frequently
very small!
��
�� ∙ �� ∙
��
��
��
��
71
�� ∙ �� ∙
��
��
14
A simplified picture … to illustrate the difference between
BULK and UTB for device applications
ߣ௎்஻
Tunneling through Vgs-dependent SBs is the distinguishing
aspect in nano-devices since UTB is frequently very small!
15
Strong tunneling currents create linear output characteristics!
This is NOT an “Ohmic contact” since the transmission
through the “tunneling” SB is gate voltage dependent!
ߣ஻௎௅௄
BULK
ߣ௎்஻
UTB
16
72
Schottky barrier field-effect transistors
Simulated output characteristics of a ballistic UTB SB-FET
Carbon Nanotube (CN) Field-Effect Transistor (FET)
17
Experimental output characteristics of an SB-MoS2FET!
-2
10
(mA/m)
DS
I
0.3
L = 200nm
-4
10
-6
10
VDS = 0.2 V to 1.0 V
Step 0.2 V
-8
10
VGS = 1.0 V to 5.0 V
step 0.5 V
-8
-7
-6
V
-5
GS
(V)
-4
-3
I
tox = 20nm
-2
tMoS2 = 8nm
0.2
0.15
DS
(mA/m)
0.25
T = 300K
0.1
0.05
0
0
Sc - contacts
0.5
1
V
DS
(V)
1.5
2
2.5
planar gated
18
73
Simulated subthreshold characteristics of an UTB SB-FET
19
Experimental subthreshold characteristics of an SB-CNFET
L = 300nm
tox = 10nm
tCN = 1.8nm
T = 300K
Ti - contacts
planar gated
20
74
Simulated subthreshold characteristics of an n-CNFET
21
Understanding the impact of the SB on the inverse
subthreshold slope:
22
75
subthreshold slope:
S|�0 � �
��
�
ln 10
S�∝ �� ∝
��
�� ∙ ��
�� ∙ �� ∙
��
��
23
subthreshold slope:
S|�0 � �
��
�
ln 10
S�∝ �� ∝
��
76
�� ∙ ��
�� ∙ �� ∙
��
��
24
subthreshold slope:
S|�0 � �
��
�
ln 10
The voltage range over which the SB-regime occurs remains
(almost) unaffected by the value of !
25
The inverse subthreshold slope also contains information
about the SB height!
SB
SB
The SB height information is hidden in the voltage difference
between VFB and Vth!
26
77
SB
Smaller SB-values result in a
smaller tunneling-current-impacted
gate voltage window!
SB
The inverse subthreshold slope does not change with SB!
27
SB
In reality the entire inverse
subthreshold slope – including the
thermal branch – is often also
impacted by interface traps, making
the identification of VFB difficult!
78
SB
28
thermal emission
thermal assisted
tunneling
However, the actual SB-value can
be determined from the temperature
SB
dependence of the inverse
subthreshold slope since the T-dependences of the
thermal and the SB-regime are distinctly different!
29
Procedure for SB extraction:
+ Measure Id-Vgs as function of temperature
30
79
+ Create gate voltage dependent Arrhenius plots
31
+ Extract “apparent” barrier versus gate voltage
assuming thermal emission theory
32
80
+ Extract “apparent” barrier versus gate voltage
assuming thermal emission theory
+ Determine the “real” SB-height at VFB
SB
J. Appenzeller et al.,
PRL 92, 048301 (2004). 33
An example:
SB-FETs from MoS2
S. Das et al., Nano Letters 13, 100 (2013). 34
81
SB-FETs – MoS2
35
SB-FETs – MoS2
Various contact types to MoS2
The metal work
function does not
entirely determine
the Fermi-level
line-up to MoS2
36
82
SB-FETs – MoS2
Fermi-level pinning in MoS2
dSB/dM ~ 0.1
Rc-Sc ൎ 500 m
for tox=5nm
Si with silicide: 150 -m
37
Data extraction using
an analytical SB-model
38
83
But the Schottky barrier height cannot always be extracted
in this way:
39
SB-FETs – WSe2
10
0
10
-2
10
-4
Pd Contact
LCH = 1.0µm
WCH = 1.0µm
V
V
I
DS
(A/m)
in this way:
V
10
-6
-8
10
-40
V
V
WSe2
-30
-20
V
-10
V
0
GS
(V)
10
20
DS
DS
DS
DS
DS
DS
= -1.0 V
= -0.6 V
= -0.2 V
= 0.2 V
= 0.6 V
= 1.0 V
30
40
40
84
SB-FETs – WSe2
10
0
10
-2
10
-4
Pd Contact
LCH = 1.0µm
WCH = 1.0µm
V
V
I
DS
(A/m)
in this way …
V
10
-6
-8
V
V
WSe2
10
-40
-30
-20
V
-10
V
0
GS
(V)
10
20
DS
DS
DS
DS
DS
DS
= -1.0 V
= -0.6 V
= -0.2 V
= 0.2 V
= 0.6 V
= 1.0 V
30
40
… then more complete simulations are required to extract
band gap and Schottky barrier information …
41
An analytical SB model
Example “electron current”:
�
��
� � � �� dE
��
�
��
��
��
�� ∗ � � ��
��
��
��
��
� � �
1
�� ∗ ��
�
42
85
The impact of the Schottky barrier height on the on/offcurrent ratio:
For the same Eg, an apparently smaller on/off-current ratio is
obtained for a Fermi level alignment closer to midgap!
43
The impact of the geometric screening length on the transfer
characteristics of SB-FETs:
The smaller , the more symmetric ambipolar device
characteristics occur independent of the SB-height!
44
86
Related Publications (presenter’s choice):
1) J. Appenzeller et al., Field-modulated carrier transport in carbon
nanotube transistors, PRL 89, 126801 (2002).
2) J. Knoch et al., Impact of the channel thickness on the performance of
Schottky barrier metal-oxide-semiconductor field-effect transistors, APL
81, 3082 (2002).
3) Z. Chen et al., The role of metal-nanotube contact in the performance
of carbon nanotube field-effect transistors, Nano Letters 5, 1497
(2005).
4) J. Knoch et al., Physics of ultrathin-body silicon-on-insulator Schottkybarrier field-effect transistors, Appl. Phys. A 87, 351 (2007).
5) S. Das et al., High performance multilayer MoS2 transistors with
scandium contacts, Nano Letters 13, 100 (2013).
45
The tunneling fieldeffect transistor (TFET)
46
87
The quantum capacitance
In addition to the geometric screening length , also the
density of states in low-dimensional nanostructures can be
substantially different from conventional materials!
Cox Cq
Qtot
Ctot e

 g Cox  Cq
Cox


  g
Cox  Cq
0
f
Cq  e
{
Qtot
 0f
Cox
Cq
Cox  Cq :
 0f  0
Cq  Cox :
 0f   g
47
The quantum capacitance
Cox


  g
Cox  Cq
0
f
{
Cox  Cq :
 0f  0
Cq  Cox :
 0f   g
+ Since Cq can be very small in 1D structures, FETs become
band rather than charge controlled devices!
(even in the on-state)
+ SB devices are frequently found to operate in the quantum
capacitance limit (QCL)!
48
88
The tunneling field-effect transistor
Combining the advantages of low-dimensional systems:
+ Ultra-thin body
 UTB  thin tunneling barrier
+ Operation in the quantum capacitance limit
 one-to-one band movement
Develop a device concept that makes use of the
intrinsic properties of low-dimensional systems!
49
Simulated gate voltage response of a T-CNFET
p
i
n
The device on-state involves band-to-band tunneling!
50
89
Simulated gate voltage response of a T-CNFET
p
i
n
The device on-state involves band-to-band tunneling!
51
Thank you!
52
90

Novel Transistors – Beyond the Planar Silicon MOSFET

Transcription

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