technical paper

James E. Judd
Open Architecture (OA) S-Band Radar Demonstration
and Risk Reduction System for CG(X)
ABSTRACT
The technical and business benefits of open
systems have been clearly demonstrated in
commercial industries such as information
technology and telecommunications. While
modern defense systems have likewise begun
to realize the benefits of open architecture,
application has generally focused on the realtime and near real-time data processing,
software, and network infrastructure
technology. The extension of open
architecture to the high-end sensor (analog)
hardware and hard real-time digital signal
processing hardware and software is in
progress. Drawing on OA experience from
various naval radars, ground-based radars, and
internal investment, successful development
and testing of an Open Architecture S-Band
Radar Risk Reduction System which reduces
CG(X) technology risks while demonstrating
the viability of extending Open Architecture to
active phased array electronics, receivers,
waveform generators, and digital signal
processing has been accomplished. This paper
presents design overview information and test
results for the risk reduction activities targeted
to a future OA Radar for CG(X).
OA RADAR DEMONSTRATION
SYSTEM
Meeting anticipated mission and affordability
requirements of the CG(X) radar will likely
necessitate the maturation and de-risking of
key technologies, products, processes, and
business practices. This includes maturing
state-of-the-art component technology, proving
application of COTS products, ensuring
competitive sources of supply, validating OA
designs, practices, and business models, and
confirming performance, sizing, and cost
models.
Lockheed Martin has designated the Open
Architecture Radar System product, which is
currently being used for CG(X) radar risk
reduction, as the “Scalable Solid-State S-Band
Radar” (S4R). A fully operational engineering
development model (EDM) was developed on
internal investment funding and is installed at
the Lockheed Martin Joint Solid-State
Advanced Radar Center (JSSARC) in
Moorestown, NJ. The phased array and RF
processor shelter is shown in Figure 1.
Figure 1 - S4R Test Facility
All planned CG(X) radar demonstrations were
successfully conducted over the past 18months. These were specifically directed at
reducing CG(X) radar technology, system, and
cost risks in the following key areas:
Wide Band-gap Devices
Digital Beamforming (DBF)
Real-time Signal/Data Processing and
Software
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
Open Architecture Technology and
Business Model
In order to ensure technical and cost risk was
addressed at the CG(X) radar level, not just in
supporting technologies, a set of radar level
technical performance measures (TPM) and
design to cost targets (DTC) were established
based on anticipated mission requirements.
The specific S4R system configuration to
support CG(X) radar risk reduction, including
the number of array elements, receiver
channels, and processor cards, was selected to
be sufficient to validate performance and
provide straightforward TPM scaling. The
TPM and cost targets were then decomposed
and allocated to the subsystems engineering
teams.
The S4R configuration, developed specifically
for CG(X) radar risk reduction, consists of an
Open Architecture Electronically Scanned
Active Phased Array, an RF processor with
distributed high performance digital receivers,
a high performance waveform generator, a
COTS digital processor which performs the
real-time digital Beamforming, signal
processing, and radar control functions, a highspeed digital data recording and playback
system, a test & evaluation support system,
and a COTS radar display. A block diagram of
the CG(X) Radar risk reduction system is
shown in Figure 2.
Array
RF Processor
RF Data
Digital Data
Control Network
Open Architecture Electronically
Scanned Active Phased Array
The S4R system uses an Open Architecture
Scaleable S-Band Electronically Scanned
Active Phased Array. The array employs the
modular building-block design structure shown
in Figure 3 which provides array scalability
ranging from approximately 5.5 feet to over 20
feet. This allows a common array architecture
design to meet mission needs while supporting
installation and cost constraints for multiple
ship classes including LCS, DDG 1000, CG
47, DDG 51, and future CG(X).
Repeating
“Building
Block”
Section
Air &
Missile
Defense
Radar
Air
Defense
Radar
Digital
Processor
Receiver
Channels
DBF Signal
Processor
Waveform
Generator
Radar Control
Processor
Radar
Display
corridor using radar waveforms, and digital
beamforming, signal processing, scheduling,
and tracking algorithms and software which
support many of the anticipated CG(X) Radar
requirements.
High-Speed
Digital
Recorders
Test & Evaluation
Support System
Common
Architecture
& Line
Replaceable
Unit (LRU)
Littoral
Combat
Radar
Figure 3 - Scalable Array Architecture
Figure 2 – OA CG(X) Radar Risk Reduction
System Block Diagram
The risk reduction system is a fully functional
digital beamforming Radar which has been in
operation since June 2007. The Radar detects
and tracks military and civilian air traffic in the
Philadelphia / New Jersey / New York air
Two versions of the scalable array have been
built and tested to date. The first is the twelve
foot DDG1000 Volume Search Radar (VSR)
EDM array which is currently supporting landbased testing. The second is the six foot S4R
array which is part of the CG(X) Radar Risk
reduction system.
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
OA Line Replaceable Unit (LRU)
As shown in Figure 3, the S4R OA array uses
modular building blocks designated as Line
Replaceable Units (LRU) to package the
transmit / receive (T/R) devices, array power
supplies, and control electronics.
As shown in Figure 4, the LRU is an OA
design which accommodates a variety of high
power amplifier device technologies, including
High Voltage Gallium Arsenide (HVGaS),
Silicon Carbide (SiC), and Gallium Nitride
(GaN), from multiple suppliers. This allows
the device technology selection to be made on
the basis of overall radar performance
requirements, technology maturity, risk
assessments, cost, and competitive analysis
without redesigning the LRU. Lockheed
Martin has developed and successfully tested
LRU designs using HVGaS and SiC
Technology.
Interchangeable
High Power
Modules
Martin is using design-to-specification and
build-to-print competition to exploit available
industry power supply technology to reduce
production costs.
Flexible Array Socket
Another basic building block of the S4R OA
Phased Array is the Flexible array Socket.
This socket is designed to accommodate LRU
designs supporting low cost, low power Radars
up through systems requiring objective CG(X)
radar power levels.
In additional to allowing a single array design
to support a broad range of applications, ship
classes, and missions, the flexible socket
concept supports an evolutionary acquisition
strategy by allowing “minimal impact” future
technology insertion which expedites new
capability to the fleet. An in-service array can
receive an on-ship upgrade to newer higherpower technology though an in-place LRU
replacement.
Array Beamformer Architecture
The Scaleable S-Band Array is designed to
support both analog and digital beamforming
(DBF). The analog beamforming design is
used in the VSR EDM array while the DBF
architecture is used in the S4R demonstrator.
Array Control Architecture
Interchangeable
Power Supplies
Figure 4 - Line Replaceable Unit (LRU)
Array Power Supplies
A significant portion of the total cost of an
active phased array radar system is in the array
power supplies. Therefore, an open technical
and business approach for procuring these
power supplies, which exploits commercial
technology and fosters competition, is critical
to achieving affordability requirements. As
shown in Figure 4, the OA LRU is designed to
accept modular power supplies which meet
form, fit, and function specifications from any
supplier. After successfully building power
supplies for both VSR and S4R, Lockheed
The Scaleable S-Band Array uses an on-array
beam-steering and control architecture. This
reduces cost, conserves deck space, and
isolates the internal operation and timing of the
array from the other radar subsystems allowing
“firewall modularity”.
RF Processor
The S4R RF processor uses a Modular
Scaleable architecture which allows the radar
system to scale from a traditional monopulse
configuration to the full digital beamforming
configuration used in the S4R demonstrator.
Common RF Modules
The RF processor uses three basic building
block modules: a digital receiver module, a
digital waveform generator (exciter) module,
and a synchronizer-controller module. These
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
modules were developed on other programs
and reused without modification in the S4R
demonstrator. Although these modules
achieve very high performance, they use lowcost COTS components throughout and are
designed for low-cost manufacturing using
automated surface-mount assembly lines. The
common RF modules use an industry-standard
9U form factor.
The digital receiver module accepts S-Band
input and outputs complex digital data over a
10 GIGE optical interface. The digital
waveform generator module is a direct digital
synthesizer (DDS) based waveform generator
which accepts digital command input and
outputs S-Band waveforms. The synchronizercontroller (SC) module provides the precision
timing and control functions for the RF
processor. Multiple SC modules can be slaved
to an SC module configured as a master
controller.
The SC module accepts a COTS processor on
an industry-standard PCI Mezzanine Card
(PMC) which provides the embedded control
functionality and the interface to the GIGE
control network. The embedded control
processor isolates the internal operation and
timing of the RF processor from the other
Radar subsystems again providing “firewall
modularity”.
RF Processor Configuration
To
Sub-Arrays
From
Sub-Arrays
Calibration Network
The scalable RF processor is configured as
shown in Figure 5.
Dual
DualUpConv
UpConv
Dual UpConv
REC
Dual UpConv
Dual
DualUpConv
UpConv
Dual UpConv
Dual
DualUpConv
UpConv
Data To Digital
Processor
REC
WFG
SC (Slave)
SC (Master)
Control & Status To &
From Digital Processor
SC (Slave)
Figure 5 - RF Processor Block Diagram
Each SC module accepts high-level command
information from the digital processor over the
GIGE control network. The command and
precision timing information is then transferred
to the associated receiver or waveform
generator module. This highly distributed
control architecture is readily scalable to a fullsize tactical CG(X) radar system.
The waveform generator module accepts a
high-level command from the SC module
which causes it to generate the commanded SBand RF waveform and send it to the array.
Each receiver module accepts an S-Band RF
signal from a sub-array channel in the array,
performs the down-conversion to baseband,
and it converts to digital data for transfer to the
Digital Processor over the 10 GIGE optical
interface.
Digital Processor
The S4R Digital Processor is a heterogeneous
COTS processor which employs a mix of Field
Programmable Gate Array (FPGA) nodes,
DSP nodes, and General Purpose Processing
nodes interconnected on a high-speed, low
latency, open standard network. The Digital
Processor hosts Digital Beamforming, DSP,
and Radar Control Open Architecture (RCOA)
software.
Digital Beamforming
The real-time digital beamforming processing
is implemented using COTS FPGA cards in
the digital processor. The sub-array sensor data
from the digital receivers in the RF processor
is transferred directly to the FPGA nodes using
10 GIGE interfaces. Each FPGA node
executes a digital filtering function to equalize
and align the input channel, performs a
bandwidth reduction function, and generates a
complex weighted sum of the associated input
channels. The summation is performed by
transferring the weighted results to adjacent
FPGA processing nodes with each node
contributing the weighted sum of the channel
to which it is connected. The partial sums are
then flowed to subsequent adjacent FPGA
processing nodes, until all beam contributors
are weighted and summed. This partial beam
summing function uses dedicated Xilinx
RocketIO interfaces on each FPGA processing
nodes. This reduces the impact of the high
DBF I/O bandwidth on the rest of the digital
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
signal processor by keeping intermediate DBF
data off of the internal network. The DBF
architecture is shown in Figure 6.
DPD/FIR
DBF
I/F
DPD/FIR
DBF
Beams To
Digital Signal
Processing
From Sub-array
N and N+1
COTS FPGA Node
I/F
From Sub-array
3 and 4
COTS FPGA Node
COTS FPGA Node
From Sub-array
1 and 2
I/F
DPD/FIR
DBF
Beams To
Digital Signal
Processing
Table 1 S4R Open Interfaces (System Level)
Interface Description
Type
Control Network
1 GIGE
Digital Data
10 GIGE
High Speed Recorder
FibreExtreme
Software
The software in the S4R demonstrator is built
with the following Open Architecture features:
It employs a loosely coupled, messagebased, distributed component architecture
It uses standards-based technology,
Application Programmer Interfaces (API)
and Libraries, including ANSI C++,
POSIX, VSIPL++, MPI, VHDL, and OCP
It abstracts the applications from the
underlying operating system and platform
through the use of a layered architecture
and standards-based APIs.
Figure 6 – S4R DBF Architecture
At the completion of DBF processing, the
beam data is queued in the FPGA memory for
transfer over the low latency network to the
General Purpose Processing nodes which
perform the balance of the digital signal
processing.
The S4R software component architecture is
shown in Figure 7.
Digital Signal Processing
The digital signal processing is designed and
performed for a waveform suite which is
consistent with the expected CG(X) Radar
multi-mission requirements. It includes
interference mitigation, waveform processing,
and detection processing.
Simulation,
FD/FI and
Calibration
Threat
Characterization
Track
Processing
Resource
Manager/
Adaptation
Open Middleware, Standard Libraries, and Common Services
DREX &
T/R Module
Control
Digital
Beamformer
Interference
Mitigation
Waveform&
Detection
Processing
Control and Track Processing
The real-time radar control, scheduling, and
track processing uses the Radar Control Open
Architecture (RCOA) product which is
designed to directly support or readily extend
to the expected CG(X) Radar multi-mission
requirements.
Open Interfaces
All major interfaces in the S4R demonstrator
use widely available industry standards such as
GIGE. All messages are well-defined and
documented in detailed specifications. The
interface design provides “firewall modularity”
for all subsystems. The major interfaces are
identified in Table 1.
Figure 7 – Software Component Architecture
Vector/Signal/Image Processing Library
(VSIPL++)
The signal and data processing algorithms are
coded using the open industry standard
Vector/Signal/Image Processing Library
(VSIPL++). The library is a high-level C++
API for parallel high-performance signal and
image-processing and includes operations such
as FFT, filters, linear system solvers, and other
functions useful in developing radar, sonar,
communication, and imaging processing
applications. The VSIPL++ API is managed
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
by the High Performance Embedded
Computing Software Initiative (HPEC-SI) a
consortium of industrial, academic, and
government partners, with sponsorship from
the DOD.
The VSIPL++ software used in the S4R
demonstrator is a commercial product from an
innovative small business which is optimized
for the real-time platform. Prior to the
selection of VSIPL++, performance and code
size benchmarking was performed. As shown
in Figure 8, the VSIPL++ real-time
performance compares favorably to highly
optimized vendor proprietary libraries.
Figure 8 - VSIPL++ Benchmark Example
Studies, performed using actual CG(X) radar
signal processing algorithms, indicate that use
of VSIPL++ provides a code size reduction of
as much as 6-to-1 compared to implementing
the same function with vendor proprietary
libraries.
processors, servers, parallel signal processors,
and supercomputers.
The MPI used in the S4R demonstrator is a
commercial product from an innovative small
business which is optimized for the real-time
platform. However, all of the application
software was developed and tested on UNIX
workstations using an Open Source version of
MPI and ported to the real-time target system
without modification.
RESULTS
The S4R demonstrator is a fully functional
DBF radar which has been in operation since
June 2007. The use of model-based design,
application of COTS products and open
standards, and reuse of existing NDI hardware
and software components resulted in shorter
design cycle times, many more first pass
successes, far fewer defects in radar system
test, and significantly shorter system
integration times when compared to metrics
for prior systems. The reduction in overall
development cycle time is noteworthy.
The complex real-time digital beamforming
software worked as designed when delivered
to radar system integration. A live S4R
composite beam pattern for the seven beam
rosette used for tracking is shown in Figure 9.
Message Passing Interface (MPI)
All control message distribution, interprocessor communication, and data
distribution uses the Message Passing Interface
(MPI). MPI is a language independent API,
protocol, and semantic specification used to
program parallel computers. It provides pointto-point message passing and collective
(global) operations to user specified groups of
processors. It is considered the de facto
standard API for communication in a parallel
program running on distributed processors.
Many high-performance commercial products
and free open source implementations are
available for networked commodity
Figure 9 - Live Seven Beam Rosette Pattern
The first live DBF track occurred only 21 days
after delivery of the DBF signal processor to
the radar test facility. The system is currently
tracking military and civilian air traffic in the
Philadelphia / New York air corridor. The live
radar display is shown in Figure 10.
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.
PLAN FORWARD
The S4R Demonstration will remain in
operation for the next few years in support of
the road to CG(X). Current plans include the
following:
Figure 10 – Live Display from OA CG(X) Radar
Demonstrator
Measurements and analyses have been
performed to assess the performance of the
S4R Demonstrator against the set of system
level Technical Performance Measures (TPM)
that was established prior to the design of the
system. To date, all of the key Technical
Performance Measures have been successfully
achieved as delineated in Table 2.
In-system test and evaluation of next
generation device technologies, such as
High Voltage Gallium Arsenide (HVGaS),
Silicon Carbide (SiC), and Gallium Nitride
(GaN), from multiple suppliers.
In-system test and evaluation of COTS and
NDI digital receiver and waveform
generator technology from third party
suppliers.
In-system test and evaluation of NDI
digital beamforming hardware and
algorithms from third party suppliers.
In-system test and evaluation of signal
processing, threat characterization, and
multi-mission algorithms and software
from on-going programs, small businesses,
and university partners.
CONCLUSION
Performance Measure
Initial Status
Beam Patterns
Achieved
Dynamic Range
Achieved
Noise Figure
Achieved
In summary, the S4R Demonstrator has been
an unqualified success. It has and will continue
to support CG(X) Radar Technology
evaluation, maturation, and risk reduction. It
will help to ensure the lowest risk, best
technology, and best value offering for the
CG(X) Radar.
Third Order Intercept (TOI)
Achieved
____________________________________
Clutter Improvement Factor
Achieved
Interference Mitigation
Achieved
Angle Measurement Accuracy
Achieved
Channel Synchronization
Achieved
Channel Alignment
Achieved
Processing Latency
Achieved
James E. Judd is the Director of Computer
and Digital Systems Engineering at Lockheed
Martin MS2, Moorestown, NJ. Mr. Judd has
BSEE from Drexel University and has over 25
years of experience in the design and
development of real-time signal and data
processors for military radar and sonar
systems.
Event Throughput
Achieved
Table 2 – Key Technical Performance Measures
Copyright © 2008 All Rights Reserved by the Lockheed Martin Corporation.