Leopard 3 Block Diagram
Transcription
Leopard 3 Block Diagram
A CLK GEN B C D Leopard 3 Block Diagram 3 Project code: 91.4C901.001 PCB P/N : 48.4C901.001 REVISION : 05205-1 4,5 ICS954206AG E Mobile CPU SYSTEM DC/DC 36 MAX1999 INPUTS OUTPUTS 5V_S3 DCBATOUT 3V_S5 Dothan 4 1394 Conn 4 26 11,12 DDR2*2 533MHz 24 22 INPUTS OUTPUTS 1D05V_S0 6,7,8,9,10 CARDBUS 1394 SD/MS/MMC/SM SD/MS 24 6 in 1 Card Slost TPS5130 DCBATOUT PCI7411 Power Switch TPS2220A 37 Host BUS 400/533MHz 22,23 PCMCIA 1 SLOT SYSTEM DC/DC LVDS LCD Alviso 1D8V_S3 13 SVIDEO/COMP GM 1D2V_S0 14 MAXIM CHARGER 34 TVOUT MAX1909 INPUTS RGB CRT DMI I/F 100MHz 3 29 Mini-PCI 802.11a/b/g OUTPUTS BT+ CRT DAUGHTER BOARD DCBATOUT BLUE THUMB 18V 4.0A 5V 100mA 3 16,17,18,19 26 25,26 RJ45 CONN 10/100 RTL8100C 35 PCI BUS P IDE ICH6-M MASTER HDD 21 MODEM MDC Card AC97-LINK DCBATOUT DVD/ 21 CD-RW SLAVE 0.844~1.3V 27A 21 MIC IN13 2 OUTPUTS VCC_CORE 30 25 MAX1907 INPUTS PCI EXPRESS/ USB2.0 EXPRESSCARD 27 AC'97 CODEC AD1981B PCB LAYER LPC Bus LINE OUT 28 OP AMP G1420BF3U Docking 2CH SPEAKER 31 13 KBC NS97551 29 Comsumer IR 1 LPC 33 Debug Conn X-BUS 31\ Touch Pad 31 Int. KB 19 Thermal & Fan G768D 21 Power Switch TPS2231 L1: Signal 1 L2: GND L3: Signal 2 L4: Signal 3 L5: VCC L6: Signal 4 32 4Mb (512kB) 1 tm ai l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Block Diagram Date: Tuesday, July 19, 2005 B C D Leopard 3 Sheet E Rev of 41 in Document Number -1 xa Size A3 f@ ho Title A 2 FlashRom 1 he RJ11 CONN CPU DC/DC USB x 2 USB x 2 30 USB 2.0 A B ICH6-M Integrated Pull-up and Pull-down Resistors ICH6-M EDS 14308 0.8V1 D E Power name description 5V_S0= 5 Voltage power up on system work(S0 state) ACZ_BIT_CLK, DPRSLP#, EE_DIN, 5V_S3= 5 Voltage suspend to RAM(S3 state) EE_DOUT, EE_CS, GNT[5]#/GPO[17], ICH6 internal 20K pull-ups 4 C GNT[6]#/GPO[16], LDRQ[1]/GPI[41], 5V_S5= 5 Voltage soft off(S5 state) 4 3D3V_S0= 3.3 Voltage power up on system work(S0 state) LAD[3:0]#/FB[3:0]#, LDRQ[0], 3D3V_S3= 3.3 Voltage suspend to RAM(S3 state) PME#, PWRBTN#, TP[3] 3D3V_S5= 3.3 Voltage soft off(S5 state) LAN_RXD[2:0] ICH6 internal 10K pull-ups ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs LVDDR_1D8V= 1.8 Voltage power up on system work(S0 state) 1D8V_S3= 1.8Voltage suspend to RAM(S3 state) 2D5V_S0= 2.5 Voltage power up on system work(S0 state) ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR, SPKR VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state) USB[7:0][P,N] ICH6 internal 15K pull-downs DD[7], SDDREQ ICH6 internal 11.5K pull-downs LAN_CLK ICH6 internal 100K pull-downs 1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S0= 1.5 Voltage power up on system work(S0 state) 1D5V_S5= 1.5 Voltage soft off(S5 state) DDR_VREF_S3= 0.9 Voltage suspend to RAM(S3 state) 0D9V_S0= 1.25 Voltage power up on system work(S0 state) 1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA 3 3 1D05V_S0= 1.05 Voltage power up on system work(S0 state) ICH6-M IDE Integrated Series Termination Resistors CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power DD[15:0], DIOW#, DIOR#, DREQ, approximately 33 ohm DDACK#, IORDY, DA[2:0], DCS1#, DCS3#, IDEIRQ PCI RESOURCE TABLE 2 DEVICE IDSEL PCI IRQ REQ# / GNT# Mini-PCI AD21 P_INTE# REQ0#/GNT0# Cardbus Controller TI7411 LAN Blue Thumb (CARBUS)P_INTG# (1394)P_INTF# AD22 (CARD READER)P_INTG# REQ1#/GNT1# AD23 REQ2#/GNT2# P_INTE# 2 AD24 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ITP Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 2 of 41 A B 3D3V_S0 C D E 3D3V_S0 3D3V_S0 R114 3D3V_48MPWR_S0 3D3V_S0 C155 SCD1U16V DY R118 10KR2 2 DY 3D3V_S0 DummyR118(up side),Mounting R125(down side) --SRC7 on 4 1 ITP_EN DY Mounting R118(up side),DummyR125(down side) --CPU2_ITP on DY DY 2 DY R125 10KR2 C382 SCD1U16V 2 C361 SCD1U16V 2 C372 SCD1U16V 1 1 1 C379 SCD1U16V 2 C378 SCD1U16V 2 C371 SCD1U16V 1 1 1 C374 SCD1U16V 2 C362 SC10U10V6ZY-U 2 2 1 3D3V_CLKGEN_S0 1 L34 2 MLB-201209-11 1 2 4 3D3V_S0 1 C154 SC4D7U10V5ZY 2 C373 SCD1U16V 2 C156 SC4D7U10V5ZY 5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 1 1 2 4D7R3 1 1 L17 1 2 2 3D3V_APWR_S0 MLB-201209-11 2 1 3D3V_S0 20,36 CLK_PWRGD# 1 3D3V_APWR_S0 3D3V_48MPWR_S0 2 C380 SC22P 3D3V_CLKGEN_S0 2 CLK_XIN X6 X-14D31818M-17 2 31 PCLK_KBC 17 PM_STPPCI# CPUCLKT0 CPUCLKT1 CPUCLKT2_ITP/SRCCLKT7 44 41 36 CLK_CPUT0 CLK_CPUC0 1 2 FSLA/USB_48MHZ FSLB/TEST_MODE 12 16 FS_A SRN33-2-U2 96MHZ_SSC/SRCCLKC0 96MHZ_SST/SRCCLKT0 18 17 CLK_SRCC0 CLK_SRCT0 RN56 DOTC_96MHZ DOTT_96MHZ 15 14 DOT96C DOT96T CLK_ICHPCI 2 SS_SEL 22R2 2 33R2 ITP_EN R113 FS_A 2 10KR2 2 2 2 R466 33R2 1 R123 33R2 1 R124 33R2 1 CLK_CPU_BCLK TP87 TPAD30 CLK_CPU_BCLK# TP88 TPAD30 close to CPU 2 DY FS_C FS_B FS_A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2 22 DREFSSCLK# 7 DREFSSCLK 7 33R2 33R2 DREFCLK# 7 DREFCLK 7 1 CLK_PCIE_NEW 1 CLK_PCIE_NEW# 1 CLK_XDP_CPU 1 CLK_XDP_CPU# 1 CLK_CPU_BCLK 1 CLK_CPU_BCLK# 1 CLK_MCH_BCLK 1 CLK_MCH_BCLK# 1 DREFSSCLK 1 DREFSSCLK# 1 CLK_MCH_3GPLL 1 CLK_MCH_3GPLL# 1 ICS954206AG Spread Spectrum Select Spread Amount% SS2 SS1 SS0 0 0 0 0 -0.8 0 0 0 1 -1.0 0 0 1 0 -1.25 CLK_PCIE_ICH 1 0 0 1 1 -1.5 CLK_PCIE_ICH# 1 0 1 0 0 -1.75 0 1 0 1 -2.0 0 1 1 0 -2.5 0 1 1 1 -3.0 1 0 0 0 +-0.3 1 0 0 1 +-0.4 1 0 1 0 +-0.5 Wistron Corporation 1 0 1 1 +-0.6 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 1 0 0 +-0.8 1 1 0 1 +-1.0 1 1 1 0 +-1.25 1 1 1 1 +-1.5 2 R444 49D9R2F 2 R443 49D9R2F 1 CPU 266M 133M 200M 166M 333M 100M 400M Reserved 2 R450 49D9R2F 2 R457 49D9R2F 2 R441 49D9R2F 2 R442 49D9R2F SS3 Title Clock Generator (ICS954206AG ) Size A3 Document Number Leopard 3 Date: Monday, August 15, 2005 A 2 R520 49D9R2F 2 R521 49D9R2F 2 R451 49D9R2F 2 R452 49D9R2F 2 R470 DY 49D9R2F 2 R465 DY 49D9R2F 2 R461 49D9R2F 2 R464 49D9R2F 2 R463 49D9R2F 2 R462 49D9R2F l.c 1 REQSEL R526 DUMMY-R2 SRN33-2-U2 R117 2 1 R116 2 1 PCLK_PCM 22 PCLK_LAN 25 PCLK_MINI 29 2 1 SB CLK48_USB 17 CLK48_CARDBUS CPU_SEL1 4,7 1 DREFCLK# 2 3D3V_CLKGEN_S0 R525 10KR2 R459 2 10R2 2 33R2 R460 DREFCLK ai 1 SD 0817 1 1 4 3 R115 1 475R2F NEAR CLKGEN 3D3V_S0 1 2 CLK_CPU_BCLK 4 CLK_CPU_BCLK# 4 ICS954206AG CLK_PCI3 CLK_PCI4 CLK_PCI5 3 CLK_XDP_CPU# 4 CLK_XDP_CPU 4 SRN33-2-U2 RN59 4 3 REQSEL R126 1 3 4 DY tm 17 1 1 42 37 11 48 2 1 CLK_IREF 2 R458 1 VDDCPU VDDA VDD48 VDDREF 7 1 34 28 21 10 51 45 29 13 6 2 38 GND GND GND GND GND GND GNDA 11,19 SMBC_ICH 11,19 SMBD_ICH CLK_CPUC2 CLK_CPUT2 B C D om 1 2K2R2 PM_STPCPU# 17,36 RN60 54 43 40 35 ho R522 2 CPU_SEL0 REF0 REF1/FSLC/TEST_SEL SCLK SDATA SRN33-2-U2 DY Sheet E f@ 4,7 52 53 46 47 R455 10KR2 CLK_MCH_BCLK 6 CLK_MCH_BCLK# 6 Rev of 41 -1 in PREQ2# 17 CLK_ICH14 27 CLK_CODEC SRCCLKT1 SRCCLKT2 SRCCLKT3 SRCCLKT4_SATA SRCCLKT5 SRCCLKT6 VDDPCI VDDPCI X2 X1 SRN33-2-U2 CLK_SRCT6 1 DY 0R2-0 0R2-0 CLK_SRCC6 1 CLK_REF14 DY R468 1 2 22R2 R467 1 22R2 2 TP_SRCC6 R523 2 TP_SRCT6 R524 2 19 22 24 26 31 33 4 3 CPU_STOP# CPUCLKC0 CPUCLKC1 CPUCLKC2_ITP/SRCCLKC7 9 55 8 5 4 3 56 39 21 CLK_SRCC5 CLK_SRCT5 1 2 3 xa TPAD30 TP57 TPAD30 TP56 4 3 SRN33-2-U2 RN41 1 2 CLK_SRCC3 CLK_SRCT3 SRCCLKC1 SRCCLKC2 SRCCLKC3 SRCCLKC4_SATA SRCCLKC5 SRCCLKC6 RN61 CLK_CPUC1 CLK_CPUT1 he 17 CLK_PCIE_ICH# 17 CLK_PCIE_ICH 4 3 SRN33-2-U2 RN40 1 2 20 23 25 27 30 32 SS_SEL SEL100_96MHZ#/PCICLK_F1 PCI/SRC_STOP# ITP_EN/PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 IREF 7 CLK_MCH_3GPLL# 7 CLK_MCH_3GPLL CLK_SRCC1 CLK_SRCT1 1 2 VDDSRC VDDSRC VDDSRC 4 3 21 CLK_PCIE_NEW# 21 CLK_PCIE_NEW VTT_PWRGD#/PD 49 50 1 RN58 3 H/L: 100/96MHz U57 2 C381 SC22P 1 R453 10KR2 CLK_XOUT 2 1 A B C D E VCCP_GMCH_S0 5,6,7,9,10,16,18,36,40,41 J2 1 2 B11 H1 K1 L2 M3 H_INIT# H_RS#0 H_RS#1 H_RS#2 6 U45B H_D#[63..0] H_HIT# H_HITM# 6 6 VCCP_GMCH_S0 BPM#0 BPM#1 BPM#2 BPM#3 PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# C8 B8 A9 C9 A10 B10 A13 C12 A12 C11 B13 A7 PROCHOT# THERMDA THERMDC B17 B18 A18 THERMTRIP# C17 A15 A16 B14 B15 ITP_CLK1 ITP_CLK0 BCLK1 BCLK0 R285 56R2J VCC_CORE_S0 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# DBR# R16 150R2 6 6 6 CPU_PROCHOT# PM_THRMTRIP-I# 7,16 CLK_XDP_CPU# 3 CLK_XDP_CPU 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 PM_THRMTRIP# should connect to ICH6 and Alviso without T-ing ( No stub) ITP Conn. Dothan A: R43,R44=DUMMY Dothan B: R43,R44=0R 2 H_DSTBN#0 H_DSTBP#0 H_DINV#0 THERMDP1 20 THERMDN 20 PM_THRMTRIP-A# 7,16 PZ47903 CPU H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_TRDY# 6 K3 K4 HIT# HITM# 16 H_LOCK# 6 H_CPURST# 6 H_RS#[2..0] 6 6 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1 TPAD30 TP3 TCK(PIN 5) 3,7 3,7 0R0402-PAD 1 R273 2 1 R276 2 CPU_SEL0 CPU_SEL1 PSI# CPU_SEL0_CPU CPU_SEL1_CPU A19 A25 A22 B21 A24 B26 A21 B20 C20 B24 D24 E24 C26 B23 E23 C25 C23 C22 D25 62.10055.011 D0# D32# D1# D33# D2# D34# D3# D35# D4# D36# D5# D37# D6# D38# D7# D39# D8# D40# D9# D41# D10# D42# D11# D43# D12# D44# D13# D45# D14# D46# D15# D47# DSTBN0# DSTBN2# DSTBP0# DSTBP2# DINV0# DINV2# Y26 AA24 T25 U23 V23 R24 R26 R23 AA23 U26 V24 U25 V26 Y23 AA26 Y25 W25 W24 T24 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H23 G25 L23 M26 H24 F25 G24 J23 M23 J25 L26 N24 M25 H26 N25 K25 K24 L24 J26 D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1# AB25 AC23 AB24 AC20 AC22 AC25 AD23 AE22 AF23 AD24 AF20 AE21 AD21 AF25 AF22 AF26 AE24 AE25 AD20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 E1 C16 C14 0R0402-PAD TPAD30 TPAD30 TPAD30 TPAD30 VCCP_GMCH_S0 VCCP_GMCH_S0 TP1 TP5 TP6 TP38 1 2 XDP_TDO 2 CPU_PROCHOT# 2 XDP_TDI 1 XDP_TMS 1 XDP_TRST# 1 XDP_TCK 1 CPU_TP3 CPU_TP4 CPU_TP5 CPU_TP6 2R23 1KR2F GTLREF R22 2KR2F C3 AF7 AC1 E26 AD26 RSVD2 RSVD3 RSVD4 RSVD5 GTLREF0 Layout Note: 0.5" max length. 1R283 54D9R2F 1R275 54D9R2F 1R274 56R2J 2R277 150R2 2R279 39D2R2F 2R278 680R2 2R280 27D4R2F COMP0 COMP1 COMP2 COMP3 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# G1 B7 C19 E4 A6 TEST1 TEST2 C5 F23 Layout Note: Comp0, 2 connect with Zo=27.4 ohm, make trace length shorter than 0.5" . Comp1, 3 connect with Zo=55 ohm, make trace length shorter than 0.5" . H_DSTBN#3 6 H_DSTBP#3 6 H_DINV#3 6 COMP0 COMP1 COMP2 COMP3 R302 R301 R25 R24 1 1 1 1 2 2 2 2 27D4R2F 54D9R2F 27D4R2F 54D9R2F 2 VCCP_GMCH_S0 R288 200R2J H_DPRSLP# 16 H_DPSLP# 16 H_DPWR# 6 H_PWRGD 16 H_CPUSLP# 6,16 TEST1 TEST2 R18 1KR2 R284 1KR2 DY BSEL[1:0] Freq.(MHz) LH 100 LL 133 3 H_DSTBN#2 6 H_DSTBP#2 6 H_DINV#2 6 PZ47903 2 H_CPURST# BSEL0 BSEL1 1 1 PSI# P25 P26 AB2 AB1 MISC TCK(PIN A13) FBO(PIN 11) D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3# 6 1 STPCLK# LINT0 LINT1 SMI# LOCK# 2 C6 D1 D4 B4 H_STPCLK# H_INTR H_NMI H_SMI# IERR# INIT# Place testpoint on H_IERR# with a GND 0.1" away H_IERR# 1 16 16 16 16 A20M# FERR# IGNNE# H_BREQ#0 6 1 C2 D3 A3 N4 A4 B5 NO STUFF DY 2 H_A20M# H_FERR# H_IGNNE# BR0# R289 56R2J 2 16 16 16 H_DEFER# 6 H_DRDY# 6 H_DBSY# 6 DATA GRP 0 DATA GRP 2 H_ADSTB#1 3 L4 H2 M2 RESET# RS0# RS1# RS2# TRDY# REQ0# REQ1# REQ2# REQ3# REQ4# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 DEFER# DRDY# DBSY# 4 6 6 6 DATA GRP 1 DATA GRP 3 6 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 H_ADS# H_BNR# H_BPRI# 1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 N2 L1 J3 2 H_REQ#0 R2 H_REQ#1 P3 H_REQ#2 T2 H_REQ#3 P1 H_REQ#4 T1 VCCP_GMCH_S0 ADS# BNR# BPRI# 1 H_ADSTB#0 H_REQ#[4..0] 3D3V_S0 62.10055.011 A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# ADSTB#0 2 6 6 P4 U4 V3 R3 V2 W1 T4 W2 Y4 Y1 U1 AA3 Y3 AA2 U3 ADDR GROUP 1 XTP/ITP SIGNALS 4 ADDR GROUP 0 U45A H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 CONTROL H_A#[31..3] 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 HCLK THERM 6 VCCP_GMCH_S0 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title CPU (1 of 2) Size A3 Document Number All place within 2" to CPU Date: Monday, August 15, 2005 A B C D Rev -1 Leopard 3 Sheet E 4 of 41 A B C D E U45D VCC_CORE_S0 62.10055.011 1 1 1D5V_S0 R17 DY 1 2 2 1D5V_VCCA_SET 2 0R2-0 G913C-U DY DY 0.1u *10 VCCP_GMCH_S0 DY 2 DY R296 49K9R2F BC2 SC1U10V3ZY 2 2 BC53 SC1U10V3ZY 1 1 1 OUT 4 DY 150u *1 3 1 TC1 ST100U6D3VM-U 2 1 2 SCD1U10V2MX-1 C26 SCD1U10V2MX-1 1 C20 2 1 2 C34 SCD1U10V2MX-1 1 2 2 C28 SCD1U10V2MX-1 1 C11 SCD1U10V2MX-1 1 2 C22 SCD1U10V2MX-1 1 C33 2 SCD1U10V2MX-1 C27 SCD1U10V2MX-1 1 C19 2 C18 1 NO STUFF VCC_CORE_S0 1 1 1 1 1 SC10U10V5ZY-L 2 SC10U10V5ZY-L 2 C276 C277 C279 C280 C281 C282 C283 C284 SC10U10V5ZY-L 2 C44 SC10U10V5ZY-L 2 DY C39 1 C38 SC10U10V5ZY-L 2 C37 SC10U10V5ZY-L 2 C36 1 C32 SC10U10V5ZY-L 2 C31 1 C29 1 C23 SC10U6D3V5MX 2 C21 SC10U10V5ZY-L 2 1 SC10U6D3V5MX 2 C17 1 1 C16 SC10U10V5ZY-L 2 1 SC10U6D3V5MX 2 2 1 Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line. 5 SC10U6D3V5MX 2 VCCSENSE and VSSSENSE lines should be of equal length. SET SC10U6D3V5MX 2 Layout Note: SHDN# GND IN 1 2 2 2 DY 1 2 3 1 R33 54D9R2F DY 1D5V_VCCA_S0 R295 12K7R3F BC54 SC22P SC10U6D3V5MX 2 R34 54D9R2F U44 1 PZ47903 3D3V_S0 SC10U6D3V5MX 2 TP_VSSSENSE I max = 120 mA 1 TP_VCCSENSE AF6 1D5V_VCCA_S0 SC10U6D3V5MX 2 AE7 36 36 36 36 36 36 3D3V_S0 4 1 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 3D3V_S0 SC10U6D3V5MX 2 E2 F2 F3 G3 G4 H4 VCCP_GMCH_S0 3,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 SC10U6D3V5MX 2 P23 W4 4,6,7,9,10,16,18,36,40,41 2 1 VCCP_GMCH_S0 SCD1U10V2MX-1 D10 CPU_D10 D12 D14 D16 E11 E13 E15 F10 F12 F14 F16 K6 L21 L5 M22 M6 N21 N5 P22 P6 R21 R5 T22 T6 U21 TP2 TPAD30 TP4 TPAD30 VCCP_GMCH_S0 TP39 TPAD30 R286 2 0R2-0 4,36 VCC_CORE_S0 1 C10 SC10U10V6ZY-U 2 C15 SCD01U16V3KX TP_VCCA1 TP_VCCA2 TP_VCCA3 D13 D15 D17 D19 D21 D23 D26 E3 E6 E8 E10 E12 E14 E16 E18 E20 E22 E25 F1 F4 F5 F7 F9 F11 F13 F15 F17 F19 F21 F24 G2 G6 G22 G23 G26 H3 H5 H21 H25 J1 J4 J6 J22 J24 K2 K5 K21 K23 K26 L3 L6 L22 L25 M1 M4 M5 M21 M24 N3 N6 N22 N23 N26 P2 P5 P21 P24 R1 R4 R6 R22 R25 T3 T5 T21 T23 T26 U2 U6 U22 U24 V1 V4 V5 V21 V25 W3 W6 W22 W23 W26 Y2 Y5 Y21 Y24 2 F26 B1 N1 AC26 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 1 1 1D5V_VCCA_S0 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 2 1D5V OR 1D8V Intel suggest Dothan A2 or later only use 1.5V A2 A5 A8 A11 A14 A17 A20 A23 A26 AA1 AA4 AA6 AA8 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AA25 AB3 AB5 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB26 AC2 AC5 AC8 AC10 AC12 AC14 AC16 AC18 AC21 AC24 AD1 AD4 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AD22 AD25 AE3 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE23 AE26 AF2 AF5 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF24 B3 B6 B9 B12 B16 B19 B22 B25 C1 C4 C7 C10 C13 C15 C18 C21 C24 D2 D5 D7 D9 D11 SCD1U10V2MX-1 G5 H22 H6 J21 J5 K22 U5 V22 V6 W21 W5 Y22 Y6 1 62.10055.011 VCC0 VCC59 VCC1 VCC60 VCC2 VCC61 VCC3 VCC62 VCC4 VCC63 VCC5 VCC64 VCC6 VCC65 VCC7 VCC66 VCC8 VCC67 VCC9 VCC68 VCC10 VCC69 VCC11 VCC70 VCC12 VCC71 VCC13 VCC14 VCCA0 VCC15 VCCA1 VCC16 VCCA2 VCC17 VCCA3 VCC18 VCC19 VCCP0 VCC20 VCCP1 VCC21 VCCP2 VCC22 VCCP3 VCC23 VCCP4 VCC24 VCCP5 VCC25 VCCP6 VCC26 VCCP7 VCC27 VCCP8 VCC28 VCCP9 VCC29 VCCP10 VCC30 VCCP11 VCC31 VCCP12 VCC32 VCCP13 VCC33 VCCP14 VCC34 VCCP15 VCC35 VCCP16 VCC36 VCCP17 VCC37 VCCP18 VCC38 VCCP19 VCC39 VCCP20 VCC40 VCCP21 VCC41 VCCP22 VCC42 VCCP23 VCC43 VCCP24 VCC44 VCC45 VCCQ0 VCC46 VCCQ1 VCC47 VCC48 VID0 VCC49 VID1 VCC50 VID2 VCC51 VID3 VCC52 VID4 VCC53 VID5 VCC54 VCC55 VCC56 VCCSENSE VCC57 VCC58 VSSSENSE 1 3 U45C AA11 AA13 AA15 AA17 AA19 AA21 AA5 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC9 AD10 AD12 AD14 AD16 AD18 AD8 AE11 AE13 AE15 AE17 AE19 AE9 AF10 AF12 AF14 AF16 AF18 AF8 D18 D20 D22 D6 D8 E17 E19 E21 E5 E7 E9 F18 F20 F22 F6 F8 G21 1.8V is for Dothan A2 before. 2 4 VCC_CORE_S0 1 VCC_CORE_S0 SC10U10V5ZY-L DY DY DY DY DY DY DY DY DY 1 1 PZ47903 tm ai l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ho Title C D E -1 xa 5 he B Leopard 3 Sheet Rev in Document Number Date: Monday, August 15, 2005 A f@ CPU (2 of 2) Size A3 of 41 A B C D E CORE_GMCH_S0 12/12 Trace 10 mil wide with 20 mil spacing H_YRCOMP VCCP_GMCH_S0 1 1 H_XRCOMP 9,10,40,41 CORE_GMCH_S0 R87 24D9R2F 4,5,7,9,10,16,18,36,40,41 VCCP_GMCH_S0 2 2 R69 24D9R2F 4 4 Power On Sequencing VCCP_GMCH_S0 U17A H_A#[31..3] Alviso Strapping Signals REV.NO. 1.0 and Configuration REF. NO. 15577 Pin Name Strap Description CFG[2:0] FSB Frequency Select page 183 Configuration 001 = FSB533 101 = FSB400 others = Reversed CFG[4:3] Reserved CFG5 DMI x2 Select 0 = DMI x2 1 = DMI x4 (Default) CFG6 Reserved 0 = DDR2 1 = DDR1 (Default) 2 CFG7 CPU Strap CFG8 Reserved CFG9 PCI Express Graphics Lane Reversal CFG[11:10] Reserved CFG[13:12] XOR/ALL Z test straps CFG[15:14] Reversed CFG16 FSB Dynamic ODT 0 = Reserved 1 = Dothan (Default) 0 = Reserve Lanes 1 = Normal (Default) 00 01 10 11 = = = = Reserved XOR mode enabled All Z mode enabled Normal Operation Reversed CFG18 GMCH core VCC Select 0 = 1.05V (Default) 1 = 1.5V CFG19 CPU VTT Select 0 = 1.05V (Default) 1 = 1.2V CFG20 Reversed SDVOCRTL _DATA SDVO Present C1 C2 D1 T1 L1 P1 HXRCOMP HXSCOMP HXSWING HYRCOMP HYSCOMP HYSWING 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled (Default) CFG17 1 (Default) H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING HADS# HADSTB#0 HADSTB#1 HVREF HBNR# HBPRI# HBREQ0# HCPURST# F8 B9 E13 J11 A5 D5 E7 H10 H_ADS# 4 H_ADSTB#0 4 H_ADSTB#1 4 HCLKINN HCLKINP AB1 AB2 CLK_MCH_BCLK# 3 CLK_MCH_BCLK 3 HDBSY# HDEFER# HDINV#0 HDINV#1 HDINV#2 HDINV#3 HDPWR# HDRDY# HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 HEDRDY# HHIT# HHITM# HLOCK# HPCREQ# HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HRS0# HRS1# HRS2# HCPUSLP# HTRDY# C6 E6 H8 K3 T7 U5 G6 F7 G4 K1 R3 V3 G5 K2 R2 W4 F6 D4 D6 B3 A11 A7 D7 B8 C7 A8 A4 C5 B4 G8 B5 H_DBSY# 4 H_DEFER# 4 Vccp Vcc_mch 10~30uS MCH_PWERGD 3 VCCP_GMCH_S0 3~10mS R336 100R2F H_BNR# 4 H_BPRI# 4 H_BREQ#0 4 H_CPURST# 4 CLK_ENABLE# VGATE TO ICH6 H_VREF C308 SCD1U10V2KX R337 200R2F H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 TP_H_EDRDY# TP_H_PCREQ# H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#0 H_RS#1 H_RS#2 H_CPUSLP#_GMCH CORE_GMCH_S0 H_DINV#[3..0] 4 R391 0R2-0 DY H_DPWR# 4 H_DRDY# 4 H_DSTBN#[3..0] 4 H_DSTBP#[3..0] 4 H_REQ#[4..0] 4 H_DPWR# 2 TP42 TPAD30 H_HIT# 4 H_HITM# 4 H_LOCK# 4 TP9 TPAD30 H_RS#[2..0] 0R0402-PAD 1 R311 2 4 H_CPUSLP# 4,16 H_TRDY# 4 For Banias/Celeron-M:R93=DUMMY For Dothan A:R93=DUMMY For Dothan B:R93=0R ALVISO-GM 1 Wistron Corporation 0 = No SDVO device present (Default) 1= SDVO device present NOTE: All strap signals are sampled with respect to the leading edge of the Alviso GMCH PWORK In signal. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ALVISO-GM:71.0GMCH.08U ALVISO-PM:71.0GMCH.0BU ALVISO-GML:71.0GMCH.0JU Title GMCH (1 of 5) Size A3 Document Number Date: Monday, August 15, 2005 A Vvid >100uS <10uS 1 12/12 Trace 10 mil wide with 20 mil spacing Vboot Vboot Vcc_core 1 2 1 C91 SCD1U16V 2 2 1 R88 100R2F C73 SCD1U16V VR_ON 2 H_YSWING 1 R68 100R2F 2 1 H_XSWING G9 C9 E9 B7 A10 F9 D8 B10 E10 G10 D9 E11 F10 G11 G13 C10 C11 D11 C12 B13 A12 F12 G12 E12 C13 B11 D13 A13 F13 1 R86 221R3F 2 2 R67 221R3F VID 4 >3mS H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# 2 1 VCCP_GMCH_S0 1 VCCP_GMCH_S0 HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# 1 H_YSCOMP E4 E1 F4 H7 E2 F1 E3 D3 K7 F2 J7 J8 H6 F3 K8 H5 H1 H2 K5 K6 J4 G3 H3 J1 L5 K4 J5 P7 L7 J3 P5 L3 U7 V6 R6 R5 P3 T8 R7 R8 U8 R4 T4 T5 R1 T3 V8 U6 W6 U3 V5 W8 W7 U2 U1 Y5 Y2 V4 Y7 W1 W3 Y3 Y6 W2 2 H_XSCOMP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 HOST 1 R89 54D9R2F 1 R70 54D9R2F 3 H_D#[63..0] 2 2 4 2 VCCP_GMCH_S0 B C D Rev -1 Leopard 3 Sheet E 6 of 41 A B C D E 9,15,18,40 2D5V_S0 Alviso will provide SDVO_CTRLCLK and CTRLDATA pulldowns on-die 9,10,11,12,38,39,40,41 1D8V_S3 5,9,17,18,21,38,39,41 1D5V_S0 2D5V_S0 1D8V_S3 1D5V_S0 6,9,10,40,41 CORE_GMCH_S0 CORE_GMCH_S0 11,40 DDR_VREF_S3 DDR_VREF_S3 SM_CS0# SM_CS1# SM_CS2# SM_CS3# M_OCDCOMP0 M_OCDCOMP1 AF22 AF16 SM_OCDCOMP0 SM_OCDCOMP1 AP14 AL15 AM11 AN10 SM_ODT0 SM_ODT1 SM_ODT2 SM_ODT3 AK10 AK11 AF37 AD1 AE27 AE28 AF9 AF10 SMRCOMPN SMRCOMPP SMVREF0 SMVREF1 SMXSLEWIN SMXSLEWOUT SMYSLEWIN SMYSLEWOUT 1 11,12 M_ODT0 11,12 M_ODT1 11,12 M_ODT2 11,12 M_ODT3 DDR_VREF_S3 M_RCOMPN M_RCOMPP SMXSLEW 1 2 R404 40D2R2F 2 R405 40D2R2F C109 SCD1U10V2MX-1 SMYSLEW 2 2 MUXING 13 13 BM_BUSY# EXT_TS0# EXT_TS1# THRMTRIP# PWROK RSTIN# DREF_CLKN DREF_CLKP DREF_SSCLKN DREF_SSCLKP NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 J23 J21 PM_EXTTS#0 H22 PM_EXTTS#1 F5 AD30 RST1# 1 AE29 1 R378 10KR2 PM_EXTTS#1 2 1 1 Ref ALVISO EDS-1 Page 115 VCCP_GMCH_S0 1 DREFCLK# 3 DREFCLK 3 DREFSSCLK# 3 DREFSSCLK 3 GMCH_TP3 GMCH_TP4 GMCH_TP5 GMCH_TP6 GMCH_TP7 GMCH_TP8 GMCH_TP9 GMCH_TP10 GMCH_TP11 GMCH_TP12 GMCH_TP13 DY DY DY 1 R50 1KR2 CFG2 CFG1 CFG0 R48 4K7R2 DY 1 DY 1 DY 1 DY 1 CFG(2..1) FREQ.(MHz) 10 400 00 533 11 Reserved DY DY 1 DY 1 DY 1 DY 1 DY 2 2 DY 1 1 R51 4K7R2 DY DY 2 CPU_SEL0 3,4 CPU_SEL1 3,4 1 1 M_RCOMPN M_RCOMPP R429 80D6R2F 1 For Dothan-B 2 2 2 R49 10KR2 1 2 1 1 1 R344 10KR2 R403 80D6R2F 1 FOR DDR2 1D8V_S3 1 PM_THRMTRIP-A# 4,16 PWROK 20 2 PLT_RST1# 19,21 R406 100R2 When Low 2.2K R375 10KR2 PM_EXTTS#0 2 1 CFG2=0(R51):133MHZ CFG2=1(R50):100MHZ LBKLT_CRTL 31 ALVISO-GM 2D5V_S0 VSYNC HSYNC CRTIREF 39R2J 2R60 39R2J 2R58 2R374 255R2F 1 1 1 PM_BMBUSY# 17 A24 A23 C37 D37 AP37 AN37 AP36 AP2 AP1 AN1 B1 A2 B37 A36 A37 150R2F 150R2F 150R2F 2 R350 DUMMY-R2 2 R348 DUMMY-R2 2 R343 DUMMY-R2 R571 2 2K2R2 2 R352 DUMMY-R2 2 R340 DUMMY-R2 2 R347 DUMMY-R2 2 R349 DUMMY-R2 2 R52 DUMMY-R2 2 R345 DUMMY-R2 2 R338 DUMMY-R2 2 R346 DUMMY-R2 2 R342 DUMMY-R2 2 R339 DUMMY-R2 2 R341 DUMMY-R2 14 BL_ON LCDVDD_ON LIBG TPAD30 TP41 TPAD30 TP51 TPAD30 TP50 NO STUFF TP20 TP18 TP19 TP15 TP16 TP17 TP7 TP8 TP14 TP13 TP12 TPAD30 2D5V_S0 TPAD30 TPAD30 RN39 TPAD30LCTLA_CLK 1 8 TPAD30LCTLB_DATA2 7 TPAD30LDDC_CLK 3 6 TPAD30LDDC_DATA 4 5 TPAD30 TPAD30 SRN2K2 TPAD30 TPAD30 BL_ON 1 2 R382 100KR2 LBKLT_CRTL 1 2 R381 100KR2 LIBG 1 2 R379 1K5R2F Ohm CFG3 CFG4 E25 F25 C23 C22 F23 F22 F26 C33 L_LVBG C31 L_VREFH F28 L_VREFL F27 LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LBKLT_CRTL LBKLT_EN LCTLA_CLK LCTLB_DATA LDDC_CLK LDDC_DATA LVDD_EN LIBG LVBG LVREFH LVREFL EXP_TXN0 EXP_TXN1 EXP_TXN2 EXP_TXN3 EXP_TXN4 EXP_TXN5 EXP_TXN6 EXP_TXN7 EXP_TXN8 EXP_TXN9 EXP_TXN10 EXP_TXN11 EXP_TXN12 EXP_TXN13 EXP_TXN14 EXP_TXN15 E32 F36 G32 H36 J32 K36 L32 M36 N32 P36 R32 T36 U32 V36 W32 Y36 14 14 14 14 TXACLKTXACLK+ TXBCLKTXBCLK+ B30 B29 C25 C24 LACLKN LACLKP LBCLKN LBCLKP 14 14 14 TXAOUT0TXAOUT1TXAOUT2- B34 B33 B32 LADATAN0 LADATAN1 LADATAN2 14 14 14 TXAOUT0+ TXAOUT1+ TXAOUT2+ A34 A33 B31 EXP_TXP0 EXP_TXP1 EXP_TXP2 EXP_TXP3 EXP_TXP4 EXP_TXP5 EXP_TXP6 EXP_TXP7 EXP_TXP8 EXP_TXP9 EXP_TXP10 EXP_TXP11 EXP_TXP12 EXP_TXP13 EXP_TXP14 EXP_TXP15 D32 E36 F32 G36 H32 J36 K32 L36 M32 N36 P32 R36 T32 U36 V32 W36 LADATAP0 LADATAP1 LADATAP2 14 14 14 TXBOUT0TXBOUT1TXBOUT2- C29 D28 C27 LBDATAN0 LBDATAN1 LBDATAN2 14 14 14 TXBOUT0+ TXBOUT1+ TXBOUT2+ C28 D27 C26 LBDATAP0 LBDATAP1 LBDATAP2 CFG5 3D3V_S0 CFG6 CFG7 CFG12 CFG17 LDDC_CLK 4 3 14 EDID_CLK 5 2 14 EDID_DAT 6 1 B DY 1 DY 1 DY 2 R380 DUMMY-R2 2 R376 DUMMY-R2 2 R377 DUMMY-R2 CFG18 CFG19 CFG20 Strapping 1 LDDC_DATA Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2N7002S Title CFG[17:3] have internal pullup resistors. CFG[19:18] have internal pulldown resistors GMCH (2 of 5) Size A3 Document Number Leopard 3 Date: Monday, August 15, 2005 A 1 U14 CFG11 CFG16 When High 1K Ohm RN38 SRN4D7KJ CFG10 CFG15 2D5V_S0 ALVISO-GM CFG9 CFG14 2 2D5V_S0 CFG8 CFG13 3 C om AN16 AM14 AH15 AG16 2R59 2R57 1 2R56 VGA_VSYNC VGA_HSYNC D30 E34 F30 G34 H30 J34 K30 L34 M30 N34 P30 R34 T30 U34 V30 W34 l.c M_CS0_R# M_CS1_R# M_CS2_R# M_CS3_R# DY DY1 DY1 EXP_RXP0 EXP_RXP1 EXP_RXP2 EXP_RXP3 EXP_RXP4 EXP_RXP5 EXP_RXP6 EXP_RXP7 EXP_RXP8 EXP_RXP9 EXP_RXP10 EXP_RXP11 EXP_RXP12 EXP_RXP13 EXP_RXP14 EXP_RXP15 ai AP21 AM21 AH21 AK21 DDCCLK DDCDATA BLUE BLUE# GREEN GREEN# RED RED# VSYNC HSYNC REFSET tm M_CKE0_R# M_CKE1_R# M_CKE2_R# M_CKE3_R# Less than 0.5", trace impendance 37.5ohm D ho 11,12 11,12 11,12 11,12 Trace impendance 50ohm VGA_BLUE VGA_GREEN VGA_RED Sheet E f@ CLK_DDR3# CLK_DDR4# 11,12 11,12 11,12 11,12 Layout Note: Route as short as possible 1 11 11 15 GMCH_DDCCLK 15 GMCH_DDCDATA 15 15 15 E30 F34 G30 H34 J30 K34 L30 M34 N30 P34 R30 T34 U30 V34 W30 Y34 Rev of 41 in SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 CLK_DDR0# CLK_DDR1# TP48 TP44 TP43 TP11 TP10 TP47 TP45 4 1 24D9R2F -1 xa SM_CK0# SM_CK1# SM_CK2# SM_CK3# SM_CK4# SM_CK5# 11 11 E24 E23 E21 D21 C20 B20 A19 B19 H21 G21 J20 SD 0817 EXP_RXN0 EXP_RXN1 EXP_RXN2 EXP_RXN3 EXP_RXN4 EXP_RXN5 EXP_RXN6 EXP_RXN7 EXP_RXN8 EXP_RXN9 EXP_RXN10 EXP_RXN11 EXP_RXN12 EXP_RXN13 EXP_RXN14 EXP_RXN15 PEG_COMP 2 7 he AN33 AK1 AE10 AJ33 AF5 AD10 CLK_DDR3 CLK_DDR4 DDR 3 11 11 2 TV_REFSET R373 4K99R2F TVDAC_A TVDAC_B TVDAC_C TV_REFSET TV_IRTNA TV_IRTNB TV_IRTNC EXP_COMPI EXP_ICOMPO PCI-EXPRESS GRAPHICS SM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK4 SM_CK5 1 R54 R55 150R2F 150R2F MISC AM33 AL1 AE11 AJ34 AF6 AC10 CLK_DDR0 CLK_DDR1 R53 150R2F A15 C16 A17 J18 B15 B16 B17 TV 11 11 COMP_VGA LUMA_VGA CRMA_VGA SDVOCTRL_DATA SDVOCTRL_CLK GCLKN GCLKP D36 D34 VGA DMITXP0 DMITXP1 DMITXP2 DMITXP3 13 13 13 H24 H25 AB29 AC29 LVDS Y33 AA37 AB33 AC37 3 CLK_MCH_3GPLL# 3 CLK_MCH_3GPLL 1 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 17 DMI_RXP[3..0] SDVO_DAT SDVO_CLK R71 2 DMITXN0 DMITXN1 DMITXN2 DMITXN3 TPAD30 TP46 TPAD30 TP49 1D5V_S0 U17G Intel suggest NC Due to votusly DVO CFG2 1 AA33 AB37 AC33 AD37 2 1KR2 2 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 17 DMI_RXN[3..0] CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 R534 1 1 2 DMIRXP0 DMIRXP1 DMIRXP2 DMIRXP3 CFG0 CFG1 4 3 Y31 AA35 AB31 AC35 G16 H13 G14 F16 F15 G15 E16 D17 J16 D15 E15 D14 E14 H12 C14 H15 J15 H14 G22 G23 D23 G25 G24 J17 A31 A30 D26 D25 1 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 2 17 DMI_TXP[3..0] CFG/RSVD DMIRXN0 DMIRXN1 DMIRXN2 DMIRXN3 PM AA31 AB35 AC31 AD35 CLK DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 NC 17 DMI_TXN[3..0] 4 DMI U17B A B C D E 4 4 3 2 AG35 AH35 AL35 AL37 AH36 AJ35 AK37 AL34 AM36 AN35 AP32 AM31 AM34 AM35 AL32 AM32 AN31 AP31 AN28 AP28 AL30 AM30 AM28 AL28 AP27 AM27 AM23 AM22 AL23 AM24 AN22 AP22 AM9 AL9 AL6 AP7 AP11 AP10 AL7 AM7 AN5 AN6 AN3 AP3 AP6 AM6 AL4 AM3 AK2 AK3 AG2 AG1 AL3 AM2 AH3 AG3 AF3 AE3 AD6 AC4 AF2 AF1 AD4 AD5 SADQ0 SADQ1 SADQ2 SADQ3 SADQ4 SADQ5 SADQ6 SADQ7 SADQ8 SADQ9 SADQ10 SADQ11 SADQ12 SADQ13 SADQ14 SADQ15 SADQ16 SADQ17 SADQ18 SADQ19 SADQ20 SADQ21 SADQ22 SADQ23 SADQ24 SADQ25 SADQ26 SADQ27 SADQ28 SADQ29 SADQ30 SADQ31 SADQ32 SADQ33 SADQ34 SADQ35 SADQ36 SADQ37 SADQ38 SADQ39 SADQ40 SADQ41 SADQ42 SADQ43 SADQ44 SADQ45 SADQ46 SADQ47 SADQ48 SADQ49 SADQ50 SADQ51 SADQ52 SADQ53 SADQ54 SADQ55 SADQ56 SADQ57 SADQ58 SADQ59 SADQ60 SADQ61 SADQ62 SADQ63 U17D SA_BS0# SA_BS1# SA_BS2# AK15 AK16 AL21 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 AJ37 AP35 AL29 AP24 AP9 AP4 AJ2 AD3 M_A_SDM0 M_A_SDM1 M_A_SDM2 M_A_SDM3 M_A_SDM4 M_A_SDM5 M_A_SDM6 M_A_SDM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 AK36 AP33 AN29 AP23 AM8 AM4 AJ1 AE5 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# AK35 AP34 AN30 AN23 AN8 AM5 AH1 AE4 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 AL17 AP17 AP18 AM17 AN18 AM18 AL19 AP20 AM19 AL20 AM16 AN20 AM20 AM15 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 SA_CAS# SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# AN15 AP16 AF29 AF28 AP15 GMCH_TP48 GMCH_TP49 DDR SYSTEM MEMORY A M_A_DATA0 M_A_DATA1 M_A_DATA2 M_A_DATA3 M_A_DATA4 M_A_DATA5 M_A_DATA6 M_A_DATA7 M_A_DATA8 M_A_DATA9 M_A_DATA10 M_A_DATA11 M_A_DATA12 M_A_DATA13 M_A_DATA14 M_A_DATA15 M_A_DATA16 M_A_DATA17 M_A_DATA18 M_A_DATA19 M_A_DATA20 M_A_DATA21 M_A_DATA22 M_A_DATA23 M_A_DATA24 M_A_DATA25 M_A_DATA26 M_A_DATA27 M_A_DATA28 M_A_DATA29 M_A_DATA30 M_A_DATA31 M_A_DATA32 M_A_DATA33 M_A_DATA34 M_A_DATA35 M_A_DATA36 M_A_DATA37 M_A_DATA38 M_A_DATA39 M_A_DATA40 M_A_DATA41 M_A_DATA42 M_A_DATA43 M_A_DATA44 M_A_DATA45 M_A_DATA46 M_A_DATA47 M_A_DATA48 M_A_DATA49 M_A_DATA50 M_A_DATA51 M_A_DATA52 M_A_DATA53 M_A_DATA54 M_A_DATA55 M_A_DATA56 M_A_DATA57 M_A_DATA58 M_A_DATA59 M_A_DATA60 M_A_DATA61 M_A_DATA62 M_A_DATA63 11 M_B_DATA[63..0] M_A_BS0# 11,12 M_A_BS1# 11,12 M_A_BS2# 11,12 M_A_SDM[7..0] 11 M_A_DQS[7..0] 11 M_A_DQS#[7..0] 11 M_A_A[13..0] 11,12 TP55 TP54 M_A_CAS# 11,12 M_A_RAS# 11,12 M_A_WE# 11,12 ALVISO-GM M_B_DATA0 M_B_DATA1 M_B_DATA2 M_B_DATA3 M_B_DATA4 M_B_DATA5 M_B_DATA6 M_B_DATA7 M_B_DATA8 M_B_DATA9 M_B_DATA10 M_B_DATA11 M_B_DATA12 M_B_DATA13 M_B_DATA14 M_B_DATA15 M_B_DATA16 M_B_DATA17 M_B_DATA18 M_B_DATA19 M_B_DATA20 M_B_DATA21 M_B_DATA22 M_B_DATA23 M_B_DATA24 M_B_DATA25 M_B_DATA26 M_B_DATA27 M_B_DATA28 M_B_DATA29 M_B_DATA30 M_B_DATA31 M_B_DATA32 M_B_DATA33 M_B_DATA34 M_B_DATA35 M_B_DATA36 M_B_DATA37 M_B_DATA38 M_B_DATA39 M_B_DATA40 M_B_DATA41 M_B_DATA42 M_B_DATA43 M_B_DATA44 M_B_DATA45 M_B_DATA46 M_B_DATA47 M_B_DATA48 M_B_DATA49 M_B_DATA50 M_B_DATA51 M_B_DATA52 M_B_DATA53 M_B_DATA54 M_B_DATA55 M_B_DATA56 M_B_DATA57 M_B_DATA58 M_B_DATA59 M_B_DATA60 M_B_DATA61 M_B_DATA62 M_B_DATA63 AE31 AE32 AG32 AG36 AE34 AE33 AF31 AF30 AH33 AH32 AK31 AG30 AG34 AG33 AH31 AJ31 AK30 AJ30 AH29 AH28 AK29 AH30 AH27 AG28 AF24 AG23 AJ22 AK22 AH24 AH23 AG22 AJ21 AG10 AG9 AG8 AH8 AH11 AH10 AJ9 AK9 AJ7 AK6 AJ4 AH5 AK8 AJ8 AJ5 AK4 AG5 AG4 AD8 AD9 AH4 AG6 AE8 AD7 AC5 AB8 AB6 AA8 AC8 AC7 AA4 AA5 SBDQ0 SBDQ1 SBDQ2 SBDQ3 SBDQ4 SBDQ5 SBDQ6 SBDQ7 SBDQ8 SBDQ9 SBDQ10 SBDQ11 SBDQ12 SBDQ13 SBDQ14 SBDQ15 SBDQ16 SBDQ17 SBDQ18 SBDQ19 SBDQ20 SBDQ21 SBDQ22 SBDQ23 SBDQ24 SBDQ25 SBDQ26 SBDQ27 SBDQ28 SBDQ29 SBDQ30 SBDQ31 SBDQ32 SBDQ33 SBDQ34 SBDQ35 SBDQ36 SBDQ37 SBDQ38 SBDQ39 SBDQ40 SBDQ41 SBDQ42 SBDQ43 SBDQ44 SBDQ45 SBDQ46 SBDQ47 SBDQ48 SBDQ49 SBDQ50 SBDQ51 SBDQ52 SBDQ53 SBDQ54 SBDQ55 SBDQ56 SBDQ57 SBDQ58 SBDQ59 SBDQ60 SBDQ61 SBDQ62 SBDQ63 SB_BS0# SB_BS1# SB_BS2# AJ15 AG17 AG21 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 AF32 AK34 AK27 AK24 AJ10 AK5 AE7 AB7 M_B_SDM0 M_B_SDM1 M_B_SDM2 M_B_SDM3 M_B_SDM4 M_B_SDM5 M_B_SDM6 M_B_SDM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 AF34 AK32 AJ28 AK23 AM10 AH6 AF8 AB4 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# AF35 AK33 AK28 AJ23 AL10 AH7 AF7 AB5 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 AH17 AK17 AH18 AJ18 AK18 AJ19 AK19 AH19 AJ20 AH20 AJ16 AG18 AG20 AG15 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_CAS# SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# AH14 AK14 AF15 AF14 AH16 DDR SYSTEM MEMORY B U17C 11 M_A_DATA[63..0] GMCH_TP50 GMCH_TP51 M_B_BS0# 11,12 M_B_BS1# 11,12 M_B_BS2# 11,12 M_B_SDM[7..0] 11 M_B_DQS[7..0] 11 M_B_DQS#[7..0] 11 3 M_B_A[13..0] 11,12 TP53 TP52 M_B_CAS# 11,12 M_B_RAS# 11,12 M_B_WE# 11,12 2 ALVISO-GM 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title GMCH (3 of 5) Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 8 of 41 B C D 1D5V_S0 1D5V_S0 G10 1 1 2 1 B 1 2 1 1 2 1 1 2 1 1 2 C323 SC4D7U10V5ZY GMCH (4 of 5) Document Number D Leopard 3 Sheet E f@ ho Title Size A3 C om l.c tm ai 1 C89 SC10U10V6ZY-U Rev of 41 in C88 ST100U6D3VM-U -1 xa C72 SCD1U10V2MX-1 C111 SCD1U10V2MX-1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 9 he DY 1 VCCP_GMCH_S0 1D5V_MPLL_S0 C107 SC10U6D3V5MX Layout Notes: VSSA_CRTDAC Route caps within 250mil of Alviso. Route FB within 3" of Alviso. Date: Tuesday, August 16, 2005 A 2 1 2 F37 G37 VCCA_3GBG VSSA_3GBG Y29 Y28 Y27 VCCA_3GPLL0 VCCA_3GPLL1 VCCA_3GPLL2 AE37 W37 U37 R37 N37 L37 J37 AF20 AP19 AF19 AF18 VCCA_SM0 VCCA_SM1 VCCA_SM2 VCCA_SM3 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 C324 SC4D7U10V5ZY 2 1 2 1 DY 2 IND-D1UH 2 CORE_GMCH_S0 6,10,40,41 L13 2 SSM5818SL 1 C110 SCD1U10V2MX-1 2 CORE_GMCH_S0 C313 SCD1U10V2MX-1 D22 2 1 10R2 Route VSSA_CRTDAC gnd from GMCH to decoupling cap ground lead and then connect to the gnd plane. 2 1 C108 SC10U6D3V5MX 1 VCCP_GMCH_S0 4,5,6,7,10,16,18,36,40,41 C71 SCD22U16V3ZY 1D5V_HPLL_S0 2 IND-D1UH 2 VCCP_GMCH_S0 C90 SCD22U16V3ZY 2 1 R358 1 C315 SCD1U10V2MX-1 1 L14 2 VCCP_GMCH_S0 DY 2 1 C74 GAP-CLOSE-PWR SCD1U10V2MX-1 1 7,10,11,12,38,39,40,41 1 1 C57 SCD1U10V2MX-1 1 1D8V_S3 2 2 7,15,18,40 DY 1 2D5V_S0 1D8V_S3 1 C302 SC10U6D3V5MX 2 L22 3 2 VCCP_GMCH_S0 1D5V_DPLLB_S0 2 IND-D1UH 1 5,7,17,18,21,38,39,41 1 2 1D5V_S0 G43 GAP-CLOSE-PWR 1 C52 SCD47U16V3ZY 2D5V_S0 C301 SCD1U10V2MX-1 2 1 DY 2 C459 SCD022U16V SC22U10V6MX 1 2 C56 SC10U6D3V5MX 1 1 1D5V_DPLLA_S0 2 IND-D1UH 2 L4 1 1 2D5V_CRTDAC_S0 R357 R560 2 1 2 DY 0R3-U 0R5J 2 VCC_SYNC VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC C312 2 1 1 1 2 2 2 2 2 1 1 1 1 2 1D5V_HMPLL_S0 1D5V_S0 2D5V_S0 G13 C53 SCD47U16V3ZY C329 C328 C327 SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1 1D5V_S0 2D5V_3GBG_S0 2D5V_TXLVDS_S0 GMCH_CORE_VCC 2D5V_S0 2 1 C122 SCD1U10V2MX-1 2 CORE_GMCH_S0 C341 C325 C326 SC10U10V5ZY-L SC10U10V5ZY-L SC10U10V5ZY-L GAP-CLOSE-PWR C330 SC10U10V5ZY-L K13 VTT0 J13 VTT1 K12 VTT2 W11 VTT3 V11 VTT4 U11 VTT5 T11 VTT6 R11 VTT7 P11 VTT8 N11 VTT9 M11 VTT10 L11 VTT11 K11 VTT12 W10 VTT13 V10 VTT14 U10 VTT15 T10 VTT16 R10 VTT17 P10 VTT18 N10 VTT19 M10 VTT20 K10 VTT21 J10 VTT22 Y9 VTT23 W9 VTT24 U9 VTT25 R9 VTT26 P9 VTT27 N9 VTT28 M9 VTT29 L9 VTT30 J9 VTT31 N8 VTT32 M8 VTT33 N7 VTT34 M7 VTT35 N6 VTT36 M6 VTT37 A6 VTT38 1VCCP_GMCH_CAP1 N5 VTT39 M5 VTT40 N4 VTT41 1 M4 VTT42 N3 VTT43 M3 VTT44 N2 VTT45 M2 VTT46 VCCP_GMCH_CAP2 B2 VTT47 VCCP_GMCH_CAP3 V1 VTT48 N1 VTT49 M1 VTT50 VCCP_GMCH_CAP4 G1 VTT51 2 H20 T29 R29 N29 M29 K29 J29 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 K26 H26 K25 J25 K24 K23 K22 K21 W20 U20 T20 K20 V19 U19 K19 W18 V18 T18 K18 K17 VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 APL5308-25AC-TR F19 E19 G19 A35 B22 B21 A21 VCCHV0 VCCHV1 VCCHV2 VCCA_LVDS B26 B25 A25 D19 H17 H18 G18 SC10U6D3V5MX VCCH_MPLL1 VCCH_MPLL0 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL VCCA_MPLL C466 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 1 VCCD_TVDAC VCCDQ_TVDAC 1 2 2 C124 C342 SCD1U10V2MX-1 SCD1U10V2MX-1 2 1 2 C465 SCD1U10V2MX-1 VOUT VIN GND VCCA_TVBG VSSA_TVBG F17 E17 D18 C18 F18 E18 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 U66 1 SCD1U10V2MX-1 U17E 2D5V_CRTDAC_S0 1 GAP-CLOSE-PWR TC16 ST100U6D3VM-U 1D5V_3GPLL_S0 1D5V_S0 G50 1 2 C123 SCD1U10V2MX-1 VCCTX_LVDS0 VCCTX_LVDS1 VCCTX_LVDS2 2D5V_ALVDS_S0 C339 SC10U10V5ZY-L AC2 AC1 B23 C35 AA1 AA2 C314 SCD1U10V2MX-1 C351 SC10U10V5ZY-L 2 C125 VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9 VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36 VCCSM37 VCCSM38 VCCSM39 VCCSM40 VCCSM41 VCCSM42 VCCSM43 VCCSM44 VCCSM45 VCCSM46 VCCSM47 VCCSM48 VCCSM49 VCCSM50 VCCSM51 VCCSM52 VCCSM53 VCCSM54 VCCSM55 VCCSM56 VCCSM57 VCCSM58 VCCSM59 VCCSM60 VCCSM61 VCCSM62 VCCSM63 VCCSM64 1 2 2 0R3-U 3 1 C126 SCD1U10V2MX-1 POWER 1 Note: All VCCSM pins shorted internally TC7 ST150U4VBM-L1 2 DY 1D8V_S3 Note: All VCCSM pins shorted internally 1D5V_DLVDS_S0 3D3V_TVDACA_S0 C92 SC10U10V5ZY-L C60 SC4D7U10V5ZY FOR DDR2 C127 SCD1U10V2MX-1 R356 3D3V_S0 C343 SC10U10V5ZY-L 1 2 0R3-U 3 GAP-CLOSE-PWR C61 SCD1U10V2MX-1 1 C311 SCD1U10V2MX-1 GAP-CLOSE-PWR C54 C55 SCD1U10V2MX-1SC10U10V5ZY-L 2 V1.8_DDR_CAP1 2 AM37 V1.8_DDR_CAP2 2 1 AH37 AP29 V1.8_DDR_CAP5 AD28 AD27 AC27 AP26 AN26 AM26 AL26 AK26 AJ26 AH26 AG26 AF26 AE26 AP25 AN25 AM25 AL25 AK25 AJ25 AH25 AG25 AF25 AE25 AE24 AE23 2 1 AE22 AE21 AE20 AE19 AE18 2 1 AE17 AE16 AE15 AE14 AP13 AN13 AM13 AL13 AK13 2 1 AJ13 AH13 AG13 AF13 AE13 AP12 AN12 AM12 AL12 AK12 AJ12 AH12 AG12 AF12 AE12 AD11 AC11 AB11 AB10 AB9 AP8 V1.8_DDR_CAP6 V1.8_DDR_CAP4 AM1 2 V1.8_DDR_CAP3 2 1 AE1 1 2 1 SC10U6D3V5MX 2D5V_TXLVDS_S0 1 B28 A28 A27 3D3V_TVDACB_S0 R355 C461 1 G11 2 2 1 C309 SCD1U10V2MX-1 0R3-U 2 1 2 2 1 1 3D3V_TVDACC_S0 2 R312 1D5V_S0 G51 2D5V_S0 G9 1 3D3V_VGA_S0 1D5V_PCIE_S0 2D5V_S0 2 2D5V_TVDAC_S0 4 C62 SCD01U16V3KX 2 C310 SCD1U10V2MX-1 2 0R3-U 2 3D3V_ATVBG_S0 1 2 GAP-CLOSE-PWR C131 ST100U6D3VM-U 2 GAP-CLOSE-PWR C63 SCD1U10V2MX-1 2 1 1 C300 SCD1U10V2MX-1 2 R313 2 0R3-U 1 R35 2 G12 2 0R3-U 2 1 1 1 1D5V_QTVDAC_S0 C340 SCD1U10V2MX-1 2D5V_ALVDS_S0 R353 SSM5818SL 1D5V_S0 G29 1 1 2D5V_S0 4 1 1 1 2 10R2 1D5V_DDRDLL_S0 C58 SC10U10V5ZY-L 1D5V_S0 D2 2TVDAC_PWR1 2 R36 1 2 GAP-CLOSE-PWR C59 SCD1U10V2MX-1 2 3D3V_VGA_S0 1 2 0R3-U C299 SCD1U10V2MX-1 2 3D3V_S0 1 2 R354 1D5V_TVDAC_S0 E 1D5V_DLVDS_S0 2 A U17H ALVISO-GM VCCP_GMCH_S0 A B VSS_NCTF68 VSS_NCTF67 VSS_NCTF66 VSS_NCTF65 VSS_NCTF64 VSS_NCTF63 VSS_NCTF62 VSS_NCTF61 VSS_NCTF60 VSS_NCTF59 VSS_NCTF58 VSS_NCTF57 VSS_NCTF56 VSS_NCTF55 VSS_NCTF54 VSS_NCTF53 VSS_NCTF52 VSS_NCTF51 VSS_NCTF50 VSS_NCTF49 VSS_NCTF48 VSS_NCTF47 VSS_NCTF46 VSS_NCTF45 VSS_NCTF44 VSS_NCTF43 VSS_NCTF42 VSS_NCTF41 VSS_NCTF40 VSS_NCTF39 VSS_NCTF38 VSS_NCTF37 VSS_NCTF36 VSS_NCTF35 VSS_NCTF34 VSS_NCTF33 VSS_NCTF32 VSS_NCTF31 VSS_NCTF30 VSS_NCTF29 VSS_NCTF28 VSS_NCTF27 VSS_NCTF26 VSS_NCTF25 VSS_NCTF24 VSS_NCTF23 VSS_NCTF22 VSS_NCTF21 VSS_NCTF20 VSS_NCTF19 VSS_NCTF18 VSS_NCTF17 VSS_NCTF16 VSS_NCTF15 VSS_NCTF14 VSS_NCTF13 VSS_NCTF12 VSS_NCTF11 VSS_NCTF10 VSS_NCTF9 VSS_NCTF8 VSS_NCTF7 VSS_NCTF6 VSS_NCTF5 VSS_NCTF4 VSS_NCTF3 VSS_NCTF2 VSS_NCTF1 VSS_NCTF0 2 Y12 AA12 Y13 AA13 L14 M14 N14 P14 R14 T14 U14 V14 W14 Y14 AA14 AB14 L15 M15 N15 P15 R15 T15 U15 V15 W15 Y15 AA15 AB15 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 R17 Y17 AA17 AB17 AA18 AB18 AA19 AB19 AA20 AB20 R21 Y21 AA21 AB21 Y22 AA22 AB22 Y23 AA23 AB23 Y24 AA24 AB24 Y25 AA25 AB25 Y26 AA26 AB26 VTT_NCTF17 VTT_NCTF16 VTT_NCTF15 VTT_NCTF14 VTT_NCTF13 VTT_NCTF12 VTT_NCTF11 VTT_NCTF10 VTT_NCTF9 VTT_NCTF8 VTT_NCTF7 VTT_NCTF6 VTT_NCTF5 VTT_NCTF4 VTT_NCTF3 VTT_NCTF2 VTT_NCTF1 VTT_NCTF0 VCC_NCTF78 VCC_NCTF77 VCC_NCTF76 VCC_NCTF75 VCC_NCTF74 VCC_NCTF73 VCC_NCTF72 VCC_NCTF71 VCC_NCTF70 VCC_NTTF69 VCC_NCTF68 VCC_NCTF67 VCC_NCTF66 VCC_NCTF65 VCC_NCTF64 VCC_NCTF63 VCC_NCTF62 VCC_NCTF61 VCC_NCTF60 VCC_NCTF59 VCC_NCTF58 VCC_NCTF57 VCC_NCTF56 VCC_NCTF55 VCC_NCTF54 VCC_NCTF53 VCC_NCTF52 VCC_NCTF51 VCC_NCTF50 VCC_NCTF49 VCC_NCTF48 VCC_NCTF47 VCC_NCTF46 VCC_NCTF45 VCC_NCTF44 VCC_NCTF43 VCC_NCTF42 VCC_NCTF41 VCC_NCTF40 VCC_NCTF39 VCC_NCTF38 VCC_NCTF37 VCC_NCTF36 VCC_NCTF35 VCC_NCTF34 VCC_NCTF33 VCC_NCTF32 VCC_NCTF31 VCC_NCTF30 VCC_NCTF29 VCC_NCTF28 VCC_NCTF27 VCC_NCTF26 VCC_NCTF25 VCC_NCTF24 VCC_NCTF23 VCC_NCTF22 VCC_NCTF21 VCC_NCTF20 VCC_NCTF19 VCC_NCTF18 VCC_NCTF17 VCC_NCTF16 VCC_NCTF15 VCC_NCTF14 VCC_NCTF13 VCC_NCTF12 VCC_NCTF11 VCC_NCTF10 VCC_NCTF9 VCC_NCTF8 VCC_NCTF7 VCC_NCTF6 VCC_NCTF5 VCC_NCTF4 VCC_NCTF3 VCC_NCTF2 VCC_NCTF1 VCC_NCTF0 L17 M17 N17 P17 T17 U17 V17 W17 L18 M18 N18 P18 R18 Y18 L19 M19 N19 P19 R19 Y19 L20 M20 N20 P20 R20 Y20 L21 M21 N21 P21 T21 U21 V21 W21 L22 M22 N22 P22 R22 T22 U22 V22 W22 L23 M23 N23 P23 R23 T23 U23 V23 W23 L24 M24 N24 P24 R24 T24 U24 V24 W24 L25 M25 N25 P25 R25 T25 U25 V25 W25 L26 M26 N26 P26 R26 T26 U26 V26 W26 1D8V_S3 L12 M12 N12 P12 R12 T12 U12 V12 W12 L13 M13 N13 P13 R13 T13 U13 V13 W13 AB12 AC12 AD12 AB13 AC13 AD13 AC14 AD14 AC15 AD15 AC16 AD16 AC17 AD17 AC18 AD18 AC19 AD19 AC20 AD20 AC21 AD21 AC22 AD22 AC23 AD23 AC24 AD24 AC25 AD25 AC26 AD26 Y1 D2 G2 J2 L2 P2 T2 V2 AD2 AE2 AH2 AL2 AN2 A3 C3 AA3 AB3 AC3 AJ3 C4 H4 L4 P4 U4 Y4 AF4 AN4 E5 W5 AL5 AP5 B6 J6 L6 P6 T6 AA6 AC6 AE6 AJ6 G7 V7 AA7 AG7 AK7 AN7 C8 E8 L8 P8 Y8 AL8 A9 H9 K9 T9 V9 AA9 AC9 AE9 AH9 AN9 D10 L10 Y10 AA10 F11 H11 Y11 AA11 AF11 AG11 AJ11 AL11 AN11 B12 D12 J12 A14 B14 F14 J14 K14 AG14 AJ14 AL14 AN14 C15 K15 A16 D16 H16 K16 AL16 C17 G17 AF17 AJ17 AN17 A18 B18 U18 AL18 C19 H19 J19 T19 W19 AG19 AN19 A20 D20 E20 F20 G20 V20 AK20 C21 F21 AF21 AN21 A22 D22 E22 J22 AH22 AL22 H23 AF23 B24 D24 F24 J24 AG24 AJ24 VSS271 VSS270 VSS269 VSS268 VSS260 VSS259 VSS258 VSS257 VSS256 VSS255 VSS254 VSS253 VSS252 VSS251 VSS250 VSS249 VSS248 VSS247 VSS246 VSS245 VSS244 VSS243 VSS242 VSS241 VSS240 VSS239 VSS238 VSS237 VSS236 VSS235 VSS234 VSS233 VSS232 VSS231 VSS230 VSS229 VSS228 VSS227 VSS226 VSS225 VSS224 VSS223 VSS222 VSS221 VSS220 VSS219 VSS218 VSS217 VSS216 VSS215 VSS214 VSS213 VSS212 VSS211 VSS210 VSS209 VSS208 VSS207 VSS206 VSS205 VSS204 VSS203 VSS202 VSS201 VSS200 VSS199 VSS198 VSS197 VSS196 VSS195 VSS194 VSS193 VSS192 VSS191 VSS190 VSS189 VSS188 VSS187 VSS186 VSS185 VSS184 VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSSALVDS VSS267 VSS266 VSS265 VSS264 VSS263 VSS262 VSS261 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0 U17F VCCSM_NCTF31 VCCSM_NCTF30 VCCSM_NCTF29 VCCSM_NCTF28 VCCSM_NCTF27 VCCSM_NCTF26 VCCSM_NCTF25 VCCSM_NCTF24 VCCSM_NCTF23 VCCSM_NCTF22 VCCSM_NCTF21 VCCSM_NCTF20 VCCSM_NCTF19 VCCSM_NCTF18 VCCSM_NCTF17 VCCSM_NCTF16 VCCSM_NCTF15 VCCSM_NCTF14 VCCSM_NCTF13 VCCSM_NCTF12 VCCSM_NCTF11 VCCSM_NCTF10 VCCSM_NCTF9 VCCSM_NCTF8 VCCSM_NCTF7 VCCSM_NCTF6 VCCSM_NCTF5 VCCSM_NCTF4 VCCSM_NCTF3 VCCSM_NCTF2 VCCSM_NCTF1 VCCSM_NCTF0 ALVISO-GM B36 AL24 AN24 A26 E26 G26 J26 B27 E27 G27 W27 AA27 AB27 AF27 AG27 AJ27 AL27 AN27 E28 W28 AA28 AB28 AC28 A29 D29 E29 F29 G29 H29 L29 P29 U29 V29 W29 AA29 AD29 AG29 AJ29 AM29 C30 Y30 AA30 AB30 AC30 AE30 AP30 D31 E31 F31 G31 H31 J31 K31 L31 M31 N31 P31 R31 T31 U31 V31 W31 AD31 AG31 AL31 A32 C32 Y32 AA32 AB32 AC32 AD32 AJ32 AN32 D33 E33 F33 G33 H33 J33 K33 L33 M33 N33 P33 R33 T33 U33 V33 W33 AD33 AF33 AL33 C34 AA34 AB34 AC34 AD34 AH34 AN34 B35 D35 E35 F35 G35 H35 J35 K35 L35 M35 N35 P35 R35 T35 U35 V35 W35 Y35 AE35 C36 AA36 AB36 AC36 AD36 AE36 AF36 AJ36 AL36 AN36 E37 H37 K37 M37 P37 T37 V37 Y37 AG37 A B C C D D E 6,9,40,41 CORE_GMCH_S0 CORE_GMCH_S0 4,5,6,7,9,16,18,36,40,41 FOR DDR2 Size A3 Date: Tuesday, July 12, 2005 VCCP_GMCH_S0 VCCP_GMCH_S0 1D8V_S3 4 7,9,11,12,38,39,40,41 Sheet E 1D8V_S3 4 VSS 3 3 CORE_GMCH_S0 2 NCTF 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Document Number GMCH (5 of 5) Leopard 3 10 of Rev 41 -1 81 82 87 88 95 96 103 104 111 112 117 118 VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 GND GND 201 DDR2-200P-4 Hi 9.2 mm 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 11 29 49 68 129 146 167 186 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 13 31 51 70 131 148 169 188 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 114 119 ODT0 ODT1 1 2 M_A_DATA0 M_A_DATA1 M_A_DATA2 M_A_DATA3 M_A_DATA4 M_A_DATA5 M_A_DATA6 M_A_DATA7 M_A_DATA8 M_A_DATA9 M_A_DATA10 M_A_DATA11 M_A_DATA12 M_A_DATA13 M_A_DATA14 M_A_DATA15 M_A_DATA16 M_A_DATA17 M_A_DATA18 M_A_DATA19 M_A_DATA20 M_A_DATA21 M_A_DATA22 M_A_DATA23 M_A_DATA24 M_A_DATA25 M_A_DATA26 M_A_DATA27 M_A_DATA28 M_A_DATA29 M_A_DATA30 M_A_DATA31 M_A_DATA32 M_A_DATA33 M_A_DATA34 M_A_DATA35 M_A_DATA36 M_A_DATA37 M_A_DATA38 M_A_DATA39 M_A_DATA40 M_A_DATA41 M_A_DATA42 M_A_DATA43 M_A_DATA44 M_A_DATA45 M_A_DATA46 M_A_DATA47 M_A_DATA48 M_A_DATA49 M_A_DATA50 M_A_DATA51 M_A_DATA52 M_A_DATA53 M_A_DATA54 M_A_DATA55 M_A_DATA56 M_A_DATA57 M_A_DATA58 M_A_DATA59 M_A_DATA60 M_A_DATA61 M_A_DATA62 M_A_DATA63 M_A_DATA[63..0] SMBD_ICH 3,19 SMBC_ICH 3,19 R575 10KR2 1 2 1 2 3D3V_S0 0329 SB R574 10KR2 3D3V_S0 C469 SCD1U16V C471 SC2D2U6D3V3MX-1 DY 1D8V_S3 8 M_A_DQS#[7..0] 8 M_A_DQS[7..0] 7,12 7,12 M_ODT0 M_ODT1 DDR_VREF_S3 C182 SCD1U16V C474 SC2D2U6D3V3MX-1 202 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 10 26 52 67 130 147 170 185 SDA SCL VDDSPD SA0 SA1 NC#50 NC#69 NC#83 NC#120 NC#163/TEST M_A_SDM0 M_A_SDM1 M_A_SDM2 M_A_SDM3 M_A_SDM4 M_A_SDM5 M_A_SDM6 M_A_SDM7 1D8V_S3 7,9,10,12,38,39,40,41 DDR_VREF_S3 7,40 DDR_VREF_S3 SMBD_ICH 195 SMBC_ICH 197 3,5,7,9,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 199 R573 10KR2 198 1 2 200 1 2 0329 SB C470 R572 10KR2 SCD1U16V 50 69 83 120 163 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 81 82 87 88 95 96 103 104 111 112 117 118 VREF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 8 9 12 15 18 21 24 27 28 33 34 39 40 41 42 47 48 53 54 59 60 65 66 71 72 77 78 121 122 127 128 132 133 138 139 144 145 149 150 155 156 161 162 165 168 171 172 177 178 183 184 187 190 193 196 GND GND 201 1D8V_S3 3D3V_S0 3D3V_S0 3D3V_S0 C472 SC2D2U6D3V3MX-1 DY 1D8V_S3 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR2-200P-5 DDR Socket Size Custom om VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD BA0 BA1 CLK_DDR1 7 CLK_DDR1# 7 M_A_SDM[7..0] 8 l.c 50 69 83 120 163 107 106 CK1 /CK1 ai NC#50 NC#69 NC#83 NC#120 NC#163/TEST M_A_BS0# M_A_BS1# CLK_DDR0 7 CLK_DDR0# 7 164 166 tm 198 200 NORMAL TYPE 199 SA0 SA1 M_A_BS2# 8,12 8,12 CK0 /CK0 ho 202 VDDSPD 8 8,12 M_CKE0_R# 7,12 M_CKE1_R# 7,12 f@ 1 C473 SC2D2U6D3V3MX-1 195 197 2 C386 SCD1U16V 2 1 DDR_VREF_S3 1 2 SDA SCL M_B_SDM0 M_B_SDM1 M_B_SDM2 M_B_SDM3 M_B_SDM4 M_B_SDM5 M_B_SDM6 M_B_SDM7 79 80 30 32 Document Number in ODT0 ODT1 M_ODT2 M_ODT3 10 26 52 67 130 147 170 185 CKE0 CKE1 Leopard 3 Date: Tuesday, August 16, 2005 Sheet Rev xa 114 119 7,12 7,12 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 M_CS0_R# 7,12 M_CS1_R# 7,12 11 he DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 CK1 /CK1 CLK_DDR4 7 CLK_DDR4# 7 M_B_SDM[7..0] 8 110 115 1 13 31 51 70 131 148 169 188 CLK_DDR3 7 CLK_DDR3# 7 164 166 /CS0 /CS1 2 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 8 M_B_DQS[7..0] CK0 /CK0 M_A_RAS# 8,12 M_A_WE# 8,12 M_A_CAS# 8,12 1 /DQS0 /DQS1 /DQS2 /DQS3 /DQS4 /DQS5 /DQS6 /DQS7 M_CKE2_R# 7,12 M_CKE3_R# 7,12 108 109 113 2 11 29 49 68 129 146 167 186 79 80 30 32 /RAS /WE /CAS NORMAL TYPE M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 8 M_B_DQS#[7..0] CKE0 CKE1 1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 M_CS2_R# 7,12 M_CS3_R# 7,12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 5 7 17 19 4 6 14 16 23 25 35 37 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175 158 160 174 176 179 181 189 191 180 182 192 194 M_B_DATA[63..0] 110 115 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 1 M_B_DATA0 M_B_DATA1 M_B_DATA2 M_B_DATA3 M_B_DATA4 M_B_DATA5 M_B_DATA6 M_B_DATA7 M_B_DATA8 M_B_DATA9 M_B_DATA10 M_B_DATA11 M_B_DATA12 M_B_DATA13 M_B_DATA14 M_B_DATA15 M_B_DATA16 M_B_DATA17 M_B_DATA18 M_B_DATA19 M_B_DATA20 M_B_DATA21 M_B_DATA22 M_B_DATA23 M_B_DATA24 M_B_DATA25 M_B_DATA26 M_B_DATA27 M_B_DATA28 M_B_DATA29 M_B_DATA30 M_B_DATA31 M_B_DATA32 M_B_DATA33 M_B_DATA34 M_B_DATA35 M_B_DATA36 M_B_DATA37 M_B_DATA38 M_B_DATA39 M_B_DATA40 M_B_DATA41 M_B_DATA42 M_B_DATA43 M_B_DATA44 M_B_DATA45 M_B_DATA46 M_B_DATA47 M_B_DATA48 M_B_DATA49 M_B_DATA50 M_B_DATA51 M_B_DATA52 M_B_DATA53 M_B_DATA54 M_B_DATA55 M_B_DATA56 M_B_DATA57 M_B_DATA58 M_B_DATA59 M_B_DATA60 M_B_DATA61 M_B_DATA62 M_B_DATA63 8 /CS0 /CS1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 2 BA0 BA1 M_B_RAS# 8,12 M_B_WE# 8,12 M_B_CAS# 8,12 1 107 106 108 109 113 2 M_B_BS0# M_B_BS1# DM1 8,12 M_A_A[13..0] /RAS /WE /CAS 1 M_B_BS2# 8,12 8,12 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 2 8,12 102 101 100 99 98 97 94 92 93 91 105 90 89 116 86 84 85 High 9.2mm M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 Low5.2 mm DM2 8,12 M_B_A[13..0] of -1 41 0D9V_S0 RN68 8,11 8,11 8,11 8,11 C364 2 2 2 2 2 2 2 SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX 8,11 8,11 8,11 8,11 C363 SCD1U16V 8 7 6 5 SRN56-1 1 2 3 4 1 C166 2 C165 1 C157 1 C164 M_A_A7 M_A_A6 M_A_A4 M_A_A2 M_CS3_R# M_B_CAS# M_B_WE# M_B_BS0# 1 2 3 4 M_B_A7 8,11 M_B_A4 8,11 M_B_A6 7,11 M_CKE3_R# 1 2 3 4 1 C192 SCD1U16V 2 C198 SCD1U16V 2 2 C174 SCD1U16V 1 1 1 C170 SCD1U16V 2 C147 SCD1U16V 2 2 2 1 1 C365 SC1U6D3V2KX SC1U6D3V2KX 2 1 1 C146 C186 SCD1U16V DY SCD01U16V2KX 0D9V_S0 2 C404 SCD1U16V 1 39 2 C358 1 1D8V_S3 2 C196 SCD1U16V 7,9,10,11,38,39,40,41 RN22 8 7 6 5 1D8V_S3 2 C356 1 DY SCD01U16V2KX 2 C399 SCD1U16V 1 2 C197 1 8 7 6 5 0D9V_S0 DY SCD01U16V2KX 1 SRN56-1 RN7 7,11 8,11 8,11 8,11 2 C180 1 SRN56-1 1 2 3 4 7,11 M_CKE2_R# 8,11 M_B_BS1# 8,11 M_B_A0 8,11 M_B_A2 1 C175 8 7 6 5 RN69 1 C200 1 1 1D8V_S3 1 PLACE CAPS BETWEEN AND NEAR DDR SKTS PLACE EACH 0.1UF CAP CLOSE TO POWER PIN 1 2 3 4 M_A_A1 M_A_A0 M_A_A3 M_A_A10 DY SCD01U16V2KX 1 2 C202 SCD1U16V 1 2 C396 SCD1U16V SRN56-1 RN49 1 1 EC42 SCD1U16V 2 EC36 SCD1U16V 2 2 EC39 SCD1U16V 2 2 C375 C383 SC10U10V5ZY-L SC10U10V5ZY-L 1 1 1 1 C203 SCD1U16V 2 2 1 8,11 EC44 SCD1U16V 8 7 6 5 SRN56-1 0D9V_S0 RN21 8 7 6 5 Address / Command 8,11 8,11 7,11 8,11 1 2 3 4 M_A_BS1# M_A_RAS# M_CS0_R# M_A_A13 SC2D2U6D3V3MX-1 C389 TC23 ST100U4VBM-U 2 2 C390 2 1 1 1 SC2D2U6D3V3MX-1 C392 2 2 C384 2 C366 DY SCD01U16V2KX 2 C194 SCD1U16V 1 2 C357 1 DY SCD01U16V2KX SRN56-1 1 SC2D2U6D3V3MX-1 1 1 1 2 C355 2 C403 1 RN50 1 2 3 4 SRN56-1 8,11 8,11 M_B_A8 M_B_A9 8,11 M_B_A12 8,11 M_B_BS2# SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 2 C161 SCD1U16V 1 8 7 6 5 2 C388 1 DY SCD01U16V2KX RN48 1 2 3 4 8,11 M_B_A13 7,11 M_CS2_R# 8,11 M_B_RAS# 8,11 M_B_A11 8 7 6 5 1 8 7 6 5 1 8 7 6 5 1 2 C181 SCD1U16V 2 C385 1 DY SCD01U16V2KX SRN56-1 RN67 For 1GB Memory 8,11 8,11 8,11 7,11 1 2 3 4 M_A_WE# M_A_BS0# M_A_CAS# M_CS1_R# 2 C405 SCD1U16V 2 C177 1 DY SCD01U16V2KX SRN56-1 RN8 8,11 8,11 8,11 8,11 1 2 3 4 M_B_A10 M_B_A1 M_B_A3 M_B_A5 2 C401 SCD1U16V 2 C187 1 DY SCD01U16V2KX SRN56-1 Control RN70 7,11 M_CKE0_R# 8,11 M_A_BS2# 8,11 M_A_A12 8,11 M_A_A9 1 2 3 4 8 7 6 5 1 2 C193 SCD1U16V 1 2 C387 SCD1U16V 8 7 6 5 1 SRN56-1 RN71 7,11 M_CKE1_R# 8,11 M_A_A11 8,11 M_A_A8 8,11 M_A_A5 1 2 3 4 DY 1 SRN56-1 2 C395 SCD1U16V 2 C171 DY SCD01U16V2KX 0D9V_S0 7,11 M_ODT0 R585 1 2 56R2J 7,11 M_ODT1 R586 1 2 56R2J 7,11 M_ODT2 R587 1 2 56R2J Wistron Corporation 7,11 M_ODT3 R588 1 2 56R2J 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title DDR Serial/Terminator Resistor Size A3 Document Number Rev -1 Leopard 3 Date: Thursday, August 18, 2005 Sheet 12 of 41 A C D 5V_S0 5V_S0 3,5,7,9,11,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 17 1 BC13 C99 SC3P50V2CN SC3P50V2CN JVGA_HS 7 JVGA_VS 7 DY 1 1 BAV99LT1 R94 C102 150R2F SC3P50V2CN DY 22 15 CRT_B 15 JST-CON20 R91 150R2F 56 55 2 1 RJ45-7 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 RJ45-8 26 RJ45-3 26 RJ45-6 26 JACK_DETECT# 28 58 57 PR_PRESENT# 26 26 26 26 RJ45-4 RJ45-5 RJ45-1 RJ45-2 MIC_PR AUD_AGND 28 DK_SPKR_R+ 28 DK_SPKR_L+ 31 VOL_UP_DK# 17 USB_PN7 17 USB_PP7 LINE-OUT USB_PN7 USB_PP7 IR_OUT TPAD30 TP40 R333 CN6 1 MIC_PR 2 0R2-0 EXT_MIC_1 27 EXT_MIC_2 27 31 VOL_DWN_DK# HP_OUT_R 27 HP_OUT_L 27 COMP_PR LUMA_PR CRMA_PR CIR_PR 5V_DOCK 1 MIC-IN EARPHONE 28 LID_SW 14 DCBATOUT_BEAD AD+ R65 1KR2 SPDIF 5V_Dock_S0 1 2 R43 0R2-0 DCBATOUT 26 14,35,37,38,39,40,41 5V_AUX 5V_DOCK DOCK_PRESENT AD+ 1 26 26 26 26 JACK_DETECT# 1 MUTE_LED 1 AUD_AGND 1 MIC_PR 1 DK_SPKR_R+ 1 DK_SPKR_L+ 1 COMP_PR 1 VOL_UP_DK# 1 VOL_DWN_DK# 1 DOCK_PRESENT 1 PR_PRESENT# 1 BT_LED 3D3V_S3 14,26 2 2 3 INPUT BAV99LT1 FUNCTION Place near the GMCH 1 2 R495 DUMMY-R2 ICH_PME# 17,25,29 DY 2 R225 DUMMY-R2 PCI_AD24 17,22,25,29 LOW B0 HIGH B1 5V_S0 U7 5V_S3 AD+ 5V_S0 DCBATOUT_BEAD LUMA 5V_S0 C297 SC47P50V2JN 2 L19 SPDIF 2 BLM18PG600SN1 PR_INSERT# 6 5 4 S VCC A C294 SC47P50V2JN C307 SC47P50V2JN CRMA_VGA 7 NC7SB3157P6X-U R536 2 2 IND-1D2UH R335 150R2F 2 COMP_VGA 7 0R2-0 1 C298 C295 SC47P50V2JN SC47P50V2JN 1 1 L25 1 SC470P25V2KN 1 R372 150R2F 2 2 COMP_PR 2 EC124 SCD1U16V 1 B1 GND B0 C51 C464 SC470P25V2KN 2 2 PR_PRESENT# 1 2 3 1 1 1 1 SPDIF_OUT 1 R64 2K2R2 2 1 SPDIF_OUT 2 3 27 CRMA_PR_1 2 IND-1D2UH 2 CRMA_PR 1 L24 PR_INSERT# 31 Q17 S2N3904-U3 1 LUMA_VGA 7 U8 2 1 2 47R2 PR_INSERT# 6 5 4 S VCC A NC7SB3157P6X-U CRMA PR_INSERT# 1 B1 GND B0 R334 150R2F R309 10KR2 R63 1 2 3 2 C338 SCD1U16V C296 SC47P50V2JN 1 C69 SCD1U25V3KX 2 2 C70 C458 SCD1U25V3KX SCD1U16V 1 1 1 1 C337 SCD1U16V 2 1 2 5V_S0 2 1 Please close to ICH6 LUMA_PR_1 2 IND-1D2UH L26 2 LUMA_PR 1 1 BC0EX2 DY 1 1 2 BC0EX1 DOCK_PRESENT 3 D31 1 26 2 EC8 SCD1U16V 2 EC11 SCD1U16V 2 EC93 SCD1U16V 2 EC95 SC1000P16V2KX 2 EC94 SC1000P16V2KX 2 EC102 SC1000P16V2KX 2 EC100 SC1000P16V2KX 2 EC101 SC1000P16V2KX 2 EC103 SC1000P16V2KX 2 EC20 SC1000P16V2KX 2 EC92 SC1000P16V2KX 2 EC19 SC1000P16V2KX 1 BT_LED LID_SW 2 5V_AUX 5V_S0 MUTE_LED 14,31 1394_TPA1P_PR 1394_TPA1N_PR 1394_TPB1P_PR 1394_TPB1N_PR FOX-CONN58D-U3 EARPHONE 26 DCBATOUT 14,15,35,37,38,39 59 AUD_AGND R432 47KR2 63.47334.1D1 5V_S3 4 MH2 2 3D3V_S0 MOLEX-CON10-1 5V_S3 14,26,28,30,32,37,38,40,41 MH1 DY Analog Signal CONN 11 1 2 3 4 5 6 7 8 9 10 12 5V_S0 CN12 BAV99LT1 DY 15 CRT_G 3 1 5V_S0 CRT_R 5V_S0 14,18,19,20,21,23,24,27,28,29,32,36,39,40,41 60 CRMA 2 BLM11B750S 3D3V_S0 2 BC12 SC3P50V2CN L15 VOL_DWN_DK# 1 1 1 VOL_UP_DK# 3 LUMA 2 BLM11B750S 2 DDC_DATA 15 DDC_CLK 15 L12 2 2 CRMA_CN5 5V_S3 1 CRMA_CN5 LUMA_CN5 1 1 LUMA_CN5 USB_PP3 17 USB_PN3 17 Docking Connector D30 2 2 USB_PP3 USB_PN3 D29 17 USB_PN1 5V_S3 USB_PN1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 4 USB_PP1 USB_PP1 1 2 21 3 E 3D3V_S0 Digital Signal CONN 2 CN5 B Place near the DOCK 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. CIR_KBC 31 Title ho TC15 ST47U6D3V-U1 B C D Rev 41 -1 xa Leopard 3 Date: Monday, August 15, 2005 of in Document Number f@ Board to board conn/ Docking Size A3 CIR,CIR_PR,CIR_KBC are connect togather. default setting 12/12 DY A om R259 2 0R2-0 R371 2 0R2-0 l.c CIR_PR 2 1 C306 C305 SC4D7U10V5ZY SCD1U16V 2 1 2 FUSE-2A6V 1 CIR ai 15 100 mil 2 tm 5V_DOCK F3 1 1 Sheet E he 5V_S3 2 2 DY AUD_AGND 1 13 A B C D E 3D3V_S0 3,5,7,9,11,13,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 INVERTER/LCD 3D3V_S3 3D3V_LCD_S0 3D3V_S0 3D3V_LCD_S0 SI3865_R1C1 13,30,40 3D3V_S3 2 BC61 SC6800P50V3KX 1 5V_S0 3 TXBOUT2TXBOUT2+ 7 7 TXBCLKTXBCLK+ 7 7 EDID_CLK EDID_DAT 3D3V_S0 31 BRIGHTNESS 31 FPBACK DCBATOUT 1 1 1 2 R1 2 IN 2N7002-F-GP 2 Q21 OUT 3 802_BT_LED# R1 GND 1 G R2 DTC114EUA-U1 LID_SW 2 100KR2 LID_SW 802_BT_LED 2 IN 2 802_ACT_LED 29 1 BT_LED 3 R2 DTC114EUA-U1 22 2 IN 7421_LED 3 3 OUT R1 7421_LED# 1 GND 5V_S3 5V_S0 R2 DTC114EUA-U1 Q6 31 2 IN CAPS_LED 3 OUT R1 CAPS_LED# 5V_S3_PA 1 GND R538 R2 DTC114EUA-U1 46 ID_DET 1 Q33 2N3906-2-U 2 1 47KR2 MH2 42 5V_S0_PA R539 44 31 2 IN NUM_LED IPEX-CON40-1-U1 3 OUT R1 ID_DET 1 Q34 2N3906-2-U 2 1 47KR2 NUM_LED# 32 1 GND R2 DTC114EUA-U1 5V_AUX LED6 Blue Blue LED8 LED7 LED1 U64 LED9 Blue LED1 Amber 2 2 1 LED2 Blue 31,32 3 HDD_LED# 21 ID_DET ID_DET IDE_LED# LED2 Q38 ID_DET#1 G R546 LED10 CAPS_LED# 2 R93 LED-O-10 NC R258 1 2 1K2R2J-1 LED6 2 5V_S0_PA R549 2 200R2J 1 NC 2 1K2R2J-1 1 2 1K2R2J-1 CHG_LED# 1 2 200R2J PWR_LED# 1 LED-O-11-U A Q13 31 2 IN PWR_LED PWR_LED# 32 1 GND R2 DTC114EUA-U1 IDE_LED# 1 Wistron Corporation LED8 1 CHG_LED# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. NC R548 2 200R2J Title Inverter/LCD LED7 2 1 Size A3 PWR_LED# LED-B-54-U B 3 OUT R1 LED9 2 5V_S3_PA 1 7421_LED# CHG_LED# 1 GND R2 DTC114EUA-U1 LED-B-54-U LED4 2 2 1 R550 1 NC R256 CAPS_LED# 3 OUT R1 LED-B-54-U LED-O-11-U 5V_S3_PR 2 2 5V_AUX_PA LED5 2 1 IDE_LED# 1 R257 Q14 2 IN CHG_LED LED-B-53 1 5V_AUX_PR MUTE_LED# 32 1 GND R2 DTC114EUA-U1 LED-B-53 LED2 R112 2 200R2J 1 LED-O-11-U 1 1 7421_LED# 2 LED-O-10 3 OUT R1 LED1 2 100R2 NC 2 1 1K2R2J-1 1 5V_S0_PA LED11 5V_S0_PR 2 IN 31 5V_S0_PR R547 13,31 MUTE_LED 5V_S0_PA NC 2 1 1K2R2J-1 1 3 2N7002-F-GP Q20 Q39 2N3906-2-U 2 1 47KR2 S change R from 100 to 200 ohm 5V_S0_PR CDROM_LED# 21 5V_AUX_PR R545 1 Q36 2N3906-2-U 2 1 47KR2 2 R544 47KR2 2 LED5 Blue Amber 1 2 LED4 PA Top U42 ID_DET# Q37 2N3906-2-U 1 D Amber Amber Amber DY 2 PR Botton R542 10KR2 R543 100KR2 Q35 2N3906-2-U 2 1 47KR2 3 1 7421 2 CAPS IR 1 HDD 2 1 R541 3 ID_DET# 5V_AUX_PA 5V_S0_PR 2 5V_S3_PR R540 CHR 13,26 CH715F Q9 5V_AUX PWR 13 C352 SC1000P50V D19 32 1 GND 2 2 2 LCDVDD_ON 1 KBC_LID# Q19 3 OUT 1 1 1 1 Q18 R431 31 R316 150R2 R314 10KR2 Q22 C291 BC56 BC59 BC55 SC1000P16V2KX SCD1U16V SCD1U SCD1U16V 2 C292 SC1000P16V2KX 2 1 5V_S0 3D3V_LCD_S0 5V_S5 2 7 7 DCBATOUT R430 4K7R2 3 TXBOUT1TXBOUT1+ 35,37,38,39,40,41 1 7 7 3D3V_S3 2 TXBOUT0TXBOUT0+ R318 47KR2 SI3865DV-U 84.03865.03D 2 7 7 4 DCBATOUT 3 TXACLKTXACLK+ 5V_S5 18,20,36,38 5V_S5 1 7 7 5V_S0 SI3865_R2 1 2 3 2 TXAOUT2TXAOUT2+ BC57 SCD1U16V D 7 7 R2 D2 D2 S TXAOUT1TXAOUT1+ BC60 SC1U10V3ZY 45 R1/C1 ON/OFF S2 1 7 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 5 4 2 TXAOUT0TXAOUT0+ MH1 R317 2 270KR2F 1 2 LCDVDD_ON_1 1KR2 1 LCDVDD_ON 2 1 7 7 7 13,18,19,20,21,23,24,27,28,29,32,36,39,40,41 1 R315 43 2 CN3 41 2 BC10 SC10U10V6ZY-U 2 BC11 SCD1U16V 4 1 1 U49 Document Number Date: Monday, August 15, 2005 C D Rev -1 Leopard 3 Sheet E 14 of 41 A B C D E PA & PR diffent parts PA PR 2D5V_S0 83.00190.W70 83.00190.W70 83.00110.D70 83.00110.D70 83.00110.D70 Dummy Dummy Dummy Dummy 56.15006.001 63.12234.1D1 63.12234.1D1 63.12234.1D1 63.12234.1D1 63.12234.1D1 4 3 83.00190.Y70 83.00190.Y70 Dummy Dummy Dummy 83.00110.E70 83.00110.E70 83.00110.E70 56.15006.001 Dummy 63.20134.1D1 63.20134.1D1 63.20134.1D1 63.20134.1D1 63.20134.1D1 2D5V_S0 CRT 7,13 7,13 CBUS1 21.H0088.001 21.H0088.001 R176 63.10334.1D1 Dummy R177 Dummy 63.10334.1D1 13 DDC_CLK 1 13 DDC_DATA 1 JVGA_HS L8 L7 2 DDC_CLK_CON BLM11B750S 2 DDC_DATA_CON BLM11B750S JVGA_HS JVGA_VS 4 U12 VGA_HSYNC JVGA_VS RN37 SRN2K2J 1 2 4 LED1 LED2 LED4 LED5 LED6 LED7 LED8 LED9 U64 U42 R256 R257 R258 R93 R112 7 GMCH_DDCDATA 7,13 VGA_VSYNC 7,13 DDC_CLK_CON 4 3 5 2 6 1 DDC_DATA_CON GMCH_DDCCLK 7 2N7002DW 7 VGA_BLUE 1 7 VGA_GREEN 1 7 VGA_RED 1 L5 2 BLM11B750S 2 BLM11B750S L9 2 BLM11B750S L6 CRT_B CRT_G CRT_B 13 CRT_G 13 CRT_R 13 3 3 CRT_R 2 1 C86 SC10P50V2JN-1 1 2 2 1 C87 SC10P50V2JN-1 1 2 2 SC10P50V2JN-1 2 2 2 C84 SC10P50V2JN-1 C100 1 C101 1 R84 75R2F 2 R85 75R2F SC10P50V2JN-1 1 1 1 R92 75R2F SB SC10P50V2JN-1 C103 SB Close to CN5 Close to U17 (N/B) CIR FOR FF 5V_AUX 2 1 1 2 IR-TSOP6236-U GND GND VS OUT 1 2 3 4 R261 100R2 2 2 R260 10KR2 CIR 2 C273 SC4D7U10V5ZY CIR 13 1 U64 IR-TSOP6236-U GND GND VS OUT DY 1 2 3 4 1 1 U42 Title B C D Sheet E 15 41 in Rev of xa Leopard 3 f@ Date: Monday, August 15, 2005 A ho CRT/ CIR Document Number he Size A3 tm ai l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. -1 A B C D E 3D3V_S0 3D3V_AUX RTC_AUX_S5 C256 2 SC4D7P50V3CN D13 1 U35A 20,31,39 RSMRST# 27,30 AC97_BITCLK 27,30 AC97_SYNC 1 27,30 AC97_RST# 1 27 30 R192 2 33R2 R191 2 33R2 LAN_RSTSYNC E12 E11 C13 LANRXD[0] LANRXD[1] LANRXD[2] C12 C11 E13 LANTXD[0] LANTXD[1] LANTXD[2] AC97_SYNC_ICH C10 B9 ACZ_BIT_CLK ACZ_SYNC AC97_RST#_ICH A10 ACZ_RST# F11 F10 B10 AC97_DIN0 AC97_DIN1 R493 2 33R2 1 27,30 AC97_DOUT AC97_DOUT_ICH C9 AC19 1 2R496 0R2-0 AE3 AD3 AG2 AF2 CPUSLP# AE27 H_CPUSLP#_ICH R310 1 2 0R2-0 H_CPUSLP# 4,6 DPRSLP# DPSLP# AE24 AD27 H_DPRSLP#_R H_DPSLP#_R R160 1 R148 1 2 0R2-0 2 0R2-0 H_DPRSLP# 4 H_DPSLP# 4 FERR# AF24 H_FERR_R R159 1 2 56R2J CPUPWRGD/GPO[49] AG25 H_PWRGD 4 IGNNE# INIT3_3V# INIT# INTR AG26 AE22 AF27 AG24 H_IGNNE# 4 H_INIT# H_INTR 4 4 RCIN# AD23 RCIN# 31 NMI SMI# AF25 AG27 H_NMI H_SMI# 4 4 STPCLK# AE26 H_STPCLK# 4 ACZ_SDO THRMTRIP# AE23 SATALED# SATA[2]RXN SATA[2]RXP SATA[2]TXN SATA[2]TXP AC2 AC1 SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS Place within 500 mils of ICH6 ball 1 R195 0R2-0 21 21 21 21 21 IDE_IORDY IDE_IRQ14 IDE_DACK# IDE_IOW# IDE_IOR# AF16 AB16 AB15 AC14 AE16 IORDY IDEIRQ DDACK# DIOW# DIOR# 1 12/12 INTEL check list DY R162 56R2J H_FERR# 4 R717 R388 R370 Dothan A DUMMY 56R 0R Dothan B 0R 0R DUMMY 3 VCCP_GMCH_S0 H_THERMTRIP_R R157 75R2 R6V9 1 AC16 AB17 AC17 IDE_A0 IDE_A1 IDE_A2 DCS1# DCS3# AD16 AE17 IDE_CS#0 21 IDE_CS#1 21 DD[0] DD[1] DD[2] DD[3] DD[4] DD[5] DD[6] DD[7] DD[8] DD[9] DD[10] DD[11] DD[12] DD[13] DD[14] DD[15] AD14 AF15 AF14 AD12 AE14 AC11 AD11 AB11 AE13 AF13 AB12 AB13 AC13 AE15 AG15 AD13 IDE_D0 IDE_D1 IDE_D2 IDE_D3 IDE_D4 IDE_D5 IDE_D6 IDE_D7 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 DDREQ AB14 DA[0] DA[1] DA[2] SATA[0]RXN SATA[0]RXP SATA[0]TXN SATA[0]TXP 2 2 ACZ_SDIN[0] ACZ_SDIN[1] ACZ_SDIN[2] AD7 AC7 AF6 AG6 SATA_RBIAS_PN AG11 AF11 ICH_A20GATE 31 H_A20M# 4 2 10KR2 2 10KR2 21 21 21 R158 2 56R2J R6V7 PM_THRMTRIP-I# 4,7 Layout Note: R6V7 needs to placed within 2" of ICH6, R6V9 must be placed within 2" of R6V7 w/o stub. 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 IDE_DREQ 21 2 VCCP_GMCH_S0 R149 56R2J VCCP_GMCH_S0 DY H_DPSLP# 1 LAN_CLK B11 3 AF22 AF23 1 LPC_LDRQ1# 1 R501 VCCP_GMCH_S0 S DY A20GATE A20M# EE_CS EE_SHCLK EE_DOUT EE_DIN RCIN# 1 DY G LPC_LFRAME# 31 LPC_LDRQ1# 2 2 Q11 2N7002-F-GP LAN_RSTSYNC 2 10KR2 P3 R488 2 1 ICH_TP5 F12 LFRAME#/FWH[4] 3D3V_S0 Open J5G1 for Dothan A step Shunt for Dothan B step & all Yonah LPC_LDRQ0# 31 1 D R194 INTRUDER# INTVRMEN CPU 1 TPAD30 TP67 R249 10KR2 LDRQ[0]# LDRQ[1]#/GPI[41] N6 P4 2 D12 B12 D11 F13 RTCRST# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 P2 N3 N5 N4 LPC AA3 AA5 RTC AA2 INTRUDER# 31 LAD[0]/FWH[0] LAD[1]/FWH[1] LAD[2]/FWH[2] LAD[3]/FWH[3] RTCX1 RTCX2 LAN RCT_RST# 3D3V_S0 The symbol use 2nd source The P/N is the main source Main source:20.D0152.103 2nd source:20.D0012.103 Y1 Y2 AC-97/AZALIA 1 RCT_X1 RCT_X2 SATA IDE GAP-OPEN LPC_LAD[3..0] 2 C255 SC3D9P50V3CN 2 BAT2 1 VCCP_GMCH_S0 4 2 2 G66 R508 C455 1MR2 SC1U10V3ZY RTC1 ETY-CON3-S1 4,5,6,7,9,10,18,36,40,41 2 20KR2 1 RTC circuitry 2 3 5 4 1 R228 10MR2J 2 2 CH751H-40-U R250 1KR2 VCCP_GMCH_S0 1 X4 XTAL-32D768K-4P 1 1 1 1 2 3D3V_AUX 4 C257 SC1U10V3ZY R507 D14 1 4 3D3V_AUX 20,31,32,34,35,36,37 3 CH751H-40-U 2 RTC_VCC 2 3D3V_S0 1 1 3,5,7,9,11,13,14,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 R161 56R2J ICH6M 2 DY H_DPRSLP# 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH6-M (1 of 4) Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 16 of 41 A B C D E U35C U35B A3 E1 R2 C3 E3 C5 G5 J1 J2 PCI_IRDY# 22,25,29 21 PCI_PAR 22,25,29 ICH_PCIRST# 19 PCI_DEVSEL# 22,25,29 PCI_PERR# 22,25,29 PLTRST# PCICLK PME# R5 G6 P6 3D3V_S0 3 TP79 TP80 TP34 TP33 TP78 N2 L2 M1 L3 ICH_TP8 ICH_TP9 ICH_TP10 ICH_TP11 ICH_TP12 AC5 AD5 AF4 AG4 AC9 SMB_LINK_ALERT# SMLINK0 SMLINK1 MCH_SYNC# 3D3V_S5 PCI_LOCK# 1 TP75 TPAD30 TP74 TPAD30 1 2 10KR2 R193 TP73 TPAD30 R227 27 10KR2 22,25,29 22,25,29 22,25,29 22,25,29 ICH_SPKR PM_BMBUSY# 7 SB PCI_SERR# 22,25,29 PCI_STOP# 22,25,29 PCI_TRDY# 22,25,29 3 FRAME# PIRQ[A]# PIRQ[B]# PIRQ[C]# PIRQ[D]# PIRQ[E]#/GPI[2] PIRQ[F]#/GPI[3] PIRQ[G]#/GPI[4] PIRQ[H]#/GPI[5] RESERVED RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5] RSVD[6] RSVD[7] RSVD[8] TP[3] D9 C7 C6 M3 INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH# AD9 AF8 AG8 U3 ICH_TP13 ICH_TP14 ICH_TP15 ICH_TP16 SUS_STAT#/LPCPD# SYS_RESET# ICH_GPI7 ECSMI# S1N4148-U2 DY SMBALERT#/GPI[11] M2 R6 GPI[12] GPI[13] ICH6_GPO19 ICH6_GPO21 ICH_GPO27 INT_PIRQD# INT_PIRQG# INT_PIRQF# INT_PIRQE# PCB_VER0 PCB_VER1 2 3D3V_S0 1 2 3 4 5 10 9 8 7 6 3D3V_S0 PCIE_WAKE# PM_BATLOW#_R 31 1 2 3 4 5 10 9 8 7 6 1 2 3 4 3D3V_S0 INT_PIRQH# PCI_REQ#2 PCI_REQ#3 PM_CLKRUN# SRP10K RP2 PCI_REQ#5 INT_PIRQA# INT_PIRQC# INT_PIRQB# RN35 PM_RI# SMB_LINK_ALERT# SMLINK0 SMLINK1 PM_SUS_STAT# R504 1 8 7 6 5 R505 1 2 8K2R2 2 10KR2 DY 3D3V_S0 PCI_SERIRQ MCH_SYNC# PCI_REQ#0 PM_THRM# SRP10K R190 1 2 10KR2 ICH_GPI7 R172 1 2 10KR2 GPI12 R500 1 2 10KR2 V3 GPIO[24] GPIO[25] GPIO[27] GPIO[28] CLKRUN# GPIO[33] GPIO[34] WAKE# SERIRQ THRM# 20 VRM_PWRGD AF21 VRMPWRGD 3 CLK_ICH14 E10 3 CLK48_USB A27 PM_SUS_CLK SUSCLK SLP_S3# SLP_S4# SLP_S5# AA1 1 R489 36 PM_DPRSLPVR 2 100R2 PM_DPRSLPVR_R PM_BATLOW#_R 31 PM_PWRBTN# PLT_RST# R481 100KR2 31 RSMRST#_KBC CLK48 T4 T5 T6 ICH_SLP_S5# ICH6_PWROK CLK14 V6 TPAD30 TP76 20 3D3V_S0 PCI_REQ#1 GPO[21] GPO[23] AB20 TPAD30 TP77 PM_SUS_STAT#R506 1 STP_CPU# AD20 AD21 AC20 21,28,31,37,38,40 PM_SLP_S3# 21,31,37,38 PM_SLP_S4# SRN10K 2 5K6R2 AD22 U5 1 SRP10K RP1 PCI_SERR# PCI_DEVSEL# PCI_PERR# PCI_LOCK# 3D3V_S5 3D3V_S0 GPO[19] AE20 PWROK DPRSLPVR V2 BATLOW# U1 PWRBTN# V5 LAN_RST# Y3 RSMRST# PERn[1] PERp[1] PETn[1] PETp[1] PERn[2] PERp[2] PETn[2] PETp[2] K25 K24 J27 J26 PERn[3] PERp[3] PETn[3] PETp[3] M25 M24 L27 L26 PERn[4] PERp[4] PETn[4] PETp[4] P24 P23 N27 N26 DMI[0]RXN DMI[0]RXP DMI[0]TXN DMI[0]TXP T25 T24 R27 R26 DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 7 7 7 7 DMI[1]RXN DMI[1]RXP DMI[1]TXN DMI[1]TXP V25 V24 U27 U26 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 7 7 7 7 DMI[2]RXN DMI[2]RXP DMI[2]TXN DMI[2]TXP Y25 Y24 W27 W26 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 7 7 7 7 DMI[3]RXN DMI[3]RXP DMI[3]TXN DMI[3]TXP AB24 AB23 AA27 AA26 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3 7 7 7 7 DMI_CLKN DMI_CLKP AD25 AC25 CLK_PCIE_ICH# 3 CLK_PCIE_ICH 3 PCIE_TXN0_R PCIE_TXP0_R 1 C207 1 C208 2 2 SCD1U16V SCD1U16V PCIE_TXN0 21 PCIE_TXP0 21 4 DMI_ZCOMP F24 DMI_IRCOMP F23 OC[4]#/GPI[9] OC[5]#/GPI[10] OC[6]#/GPI[14] OC[7]#/GPI[15] C23 D23 C25 C24 USB_OC#4 USB_OC#5 USB_OC#6 USB_OC#7 OC[0]# OC[1]# OC[2]# OC[3]# C27 B27 B26 C26 USB_OC#0 USB_OC#1 USB_OC#2 USB_OC#3 USBP[0]N USBP[0]P USBP[1]N USBP[1]P USBP[2]N USBP[2]P USBP[3]N USBP[3]P USBP[4]N USBP[4]P USBP[5]N USBP[5]P USBP[6]N USBP[6]P USBP[7]N USBP[7]P C21 D21 A20 B20 D19 C19 A18 B18 E17 D17 B16 A16 C15 D15 A14 B14 USBRBIAS# USBRBIAS A22 B22 Layout Note: PCIE AC coupling caps need to be within 250 mils of the driver. 1D5V_S0 Place within 500 mils of ICH 3 R479 24D9R2F DMI_IRCOMP_R RP3 USB_OC#0 USB_OC#1 USB_OC#3 USB_OC#2 3D3V_S5 1 2 3 4 5 10 9 8 7 6 3D3V_S5 USB_OC#5 USB_OC#4 USB_OC#7 USB_OC#6 SRP10K TP27 TPAD30 TP28 TPAD30 USB_PN1 USB_PP1 USB_PN2 USB_PP2 USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN6 USB_PP6 USB_PN7 USB_PP7 13 13 26 26 30 30 30 30 21 21 13 13 13 13 2 R156 USB_RBIAS_PN 1 2 Intel 22.6 ohm 1% 22D6R2F 2 3D3V_S0 10 9 8 7 6 STP_PCI# AB21 PM_THRM# 20 ICH6 Pullups RP4 1 2 3 4 5 AC21 P5 R3 T3 AF19 AF20 AC18 22,29,31 PCI_SERIRQ PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# GPI[7] GPI[8] GPI12 ECSWI# 21 PCIE_WAKE# ICH6M BMBUSY# AE19 R1 W6 PM_STPPCI# TPAD30 TP69 TPAD30 TP89 AD19 ECSCI# 3,36 PM_STPCPU# TPAD30 TPAD30 TPAD30 TPAD30 SMBCLK SMBDATA LINKALERT# SMLINK[0] SMLINK[1] MCH_SYNC# SPKR U2 INT_PIRQE# 25,29 INT_PIRQF# 22 INT_PIRQG# 22 TP81 TP31 TP32 TP83 Y4 W5 Y5 W4 U6 AG21 F8 W3 1 21 NEWCARD_RST# 26 BT_EN 29 WIRELESS_EN# 22,25,29,31 PM_CLKRUN# SATA[0]GP/GPI[26] SATA[1]GP/GPI[29] SATA[2]GP/GPI[30] SATA[3]GP/GPI[31] SYS_RESET# TPAD30 TP68 PLT_RST# 19 CLK_ICHPCI 3 ICH_PME# 13,25,29 RI# AF17 AE18 AF18 AG18 PM_SUS_STAT# D34 3 CPPE# Interrupt I/F INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# SRN100K 19,21 SMB_CLK 19,21 SMB_DATA TP72 TPAD30 SATA0_R0 SATA0_R1 SATA0_R2 SATA0_R3 8 7 6 5 PCIE_RXN0 21 PCIE_RXP0 21 1 IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# PCI_REQ#3 ICH_GNT3 PCB_VER2 ICH_GPO48 PCI_REQ#5 ICH_GPO17 ICH_GPI0_R ICH_GPO16 1 2 3 4 H25 H24 G27 G26 2 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 PCI_REQ#2 29 29 22 22 25 25 GPIO C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]# J6 H6 G4 G2 PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#1 PCI-EXPRESS RN33 L5 C1 B5 B6 M5 F1 B8 C8 F7 E7 E8 F6 B7 D8 CLOCKS PCI_REQ#0 REQ[0]# GNT[0]# REQ[1]# GNT[1]# REQ[2]# GNT[2]# REQ[3]# GNT[3]# REQ[4]#/GPI[40] GNT[4]#/GPO[48] REQ[5]#/GPI[1] GNT[5]#/GPO[17] REQ[6]#/GPI[0] GNT[6]#/GPO[16] PCI POWER MGT USB J3 22,25,29 PCI_FRAME# AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] 2 4 E2 E5 C2 F5 F3 E9 F2 D6 E6 D3 A2 D2 D5 H3 B4 J5 K2 K5 D4 L6 G3 H4 H2 H5 B3 M6 B2 K6 K3 A5 L1 K4 T2 Direct Media Interface PM_RI# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 PCIE AC coupling caps need to be within 250 mils of the driver. 3D3V_S0 13,22,25,29 PCI_AD[31..0] Place within 500 mils of ICH ICH6M 3D3V_S0 ICH_TP16 ICH_TP9 ICH_TP8 ICH_TP13 3D3V_S5 1 R503 100KR2 3D3V_S0 3D3V_S0 3,5,7,9,11,13,14,16,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 STUFF R7F8 A16 Swap Override NO_STUFF STUFF R7F7 Boot BIOS NO_STUFF STUFF 1 D12 6 1 ECSMI#_KBC 31 ECSCI# 5 2 ECSCI#_KBC 31 ECSWI# 4 3 ECSWI#_KBC 31 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title ICH6-M (2 of 4) CH731U-U Size A3 Document Number Leopard 3 Date: Monday, August 15, 2005 A B om ECSMI# l.c 0 0 0 0 1 NO_STUFF ai 0 1 0 1 0 No Reboot tm 18,19,21,25,29,31,35,37,39,40 0 0 1 1 0 R7F9 C D ho 5,7,9,18,21,38,39,41 3D3V_S5 PCB_VER2 OPTIONAL OVERRIDE Sheet E f@ 1D5V_S0 3D3V_S5 PCB_VER1 DEFAULT Rev of 41 in 1 2 1D5V_S0 PCB_VER0 FUNCTION -1 xa 2 2 DY Ver. SA SB SC -1 -2 REF he DY R248 DUMMY-R2 10KR2 DUMMY-R2 1 R246 PUMA Board Version Setting R502 100KR2 2 PCB_VER2 PCB_VER0 PCB_VER1 R226 100KR2 2 2 2 SRN0 ICH6-M Strapping Options 1 8 7 6 5 1 1 1 2 3 4 2 1 DUMMY-R2 SB 10KR2 R591 1 R247 10KR2 1 2 DY R245 1 RN36 R590 17 A B C D E 1D5V_S0 Layout Note: Place above caps within 100 mils of ICH near F27, P27, AB27 3,5,7,9,11,13,14,16,17,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 39 2 1 1 1 2 2 2 2 2 1 1 2 1 2 D11 CH751H-40-U 12 1D5V_S5 1 1D5V_ICH_S5 1 R189 100R2 D8 CH751H-40-U 2 C254 SCD1U10V2MX-1 1 C235 SCD1U16V 2 1 1 C440 SCD1U10V2MX-1Layout Note: Place near U7 1D5V_ICH_S5 3D3V_S5 5V_S5 1 1 1D5V_S0 C391 SCD1U16V 2 V2D5S_PCI_IDE 2 1 12 V5REF_S5 Intel 10 ohm 2 2 D28 CH751H-40-U C406 SCD1U10V2MX-1 Place both within 100 mils of ICH near D27 2 C407 SCD1U10V2MX-1 R480 10R2 1 C418 SCD1U10V2MX-1 1 ICH_VCC1_5 C408 SC1U10V3ZY 2 2D5V_S0 F21 A25 A24 1 3D3V_S5 Place within 100 mils of ICH C217 SCD01U16V3KX ICH6_VCCLAN1D5V 2 AB3 ICH6_VCCLAN1D5V G11 G10 RTC_AUX_S5 Place within 100 mils of ICH pin G10 AG23 AD26 AB22 VCCP_GMCH_S0 G16 G15 F16 F15 E16 D16 C16 1D5V_S0 Place within 100 mils of ICH C218 SCD1U10V2MX-1 1 V5REF_SUS VCCUSBPLL VCCSUS3_3 V5REF_S0 V5REF_S5 2 AA18 A8 1D5V_ICH_S0 C427 GAP-CLOSE-PWR SCD1U10V2MX-1 Layout Note: Place near AB18 C410 SCD1U10V2MX-1 C453 SCD1U10V2MX-1 1 V5REF V5REF 2 DY 2 VCC2_5 VCC2_5 1 Layout Note: Place near AB3 C454 SCD1U10V2MX-1 Layout Note: Place near AG23 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 2 1 C419 C415 SCD1U10V2MX-1 SCD1U10V2MX-1 NO_STUFF NO_STUFF 2 C416 SCD1U10V2MX-1 C441 SCD1U10V2MX-1 1 1 ICH6M B C234 SC1U10V3ZY 2 2 C437 SCD1U10V2MX-1 Intel 10 ohm 2 V5REF_S0 1 1D5V_ICH_S5 3 2 2 C253 SCD1U10V2MX-1 2 C435 SCD1U10V2MX-1 3D3V_S0 3D3V_S0 1 1 Layout Note: Distribute in PCI section near pin A2-A6 near D1-H1 1 2 5V_S0 C226 SCD1U10V2MX-1 Title C223 SCD1U10V2MX-1 Place within 100 pin mils A17of ICH ICH6-M (3 of 4) Size A3 Document Number Rev C D -1 Leopard 3 Date: Monday, August 15, 2005 A VCCP_GMCH_S0 *Within a given well, 5VREF needs to be up before the corresponding 3.3V rail 3D3V_S5 Place within 100 mils of ICH pin V7 2D5V_S0 VCCP_GMCH_S0 G65 AB18 P7 VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCRTC VCCLAN3_3/VCCSUS3_3 VCCLAN3_3/VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 VCCSUS3_3 VCCSUS3_3 V_CPU_IO VCCSUS3_3 V_CPU_IO VCCSUS3_3 V_CPU_IO VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 1 1 1 G8 2 VCC1_5_A 4,5,6,7,9,10,16,36,40,41 ALL NO_STUFF Caps do not have layout requirements but if layout allows then place next to ICH6 3D3V_S0 2 CORE IDE G20 F20 E24 E23 E22 E21 E20 D27 D26 D25 D24 1D5V_S5 DY 1 A17 B17 C17 F18 G17 G18 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A DY 2 A11 U4 V1 V7 W2 Y7 VCCSUS1_5 G19 C224 SCD1U10V2MX-1 DY 1 2 C456 SCD1U10V2MX-1 DY 3D3V_S0 Place within 100 mils of ICH pin A13 3D3V_S5 VCCSATAPLL VCC3_3 A13 F14 G13 G14 Intel dummy 1 AE1 AG10 U7 R7 Place within 100 mils of ICH pin AG13, AG16 DY 2 2 C236 SCD1U10V2MX-1 VCCDMIPLL VCC3_3 2 GAP-CLOSE-PWR Place within 100 mils of ICH pin AE1 AC27 E26 VCCSUS1_5 VCCSUS1_5 DY 1 1 1 C426 SCD1U10V2MX-1 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A P1 M7 L7 L4 J7 H7 H1 E4 B1 A6 DY 2 1 1 1D5V_ICH_S0 G37 1 Place within 100 mils of ICH pin AG10 1 1D5V_S0 ICH6_VCCLAN3D3V 3D3V_S0 DY 2 2 Place within 100 mils of ICH near E26, E27 DY C211 SCD01U16V3KX 2 1 C210 SC10U10V5ZY-L 3D3V_S0 2 GAP-CLOSE-PWR 1 Place within 100 mils of ICH DY 2 AA7 AA8 AA9 AB8 AC8 AD8 AE8 AE9 AF9 AG9 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 1D5V_S0 1D5V_S5 4 2 G32 1 NO_STUFF NO_STUFF C238 C443 SCD1U10V2MX-1 SCD1U10V2MX-1 2 C444 SCD1U10V2MX-1 1D5V_GPLL_ICH_S0 1D5V_S0 2 2 1 1D5V_S0 Place within 100 mils of ICH near pin AG9 AA10 AG19 AG16 AG13 AD17 AC15 AA17 AA15 AA14 AA12 5V_S0 1D5V_S0 C438 C439 C422 C421 C436 C239 SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1 SCD1U10V2MX-1SCD1U10V2MX-1 1 DY VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 3D3V_S5 5V_S0 7,9,15,40 2D5V_S0 2 2 DY VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A F9 U17 U16 U14 U12 U11 T17 T11 P17 P11 M17 M11 L17 L16 L14 L12 L11 AA21 AA20 AA19 1 DY AA6 AB4 AB5 AB6 AC4 AD4 AE4 AE5 AF5 AG5 VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A VCC1_5_A 2 1 1 NO_STUFF NO_STUFF C445 C237 SCD1U10V2MX-1 SCD1U10V2MX-1 2 C442 SCD1U10V2MX-1 2 Place within 100 mils of ICH near pin AG5 1 1D5V_S0 PCI C225 SC10U10V5ZY-L 2 3 USB 1 Layout Note: PCI decoupling 3D3V_S0 USB CORE 2 C252 SC10U10V5ZY-L PCI/IDE REF 1 Layout Note: IDE decoupling 3D3V_S0 PCIE 2 SCD1U10V2MX-1 SATA 1 1 C209 C409 C424 SCD1U10V2MX-1SCD1U10V2MX-1 2 TC9 ST220U10V-U 2 DY 2 4 1 1 Place near pin AA19 VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B VCC1_5_B 3D3V_S0 3D3V_S5 1 1 2 2 2 5,7,9,17,21,38,39,41 Layout Note: 1D5V_S0 AA22 AA23 AA24 AA25 AB25 AB26 AB27 F25 F26 F27 G22 G23 G24 G25 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N21 N22 N23 N24 N25 P21 P25 P26 P27 R21 R22 T21 T22 U21 U22 V21 V22 W21 W22 Y21 Y22 3D3V_S0 13,14,19,20,21,23,24,27,28,29,32,36,39,40,41 C417 C420 C423 C428 C425 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 2 U35E 1 1 1 17,19,21,25,29,31,35,37,39,40 Sheet E 18 of 41 A B C D E 3D3V_S0 U35D 3D3V_S0 3D3V_S5 17,18,21,25,29,31,35,37,39,40 3D3V_S5 5V_S0 13,14,18,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0 4 3 5V_S0 U61A 14 PLT_RST# 1 RSTDRV#_R 3 2 1 R511 2 33R2 RSTDRV#_5 21 7 TSAHCT32 PCIRST# 3V to 5V level shift for HDD & CDROM 2 SMBUS(ICH6 ---> SODIMM,CLKGEN) 3D3V_S0 14 3D3V_S0 U37B 4 6 17 PLT_RST#_R 5 PLT_RST# 1 2 7 3D3V_S0 TSLCX08-U RN31 SRN4D7KJ 3D3V_S5 1 R187 2 33R2 PLT_RST1# 7,21 ICH6 asserts PLTRST# to reset devices on the platform. E27 Y6 Y27 Y26 Y23 W7 W25 W24 W23 W1 V4 V27 V26 V23 U25 U24 U23 U15 U13 T7 T27 T26 T23 T16 T15 T14 T13 T12 T1 R4 R25 R24 R23 R17 R16 R15 R14 R13 R12 R11 P22 P16 P15 P14 P13 P12 N7 N17 N16 N15 N14 N13 N12 N11 N1 M4 M27 M26 M23 M16 M15 M14 M13 M12 L25 L24 L23 L15 L13 K7 K27 K26 K23 K1 J4 J25 J24 J23 H27 H26 H23 G9 G7 G21 G12 G1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3,5,7,9,11,13,14,16,17,18,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS F4 F22 F19 F17 E25 E19 E18 E15 E14 D7 D22 D20 D18 D14 D13 D10 D1 C4 C22 C20 C18 C14 B25 B24 B23 B21 B19 B15 B13 AG7 AG3 AG22 AG20 AG17 AG14 AG12 AG1 AF7 AF3 AF26 AF12 AF10 AF1 AE7 AE6 AE25 AE21 AE2 AE12 AE11 AE10 AD6 AD24 AD2 AD18 AD15 AD10 AD1 AC6 AC3 AC26 AC24 AC23 AC22 AC12 AC10 AB9 AB7 AB2 AB19 AB10 AB1 AA4 AA16 AA13 AA11 A9 A7 A4 A26 A23 A21 A19 A15 A12 A1 4 3 2 ICH6M 8 SMBD_ICH 3,11 10 6 1 TSLCX08-U PCIRST1# 22,23,25,29,31 1 Secondary PCI Bus reset signal. Wistron Corporation l.c ai SMB_CLK SMBC_ICH 3,11 tm 17,21 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCIRST# Buffer to enhance the driving strength ICH6-M (4 of 4) 2N7002DW Size A3 17,21 SMB_DATA Document Number Leopard 3 Date: Monday, August 15, 2005 A B C ho 2 2 33R2 D Sheet E f@ 3 5 ICH_PCIRST#_R 1 R188 4 3 4 7 17 ICH_PCIRST# Rev of 41 in U32 -1 xa RN32 SRN10KJ 1 U37C 9 om SMB_ICH_CTL he 1 2 14 4 3 3D3V_S0 19 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 3D3V_S5 17,18,19,21,25,29,31,35,37,39,40 5V_S0 Close to G768D 5V_G768_S0 16,31,32,34,35,36,37 3D3V_AUX 5V_S0 5V_G768_S0 4 2 5V_S0 5V_S5 1 BC7 SCD1U16V 2 EC12 SC1000P50V 2 1 GAP-CLOSE-PWR 1 13,14,18,19,21,23,24,27,28,29,32,36,39,40,41 2 1 3D3V_AUX Reserve for G768B works at High Speed G8 4 3D3V_S5 U6 BC5 SC10U10V6ZY-U VCC_FAN 1 2 3 4 5 6 7 8 DY 4 4 THERMDP1 THERMDN 1 RUNPWROK 1 R31 THERMDP2 2 G768_RST# 4K7R2 R32 10KR2 FANVCC VCC DXP1 DXN DXP2 RESET# GND AGND TH_SHUT VCC SMBCLK NC SMBDATA ALERT# FG CLK 14,18,36,38 5V_S5 16 15 14 13 12 11 10 9 SMBC_G768D SMBD_G768D PM_THRM# 17 FAN_FB CLK32_G768 31 2 G768D R47:5K SET TO 120°C Must close to MAX6509 1 U65 Put these two Caps near the thermal diode. 1 2 3 3,36 CLK_PWRGD# VCC 5 Y 4 3D3V_AUX VRM_PWRGD SET GND OUT# VCC 5 HYST 4 5V_S5 C30 SCD1U25V3KX 3 MAX6509HAUK-T-U 2 3 NC A GND R19 22KR3F M6509_SET 1 2 3 1 U4 3D3V_S0 2 SD 0817 THERMDP1 1 D3 BAT54-1 R47 10KR2 36 SYSTEM SENSOR 0R0402-PAD 1 R532 2 VGATE PWROK 0R0402-PAD 1 R533 2 2 VRM_PWRGD 17 BC6 SCD1U16V 31 S5_ENABLE 1 A 2 B 3 GND DY VCC 5 Y 4 1999_S5ENABLE 37,38 NC7S08-U 2 1 2 BC8 SC2K2P THERMDN BC4 SC2K2P THERMDN 3D3V_S0 14 THERMDP1/DP2/THERMDN ON THE SAME LAYER W/S = 10/5 MIL, 12 MIL AWAY FROM OTHERS CAPS CLOSE TO G768B 2 3D3V_AUX U13 7 THERMDP2 1 THERMDP1 RSMRST# 16,31,39 DY 2 DY 1 BC1 SC470P50V3JN 1 S2N3904-U3 Put under CPU Socket 3 DY 2 2 DY THERMDN 2 Q5 1 BC9 SC470P50V3JN NC7S14-U 1 3 1 THERMDP2 2 SD 0817 RUNPWROK U37D 2 12 11 VCCP_PWGD 7 38 13 ICH6_PWROK 17 TSLCX08-U 180 ms after VCC_G768 > 4.38v, p2, 7 5V_S0 1 2 1 5V_S0 R435 10KR2 RN1 SRN10KJ 4 3 2 2 BC66 SCD1U16V SMBD_G768D BC67 SCD1U16V 31 SMBD_KBC 1 1 1 BC65 SC10U10V6ZY-U 2 D26 S1N4148-U2 ETY-CON3-S1 1 1 VCC_FAN 1 1 4 FAN_FB 3 5 3 2 2 FAN1 Wistron Corporation SMBC_G768D 31 The symbol use 2nd source The P/N is the main source Main source:20.D0152.103 2nd source:20.D0012.103 SMBC_KBC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title G768D Size A3 Document Number Date: Monday, August 15, 2005 A B C D Rev -1 Leopard 3 Sheet E 20 of 41 A B C D E 3,5,7,9,11,13,14,16,17,18,19,20,22,23,24,25,27,29,30,31,32,36,38,40,41 HDD Connector 13,14,18,19,20,23,24,27,28,29,32,36,39,40,41 HDD1 IDE_A1 16 IDE_A0 16 IDE_CS#0 16 5V_S0 IDE_IORDY 16 IDE_DACK# 16 IDE_IRQ14 16 HDD_LED# R423 10KR2 HDD_LED# 14 IDE_DACK# BAY_ID0 DIAG IDE_A2 IDE_CS#1 TPAD30 TP35 R422 2K7R2J SPD-CONN44D-3-U1 20.F0362.044 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 IDE_DREQ IDE_IOR# 5V_S0 4 CD_AUDL 27 2 1 DY CD_AGND 27 RSTDRV#_5 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 IDE_IOW# IDE_IORDY IDE_IRQ14 IDE_A1 IDE_A0 IDE_CS#0 5V_S0 CDROM_LED# 14 R230 10KR2 5V_S0 CSEL CDROM_CSEL R196 DUMMY-R2 SYN-CONN50-4R3GP 1 1 C258 SCD1U16V 2 D25 SSM24L-U C353 SC10U10V5ZY-L 2 C354 SCD1U16V 3 2 1 5V_S0 2 1 2 DY 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 MH2 52 2 R401 4K7R2 0R0402-PAD 2 51 MH1 1 1 1 R424 2 CD_AUDR 2 PBIDDACK# 1D5V_S0 1 R421 4K7R2 DY IDE_DREQ 16 IDE_IOW# 16 IDE_IOR# 16 5V_S0 1D5V_S0 1 27 R425 4K7R2 5,7,9,17,18,38,39,41 3D3V_LAN_S5 5V_S0 BC38 SC10U10V6ZY-U 3 DY PIN 49,50 DON'T USE 2 5V_S0 3D3V_S0 1 DIAG 2 R400 470R2 16 IDE_A2 16 IDE_CS#1 3D3V_S0 CN16 5V_S0 3D3V_S0 1 1 HDDCSEL1 IDE_D7 IDE_D6 IDE_D5 IDE_D4 IDE_D3 IDE_D2 IDE_D1 IDE_D0 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 46 48 2 4 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 CDROM RSTDRV#_5 19 1 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 PBRSTDRV1#_5 1 2 2 47 45 1 2 16 IDE_D[15..0] 3D3V_S0 25,41 3D3V_LAN_S5 The symbol use 2nd source The P/N is the main source Main source:20.10150.050 2nd source:20.B0040.050 1013 -1 3D3V_S0 NEWCARD Connector IDE_IRQ14 SKT3 Place them Near to Chip 3D3V_S5 1 2 3 4 1 R229 2 8K2R2 Place them Near to Connector 1D5V_S0 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5 1 C220 SCD1U16V 2 C221 SC10U10V5ZY-L 2 1 1 C231 SCD1U16V 2 1 C232 SC10U10V5ZY-L 2 C216 SCD1U16V DY 2 2 1 1 2 C215 SCD1U16V 2 1 CARD-SKT21-U2 For Newcard socket C219 SCD1U16V DY 2 CN14 7 8 3.3VOUT 3.3VOUT TP26 3D3V_S5 NEWCARD_OC# PERST# 3D3V_NEW_LAN_S5 23 21 9 20 OC# 3.3VAUX_IN PERST# AUX_OUT NC#1 NC#10 NC#12 NC#13 NC#24 1 10 12 13 24 GND GND 11 25 3 CLK_PCIE_NEW 3 CLK_PCIE_NEW# 17 CPPE# PM_SLP_S3# 17,28,31,37,38,40 3D3V_S0 PM_SLP_S4# 17,31,37,38 2 PLT_RST1# 0R2-0 2N7002-F-GP TPAD30 TP65 R569 10KR2 Q30 PERST# 3D3V_NEW_LAN_S5 17 PCIE_WAKE# G 3 TPAD30 TP66 TPAD30 TP61 SD 0817 3D3V_S5 TPS2231 U68 7,19 PLT_RST1# 17 NEWCARD_RST# 1 A 2 B 3 GND VCC 5 Y 4 CONN_WAKE# 1D5V_NEW_S0 CONN_CLKREQ# 17,19 SMB_DATA 17,19 SMB_CLK PREQ2# CONN_CLKREQ# 3D3V_NEW_S0 17 17 USB_PP6 USB_PN6 SMB_DATA_C SMB_CLK_C CONN_TP2 CONN_TP3 CPUSB# SMBUS(ICH6--NEWCARD,LAN) 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title 1 TPS2231_RST# HDD / CDROM/NEWCARD JAE-CON26-U Size A3 NC7SZ08-U DY A B Document Number Leopard 3 Date: Tuesday, July 12, 2005 C om 3.3VIN 3.3VIN 3D3V_NEW_S0 1 R183 PCIE_RXP0_R PCIE_RXN0_R PCIE_RXP0 PCIE_RXN0 l.c 3D3V_S0 5 6 TPS2231_RST# 1 1.5VOUT 1.5VOUT CPUSB# CPPE# 2 17 16 14 15 4 3 2 22 S 1D5V_NEW_S0 CPUTSB# CPPE# STBY# SHDN# SYSRST# RCLKEN ai 1 1.5VIN 1.5VIN D TP-2 19 18 tm 17 17 SRN100KJ 1D5V_S0 ho CPPE# CPUSB# 3 4 D f@ U34 26 25 24 MH2 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 MH1 3 2 Rev of 41 in RN30 2 1 PCIE_TXP0 PCIE_TXN0 -1 xa 17 17 Sheet E he 3D3V_S5 21 A B U39A VCCP VCCP U1-1 3D3V_PLL_S0 * All 1394 signals must be routed on top side only * Differential pairs of each ports should have equal trace length * Stubs must be keep as short as possible U15 1394_TPBIAS0 26 TPA0P TPA0N V15 W15 1394_TPA0P 26 1394_TPA0N 26 TPB0P TPB0N V14 W14 AGND AGND AGND 2 R232 4K7R2 2 R231 4K7R2 1 E1 E2 B_USB_EN# A_USB_EN# M2 M3 SDA SCL 2 1 C229 SC1000P50V W17 T19 P12 3D3V_S0 TPAD30 TP85 PCI7421_TP1 TPAD30 TP84 TPAD30 TP86 PCI7421_TP2 PCI7421_TP3 TPAD30 TP37 PCI7421_TP5 L5 L2 K5 K3 K7 L1 L3 NC#W17 RSVD TEST0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD C227 SC1U10V3KX 1 C259 2 SC15P U17 TPA1P TPA1N V18 W18 TPB1P TPB1N V16 W16 1394_TPBIAS1 3D3V_S0 1394_TPBIAS1 26 1394_TPB1P 1394_TPB1N 1394_TPB1P 1394_TPB1N E3 F5 F6 G5 F3 U1-5 MS_DATA3/SD_DAT3/SM_D3 MS_DATA2/SD_DAT2/SM_D2 MS_DATA1/SD_DAT1/SM_D1 U1-6 R184 10KR2 1394_TPB1P 26 1394_TPB1N 26 MC_PWR_CTRL# MC_PWR_CTRL# MC_PWR_CTRL-1 TP36 TPAD30 2 SD MS/MS_pro SD_CD# MS_CD# SM_CD# MS_CLK MS_BS 24 24 24 24 24 H5 G3 G2 MS_D3 MS_D2 MS_D1 24 24 24 MS_SDIO(DATA0)/SD_DAT0/SM_D0 SD_CLK/SM_RE# SD_CMD/SM_ALE G1 J5 J3 SD_DAT0/SM_D4 SD_DAT1/SM_D5 SD_DAT2/SM_D6 SD_DAT3/SM_D7 H3 J6 J1 J2 3 MS_SDIO 24 SM_CD# 2 SM_RE# 24 SM_ALE 3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41 BAW56-1 SM_D4 24 SM SM_D5 24 SM_D6 24 SM_D7 24 SD_WP/SM_CE SM_CLE SM_R/B# SM_PHYS_WP# H7 J7 K1 K2 1 R570 2 0R2-0 3D3V_S0 1 SD_CD# MS_CD# SM_CD# MS_CLK/SD_CLK/SM_EL_WP# MS_BS/SD_CMD/SM_WE# 1 C240 SCD1U16V 2 1394_TPA1P 26 1394_TPA1N 26 U36 3D3V_S0 2N7002DW U1-9 SD_WP SM_CLE SM_R/B# MS/MS_pro D9 XD SD_CD# R180 100KR2 R182 10KR2 1 2 R236 150R2 2 1 C228 SC10U10V5ZY-L N12 U14 U16 F1 F2 U1-10 2 GAP-CLOSE-PWR 1 2 SC12P 2 1 C243 1 B_USB_EN A_USB_EN 3D3V_PLL_S0 G34 6 R233 10KR2 2 2 10KR2 1 1 R234 2 3D3V_S0 2 1 3D3V_S0 UNUSED TERMINALS 2 1 3 3D3V_S0 X2 X-24D576M-2 U13 V13 MC_PWR_CTRL_0 MC_PWR_CTRL_1 U1-8 DATA CLOCK LATCH SPKROUT DY 1 1394_XO 1394_XI R12 PC[2:0]=000 TPBIAS1 SUSPEND# SD/SDIO 2 CS_SUSPEND# R2 10KR2 N1 L6 N2 L7 1 R211 CB_DATA CB_CLOCK CB_LATCH PCI_SPKR C261 SCD1U16V DY 2 PC0(TEST1) PC1(TEST2) PC2(TEST3) C260 SCD1U16V 1394_TPB0P 26 1394_TPB0N 26 1 R17 1394_PHYTEST M11 1394_CPS 1 P15 1394_CNA R19 R18 C271 SCD1U16V 1 XO XI C269 SC1000P50V 2 PHY_TEST_MA CPS CNA 3D3V_S0 1 TPBIAS0 C249 SCD1U16V DY 2 2 6K34R3F C248 SCD1U16V 1 1 R198 C247 SCD1U16V DY 2 U18 1394_R0 U19 1394_R1 C270 SC1000P50V 2 C242 SCD1U16V 1 2 VDPLL_15 1 VDPLL_15 VSSPLL T18 T17 2 V19 VDPLL_33 P14 1 VDPLL_33 VSSPLL R0 R1 PAR FRAME# TRDY# IRDY# STOP# DEVSEL# IDSEL PERR# SERR# REQ# GNT# PCLK PRST# GRST# RI_OUT#/PME# 3D3V_S0 2 AVDD AVDD AVDD U1-7 R13 R14 V17 3D3V_S0 23 23 23 27 4 PCI7421 as possible 2 7421_PME# Should be places as close to 3 5 TPAD30 TP82 2CS_IDSEL 100R2 Bypass/Decupoling Capacitors 7421_LED 14 PM_CLKRUN# 17,25,29,31 4 1 R210 17,25,29 PCI_PERR# 17,25,29 PCI_SERR# 17 PCI_REQ#1 17 PCI_GNT#1 3 PCLK_PCM 19,23,25,29,31 PCIRST1# P9 V7 R8 U7 W8 N8 W5 V8 U8 U1 T2 P5 R3 T1 T3 3D3V_S0 MC_PWR_CTRL 24 1 17,25,29 PCI_PAR 17,25,29 PCI_FRAME# 17,25,29 PCI_TRDY# 17,25,29 PCI_IRDY# 17,25,29 PCI_STOP# 17,25,29 PCI_DEVSEL# PCI_AD22 INT_PIRQG# CB_MFUNC5 CLK48_CARDBUS 3D3V_S0 INT_PIRQF# 17 PCI_SERIRQ 17,29,31 1 C/BE0# C/BE1# C/BE2# C/BE3# INT_PIRQG# 17 2 0R2-0 3 PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3 M1 1 R237 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,23,24,25,27,29,30,31,32,36,38,40,41 1 17,25,29 17,25,29 17,25,29 17,25,29 CLK_48 PCM_INTB# E 2 W11 W9 W7 W4 3 N3 M5 P1 P2 P3 N5 R1 2 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 1394 4 U2 V1 V2 U3 W2 V3 U4 V4 V5 U5 R6 P6 W6 V6 U6 R7 V9 U9 R9 N9 V10 U10 R10 N10 V11 U11 R11 W12 V12 U12 N11 W13 CARD BUS PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 2 W3 W10 1 of 4 13,17,25,29 PCI_AD[31..0] D CARBUS 1 NONE 1394 CARD READER 1 3D3V_S0 C INTA# INTB# INTC# INTD# 7421_LED 24 24 3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41 PCI7411 1 1 Wistron Corporation 7411:71.07411.00U 7421:71.07421.00U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title TI SNC1Q21 (1 of 2) Size A3 Document Number Rev A B C D -1 Leopard 3 Date: Monday, August 15, 2005 Sheet E 22 of 41 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 5V_S0 13,14,18,19,20,21,24,27,28,29,32,36,39,40,41 G10 CBB_A13 24 C8 A8 B8 A9 C9 E10 CBB_A23 CBB_A22 CBB_A15 CBB_A20 CBB_A21 CBB_A19 A_CPERR#/A_A14 A_CSERR#/A_WAIT# F10 B3 CBB_A14 24 CBB_WAIT# 24 A_CREQ#/A_INPACK# A_CGNT#/A_WE# E7 B9 CBB_INPACK# 24 CBB_WE# 24 A_CSTSCHG/A_BVD1(STSCHG#/RI#) A_CCLKRUN#/A_WP(IOIS16#) A_CCLK/A_A16 B2 C3 E9 CBB_BVD1# 24 CBB_WP 24 CBB_A16 24 A_CINT#/A_READY(IREQ#) A_CRST#/A_RESET C4 A6 CBB_RDY 24 CBB_RESET 24 A_CAUDIO/A_BVD2(SPKR#) A2 CBB_BVD2# 24 A_CCD1#/A_CD1# A_CCD2#/A_CD2# A_CVS1/A_VS1# A_CVS2/A_VS2# C15 E5 A3 E8 CBB_CD1# CBB_CD2# CBB_VS1# CBB_VS2# A_RSVD/A_D14 A_RSVD/A_D2 A_RSVD/A_A18 B13 D2 C10 CBB_D14 24 CBB_D2 24 CBB_A18 24 2 24 24 24 24 24 24 24 24 24 24 E18 J15 RSVD RSVD RSVD F14 A18 H18 RSVD RSVD RSVD B19 F17 C17 RSVD RSVD RSVD RSVD N13 B17 C18 F19 RSVD RSVD RSVD N17 A15 K15 2 2 1 1 1 VCC_ASKT_S0 U60 DY CB_DATA 5V_S0 22 22 CB_CLOCK 22 CB_LATCH 19,22,25,29,31 PCIRST1# 1 2 10KR2 R498 3D3V_S0 PS_SHDN# 3 4 5 12 21 13 C452 SCD1U16V DATA CLOCK LATCH RESET# SHDN# 3.3V AVCC AVCC 9 10 AVPP 8 OC# 15 NC NC NC NC NC NC NC NC NC 24 23 22 19 18 17 16 14 6 VPP_ASKT_S0 3 5V_S0 C434 SC4D7U10V5ZY DY RSVD RSVD C433 SC4D7U10V5ZY 2 J18 B18 1 RSVD RSVD 2 G19 H17 J13 J17 H19 J19 C449 SCD1U16V C451 SC100P50V2JN-U 1 2 5V 5V 7 20 12V 12V 11 25 GND GND 1 RSVD RSVD RSVD RSVD RSVD RSVD R497 100KR2 C450 SCD1U16V 2 C447 SCD1U16V 2 K13 VCC_ASKT_S0 PCIRST1# 1 RSVD VPP_ASKT_S0 C446 SC1U10V3ZY TSP2220A 3D3V_S0 U39D 4 PCI7411 PCI7411 H8 H9 H10 H11 H12 J8 M7 J12 M9 M10 M12 K8 K12 N7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC G7 G8 G13 H13 J9 J10 J11 K9 K10 K11 L8 L9 L10 L11 L12 M8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND of 4 VR_PORT VR_PORT VR_EN# M19 PT_PORT H1 VR_PORT 2 H2 C263 SCD1U16V 1 A_CPAR/A_A13 A_CFRAME#/A_A23 A_CTRDY#/A_A22 A_CIRDY#/A_A15 A_CSTOP#/A_A20 A_CDEVSEL#/A_A21 A_CBLOCK#/A_A19 F15 G18 K14 M18 4 C262 SCD1U16V 2 CBB_REG# 24 CBB_A12 24 CBB_A8 24 CBB_CE1# 24 RSVD RSVD RSVD RSVD Power switch 1 C5 F9 B10 G12 U1-3 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD B15 A16 B16 A17 C16 D17 C19 D18 E17 E19 G15 F18 H14 H15 G17 K17 L13 K18 L15 L17 L18 L19 M17 M14 M15 N19 N18 N15 M13 P18 P17 P19 2 A_CC/BE3#/A_REG# A_CC/BE2#/A_A12 A_CC/BE1#/A_A8 A_CC/BE0#/A_CE1# CBB_D10 24 CBB_D9 24 CBB_D1 24 CBB_D8 24 CBB_D0 24 CBB_A0 24 CBB_A1 24 CBB_A2 24 CBB_A3 24 CBB_A4 24 CBB_A5 24 CBB_A6 24 CBB_A25 24 CBB_A7 24 CBB_A24 24 CBB_A17 24 CBB_IOWR# 24 CBB_A9 24 CBB_IORD# 24 CBB_A11 24 CBB_OE# 24 CBB_CE2# 24 CBB_A10 24 CBB_D15 24 CBB_D7 24 CBB_D13 24 CBB_D6 24 CBB_D12 24 CBB_D5 24 CBB_D11 24 CBB_D4 24 CBB_D3 24 D19 K19 1 D1 C1 D3 C2 B1 B4 A4 E6 B5 C6 B6 G9 C7 B7 A7 A10 E11 G11 C11 B11 C12 B12 A12 E12 C13 F12 A13 C14 E13 A14 B14 E14 RSVD RSVD POWER TERMINALS CARDBUS A 3 A_CAD31/A_D10 A_CAD30/A_D9 A_CAD29/A_D1 A_CAD28/A_D8 A_CAD27/A_D0 A_CAD26/A_A0 A_CAD25/A_A1 A_CAD24/A_A2 A_CAD23/A_A3 A_CAD22/A_A4 A_CAD21/A_A5 A_CAD20/A_A6 A_CAD19/A_A25 A_CAD18/A_A7 A_CAD17/A_A24 A_CAD16/A_A17 A_CAD15/A_IOWR# A_CAD14/A_A9 A_CAD13/A_IORD# A_CAD12/A_A11 A_CAD11/A_OE# A_CAD10/A_CE2# A_CAD9/A_A10 A_CAD8/A_D15 A_CAD7/A_D7 A_CAD6/A_D13 A_CAD5/A_D6 A_CAD4/A_D12 A_CAD3/A_D5 A_CAD2/A_D11 A_CAD1/A_D4 A_CAD0/A_D3 CARDBUS B U1-2 A5 A11 of 4 2 4 VCCA VCCA 3 1 U39C C448 2 SCD01U16V3KX 1 1 2 of 4 2 VCC_ASKT_S0 2 U39B 5V_S0 U1-4 1 1 PCI7411 tm ai l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. A B C D Sheet E Rev of 41 -1 xa Leopard 3 he Date: Tuesday, July 12, 2005 in Document Number f@ TI PCI7411 GHK (2 of 2) Size A3 ho Title 23 A B C D E 3D3V_S0 Cardbus I/F PCMCIA Socket CBB_WAIT# CBB_A3 CBB_INPACK# CBB_REG# CBB_A1 Place close to pin 19. CBB_BVD2# C233 DUMMY-C2 2 CBB_A0 CBB_BVD1# CBB_D0 CBB_D8 CBB_D1 CBB_D9 CBB_D2 CBB_D10 2 DY MS_BS_1 MS_CD# MS_CLK_R 1 R449 RSV#4 XD-CD 4 39 SD-CD-COM SD-CD-SW SD-WP-SW SD-CLK SD-CMD 41 42 5 8 10 S.M#/XD-CLE S.M#/XD-ALE S.M#/XD-WE S.M#/XD-CE S.M#/XD-RE S.M#/XD-R/B S.M/XD-WP-IN 38 37 36 28 27 26 35 GND GND GND GND 46 45 44 1 1 1 2 2 2 1 1 1 22 22 22 22 C250 SCD01U16V3KX 3D3V_CR_S0 MS_SDIO MS_D1 MS_D2 MS_D3 3D3V_CR_S0 22 22 22 22 R562 22KR2J 22 SM_RE# 3D3V_CR_S0 SM_D4 SM_D5 SM_D6 SM_D7 MS_SDIO15 MS_D1 14 MS_D2 16 MS_D3 18 MS_D1 MS_D2 MS_D3 SM_D4 SM_D5 SM_D6 SM_D7 33 32 31 21 22 23 24 DY 25 2 30 0R2-0 34 R563 22KR2J SM_CD# SM_CD# MS_SDIO 1 R555 MS_BS SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 S.M/XD-D1 S.M/XD-D2 S.M/XD-D3 S.M/XD-D4 S.M/XD-D5 S.M/XD-D6 S.M/XD-D7 S.M-LVD S.M-CD# S.M-D0 MS_CD# 22 MS_CLK 22 2 MS_CLK 33R2 SM_CD# 3 SD_CD# SD_WP MS_CLK MS_BS 1 2 33R2 R584 SM_CLE SM_ALE MS_BS_1 1 2 22R2 SD_WP R564 SM_RE# SM_R/B# MS_CLK_R0 SD_CD# SD_WP 22 22 SM_CLE SM_ALE 22 22 SM_RE# SM_R/B# 22 22 MS_BS 2 MS_CLK_R 1 R440 22 330R2 SKT-MEMO-12-GP 3D3V_CR_S0 3D3V_S0 U30 R565 22KR2J DY 3D3V_CR_S0 R566 22KR2J DY SM_ALE 1 2 3 SM_CLE R589 4K7R2 OUT GND SET IN 5 ON# 4 2 3D3V_CR_S0 MC_PWR_CTRL AAT46101GV-1 C169 SCD1U16V R583 15KR2 C185 SC1U10V3ZY 3D3V_CR_S0 70 1 Clock AC termination 33MHz clock for 32-bit Cardbus card I/F CBB_WP CBB_CD2# 13 17 19 22 2 1 2 CBB_A2 MS-BS MS-INS MS-SCLK 1 DY 7 6 12 11 2 1 CBB_RESET CBB_A4 R186 DUMMY-R2 33R2 33R2 33R2 33R2 1 CBB_A5 2 2 2 2 1 CBB_A16 1 1 1 1 2 CBB_VS2# SM_CD# MS_CLK_R0 1 C430 SCD1U16V R576 R577 R578 R579 2 2 1 CBB_A16 CBB_A22 CBB_A15 CBB_A23 CBB_A12 CBB_A24 CBB_A7 CBB_A25 CBB_A6 2 3 43 CBB_RESET 1 CBB_A21 VPP_ASKT_S0 47K 2 CBB_RDY DY MS_SDIO MS_D1 MS_D2 MS_D3 1 CBB_A20 R212 DUMMY-R2 2 CBB_WE# 3 SM-CD-COM SM-CD-SW SM-WP-SW XD-VCC S.M-VCC MS-VCC SD-VCC 1 2 C431 SC1000P50V C429 SCD1U16V CBB_A8 CBB_A17 CBB_A13 CBB_A18 CBB_A14 CBB_A19 C370 SCD01U16V3KX C360 SCD01U16V3KX VCC_ASKT_S0 2 1 1 2 C432 SC22U10V6ZY-U 2 1 CBB_IOWR# C377 SCD01U16V3KX 40 29 20 9 1 CBB_IORD# CBB_A9 C359 SCD01U16V3KX SKT2 2 CBB_A11 1 CBB_CE2# CBB_OE# CBB_VS1# VCC_ASKT_S0 2 CBB_A10 6 in 1 Connector 3D3V_CR_S0 1 CBB_CE1# CBB_D15 4 CBB_CE1# 23 CBB_CE2# 23 CBB_BVD1# 23 CBB_BVD2# 23 CBB_CD1# 23 CBB_CD2# 23 CBB_VS1# 23 CBB_VS2# 23 2 CBB_CD1# CBB_D4 CBB_D11 CBB_D5 CBB_D12 CBB_D6 CBB_D13 CBB_D7 CBB_D14 DCBATOUT DCBATOUT 2 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 14,35,37,38,39,40,41 CBB_IORD# 23 CBB_IOWR# 23 CBB_OE# 23 CBB_WE# 23 CBB_REG# 23 CBB_RDY 23 CBB_WP 23 CBB_RESET 23 CBB_WAIT# 23 CBB_INPACK# 23 69 CBB_D3 3D3V_S0 CBB_D[0..15] 23 CBB_A[0..25] 23 CBUS1 4 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,25,27,29,30,31,32,36,38,40,41 R568 47KR2 R567 22KR2J 5V_S0 2 2 CARDBUS68P-9 62.10024.491 SD_WP SM_R/B# SKT1 1 2 3 4 U67 CARDBUS-SKT45-U1 1 MS_CLK 1 A MS_CLK_R 2 B 3 GND VCC 5 SE 4 DY SD_CD# 1 NC7SZ66P5X Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PCMCIA SLOT/ CARDBUS SKT Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 24 of 41 A B C D E 3D3V_LAN_S5 1 R111 PCI_C/BE#[0..3] 2 3K6R3 U29 R110 LAN_X2 1 1 2 3 4 2 CS SK DI DO VCC DC ORG GND 8 7 6 5 AVDD25 17,22,29 VDD25 13,17,22,29 C168 SCD1U16V 1 R100 C135 SCD1U16V M93C46-W-3 2 DUMMY-R2 X5 1 2 4 2 0R3-U 1 EECS_3 EESK EEDI EEDO 2 LAN_X1 PCI_AD[0..31] 1 Close to RTL8100C Pin121,Pin122 4 R108 5K6R3F 1 3D3V_LAN_S5 1 3D3V_LAN_S5 19,22,23,29,31 PCIRST1# 3 PCLK_LAN 17 PCI_GNT#2 17 PCI_REQ#2 13,17,29 ICH_PME# VDD25 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 3D3V_S0 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 1 1 2 2 2 2 C132 SCD1U16V 1 1 1 C142 C149 SCD1U16V SCD1U16V C152 SCD1U16V 2 C130 SC22U10V6ZY-U 2 VDD25 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 1 GAP-CLOSE-PWR 2 PCI_AD2 2 2 PCI_AD7 PCI_C/BE#0 3D3V_LAN_S5 1 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 L16 BLM11A601S AVDD33 PCI_AD13 PCI_AD14 PCI_PERR# PCI_STOP# PCI_DEVSEL# PCI_TRDY# C139 SCD1U16V C138 SCD1U16V PCI_PAR 17,22,29 PCI_SERR# 17,22,29 1 1 PCI_AD15 VDD25 PCI_C/BE#1 PCI_PAR PCI_SERR# 2 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 NC NC NC NC AVDDH VSSPST GND LED0 VDD18 LED1 LED2 LED3 GND EESK VDD18 EEDI EEDO VDD33 EECS LANWAKE PCIAD0 PCIAD1 NC GND NC XTAL1 XTAL2 VSS GND GND VSS 3 121 122 123 124 125 CTRL18 NC AVDD18 VSS RSET RTL8100CL-U PCIAD2 VSSPST GND VDD25 VDD18 PCIAD3 PCIAD4 PCIAD5 PCIAD6 VDD33 PCIAD7 CBEB0 GND VSSPST PCIAD8 PCIAD9 NC M66EN PCIAD10 PCIAD11 PCIAD12 VDD33 PCIAD13 PCIAD14 GND VSSPST GND PCIAD15 VDD25 VDD18 CBEB1 PAR SERRB SERR# NC NC GND NC VDD33 PERRB PERR# STOPB STOP# DEVSELBDEVSEL# TRDYB TRDY# GND VSSPST CLKRUNBCLKRUN# GND C136 SCD1U16V C134 SCD1U16V 2 17,29 INT_PIRQE# VDD25 2 2 ISOLATE 2 3 G30 1 1 AVDD33 CHP69 Q8 2LAN_PWR_CTRL 1 0R2-0 2 AVDD25 TX+ MDI0+ TXMDI0AVDD33 AVDDL GND VSS RX+ MDI1+ RXMDI1AVDD33 AVDDL CTRL25 NC VSS AVDDH NC HSDAC+ NC HSDAC- AVDD25 NC VSS NC MDI2+ NC MDI2NC AVDDL GND VSS NC MDI3+ NC MDI3AVDD33 AVDDL VSSPST GND NC GND ISOLATE# ISOLATEB NC VDD18 INTAB INTA# VDD33 PCIRST# PCIRSTB PCICLK GNTB GNT# REQB REQ# PMEB PME# VDD25 VDD18 PCIAD31 PCIAD30 GND PCIAD29 PCIAD28 VSSPST GND CTRL25 1 R103 1 AVDD33 CTRL25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PCIAD27 PCIAD26 VDD33 PCIAD25 PCIAD24 CBEB3 VDD18 NC IDSEL PCIAD23 NC GND PCIAD22 PCIAD21 GND VSSPST GND PCIAD20 VDD18 VDD25 PCIAD19 VDD33 PCIAD18 PCIAD17 PCIAD16 CBEB2 FRAME#FRAMEB NC GND IRDY# IRDYB VDD18 NC RX+ RX- 3D3V_LAN_S5 2 DY PCI_PERR# 17,22,29 PCI_STOP# 17,22,29 PCI_DEVSEL# 17,22,29 PCI_TRDY# 17,22,29 3D3V_S5 3D3V_LAN_S5 PM_CLKRUN# 17,22,29,31 G31 1 2 GAP-CLOSE-PWR 3D3V_S0 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 26 26 AVDD33 NC TX+ TX- GND 3 26 26 126 128 127 1 2 U28 C137 SCD1U16V 2 1 2 1 2 2 3D3V_LAN_S5 2 1 2 C140 SCD1U16V C148 C150 C141 C151 C153 C133 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V PCI_AD1 PCI_AD0 EECS_3 EEDO EEDI EESK R105 49D9R2F LAN_LED2 LAN_LED1 R104 49D9R2F LAN_LED0 R106 49D9R2F R107 49D9R2F LAN_X1 LAN_X2 Close to LAN chip C143 SCD1U16V 2 RX+ 2 RX- 2 TX- 1 TX+ 1 3D3V_LAN_S5 1 TP23 TPAD30 TP21 TP22 TPAD30 TPAD30 1 2 2 C144 SC12P50V2JN 1 1 2 C145 SC12P50V2JN 2 1 XTAL-25MHZ-43 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,27,29,30,31,32,36,38,40,41 3D3V_S0 1 3D3V_S5 3D3V_LAN_S5 41 3D3V_LAN_S5 1 2 l.c 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Size A3 tm Document Number Leopard 3 Date: Wednesday, July 13, 2005 A B C D f@ LAN RTL8100C PCI_FRAME# 17,22,29 Rev of 41 in PCI_AD23 ho Title 17,22,29 1 PCI_IRDY# -1 xa 1 2 ai R109 100R2 DY om Wistron Corporation 3D3V_LAN_S5 R101 15KR2 3D3V_S5 Sheet E he 2 PCI_C/BE#2 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 VDD25 PCI_AD20 PCI_AD21 PCI_AD22 ISOLATE PCI_AD23 LAN_IDSEL 1 PCI_C/BE#3 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 R102 1KR2 17,18,19,21,29,31,35,37,39,40 25 A B 29 29 BT_PRIOR WLAN_ACT D E 3D3V_LAN_S5 Place on bottom side Blue thumb R556 100R2 1 2 1 2 13 R557 13 100R2 13,14 17 17 C 1394 Connector 25,41 3D3V_LAN_S5 CN4 10 8 7 6 5 4 3 2 BC0EX2 BC0EX1 BT_LED USB_PN2 USB_PP2 4 1 9 3D3V_BT_S0 22 1394_TPA0P 0R0402-PAD 1 R98 2 TPA0+ 22 1394_TPA0N 0R0402-PAD 1 R96 2 TPA0- 22 1394_TPB0P 0R0402-PAD 1 R97 2 22 1394_TPB0N 0R0402-PAD 1 R99 2 1394_1 2 1 4 1 5 4 2 1 SKT-1394-4P-6-U1 R207 56R2F R208 56R2F 1394_TPB0_T 3D3V_BT_S0 2 22 1394_TPB1P 0R0402-PAD 1 R62 2 22 1394_TPB1N 0R0402-PAD 1 R42 2 1 R369 11KR3F 0R0402-PAD 1 R45 2 2 C85 SCD1U16V 22 1394_TPA1N R200 56R2F 2 1 2 R390 10KR2 2 R201 56R2F 1 5V_S3 C321 SC4D7U10V5ZY 78.47593.411 2 G913C-U 0R0402-PAD 1 R66 2 3 1394_TPB1N_PR 13 R203 56R2F R202 56R2F 1394_TPB1_T 2 C244 SC220P R204 5K1R2 2 G BT_EN S 17 C241 SC1U10V3KX RJ45 PIN 2 10/100 LAN Transformer QB4 2N7002-F-GP 2 BT_EN# D 2 1 22 1394_TPBIAS1 1394_TPA1P_PR 13 1394_TPA1N_PR 13 1394_TPB1P_PR 13 1 2 Close to CN20 22 1394_TPA1P 2 4 1 OUT 2 1 2 2 1 1 2 EC110 SCD1U DY 1 SET DY 1 SHDN# GND IN 3D3V_BT_SET 5 1 1 2 3 2 BT_EN# 2 78.20034.1B1 3 DY R209 5K1R2 C246 SC220P 1 U55 DY R370 18KR3F 2 I max = 150 mA EC18 EC17 EC16 SCD1U SCD1U SCD1U 1 1 1 C304 SC20P 2 C322 SC1U10V3ZY 78.10593.4B1 3D3V_BT_S0 5V_S3 1 MAX 150mA POWER SWITCH C245 SC1U10V3KX 3D3V_BT_S0 1 BC0EX2 BC0EX1 BT_LED 2 1 22 1394_TPBIAS0 TPB0TPB0+ 2 2 R206 56R2F 1 2 R205 56R2F 1 BC0EX2 connect to PCI_AD22 on main board. BC0EX1 connect to ICH_PME# on main board. 1 1 JST-CON8-7 6 3 TD+ --> TX+ RJ45-1 TD- --> TX- RJ45-2 RD+ --> RX+ RJ45-3 RD- --> RX- RJ45-6 These components near to chip side. 2 10/100M Lan Transformer U3 XFR_RDC 3 XFR_CMT 11 XFR_RXC 14 XFR_TDC 6 8 7 TDTD+ RXRX+ 15 16 RDRD+ 2 1 TXTX+ 9 10 RJ45-8 RJ45-7 RJ45-6 RJ45-5 RJ45-4 RJ45-3 RJ45-2 RJ45-1 RXRX+ RXRX+ 25 25 TXTX+ RJ45-8 RJ45-7 RJ45-6 RJ45-5 RJ45-4 RJ45-3 RJ45-2 RJ45-1 13 13 13 13 13 13 13 13 JK1 1 9 RJ45_END1 XFORM-187-U DY 1 RJ45_END2 1 C25 SCD1U16V R300 75R2F XFR_CMT 1 R298 1 R297 2 75R2F 2 75R2F 2 XFR_RXC RJ45_END LAN_TERMINAL 1.route on bottom as differential pairs. 2.Tx+/Tx- are pairs. Rx+/Rx- are pairs. CN1 3.No vias, No 90 degree bends. 4.pairs must be equal lengths. 5.6mil trace width,12mil separation. 6.36mil between pairs and any other trace. ETY-CON2-R1 7.Must not cross ground moat,except RJ-45 moat. 2 C278 SC1500P2KV8KX 1 RJ45-1 RJ45_1 RJ45-2 RJ45-3 RJ45-4 RJ45-5 RJ45-6 RJ45-7 RJ45-8 RJ45_2 RJ45_3 RJ45_4 RJ45_5 RJ45_6 RJ45_7 RJ45_8 TIP RING RJ11_1 RJ11_2 1 4 1 R299 75R2F 2 2 C24 SCD1U16V 2 1 TXTX+ CT CT CT CT 1 2 TIP_MDC RING_MDC 1 1 L20 MLB160808 2 2 L21 MLB160808 TIP RING Wistron Corporation 10 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. RJ45-74-U1 3 Title LAN / 1394 Connector 20.D0151.102 Size A3 Document Number Rev A B C D -1 Leopard 3 Date: Monday, August 15, 2005 Sheet E 26 of 41 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,29,30,31,32,36,38,40,41 3D3V_S0 5V_S0 3D3V_S0 BC80 SC1U10V3ZY 2 2 BC81 SCD1U16V 5V_S0 1 1 1 BC82 SCD1U16V 2 2 1 13,14,18,19,20,21,23,24,28,29,32,36,39,40,41 BC79 SCD1U16V 4 4 AUD_AGND 5V_AUDIO_S0 2 1 3 BC47 2 DUMMY-C2 DY DY 5V_S0 BC84 SC22P DY 1 DUMMY-R2 R241 4K7R2 AUX_L AUX_R 5V_AUDIO_S0 R515 28K7R3F EC156 SCD1U16V 2 SPDIF_OUT DY 2XTALOUT_CODEC_R1 1 AC97_BITCLK 16,30 AC97_SYNC 16,30 AC97_RST# 16,30 SPDIF_OUT 13 2 BC45 SC22P 1 1 2 33R2 DY R242 U63 1 SHDN# 2 GND 3 IN SET BC85 SC1U10V3ZY AD1981B-AS 5VA_SET 5 5V_AUDIO_S0 OUT R516 10KR3F 4 MAX8863-S BC83 SC10U10V6ZY-U For High limit --> H45 2 AUD_AGND 2 AC97_CBITCLK 1 R224 6 10 11 48 AC97_DIN0 16 AC97_DOUT 16,30 1 29 30 31 32 AFILT1 AFILT2 AFILT3 AFILT4 27 28 VREF VREFOUT 1 9 DVDD1 DVDD2 HP_OUT_L HP_OUT_R 26 40 44 33 2 1 2 22R2 1 1 R219 X3 X-24D576MHZ-3-U1 2 CD_AGND BIT_CLK SYNC RESET# SPDIF 2 22R2 1 BC37 DUMMY-C2 DY 1 21 CD_L CD_R CD_GND_REF AC97_DIN0_CODEC 1 R223 2 2 2 22R2 8 5 CLK_CODEC 3 XTALOUT_CODEC 1 1 R218 SDATA_IN SDATA_OUT DY 1 CD_AUDR 2 3 2 BC46 SC22P 1 2 21 1 2 22R2 XTL_IN XTL_OUT 2 1 R221 HPSENSE 28 EAPD 28,31 R243 0R2-0 1 2 MONO_OUT PHONE_IN HPSENSE_1 28 1 DY CD_AUDL DY 3 S1N4148-U2 2 2K2R2 2 DY 21 2 3 1 R499 17 16 47 NC NC R220 150KR2J BC42 AUD_MDC_CODEC 37 2 SCD1U16V AUD_PHONE_CODEC13 2 BC36 SCD1U16V CDAUDL CDAUD_L 18 1 2 BC35 CDAUD_R 20 SC1U25V5ZY CDAUD_GND 19 CDAUDR 1 2 BC33 39 SC1U25V5ZY 41 CDAGND 1 2 BC34 AUD_PC_BEEP 14 SC1U25V5ZY 15 R217 R222 150KR2J 150KR2J 1 1 30 AUD_MDC_OUT 30 AUD_PHONE 1 AD1981_JS0 12 42 AUD_LOR LINE_IN_L LINE_OUT_L LINE_IN_R LINE_OUT_R ID1# ID0# 28 23 35 24 36 D10 U41 JS0 JS1 EAPD 46 45 AUD_LOL MIC1 MIC2 4 7 28 21 22 DVSS1 DVSS2 BC32 SC1U10V3ZY AVDD1 AVDD2 AVDD3 AVDD4 BC31 SC1U10V3ZY AUD_MICIN1 2 1 AUD_MICIN2 2 1 AVSS1 AVSS2 AVSS3 AVSS4 EXT_MIC_1 EXT_MIC_2 R213 10KR2 AUD_AGND 25 38 43 34 AUD_AGND 3D3V_S0 2 1 2 C267 SC270P50V3JN 1 2 C265 SC270P50V3JN 2 C266 SC270P50V3JN 1 2 C268 SC270P50V3JN 1 BC43 SCD1U16V ADAF1 ADAF2 ADAF3 ADAF4 2 2 2 2 BC73 BC41 BC44 SCD1U16V SCD1U16V SCD1U16V CODECVREF VREFOUT 1 1 1 1 1 13 13 AUD_AGND HP_OUT_L HP_OUT_R AUD_AGND AUD_AGND G38 1 VREFOUT 2 GAP-CLOSE 2 2 BC29 SC1U10V3ZY 1 1 2 R215 3KR2F DY 13 1 GAP-CLOSE MIC2 PREAMP 2 AUD_AGND EXT_MIC_2 AUD_AGND CLOSE TO CODEC 5V_AUDIO_S0 UNDER CODEC 1 U40A 2 14 GAP-CLOSE 7 2 TSAHCT86 BC30 SC1U10V3ZY DY R251 1KR2 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. CLOSE TO CODEC 1 AUD_AGND 1 AUD_AGND SB-27-02 1 2 EXT_MIC_1 AUD_AGND AUD_AGND MIC1 PREAMP AUD_AGND 13 R216 3KR2F BC28 SC1000P50V3KX Title Date: Tuesday, July 12, 2005 B C D Sheet E 27 Rev of 41 -1 xa Leopard 3 in Document Number he Size A3 AUD_AGND f@ AUDIO CODEC AD1981B AUD_AGND A om C272 SCD1U16V GAP-CLOSE l.c TSAHCT86 AUD_AGND R252 10KR2 2 10KR2 ai AUD_SYS_BEEP 1 R238 C264 SCD1U16V AUD_BEEP 1 AUD_PC_BEEP 2 2 tm 7 AUD_BEEP2 10 1 ho 8 5 AUD_AGND G39 2 1 14 U40C 1 VREFOUT U40B 4 9 U39_PL 2 GAP-CLOSE 2 7 14 1 1 G40 6 KBC_BEEP G35 2 AUD_AGND 5V_AUDIO_S0 AUD_AGND 5V_AUDIO_S0 31 G68 1 AUD_AGND TSAHCT86 2 2 1 ICH_SPKR CUT MOAT GAP-CLOSE 2 17 3 BC27 SC1000P50V3KX AUD_BEEP1 1 1 1 PCI_SPKR 2 22 AUD_AGND 2 G36 A B C D E 5V_S0 13,14,18,19,20,21,23,24,27,29,32,36,39,40,41 2 BC88 SC10P50V2JN-1 1 R519 CSOUTL2 1 4 2 SC4D7U10V5ZY 1 R518 5V_S0 BC50 1 2 AUD_LOL 2 BC49 SC220P 1 SB 27 SPKR_L+ 2 20KR2 15KR2 R254 CSOUTL1 1 SCD1U16V3KX 2 L_LINE_IN 1 SPKR_L+ 1 2 18KR2J R253 1 BC78 AUD_LOL 1 2 4 15KR2 2 DK_SPKR_L+ 13 R561 100KR2 TC21 SE100U16VGM-2 2 BC86 SCD1U16V3KX AUD_AGND R_BYPASS HP_R AUD_AGND 8 2 17 23 SHUTDOWN TJ HP-IN VOL 18 19 20 21 RVDD RBYPASS RHPIN RLINEIN G1421BF3U AUD_AGND SE/BTL# HP/LINE# MUTEIN MUTEOUT GND/HS GND/HS GND/HS GND/HS 14 16 11 9 1 12 13 24 ROUTROUT+ 15 22 SPKR_L+ SPKR_L- G1420_SHUTDOWN# D 3 10 Q40 2N7002-F-GP HPSENSE_1 G PM_SLP_S3# 17,21,31,37,38,40 AUD_MUTE AUD_AGND G1420_SHUTDOWN# 1 R517 10KR2 DY 2 AUD_AGND SPKR_RSPKR_R+ AUD_AGND SB 3 25 3 LOUT+ LOUT- GND 1 1 BC74 SCD1U16V3KX 2 2 1 L_BYPASS G1420_SHUTDOWN# LLINEIN LHPIN LBYPASS LVDD S 4 5 6 7 HP_L 2 U62 5VA_OP_S0 BC87 SC10U10V6ZY-U 5V_S0 AUD_AGND 27 BC40 SCD1U16V3KX CSOUTR1 1 1 2 R240 AUD_LOR R_LINE_IN 2 15KR2 1 SPKR_R+ 2 18KR2J R239 1 DK_SPKR_R+ 13 2 TC22 SE100U16VGM-2 1 2 BC39 SC220P 5VA_OP_S0 5V_S0 BC77 SC4D7U10V5ZY AUD_LOR 1 2 CSOUTR2 G67 1 R513 2 15KR2 1 R514 SPKR_R+ 2 20KR2 1 2 GAP-CLOSE-PWR 1 2 BC76 SC10P50V2JN-1 5V_S0 R_BYPASS 1 L_BYPASS 1 1 R510 100KR2 R509 100KR2 HPSENSE_1 2 Q29 2N7002-F-GP 2 AUD_AGND 1 R214 EARPHONE 2 22KR2J 2 2 C457 SC1U10V3ZY S 1 13 EARPHONE_R 2 BC75 SC4D7U10V5ZY AUD_AGND HPSENSE 27 1 G 13 JACK_DETECT# HPSENSE_1 27 BC48 SC4D7U10V5ZY D 1 2 5V_S0 2 2 C251 SC1U10V3ZY 5V_S0 14 9 8 HPSENSE TSAHCT32 AUD_MUTE SPK1 6 4 3 2 1 1 10 EC152 SC220P EC154 SC220P 1 5 TSAHCT32 2 R512 10KR2 EC159 SC220P 2 7 1 AUD_MUTE_1 1 6 SPKR_RSPKR_L+ SPKR_L- 2 5 27,31 U61C 1 EAPD 1 SPKR_R+ U61B 2 4 1 KBC_MUTE Speaker 2 31 7 14 5V_S0 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. ETY-CON4-11-U EC153 SC220P 20.D0151.104 Title AUDIO Size A3 Document Number Rev A B C D -1 Leopard 3 Date: Monday, August 15, 2005 Sheet E 28 of 41 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,30,31,32,36,38,40,41 3D3V_S0 5V_S0 MINI-PCI 13,14,18,19,20,21,23,24,27,28,32,36,39,40,41 5V_S0 4 4 PCI_C/BE#[3..0] 1 1 BC72 SCD1U16V 2 2 BC69 SCD1U16V 2 BC71 SC4D7U10V5ZY 13,17,22,25 2 PCI_AD[31..0] 1 1 3D3V_S0 BC70 SCD1U16V 17,22,25 3D3V_S0 3D3V_S5 2 1 CN13 TIP R244 10KR2 R476 DUMMY-R2 1 2 DY 14 802_ACT_LED WIRELESS_EN WIRELESS_EN D INT_PIRQE# 3D3V_S0 Q12 2N7002-F-GP 3 G 3 PCLK_MINI 17 PCI_REQ#0 S 17 WIRELESS_EN# MINI_PIN21 TPAD30 TP25 PCI_AD31 PCI_AD29 PCI_AD27 PCI_AD25 26 WLAN_ACT 3D3V_S0 PCI_AD21 PCI_AD19 1 PCI_AD17 PCI_C/BE#2 R477 10KR2 2 PCI_C/BE#3 PCI_AD23 17,22,25 PCI_IRDY# 17,22,25,31 PM_CLKRUN# 17,22,25 PCI_SERR# 17,22,25 PCI_PERR# PCI_C/BE#1 PCI_AD14 PCI_AD12 PCI_AD10 2 PCI_AD8 PCI_AD7 PCI_AD5 PCI_AD3 5V_S0 PCI_AD1 1 125 2 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 123 124 126 RING 5V_S0 INT_PIRQE# 17,25 3 3D3V_S5 PCIRST1# 19,22,23,25,31 3D3V_S0 PCI_GNT#0 17 MINI_PME# 1 R484 PCI_AD30 PCI_AD28 PCI_AD26 PCI_AD24 MOD_IDSEL 1 2 DY 0R2-0 ICH_PME# 13,17,25 BT_PRIOR 26 1201 -2 R485 2 10R2 PCI_AD21 PCI_AD22 PCI_AD20 PCI_PAR PCI_AD18 PCI_AD16 17,22,25 PCI_FRAME# 17,22,25 PCI_TRDY# 17,22,25 PCI_STOP# 17,22,25 PCI_DEVSEL# 17,22,25 PCI_AD15 PCI_AD13 PCI_AD11 2 PCI_AD9 PCI_C/BE#0 PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0 PCI_SERIRQ 17,22,31 3D3V_S5 PCIMODEM124A1U1 62.10032.001 1 1 The symbol use 2nd source The P/N is the main source Main source:62.10032.001 2nd source:62.10032.031 l.c ai tm MINI-PCI B C D Rev 41 -1 xa Leopard 3 Date: Tuesday, July 12, 2005 of in Document Number Sheet E he Size A3 f@ ho Title A om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 29 A B C D E 5V_AUX USB POWER 14,15,35,37,38,39 5V_AUX 5V_S3 5V_S3 13,14,26,28,32,37,38,40,41 5V_USB1_S3 F1 100 mil C104 SC1000P50V 2 1 3D3V_S3 1 1 C105 SCD1U16V 2 4 2 MINISMDC110-U C106 SC4D7U10V5ZY 1 2 2 1 5V_S3 13,14,40 3D3V_S3 TC6 ST100U6D3VBM-6GP 4 5V_USB1_S3 USB1 11 9 1 0329 SB 17 17 3 5 2 3 4 10 12 USB_PN4 USB_PP4 6 7 8 USB_PN5 USB_PP5 17 17 3 SKT-USB-76-U 2 2 MDC Connector AUD_MDCIN 1 1 3D3V_S0 DY G64 2 2 GAP-CLOSE-PWR 16,27 AC97_DOUT 16,27 AC97_RST# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 33 2 C411 SCD1U16V AUD_PHONE 27 Check with Ambit ACSDATAIN1_A ACSDATAIN1_B 1 R168 34 1 C413 SCD1U16V C412 DY SC4D7U10V5ZY 2 1 1 2 1 MDC_S3_1 32 36 R486 DUMMY-R2 CN9 31 AMP-CONN30A-1 20.F0099.030 2 22R2 1 R169 AC97_SYNC 16,27 AC97_DIN1 16 2 DY 22R2 1 AC97_BITCLK 16,27 Wistron Corporation 1 3D3V_S3 35 DY DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. C222 SC22P 2 R155 2 1 27 AUD_MDC_OUT Title DY USB / MDC CONN. Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 30 of 41 A B C D E 3D3V_S0 IOPF0/PSCLK1 IOPF1/PSDAT1 IOPF2/PSCLK2 IOPF3/PSDAT2 IOPF4/PSCLK3 IOPF5/PSDAT3 IOPF6/PSCLK4 IOPF7/PSDAT4 1 R141 20MR3 2 3D3V_S0 32 32 2 X4P-32D768KHZ-3 158 160 32KX1/32KCLKIN 32KX2 PSDAT4 2 10KR2 KBC_32KX1 KBC_32KX2 7 BL_ON 14,32 ID_DET 14 FPBACK 20 S5_ENABLE 62 63 69 70 75 76 CHG_I_SEL CHG_I_PRE_SEL CHG_ON# VCC_+3VSB IOPM0/D8 IOPM1/D9 IOPM2/D10 IOPM3/D11 IOPM4/D12 IOPM5/D13 IOPM6/D14 IOPM7/D15 173 174 47 SEL0# SEL12_SEL2# IOPQ3/CLK KBC_SEL1 KBC_CLK 17 35 46 122 137 159 167 PC97551-VPC-U A5/SHBM 1 1 2 2 2 1 IOPE4/SWIN IOPE5/A20//EXWINT40 IOPE6/LPCPD#/EXWINT45 IOPE7/CLKRUN#/EXWINT46 2 44 24 25 KBC_PME# 1 2 0R2-0 R164 2 SRN10K 2 C230 SCD1U16V3KX KBC_3D3V_AUX 150 151 KBC_PME# PM_PWRBTN# B SELIO# 152 PortD-2 PortM IOPD4 IOPD5 IOPD6 IOPD7 41 42 54 55 PR_INSERT# 13 KBC_MUTE 28 ECSWI#_KBC 17 PortK A8 A9 A10 A11 A12 A13_BE0 A14_BE1 A15_CBRD 143 142 135 134 130 129 121 120 A8 A9 A10 A11 A12 A13 A14 A15 33 33 33 33 33 33 33 33 PortL A16 A17 A18 IOPL3/A19 IOPL4/WR1# 113 112 104 103 48 A16 A17 A18 33 33 33 C 2 6K8R2F 2 6K8R2F 2 10KR2 2 R138 3 1 DUMMY-R2 DY KBC_3D3V_AUX DVD_BT# CDROM_BT# 1 R137 1 R166 RSMRST#_KBC 1 R150 2 100KR2 S5_ENABLE 1 R142 2 10KR2 2 10KR2 2 10KR2 KBC HARDWARE SETTING KBC_3D3V_AUX DY R152 A0/ENV0 1 2 A1/ENV1 A2/BADDR0 2 DUMMY-R2 3 4 RN29 2 1 SRN10KJ KBC_SEIO# A3/BADDR1 1 DY A4/TRIS DY TP60 TPAD30 IRE OBD DEV PROG 1 ENV0 0 0 1 1 R153 2 DUMMY-R2 R144 2 DUMMY-R2 ENV1 0 1 0 1 TRIS 0 0 0 0 SHBM=1: Enable shared memory with host BIOS TRIS=1: While in IRE and OBD, float all the signals for clip-on ISE use I/O Address BADDR1-0 Index Data 2E 2F 0 0 4E 0 1 4F (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1 1 0 Reserved 1 1 1 Wistron Corporation TP64 TPAD30 TP71 TPAD30 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title KBC NS97551 C214 SCD1U16V Size Document Number Custom For NS97551 use only Date: Wednesday, July 13, 2005 A 1 R136 1 R135 1 R165 BT_SDA KBCBIOS_RD# 33 KBCBIOS_WE# 33 KBC_PIN21 DY 2 1 BT_SCL PM_CLKRUN# 17,22,25,29 RD# WR0# WR1# SRN10KJ 3 4 RN15 SMBC_KBC SMBD_KBC A0/ENV0 33 A1/ENV1 33 A2/BADDR0 33 A3/BADDR1 33 A4/TRIS 33 A5/SHBM 33 A6 33 A7 33 KBC_D[0..7] 33 KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7 8 7 6 5 KBC_PWRBTN# 32 KBC_LID# 14 138 139 140 141 144 145 146 147 PortJ-1 1 1 1 2 CDROM_BT# 32 CIR_KBC 13 AC_IN# 35 D0 D1 D2 D3 D4 D5 D6 D7 AGND 2 10KR2 1 2 26 29 30 124 125 126 127 128 131 132 133 KBC_3D3V_AUX 1 R143 2 IOPD0/RI1#/EXWINT20 IOPD1/RI2/EXWINT21 IOPD2/EXWINT24/RESET2# NC#11 NC#12 NC#20 VCORF NC#85 NC#86 NC#91 NC#92 NC#97 NC#98 TPAD30 TP59 TPAD30 TP70 1 2 95 AVCC PM_PWRBTN# 17 SMBC_KBC 20 SMBD_KBC 20 MAINTAIN_CHG 35 DVD_BT# 32 PM_SLP_S4# 17,21,37,38 PM_SLP_S3# 17,21,28,37,38,40 CLK32_G768 20 PortJ-2 1 1 2 3 4 2 100KR3F MUTE_BTN# 32 802_BT_BTN# 32 BRIGHTNESS 168 169 170 171 172 175 176 1 PortP AD_IA 1 R175 CAPS_LED 14 NUM_LED 14 MUTE_LED 13,14 BT_SCL 34 BT_SDA 34 PCIRST1# 19,22,23,25,29 BT_SCL BT_SDA 11 12 20 21 85 86 91 92 97 98 33 KBCBIOS_CS# 2 0R2-0 IOPC0 IOPC1/SCL2 IOPC2/SDA2 IOPC3/TA1 IOPC4/TB1/EXWINT22 IOPC5/TA2 IOPC6/TB2/EXWINT23 IOPC7/CLKOUT 2 17 RSMRST#_KBC 35 NI_BAT 34 AD_OFF 148 149 155 156 3 4 27 28 PWM_BRI 1 R559 153 154 162 163 164 165 PS2 Interface IOPJ2/BST0 IOPJ3/BST1 IOPJ4/BST2 IOPJ5/PFS IOPJ6/PLI IOPJ7/BRKL_RSTO# BRIGHTNESS 14 RN34 VOL_UP_BTN# VOL_DWN_BTN# VOL_UP_DK# VOL_DWN_DK# TP63 TPAD30 TP62 KBC_BEEP 27 TPAD30 PWR_LED 14 CHG_LED 14 VOL_UP_BTN# 32 VOL_DWN_BTN# 32 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 96 1 2 1 2 100KR2 BC14 SC1U10V3ZY 1 R151 2 0R2-0 13 VOL_UP_DK# 13 VOL_DWN_DK# 35 CHG_I_SEL 35 CHG_I_PRE_SEL 35 LI/NI# 35 CHG_ON# 1 R134 TCLK_5 TDATA_5 BT_SENSE TP30 TPAD30 TP29 TPAD30 IOPB0/URXD1 IOPB1/UTXD1 IOPB2/USCLK1 IOPB3/SCL1 IOPB4/SDA1 IOPB7/RING#/PFAIL#/RESET2# PortH GND GND GND GND GND GND GND 1 1 PortB 32 33 36 37 38 39 40 43 R174 560KR3F om 110 111 114 115 116 117 118 119 PSCLK1 PSDAT1 PSCLK2 PSDAT2 X1 3D3V_S5 1 1 105 106 107 108 109 KBSOUT0 KBSOUT1 KBSOUT2 KBSOUT3 KBSOUT4 KBSOUT5 KBSOUT6 PortC KBSOUT7 KBSOUT8 KBSOUT9 KBSOUT10 KBSOUT11 KBSOUT12 PortD-1 KBSOUT13 KBSOUT14 KBSOUT15/XOR_OUT PortE TINT# TCK JTAG Debug Port TDO TDI TMS TINT# TCK TDO TDI TMS BC18 SC3P50V2CN 34 45 123 136 157 166 16 49 50 51 52 53 56 57 58 59 60 61 64 65 66 67 68 IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7 99 100 101 102 THERMAL_DP THERMAL_DN R558 0R2-0 DA_BRI 1 DY 2 CHG_ICTL CHG_VCTL BT_TH 34,35 AIRLINE_VOLT 35 AD_IA 35 PM_SUS_STAT# 17 KBC_MATRIX1 32 KBC_MATRIX2 32 EAPD 27,28 4 3D3V_S0 l.c 5 6 7 8 RN28 SRN10K-2 1 R140 DA0 DA1 DA2 DA3 81 82 83 84 87 88 89 90 93 94 BT_SENSE 3D3V_S5 ai 4 3 2 1 3D3V_S0 KCOL1 KCOL2 KCOL3 KCOL4 KCOL5 KCOL6 KCOL7 KCOL8 KCOL9 KCOL10 KCOL11 KCOL12 KCOL13 KCOL14 KCOL15 KCOL16 17,18,19,21,25,29,35,37,39,40 tm KCOL[1..16] Key Matrix Scan 5V_AUX ho 32 PWM or PortA KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 BC26 SCD1U16V BT+ DA Output 71 72 73 74 77 78 79 80 BC24 SCD1U16V D Rev Leopard 3 Sheet E f@ MOLEX-CON8-2 4 Host Interface KROW1 KROW2 KROW3 KROW4 KROW5 KROW6 KROW7 KROW8 BC23 SCD1U16V in KROW[1..8] BC20 SCD1U16V 3D3V_S5 AD0 AD1 AD2 AD3 IOPE0 IOPE1 IOPE2 IOPE3 NC#93 NC#94 AD input IOPB5/(GA20) IOPB6/KBRST# BC16 SCD1U16V -1 xa 32 DY KBC_32KX2_1 IOPD3/ECSCI 5 6 10 BC19 3 31 BC21 SCD1U16V 16,20,32,34,35,36,37 3D3V_AUX 31 of he ECSCI#_KBC 3D3V_AUX 1 17 16 ICH_A20GATE 16 RCIN# KBC_D0 TINT# TCK TDO TDI TMS SC3P50V2CN 2 SERIRQ IOPQ0/LDRQ# LFRAME# LAD0 LAD1 LAD2 LAD3 LCLK RESET1# IOPQ1/SMI# IOPQ2/PWUREQ# 3D3V_S0 14,15,35,37,38,39 5V_AUX DUMMY-R2 DY 9 1 2 3 4 5 6 7 8 KBC_PWUREQ# 7 8 9 15 14 13 10 18 19 22 23 2 1KR2 BC17 SCD1U16V 2 KBC_3D3V_AUX CN15 LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 3 PCLK_KBC 16,20,39 RSMRST# 17 ECSMI#_KBC 2 R173 ECSWI#_KBC 1 2 VDD 2 17,22,29 PCI_SERIRQ 16 LPC_LDRQ0# 16 LPC_LFRAME# 3 U33 BC22 SCD1U16V VCC VCC VCC VCC VCC VCC 1 16 LPC_LAD[0..3] 4 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,32,36,38,40,41 161 DY GAP-CLOSE-PWR BC25 SCD1U16V KBC_3D3V_AUX VBAT 2 2 SSM5818SL 2 BLM11P600S L18 BC15 SCD1U16V 2 1 1 1 D7 3D3V_S0 G33 KBC_AVCC KBC_3D3V_AUX 1 3D3V_AUX RTC_AUX_S5 KBC_RTC_VCC1 R139 2 KBC_3D3V_AUX 41 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,36,38,40,41 3D3V_S0 3D3V_S0 16,20,31,34,35,36,37 R319 10KR2 KCOL[1..16] 5V_S0 R321 10KR2 13,14,18,19,20,21,23,24,27,28,29,36,39,40,41 31 2 802_BT_BTN# 5V_S3 LAUNCH Board 2 MUTE_BTN# CN7 1 3D3V_AUX 2 POWER BUTTON 1 R322 31 KBC_PWRBTN# 2 470R2 R303 10KR2 5V_S0 C290 SCD1U10V2MX-1 2 1 PWRBTN# SCD1U10V2MX-1 14 PWR_LED# 14 MUTE_LED# 14 802_BT_LED# 31 VOL_UP_BTN# 31 VOL_DWN_BTN# 31 802_BT_BTN# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 14,31 ID_DET 14 NUM_LED# 31 MUTE_BTN# 1 DVD_BT# CDROM_BT# EC89 EC88 SC1000P16V2KX SC1000P16V2KX 26 PA JST-CON20 2 KBC_MATRIX2,KBC_MATRIX1 R177 10KR2 3 PR 3D3V_S0 DY FF 00 01 DF 10 11 1 1 DY 2 the matrix table for PCB R178 10KR2 22 1 BC58 SCD1U16V 31 DVD_BT# 31 CDROM_BT# KBC_3D3V_AUX 4 21 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 KROW8 KROW7 KCOL10 KROW5 KROW6 KCOL1 KROW3 KROW4 KCOL6 KCOL2 KROW1 KCOL3 KCOL5 KCOL8 KCOL9 KCOL7 KCOL4 KCOL13 KCOL14 KCOL15 KCOL12 KCOL11 KCOL16 2 KROW2 ETY-CON24-1 20.K0170.001 D32 BAV99LT1 EC82 1 DY EC83 EC85 EC86 SC1000P16V2KX 1 1 EC84 2 2 2 SC1000P16V2KX SC1000P16V2KX SC1000P16V2KX SC1000P16V2KX SC1000P16V2KX EC87 2 10KR2 1 VOL_DWN_BTN# VOL_UP_BTN# 802_BT_LED# MUTE_LED# PWR_LED# NUM_LED# 1 DY R176 2 VOL_UP_BTN# 3 KBC_MATRIX2 31 KBC_MATRIX1 31 2 2 2 10KR2 1 1 1 DY R179 1 3 1 2 2 25 5V_S0 CN2 C289 1 2 2 31 4 3D3V_AUX 1 1 INTERNAL KEYBOARD CONNECTOR KROW[1..8] 3D3V_AUX 3D3V_S0 3D3V_S0 D33 NONE Quick Play Quick Play 2 VOL_DWN_BTN# 3 0 MATRIXID1# 1 1 BAV99LT1 DY TouchPad Connector 5V_S3 for EMI CN8 9 8 7 6 5 4 3 2 for EMI KROW3 KCOL1 KROW6 KROW5 1 2 1 BC64 SC47P50V2JN 2 BC63 SC47P50V2JN 1 RC1 SRC100P50V-U 2 8 7 6 5 TDATA_5 TCLK_5 1 2 3 4 RC2 SRC100P50V-U 1 2 3 4 RC3 SRC100P50V-U 1 2 3 4 1 2 3 4 RC4 SRC100P50V-U 8 7 6 5 8 7 6 5 8 7 6 5 31 31 R434 10KR2 2 R433 10KR2 KCOL16 KCOL11 KCOL12 KCOL15 2 KCOL14 KCOL13 KCOL4 KCOL7 1 KROW1 KCOL2 KCOL6 KROW4 2 KCOL9 KCOL8 KCOL5 KCOL3 2 1 1 2 DY DY DY DY 1 BC68 BC62 10 SC1U10V3ZY SCD1U16V ETY-CON8-5 20.K0121.008 KCOL10 KROW7 KROW8 KROW2 8 7 6 5 1 8 7 6 5 1 Wistron Corporation RC5 SRC100P50V-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 2 3 4 1 2 3 4 RC6 SRC100P50V-U Title KEYBOARD/TOUCH PAD/Launch key Size A3 Document Number for EMI Date: Tuesday, July 12, 2005 A B C D Rev Leopard 3 Sheet E -1 32 of 41 A B C D E 3D3V_S0 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 5V_S0 13,14,18,19,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0 4 4 KBC_D[0..7] 3 31 3 512KB Flash U38 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 31 KBC_3D3V_AUX 31 31 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A0/ENV0 A1/ENV1 A2/BADDR0 A3/BADDR1 A4/TRIS A5/SHBM A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 20 19 18 17 16 15 14 13 3 2 31 1 12 4 5 11 10 6 9 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VDD KBC_D0 KBC_D1 KBC_D2 KBC_D3 KBC_D4 KBC_D5 KBC_D6 KBC_D7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 21 22 23 25 26 27 28 29 CE# 30 KBCBIOS_CS# 31 WE# 7 KBCBIOS_WE# 31 OE# 32 KBCBIOS_RD# 31 VSS 24 PM39LV040-70VC 2 2 1 1 tm ai l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. BIOS/GF Date: Tuesday, July 12, 2005 A B C D E Rev 41 -1 xa Leopard 3 Sheet of in Document Number he Size A3 f@ ho Title 33 A B C D E 3D3V_AUX Adaptor in to generate DCBATOUT 16,20,31,32,35,36,37 3D3V_AUX AD+ D15 3 Layout 1 AD+ 200mil 13,35,41 AD+ 31,35,41 BT+ BT+ MMBZ5252B DCIN1 4 AD_JK 3 AD+_2 1 2 EC1 SCD1U50V3ZY 4 D D D D 5V_AUX 8 7 6 5 14,15,35,37,38,39 5V_AUX 1 1 1 R15 200KR2J BC51 SCD1U50V3ZY EC165 SCD1U50V3ZY 2 DC-JACK92 U1 S S S G AO4407 2 2 5 2 BC52 SC1000P50V 1 4 1 2 3 4 2 1 2 1 B 2 IN AD_OFF Q1 R14 100KR2 2 PDTA124EU C Q2 31 1 1 E AD_OFF# 3 3 OUT R1 2 C274 SCD1U50V5KX 1 GND R2 DTC114EUA-U1 3 3 3D3V_AUX 3D3V_AUX 3D3V_AUX D17 D18 2 BT_SCL D16 2 3 BT_SDA 2 BT_TH 3 3 1 1 1 BAV99LT1 BAV99LT1 BAV99LT1 BATTERY CONNECTOR BT+ 2 CN11 2 2 7 1 1 F2 FUSE-10A125V 31 31 31,35 G5 35 BT+SENSE 1 2 BT_SCL BT_SDA BT_TH BAT+ 2 BCC1 SCD1U 2 1 SYN-CON6-2-U2 1 GAP-CLOSE 2 3 4 5 6 8 BC3 SC1000P50V 1 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Adaptor/ Bettery conn. Size A3 Document Number Rev A B C D -1 Leopard 3 Date: Tuesday, July 12, 2005 Sheet E 34 of 41 A B C DB1 2 CB1 SCD1U 1 D E 3D3V_S5 3D3V_AUX 2 16,20,31,32,34,36,37 3 AIRLINE_VOLT -1 1 14,15,37,38,39 1 C275 SC1000P50V R367 100KR2F L35 S S S G AD+_TO_SYS 1 2 3 4 1 2 1 2 1 2 3 4 HI1806T600R-00 D01R3720F 14,37,38,39,40,41 U46 S S S G AO4407 D D D D 8 7 6 5 AO4407 BT+ 2 1 1 G CHG_ON# 2N7002-F-GP S 1 2 1 1 2 2 1 23 MAX1909_DHI DLO 20 MAX1909_DLO 1 DHI 5 6 7 8 CSSN 21 BT+ 1 PKPRES# ACOK 1 R38 2 3 PGND 19 U10 SI4800BDY TC12 SC10U25V0KX 1 6 2 31K6R2F AC_OK 1 R327 L23 D015R3720F-1 2 2 CLS 2 CHG_PWR-31 IND-15UH-35 1 1 IINP 9 R324 CHG_PWR-2 5 6 7 8 ACIN 8 MAX1909_CLS C64 SC1U10V3ZY D D D D 3 MAX1909_IINP MAX1909_DLOV TC13 SC10U25V0KX G S S S 1 R328 31 2 2 25 2 MAX1909_LDO S G 4 3 2 1 1 1 2 DLOV VCTL ICTL MODE 4 3 2 1 Q23 D D S 2 2 G CHG_I_SEL 11 10 7 D 1 1 Q24 2N7002-F-GP 31 C46 SC10U25V0KX C45 SC10U25V0KX Near MAX1909 Pin 21 2 2 22 28 2 2 MAX1909_VCTL MAX1909_ICTL MAX1909_MODE R330 49K9R3F LI/NI# CSSP 2 1 1 1 1 20KR3F C47 SCD1U R37 33R2 DHIV PDL LDO PDS SRC DCIN U9 SI4431BDY D D D D MAX1909_PDS27 AD+_TO_SYS 24 MAX1909_DC_IN 1 R40 28K7R3F QB1 2N7002-F-GP 31 U11 2 C49 SC1U10V3ZY 1 S S S G 2/24 Close to MAX1909 pin 24 Near MAX1909 Pin 2 C65 SCD1U25V3KX MAX1909_DHIV R41 MAX1909_LDO C67 SCD1U CSSN1 2 2 1 R39 39KR3F 26 2 C50 SCD1U C68 EC166 SCD1U SCD1U25V3KX C66 SCD1U25V3KX 2 1 1 1 MAX1909_REF 3 R305 22K6R3F 4 DCBATOUT MAX1909_LDO R329 100KR3 BT+ AD+_TO_SYS 2 CH521S-30 R304 54K9R3F 31,34,41 G41 1 1 AD+ GAP-CLOSE-PWR GAP-CLOSE-PWR HM1-SB ACOK is 13V D4 AD+ G42 13,34,41 MAX1909_PDL R365 19K1R3F 2 SET Vout MAX VCELL= 4.1998V/CELL VBAT=CELL*VCELL==>VCELL=VBAT/CELL =VREF+(VVCTL-1.8) /9.52 =4.1998V 2 2 2 MAX1909_ACIN AD+ C288 SCD1U DY AC_IN Threshold 2.089V Max. AC_IN > 2.089V --> AC DETECT DCBATOUT BT+ 2 1 2 4 D D D D DCBATOUT DCBATOUT DCBATOUT_BEAD R272 U43 8 7 6 5 5V_AUX BAV99LT1 2 AD+ 5V_AUX 31 HM1-SB AD<=17V, disable charger function R366 100KR2F 1 2 15K4R2F-GP 1 1 R368 3D3V_AUX 2 49K9R2F 2 1KR2 5 PGND 29 CSIP 18 CSIN BATT GND 17 16 15 PKPRES G6 BT+SENSE 34 1 4 1 2 3 2 DCBATOUT 1 2 499R5F BT+ 1 RB3 100KR2 DY 5V_AUX 1 RB4 49K9R2F 1 DY 2 1K5R3F R306 100KR2 31 U47 2 1 ho CHARGER MAX1999 Size C Date: C tm 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title If Charger is MAX8725,dummy them. B ai Wistron Corporation 2N7002S If Charger is MAX1909,dummy them. A l.c 6 f@ AC_IN# D Document Number Rev -1 Leopard 3 Sheet Thursday, August 18, 2005 E in 31 om 5 DY AC_OK xa 1 G MAX1909_ICTL 3 35 of he 31 MAINTAIN_CHG Maintain Charge Current = 12.2mA MAINTAIN_CHG is H 4sec, L 1sec So, Avg. Current = 9.76mA 4 S DY DY MAX1909_ICTL 1 2 D NI_BAT 2N7002S DY QB3 2N7002-F-GP RB1 100KR3F 1 2 2 4 1 RB2 DY 2 31 CHG_I_PRE_SEL 2 6 GAP-CLOSE-PWR QB2 TP0610K-U 1 3 1 R332 3 5 G7 D 5 4 2 PKPRES# G 6 2 BT_TH 2 31,34 S 1 1 2 U48 R331 100KR2 2 1 2 C48 SC1U10V3ZY R326 19K6R3F UB1 2N7002S DY R307 100KR2 MAX1909_LDO R308 100KR2 1 SET CHG OFF BAT_CHG_I = (0.075/R624)*(VICTL/3.6) LI BAT : CHG_I_SET = H(6cell), Charge current = 3A CHG_I_SET = L(12cell), Charge current = 3.3A NI-MH BAT : NI_BAT = H, Charge current = 2.5A Pre-Charge (or Maintain Charge) : MAX8725 MAX1909 : Pre-Charge current = 300mA, MAX8725 : CHG_I_PRE_SEL = H, Pre-Charge current = 200mA Maintain charge current = 12.5mA ==> H 4sec, L 60sec So,Constant Power=18.5*3.16=58.46W MAX1909_CLS(90%) 2 2 ISOURCE_MAX = (0.075/R615)*(VCLS/VREF) = 3.16A R325 27KR3F 1 When V(ICTL)<0.8V or DCIN<7V -->Charge Disable 1 C41 SCD01U16V3KX 3D3V_AUX V_REF :4.2235V (<500uA) 2 1 MAX1909ETI 1 2 C40 SCD01U16V3KX C42 SCD01U16V3KX 2 2 CCV CCI CCS MAX1909_REF -1 13 12 14 REF 1 R27 16K5R3F 2 C43 SCD1U16V3KX R26 10KR2 1 1 GAP-CLOSE-PWR 2 3/19 HM1-SD Detect adaptor input current 1 AD_IA MAX1909_CCV MAX1909_CCI MAX1909_CCS 2 2 31 1 41 A B C 5V_S5 D E 5V_S5 DCBATOUT_BEAD 2 DCBATOUT_BEAD 2 1KR2 7 1 C1 SC270P50V2JN 1 2 MAX1907_CC 12 SHDN# FB 15 NEG 14 TON 1 R9 MAX1907_NEG GND NC 11 41 TIME DY 1 2 2 2 2 2 1 1 1 1 1 1 2 DUMMY-R3 2 C35 SCD47U10VKX G4 G3 3 GAP-CLOSE-PWR LS/IRFR3709Z/8.2mOhm/@4.5V GAP-CLOSE-PWR 1907_CSP 1 R268 1 1 2 DY 1 R4 1 R293 2 DY 130R3F 2 698R2F G1 2 100KR2F 1 offset 1.2% 2 GAP-CLOSE 2 R582 DUMMY-R2 2 1 1 S R294 1K18R3F R3 47KR3 1 2 0R2-0 R271 100KR2 1 13 MAX1907AETL-U 2 1 R581 17 PM_DPRSLPVR POS 1 PM_STPCPU# 3,17 PM_STPCPU# 1 G S R20 1 2 20 2 DDO# 39 1 1 2 27 Q3 IRFR3709Z 2 130R3F MAX1907_POS SUS ILIM 35 MAX1907_ILIM 9 R270 150KR2F DPSLP# REF 1 G TC11 TC3 TC4 TC2 ST220U2VDM-1 ST220U2VDM-1 ST220U2VDM-1 ST220U2VDM-1 GAP-CLOSE-PWR Q16 IRFR3709Z R62 698R2F G2 D 2 110R2F 2 C4 SC100P50V2JN-U 1 CC 8 MAX1907_REF C3 SC1U10V3KX 1 R7 2 C6 SC470P50V2KX R21 698R2F D 2 MAX1907_OAIN+ MAX1907_OAIN- 1 2 200R2F 1 17 16 2 C5 SC1000P50V 1 R8 2 OAIN+ OAIN- 1 2 IND-D68UH-10 L1 1 1907_CSP1 1907_CSN1 2 200R2F 1 40 4 4 2 18 19 2 R269 DY DUMMY-R2 CSP CSN 1 1 R5 1 1 R2 Ton=NC, Freq.=300KHz PGND 2 CPU_SHDN# 3 29 28 1907_CSP_G B0 B1 B2 DL 1 38 1 2 3 2 R553 100KR2 D0 D1 D2 D3 D4 D5 VCC_CORE_S0 MAX1907_DL 2 MAX1907_B0 MAX1907_B1 MAX1907_B2 26 25 24 23 22 21 HS/IRFR3707Z/12.5mOhm/@4.5V MAX1907_LX 2 32 S MAX1907_DH 2 LX G S 1 33 G 2 C8 SCD1U25V3KX 1 2 DH S0 S1 S2 2 0R3-0-U 4 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 1 5 5 5 5 5 5 4 5 6 1 R10 4 TC10 SE100U25V-U1 VCC_CORE_S0_G92 31 3 BST 3 MAX1907_S0 MAX1907_S1 MAX1907_S2 CLKEN# SYSPOK IMVPOK 3 38 36 37 SYSPOK VGATE Q4 IRFR3707Z C286 C285 C13 C9 C287 SC4D7U25V6KX-L SC4D7U25V6KX-L SCD1U SC4D7U25V6KX-L SC4D7U25V6KX-L 1 4 20 1 3,20 CLK_PWRGD# C14 SCD1U Q15 IRFR3707Z 1 1 30 D 2 1 VDD D D1 SSM5818SL 2 34 VCC 1 C12 SC4D7U10V5ZY U2 V+ 10 R12 100KR2 3 2 2 1 1 R11 100KR2 R554 0R3-0-U DY 4 R13 2K2R2F 1 R537 0R3-0-U 2 C7 SCD1U25V3KX 78.10422.2B1 1 2 C2 SC4D7U10V5ZY 1 2 DCBATOUT_BEAD 2 3D3V_S0 R535 10R3 2 MAX1907_VCC 1 1 CPU_CORE-MAX1907 5V_S0 3D3V_S0 2 3D3V_AUX 2 1 2 VCCP_GMCH_S0 1 R527 100KR2 2 R529 4K7R2 2 DY D R528 10KR2 1 OCP=30A, Vally current = 27.5A, Vilim=550mV(55mVp-p*10) SYSPOK 2 Q31 2N7002-F-GP G 1 1 0 1 0 1.292 0 1 1 1 0 0 1.260 0 1 1 1 0 1 1.244 0 1 1 1 1 1 1.212 1 0 0 0 0 1 1.180 1 0 0 0 1 1 1.148 1 0 0 1 1 0 1.100 1 0 1 0 0 1 1.052 1 0 1 0 1 1 1.020 1 0 1 1 1 0 0.972 1 1 0 0 0 0 0.940 1 R290 DUMMY-R2 DY S 3 2 0 R265 DUMMY-R2 Q32 S2N3904-U3 1 1 0 1.324 C462 SCD1U10V2MX-1 R530 22KR2J 2 1 1.340 0 1 1 0 2 1 1 2 R291 20KR2 2 0 1 1 MAX1907_B2 1 1 R292 20KR2 2 2 R282 20KR2 2 1 1 2 R287 20KR2 R281 DUMMY-R2 DY 1 0 2 2 MAX1907_B1 V 0 DY 1 MAX1907_B0 R266 DUMMY-R2 DY VID5 VID4 VID3 VID2 VID1 VID0 5V_S0 1 1 1 MAX1907_S2 1 5V_S0 R267 DUMMY-R2 DY 2 MAX1907_S1 5V_S0 R262 DUMMY-R2 DY 2 2 MAX1907_S0 R263 DUMMY-R2 DY 2 R264 DUMMY-R2 DY 5V_S0 1 5V_S0 1 5V_S0 Vcore VID Boot-up Voltage : 1.2V , B0=L, B1=L, B2=Open Deeper Sleep Voltage : 0.940V , S0=L, S1=L, S2=Open, 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title IMVP IV-CPU POWER-MAX1907 Size A3 Document Number Date: Thursday, August 18, 2005 A B C D Rev -1 Leopard 3 Sheet E 36 of 41 A B C D E 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 SYSTEM DC/DC 3D3V_S5 / 5V_S5 17,18,19,21,25,29,31,35,39,40 16,20,31,32,34,35,36 3D3V_S0 3D3V_S0 3D3V_S5 3D3V_S5 3D3V_AUX 3D3V_AUX 14,18,20,36,38 5V_S5 5V_S5 14,15,35,38,39 5V_AUX 14,35,38,39,40,41 DCBATOUT 5V_AUX 5V_AUX DCBATOUT DCBATOUT MAX1999_VCC 4 4 5V = 5Arms, OCP>6.8A 1 1 C319 SC1U10V3ZY 2 3 D21 BAW56-1 DCBATOUT 16 MAX1999_DH5 LX5 15 MAX1999_LX5 MAX1999_DL3 24 DL3 DL5 19 MAX1999_DL5 22 OUT3 OUT5 21 3 4 ON3 ON5 MAX1999_SHDN# 6 SHDN# MAX1999_FB5 PRO# NC 10 1 MAX1999_PRO# 1 2 100KR2 R385 ILIM5 11 MAX1999_ILIM ILIM3 5 PGOOD 2 1 2 1 5V_AUX 1 MAX1999_LDO5 1 2 C320 SC1U10V3KX 2 2 2 MAX1999_SKIP# 2 GAP-CLOSE-PWR 1 1 1 C318 SC2D2U6D3V3MX-1 ILIM3: 5V * 200K / (200K+300K) = 2.0V 200mV / 24 = 8.3A OCP point = 8.3A +1/2Iripple OCP point = 20A +1/2Iripple 2 GAP-CLOSE-PWR 1 3 OUT 2 1 GND R2 DTC115EE-U EC167 SCD1U25V3KX 5V_S5 spec. = 10mA PM_SLP_S3# 3D3V_S5 PM_SLP_S3# high = PWM PM_SLP_S3# low = Ultrasonic ILIM5: 5V * 200K / (200K+300K) = 2.0V 200mV / 24 = 8.3A OCP point = 8.3A +1/2Iripple G45 1 R1 2 2 2 MAX1999EEI G44 1 2 2 IN These components should be located near by MAX1977 5V_LDO=100mA C316 SCD22U10V3KX MAX1999_LDO3 3D3V_S5 Q26 C77 SC100P50V2JN-U R78 10KR3F 1 300KR3 R75 200KR3 23 3V_LDO=100mA 3D3V_AUX R74 150KR3 R79 15K4R3 1 LDO5 18 LDO3 GND 2 R77 R384 300KR2J R76 300KR3 ILIM*=Vcc 100mV ILIM*=Vref 200mV OCP= 0.1Vth/Rds(on) + 0.5Iripple MAX1999_ON3 1 1 G21 1 2 Wistron Corporation GAP-CLOSE C331 DUMMY-C2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. B C D Sheet E Rev of 41 -1 xa Leopard 3 he Date: Monday, August 15, 2005 in Document Number f@ DC/DC 3V_S5/5V_S5 Size A3 A ho Title DY 2 tm ai l.c C317 DUMMY-C2 DY 1 om MAX1999_ON5 1 SKIP# > 2.4V : PWM mode SKIP# = GND( ,0.8V) : SKIP MODE SKIP# = REF (1.7V~2.3V)/FloatING Ultrasonic MODE(25KHz min) 2 3D3V_DC_S5 1 2 2 5V_AUX MAX1999_V+ 17,21,28,31,38,40 SKIP# Vref = 2V DY 1 5V_S3 12 1 D5 1SS400 5V_DC_S3 REF 25 2 2 8 2 1KR2 2 1KR2 MAX1999_VCC TON MAX1999_REF DY BL3# R81 2MR3 Rds(on) = 24 mohm 2 2 1 R393 1 R386 20,38 1999_S5ENABLE 17,21,31,38 PM_SLP_S4# 39 1 G S S S AO4422 1 13 TC14 ST150U6D3VDM-9 C79 SC47P50V2JN 1 MAX1999_ON3 MAX1999_ON5 U19 9 FB5 2 FB3 4 3 2 1 Rds(on) = 24 mohm D6 1SS400 2 1 2 3 1 7 R82 10KR3F These components should be located near by MAX1977 2 IND-8UH-2 2 MAX1999_FB3 2 1 2 3 4 1 1 2 R80 6K98R3F L28 D D D D 1 1 2 1 2 U25 AO4422 G S S S C78 SC100P50V2JN-U 2 1 1 DH5 LX3 2 DH3 27 5 6 7 8 26 MAX1999_LX3 8 7 6 5 MAX1999_DH3 C96 SC47P50V2JN R90 2MR3 2 5 6 7 8 D D D D G S S S AO4422 MAX1999_BST5R 4 3 2 1 14 5V_DC_S3 CLOSE TO CMOS 1 BST5 C303 SCD1U50V5KX 2 R362 0R3-U U54 VCC V+ 1 1 2 3 4 17 20 R399 0R3-U MAX1977_BST3R 28 BST3 2 IND-8UH-2 D D D D TC19 ST220U4VDM-L3 C82 C83 C98 SC4D7U25V-USC4D7U25V-U SCD1U U16 1 2 2 C336 SCD1U50V5KX 1 1 2 1 1 2 U24 AO4422 G S S S L30 2 47R2 MAX1999_BST3 8 7 6 5 D D D D 3D3V_DC_S5 3 C81 SCD1U C120 SC4D7U25V-U 3V = 4Arms, OCP>6A 1 1 R387 1 C121 SCD1U 2 2 1 C80 SC1U25V5ZY 2 1 Sanyo / 6*7.7 / CV-AX MAX1999_V+ 2 4D7R5 2 1 R83 37 A B For 1.5V SETTING=1.517V OCP_1.05V 2 10KR3F 1 1 R410 DCBATOUT 2 7K87R2F 1 R408 R409 3K9R2F C346 1 2 For 1.05V SETTING=1.061V 5130_INV1 1 R396 5130_FB1 2 C347 SC5600P25V2KX C334 SC3300P50V2KX 3 5130_LH1 C115 SCD1U50V5KX 5130_LL1 1 2 5130_INV3 5130_INV2 5130_TRIP2 1 2 GAP-CLOSE SCD1U16V3KX close to IC 5130_OUT1U 39 5130_OUT1D 39 OCP_1D5V DCBATOUT 1 R394 DCBATOUT 2 20KR3 1 5130_SS_STBY1 C119 SC1500P50V3KX 5130_REF close to IC LL2 OUT2_U LH2 VIN VREF3.3 VREF5 REG5V_IN LDO_IN LDO_CUR LDO_GATE LDO_OUT INV_LDO SS_STBY3 FB3 INV3 PGOUT PG_DELAY TRIP3 VIN_SENSE3 LH3 OUT3_U LL3 OUT3_D OUTGND3 U50 2N7002S 5130_CT 2 3 2 1 2 1 36 35 34 33 32 31 30 29 28 27 26 25 5130_OUT2U 5130_OUT3D 5130_LL3 5130_OUT3U 1 1 1 5130_REF 2 C95 SC1000P25V C97 SCD1U16V3KX 5130_LH3 1 C94 2 2 C118 SC4700P50V3KX 1 2 C344 SCD1U 5V_DC_S5 5V_S5 1 1 R552 2 0R2-0 5V_S3 C463 SCD1U 2 GAP-CLOSE-PWR C93 SC4D7U10V5ZY For 1.5V SETTING=1.505V 5130_SS_STBY3 5130_FB3 5130_INV3 5130_SS_STBY2 17,21,31,37 PM_SLP_S4# DCBATOUT 5130_OUT2U 39 2 TPS5130PT-U 13 14 15 16 17 18 19 20 21 22 23 24 C117 SC47P50V2JN 5130_LL2 39 G52 1 TPS5130 4 5 2 100KR2 6 1 R359 STBY_REF 2 1KR3 FB1 SS_STBY1 INV2 FB2 SS_STBY2 PWM_SEL CT GND REF STBY_VREF5 STBY_VREF3.3 STBY_LDO 3 5130_OUT3U 39 2 SCD1U50V5KX D23 5V_AUX 5130_OUT3D 39 1 1 R392 20,37 1999_S5ENABLE SCD1U16V3KX R383 300KR2J 5130_LL3 39 2 5V_DC_S5 2 2 PM_SLP_S3# 1 2 3 4 5 6 7 8 9 10 11 12 C332 2 close to IC C114 SCD1U50V5KX 5130_LH2 1 5130_LL2 2 INV1 FLT LH1 OUT1_U LL1 OUT1_D OUTGND1 TRIP1 VIN_SENSE12 TRIP2 OUTGND2 OUT2_D 5 6 4 3 2 1 U51 2N7002S 5130_FB1 5130_SS_STBY1 5130_INV2 5130_FB2 5130_SS_STBY2 5130_PWM_SEL 5130_CT 5130_OUT2D 39 U23 48 47 46 45 44 43 42 41 40 39 38 37 C116 SCD01U16V3KX 1 5130_OUT2D 1 2 100KR2 5130_FLT 5130_INV1 2 1 5130_FLT 2 2 5130_TRIP3 5130_FB2 1 R360 5V_AUX G28 C345 2 5130_TRIP1 2 5V_AUX DCBATOUT 2 5130_TRIP2 5130_LL1 39 5130_OUT1U 5130_OUT1D 1 2 3 R407 1 1 5130_FB3 SB C350 SC3300P50V2KX OCP_1.8V -1 15KR3 D24 BAW56-1 2 20KR2F 1 2 1 2 11K5R2F R412 R414 2KR2F close to IC 5V_DC_S5 R397 2K7R2J 2 10K2R3F 1 1 R395 1 PWM_1D8V 2 1 680R2 2 C333 SC5600P25V2KX 2 80K6R3F 2 For 1.8V SETTING=1.8V 2 1 680R2 4 SCD1U16V3KX 2 1 R398 1 R411 PWM_1D05V 1 2 C349 SC4700P50V3KX 2 15KR3 5130_TRIP1 1 2 4 1 R415 E (1D5V=>CH1 , 1D8V=>CH2 , 1D05V =>CH3) 2 C348 SC4700P50V3KX 2 1 680R2 D TI TPS5130 for 1D8V, 1.5V, 1.05V. PWM_1D5V 1 R413 1 R416 C 3 Q25 1 DCBATOUT 5V_AUX 1 R361 17,21,28,31,37,40 BAT54-1 2 100KR2 PM_SLP_S3# 2 IN R1 5130_PWM_SEL 3 OUT 1 GND R2 DTC115EE-U 5130_TRIP3 1 4 5 6 3D3V_S0 U53 2N7002S R170 10KR2 1 14 1 3D3V_S0 U37A 3 2 1 2 Wistron Corporation 1 20 VCCP_PWGD 3 PM_SLP_S3# 2 1 7 5130_SS_STBY3 2 PM_SLP_S3# CPU_SHDN# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 36 TSLCX08-U Title DC/DC 2D5V/1D5V/1D05V C335 SC1500P50V3KX Size A3 HW Thermal Throttling Document Number Date: Monday, August 15, 2005 A B C D Rev -1 Leopard 3 Sheet E 38 of 41 A B C D E TI TPS5130 for 2.5V, 1.5V, 1.05V 14,35,37,38,40,41 DCBATOUT 17,18,19,21,25,29,31,35,37,40 (1D5V=>CH1 , 2D5V=>CH2 , 1D05V =>CH3) 1D5V/5A OCP=10A 1D8V_S3 5V_S0 5V_S0 1 12 0D9V_S0 0D9V_S0 4 G S S S PWM_1D5V 1D5V_S0 PWM_1D5V 1D05V_S0 PWM_1D05V 1D5V_S5 L31 2 IND-4D7UH-56 U59 3D3V_S5 VOUT 2 GND 1 2 Rds(on)=16mOhm TC18 ST220U2VDM-1 G9131-15T73UF-GP C414 SC10U10V6ZY-U 2 D D D D 1 5 6 7 8 VIN 1 1 3 U26 IRF7807Z 1D5V_S5 1D8V_S3 1.5V_S5 (For ICH6) 5130_OUT1U 5130_LL1 5130_OUT1U 5130_LL1 5V_AUX 1D5V_S5 13,14,18,19,20,21,23,24,27,28,29,32,36,40,41 C129 SC4D7U25V6KX-L 4 3 2 1 38 38 7,9,10,11,12,38,40,41 D D D D 2 5 6 7 8 C128 SCD1U 2 1 DCBATOUT U27 SI4800BDY 3D3V_S5 14,15,35,37,38 5V_AUX 18 4 DCBATOUT 3D3V_S5 4 3 2 1 S S S G Imax=300mA 5130_OUT1D 38 5130_OUT1D PWM_1D8V 1D8V_S3 3 3 DCBATOUT Power budget:0D9V/2.2Apeak (For DDR2_VTT) 1 1 2 5 6 7 8 C113 SC4D7U25V6KX-L D D D D C367 SC10U10V5ZY-L 2 U22 SI4800BDY 2 1 1D8V_S3 C112 SCD1U 1D8V_S3 5V_S0 4 3 2 1 0D9V_S0 PWM_1D8V 2 2 IND-4D7UH-56 VIN VREF VCNTL 1 3 6 GND GND 2 9 APL533_VREF1 2 4 3 2 1 R447 C368 1KR2F SCD1U10V2MX-1 2 DY APL5331KAC-TR 1 G S S S 1 U52 R363 1MR2F 1 2 3 HTH GND LTH VCC 5 RESET#/RESET 4 D20 2 3 1 2 HTH 1D05V/5A OCP=10A L3# at 8.13V BAT54-1 R364 6K04R2F BL3# 1 tm ai R323 174KR2F ho Title B C D Leopard 3 Sheet E f@ Date: Thursday, August 18, 2005 Rev of 41 in Document Number -1 xa 2 39.DC/DC 1D8V/1D5V/1D05V-2 Size A3 A om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. l.c 2 2 HTH 4 3 2 1 S S S G DY TC5 ST220U4VDM-10 1 R73 1KR2 2 1 D D D D 1 37 5130_OUT3D 5130_OUT3D RSMRST# 16,20,31 G680LT1 1 L27 2 IND-4D7UH-56 5 6 7 8 1 Rds(on)=16mOhm 38 C293 SCD1U10V2MX-1 2 1 1 2 DCBATOUT C76 SC4D7U25V6KX-L D D D D 2 5 6 7 8 C75 SCD1U 4 3 2 1 5130_OUT3U 5130_LL3 U15 IRF7807Z 1 2 5V_AUX PWM_1D05V 38 5130_OUT3U 38 5130_LL3 R446,R447 for 1G Memory L3# circuit DCBATOUT U18 SI4800BDY 40 ST330U3VDM-1-GP 5130_OUT2D 5130_OUT2D DDR_VREF_1 he 38 2 0R2-0 2 S S S G TC17 2 1 R133 1 NC NC NC 2 1 1 VOUT 1 2 SE220U16VM-U Rds(on)=16mOhm TC20 8 ST150U4VBM-L17 5 SC10U10V5ZY-L C460 2 TC8 1 4 1 L29 5 6 7 8 1 D D D D U21 IRF7807Z R446 C376 1KR2F SCD1U10V2MX-1 U58 2 5130_OUT2U 5130_LL2 38 5130_OUT2U 38 5130_LL2 1 G S S S 1 0D9V / 1A 39 A B C D E 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,41 3D3V_S0 3D3V_S0 13,14,30 3D3V_S3 3D3V_S3 17,18,19,21,25,29,31,35,37,39 FOR GMCH Power 3D3V_S5 13,14,18,19,20,21,23,24,27,28,29,32,36,39,41 5V_S0 5V_S3 5V_S3 14,18,20,36,38 5V_S5 5V_S5 13,14,26,28,30,32,37,38,41 G27 1 2 7,9,15,18 2D5V_S0 GAP-CLOSE-PWR 4 CORE_GMCH_S0 2 1D05V_S0 1D8V_S3 1D8V_S3 7,11 DDR_VREF_S3 GAP-CLOSE-PWR 14,35,37,38,39,41 G25 1 2D5V_S0 4 7,9,10,11,12,38,39,41 G26 1 3D3V_S5 5V_S0 DDR_VREF_S3 DCBATOUT DCBATOUT 38,39,41 1D05V_S0 2 4,5,6,7,9,10,16,18,36,41 GAP-CLOSE-PWR 1D05V_S0 VCCP_GMCH_S0 VCCP_GMCH_S0 6,9,10,41 CORE_GMCH_S0 CORE_GMCH_S0 G14 1 2 GAP-CLOSE-PWR 1D8V_S3 G15 2 5V_S3 GAP-CLOSE-PWR 2 G16 C183 SCD1U16V3KX R130 220R3F 1 2 C206 SCD1U16V 2 R132 220R3F IN+ VSS ING1214 VDD 5 OUT 4 DDR_VREF_S3 3 DY 2 C184 SCD1U16V3KX 1 2 3 2 2 3 1 1 39 DDR_VREF_1 1 GAP-CLOSE-PWR DDR_VREF_S3 need 10 mil and must neat NB and DIMM U31 2 1 1 1D05V_S0 1 1 VCCP_GMCH_S0 1 R131 C167 SCD1U16V VREFOUT = 0.9V 2 0R3-U FOR DDR 2 Power Q27 TP0610K-U Run Power 5V_S0 3 Suspend Power 5V_S3 S D 2 DCBATOUT U20 1 2 1 2 2 330KR2 C369 SCD22U50V5KX 8 7 6 5 3D3V_S3 AO4422 D27 MMGZ5242B 3D3V_S0 2 3D3V_S5 2 R95 1 0R3-U 3D3V_S5 U56 1 1 1 R436 1KR2 RB5 100R2 G S S S 1 2 3 4 D D D D 1 R438 1 2 3 4 PWR_S0_CTL G S S S 2 10KR2 D D D D 1 R437 G 2 8 7 6 5 D Q28 2N7002-F-GP D 2 2 AO4422 QB5 2N7002-F-GP G S 2 3D3V_S0 R448 100KR2 2D5V_S0 U69 1 2 APL5308-25AC-TR 3 1 2 C467 SCD1U10V2MX-1 1 2 VOUT VIN GND 1 1 Wistron Corporation 1 G PM_SLP_S3# S 17,21,28,31,37,38 C468 SC10U6D3V5MX 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title PWRPLANE&RESETLOGIC Size A3 Document Number Date: Tuesday, July 12, 2005 A B C D Rev -1 Leopard 3 Sheet E 40 of 41 A B C D E AD+ 2 2 DY DY DY 1 EC4 2 2 2 2 2 2 2 2 2 2 2 2 EC5 DY VCCP_GMCH_S0 4 BT+ EC7 EC118 1 EC96 1 EC9 EC111 EC134 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 3D3V_LAN_S5 2 EC30 SCD1U16V 2 2 2 2 2 2 2 EC119 EC26 EC28 EC27 EC25 EC24 EC117 EC122 EC116 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 2 TSAHCT86 EC32 EC21 SCD1U16V 2 2 TSAHCT32 7 7 2 1 11 13 AUD_AGND 1D8V_S3 1 2 2 2 2 2 2 2 2 2 2 1D05V_S0 12 11 13 2 2 EC78 SCD1U16V 2 EC97 1 EC15 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 1 EC13 1 EC6 1 EC2 1 EC107 1 EC73 1 1 EC128 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 2 12 EC75 1 EC171 U40D 14 14 U61D 1 5V_AUDIO_S0 5V_S0 1 1 5V_S0 2 EC169 EC160 EC161 EC162 EC163 EC164 EC52 EC91 2 EC14 SCD1U25V3KX SCD1U16V SCD1U25V3KXSCD1U25V3KXSCD1U25V3KXSCD1U25V3KX SCD1U16V SCD1U25V3KXSCD1U25V3KXSCD1U25V3KXSCD1U25V3KX 1 1 1 1 EC168 EC104 1 1 1 1 1 1 1 1 1 AUD_AGND 1 AUD_AGND EC77 SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX AUD_AGND AUD_AGND 1 EC3 4 AUD_AGND 1 EC81 2 EC90 1 EC109 1 EC76 1 1 EC106 1 EC108 EC99 1 EC105 1 1 1 EC129 1 DY DY 2 2 2 2 DY DY EC74 2 EC151 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V EC98 DCBATOUT SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SC1000P50V SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX 2 1 EC158 2 EC136 EC145 1 1 1 1 1 1 1 EC157 SCD1U16V 2 EC132 SCD1U16V 2 1 EC79 EC35 EC125 1 1 DCBATOUT 1 DCBATOUT_BEAD AUD_AGND 1 DY DY 1 2 1 1 2 2 2 2 2 2 1 1 1 1 DY DY DY 1 1 1 2 2 2 2 2 DY 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 5V_S3 2 EC23 SCD1U16V DY DY DY DY DY DY DY DY DY EC68 1 1 EC40 EC63 SCD1U16V EC69 DY DY 2 2 SCD1U16V SCD1U16V SCD1U16V 2 2 EC37 SCD1U16V 1 5V_S0 1 1 EC142 SCD1U16V 2 EC54 SCD1U16V 2 2 EC49 SCD1U16V 1 5V_S0 1 1 EC60 SCD1U16V 2 1 EC61 SCD1U16V DY DY EC121 EC135 1 EC149 1 EC146 1 1 EC34 EC114 1 2 2 2 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 2 2 2 2 2 2 EC126 SCD1U16V SCD1U16V 1 EC148 2 EC33 1 1 EC10 1 1 1 EC115 SCD1U16V SCD1U16V SCD1U16V SCD1U16V 2 H24 HOLE DY 1D5V_S0 1 1 1 1 1 2 1 1 2 2 2 2 2 2 SCD1U25V3KXSCD1U16V SCD1U16V SCD1U16V H25 HOLE EC133 H18 DY 1 1 1 1 H20 HOLE 1 1 1 1 H22 HOLE DY DY 2 1 H23 HOLE DY DY H3 HOLE DY EC46 SCD1U16V EC66 EC72 EC64 EC29 EC51 EC38 EC45 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 1 1 H21 HOLE DY 1 1 H16 HOLE H2 HOLE DY 5V_S0 1 1 H4 HOLE DY 1 1 H7 HOLE H9 DY CORE_GMCH_S0 1 1 H6 HOLE H1 HOLE DY 5V_S3 EC53 EC59 SCD1U16V SCD1U16V SCD1U16V EC170 EC113 EC112 EC120 ai tm 1 ho Title MISC & EMI Date: Tuesday, July 12, 2005 A B C D E Rev 41 -1 xa Leopard 3 Sheet of in Document Number he Size A3 f@ 1 1 1 1 1 1 l.c om Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. 1 1 DY H15 HOLE 1 1 H13 HOLE 1 1 EC147 EC67 SCD1U16V DY H5 HOLE DY 2 H12 HOLE DY 1 H10 DY 2 H11 HOLE DY 5V_S3 2 H8 HOLE 2 DY K69 GNDPAD 2 K71 GNDPAD 1 K70 GNDPAD 1 1 1 H14 HOLE EC144 SCD1U16V SPRING-4 2 H17 HOLE 1 1 DY EC48 EC65 EC58 EC47 EC43 EC62 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V DY H19 EC138 SCD1U16V 3D3V_S0 1 1 1 EC139 EC131 SCD1U16V 2 SPRING-4SPRING-4 EC55 SCD1U16V 2 SPRING-4 K72 GNDPAD SPR10 2 SPRING-4 1 1 SPRING-4 EC70 SCD1U16V 1 SPR16 1 SPRING-4 1 SPRING-4 1 SPR15 1 SPR11 1 SPR17 1 SPR14 1 SPR13 EC130 SCD1U16V 1 1 DY 5V_S3 SPR12 3D3V_S0 SPRING-18-U SPRING-18-U 1 1 1 1 1 SPRING-18-U 1 EC57 EC137 EC150 EC71 EC143 EC127 EC123 EC141 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V AUD_AGND DY SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U 1 EC41 1 1 2 AUD_AGND SPR9 2 SPR1 2 SPR4 2 SPR7 2 SPR3 3D3V_S0 3 EC50 SCD1U16V 2 SPR2 3D3V_S0 EC155 SCD1U16V 2 SPR8 EC140 SCD1U16V 2 2 3 1 1 3D3V_S0 41
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