S13 Block Diagram

5
4
3
2
S13 Block Diagram
DDRII Slot 0
8
667/800
DDRII 667/800 MHz Channel A
DDRII Slot 1
9
667/800
DDRII 667/800 MHz Channel B
1
CPU V_CORE
Project code
PCB Number
Revision
Thermal
& Fan
G792 21
AMD S1G2 CPU
: 91.4H801.001
: 48.4H801.0SC
: SC
INPUTS
OUTPUTS
DCBATOUT
VCC_CORE
638-Pin uFCPGA
D
SYSTEM DC/DC
TPS51124
4,5,6,7
CLK GEN
ICS9LPR480
16X16
3
1D8V_S3
DDRII
(32MB)12
SYSTEM DC/DC
Power SW
G577
ATi RS780M
10
OUTPUTS
1D2V_S0
North Bridge
PCIE X8
INPUTS
OUTPUTS
DX10 IGP
DVI-I
5V_S5
DCBATOUT
LVDS/TVOUT/TMDS
PCIE
DISPLY PORT X2
PCIE x 1 & USB 2.0 x 1
3D3V_S5
New Card
22
Side Port Memory
C
LCD CONN
LVDS
1 X 16 PCIE I/F
14
6 X 1 PCIE I/F
802.11a/b/g/n
24
SD/MMC 24
MS/MS Pro/xD
JMB380
INPUTS
OUTPUTS
5V_S5
0D9V_S3
3D3V_S0
1D5V_S0
(e-SATA Combo+USBx1)
(USB Port x1)
(RJ45 CONN)
SYSTEM DC/DC
25
PCIE
USB 2.0 x 1
24
Ati SB700
USB Port
INPUTS
25
USB 2.0
USB 2.0 x 1
Bluetooth
Azalia
CODEC
USB 2.0 x 1
CAMERA
3D3V_S5
1D2V_S5
3D3V_S0
2D5V_S0
MIC IN
SYSTEM DC/DC
High Definition Audio
ATA 66/100
AZALIA
OUTPUTS
23
ETHERNET (10/100/1000Mb)
B
SATA
PCI/PCI BRIDGE
LINE OUT
HP OUT
W/SPDIF
INPUTS
SATA
OUTPUTS
HDD
DCBATOUT
26
3D3V_AUX_S5
PATA
16,17,18,19,20
OP AMP
G1412 28
27
SATA
ODD
MAXIM CHARGER
26
BQ24745
LPC Bus
2CH
SPEAKER
B
5V_AUX_S5
LPC I/F
ALC888
36
TPS51125
14
ACPI 1.1
LINE IN
39
LDO
South Bridge
USB 2.0/1.1 ports
Digital Array
29
Mic
22
Daughter CONN
USB 2.0 x 1
STAT & USB 2.0 x 1
PCIE
4X4
C
39
LDO
10,11,12,13
PCIE x 1
1394a
SYSTEM DC/DC
Mini-Card
PCIE x 1 & USB 2.0 x 1
1 X 4 PCIE I/F WITH SB
1394
card reader
36
TPS51125
22
HyperTransport LINK0 CPU I/F
DVI-I CONN15
D
37
DCBATOUT
Side Port
LASSO CONN
INPUTS
IN
OUT
HyperTransport
34,35
ISL6265
INPUTS
OP AMP
G1432Q
Hyper Flash
28
OUTPUTS
AD+
BT+
23
41
DCBATOUT
KBC
Winbond WPC775L
30,31
<Core Design>
A
A
LPC
DEBUG
CONN 32
SPI
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Touch
Pad 32
Int.
KB32
System Block Diagram
Flash ROM
2MB 31
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
1
of
44
5
4
3
0
USB1
1
CAMERA
1
RS780M Functional Strap Definitions
DESTINATION
USB PORT#
2
STRAP_DEBUG_BUS_GPIO_ENABLE
D
D
Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC)
0 : Enable
1 : Disable
*
Combo(ESATA/USB)
2
RS780: Enables Side port memory ( RS780 use HSYNC)
*
3
0 : Enable
1 : Disable
NEW CARD
SUS_STAT#
4
USB2
*
5
Bluetooth
6
NC
7
WLAN
Selects Loading of STRAPS From EEPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected,
or use default values if not connected
2.0
SB700
C
SB700 Functional Strap Definitions
PULL HIGH
PULL LOW
8
NC
CLK_PCI_2 WatchDOG (NB_PWRGD)
ENABLED
DISABLED
9
NC
CLK_PCI_3
DEBUG STRAPS
10
NC
CLK_PCI_1
CLK_PCI_4
RESERVED
11
NC
LPCCLK0
PCI MEM BOOT
ENABLED
DISABLED
12
NC
LPCCLK1
INTERNAL CLK GEN
ENABLED
DISABLED
13
NC
RTCCLK
INTERNAL RTC
ENABLED
DISABLED
AZ_RST#
IMC
C
DEFAULT
USB
IGNORE
DEFAULT
DEFAULT
DEFAULT
1.1
DEFAULT
ENABLED
DISABLED
DEFAULT
SB_GPO17
ROM TYPE
SB_GPO16
B
PCI EXPRESS
DESTINATION
H, L = SPI ROM
Lane 0
NEW CARD
L, L = FWH ROM
Lane 1
WLAN
Lane 2
LAN
Lane 3
CARD READER&1394
Lane 4
NC
Lane 5
NC
B
H, H = Reserved
L, H = LPC ROM
DEFAULT
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
2
of
44
5
4
3D3V_S0
3D3V_CLK_VDD
2
1
L45
BLM18AG601SN-3GP
Due to PLL issue on current clock chip, the SBlink clock
need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.
C528
2
1
3D3V_48MPWR_S0
2
SC2D2U6D3V3KX-GP
2
1
1
C533
SCD1U10V2KX-4GP
2
1
C516
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
C515
2
C511
SCD1U10V2KX-4GP
2
1
C512
SCD1U10V2KX-4GP
2
1
C514
2
C517
SCD1U10V2KX-4GP
2
1
1
1
1
C537
SCD1U10V2KX-4GP
2
1
C534
SCD1U10V2KX-4GP
2
C297
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
D
2
C314
SCD1U10V2KX-4GP
L18
BLM18AG601SN-3GP
1
3D3V_S0
2
1
1
3D3V_S0
3
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
D
1
DY 2
R325 0R3-0-U-GP
1D1V_CLK_VDDIO
1
1
C521
SC1U10V2KX-1GP
2
SC10U10V5KX-2GP
2
C739
VDD_REF
3D3V_48MPWR_S0
11 CLK_NB_GPPSB
11 CLK_NB_GPPSB#
EXPRESS CARD
22 CLK_PCIE_NEW
22 CLK_PCIE_NEW#
25 CLK_PCIE_LAN
25 CLK_PCIE_LAN#
LAN
WLAN
22 CLK_PCIE_WLAN
22 CLK_PCIE_WLAN#
CARD READER
24 CLK_PCIE_CARD
24 CLK_PCIE_CARD#
16 CLK_PCIE_SB
16 CLK_PCIE_SB#
B
2
RN21
1
SRN22-3-GP
RN22
4
SRN0J-6-GP 3
3
4
CLK_NB_GPPSB_R
CLK_NB_GPPSB#_R
1
2
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
RN25
4
SRN0J-6-GP 3
1
2
CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R
RN24
4
3
1
2
CLK_PCIE_CARD_R
CLK_PCIE_CARD#_R
2
RN23
1
SRN0J-6-GP
3
4
CLK_PCIE_SB_R
CLK_PCIE_SB#_R
SRN22-3-GP
PD#
1 CLK_PCIE_NEW_R
2 CLK_PCIE_NEW#_R
RN26
4
SRN0J-6-GP 3
NB ALINK(100MHz)
SB PCIE(100MHz)
2
RN19
1
SRN0J-6-GP
11 CLK_NBHT_CLK
11 CLK_NBHT_CLK#
VDDATIG
VDDATIG_IO
48
47
VDDCPU
VDDCPU_IO
16
17
11
VDDSRC
VDDSRC_IO
VDDSRC_IO
3
4
CLK_NBHT_CLK_R
CLK_NBHT_CLK#_R
35
34
VDDSB_SRC
VDDSB_SRC_IO
40
4
55
56
63
VDDSATA
VDDDOT
VDDHTT
VDDREF
VDD48
51
PD#
22
21
20
19
15
14
13
12
9
8
42
41
6
5
SRC0T
SRC0C
SRC1T
SRC1C
SRC2T
SRC2C
SRC3T
SRC3C
SRC4T
SRC4C
SRC6T/SATAT
SRC6C/SATAC
SRC7T/27M_SS
SRC7C/27M_NS
37
36
32
31
SB_SRC0T
SB_SRC0C
SB_SRC1T
SB_SRC1C
54
53
X1
X2
2
3
ATIG0T
ATIG0C
ATIG1T
ATIG1C
30
29
28
27
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
23
45
44
39
38
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
CPUK8_0T
CPUK8_0C
50
49
CPU_CLK_R
CPU_CLK#_R
48MZ_0
64
CLK_48
SEL_HTT66/REF0
SEL_SATA/REF1
SEL_27/REF2
59
58
57
REF0
REF1
REF2
GNDSATA
GNDATIG
GNDDOT
GNDHTT
GNDREF
GNDCPU
GND48
43
24
7
52
60
46
1
GNDSRC
GNDSRC
10
18
GNDSB_SRC
33
GND
65
1
1
REF0
REF1
REF2
SEL_HTT66
FS0
RN18
4
3 SRN0J-6-GP
3
4
2 RN20
1
SRN22-3-GP
TP30
TP27
TP26
TP24
TP25
TPAD28
TPAD28
TPAD28
TPAD28
TPAD28
1 10KR2J-3-GP
CLK_PCIE_LASSO 10
CLK_PCIE_LASSO# 10
CLK_NB_GFX 11
CLK_NB_GFX# 11
RN17
HTT0T/66M
HTT0C/66M
3
4
2
2
CLKREQ# Internal
pull high
DY
R176
261R2F-GP
2
1
SRN0J-6-GP
1
R324 33R2J-2-GP
CPU_CLK
CPU_CLK#
CPU_CLK(200MHz)
6
6
CLK48_USB 17
1 EC48
DY SC4D7P50V2CN-1GP
NB CLOCK INPUT TABLE
RS740
NB CLOCKS
B
RX780
RS780
HT_REFCLKP
66M SE(SINGLE END)
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
REFCLK_N
14M SE (3.3V)
NC
14M SE (1.8V)
NC
14M SE (1.1V)
vref
GFX_REFCLK
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
GPP_REFCLK
NC
100M DIFF
NC or 100M DIFF OUTPUT
GPPSB_REFCLK
100M DIFF
100M DIFF
100M DIFF
HT_REFCLKN
RTM880N-796-GRT-GP
SEL_SATA
FS1
1
66 MHz 3.3V single ended HTT clock
0*
100 MHz differential HTT clock
REFCLK_P
150R2F-1-GP
2
2
1R313
CLK_NB_14M 11
1 R312
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
PD#
1
1
R320
10KR2J-3-GP
SEL_27
FS2
*
1
0
<Core Design>
A
OSC_14M_NB
RS780M 1.1V 158R/90.9R
100 MHz non-spreading differential SATA clock
1
0
R315
10KR2J-3-GP
1
2
2
2
DY
CLK_NB_GFX_R
CLK_NB_GFX#_R
1
2
* default
DY
R317
10KR2J-3-GP
A
R318
10KR2J-3-GP
CLK_PCIE_LASSO_R
CLK_PCIE_LASSO#_R
2
2
2
R311
10KR2J-3-GP
1
R321
10KR2J-3-GP
SC27P50V2JN-2-GP
SMBCLK0_SB 8,9,17
SMBDAT0_SB 8,9,17
3D3V_S0
R314 2
DY
X2
C311
X-14D31818M-44GP
2
1
C
75R2F-2-GP
DY
CL=20pF±0.2pF
SMBCLK
SMBDAT
REF1
3D3V_S0
CLK_X1
CLK_X2
61
62
2
26
25
2
C
1
10MR2J-L-GP
U32
0R0603-PAD
1
2
1D1V_CLK_VDDIO
R323
3D3V_CLK_VDD
DY
1
3D3V_CLK_VDD
SCD1U10V2KX-4GP
2
C523
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
C513
2
C510
1
1
1
1
C518
2
1
C530
2
1
C536
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
2
C312
SCD1U10V2KX-4GP
L44
BLM18AG601SN-3GP
C306
SC27P50V2JN-2-GP
2
1
R180
2
1D2V_S0
2
1
1
*
100 MHz spreading differential SRC clock
27MHz non-spreading singled clock on pin 13 and
27MHz spread clock on pin 14
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Clock Gen-ICS 9LPR473
Size
A3
100MHz differential spreading SRC clock
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
3
of
44
5
4
3
2
1
D
D
1D2V_S0
DY
1
C261
(1.2V)1.5A for VLDT
2
1
2
1
2
1
2
1
2
1
2
2
C268
SC180P50V2JN-1GP
C442
SC180P50V2JN-1GP
C483
SCD22U6D3V2KX-1GP
C277
SCD22U6D3V2KX-1GP
C282
SC4D7U6D3V5KX-3GP
B
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
C
1
Place close to socket
C440
U54A
D1
D2
D3
D4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
HT LINK
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
10
10
10
10
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
J3
J2
J5
K5
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
N1
P1
P3
P4
10
10
10
10
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
Y1
W1
Y4
Y3
HT_CPU_NB_CLK_H0 10
HT_CPU_NB_CLK_L0 10
HT_CPU_NB_CLK_H1 10
HT_CPU_NB_CLK_L1 10
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
R2
R3
T5
R5
HT_CPU_NB_CTL_H0 10
HT_CPU_NB_CTL_L0 10
HT_CPU_NB_CTL_H1 10
HT_CPU_NB_CTL_L1 10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C
B
SKT-CPU638P-GP-U2
62.10055.111
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_HT_LINK I/F_(1/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
4
of
44
5
4
3
2
1
U54C
MEM:DATA
0D9V_S3
Place near to CPU
DY
0D9V_S3
1
2
1
C137
2
1
C132
2
1
C128
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
C280
SC180P50V2JN-1GP
DY
C287
SC180P50V2JN-1GP
DY
C121
SC180P50V2JN-1GP
DY
C284
SC180P50V2JN-1GP
DY
C124
SC1000P50V3JN-GP
2
1
C258
SC1000P50V3JN-GP
2
1
C273
SC1000P50V3JN-GP
2
C127
SC1000P50V3JN-GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
SC4D7U6D3V5KX-3GP
2
C266
SCD22U6D3V2KX-1GP
C120
SCD22U6D3V2KX-1GP
C118
SCD22U6D3V2KX-1GP
C291
SCD22U6D3V2KX-1GP
C289
1
D
DY
1D8V_S3
(0.9V)750mA for VTT
MEMVREF
W17
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
RSVD_M2
B18
W26
W23
Y26
MEM_MB0_ODT0 9
MEM_MB0_ODT1 9
8 MEM_MA0_CS#0
8 MEM_MA0_CS#1
T20
U19
U20
V20
MB0_ODT0
MB0_ODT1
MB1_ODT0
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
V26
W25
U22
MEM_MB0_CS#0 9
MEM_MB0_CS#1 9
8 MEM_MA_CKE0
8 MEM_MA_CKE1
J22
J20
MA_CKE0
MA_CKE1
MB_CKE0
MB_CKE1
J25
H26
MEM_MB_CKE0 9
MEM_MB_CKE1 9
MEM_MB_CLK0_P
MEM_MB_CLK0_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MEM_RSVD_M2 1
TP17
8
8
8
8
MEM_MA_CLK0_P
MEM_MA_CLK0_N
MEM_MA_CLK1_P
MEM_MA_CLK1_N
N19
N20
E16
F16
Y16
AA16
P19
P20
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
MEM_MB_ADD0 9
MEM_MB_ADD1 9
MEM_MB_ADD2 9
MEM_MB_ADD3 9
MEM_MB_ADD4 9
MEM_MB_ADD5 9
MEM_MB_ADD6 9
MEM_MB_ADD7 9
MEM_MB_ADD8 9
MEM_MB_ADD9 9
MEM_MB_ADD10 9
MEM_MB_ADD11 9
MEM_MB_ADD12 9
MEM_MB_ADD13 9
MEM_MB_ADD14 9
MEM_MB_ADD15 9
8 MEM_MA_BANK0
8 MEM_MA_BANK1
8 MEM_MA_BANK2
R20
R23
J21
MA_BANK0
MA_BANK1
MA_BANK2
MB_BANK0
MB_BANK1
MB_BANK2
R24
U26
J26
MEM_MB_BANK0 9
MEM_MB_BANK1 9
MEM_MB_BANK2 9
8 MEM_MA_RAS#
8 MEM_MA_CAS#
8 MEM_MA_WE#
R19
T22
T24
MA_RAS_L
MA_CAS_L
MA_WE_L
MB_RAS_L
MB_CAS_L
MB_WE_L
U25
U24
U23
MEM_MB_RAS# 9
MEM_MB_CAS# 9
MEM_MB_WE# 9
C130
1
2
SCD1U10V2KX-4GP
RSVD_M1
1
TP9
T19
V22
U21
V19
P22
R22
A17
A18
AF18
AF17
R26
R25
2
0D9V_S3_VREF
CPU_VTT_SUS_FB 1
C131
R145
1KR2F-3-GP
2
Y10
1
VTT_SENSE
R142
1KR2F-3-GP
2
MEM_RSVD_M1
MEMZP
MEMZN
SC1000P50V3JN-GP
1
AF10
AE10
SCD1U10V2KX-4GP
H16
8 MEM_MA0_ODT0
8 MEM_MA0_ODT1
B
MEMZP
MEMZN
C152
W10
AC10
AB10
AA10
A10
1
1D8V_S3
MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
VTT8
VTT9
2
C
R127
39D2R2F-L-GP
1
2
1
2
R126
39D2R2F-L-GPTP14
VTT1
VTT2
VTT3
VTT4
1
U54B
D10
C10
B10
AD10
9
9
9
9
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
8
8
8
8
8
8
8
8
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
E12
C15
E19
F24
AC24
Y19
AB16
Y13
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
MEM_MB_DATA0 9
MEM_MB_DATA1 9
MEM_MB_DATA2 9
MEM_MB_DATA3 9
MEM_MB_DATA4 9
MEM_MB_DATA5 9
MEM_MB_DATA6 9
MEM_MB_DATA7 9
MEM_MB_DATA8 9
MEM_MB_DATA9 9
MEM_MB_DATA10 9
MEM_MB_DATA11 9
MEM_MB_DATA12 9
MEM_MB_DATA13 9
MEM_MB_DATA14 9
MEM_MB_DATA15 9
MEM_MB_DATA16 9
MEM_MB_DATA17 9
MEM_MB_DATA18 9
MEM_MB_DATA19 9
MEM_MB_DATA20 9
MEM_MB_DATA21 9
MEM_MB_DATA22 9
MEM_MB_DATA23 9
MEM_MB_DATA24 9
MEM_MB_DATA25 9
MEM_MB_DATA26 9
MEM_MB_DATA27 9
MEM_MB_DATA28 9
MEM_MB_DATA29 9
MEM_MB_DATA30 9
MEM_MB_DATA31 9
MEM_MB_DATA32 9
MEM_MB_DATA33 9
MEM_MB_DATA34 9
MEM_MB_DATA35 9
MEM_MB_DATA36 9
MEM_MB_DATA37 9
MEM_MB_DATA38 9
MEM_MB_DATA39 9
MEM_MB_DATA40 9
MEM_MB_DATA41 9
MEM_MB_DATA42 9
MEM_MB_DATA43 9
MEM_MB_DATA44 9
MEM_MB_DATA45 9
MEM_MB_DATA46 9
MEM_MB_DATA47 9
MEM_MB_DATA48 9
MEM_MB_DATA49 9
MEM_MB_DATA50 9
MEM_MB_DATA51 9
MEM_MB_DATA52 9
MEM_MB_DATA53 9
MEM_MB_DATA54 9
MEM_MB_DATA55 9
MEM_MB_DATA56 9
MEM_MB_DATA57 9
MEM_MB_DATA58 9
MEM_MB_DATA59 9
MEM_MB_DATA60 9
MEM_MB_DATA61 9
MEM_MB_DATA62 9
MEM_MB_DATA63 9
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
A12
B16
A22
E25
AB26
AE22
AC16
AD12
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N
9
9
9
9
9
9
9
9
D
C
B
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_DDR_(2/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
5
of
44
5
4
3
1D8V_S0
2
1
8
7
6
5
LYAOUT:ROUTE VDDA TRACE APPROX.
50mils WIDE(USE 2X25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
RN31
SRN300J-1-GP
2D5V_S0
1
CLKIN_H
CLKIN_L
LDT_RST#_CPU
B7
LDT_PWROK
A7
LDT_STP#_CPU
F10
CPU_LDT_REQ#_CPU C6
1D8V_S3
R1341
2
R133 1
CPU_SIC
390R2J-1-GP
2
390R2J-1-GP
TP51
1D2V_S0
CPU_SID
CPU_HTREF0
2
2 44D2R2F-GP CPU_HTREF1
44D2R2F-GP
1
R1461
R147
C
1
D
W7
W8
VDD1_FB_H
VDD1_FB_L
VDDNB_FB_H
VDDNB_FB_L
H6
G6
G10
AA9
AC9
AD9
AF9
DBRDY
TMS
TCK
TRST_L
TDI
CPU_TEST23
AD7
TEST23
CPU_TEST18
CPU_TEST19
H10
G9
TEST18
TEST19
G
1
CPU_TEST25_H
CPU_TEST25_L
1
1
FDV301N-NL-GP
Q10
CPU_TEST21
CPU_TEST20
CPU_TEST24
CPU_TEST22
CPU_TEST12
CPU_TEST27
For HDT DBG
1
CPU_TEST9
2
R302
0R2J-2-GP
3D3V_S5
THERMDC
THERMDA
Y6
AB6
TP21
TP23
B
HT_REF0
HT_REF1
34 CPU_VDD1_RUN_FB_H
34 CPU_VDD1_RUN_FB_L
LDT_RST#_CPU
S
R6
P6
VDDIO_FB_H
VDDIO_FB_L
TP50
D
SIC
SID
ALERT_L
VDD0_FB_H
VDD0_FB_L
2
HDT_RST#
AF4
AF5
AE6
AF6
AC7
AA8
THERMTRIP_L
PROCHOT_L
MEMHOT_L
34 CPU_VDD0_RUN_FB_H
34 CPU_VDD0_RUN_FB_L
1
R308
10KR2J-3-GP
RESET_L
PWROK
LDTSTOP_L
LDTREQ_L
W9
Y9
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
E9
E8
CPU_SVC
CPU_SVD
1
1
2
2
1
2
1
2
R301
1KR2F-3-GP
A6
A4
SVC
SVD
F6
E6
1D8V_S0
3D3V_S0
CPU_SIC
CPU_SID
CPU_ALERT#
R299
1KR2F-3-GP
M11
W18
KEY1
KEY2
R122
2K2R2F-GP
C112
1
2
34
34
SCD1U16V2ZY-2GP
B
A9
A8
1
1
CLKCPU_IN
CLKCPU#_IN
VDDA1
VDDA2
R116
300R2J-4-GP
1
2
R294
169R2F-GP
2
2SC3900P50V2KX-2GP
SC3900P50V2KX-2GP
U54D
F8
F9
R130
300R2J-4-GP
1
C5051
C506
CPU_CLK
CPU_CLK#
R131
300R2J-4-GP
3
3
1D8V_S3
1
LDT_STP#_CPU 11
D
LDT_PWROK
C242
2
R300
1
C241
2
11 CPU_LDT_REQ#
1
C288
2
R295
1D8V_S3
(2.5V)250mA for VDDA
SC3300P50V2KX-1GP
16 CPU_LDT_STOP#
1
+2.5V_RUN_VDDA
L15
BLM18PG330SN1D-GP
1
2
SCD22U6D3V2KX-1GP
R296
0R0402-PAD
LDT_PWROK
2
0R0402-PAD
2
0R0402-PAD
CPU_LDT_REQ#_CPU
2
0R0402-PAD
LDT_RST#_CPU 11
SC4D7U6D3V5KX-3GP
16 CPU_PWRGD
2
2
R297
1
1
16 CPU_LDT_RST#
2
1
2
3
4
D
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
AA6
TEST9
TEST6
A3
A5
B3
B5
C1
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
E
CPU_PROCHOT#_L
1
Q8
MMBT3904-3-GP
C
CPU_THERMTRIP#_L 17
CPU_PROCHOT# 16
2
R129
0R2J-2-GP
H_THERMDC
H_THERMDA
1DY 2
C133
SC100P50V2JN-3GP
CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
CPU_VDDNB_RUN_FB_H
CPU_VDDNB_RUN_FB_L
21
21
The Processor has
reached a preset
maximum operating
temperature. 100℃
I=Active HTC
O=FAN
TP8
TP6
1
1
34
34
AE9 CPU_TDO
TDO
TEST28_H
TEST28_L
J7
H8
CPU_TEST28_H 1
CPU_TEST28_L 1
TP13
TP15
TEST17
TEST16
TEST15
TEST14
D7
E7
F7
C7
CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
1
1
TP22
TP19
TEST7
TEST10
C3
K8
TEST8
C4
TEST29_H
TEST29_L
C9
C8
CPU_TEST29H
CPU_TEST29L
1
1
TP20
TP18
LAYOUT: Route FBCLKOUT_H/L
differentially impedance 80
HDT Connectors
H18
H19
AA7
D5
C5
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
1
1
R170
10KR2J-3-GP
LDT_PWROK
H
2
D
D
D
D
2
1D8V_S3
CPU_PWRGD_SVID_REG
L
G
34
CPU_DBREQ# R344 1
CPU_TEST27 R124 1
H
CPU_TEST12
CPU_TEST15
CPU_TEST14
CPU_TEST18
CPU_TEST19
CPU_TEST21
CPU_TEST20
CPU_TEST22
CPU_TEST24
Q11
FDV301N-NL-GP
G
S
S
Q9
FDV301N-NL-GP
R139
R162
R160
R303
R304
R128
R136
R138
R137
1
1
1
1
1
1
1
1
1
DY
DY
DY
DY
DY
DY
DY
DY
2 300R2J-4-GP
2 300R2J-4-GP
2
2
2
2
2
2
2
2
2
3
5
7
9
11
13
15
17
19
21
23
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
R171
10KR2J-3-GP
LDT_PWROK#
1D8V_S3
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
300R2J-4-GP
2
DY
4
6
8
10
12
14
16
18
20
22
24
26
SMC-CONN26A-FP
20.F0357.025
HDT_RST#
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_Control&Debug_(3/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
B
HDT1
1
3D3V_S0
SKT-CPU638P-GP-U2
FDV301N, the Vgs is:
min = 0.65V
Typ = 0.85V
Max = 1.5V
C
E10 CPU_DBREQ#
DBREQ_L
TEST25_H
TEST25_L
AB8
AF7
AE7
AE8
AC8
AF8
CPU exceeds to 125℃
2
Rev
S13
SC
Sheet
1
6
of
44
5
4
3
2
1
D
D
U54F
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
+VCC_CORE0
36A for VDD0&VDD1
Bottom Side Decoupling
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
SC4D7U6D3V3KX-GP
1
SC4D7U6D3V3KX-GP
2
SC4D7U6D3V3KX-GP
1
SC4D7U6D3V3KX-GP
2
SCD22U6D3V2KX-1GP
1
SCD22U6D3V2KX-1GP
2
SC22U6D3V5MX-2GP
SCD22U6D3V2KX-1GP
B
SC22U6D3V5MX-2GP
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
SC180P50V2JN-1GP
DY DY
SC180P50V2JN-1GP
SC22U6D3V5MX-2GP
C149 C234 C230 C212 C190 C169
SCD22U6D3V2KX-1GP
SKT-CPU638P-GP-U2
C182 C144 C181 C174 C150 C202 C229 C209 C163 C175 C193
SCD01U50V2KX-1GP
(1.8V)2A for VDDIO
Bottom Side Decoupling
1D8V_S3
Place near to CPU
SCD01U50V2KX-1GP
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
C
SC180P50V2JN-1GP
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
C122 C146 C147 C162 C153 C161 C160
SC22U6D3V5MX-2GP
SC180P50V2JN-1GP
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2
SC22U6D3V5MX-2GP
SCD01U50V2KX-1GP
C205
K16
M16
P16
T16
V16
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
SC22U6D3V5MX-2GP
SCD22U6D3V2KX-1GP
C194
SC22U6D3V5MX-2GP
1D8V_S3
SC22U6D3V5MX-2GP
C176
VDD0_1
VDD0_2
VDD0_3
VDD0_4
VDD0_5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
SCD22U6D3V2KX-1GP
SC22U6D3V5MX-2GP
(0.8~1.1V)3A for VDDNB
G4
H2
J9
J11
J13
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
Bottom Side Decoupling
SCD01U50V2KX-1GP
SC22U6D3V5MX-2GP
CPU_VDDNB
+VCC_CORE1
U54E
SC180P50V2JN-1GP
2
1
C216 C222 C220 C221 C179 C185 C208
SC22U6D3V5MX-2GP
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
SC22U6D3V5MX-2GP
B
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
SC22U6D3V5MX-2GP
C
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
SKT-CPU638P-GP-U2
DY
DY
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_Power_(4/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
7
of
44
5
4
3
2
1
DIMM1 (A0)
A
0D9V_S3
DIMM2 (A4)
A B
CN10
F25
F26
G25
G26
H25
H26
J25
J26
K25
K26
L25
L26
M25
M26
N25
N26
P25
P26
R25
R26
T25
T26
U25
U26
V25
V26
W25
W26
W17
W22
W21
W23
W18
W24
V17
V19
V21
V22
V18
V23
V24
V20
U23
U22
U21
U19
U24
U18
U17
U20
T24
T20
T18
W15
W16
T19
V16
W14
T17
V15
W13
T21
U16
V14
T22
U15
V13
T23
R17
R18
R20
R19
T16
U14
R22
R21
T15
U13
R23
R16
T13
T14
R24
P22
W11
W12
P18
V12
P17
V11
P21
U12
P24
U11
P20
T12
V10
P23
T11
V9
P19
R11
U9
U10
P16
P11
T10
W9
T9
W10
R9
W7
W8
W2
W6
W5
W4
W3
W1
R10
V5
V6
P10
V3
V4
P9
V1
V2
V8
U6
V7
U5
U7
U3
U4
U8
U1
U2
T7
T6
T8
T5
R7
T4
R8
T3
P7
T1
T2
P8
R4
R6
AC25
AC26
AD25
AD26
AE25
AF22
AF23
AF24
AA26
AB26
AA25
AB25
Y25
Y26
AF17
AF18
AF19
AF20
AE24
AF21
AE23
AE18
AE22
AE17
AE19
AD24
AE21
AD22
AD23
AE20
AC24
AD20
AC23
AD18
AC22
AD17
AC21
AD21
AC19
AC20
AD19
AB22
AC17
AB21
AC18
AB19
AB18
AB17
AB20
AB24
AB23
AA24
AA18
AA17
AA22
AF16
AA21
AF15
AA20
AE16
AA19
AE15
AA23
AD16
Y22
AD15
Y21
AC16
Y17
AC15
Y20
AB16
Y19
AB15
Y18
AA16
AF14
Y24
AA15
AF13
Y23
Y16
AE14
AF9
Y15
AE13
AF8
AD13
AD14
AF7
AC13
AF12
AC14
AF11
AB13
AE12
AB14
AE11
AA14
AD12
AA13
AD11
Y13
AC12
Y14
AC11
AF5
AB12
AF4
AF6
AB11
AE9
AA12
AD9
AA11
AC9
Y11
AB9
Y12
AA9
AE2
AE5
AE3
AE4
AF10
AE7
AE8
AE10
AD8
AD10
AD7
AC10
AC8
AB10
AC7
AA10
AB8
Y9
AB7
Y10
AA8
AE6
AA7
AD6
AD1
AC6
AD3
AB6
AD5
AB5
AD4
AB4
AD2
AB2
AB3
AC4
AA6
AC1
AA5
AC2
AA4
AC3
AA2
AA3
AC5
Y5
Y6
AB1
Y4
AA1
Y3
Y1
Y2
1
2
C111
SC2D2U6D3V3KX-GP
1
2
210KR2J-3-GP
10KR2J-3-GP
2
3D3V_S0
1
R1231
R117
MEM_MA_BANK0 5
MEM_MA_WE# 5
MEM_MA_ADD3 5
MEM_MA_ADD1 5
SRN47J-4-GP
RN15
8
7
6
5
MEM_MA_ADD15 5
MEM_MA_CKE0 5
MEM_MA_BANK2 5
MEM_MA_CKE1 5
1
2
3
4
SRN47J-4-GP
RN5
8
7
6
5
MEM_MA0_ODT1 5
MEM_MA0_CS#1 5
MEM_MA_CAS# 5
MEM_MA_ADD10 5
1
2
3
4
SRN47J-4-GP
RN2
8
7
6
5
MEM_MA0_CS#0 5
MEM_MA_RAS# 5
MEM_MA0_ODT0 5
MEM_MA_ADD13 5
1
2
3
4
SRN47J-4-GP
RN13
8
7
6
5
MEM_MA_ADD8 5
MEM_MA_ADD5 5
MEM_MA_ADD9 5
MEM_MA_ADD12 5
1
2
3
4
SRN47J-4-GP
RN11
8
7
6
5
MEM_MA_ADD14 5
MEM_MA_ADD11 5
MEM_MA_ADD7 5
MEM_MA_ADD6 5
1
2
3
4
TPAD60 TPAD60
TP53
TP52
C114
SCD1U10V2KX-4GP
(A0)
1D8V_S3
1
2
1
PARALLEL TERMINATION
C198
Put decap near power(0.9V) and pull-up resistor
Do not share the Term resistor between
the DDR addess and Control Signals.
MEM_MA_CLK1_P
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
B
1
C170
2
1
1
2
SCD1U16V2KX-3GP
2
1
C180
SCD1U10V2KX-4GP
2
1
C200
SCD1U10V2KX-4GP
2
1
C274
SCD1U10V2KX-4GP
2
1
C256
SCD1U10V2KX-4GP
2
C246
SCD1U10V2KX-4GP
DY
2
1
1
C235
SCD1U10V2KX-4GP
2
1
C214
SCD1U16V2KX-3GP
2
1
1
C248
SCD1U10V2KX-4GP
2
C213
SCD1U10V2KX-4GP
2
C158
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
C279
1
C223
1
C173
2
2
1
DY
C126
SC1D5P50V2CN-1GP
MEM_MA_CLK1_N
0D9V_S3
DY
DDR_VREF
1D8V_S3
VREF_DDR_MEM
0D9V_S3
C301
SCD1U10V2KX-4GP
2
2
1
1
R178
1KR2F-3-GP
TP58
2
TPAD60
1
C300
SCD1U10V2KX-4GP
C304
SC1KP50V2KX-1GP
2
2
R177
1KR2F-3-GP
2
TP57
1
1
TPAD60
DDR2-200P-22-GP-U2
LAYOUT: Locate close to DIMM
HI 9.2mm
Place C2.2uF and 0.1uF <
500mils from DDR connector
1D8V_S3
1 DY2
C166
SCD1U10V2KX-4GP
1 DY2
C269
SCD1U10V2KX-4GP
1 DY2
C231
SCD1U10V2KX-4GP
1 DY2
C224
SCD1U10V2KX-4GP
1 DY2
C253
SCD1U10V2KX-4GP
1 DY2
C196
SCD1U10V2KX-4GP
1 DY2
C167
SCD1U10V2KX-4GP
1 DY2
C257
SCD1U10V2KX-4GP
1
2
C498
SCD1U10V2KX-4GP
1
2
C228
SCD1U10V2KX-4GP
A
1
2
C243
SCD1U10V2KX-4GP
<Core Design>
Wistron Corporation
1
2
C482
SCD1U10V2KX-4GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR_DIMM1
Size
Custom
Date:
5
C
2
1
C454
2
1
2
1
2
1
2
1
2
2
1
2
1
2
C493
D
SRN47J-4-GP
SC180P50V2JN-1GP
C265
SCD01U50V2KX-1GP
C302
SC180P50V2JN-1GP
C294
SCD01U50V2KX-1GP
C502
SC2D2U6D3V3KX-GP
C296
SC1D5P50V2CN-1GP
MEM_MA_CLK0_N
C456
SC2D2U6D3V3KX-GP
MEM_MA_CLK0_P
C276
SC2D2U6D3V3KX-GP
TPAD60
SC2D2U6D3V3KX-GP
SC2D2U6D3V3KX-GP
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
1
Decoupling Capacitor
Place these Caps near DM1
1D8V_S3
TP54
MEM_MA_ADD0 5
MEM_MA_ADD2 5
MEM_MA_ADD4 5
MEM_MA_BANK1 5
SRN47J-4-GP
RN7
8
7
6
5
B
SMBDAT0_SB 3,9,17
SMBCLK0_SB 3,9,17
DIMM1_SA0
DIMM1_SA1
8
7
6
5
1
2
3
4
E26
E25
N19
N18
N17
N20
N22
N24
N21
N23
M19
M17
M18
M22
M21
M24
M20
M23
L19
L24
L20
L22
L18
L17
L21
L23
K20
K18
K19
K23
N16
K17
M16
K24
L16
K22
L15
K21
K16
L14
N11
J22
K15
L13
M11
N10
J24
J16
L12
N9
J23
J15
K13
K14
L11
M9
M10
J19
J14
K12
L10
J20
J13
K11
L9
J18
J12
K10
J17
J11
K9
N7
N8
J21
J10
M7
M8
R1
R2
R3
R5
P3
P6
P2
P4
P1
P5
REVERSE TYPE
D26
H24
J9
L7
L8
N6
N2
K8
N5
K7
N3
N4
J7
M6
J8
M5
N1
M3
M4
M2
L4
L5
M1
L2
L3
1
D25
H23
H20
H22
H19
H21
H18
G22
G24
H17
G21
G23
G17
F23
G18
F22
H15
H16
F19
G16
H14
F21
G15
H13
F17
F15
F16
G13
G14
F24
F14
H11
H12
F20
F13
G11
G12
F18
F12
H10
H9
F11
G9
G10
H8
F9
H7
F10
F7
F8
L6
K3
L1
K4
K5
K2
K1
K6
J4
J6
BGA638_50_26SQ_S1G2_OEM
J5
J1
1
C26
E23
E24
E20
E22
E21
E17
E19
E18
E15
E16
E13
E14
E11
E12
E10
E9
E8
E7
H5
H6
H4
G5
G6
G4
F5
F4
H2
H3
F6
G3
2
C25
D23
B25
D22
D17
D21
D24
D19
D20
D18
C19
C22
C17
C21
C18
C20
C23
C24
B17
B23
B22
B19
B21
B24
B20
B18
D16
A24
D15
A20
C16
A19
C15
D13
D14
A18
B15
B16
C13
C14
A23
A16
B14
A22
A15
B13
A21
A14
A17
A13
D9
D10
D12
C10
D8
D11
C9
D7
C12
B10
C8
C11
B9
C7
B12
A10
B8
B11
A9
B7
A11
A8
E5
E6
E4
G2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
5
5
5
5
5
5
5
5
A12
A7
D5
D6
D4
C5
C6
C4
B6
G1
H1
F1
81
82
87
88
95
96
103
104
111
112
117
118
MH2
1
2
F2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
MH2
OTD0
OTD1
F3
50
69
83
120
163
MH1
114
119
E1
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
MH1
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
D1
198
200
201
13
31
51
70
131
148
169
188
SCD1U16V2KX-3GP
199
SA0
SA1
GND
MEM_MA_DQS0_P
MEM_MA_DQS1_P
MEM_MA_DQS2_P
MEM_MA_DQS3_P
MEM_MA_DQS4_P
MEM_MA_DQS5_P
MEM_MA_DQS6_P
MEM_MA_DQS7_P
SC2D2U6D3V3KX-GP
VDDSPD
GND
5
5
5
5
5
5
5
5
B4
195
197
B5
SDA
SCL
A6
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
A4
MEM_MA_CLK1_P 5
MEM_MA_CLK1_N 5
10
26
52
67
130
147
170
185
A5
164
166
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
J3
CK1
CK1#
J2
MEM_MA_CLK0_P 5
MEM_MA_CLK0_N 5
E2
MEM_MA_CKE0 5
MEM_MA_CKE1 5
30
32
E3
79
80
CK0
CK0#
D2
CKE0
CKE1
VREF
VSS
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
C303
MEM_MA0_CS#0 5
MEM_MA0_CS#1 5
202
11
29
49
68
129
146
167
186
C299
110
115
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEM_MA_DQS0_N
MEM_MA_DQS1_N
MEM_MA_DQS2_N
MEM_MA_DQS3_N
MEM_MA_DQS4_N
MEM_MA_DQS5_N
MEM_MA_DQS6_N
MEM_MA_DQS7_N
VREF_DDR_MEM
CS0#
CS1#
D3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
5
5
5
5
5
5
5
5 MEM_MA0_ODT0
5 MEM_MA0_ODT1
A
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
MEM_MA_RAS# 5
MEM_MA_WE# 5
MEM_MA_CAS# 5
C3
B
BA0
BA1
108
109
113
C1
C
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
107
106
RAS#
WE#
CAS#
C2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
B3
5 MEM_MA_BANK2
5 MEM_MA_BANK0
5 MEM_MA_BANK1
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
A3
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
A1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
D
RN6
1
2
3
4
4
3
2
Document Number
Rev
S13
SC
Friday, May 16, 2008
Sheet
1
8
of
44
5
4
3
2
1
DIMM1
MEM_MB_BANK2 5
MEM_MB_CKE0 5
MEM_MB_ADD15 5
MEM_MB_CKE1 5
SRN47J-4-GP
RN14
8
7
6
5
MEM_MB_ADD14 5
MEM_MB_ADD11 5
MEM_MB_ADD7 5
MEM_MB_ADD6 5
1
2
3
4
SRN47J-4-GP
RN4
8
7
6
5
MEM_MB0_ODT1 5
MEM_MB0_CS#1 5
MEM_MB_WE# 5
MEM_MB_CAS# 5
1
2
3
4
SRN47J-4-GP
RN3
8
7
6
5
MEM_MB0_CS#0 5
MEM_MB_RAS# 5
MEM_MB0_ODT0 5
MEM_MB_ADD13 5
C
MEM_MB_CLK1_P
1D8V_S3
0D9V_S3
1 DY2
C171
SCD1U10V2KX-4GP
1 DY2
C199
SCD1U10V2KX-4GP
1 DY2
C250
SCD1U10V2KX-4GP
1 DY2
C168
SCD1U10V2KX-4GP
1 DY2
C227
SCD1U10V2KX-4GP
1 DY2
C254
SCD1U10V2KX-4GP
1 DY2
C157
SCD1U10V2KX-4GP
1 DY2
C275
SCD1U10V2KX-4GP
Decoupling Capacitor
1
C239
1
2
C503
SCD1U10V2KX-4GP
1
2
C481
SCD1U10V2KX-4GP
B
1
2
C475
SCD1U10V2KX-4GP
1
2
C461
SCD1U10V2KX-4GP
C270
2
1
C215
2
1
C184
2
1
C509
2
C479
2
1
C457
2
C497
1
C466
1
Place these Caps near DM2
1D8V_S3
2
GND
SRN47J-4-GP
RN16
8
7
6
5
C123
SC1D5P50V2CN-1GP
MEM_MB_CLK1_N
1
GND
1
2
3
4
Layout Note: DY
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT
0D9V_S3
1
VREF
MEM_MB_ADD4 5
MEM_MB_ADD2 5
MEM_MB_ADD0 5
MEM_MB_BANK1 5
C295
SC1D5P50V2CN-1GP
MEM_MB_CLK0_N
2
202
ODT0
ODT1
1
SRN47J-4-GP
RN8
8
7
6
5
SRN47J-4-GP
1
SCL
SDA
114
119
1
2
3
4
D
MEM_MB_CLK0_P
2
197
195
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
SC180P50V2JN-1GP
CS0#
CS1#
CKE0
CKE1
RAS#
CAS#
WE#
C113
SCD1U10V2KX-4GP
SCD01U50V2KX-1GP
110
115
79
80
108
113
109
C110
SC180P50V2JN-1GP
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEM_MB_ADD10 5
MEM_MB_BANK0 5
MEM_MB_ADD1 5
MEM_MB_ADD3 5
1
2
3
4
SCD01U50V2KX-1GP
50
69
83
120
163
81
82
87
88
95
96
103
104
111
112
117
118
(A2)
3D3V_S0
1D8V_S3
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
3D3V_S0
1
199
2
210KR2J-3-GP
10KR2J-3-GP
MEM_MB_ADD8 5
MEM_MB_ADD5 5
MEM_MB_ADD12 5
MEM_MB_ADD9 5
SRN47J-4-GP
RN10
8
7
6
5
2
VDD_SPD
DIMM2_SA0
1
DIMM2_SA1R1191
R120
1
198
200
5
5
5
5
SC2D2U6D3V3KX-GP
1
A
2
1
2
1
2
1
C260
SCD1U10V2KX-4GP
2
1
C251
SCD1U10V2KX-4GP
2
1
C244
SCD1U10V2KX-4GP
2
1
C237
SCD1U10V2KX-4GP
2
1
C225
SCD1U10V2KX-4GP
2
1
C211
SCD1U10V2KX-4GP
2
C197
SCD1U10V2KX-4GP
2
C178
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2
C263
1
C236
1
C159
SCD1U10V2KX-4GP
Place C2.2uF and 0.1uF <
500mils from DDR connector
SCD1U10V2KX-4GP
LOW 5.2 mm
C255
1
C206
SCD1U10V2KX-4GP
62.10017.E31
2
C164
SKT-SODIMM200-38GP
1
201
2
C305
2
1
SA0
SA1
MEM_MB_CLK0_P
MEM_MB_CLK0_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N
SC2D2U6D3V3KX-GP
2
30
32
164
166
SCD1U10V2KX-4GP
SCD1U16V2KX-3GP
SC2D2U6D3V3KX-GP
A
C298
CK0
CK0#
CK1
CK1#
Do not share the Term resistor between
the DDR addess and Control Signals.
SC2D2U6D3V3KX-GP
5 MEM_MB0_ODT0
5 MEM_MB0_ODT1
VREF_DDR_MEM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
5
5
5
5
5
5
5
8
7
6
5
1
2
3
4
Put decap near power(0.9V) and pull-up resistor
SC2D2U6D3V3KX-GP
3,8,17 SMBCLK0_SB
3,8,17 SMBDAT0_SB
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
RN12
1
2
3
4
PARALLEL TERMINATION
SC2D2U6D3V3KX-GP
5 MEM_MB0_CS#0
5 MEM_MB0_CS#1
5 MEM_MB_CKE0
5 MEM_MB_CKE1
5 MEM_MB_RAS#
5 MEM_MB_CAS#
5 MEM_MB_WE#
10
26
52
67
130
147
170
185
0D9V_S3
1
B
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
C
BA0
BA1
MEM_MB_DQS0_P
MEM_MB_DQS1_P
MEM_MB_DQS2_P
MEM_MB_DQS3_P
MEM_MB_DQS4_P
MEM_MB_DQS5_P
MEM_MB_DQS6_P
MEM_MB_DQS7_P
MEM_MB_DQS0_N
MEM_MB_DQS1_N
MEM_MB_DQS2_N
MEM_MB_DQS3_N
MEM_MB_DQS4_N
MEM_MB_DQS5_N
MEM_MB_DQS6_N
MEM_MB_DQS7_N
SC2D2U6D3V3KX-GP
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
2
5
5
5
5
5
5
5
5
5
5
107
106
MH2
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
1
5 MEM_MB_BANK0
5 MEM_MB_BANK1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
2
D
MH2
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
1
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
5 MEM_MB_ADD10
5 MEM_MB_ADD11
5 MEM_MB_ADD12
5 MEM_MB_ADD13
5 MEM_MB_ADD14
5 MEM_MB_ADD15
5 MEM_MB_BANK2
REVERSE TYPE
5
5
5
5
5
5
5
5
5
5
MH1
2
MH1
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
LOW 5.2 mm
DY
DY
Title
DDR_DIMM2
Size
Custom
Date:
5
4
3
2
Document Number
Rev
S13
SC
Friday, May 16, 2008
Sheet
1
9
of
44
5
4
3
2
1
U55A
D
C
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
4
4
4
4
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_NB_CPU_CLK_H0 4
HT_NB_CPU_CLK_L0 4
HT_NB_CPU_CLK_H1 4
HT_NB_CPU_CLK_L1 4
HT_NB_CPU_CTL_H0 4
HT_NB_CPU_CTL_L0 4
HT_NB_CPU_CTL_H1 4
HT_NB_CPU_CTL_L1 4
PART 1 OF 6
HYPER TRANSPORT CPU I/F
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
4
4
4
4
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
4
4
4
4
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
M22
M23
R21
R20
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
M24
M25
P19
R18
C23
A24
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
B24
B25
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
2 R288
301R2F-GP
1
HT_RXCALP
HT_RXCALN
Place < 100mils from pin C23 and A24
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
B
NEW
WLAN
LAN
CARD
A
A-LINK
22
22
22
22
PCIE_NBRX_NEWTX_P0
PCIE_NBRX_NEWTX_N0
PCIE_NBRX_WLANTX_P1
PCIE_NBRX_WLANTX_N1
25 PCIE_NBRX_LANTX_P2
25 PCIE_NBRX_LANTX_N2
24 PCIE_NBRX_CARDTX_P3
24 PCIE_NBRX_CARDTX_N3
16
16
16
16
16
16
16
16
ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
PART 2 OF 6
PCIE I/F GFX
PCIE_NB_LASSO_RX0P
PCIE_NB_LASSO_RX0N
PCIE_NB_LASSO_RX1P
PCIE_NB_LASSO_RX1N
PCIE_NB_LASSO_RX2P
PCIE_NB_LASSO_RX2N
PCIE_NB_LASSO_RX3P
PCIE_NB_LASSO_RX3N
PCIE_NB_LASSO_RX4P
PCIE_NB_LASSO_RX4N
PCIE_NB_LASSO_RX5P
PCIE_NB_LASSO_RX5N
PCIE_NB_LASSO_RX6P
PCIE_NB_LASSO_RX6N
PCIE_NB_LASSO_RX7P
PCIE_NB_LASSO_RX7N
PCIE I/F GPP
PCIE I/F SB
RS780M-GP-U2
5
DY
2
35
3D3V_S0
F2
1
DY
2
PCIE_NB_LASSO_TX0P
PCIE_NB_LASSO_TX0N
FUSE-1A6V-2-GP
PCIE_NB_LASSO_TX1P
PCIE_NB_LASSO_TX1N
PCIE_NB_LASSO_TX2P
PCIE_NB_LASSO_TX2N
PCIE_NB_LASSO_TX3P
R465 1
3D3V_S0
R404 1
3D3V_S0
16
MXM_RST#
33 CPWRON
17,22,25 SB_PCIE_WAKE#
3D3V_S5
4
4
4
4
4
4
4
4
4
4
4
4
PCIE_NB_LASSO_TX3N
2 8K2R2F-1-GP
2 8K2R2F-1-GP
R284 2
1 33R2J-2-GP
R283 2
1 33R2J-2-GP
R285 2
1 33R2J-2-GP
1
2
DY
R494
PCIE_NB_LASSO_TX4P
10KR2J-3-GP
PCIE_NB_LASSO_TX4N
PCIE_NB_LASSO_TX5P
PCIE_NB_LASSO_TX5N
PCIE_NB_LASSO_TX6P
PCIE_NB_LASSO_TX6N
PCIE_NB_LASSO_TX7P
PCIE_NB_LASSO_TX7N
3D3V_BUS
17 CPRSNT2#
CPRSNT2#
NP1
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
NP3
T14
T15
T16
T17
T18
T19
T20
T21
NP4
T22
T23
T24
T25
T26
T27
T28
T29
T30
T31
T32
T33
T34
USBP_9+
USBP_9-
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
PCIE_NB_LASSO_RX0P
PCIE_NB_LASSO_RX0N
D
PCIE_NB_LASSO_RX1P
PCIE_NB_LASSO_RX1N
PCIE_NB_LASSO_RX2P
PCIE_NB_LASSO_RX2N
B13
B14
B15
B16
B17
B18
B19
B20
PCIE_NB_LASSO_RX3P
PCIE_NB_LASSO_RX3N
CLK_PCIE_LASSO 3
CLK_PCIE_LASSO# 3
PCIE_NB_LASSO_RX4P
PCIE_NB_LASSO_RX4N
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
NP2
38
2 R282
301R2F-GP
1
B1
PCIE_NB_LASSO_RX5P
PCIE_NB_LASSO_RX5N
PCIE_NB_LASSO_RX6P
PCIE_NB_LASSO_RX6N
PCIE_NB_LASSO_RX7P
PCIE_NB_LASSO_RX7N
C
36
JAE-CONN68-GP-U1
Placement: close RS780
U55B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
3D3V_BUS
37
0R5J-6-GP
Place < 100mils from pin B25 and B24
RS780M-GP-U2
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
HT_TXCALP
HT_TXCALN
CN9
R253
1
GFX_TX0P_C
GFX_TX0N_C
GFX_TX1P_C
GFX_TX1N_C
GFX_TX2P_C
GFX_TX2N_C
GFX_TX3P_C
GFX_TX3N_C
C485
C486
C487
C488
C490
C489
C492
C491
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R455
R486
R487
R488
R489
R490
R491
R492
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
DVI_TXAOUT2+ 15
DVI_TXAOUT2- 15
DVI_TXAOUT1+ 15
DVI_TXAOUT1- 15
DVI_TXAOUT0+ 15
DVI_TXAOUT0- 15
DVI_TXACLK+ 15
DVI_TXACLK- 15
RN37
GFX_TX8P_C
GFX_TX8N_C
GFX_TX9N_C
GFX_TX9P_C
GFX_TX10N_C
GFX_TX10P_C
GFX_TX11N_C
GFX_TX11P_C
GFX_TX12N_C
GFX_TX12P_C
GFX_TX13N_C
GFX_TX13P_C
GFX_TX14P_C
GFX_TX14N_C
GFX_TX15N_C
GFX_TX15P_C
C478
C480
C476
C477
C472
C473
C468
C470
C465
C467
C463
C464
C460
C462
C458
C459
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_NBTX_NEWRX_P0 C451
PCIE_NBTX_NEWRX_N0 C453
PCIE_NBTX_WLANRX_P1C446
PCIE_NBTX_WLANRX_N1C444
PCIE_NBTX_LANRX_P2 C445
PCIE_NBTX_LANRX_N2 C443
PCIE_NBTX_CARDRX_P2C450
PCIE_NBTX_CARDRX_N2C448
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
ALINK_NBTX_SBRX_P0
ALINK_NBTX_SBRX_N0
ALINK_NBTX_SBRX_P1
ALINK_NBTX_SBRX_N1
ALINK_NBTX_SBRX_P2
ALINK_NBTX_SBRX_N2
ALINK_NBTX_SBRX_P3
ALINK_NBTX_SBRX_N3
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
PCE_CALRP
PCE_CALRN
AC8
AB8
PCE_PCAL
PCE_NCAL
C434
C433
C430
C429
C436
C435
C438
C437
1
R262 1
R261
2
2 1K27R2F-L-GP
2KR2F-3-GP
17
17
PCIE_NB_LASSO_TX0P
PCIE_NB_LASSO_TX0N
PCIE_NB_LASSO_TX1P
PCIE_NB_LASSO_TX1N
PCIE_NB_LASSO_TX2P
PCIE_NB_LASSO_TX2N
PCIE_NB_LASSO_TX3P
PCIE_NB_LASSO_TX3N
PCIE_NB_LASSO_TX4P
PCIE_NB_LASSO_TX4N
PCIE_NB_LASSO_TX5P
PCIE_NB_LASSO_TX5N
PCIE_NB_LASSO_TX6P
PCIE_NB_LASSO_TX6N
PCIE_NB_LASSO_TX7P
PCIE_NB_LASSO_TX7N
PCIE_NBTX_C_NEWRX_P0 22
PCIE_NBTX_C_NEWRX_N0 22
PCIE_NBTX_C_WLANRX_P1 22
PCIE_NBTX_C_WLANRX_N1 22
PCIE_NBTX_C_LANRX_P2 25
PCIE_NBTX_C_LANRX_N2 25
PCIE_NBTX_C_CARDRX_P3 24
PCIE_NBTX_C_CARDRX_N3 24
ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3
3
USBP9USBP9+
USBP9USBP9+
3
4
USBP_9USBP_9+
2
1
SRN0J-6-GP
B
NEW
WLAN
LAN
CARD
<Core Design>
16
16
16
16
16
16
16
16
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-RS780M_HT LINK&PCIE(1/4)
1D1V_S0
Size
A3
Place < 100mils from pin AC8 and AB8
4
LASSO CONNECTOR
Document Number
Date: Friday, May 16, 2008
2
Rev
S13
SC
Sheet
1
10
of
44
4
3
3D3V_S0
2
+3.3V_RUN_AVDD
L13
1D8V_S0
2
C_Pr
Y
COMP_Pb
G18
G17
E18
F18
E19
F19
RED
REDb
GREEN
GREENb
BLUE
BLUEb
15 NB_CRT_GREEN
2
15 NB_CRT_BLUE
6 CPU_LDT_REQ#
R152 1
2 140R2F-GP
R157 1
2 150R2F-1-GP
R155 1
2 150R2F-1-GP
A11
B11
F8
E8
DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA
G14
DAC_RSET
A12
D14
B12
PLLVDD
PLLVDD18
PLLVSS
+1.8V_VDDA18HTPLL
H17
VDDA18HTPLL
+1.8V_VDDA18PCIEPLL
D7
E7
VDDA18PCIEPLL1
VDDA18PCIEPLL2
D8
A10
C10
C12
SYSRESET#
POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP
C25
C24
HT_REFCLKP
HT_REFCLKN
E11
F11
REFCLK_P/OSCIN
REFCLK_N
15 NB_CRT_HSYNC
15 NB_CRT_VSYNC
C
1D1V_S0
+1.1V_RUN_PLLVDD
2
BLM15AG221SN-GP
C494
SC2D2U6D3V3KX-GP
2 NB_PWRGD
300R2J-4-GP
1
R220
2
1
1
2DAC_RSET
715R2F-GP
1
R153
L39
1D8V_S0
+1.8V_RUN_PLVDD18
1D8V_S0
L14
33
1
2
BLM15AG221SN-GP
1
1
NB_PWRGD
C278
SCD1U10V2KX-4GP
2
SC10U10V5KX-2GP
2
C281
SYSREST#
NB_PWRGD
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
1D1V_S0
1
ENABLE External CLK GEN
1KR2F-3-GP
R169
2
1
R167
1KR2F-3-GP
3 CLK_NBHT_CLK
3 CLK_NBHT_CLK#
3 CLK_NB_14M
NB_REFCLK_N
2
3 CLK_NB_GFX
3 CLK_NB_GFX#
B
3 CLK_NB_GPPSB
3 CLK_NB_GPPSB#
14 NB_LCD_DDCLK
14 NB_LCD_DDCDAT
3D3V_S0
GPIO MODE
STRP_DATA
R158
*1
1
1.0V 1.1V
2
U1
U2
GPP_REFCLKP
GPP_REFCLKN
V4
V3
GPPSB_REFCLKP
GPPSB_REFCLKN
B9
A9
B8
A8
B7
A7
I2C_CLK
I2C_DATA
DDC_CLK0/AUX0P
DDC_DATA0/AUX0N
DDC_DATA0/AUX0N DDC_CLK0/AUX0P
DDC_CLK1/AUX1P
DDC_DATA1/AUX1N
B10
STRP_DATA
RESERVED
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
B16
A16
D16
D17
VDDLTP18
VSSLTP18
A13
B13
VDDLT18_1
VDDLT18_2
VDDLT33_1
VDDLT33_2
A15
B15
A14
B14
VSSLT1
VSSLT2
VSSLT3
VSSLT4
VSSLT5
VSSLT6
VSSLT7
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON
LVDS_BLON
LVDS_ENA_BL
E9
F7
G12
TXOUT0+
TXOUT0TXOUT1+
TXOUT1TXOUT2+
TXOUT2-
TXCLK+
TXCLK-
14
14
14
14
14
14
14
14
1D8V_S0
+1.8V_RUN_VDDLP18
C500
SC2D2U6D3V3KX-GP
+1.8V_RUN_VDDLT18
C499
SC4D7U6D3V3KX-GP
C
L41
1
2
BLM15AG221SN-GP
L42
1
2
BLM15AG221SN-GP
C496
SCD1U10V2KX-4GP
NB_LVDS_DIGON
PANEL_BKEN 30
PANEL_BKEN
R154 1
21K27R2F-L-GP
R293 1
2100KR2J-1-GP
14
B
DY
MIS.
G11
A22
B22
A21
B21
B20
A20
A19
B19
TMDS_HPD
HPD
D9
D10
SUS_STAT#
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
SUS_STAT#_R
R307 1
2 0R0402-PAD
DVI_A_HPD
15
SUS_STAT#
17
NB_THERMDP 21
NB_THERMDN 21
RS780_AUX_CAL
C8
D13 TESTMODE_NB
AUX_CAL
R305
1K8R2F-GP
RS780M-GP-U2
150R2F-1-GP
2
VCC_NB
0
1
1
GFX_REFCLKP
GFX_REFCLKN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
1
STRP_DATA
15 DVI_DDCCLK
15 DVI_DDCDATA
R292
1
2
10KR2J-3-GP
TP64
TP65
T2
T1
PART 3 OF 6
1
R291
0R2J-2-GP
NB_CRT_RED
D
SUS_STAT#
2
E17
F17
F15
Close to NB ball
15
1 : Disable
1
AVDD1
AVDD2
AVDDDI
AVSSDI
AVDDQ
AVSSQ
NB_ALLOW_LDTSTOP
R289
0R0402-PAD
: Enable
U55C
F12
E12
F14
G15
H15
H14
2
1
16 ALLOW_LDTSTOP
2
*0
Selects Loading of STRAPS From EEPROM
Bypass the loading of EEPROM straps and use Hardware Default Values
*10 :: I2C
Master can load strap values from EEPROM if connected,
or use default values if not connected
DY
DY
1
*
RS780: Enables Side port memory ( RS780 use HSYNC)
2
R286
4K7R2F-GP
R161
3KR2F-GP
Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC)
0 : Enable
1 : Disable
1
1
C233
SCD1U10V2KX-4GP
1
C286
SC2D2U6D3V3KX-GP
2
3D3V_S0
1
R165
1
2
BLM18BB221SN1D-GP
NB_LDT_STOP#
0R0402-PAD
2
R290
2
+1.8V_RUN_AVDDQ
1D8V_S0
2
6 LDT_STP#_CPU
1
NB_CRT_VSYNC
NB_CRT_HSYNC
2
0R0603-PAD
DY
R159
3KR2F-GP
2
+1.8V_RUN_AVDDDI
2
1
1
1
C283
SC2D2U6D3V3KX-GP
R164
D
2
DY
CRT/TVOUT
3D3V_S0
R287
4K7R2F-GP
R163
3KR2F-GP
PLL PWR
LVTM
33ohm 3A
R156
3KR2F-GP
CLOCKs PM
0R2J-2-GP
C264
SC2D2U6D3V3KX-GP
1
BLM18PG330SN1D-GP
1
SYSREST#
1
0R2J-2-GP
2
2
2
STRAP_DEBUG_BUS_GPIO_ENABLE
1
1
PLTRST#
2
2
16,33
DY
1
1
R309
1
R310
6 LDT_RST#_CPU
1
3D3V_S0
2
5
15mil width
+1.8V_VDDA18HTPLL
15mil width
1D8V_S0
1
C508
SC2D2U6D3V3KX-GP
2
1
1
2
BLM18BB221SN1D-GP
C238
SCD1U10V2KX-4GP
1
2
C218
SC2D2U6D3V3KX-GP
A
L43
2
2
BLM15AG221SN-GP
1
1
<Core Design>
+1.8V_VDDA18PCIEPLL
L11
2
1D8V_S0
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
C252
SCD1U10V2KX-4GP
Title
ATi-RS780M_LVDS&CRT_(2/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
11
of
44
5
4
3
2
1
U55D
IOPLLVDD18
IOPLLVDD
AE23
AE24
+1.8V_IOPLLVDD18
+1.1V_IOPLLVDD
IOPLLVSS
AD23
MEM_VREF
AE18
MEM_COMPP
MEM_COMPN
C135
C141
SCD1U10V2KX-4GP
MEM_VREF_NB
+1.8V_MEM_VDDQ
RS780M-GP-U2
1
R266
40D2R2F-GP
R143
1KR2F-3-GP
2
C
U28
F7
E8
LDQS
LDQS
MEM_DQS1P
MEM_DQS1N
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
1
1
R112
1KR2F-3-GP
2
2
C105
SCD1U10V2KX-4GP
1
1
MEM_VREF_CHIP
2
A
R111
1KR2F-3-GP
2
C104
SCD1U10V2KX-4GP
MEM_BA2
C100
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
1
2
C101
SC1U6D3V2KX-GP
MEM_DQS0P
MEM_DQS0N
ODT
SC1U6D3V2KX-GP
K9
VDDL_VRAM
Layout Note: 50 mil for VSSDL
1
VDDL
VSSDL
ODT
+1.8V_MEM_VDDQ
J1
J7
DY
C117
C119
C431
C426
C106
DY
1
600 ohm @ 100MHz,200mA
220 ohm @ 100MHz,2A
C422
2
LDM
UDM
1
2
HCB2012KF-221T30-GP
L4
BLM18AG601SN-3GP
1
F3
B3
A1
E1
J9
M9
R1
2
CAS
MEM_DM0
MEM_DM1
VDD1
VDD2
VDD3
VDD4
VDD5
1
RAS
L7
C140
+1.8V_MEM_VDDQ
2
K7
CAS#
L5
SC1U6D3V2KX-GP
RAS#
C
B
1D8V_S0
SC1U6D3V2KX-GP
WE
SCD1U10V2KX-4GP
CS
K3
SCD1U10V2KX-4GP
L8
WE#
SC10U6D3V5KX-1GP
CS#
C134
+1.8V_MEM_VDDQ
SC10U6D3V5KX-1GP
CKE
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
1
B
K2
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
2
CKE
CK
CK
1
R251
2 100R2F-L1-GP-U
K8
J8
2
DY
1
1
R141
1KR2F-3-GP
2
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MEM_DQ15
MEM_DQ14
MEM_DQ13
MEM_DQ12
MEM_DQ11
MEM_DQ10
MEM_DQ9
MEM_DQ8
MEM_DQ7
MEM_DQ6
MEM_DQ5
MEM_DQ4
MEM_DQ3
MEM_DQ2
MEM_DQ1
MEM_DQ0
1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
2
MEM_A12
MEM_A11
MEM_A10
MEM_A9
MEM_A8
MEM_A7
MEM_A6
MEM_A5
MEM_A4
MEM_A3
MEM_A2
MEM_A1
MEM_A0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
1
BA0
BA1
2
L2
L3
2
MEM_CLKN
MEM_CLKP
MEM_BA0
MEM_BA1
SCD1U10V2KX-4GPSCD1U10V2KX-4GP
AE12
AD12
MEM_DM0
MEM_DM1
BLM15AG221SN-GP
1
MEM_COMPP
MEM_COMPN
W17
AE19
2
2
MEM_CKP
MEM_CKN
MEM_DM0
MEM_DM1/DVO_D8
1
1
V15
W14
MEM_CLKP
40D2R2F-GP MEM_CLKN
R265
1
2
1
2
MEM_DQS0P/DVO_IDCKP
MEM_DQS0N/DVO_IDCKN
MEM_DQS1P
MEM_DQS1N
1D1V_S0
L7
15mil width
2
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
D
BLM15AG221SN-GP
C138
SC2D2U6D3V3KX-GP
1
W12
Y12
AD18
AB13
AB18
V14
MEM_DQS0P
MEM_DQS0N
MEM_DQS1P
MEM_DQS1N
2
2
RAS#
CAS#
WE#
CS#
CKE
ODT
Y17
W18
AD20
AE21
1
1
MEM_BA0
MEM_BA1
MEM_BA2
1D8V_S0
L8
15mil width
2
AD16
AE17
AD17
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
1
MEM_BA0
MEM_BA1
MEM_BA2
MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ0/DVO_VSYNC
MEM_DQ1/DVO_HSYNC
MEM_DQ2/DVO_DE
MEM_DQ3/DVO_D0
MEM_DQ4
MEM_DQ5/DVO_D1
MEM_DQ6/DVO_D2
MEM_DQ7/DVO_D4
MEM_DQ8/DVO_D3
MEM_DQ9/DVO_D5
MEM_DQ10/DVO_D6
MEM_DQ11/DVO_D7
MEM_DQ12
MEM_DQ13/DVO_D9
MEM_DQ14/DVO_D10
MEM_DQ15/DVO_D11
SC2D2U6D3V3KX-GP
+1.8V_MEM_VDDQ
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
2
TP11
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
SBD_MEM/DVO_I/F
D
PAR 4 OF 6
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
1MEM_A13
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
HYB18T512161B2F-25-GP
Title
ATi-RS780M_SidePort_(3/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
12
of
44
5
4
3
2
1
D
D
U55F
0.6A per ANT Rev1.1, Page3
L10
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
2
2
1
2
HCB2012KF-221T30-GP
C129
1
C143
220 ohm @ 100MHz, 2A
2
1
2
1
2
1
2
1
2
2
2
+3.3V_RUN_VDD33
C240
1
1
1
C142
C504
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
C
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
B
RS780M-GP-U2
2
R306
0R0603-PAD
2
1
1
2
1
2
2
1
2
1
1
2
POWER
1
2
1
2
1
2
C136
L6
3D3V_S0
1
1
2
1
2
1
2
1
2
1
2
1
2
C125
15mil width
H11
H12
2
1
1
1
2
2
2
AE10
AA11
Y11
AD10
AB10
AC10
C145
SC4D7U6D3V3KX-GP
1
C210
+1.8V_RUN_MEM
SCD1U10V2KX-4GP
2
C226
SC10U6D3V5KX-1GP
C189
SC10U6D3V5KX-1GP
C204
SCD1U10V2KX-4GP
VDD33_1
VDD33_2
SC4D7U6D3V3KX-GP
RS780M-GP-U2
220 ohm @ 100MHz, 2A
1D8V_S0
SCD1U10V2KX-4GP
15mil width
C425
VDD18_1
VDD18_2
VDD18_MEM1
VDD18_MEM2
1
2
HCB2012KF-221T30-GP
C245
15mil width
SCD1U10V2KX-4GP
R257
0R0603-PAD
F9
G9
AE11
AD11
DY
C232
SCD1U10V2KX-4GP
+1.8V_RUN_VDD18_MEM
C103
SCD1U10V2KX-4GP
2
C186
SCD1U10V2KX-4GP
1
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C249 1D8V_S0
C98
SCD1U10V2KX-4GP
15mil width
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
C267
+NB_VCORE
SCD1U10V2KX-4GP
DY
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
C183
1D1V_S0
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C191
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
L12
100mil Width
+1.1V_RUN_VDDPCIE
C262
C203
SCD1U10V2KX-4GP
C177
+1.8V_RUN_VDDA18PCIE
C217
C172
C154
SCD1U10V2KX-4GP
C155
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D8V_S0
C165
SCD1U10V2KX-4GP
B
+1.2V_RUN_VDDHTTX
C151
C148
20mil width
SC4D7U6D3V3KX-GP
220 ohm @ 100MHz,2A
SC4D7U6D3V3KX-GP
1
2
HCB2012KF-221T30-GP
SCD1U10V2KX-4GP
L9
SCD1U10V2KX-4GP
1D8V_S0
SC4D7U6D3V3KX-GP
220 ohm @ 100MHz,2A
C201
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
SCD1U10V2KX-4GP
L37
C441
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
AE25
AD24
AC23
AB22
AA21
Y20
W19
V18
U17
T17
R17
P17
M17
1D2V_S0
1
2
HCB2012KF-221T30-GP
H18
G19
F20
E21
D22
B23
A23
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C495
SCD1U10V2KX-4GP
220 ohm @ 100MHz,2A
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
C
+1.1V_RUN_VDDHTRX
C484
C247
C259
PART 5/6
SC1U6D3V2KX-GP
0.45A per ANT Rev1.1, Page3
L40
1
2
HCB2012KF-221T30-GP
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
SC1U6D3V2KX-GP
1D1V_S0
J17
K16
L16
M16
P16
R16
T16
SCD1U10V2KX-4GP
2
1
U55E
SCD1U10V2KX-4GP
2
+1.1V_RUN_VDDHT
C207
C188
SCD1U10V2KX-4GP
C156
C219
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
220 ohm @ 100MHz,2A
SC4D7U6D3V3KX-GP
1
2
HCB2012KF-221T30-GP
1D1V_S0
0.7A per ANT Rev1.1, Page3
GROUND
1D1V_S0
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-RS780M_PWR&GD_(4/4)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
13
of
44
5
4
3
2
1
LCD CONNECTOR
D
D
1
1
2
2
DCBATOUT
C53
SCD1U25V3KX-GP
CN5
C50
SC10U25V6KX-1GP
42
0R0402-PAD
BLON_OUT
R77
2
10KR2F-2-GP
CAMERA POWER
C
17
17
USBP1+
USBP1-
11
11
TXOUT2TXOUT2+
11
11
TXOUT1TXOUT1+
11
11
TXOUT0+
TXOUT0TXCLK+
TXCLK-
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1
40
5V_CAM_S0
D_MIC_CLKOUT
DMIC_DATAIN
D_MIC_CLKOUT
DMIC_DATAIN
CAMERA_EN
R493 1
2 0R3-0-U-GP
R96 1
R100 1
C69
SCD1U16V2ZY-2GP
2 4K7R2F-GP 3D3V_S0
2 4K7R2F-GP
NB_LCD_DDCLK 11
NB_LCD_DDCDAT 11
3D3V_S0
2
11
11
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
2
1
1
30
R69
1
31 BRIGHTNESS
C
EC4
SCD1U16V2ZY-2GP
ARRAY_DETC
27
41
LCDVDD_S0
U18
CAMERA_EN
SCD1U16V2ZY-2GP
CAMERA_EN 30
5V_CAM_S0
1
C91
GND
EN
OUT
IN#1
C96
SC10U10V5KX-2GP
2
1
ETY-CONN40C-GP-U1
4
3
2
1
2
IN#5
IN#6
IN#7
IN#8
GND
R93
100KR2J-1-GP
C60
SC1U10V2KX-1GP
2
G5281RC1U-GP
74.05281.093
2
1
5
6
7
8
9
1
C82
SCD1U16V2ZY-2GP
2
1
5V_S0
DY
1
D_MIC_CLKOUT
B
2
B
D_MIC_CLKOUT 27
SC33P50V2JN-3GP
C619
LCDVDD_S0
TOP VIEW
IN#5
IN#6
IN#7
IN#8
GND
GND
EN
OUT
IN#1
4
3
2
1
21
1
40
2
NB_LVDS_DIGON
11
G5281RC1U-GP
74.05281.093
R109
100KR2J-1-GP
2
<DUMMY>
5
6
7
8
9
20
DMIC_DATAIN 27
SC33P50V2JN-3GP
C653
1
1
SCD1U16V2ZY-2GP
2
C84
C90
SC1U10V2KX-1GP
2
U22
3D3V_S0
1
1
DMIC_DATAIN
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
LCD CONN/CAMERA
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
14
of
44
5
4
3
2
1
CN6
25
Layout Note:
Place these resistors close to the connector
D
5V_S0
L31 1
C4
CRT_B
2
NBQ201209T-070Y-N-GP
1
1
1
A
CRT_G
2
NBQ201209T-070Y-N-GP
1
2
EC9
F1
K
1
2
10 DVI_TXACLK+
RB521S-30-2-GP
FUSE-1A6V-2-GP
10 DVI_TXACLK-
DVI_A_HPD_R
CRT_B
JVGA_HS
NP1
1
2
D
DVI_TXAOUT2- 10
DVI_TXAOUT2+ 10
3
4
5
DVI_DDC_CLK
6
DVI_DDC_DATA
7
8
JVGA_VS
C1
C6
NP2
C2
26
CRT_R
CRT_G
FOX-CONN24-3R-5GP
SC3D3P50V2CN-GP
EC8
SC3D3P50V2CN-GP
1
2
2
EC7
SC3D3P50V2CN-GP
1
EC12
SC3D3P50V2CN-GP
1
2
1
2
EC11
SC3D3P50V2CN-GP
2
C
EC10
SC3D3P50V2CN-GP
2
2
150R2F-1-GP
2
R229
150R2F-1-GP
140R2F-GP
R228
1
R227
SCD01U50V2KX-1GP
L32 1
11 NB_CRT_BLUE
5V_DVI_S0
D4
1
11 NB_CRT_GREEN
5V_DVI1_S0
CRT_R
2
NBQ201209T-070Y-N-GP
2
11 NB_CRT_RED
L30 1
17
9
18
10
19
11
20
12
21
13
22
14
23
15
24
16
C3
C5
C4
10 DVI_TXAOUT010 DVI_TXAOUT110 DVI_TXAOUT0+
10 DVI_TXAOUT1+
C
R225
1
2
DVI_A_HPD
11
1
DVI_A_HPD_R
20KR2F-L-GP
R224
5V_DVI1_S0
5
1
6
1
2
1
1
14
2
11 NB_CRT_VSYNC
U9A
SSAHCT125PWR-GP
3
Hsync & Vsync level shift
2
1
C5
SCD1U10V2KX-4GP
7
2
D G S
S G D
Q1
4
2
1
11 DVI_DDCCLK
11 DVI_DDCDATA
3
R8
4K7R2J-2-GP
2
1
R2
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
2
R1
100KR2J-1-GP
3D3V_S0
R4
5V_S0
2
3D3V_S0
DVI_DDC_CLK
DVI_DDC_DATA
RN1
VSYNC_5
HSYNC_5
5V_S0
2N7002DW-1-GP
B
2
1
3
4
JVGA_VS
JVGA_HS
B
5
U9B
SSAHCT125PWR-GP
6
7
11 NB_CRT_HSYNC
4
14
SRN33J-5-GP-U
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
750R2F-GP
750R2F-GP
750R2F-GP
750R2F-GP
750R2F-GP
750R2F-GP
750R2F-GP
750R2F-GP
5V_S0
TMDS_PL
D
DVI_TXACLK+ R15
DVI_TXACLK- R16
DVI_TXAOUT0+ R7
DVI_TXAOUT0- R11
DVI_TXAOUT1+ R9
DVI_TXAOUT1- R6
DVI_TXAOUT2+ R5
DVI_TXAOUT2- R3
Q17
2N7002-11-GP
S
1
1
G
A
C380
SCD1U10V2KX-4GP
<Core Design>
A
2
R230
2
100KR2J-1-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DVI CONN
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
15
of
44
4
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
T25
T24
PCIE_CALRP
PCIE_CALRN
P24
PCIE_PVDD
AD3
AC4
AE2
AE3
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
SERIRQ
G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15
C
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
K23
K22
NB_DISP_CLKP
NB_DISP_CLKN
M24
M25
NB_HT_CLKP
NB_HT_CLKN
P17
M18
CPU_HT_CLKP
CPU_HT_CLKN
M23
M22
SLT_GFX_CLKP
SLT_GFX_CLKN
1
R350
B
DY
2
2
20MR3-GP
GPP_CLK1P
GPP_CLK1N
M19
M20
GPP_CLK2P
GPP_CLK2N
N22
P22
GPP_CLK3P
GPP_CLK3N
L18
25M_48M_66M_OSC
32K_X1
1
TP37
1
J21
25M_X1
1
4
C587
SC12P50V2JN-3GP
3
GPP_CLK0P
GPP_CLK0N
L20
L19
CLOCK GENERATOR
J19
J18
PCI INTERFACE
N25
N24
J20
25M_X2
2
1
C565
SC12P50V2JN-3GP
32K_X2
1
0R2J-2-GP
R340
2
32K_X2_R
X1
B3
X2
1D8V_S0
R390
LPC
X5
X-32D768KHZ-38GPU
A3
RTC XTAL
1
2
2
R335
20MR3-GP
ALLOW_LDTSTP
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
RTCCLK
INTRUDER_ALERT#
VBAT
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
20
20
20
20
20
20
20
20
10
C
U87
PLTRST#
1
B
PE_GPIO0
2
A
3
VCC
5
Y
4
MXM_RST#
GND
74LVC1G08GW-1-GP
DY
3D3V_S0
R218
IRQ_SERIRQ
1
2
8K2R2J-3-GP
DY
B
PM_CLKRUN# 30
R464
10KR2J-3-GP
DY
PE_GPIO0
LPCCLK0_R R395 1
LPCCLK1_R R370 1
2 22R2J-2-GP
2 22R2J-2-GP
LPC_LAD0 30
LPC_LAD1 30
LPC_LAD2 30
LPC_LAD3 30
LPC_LFRAME# 30
SB700_GPIO65
LPCCLK0
LPCCLK1
3D3V_AUX_S5
RTCCLK
C580
30
49K9R2F-L-GP +RTC_CELL
20,21
R366
DY
1
2
1
2
C573
3
1
2
NP1
NP2
2
0R3-0-U-GP
2
PWR
GND
NP1
NP2
BAT-CON2-1-GP-U
<Core Design>
SC22P50V2JN-4GP
C599
DY DY
RTC1
DY
2
1
R367
R351
510R2J-1-GP
+COIN_CELL
D25
BAT54CW-1-GP
1
2
10KR2J-3-GP
IRQ_SERIRQ
INTRUDER_ALERT#
+VBAT_IN
20,30
20
3D3V_S0
R474 1
C420
3
MXM_RST#
3D3V_S0
SC22P50V2JN-4GP
4
MXM_RST#
2
D35
CH751H-40PT
DY
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-SB700_PCIE&PCI_(1/5)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
2
1
R478
2K2R2F-GP
SCD1U16V2KX-3GP
SB700-1-GP-U1
A
C3
C2
B2
PE_GPIO0
SC1U6D3V2KX-GP
RTC
F23
F24
F22
G25
G24
CPU
1
2
300R2J-4-GP
11 ALLOW_LDTSTOP
6 CPU_PROCHOT#
6 CPU_PWRGD
6 CPU_LDT_STOP#
6 CPU_LDT_RST#
1
D36
CH751H-40PT
2
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
PCIE_PVSS
PLTRST#
11,33 PLTRST#
1
U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5
TP62
1
1
40mA
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#/GPIO70
REQ4#/GPIO71
GNT0#
GNT1#
GNT2#
GNT3#/GPIO72
GNT4#/GPIO73
CLKRUN#
LOCK#
Place R <100mils form pins T25,T24
3 CLK_PCIE_SB
3 CLK_PCIE_SB#
N1
20
20
20
20
20
2
C363
PCIRST#
CLK_PCI_1
CLK_PCI_2
CLK_PCI_3
CLK_PCI_4
CLK_PCI_5
D
1
P25
P4
P3
P1
P2
T4
T3
LPCCLK1
2
C367
SC1U6D3V2KX-GP
1
20mil Width
SC10U6D3V5KX-1GP
200 ohm 2A
U22
U21
U19
V19
R20
R21
R18
R17
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5/GPIO41
LPCCLK0
L28
1
2
HCB2012KF-221T30-GP
PCIE_CALRP
2 562R2F-GP
2 2K05R2F-GP PCIE_CALRN
1
1
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
1
R430
R424
Part 1 of 5
1
+1.2V_PCIE_VDDR
ALINK_NBTX_C_SBRX_P0
ALINK_NBTX_C_SBRX_N0
ALINK_NBTX_C_SBRX_P1
ALINK_NBTX_C_SBRX_N1
ALINK_NBTX_C_SBRX_P2
ALINK_NBTX_C_SBRX_N2
ALINK_NBTX_C_SBRX_P3
ALINK_NBTX_C_SBRX_N3
SB700
A_RST#
V23
V22
V24
V25
U25
U24
T23
T22
2
10
10
10
10
10
10
10
10
ALINK_NBRX_C_SBTX_P0
ALINK_NBRX_C_SBTX_N0
ALINK_NBRX_C_SBTX_P1
ALINK_NBRX_C_SBTX_N1
ALINK_NBRX_C_SBTX_P2
ALINK_NBRX_C_SBTX_N2
ALINK_NBRX_C_SBTX_P3
ALINK_NBRX_C_SBTX_N3
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
2
2
2
2
2
2
2
N2
2
+1.2V_RUN_PCIE_PVDD
2
1D2V_S0
1
1
1
1
1
1
1
1
1
U62A
NB_RST#
1
D
C644
C647
C643
C646
C627
C642
C623
C630
ALINK_NBRX_SBTX_P0
ALINK_NBRX_SBTX_N0
ALINK_NBRX_SBTX_P1
ALINK_NBRX_SBTX_N1
ALINK_NBRX_SBTX_P2
ALINK_NBRX_SBTX_N2
ALINK_NBRX_SBTX_P3
ALINK_NBRX_SBTX_N3
2
2
10
10
10
10
10
10
10
10
33R2J-2-GP
R436
2
PCI CLKS
1
11,33 PLTRST#
3
PCI EXPRESS INTERFACE
5
Rev
S13
SC
Sheet
1
16
of
44
5
4
3
2
1
U62D
30 KA20GATE
30 KBRCIN#
30 ECSCI#_KBC_R
SMBCLK0_SB
2K2R2F-GP
ECSMI#_KBC
SMBDAT0_SB
2K2R2F-GP
10,22,25 SB_PCIE_WAKE#
3D3V_S5
SMB_ALERT#
1
2 0R0402-PAD
SB_TO_EC_PWRGD
33 SB_TO_EC_PWRGD
1
R195
1
R196
1
R407
1
R204
1
R414
1
R373
1
R249
1
R202
1
R406
1
R416
1
R421
1
R255
DY
2
DY
2
1
R432
1
R205
1
R200
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
2
DY
2
2
2
2
TP68
SB_TEST2
RSMRST#_SB
1
2K2R2F-GP
SB_TEST1
R374
2K2R2F-GP
TPAD60
SB_TEST0
ECSCI#_KBC_R
10KR2J-3-GP
ECSMI#_KBC
10KR2J-3-GP
RSMRST#_SB
10KR2J-3-GP
3,8,9
3,8,9
22
22
ECSWI#_SB
10KR2J-3-GP
SB_PCIE_WAKE#
10KR2J-3-GP
1
1
1
1
1
1
SB700_GPIO10
SB700_GPIO6
SB700_GPIO4
SB700_GPIO0
SB700_GPIO39
SB700_GPIO40
27
SB_SPKR
SMBCLK0_SB
SMBDAT0_SB
SMBCLK1_SB
SMBDAT1_SB
SMB_ALERT#
10KR2J-3-GP
SMBCLK1_SB
SHUTDOWN#/GPIO5
2K2R2F-GP
SMBDAT1_SB
AE18
AD18
AA19
W17
V17
W20
W21
AA18
W18
K1
K2
AA20
Y18
C1
Y19
G5
USB MISC
SATA_IS0#/GPIO10
CLK_REQ3#/SATA_IS1#/GPIO6
SMARTVOLT/SATA_IS2#/GPIO4
CLK_REQ0#/SATA_IS3#/GPIO0
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
LLB#/GPIO66
SHUTDOWN#/GPIO5
DDR3_RST#/GEVENT7#
2K2R2F-GP
CPRSNT2#
10KR2J-3-GP
SB_AZ_BITCLK
30
10KR2J-3-GP
SB_AZ_CODEC_SDIN0
24 CR_CPPE#
10KR2J-3-GP
SUS_STAT#
10KR2J-3-GP
27 SB_AZ_CODEC_BITCLK
27 SB_AZ_CODEC_SDOUT
27 SB_AZ_CODEC_SDIN0
27 SB_AZ_CODEC_SYNC
27 SB_AZ_CODEC_RST#
ECSWI#_SB
ECSWI#_SB
TP32
1
CPRSNT2# R256 2
1 33R2J-2-GP
22
CPPE#
TP34
1
TP61
1
SB_AZ_BITCLK
SB_AZ_SDOUT
SB_AZ_CODEC_SDIN0
10 CPRSNT2#
Close to SB700
R433
R419
R429
R425
1
1
1
1
2 33R2J-2-GP
2 33R2J-2-GP
2 33R2J-2-GP
2 33R2J-2-GP
SB_AZ_SYNC
SB_AZ_RST#
B
SB_AZ_RST#
B9
B8
A8
A9
E5
F8
E4
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GPM5#
USB_OC4#/IR_RX0/GPM4#
USB_OC3#/IR_RX1/GPM3#
USB_OC2#/GPM2#
USB_OC1#/GPM1#
USB_OC0#/GPM0#
M1
M2
J7
J8
L8
M3
L6
M4
L5
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO42
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
AZ_SDIN3/GPIO46
AZ_SYNC
AZ_RST#
AZ_DOCK_RST#/GPM8#
20
TO STRAPS
IDE_RST#
1
2
R377
0R2J-2-GP
DY
IDE_RST#_R
H19
H20
H21
F25
IMC_GPIO0
IMC_GPIO1
SPI_CS2#/IMC_GPIO2
IDE_RST#/F_RST#/IMC_GPO3
D22
E24
E25
D23
IMC_GPIO4
IMC_GPIO5
IMC_GPIO6
IMC_GPIO7
INTEGRATED uC
23
DY
R385
2
10KR2J-3-GP
1
1D8V_S0
DY
D
Place R near pin14. Route it with 10mils
Trace width and 25mils spacing to any
signals in X, Y, Z directions.
F7
E8
USB_HSD11P
USB_HSD11N
H11
J10
USB_HSD10P
USB_HSD10N
E11
F11
USB_HSD9P
USB_HSD9N
A11
B11
USB_HSD8P
USB_HSD8N
C10
D10
USB_HSD7P
USB_HSD7N
G11
H12
USB_HSD6P
USB_HSD6N
E12
E14
USB_HSD5P
USB_HSD5N
C12
D12
USBP5+ 22
USBP5- 22
----->NEW CARD
USB_HSD4P
USB_HSD4N
B12
A12
USBP4+ 23
USBP4- 23
----->BT
USB_HSD3P
USB_HSD3N
G12
G14
USBP3+ 25
USBP3- 25
----->USB PORT
USB_HSD2P
USB_HSD2N
H14
H15
USBP2+ 25
USBP2- 25
----->ESATA USB
USB_HSD1P
USB_HSD1N
A13
B13
USBP1+ 14
USBP1- 14
----->CAMERA
USB_HSD0P
USB_HSD0N
B14
A14
USBP0+ 25
USBP0- 25
----->USB PORT
IMC_GPIO8
IMC_GPIO9
IMC_PWM0/IMC_GPIO10
SCL2/IMC_GPIO11
SDA2/IMC_GPIO12
SCL3_LV/IMC_GPIO13
SDA3_LV/IMC_GPIO14
IMC_PWM1/IMC_GPIO15
IMC_PWM2/IMC_GPO16
IMC_PWM3/IMC_GPO17
A18
B18
F21
D21
F19
E20
E21
E19
D19
E18
IMC_GPIO18
IMC_GPIO19
IMC_GPIO20
IMC_GPIO21
IMC_GPIO22
IMC_GPIO23
IMC_GPIO24
IMC_GPIO25
G20
G21
D25
D24
C25
C24
B25
C23
IMC_GPIO26
IMC_GPIO27
IMC_GPIO28
IMC_GPIO29
IMC_GPIO30
IMC_GPIO31
IMC_GPIO32
IMC_GPIO33
IMC_GPIO34
IMC_GPIO35
IMC_GPIO36
IMC_GPIO37
IMC_GPIO38
IMC_GPIO39
IMC_GPIO40
IMC_GPIO41
B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18
RSMRST#
1
2
C577
SC10P50V2JN-4GP
3
Place these close SB700
E6
E7
USB_FSD12P
USB_FSD12N
0R0402-PAD
TP44
TP43
TP42
TP41
TP39
TP40
2K2R2F-GP
SB_RSMRST#_R D3
2
INTEGRATED uC
C
R415
6 CPU_THERMTRIP#_L
CLK48_USB_R2
DY
1%
USB_FSD13P
USB_FSD13N
CLK48_USB
USBP9+ 10
USBP9- 10
USBP7+ 22
USBP7- 22
----->WLAN
C
SB_GPO16 20
SB_GPO17 20
Strap Pin / define to use LPC or SPI ROM
B
1
R372
DY
2
0R2J-2-GP
1
30 RSMRST#_KBC
RSMRST#_SB
2
D30
CH751H-40PT
1
2
SUS_STAT#
4K7R2F-GP
R360
10R2F-L-GP
1
2
2
R378
100KR2J-1-GP
2
2
SB_TEST2
SB_TEST1
SB_TEST0
SB_TO_EC_PWRGD
10KR2J-3-GP
USB_PCOMP 1
R197
11K8R2F-GP
USB 1.1
2
10KR2J-3-GP
CLK48_USB
G8
USB 2.0
2
PM_PWRBTN#_R
SB_PWRGD
SUS_STAT#
C8
USB_RCOMP
GPIO
2
33
11
USBCLK/14M_25M_48M_OSC
USB OC
DY
2
R401
0R0402-PAD
Part 4 of 5
SB700
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S2/GPM9#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST2
TEST1
TEST0
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
BLINK/GPM6#
SMBALERT#/THRMTRIP#/GEVENT2#
NB_PWRGD
HD AUDIO
1
R213
1
R219
1
R201
1
R217
1
R216
D
1
31 PM_PWRBTN#
SHUTDOWN#/GPIO5
E1
E2
H7
F5
G1
H2
H1
K3
H5
H4
H3
Y15
W15
K4
K24
F1
J2
H6
F2
J6
W14
ACPI / WAKE UP EVENTS
3D3V_S0
TP38
21,22,30,33,38 PM_SLP_S3#
22,30,37,39 PM_SLP_S5#
1SB700_SLPS2
SB700-1-GP-U1
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-SB700_USB&GPIO_(2/5)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
17
of
44
5
4
3
2
1
PIDE_D[0..15]
23
U62B
SATA_RX0N
SATA_RX0P
26 SATA_TX1+_R
26 SATA_TX1-_R
C567 1
C558 1
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
SATA_TX1+
SATA_TX1-
AE10
AD10
SATA_TX1P
SATA_TX1N
26
26
C554 1
C552 1
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
SATA_RX1-_R
SATA_RX1+_R
AD11
AE11
SATA_RX1N
SATA_RX1P
AB12
AC12
SATA_TX2P
SATA_TX2N
SATA_TX3P
SATA_TX3N
AB14
AC14
SATA_RX3N
SATA_RX3P
AE14
AD14
SATA_TX4P
SATA_TX4N
AD15
AE15
SATA_RX4N
SATA_RX4P
AB16
AC16
SATA_TX5P
SATA_TX5N
AE16
AD16
SATA_RX5N
SATA_RX5P
1
1KR2F-3-GP
R208
1
2 SATA_CAL
2
2
R222
1MR2F-GP
V12
SATA_CAL
SATA_X1
Y12
SATA_X1
SATA_X2
AA12
SATA_X2
R221
SATA_X2_R
1
20R2J-2-GP
C379
SC12P50V2JN-3GP
L29
1
2
BLM15AG221SN-GP
20mil Width
SATA_ACT#/GPIO67
AA11
77mA
PLLVDD_SATA
W12
XTLVDD_SATA
1mA
C374
+3.3V_XTLVDD_SATA
L27
1
2
BLM15AG221SN-GP
SPI_DI/GPIO12
SPI_DO/GPIO11
SPI_CLK/GPIO47
SPI_HOLD#/GPIO31
SPI_CS#/GPIO32
G6
D2
D1
F4
F3
LAN_RST#/GPIO13
ROM_RST#/GPIO14
U15
J1
FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49
M8
M5
M7
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
P5
P8
R8
TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
C6
B6
A6
A5
B5
VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60
A4
B4
C4
D4
D5
D6
A7
B7
C370
SC1U6D3V2KX-GP
C
LAN_RST#
TP66
1
CR_WAKE#
24
TALERT#
LFB_ID2 LFB_ID1 LFB_ID0
LFB_ID0
LFB_ID1
LFB_ID2
AVSS
G7
Hynix
Qimonda
Samsung
*
C340
SC2D2U6D3V3KX-GP
F6
21
Local Frame Buffer Strapping List
Copy from Becks.
SCD1U10V2KX-4GP
SB700-1-GP-U1
5mA AVDD
D
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_D3
PIDE_D4
PIDE_D5
PIDE_D6
PIDE_D7
PIDE_D8
PIDE_D9
PIDE_D10
PIDE_D11
PIDE_D12
PIDE_D13
PIDE_D14
PIDE_D15
+3.3V_AVDD_HWM
2
1
3D3V_S0
W11
SC2D2U6D3V3KX-GP
2
20mil Width
+1.2V_PLLVDD_SATA
1
1D2V_S0
B
SATA_RX2N
SATA_RX2P
AD24
AD23
AE22
AC22
AD21
AE20
AB20
AD19
AE19
AC20
AD20
AE21
AB22
AD22
AE23
AC23
3D3V_S5
L23
1
1
C378
SC12P50V2JN-3GP
1
1
AE12
AD12
SATA_TX3+ AD13
SATA_TX3- AE13
IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23
IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30
PIDE_IORDY 23
PIDE_IRQ14 23
PIDE_A0
23
PIDE_A1
23
PIDE_A2
23
PIDE_DACK# 23
PIDE_DREQ 23
PIDE_IOR# 23
PIDE_IOW# 23
PIDE_CS#0 23
PIDE_CS#1 23
0
0
0
0
0
1
0
1
0
B
2
BLM15AG221SN-GP
C337
2
20R2J-2-GP
20R2J-2-GP
SATA_RX3SATA_RX3+
X4
XTAL-25MHZ-96GP
2
R461 1
R460 1
AA24
AA25
Y22
AB23
Y23
AB24
AD25
AC25
AC24
Y25
Y24
1
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
IDE_IORDY
IDE_IRQ
IDE_A0
IDE_A1
IDE_A2
IDE_DACK#
IDE_DRQ
IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#
2
C664 1
C663 1
1
2
SATA_RX1SATA_RX1+
Part 2 of 5
ATA 66/100/133
AB10
AC10
SPI ROM
SATA_RX0SATA_RX0+
SATA_RX0-_R
SATA_RX0+_R
25
25
C
SATA_TX0P
SATA_TX0N
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
25 SATA_TX3+_R
25 SATA_TX3-_R
ESATA
SB700
AD9
AE9
HW MONITOR
SATA ODD
20R2J-2-GP SATA_TX0+
20R2J-2-GP SATA_TX0-
C545 1
C547 1
26
26
D
R215 1
R212 1
SERIAL ATA
26 SATA_TX0+_R
26 SATA_TX0-_R
SATA HDD
2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP
SATA PWR
C542 1
C543 1
LFB_ID0 to LFB_ID2 got internal PU to S5.
3D3V_S5
R358 1
R356 1
R354 1
Layout connect to Cap then GND
LFB_ID0
LFB_ID1
LFB_ID2
R355 1
R357 1
R359 1
DY
DY
DY
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
2 10KR2J-3-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-SB700_SATA-IDE_(3/5)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
18
of
44
4
3
2
2
1
1
2
1
2
1
1
2
BLM15AG221SN-GP
2
1
2
1
2
1
C620
T10
U10
U11
U12
V11
V14
W9
Y9
Y11
Y14
Y17
AA9
AB9
AB11
AB13
AB15
AB17
AC8
AD8
AE8
1D2V_S0
L49
+3.3V_AVDDCK
AVDDCK_1.2V
K17
+1.2V_AVDDCK L22
16mA
SB700-1-GP-U1
C343
1
2
BLM15AG221SN-GP
C336
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
C560
GROUND
1
2
BLM15AG221SN-GP
220 ohm @ 100MHz, 300mA
2
1
2
1
1D2V_S5
C604
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
2
1
2
C606
PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21
5V_S0
2
1
R459
1KR2F-3-GP
3D3V_S0
1
D33
C654
1
H18
J17
J22
K25
M16
M17
M21
P16
2
2
+3.3V_ALW_R_AVDDC
E9
1D2V_S5
1
3D3V_S5
1
AVDDC
1
1
J16
CH751H-40PT
1D8V_S0
D34
1
2
PLL
44mA
C584
+5V_VREF1
AE7
AVDDCK_3.3V
1
7mA
V5_VREF
2
DY
4mA
USB I/O
1
C339
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5
SC2D2U6D3V3KX-GP
A16
B16
C16
D16
D17
E17
F15
F17
F18
G15
G17
G18
AVDDTX:330mA
AVDDRT:209mA
C571
2
A10
B10
2
3.3V_S5 I/O
CORE S5
USB_PHY_1.2V_1
USB_PHY_1.2V_2
G2
G4
113mA
2
1
2
1
2
1
2
1
2
S5_1.2V_1
S5_1.2V_2
C610
SC1U10V3KX-3GP
1
101mA
SCD1U10V2KX-4GP
SC1U10V3KX-3GP
2
Part 5 of 5
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
A15
B15
C14
D8
D9
D11
D13
D14
D15
E15
F12
F14
G9
H9
H17
J9
J11
J12
J14
J15
K10
K12
K14
K15
L48
20mil Width
50mil Width
SC22U6D3V5MX-2GP
C342
+1.2V_ALW_SUS_R
SC1U6D3V2KX-GP
C341
A17
A24
B17
J4
J5
L1
L2
SC1U6D3V2KX-GP
367mA
SCD1U10V2KX-4GP
C582
SCD1U10V2KX-4GP
C589
AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
SATA I/O
1
C372
2
1
2
1
2
1
2
1
SB700
220 ohm @ 100MHz, 2A
1
SC22U6D3V5MX-2GP
2
C345
SC1U6D3V2KX-GP
C651
AA14
AB18
AA15
AA17
AC18
AD17
AE17
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7
SCD1U10V2KX-4GP
C655
SCD1U10V2KX-4GP
SC1U10V3KX-3GP
C570 C338
SC1U10V3KX-3GP
SC22U6D3V5MX-2GP
1
C349
U62E
16mA
A-LINK I/O
1
2
1
1
2
1
2
1
1
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
844mA
+3.3V_AVDD_USB
2
C346
2
CLKGEN I/O
IDE/FLSH I/O
1
2
1
2
1
2
1
2
2
2
DY
C347
1
2
HCB2012KF-221T30-GP
50mil Width
2
CORE S0
PCI/GPIO I/O
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
2
C360
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C665
Use Plane Shape for +3.3V_AVDD_USB
L46
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
DY
C365
SCD1U10V2KX-4GP
C359
SC1U6D3V2KX-GP
C355
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP
C671
C358
3D3V_S5
P18
P19
P20
P21
R22
R24
R25
1
2
HCB2012KF-221T30-GP
B
286mA
SC10U6D3V5KX-1GP
71mA
+1.2V_AVDD_SATA
50mil Width
C362
2
HCB2012KF-221T30-GP
POWER
SC1U6D3V2KX-GP
C350
SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP
220 ohm 2A
3D3V_S5
VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4
SC1U6D3V2KX-GP
C371
SCD1U10V2KX-4GP
DY
C375
SCD1U10V2KX-4GP
C376
SCD1U10V2KX-4GP
C656
50mil Width
C
C351
1D2V_S0
L21
1
+1.2V_RUN_CKVDD
Y20
AA21
AA22
AE25
+1.2V_PCIE_VDDR
1
2
HCB2012KF-221T30-GP
L61
CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4
L21
L22
L24
L25
C361
SC1U6D3V2KX-GP
DY
C356
SCD1U10V2KX-4GP
C368
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
C369
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C650
L25
1D2V_S0
C377
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
Part 3 of 5
604mA
71mA
Use Flash I/O:+1.8V / IDE:+3.3V
SC1U6D3V2KX-GP
SC22U6D3V5MX-2GP
1D2V_S0
C364
SC1U6D3V2KX-GP
1D8V_S0
C357
SC1U6D3V2KX-GP
C354
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C373
SCD1U10V2KX-4GP
SC22U6D3V5MX-2GP
D
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
L15
M12
M14
N13
P12
P14
R11
R15
T16
SC22U6D3V5MX-2GP
3D3V_S0
+1.2V_RUN_VDD
SB700
1
U62C
L9
M9
T15
U9
U16
U17
V8
W7
Y6
AA4
AB5
AB21
1
2
5
PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8
F9
2
AVSSC
AVSSCK
A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24
D
C
P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25
B
L17
SB700-1-GP-U1
CH751H-40PT
3D3V_S5
3D3V_S0
1
1
2
BLM15AG221SN-GP
C333
C344
SC2D2U6D3V3KX-GP
2
20mil Width
2
1D2V_S0
1
<Core Design>
+1.2V_AVDDCK
L26
A
Wistron Corporation
2
1
1
2
1
1
2
1
2
2
DY
C334
SC22U6D3V5MX-2GP
C335
SCD1U10V2KX-4GP
C352
SCD1U10V2KX-4GP
DY
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
A
C348
+3.3V_AVDDCK
L24
1
BLM15AG221SN-GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
20mil Width
C353
SC2D2U6D3V3KX-GP
Title
ATi-SB700_POWER&GND_(4/5)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
19
of
44
5
4
3
2
REQUIRED STRAPS
1
DEBUG STRAPS
3D3V_S5
3D3V_S0
D
D
1 R445
1 R452
1 R463
1 R447
1 R475
1 R456
1 R467
1 R472
2
2
2
2
2
2
2
2
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
C
10KR2J-3-GP
1 R446
1 R453
1 R462
1 R450
1 R476
1 R457
1 R473
1 R434
1 R438
2
2K2R2F-GP
2
2K2R2F-GP
2
2
2K2R2F-GP
2K2R2F-GP
2
2
10KR2J-3-GP
2K2R2F-GP
2
10KR2J-3-GP
2
2
10KR2J-3-GP
2K2R2F-GP
2
10KR2J-3-GP
2
2
10KR2J-3-GP
2
2
10KR2J-3-GP
2K2R2F-GP
2
2K2R2F-GP
1 R441
1 R405
1 R368
1 R190
1 R431
16
16
16
16
16
16
16
16
DY DY DY DY DY DY DY DY
10KR2J-3-GP
2
2K2R2F-GP
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
DY
2
2
DY
2K2R2F-GP
2
10KR2J-3-GP
DY
10KR2J-3-GP
DY DY
1 R352
1 R361
1 R444
1 R211
C
16
16
16
16,30
16
16,21
17
17
17
16
16
10KR2J-3-GP
CLK_PCI_2
CLK_PCI_3
CLK_PCI_1
LPCCLK0
LPCCLK1
RTCCLK
SB_AZ_RST#
SB_GPO16
SB_GPO17
CLK_PCI_4
CLK_PCI_5
1 R468
1 R439
1 R442
1 R399
1 R363
1 R191
1 R418
1 R353
1 R437
2
DY DY DY DY DY DY DY DY
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
10KR2J-3-GP
2
2
DY DY DY DY DY DY DY
2K2R2F-GP
2
2K2R2F-GP
2
10KR2J-3-GP
10KR2J-3-GP
2
DY DY DY
10KR2J-3-GP
1 R362
1 R443
1 R210
3D3V_S0
REQUIRED SYSTEM STRAPS
CLK_PCI_2
B
PULL
HIGH
CLK_PCI_3
WatchDOG
(NB_PWRGD)
ENABLED
CLK_PCI_4
CLK_PCI_5
LPCCLK0
ENABLE PCI
MEM BOOT
USE
DEBUG
STRAPS
WatchDog
(NB_PWRGD)
DISABLED
IGNORE
DEBUG
STRAPS
DEFAULT
DEFAULT
RTCCLK
AZ_RST#
CLKGEN
ENABLED
INTERNAL
RTC
IMC
ENABLED
(Use Internal)
RESERVED
PULL
LOW
LPCCLK1
DISABLE PCI CLKGEN
MEM BOOT
DISABLED
DEFAULT
(Use External)
DEFAULT
ROM TYPE:
DEFAULT
H, H = Reserved
EXT. RTC
(PD on X1,
apply
32KHz to
RTC_CLK)
H, L = SPI ROM
IMC
DISABLED
DEFAULT
PCI_AD28 PCI_AD27 PCI_AD26
SB_GPO17 , SBGPO16
L, H = LPC ROM
DEFAULT
PULL
HIGH
USE
LONG
RESET
(DEFAULT)
PULL
LOW
USE
SHORT
RESET
PCI_AD25
PCI_AD24
PCI_AD23
USE DEFAULT
PCIE STRAPS Reserved
USE PCI
PLL
USE ACPI
BCLK
USE IDE
PLL
(DEFAULT)
(DEFAULT)
(DEFAULT)
(DEFAULT)
(DEFAULT)
BYPASS
PCI PLL
BYPASS
ACPI
BCLK
BYPASS IDE
PLL
USE EEPROM
PCIE STRAPS
Reserved
PCI_AD30
PCI_AD29
B
Reserved
L, L = FWH ROM
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK
Note: SB700 has 15K internal PU FOR PCI_AD[30:23]
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ATi-SB700_STRAPPING_(5/5)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
20
of
44
4
3
5V_S0
2
1
1
C413
FAN1_VCC
FAN1
R246
CH751H-40PT
D16
4
1
2
1
2
10KR2J-3-GP
2
1
1
2
2
1
2
2
D
C415
SC2200P50V2KX-2GP
C94
SC4D7U6D3V5KX-3GP
C419
1
5V_S0
SCD1U16V2ZY-2GP
C99
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
1
1
FAN1_VCC
2
5
2
3
FAN1_FG1
5
C414
D
ACES-CON3-GP-U1
SC1KP50V2KX-1GP
FAN1_VCC
U23
R99
ALERT#
THERM#
THERM_SET
RESET#
R104
49K9R2F-L-GP
C
Q23
MMBT3904-3-GP
B
SC470P50V2KX-3GP
E
8
10
12
1
SGND1
SGND2
SGND3
C474
DY
2
5
17
G792_DXN2
CPU SENSOR
G48
74.00792.A79
G87
H_THERMDC
G792_DXN2
G792_DXN3
G792SFUF-GP
2
DXP1:108 Degree
DXP2:H/W Setting
DXP3:88 Degree
DGND
DGND
SC2200P50V2KX-2GP
G37
6
G792_DXP3
C139
2
1
1
G792_ALERT#
15
HW_THRM_SHDN# 13
V_DEGREE 3
2
C471
C427
NB_THERMDP 11
C428
NB SENSOR
H_THERMDA
SC2200P50V2KX-2GP
SC470P50V2KX-3GP
G88
G792_DXN3
2
1
C
NB_THERMDN 11
1
1
1
SC2200P50V2KX-2GP
2
2
4K99R2F-L-GP
2
2
SCD1U16V2ZY-2GP
V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC
1
DXP1
DXP2
DXP3
G792_DXP2
1
7
9
11
FAN1_FG1
G792_32K
SMBD_G792
SMBC_G792
2
G792_DXP2
G792_DXP3
1
4
14
16
18
19
1
6 H_THERMDA
R97
FAN1
FG1
CLK
SDA
SCL
NC#19
2
VCC
DVCC
2
C83
Setting T8 as
100 Degree
C
5V_S0
1
100R2J-2-GP
6
20
2
5V_S0
5V_G792_S0
2
1
1
3D3V_S0
5V_S5
U66
VCC
4
Y
U19
1
A
2
GND
3
PM_SLP_S3#
17,22,30,33,38 PM_SLP_S3#
PM_SLP_S3#
16,20 RTCCLK
3D3V_S5
1
B
2
A
3
74LVC1G08GW-1-GP
VCC
5
Y
4
R106
10R2J-2-GP
1
2
GND
74LVC1G08GW-1-GP
R103
10KR2J-3-GP
2
DY
R101
100KR2J-1-GP
R107
18
2
2
DY
R108
10KR2J-3-GP
1
4K7R2F-GP
2
G792_RESET#
1
1
PWROK
1
33
R105
100KR2J-1-GP
2
R102
G792_32K
1
B
5
1
TALERT#
2
G792_ALERT#
0R2J-2-GP
DY
3D3V_AUX_S5
3D3V_S0
B
SMBUS
B
5
6
7
8
3D3V_S0
3D3V_S0
1
RN9
SRN4K7J-10-GP
30
2
TP67
TPAD60
KBC_SCL2
KBC_SCL2
3
4
2
5
1
6
SMBC_G792
D
HW_THRM_SHDN#
S
Q22
2N7002-11-GP
SMBD_G792
1
1
30
D20
CH751H-40PT
R281
SMBD_G792 26
KBC_SDA2
31
3D3V_AUX_S5
U56
2
A
EC_RST#
KBC_SDA2
2
10KR2J-3-GP
SMBC_G792 26
G
3D3V_AUX_S5
D19
2N7002DW-1-GP
84.27002.D3F
4
3
2
1
R278
10KR2J-3-GP
1
S5_ENABLE
2
A
3
GND
1
30
2
C469
<Core Design>
B
VCC
5
Y
4
A
Wistron Corporation
PWR_S5_EN 36
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
74LVC1G08GW-1-GP
Title
SCD1U16V2ZY-2GP
THERMAL G792
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
21
of
44
5
4
3
2
1
NEWCARD Connector
WLAN Connector
Newcard Head
Newcard Frame
NEWCARD1
SKT2
2
D
CARDBUS2P-15-GP
21.H0146.001
USBP7USBP7+
1
2
23
23
3 CLK_PCIE_NEW
3 CLK_PCIE_NEW#
17
CPPE#
TP31
CLK_PCIE_WLAN# 3
CLK_PCIE_WLAN 3
CPPE#
1CONN_CLKREQ#
PERST#
3D3V_NEW_S5
30
30
C531
PCIE_NBRX_WLANTX_N1 10
PCIE_NBRX_WLANTX_P1 10
SCD1U16V2ZY-2GP
17 SMBDAT1_SB
17 SMBCLK1_SB
TP29
TP28
2
E51_RxD
E51_TxD
1
10,17,25 SB_PCIE_WAKE#
PCIE_NBTX_C_WLANRX_N1 10
PCIE_NBTX_C_WLANRX_P1 10
17
17
1CONN_TP2
1CONN_TP3
CPUSB#
USBP5+
USBP5-
1D5V_NEW_S0
5V_AUX_S5
C307
28
NP2
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
C
1
NP1
27
C522
SCD1U16V2ZY-2GP
LED_WWAN#
LED_WLAN#
LED_WPAN#
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54
E51_RxD
E51_TxD
BT_BUSY
WIFI_BUSY
TP46
SC10U10V5ZY-1GP
1
1
1
TP47
TP48
TP49
1
1
17
17
C
BT_BUSY
WIFI_BUSY
MINI_REQ#
10 PCIE_NBRX_NEWTX_P0
10 PCIE_NBRX_NEWTX_N0
2
SMBCLK1_SB
SMBDAT1_SB
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
3
5
7
9
11
13
15
TP45
1
RF_ON/OFF#
PLT_RST1#_WLAN
1
0R0402-PAD
2
R243
PLTRST_SYS#
3D3V_S5
1
2
23,24,25,26,30,33
4
6
8
10
12
14
16
MINI_WAKE#
10 PCIE_NBTX_C_NEWRX_P0
10 PCIE_NBTX_C_NEWRX_N0
C538
SCD1U16V2ZY-2GP
1D5V_S0
2
C313
SC10U10V5ZY-1GP
3D3V_S0
53
NP1
1
1
3D3V_NEW_S0
SKT4
2
1
D
CARDBUS26P-7GP
62.10024.861
Place them Near to Chip
SKT-MINI52P-8-GP
2
1
1D5V_S0
C519
SCD1U16V2ZY-2GP
1D5V_NEW_S0
1
2
C524
SCD1U16V2ZY-2GP
30
2
RF_ON/OFF#
B
3D3V_S5
R242
10KR2J-3-GP
U58
C540
SCD1U16V2ZY-2GP
3_3VIN
3_3VOUT
1_5VIN
1_5VOUT
AUXIN
AUXOUT
2
2
2
3
12
11
17
15
C529
SCD1U16V2ZY-2GP
1
1
3D3V_S0
1
SYSRST#
CPPE#
CPUSB#
PERST#
SHDN#
3_3VIN
3_3VOUT
1_5VOUT
1_5VIN
NC#16
G577BR91U-GP
1
18
19
21
STBY#
RCLKEN
OC#
GND
17,30,37,39 PM_SLP_S5#
6
10
9
8
20
3D3V_NEW_S5
4
5
13
14
16
3D3V_S0
3D3V_NEW_S0
1D5V_NEW_S0
1D5V_S0
1
PLTRST#_577
1
2
R319 0R0402-PAD CPPE#
CPUSB#
PERST#
C532
SCD1U16V2ZY-2GP
2
PLTRST_SYS#
GND
23,24,25,26,30,33
7
1
C539
SCD1U16V2ZY-2GP
2
1
C526
SCD1U16V2ZY-2GP
2
1
C393
SC10U10V5ZY-1GP
2
1
C525
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
2
C409
2
1
RF_ON/OFF#
B
1
C520
SCD1U16V2ZY-2GP
1D5V_S0 3D3V_S5
2
3D3V_NEW_S0
3D3V_S0
17,21,30,33,38 PM_SLP_S3#
1
TP60
NEWCARD_OC#
<Core Design>
A
A
Wistron Corporation
3D3V_S5
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
RN32
1
2
4
3
CPUSB#
CPPE#
Title
WLAN/NEW CARD
SRN10KJ-5-GP
Size
A3
DY
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
22
of
44
5
4
3
2
1
HYPER FLASH
Bluetooth
18 PIDE_D[0..15]
D
D
HYPER1
CN1
41
PIDE_D13
PIDE_D12
PIDE_D11
PIDE_D10
PIDE_D9
PIDE_D8
C
18
PIDE_A1
18
PIDE_IORDY 18
C402
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PIDE_D0
PIDE_D1
PIDE_D2
PIDE_IOW# 18
DY
PIDE_D3
PIDE_D4
1
ACES-CON10-5-GP-U1
PIDE_D15
PIDE_D14
PIDE_A0
1D8V_S0
C407
2
18 PIDE_DREQ
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIDE_CS#0 18
22
23
24
25
C408
DY
SCD1U16V2ZY-2GP
18 PIDE_IOR#
21
1
DY
18 PIDE_IRQ14
18 PIDE_DACK#
12
2
3
4
5
2
3D3V_BT_S0
20R2J-2-GP
1
PIDE_A2
SC10U10V5ZY-1GP
22 WIFI_BUSY
30 BLUETOOTH_EN
22
BT_BUSY
18
SCD1U16V2ZY-2GP
2
3
4
5
6
7
8
9
10
USBP4+
USBP4-
NP1
1
R240
1
17
17
18 PIDE_CS#1
2
11
1
DY
PIDE_D5
PIDE_D6
PIDE_D7
HYPER_RST#
C
NP2
42
R239
1
CARDBUS-SKT102-GP-U
2
20.I0070.001
0R3-0-U-GP
DY
DY
U48
4
3
2
1
BLUETOOTH_EN 30
3D3V_BT_S0
1D8V_S0
EC14
1
<DUMMY>
R244
10KR2J-3-GP
DY
2
1
C390
2
SC1U10V3ZY-6GP
B
R237
10KR2J-3-GP
SC270P50V2KX-1GP
G5281RC1U-GP
74.05281.093
1
GND
EN
OUT
IN#1
2
IN#5
IN#6
IN#7
IN#8
GND
2
5
6
7
8
9
1
SCD1U16V2ZY-2GP
2
C391
1
3D3V_S0
22,24,25,26,30,33
D14
PLTRST_SYS#
1
B
HYPER_RST#
2
CH751H-40PT
17
D15
IDE_RST#
1
DY
2
CH751H-40PT
DY
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HYPER FLASH/BT
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
23
of
44
2
DLW21HN900SQ2LGP
2
R408
56R2F-1-GP
6
5
4
3
2
1
TPA0+
TPA0TPB0+
TPB0-
GND
GND
TPA0+
TPA0TPB0+
TPB0-
D
4
2
1
1
SKT5
L17
3
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
2
56R2F-1-GP
2
1
2
2
56R2F-1-GP
C652
SKT-1394-4P-30-GP
L16
1
DLW21HN900SQ2LGP
1
C569
SC1KP50V2KX-1GP
C618
1
2
Place Choke close to CONN
R409
1
2
SC220P50V2KX-3GP
4
1
2
3
2
2
1
1
1
C559
1
56R2F-1-GP
1
2
SC4D7U6D3V3KX-GP
2
2
SCD1U10V2KX-4GP
C557
SCD1U10V2KX-4GP
C612
C578
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
C598
APVDD
2
L47 2
1
BLM15BB121SN-GP
2
1
R411
R427
5K11R2F-L1-GP
DY
2
0R3-0-U-GP
SCD1U10V2KX-4GP
2
C615
DVDD18
R402
1
C616
1
1
2
1
2
1D8V_S0
C601
R410
CLOSE TO CHIP
SCD1U10V2KX-4GP
C603
SCD1U10V2KX-4GP
D
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C617
TAV33
2
0R0603-PAD
1
R413
1
SCD33U10V3KX-3GP
3D3V_S0
1
1
3
2
4
1
5
R480
Q12
AO3403-GP
3D3V_S0
3D3V_CARD
1
DY
CR_CPPE# 17
GND
24
23
22
21
20
19
18
17
16
15
14
13
MDIO13
MDIO14
1
2
3D3V_S0
CR1_PCTLN
CR1_CD0N
CR1_CD1N
DVDD18
2
D29
1
CH751H-40PT
CR_WAKE# 18
CR_CPPE_R#
RN33
4
3 SRN0J-6-GP
MDIO0_R
MDIO1_R
MDIO2 1
MDIO3 2
RN34
4
3 SRN0J-6-GP
MDIO2_R
MDIO3_R
MDIO8 1
MDIO9 2
RN35
4
3 SRN0J-6-GP
MDIO8_R
MDIO9_R
MDIO10 1
MDIO11 2
RN36
4
3 SRN0J-6-GP
MDIO10_R
MDIO11_R
PLTRST_SYS#
MDIO5
1
1
2 C561 SCD1U10V2KX-4GP
2 C562 SCD1U10V2KX-4GP
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
2
2 200KR2F-L-GP
MDIO12
xD_CD
R375 1
2 200KR2F-L-GP
MDIO14
1
2
2
L70
MLVG0402220NV09BP-GP
1
L68
MLVG0402220NV09BP-GP
2
L69
MLVG0402220NV09BP-GP
1
MDIO0_R
L66
1
C555
2
14
MS_VCC
23
SD_VCC
33
XD_VCC
MDIO13
MDIO12
MCLK
MDIO7
MDIO14
MDIO4
MDIO6
xD_CD
1
2
3
4
5
6
7
34
XD_R/B
XD_RE
XD_CE
XD_CLE
XD_ALE
XD_WE
XD_WP
XD_CD_SW
MDIO0_R
MDIO1_R
MDIO2_R
MDIO3_R
MDIO8_R
MDIO9_R
MDIO10_R
MDIO11_R
8
9
26
27
28
30
31
32
XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7
NP1
NP2
C566
NP1
NP2
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
25
29
10
11
MDIO0_R
MDIO1_R
MDIO2_R
MDIO3_R
SD_CMD
SD_CLK
SD_WP_SW
SD_CD_SW
12
24
35
36
MDIO4
MCLK
MDIO6
CR1_CD0N
MS_DATA0
MS_DATA1
MS_DATA2
MS_DATA3
19
20
18
16
MDIO0_R
MDIO1_R
MDIO2_R
MDIO3_R
MS_SCLK
MS_INS
MS_BS
15
17
21
MCLK
CR1_CD1N
MDIO4
4IN1_GND
4IN1_GND
13
22
GROUND
GROUND
37
38
B
CARD-PUSH-36P-3-GP
20.I0080.001
<Core Design>
U37
R403 1
C319
SC220P50V2KX-3GP
MDIO1_R
2 10KR2J-3-GP MDIO13
L67
MLVG0402220NV09BP-GP
R391 1
MDIO2_R
C597
SC15P50V2JN-2-GP
2 10KR2J-3-GP MDIO6
L64
MLVG0402220NV09BP-GP
X-24D576MHZ-44GP
R333 1
MDIO3_R
3D3V_CARD
2
L65
MLVG0402220NV09BP-GP
CR1_CD1N
MDIO8_R
2 10KR2J-3-GP MDIO7
L63
MLVG0402220NV09BP-GP
2 4K7R2F-GP
R387 1
MDIO9_R
C609
SC15P50V2JN-2-GP
R334 1
L62
MLVG0402220NV09BP-GP
X3
1
CR1_CD0N
MDIO10_R
XOUT
2
1MR2F-GP
2 4K7R2F-GP
MLVG0402220NV09BP-GP
R380
1
MDIO11_R
R339 1
A
MCLK
2
22R2J-2-GP
MCLK
PCIE_NBTX_C_CARDRX_N3 10
PCIE_NBTX_C_CARDRX_P3 10
R336
8K2R2F-1-GP
3D3V_S0
XIN
R369 1
PCIE_NBRX_CARDTX_P3 10
PCIE_NBRX_CARDTX_N3 10
1
3 CLK_PCIE_CARD#
3 CLK_PCIE_CARD
APVDD
1
2
3
4
5
6
7
8
9
10
11
12
APVDD
22,23,25,26,30,33
2
3D3V_CARD
B
JMB380-QGAZ0A-GP
C593
CARD1
SCD1U10V2KX-4GP
MDIO0 1
MDIO1 2
1
49
TCPS
MDIC13
MDIC14
CR1_LEDN_GPIO0
DV33
DV33
DV18
CR1_PCTLN_GPIO1
CR1_CD0N_GPIO2
CR1_CD1N_GPIO3
SEECLK
SEEDAT
2
MDIO3
MDIO2
MDIO1
MDIO0
DV18
TXIN/TOSC
TXOUT
MDIO7
MDIO6
MDIO5
MDIO4
DV33
MDIO3
MDIO2
MDIO1
MDIO0
XRST#
XTEST
APCLKN
APCLKP
APVDD
APGND
APREXT
APRXP
APRXN
APV18
APTXN
APTXP
3D3V_S0
37
38
39
40
41
42
43
44
45
46
47
48
C572
SC4D7U6D3V3KX-GP
XIN
XOUT
MDIO7
MDIO6
MDIO5
MDIO4
For SD/MS Card Power
0R0603-PAD
SCD1U10V2KX-4GP
DVDD18
402KR2F-GP
R620
SCD1U10V2KX-4GP
TREXT
TPBIAS_1
TPA1P
TPA1N
TPB1P
TPB1N
TAV33
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
U61
R337 2
1
36
35
34
33
32
31
30
29
28
27
26
25
CR1_PCTLN
C
1
R348
1KR2F-3-GP
D
2
S
20mil Trace
1
G
TREXT
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
TAV33
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
Q47
2N7002-11-GP
D
G
CR_CPPE_R#
DY
S
3D3V_S0
10KR2J-3-GP
D
C
1
2
2
2
G
R412
12KR2J-L-GP
2
CR1_CD0N
1
CR1_CD1N
A
Wistron Corporation
3
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CH715FPT-GP
1394/CARD READER
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
24
of
44
5
4
3
USB PORT
U46
SC1U16V3ZY-GP
2
C382
1
G545B2P8U-GP
1
EC13
TC1
ST100U10VDM-5GP
10 PCIE_NBRX_LANTX_P2
10 PCIE_NBRX_LANTX_N2
2
2
C381
1
10 PCIE_NBTX_C_LANRX_P2
10 PCIE_NBTX_C_LANRX_N2
8
7
6
5
2
USB_PWR_EN#
GND
OUT#8
IN#2
OUT#7
IN#3
NC#6
EN/EN#
OC#
SC1KP50V2KX-1GP
1
2
3
4
1
CN8
5V_USB1_S3
1
5V_S5
SCD1U16V2ZY-2GP
30 USB_PWR_EN#
50 mil
400uS rise time
Supply 1.5~1.1A
D
50 mil
2
17
17
USBP3+
USBP3-
17
17
USBP2+
USBP2-
18 SATA_TX3-_R
18 SATA_TX3+_R
18 SATA_RX318 SATA_RX3+
43
42
2
41
NP1
1
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
46
45
44
NP2
D
3D3V_S5
CLK_PCIE_LAN 3
CLK_PCIE_LAN# 3
PLTRST_SYS# 22,23,24,26,30,33
SB_PCIE_WAKE# 10,17,22
3D3V_S0
USB_PWR_EN#
5V_S5
1D8V_S3
ACES-CONN40D-1-GP
C
C
5V_USB1_S3
SKT3
5
NP1
1
1
2
1
2
1
2
1
C704
SC1U10V2KX-1GP
2
1
C707
SCD1U16V2ZY-2GP
2
C73
SC10U10V5ZY-1GP
SC1U10V2KX-1GP
DY
C62
B
DY
I/O1
2
VREF GND
1
I/O2
C64
SC1U10V2KX-1GP
4
DY
C65
SCD1U16V2ZY-2GP
3
C401
SC1U10V2KX-1GP
U47
USBP_05V_USB1_S3
C406
SC1U10V2KX-1GP
B
C398
SCD1U16V2ZY-2GP
2
SKT-USB-122-GP
1D8V_S3
1
3D3V_S5
2
SRN0J-6-GP
5V_S5
2
3
4
NP2
6
1
USBP_0USBP_0+
2
1
2
3
4
1
USBP0USBP0+
2
USBP0USBP0+
1
RN27
17
17
USBP_0+
PJSR05-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB & DAUGHTER CONN
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
25
of
44
5
4
3
2
SATA HDD Connector
1
SATA ODD Connector
ODD1
SATA1
8
23
NP1
1
C325
A
2
SC10U10V5ZY-1GP
C
1
NP2
SKT-SATA7P+6P-14-GP-U1
2
K
1
1
K
DY
TPAD28 R331
10KR2J-3-GP
D8
SR24-GP
DY
TP59
NP1
ODD_DP P1
P2
P3
ODD_MD P4
P5
P6
9
1
TC20
SCD1U16V2ZY-2GP
5V_S0
C546
D21
SSM24PT-GP
2
C323
SCD1U16V2ZY-2GP
2
1
C324
SC10U10V5ZY-1GP
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP2
24
3D3V_S0
SC22U6D3V5MX-2GP
18 SATA_RX118 SATA_RX1+
5V_S0
1
SATA_RX0SATA_RX0+
2
18
18
2
3
4
5
6
7
1
SATA_TX0+_R
SATA_TX0-_R
A
Close to HDD
18
18
D
S1
S2
S3
S4
S5
S6
S7
18 SATA_TX1+_R
18 SATA_TX1-_R
2
D
C
TYCO-CON22-GP-U
LAUNCH BD CONN
LED BD CONN
PWRBTN BD CONN
1
SC1U10V2KX-1GP
C670
3D3V_AUX_S5
TPAD2
B
3D3V_S5
10
3D3V_S0
3D3V_S0
2
R67
470R2J-2-GP
1
KBC_PWRBTN# 30
1
R481
10KR2J-3-GP
SMBC_G792 21
SMBD_G792 21
I2C_INT#
30
LAUNCH_RST
1
PWRBTN_LED 30
DY
D
2
3
4
6
9
2 C56
LAUNCH_RST SCD1U16V2ZY-2GP
2
TP56
TP55
TPAD60 TPAD60
1
SCD1U16V2ZY-2GP
1
6
5
4
3
2
R238
100KR2J-1-GP
Q32
2N7002-11-GP
G
7
FOX-CON4-12-GP-U
1
SC1U10V2KX-1GP
C669
C695
DY
PLTRST_SYS# 22,23,24,25
S
2
ACES-CON6-5GP-U1
SCD1U16V2ZY-2GP
2
1
2
8
2
1
5
1
ETY-CON8-6-GP
SCD1U16V2ZY-2GP
C392
CN3
3D3V_S5
C659
2
0R0603-PAD
CN4
1
2
3
4
5
6
7
8
1
C740
SC1KP50V2JN-2GP
2
1
30 WLANONLED#
30 PWR_LED#
30
BAT_LED#
30 BATLOW_LED#
1
R63
2
2
B
C660
2
SCD1U16V2ZY-2GP
1
3D3V_S0
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
HDD/CDROM/LED/LAUNCH
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
26
of
44
A
B
C
D
E
5V_S0
KBC_BEEP_R
1
2
47KR2F-GP
1
SB_AZ_CODEC_SYNC
17
SB_AZ_CODEC_BITCLK
SC100P50V2JN-3GP
AUD_VAUX
2
10KR2J-3-GP
5V_AUDIO_S0
DY
1
R379
17
C621
DY
5V_AUDIO_S0
5V_AUDIO_S0
1
4
2
4
1
5
2
2
SB_AZ_CODEC_RST# 17
SCD1U16V2KX-3GP
2
2
SC1U16V3ZY-GP
C581
1
R347
2
KBC_BEEP
R365
SET
OUT
C579
G923-475T1UF-GP
C583
SCD1U16V2KX-3GP
47KR2F-GP
4K7R2J-2-GP
31
C564
1
AUD_BEEP
2
1
1
2
MCP_SPKR_R
SHDN#
GND
IN
SCD1U16V2KX-3GP
2
SC1U16V3ZY-GP
C588
1
2AUD_PC_BEEP
SCD1U16V2KX-3GP
SB_SPKR
R346
SCD1U16V2KX-3GP
17
C563
1
C568
2
C575
4
1
1
U41
1
2
3
5V_AUDIO_S0
SC20P50V2JN-1GP
1
1
TP36
TPAD30
AUD_CEN_OUT
1
TP35
TPAD30
1
AUD_LFE_OUT
C613
MICIN_JD#
R345
100KR2J-1-GP
D
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP
R386
1
2
39K2R2F-L-GP
SCD1U16V2KX-3GP
2
39K2R2F-L-GP
1
1
1
2
2
R349
1
C594
2
MICIN_L
2
SC2D2U10V3KX-1GP
MICIN_R
2
SC2D2U10V3KX-1GP
1
Fortemedia
ADI
NC
LINEIN_JD#
GND
R198
100KR2J-1-GP
21
22
16
17
MIC1-L/PORT-B-L
MIC1-R/PORT-B-R
MIC2-L/PORT-F-L
MIC2-R/PORT-F-R
SENSE_B
SENSE_A
2
34
13
44
43
LINEIN_JD#
10KR2F-2-GP
S
G
SDATA-OUT
SDATA-IN
5
8
SPDIFO
SPDIFI/EAPD
48
47
R371
1
SPDIF
28
1 R396
0R0603-PAD
2
SPDIF_CN
C611
SIDE-L/PORT-H-L
SIDE-R/PORT-H-R
29
C614
SC470P50V2KX-3GP
DY
DY
SC470P50V2KX-3GP
MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO
26
42
4
7
45
46
29
SB_AZ_CODEC_SDOUT 17
SB_AZ_CODEC_SDIN0 17
2 33R2J-2-GP
EAPD#
LINEIN_JD
Q14
2N7002-11-GP
1
LINE1-VREFO
LINE2-VREFO
ALC888-GR-GP
3
1
29
31
AVSS1
AVSS2
DVSS
DVSS
MIC1VREFO_R
MIC1VREFO_L
TPAD30
TP33
LINE1-L/PORT-C-L
LINE1-R/PORT-C-R
LINE2-L/PORT-E-L
LINE2-R/PORT-E-R
32
28
MIC2VREFO 30
2
29
5V_AUDIO_S0
2
C330 1
14
MICIN_JD#
2
20KR2F-L-GP
2
C331 1
MIC_IN_R
ARRAY_DETC
MICIN_JD
Q13
2N7002-11-GP
CODECVREF
SURR-L/PORT-A-L
SURR-R/PORT-A-R
39
41
FRONT-L/PORT-D
FRONT-R/PORT-D
35
36
2
AUD_LOL
AUD_LOR
28
28
CD-L
CD-R
CD-GND
MIC_IN_L
29
G
29
18
20
19
29
23
24
14
15
LFE/PORT-G-R
CENTER/PORT-G-L
LINEIN_R
2
SC4D7U6D3V3KX-GP
GPIO0/DMIC-CLK
GPIO1/DMIC-DATA
1
C328
HP_OUT_L
HP_OUT_R
2
3
LINE_IN_R
PCBEEP
RESET#
SYNC
BCLK
NC#33
29
28
28
LINEIN_L
2
SC4D7U6D3V3KX-GP
JDREF
PIN37-VREFO
1
C329
VREF
LINE_IN_L
40
37
29
DVDD
DVDD-IO
AVDD1
AVDD2
U42
12
11
10
6
33
SCD1U16V2KX-3GP
27
C602
1
9
25
38
SC10U6D3V5KX-1GP
R338
1
2
3
C332
LOUR_JD#
S
R448
1
D
LOUR_JD#_R
3D3V_S0
1
1
C590
2
2
C608
2
1
SCD1U16V2KX-3GP
R376
1
2 33R2J-2-GP
DMIC_DATAIN 14
R388
1
2 33R2J-2-GP
D_MIC_CLKOUT 14
AUD_JDEF
<Core Design>
1
1
1
1
1
R394
20KR2F-L-GP
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
SCD1U16V2KX-3GP
2
C591
SCD1U16V2KX-3GP
2
C595
Title
AUDIO CODEC ALC888
Size
A3
Document Number
Date: Friday, May 16, 2008
A
B
C
D
Rev
S13
SC
Sheet
E
27
of
44
A
B
C
D
E
1
5VA_OP_S0
Internal Speaker
R451
10KR2J-3-GP
5VA_OP_S0
2
5V_S0
1
D
1
S
1
1
2
2
SPKR_L+
1
1
EC49
DY
3
ETY-CON2-5-GP-U
20.D0196.102
S
SC100P50V2JN-3GP
Q31
2N7002-11-GP
1
3
EC50
DY
2
1
1
SPKR_L-
G
KBC_MUTE#
4
C672
SC100P50V2JN-3GP
D
COVER2
2
G1432Q5U-GP
DY
ETY-CON2-5-GP-U
20.D0196.102
SC1U16V3ZY-GP
2
GND
GND
14
25
11
C648
27
2
2
13
5
RBYPBASS
MUTE
1
R_BYPASS
16
AUD_LOR
R479 1
2
10KR3F-L-GP
C667
1
2
DY
L_BYPASS
3
LBYPASS
2
DY
EC5
SC2D2U10V3KX-1GP
DY
30
1
EC6
R454
C649
2
1 SOUND_R2 1
2
10KR3F-L-GP
SC1U16V3ZY-GP
SPKR_R+
SPKR_R-
SC2D2U10V3KX-1GP
1
2
R393 0R2J-2-GP
EAPD#
2
SPKR_R+
SOUND_R_OP1
18
17
19
12
RIN1
RIN2
ROUT+
ROUT-
2
NC#6
NC#8
NC#23
IN1#/IN2
6
8
23
GND/HS
GND/HS
GND/HS
GND/HS
DY
LIN1
LIN2
LOUT+
LOUT-
SHUTDOWN
VOL
LVDD
RVDD
SPKR_L+
SPKR_L-
1
2
24
7
KBC_MUTE
27
4
SPKR_R-
31
3
9
10
21
22
SOUND_L_OP1
1 R466
2
10KR3F-L-GP
C666
1
2
AMP_SD#
10KR2J-3-GP
R470
20
4
15
2
2
1
TPAD30 TP63
R440
10KR2J-3-GP
3
1
2
R469 0R0402-PAD
G1432_VOL
SC1U16V3ZY-GP
5VA_OP_S0
4
G
SC100P50V2JN-3GP
C673
R477
1
2SOUND_L2 1
2
10KR3F-L-GP
SC1U16V3ZY-GP
AUD_LOL
COVER1
Q30
2N7002-11-GP
U64
27
G1412_SHDN#
C645
SC100P50V2JN-3GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
C628
AMP_SHUTDOWN
SCD1U16V2KX-3GP
C658
2
C629
4
SCD1U16V2KX-3GP
2
0R0805-PAD
1
1
1 R435
1
G1412_VSS
8
3
C668
HP_L
HP_R
2
OUTL
OUTR
2
4
SHDN#
5
PGND
1
PVDD
NVDD
INL
INR
9
NC#9
3VA_S0_AU
U65
1
2
3
G1412_SHDN#
OUT
IN
C1-
C1+
SHDN#
GND
6
5
4
G1412_SHDN#
C596
G5930TBU-GP
2
2
7
6
C592
SC2D2U10V3KX-1GP
LINE_OUT_L
LINE_OUT_R
1
1
C661
2
1
1
2
U60
SCD1U16V2KX-3GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
3VA_S0_AU
1 R471
2
0R0603-PAD
C662
2
3D3V_S0
SCD1U16V2KX-3GP
1
2
G1412RC1U-GP
C657
SC4D7U6D3V5KX-3GP
LINE Out
LINE_OUT_L
2
SC47P50V2JN-3GP
27
HP_OUT_L
C327 1
SC22U6D3V5MX-2GP
2
R382
HP_OUT_C_L 1
2
10KR3F-L-GP
R383
1
2
10KR3F-L-GP
1
470R3D-GP
27
HP_OUT_R
C326 1
SC22U6D3V5MX-2GP
2
R341
HP_OUT_C_R 1
2
10KR3F-L-GP
R342
1
2
10KR3F-L-GP
1
470R3D-GP
LINE_OUT_CN_L 29
R343
2
<Core Design>
1
1
29
C586
Wistron Corporation
2
LINE_OUT_R
2
SC47P50V2JN-3GP
LINE_OUT_CN_R
C607
SC100P50V2JN-3GP
C585
1
2
SC100P50V2JN-3GP
HP_R
R384
1
1
C600
1
2
HP_L
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
AUDIO AMP/Speaker
Size
A3
Document Number
Date: Friday, May 16, 2008
A
B
C
D
Rev
S13
SC
Sheet
E
28
of
44
4
3
MLVG0402220NV09BP-GP
1
2
2
1
MLVG0402220NV09BP-GP
C641
MLVG0402220NV09BP-GP
1
1
DY
L58
1
DY
2
2
L51
SC1KP50V2JN-2GP
SHIELDING
1
D
MICIN_JD
DY
C624
SC1KP50V2JN-2GP
SC1KP50V2JN-2GP
JK2
DY
L59
2
L52
DY
C638
MIC_IN_L_L
DY
C626
LINE IN
DY
MLVG0402220NV09BP-GP
DY
2
2
2
MIC_IN_R_R
1
2
C639
MLVG0402220NV09BP-GP
MICIN_JD
2
27
SC100P50V2JN-3GP
SC100P50V2JN-3GP
PHONE-JK240-GP-U1
C632
2
C640
5
7
8
NP1
NP2
1
1
MICIN_JD
1
4
R423 1
SC1KP50V2JN-2GP
MIC_IN_R_R
L60
2
27
C633
3
DY
1
MIC_IN_R
L50
2
2
1KR2F-3-GP
DY
6
LINEIN_JD
DY
1
LINE_IN_CN_L
DY
SC1KP50V2JN-2GP
27
SC1KP50V2JN-2GP
MIC_IN_L
1
LINE_IN_CN_R
2
1KR2F-3-GP
2
R422 1
1
MIC_IN_L_L
2
1
D
R417
2K2R2F-GP
1
SHIELDING
1
MLVG0402220NV09BP-GP
2
MIC1VREFO_R
R428
2K2R2F-GP
JK1
1
1
MIC1VREFO_L
MIC IN
2
2
5
C
C
G5240B1T1U-GP
Q29
2N7002-11-GP
1
L55
C636
2
2
MLVG0402220NV09BP-GP
1
1
DY
B
S
G
MLVG0402220NV09BP-GP
1
C637
DY
L53
MLVG0402220NV09BP-GP
2
L56
DY
C634
2
EN
OUT
GND
NC#3
DY
SPDIF_PWR
DY
SC1KP50V2JN-2GP
D
IN
SC1KP50V2JN-2GP
G5240_EN 4
DY
1
2
3
1
1
2
1
2
1
5
LOUR_JD#
2
U63
R458
10KR2J-3-GP
B
SPDIF_CN
1
1
SPDIF_PWR
2
0R2J-2-GP
L57
C631
1
DY
1
R449
DY
2
3D3V_S0
LINEIN_JD
L54
C635
C625
SC100P50V2JN-3GP
SC100P50V2JN-3GP
PHONE-JK240-GP-U1
27
C622
2
LINEIN_JD
5
7
8
NP1
NP2
DY
SC1KP50V2JN-2GP
4
R420 1
SC1KP50V2JN-2GP
LINE_IN_CN_R
SC1KP50V2JN-2GP
3
2
27
6
LOUR_JD#
DY
2
LINE_IN_R
LINE_OUT_CN_L
DY
MLVG0402220NV09BP-GP
2
1KR2F-3-GP
LINE_OUT_CN_R
1
27
2
LINE_IN_L
2
2
1KR2F-3-GP
MLVG0402220NV09BP-GP
R426 1
1
LINE_IN_CN_L
2
SPDIF / LINE OUT
LOUT1
METAL
8
9
6
1
4
7
5
LED
DRIVE
IC
TX
A
B
C
LINE_OUT_CN_R
LINE_OUT_CN_L
LOUR_JD#
SPDIF_PWR
SPDIF_CN
LINE_OUT_CN_R 28
LINE_OUT_CN_L 28
LOUR_JD#
27
SPDIF_CN
27
NP1
NP2
PHONE-JK287-GP
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
AUDIO CONN/SUBWOOFER
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
29
of
44
5
4
3
2
1
D
3D3V_AUX_S5
1
R275
2
BAT_SDA
4K7R2J-2-GP
THERMAL----->
BATTERY----->
KBC_SDA2
KBC_SCL2
BAT_SDA
BAT_SCL
21 KBC_SDA2
21 KBC_SCL2
40,41 BAT_SDA
40,41 BAT_SCL
3D3V_S0
DY
GPIO66/G_PWM
2
I2C_INT#
10KR2J-3-GP
1
E51_TxD
E51_RxD
E51_TxD
E51_RxD
111
113
1 CCD_ON 112
TPAD28
114
14
15
TP5
26 PWRBTN_LED
26
I2C_INT#
21 S5_ENABLE
I2C_INT#
E51_TxD
10KR2J-3-GP
R248
4K7R2J-2-GP
VCORF
44
GPIO
GPO83/SOUT_CR/BADDR1
GPIO87/SIN_CR
GPO84/BADDR0
GPIO16
GPIO34
GPIO36/TB3
SER/IR
1
2
2
2
1
1
1
1
1
2
1
1
DY
2
PM_SLP_S3# 17,21,22,33,38
KBC_PWRBTN# 26
AC_IN#
41
LID_CLOSE# 32
PANEL_BKEN 1
R364
2 KBC_MATRIX0
DY 0R2J-2-GP
CAMERA_EN 14
PWR_LED#
26
AD_OFF
40
RSMRST#_KBC 17
PM_SLP_S5# 17,22,37,39
BAT_LED#
26
1
R252
2
10KR2J-3-GP
B
KBC for AMD
3D3V_AUX_S5
3D3V_AUX_S5
KBC_MUTE# 28
BLON_OUT 14
RF_ON/OFF# 22
SPI_WP#
R498
R497
10KR2J-3-GP
31
USB_PWR_EN# 25
DY
DY
10KR2J-3-GP
KBC_MATRIX0
KBC_MATRIX1
C432
SCD1U16V2ZY-2GP
R495
R496
10KR2J-3-GP
WPC775L-0DG-GP-U
71.00775.00G
17 ECSCI#_KBC_R
2
2
1
PCB_VER0
PCB_VER1
VCORF
103
1
R273
22
22
SPI
64
95
93
94
119
6
109
120
65
66
16
17
20
21
22
23
24
25
26
27
28
73
74
75
110
R271
10KR2J-3-GP
R279
10KR2J-3-GP
1
E51_TxD
10KR2J-3-GP
GPIO77/SPI_DI
GPIO76/SPI_DO/SHBM
GPIO75/SPI_CLK
GPIO81
GPIO01/TB2
GPIO03/AD6
GPIO06
GPIO07/AD7
GPIO23/SCL3
GPIO24
GPIO30
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/TRST#
GPIO47/SCL4
GPIO50/TDO
GPIO51/TA3
GPIO52/RDY#
GPIO53/SDA4
GPIO70
GPIO71
GPIO72
GPO82/TRIS#
TP7
TP12
2
2
4K7R2J-2-GP
101
105
106
107
PCB_VER0
PCB_VER1
GND
GND
GND
GND
GND
GND
2
E51_RxD
10KR2J-3-GP
2
5
18
45
78
89
116
1
R254
2
1
R276
26 WLANONLED#
GPI94/DA0
GPI95/DA1
GPI96/DA2
GPI97/DA3
KBC_MATRIX1 1
KBC_MATRIX0 1
C
41
2
102
4
VDD
AVCC
SP
AGND
DY
23 BLUETOOTH_EN
KA20GATE
10KR2J-3-GP
84
83
82
91
2
1
2
1
81
SMB
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05/AD4
GPIO04/AD5
DY
AD_IA
1
1
R270
2
DY
2
1
R267
2
DY
1
R268
GPIO74/SDA2
GPIO73/SCL2
GPIO22/SDA1
GPIO17/SCL1
KBRCIN#
2
10KR2J-3-GP
1
R264
B
68
67
69
70
D/A
104
97
98
99
100
108
96
1
BAT_SCL
4K7R2J-2-GP
LPC
VREF
10KR2J-3-GP
2
2
A/D
R272
10KR2J-3-GP
R280
10KR2J-3-GP
1
1
R274
U29A
2
2
R485
0R0402-PAD
3D3V_S0
1
PANEL_BKEN 1
11 PANEL_BKEN
GPIO10/LPCPD#
LRESET#
LCLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
SERIRQ
GPIO11/CLKRUN#
KBRST#
GA20
ECSCI#/GPIO54
GPIO65/SMI#
GPIO67/PWUREQ#
C439
PCB_VER1
0
0
1
2
2PCLK_KBC_RC
C417
DY SC4D7P50V2CN-1GP
1
3D3V_AUX_S5
SCD1U16V2ZY-2GP
80
1
2
2
R250
0R2J-2-GP
2
124
7
2
3
126
127
128
1
125
8
122
121
ECSCI#_KBC
29
9
ECSWI#_KBC 123
16 LPC_LFRAME#
16 LPC_LAD0
16 LPC_LAD1
16 LPC_LAD2
16 LPC_LAD3
16 IRQ_SERIRQ
16 PM_CLKRUN#
17 KBRCIN#
17 KA20GATE
1
DY
2
GPIO41
26 BATLOW_LED#
16,20 LPCCLK0
C424
SCD1U16V2ZY-2GP
C
BAT_IN#
C452
SCD1U16V2ZY-2GP
SC27P50V2JN-2-GP
C418
40
3D3V_S0
C423
SCD1U16V2ZY-2GP
PLT_RST1#_1
2
100R2J-2-GP
C195
SCD1U16V2ZY-2GP
1
R247
C447
SC10U10V5ZY-1GP
PLTRST_SYS#
SC1U16V3ZY-GP
22,23,24,25,26,33
1
KBC_AVCC
C449
BOAR VERSION
PCB_VER0
SA
0
SB
1
PD
0
L38
1
2
BLM11P600S
C301,C295 colse to Pin VDD
19
46
76
88
115
2
2
SC10U10V5ZY-1GP
VCC
VCC
VCC
VCC
VCC
C421
C89
D
SCD1U16V2ZY-2GP
1
1
3D3V_S0
ECSCI#_KBC
<Core Design>
A
A
D17
CH751H-40PT
2
17 ECSWI#_SB
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
ECSWI#_KBC
D18
CH751H-40PT
Title
KBC_WPC775 / BIOS
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
30
of
44
5
4
3
2
1
D
D
1
X1
1
C192
KROW[1..8]
32
KCOL[1..16]
32
C187
3
2
4
1
SC18P50V2JN-1-GP
2
1KBC_XO_R2
SC18P50V2JN-1-GP
2 R269
1 10KR2J-3-GP
DY
U29B
X-32D768KHZ-40GPU
28 AMP_SD#
TPAD28
TP10
1
KBC_CIR
17 PM_PWRBTN#
41 CHG_ON#
27 KBC_BEEP
C
14 BRIGHTNESS
MODEL_1
MODEL_0
32
32
TPDATA
TPCLK
TPDATA
TPCLK
32KX1/32KCLKIN
79
30
32KX2
GPIO55/CLKOUT
63
117
31
32
118
62
GPIO14/TB1
GPIO20/TA2
GPIO56/TA1
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
13
12
11
10
71
72
GPIO12/PSDAT3
GPIO25/PSCLK3
GPIO27/PSDAT2
GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
54
55
56
57
58
59
60
61
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
VCC_POR#
85
ECRST#
KBC
PS/2
3D3V_S0
1
1
SPIDI
SPIDO
SPICS#
SPICLK
2
F_SDI
F_SDO
F_CS0#
F_SCK
FIU
R258
2
DY
TP4
TP3
1
1
TPAD28
TPAD28
3D3V_AUX_S5
2
R277
1
10KR2J-3-GP
ECRST#
21
Q21
B
EC_RST#
MMBT3906-3-GP
C
R260
10KR2J-3-GP
DY
C455
WPC775L-0DG-GP-U
10KR2J-3-GP
MODEL_0
MODEL_1
B
1
1
3D3V_AUX_S5
5
6
7
8
3D3V_AUX_S5
SRN10KJ-6-GP
RN30
KBC
1
DY
2
2
2
EC45
DY
1
10KR2J-3-GP
SCD1U16V2ZY-2GP
R259
R263
10KR2J-3-GP
4
3
2
1
B
86
87
90
92
C
SC1U10V3KX-3GP
KBSOUT0/JENK#
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4/JEN0#
KBSOUT5/TDO
KBSOUT6/RDY#
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
1
2
KBC_XO
77
2
KBC_XI
1
2
R148
10MR2J-L-GP
E
R149
33KR2J-3-GP
SPI_HOLD#
1
2
3
4
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DIO
8
7
6
5
EC46
SC47P50V2JN-3GP
SPI_WP#
DY
SC4D7P50V2CN-1GP
2M Bits
SPI FLASH ROM
30
SPI_VCC
SPIDI_R
SPI_WP#
2
3
4
7
6
5
SPI_HOLD#
SPICLK_R
SPIDO_R
SKT-SPI8P-GP-U
ER2
ER3
W25X16VSSIG-GP
A
8
0R0603-PAD
2 0R2J-2-GP
2 150R2F-1-GP
1
1
SPICLK
SPIDO
DY
1
SPIDI_R
SPI_WP#
1
EC47
DY
<Core Design>
2
2
150R2F-1-GP
1
EC44
SC47P50V2JN-3GP
1
SPI_VCC
SPI_HOLD#
SPICLK_R
SPIDO_R
2
1
DY
SPICS#
2
U31
SPICS#
SPIDI ER1
2
MODEL (KBC internal pull high)
MODEL_0
MODEL_1
X17
0
0
P15
0
1
S13
1
0
P1
1
1
SKT FOR DEBUG
SKT1
ER4
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
KBC_WPC775 / BIOS(2/2)
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
31
of
44
5
4
3
2
1
TouchPad Connector
Internal KeyBoard Connector
5V_S0
4
3
D
1
C95
SCD1U16V2ZY-2GP
2
CN2
RN29
SRN10KJ-5-GP
KCOL5
KCOL7
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
KCOL2
KCOL3
KCOL6
KCOL8
KCOL9
KCOL10
KCOL11
KCOL13
KCOL14
KCOL15
KCOL16
KCOL1
KCOL12
KROW[1..8]
D
TPAD1
13
1
31
1
2
31
31
TPDATA
TPCLK
EC42
SC33P50V2JN-3GP
1
2
3
4
5
6
7
8
9
10
11
12
31
1
KCOL[1..16]
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
KCOL4
1
1
2
25
C97
SC1U10V2KX-1GP
2
1
5V_S0
RIGHT#
EC43
SC33P50V2JN-3GP
24
LEFT#
14
12
1
ACES-CON12-4-GP-U
26
C
C
ETY-CON24-3-GP-U
5V_S0
5V_S0
1
1
TOUCHPAD BUTTON SWITCH
DY
2
R207
10KR2J-3-GP
DY
2
R206
10KR2J-3-GP
SW1
1
GOLDEN FINGER FOR DEBUG BOARD
SW2
3
LEFT#
1
2
RIGHT#
3
5
5
4
2
SW-TACT-91-GP
62.40009.561
4
SW-TACT-91-GP
62.40009.561
B
B
COVER SWITCH
1
3D3V_AUX_S5
3D3V_AUX_S5
R114
56KR2J-L1-GP
1
2
OUTPUT
VDD
2
3
1
LID_CLOSE#
30
C102
SCD22U6D3V2KX-1GP
U25
EM-6781-T30-GP
2
VSS
SCD1U16V2ZY-2GP
A
2
100R2J-2-GP
1
1
COVER_SW
2
R110
C107
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
KEYBOARD/TPAD/DEBUG/LID
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
32
of
44
5
4
3
2
1
1
3D3V_S0
NB_SB POWERGOOD CIRCUIT
R328
10KR2J-3-GP
3D3V_S5
10
2
CPWRON
3D3V_S0
D23 1
CH751H-40PT
2
37 1D2V_PWRGD
D24 1
CH751H-40PT
2
S
C675
DY
D
1
S
SCD1U10V2KX-4GP
S
Q27
2N7002-11-GP
1
2
G
R381 0R0402-PAD
ATI 1.8V PULL HIGH
1
C
D
S
2
1
37 1D8V_S3_PG
R398
0R2J-2-GP
2
2
Q25
2N7002-11-GP
2D5V_PWRGD
G
D
Q28
2N7002-11-GP
G
2
D28 1
CH751H-40PT
R332
10KR2J-3-GP
DY
2
1
SB_PWRGD 17
R397
10KR2J-3-GP
1
1
CH751H-40PT
D31
2
3D3V_S5
D
34,37
Q24
2N7002-11-GP
G
1
R400
10KR2J-3-GP
2
2
S
R389
10KR2J-3-GP
17,21,22,30,38 PM_SLP_S3#
VCORE_EN
R329
10KR2J-3-GP
2D5V_S0
2
1
Q26
2N7002-11-GP
G
D
3D3V_S0
1
D
D
C
1D8V_S0
1
2EC_NB_PWRGD_R
4K7R2F-GP
2
2
C937
B
2
A
3
SCD01U50V2KX-1GP
D26 1
CH751H-40PT
21 PWROK
R588
1
17 SB_TO_EC_PWRGD
VCC
5
Y
4
DY
RS780M
Databook
V1.01
2
2
NB_PWRGD
NB_PWRGD
11
GND
1
D22 1
CH751H-40PT
34 VGATE_PWRGD
R209
4K7R2F-GP
U43
1
74LVC1G08GW-1-GP
C366
SCD1U10V2KX-4GP
2
2
1
D27 1
CH751H-40PT
38 1D1V_PWRGD
SCD1U10V2KX-4GP
2
C605
1
R214
Ati:0~30n sec
DY
2
0R2J-2-GP
DY
Run Power
3
5
2
6
U16
2N7002DW-1-GP
1
DY
PM_SLP_S3# 17,21,22,30,38
B
8
7
6
5
AO4468-GP
84.04468.037
3D3V_S5
2
3D3V_S0
3D3V_S5
1
2
3
4
C59
U17
S
S
S
G
D
D
D
D
1
C57
SCD1U10V2KX-4GP
8
7
6
5
11,16
PLTRST#
U27
1
B
2
A
3
VCC
5
Y
4
PLTRST_SYS# 22,23,24,25,26,30
GND
74LVC1G08GW-1-GP
AO4468-GP
84.04468.037
DY
1
1D8V_S0
1D8V_S3
1
2
3
4
2
R189
0R2J-2-GP
DY
SCD1U25V3KX-GP
84.27002.D3F
DY
2
R68
0R2J-2-GP
4
2
2
1
1
1
C411
D
D
D
D
2
Z_12V_D3
2
1
2
1
2
Z_12V_D3
D
S
Z_12V_D4
SCD1U25V3KX-GP
Q7
2N7002-11-GP
G
2
1
1
3D3V_runpwr 2
R56
100KR2J-1-GP
SCD1U25V3KX-GP
DY
A
R74
10KR2J-3-GP
2
R245
0R2J-2-GP
RLZ12B-1-GP
Z_12V_G3
1
330KR2F-L-GP
330KR2F-L-GP
SCD1U25V3KX-GP
G
2
R55
R81
100R5J-3-GP
D6
R87
1
2
3
4
1
1
C78
3D3V_S0
2
2
2
RUN_POWER_ON
D
2 Z_12V
10KR2J-3-GP
S
1
R58
Q6
TP0610K-T1-GP
3
U53
S
S
S
G
1
DCBATOUT
1
B
5V_S5
5V_S0
DY
C316
U33
S
S
S
G
D
D
D
D
8
7
6
5
<Core Design>
A
AO4468-GP
84.04468.037
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
C412
SCD1U25V3KX-GP
1
Title
RUNPOWER
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
33
of
44
5
4
3
C48
1
5V_S0
DCBATOUT
C45
2
1
1 R53
26265_FB_NB_R
44K2R2F-1-GP
C41
SC1U10V2KX-1GP
SC180P50V2JN-1GP
2
1
C46
DCBATOUT_6265
G77
1
1
GAP-CLOSE-PWR
G78
2
1
GAP-CLOSE-PWR
G79
2
1
GAP-CLOSE-PWR
G76
2
2
SC1KP50V2KX-1GP
2
2
1
2R3J-GP
1
2
R46
1
2
SC33P50V2JN-3GP
C43
1
GNDA_VCORE
GAP-CLOSE-PWR
R48
10R2F-L-GP
1 R52
3D3V_S0
2 0R2J-2-GP
GNDA_VCORE
1/31
33 VGATE_PWRGD
6 CPU_PWRGD_SVID_REG
6
CPU_SVD
6
CPU_SVC
33,37 VCORE_EN
R51
R50 1
R61 1
2
27KR2F-L-GP R65
1
R70
2/1
G84
2
1
+VCC_CORE1
1
Close to
CPU socket
1
R150
10R2J-2-GP
U11
BOOT_NB
BOOT0
UGATE0
PHASE0
36
35
34
33
32
31
30
29
28
27
26
25
BOOT_NB
BOOT0
UGATE0
PHASE0
PGND0
LGATE0
PVCC
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
1
1
GAP-CLOSE-PWR
G82
2
1
GAP-CLOSE-PWR
G83
2
GAP-CLOSE-PWR
5V_S0
LGATE0
LGATE1
PHASE1
UGATE1
BOOT1
2
GAP-CLOSE-PWR
G80
2
C
BOOT_NB 35
UGATE0
PHASE0
BOOT0
LGATE0
35
35
35
35
UGATE1
PHASE1
BOOT1
LGATE1
35
35
35
35
20071207
C54
+VCC_CORE1
ISP1
B
R84
0R2J-2-GP
DY
R144
10R2J-2-GP
6
ISP0
ISN0
35
35
ISP1
35
2
2
2
B
ISP0
ISN0
+VCC_CORE0
1
2
C953
SCD22U6D3V2KX-1GP
CPU_VDDNB_RUN_FB_L
49
48
47
46
45
44
43
42
41
40
39
38
37
GNDA_VCORE
1D8V_S3
1
1 R57
2
0R2J-2-GP
13
14
15
16
17
18
19
20
21
22
23
24
IC CTRL ISL6265HRTZ-T QFN 48P
74.06265.073
DCBATOUT_6265B
G81
UGATE_NB 35
R49
10R2F-L-GP
6265_VSEN0
6265_RTN0
6265_RTN1
6265_VSEN1
6265_VDIFF1
6265_FB1
6265_COMP1
6265_VW1
1
GAP-CLOSE-PWR
6265_ENABLE
UGATE_NB
CPU_VDDNB_RUN_FB_L_R
ISP0
ISN0
VSEN0
RTN0
RTN1
VSEN1
VDIFF1
FB1
COMP1
VW1
ISP1
ISN1
GNDA_VCORE
OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0
FB0
COMP0
VW0
DCBATOUT
LGATE_NB 35
PHASE_NB
SC2D2U10V3KX-1GP
6265_SVD
2
2 0R2J-2-GP 6265_SVC
0R2J-2-GP 6265_ENABLE
2
22K2R2J-2-GP 6265_RBIAS
90K9R2F-GP6265_OCSET
6265_VDIFF0
6265_FB0
6265_COMP0
6265_VW0
1
1
1
2
3
4
5
6
7
8
9
10
11
12
LGATE_NB
1
C
GNDA_VCORE
PHASE_NB 35
11K5R2F-GP
GND
VIN
VCC
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
DY
6265_OFS/VFIXEN
R43
0R2J-2-GP
2
2
DY
1
R62
10KR2F-2-GP
PHASE_NB
2
20071122
6
2
DY
2
R42
10KR2F-2-GP
6265_OCSET_NB
2
R44
0R2J-2-GP
1
1
2
R45
0R2J-2-GP
6265_VIN
6265_VCC
6265_FB_NB
6265_COMP_NB
6265_FSET_NB
6265_VSEN_NB
1
1
1 R54
CPU_VDDNB_RUN_FB_H
1
5V_S0
1
GNDA_VCORE
3D3V_S0
TC15
ST15U25VDM-1-GP
2
C39
SCD1U50V3KX-GP
2
2R3J-GP
GNDA_VCORE
2
1
DCBATOUT_6265
DY
CPU_VDDNB
1 R47
2
22KR2F-GP
2
1
D
SCD1U10V2KX-4GP
1 R41
2
D
2
6 CPU_VDD0_RUN_FB_H
6 CPU_VDD0_RUN_FB_L
R72
R73
R85
R86
1
1
6 CPU_VDD1_RUN_FB_L
6 CPU_VDD1_RUN_FB_H
2
R140
10R2F-L-GP
2
R151
10R2J-2-GP
1
1
2
2 0R2J-2-GP
0R2J-2-GP
2
2 0R2J-2-GP
0R2J-2-GP
1
1
Parallel
Close to
CPU socket
DY
A
6265_FB0_C
R71
249R2F-GP
1
2
C77
C61
1
C68
1
2
SC4700P50V2KX-1GP
1
2
2
1KR2F-3-GP
1
SC180P50V2JN-1GP
R79
1 R80
1
2
SC180P50V2JN-1GP
2 DY
C66
1
C76
2
6265_FB1_C
R94
249R2F-GP
1
2
C81
1
2
1
R88
2
1
1
2
2
1KR2F-3-GP
SC180P50V2JN-1GP
C67
1
2
1
2
C75
1
2
54K9R2F-L-GP SC1000P50V3JN-GP
6265_FB1_R
SC1KP50V2KX-1GP
C70
2
<Core Design>
C72
1
1 R83
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
2
Title
6K81R2F-1-GP
ISL6265HR_CPU_Core/VDDNB_1/2
Size
A3
2
Document Number
SC180P50V2JN-1GP
Date: Friday, May 16, 2008
5
4
A
SC1KP50V2KX-1GP
Wistron Corporation
R82
1 R92
2
6K81R2F-1-GP
SC180P50V2JN-1GP
2
1
SC4700P50V2KX-1GP SC180P50V2JN-1GP
SC1KP50V2KX-1GP
54K9R2F-L-GP
6265_FB0_R
C71
C79
3
2
S13
Rev
SC
Sheet
1
34
of
44
5
4
3
2
1
DCBATOUT_6265
2
2
+VCC_CORE0
Design Current: 12.6A
Peak current: 18A
OCP_min:24A
D
+VCC_CORE0
L34
UGATE0
PHASE0
UGATE0
PHASE0
C403
1
1
1
2
1
2
4
3
2
1
C395
SCD1U50V3KX-GP
S
S
S
G
SI7686
84.07686.037
C396
SC10U25V6KX-1GP
POWERPAK-8P-GP
34
34
D
D
D
D
U52
D
SC10U25V6KX-1GP
5
6
7
8
C399
SC10U25V6KX-1GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Inductor: 4.7uH NEC_TOKIN MPLC0730L4R7 / 68.4R710.20G
O/P cap: 330U 2.5V 2R5TPE330M9L/ 77.23371.13L
H/S: SI7326DN/30mOhm/ 4.5Vgs/ 84.07326.037
L/S: SI7326DN/30mOhm/ 4.5Vgs/ 84.07326.037
1
2
5
6
7
8
DY
1
1
2
2
2
NTC-10K-9-GP
1
ISP0
G32
2
1
2
1
2
1
2
5
6
7
8
ISP0
1
34
ISN0
C
4
3
2
1
G
S
S
S
D
D
D
D
DY
34
2
R89
10R2F-L-GP
ISP0_R
GAP-CLOSE-PWR-3-GP
C52
SCD1U50V3KX-GP
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
SC10U25V6KX-1GP
SC10U25V6KX-1GP
U14
SI4800BDY-T1
C49
DY
SCD1U16V3KX-3GP
R98
DY
1
C405
TC19
SE330U2VDM-6-GP
1 R91
2
4K02R2F-GP
C80
1
2
DCBATOUT_6265
C
SE330U2VDM-6-GP
11/13
TC10
SE330U2VDM-6-GP
1
2
R90
16K2R2F-GP
SI4634DY
84.04634.037
LGATE0
TC17
1/31
11/13
S
S
S
G
SI4634DY
84.04634.037
POWERPAK-8P-GP
LGATE0
S
S
S
G
POWERPAK-8P-GP
34
U13
ISN0
U49
1
2
C51
SCD22U10V3KX-GP
2
1
4
3
2
1
BOOT0_R
4
3
2
1
1 R60
2
1R3J-L1-GP
D
D
D
D
BOOT0
BOOT0
D
D
D
D
34
5
6
7
8
IND-D36UH-9-GP
R298
2
1
2
IND-4D7UH-120-GP
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
B
C410
SCD1U10V2KX-4GP
2
DY
TC16
ST220U2VDM-5-GP
2
U15
SI4800BDY-T1
1
2/1
5
6
7
8
1R2F-GP
PHASE_NB
2
Iomax=3A
OCP>6A
SCD22U10V3KX-GP
D
D
D
D
BOOT_NB 1
CPU_VDDNB
L36
11/13
DCBATOUT_6265B
G
S
S
S
B
20071207
LGATE_NB
2
C63
SI4634DY
84.04634.037
ISP1
LGATE1
34
ISP1
1
2
1 R75
2
4K02R2F-GP
11/13
SE330U2VDM-6-GP
TC9
SE330U2VDM-6-GP
1
TC18
+VCC_CORE1
2
1
5
6
7
8
SI4634DY
84.04634.037
IND-D36UH-9-GP
R78
16K2R2F-GP
11/13
S
S
S
G
LGATE1
U50
POWERPAK-8P-GP
34
S
S
S
G
A
POWERPAK-8P-GP
SCD22U10V3KX-GP
U12
4
3
2
1
5
6
7
8
2
4
3
2
1
BOOT1_R 1
D
D
D
D
BOOT1 1 R66
2
1R3J-L1-GP
D
D
D
D
BOOT1
2
1
1
1
UGATE1
PHASE1
2
L35
UGATE1
PHASE1
C58
34
+VCC_CORE1
Design Current: 12.6A
Peak current: 18A
OCP_min:24A
SE330U2VDM-6-GP
1
2
1
1
2
2
C404
SCD1U50V3KX-GP
4
3
2
1
C397
SC10U25V6KX-1GP
SI7686
84.07686.037
C400
SC10U25V6KX-1GP
S
S
S
G
POWERPAK-8P-GP
34
34
D
D
D
D
U51
SC10U25V6KX-1GP
5
6
7
8
C394
2
34 LGATE_NB
1
BOOT_NB
PHASE_NB 34
4
3
2
1
34
C47
1
1
UGATE_NB
34 UGATE_NB
TC8
DY
2
SCD1U16V3KX-3GP
R95
1 R76
2
1 DY
2
10R2F-L-GP
NTC-10K-9-GP
DY
<Core Design>
A
Wistron Corporation
ISP1_R
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1/31
Title
ISL6265HR_CPU_Core/VDDNB_2/2
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
35
of
44
5
4
1
DY
R36
100KR2J-1-GP
D
1
C24
1/31
2
1
GAP-CLOSE-PWR
G17
2
1
GAP-CLOSE-PWR
G18
2
1
GAP-CLOSE-PWR
G19
2
1
GAP-CLOSE-PWR
G20
2
1
GAP-CLOSE-PWR
G21
2
1
GAP-CLOSE-PWR
G22
2
2
D
G
Q4
2N7002-11-GP
D
Q2
2N7002-11-GP
Q3
2N7002-11-GP
G
5V_S5
G16
1
S
2
R30
150KR2F-L-GP
5V_PWR
5V_AUX_S5
2
1
1
1
GAP-CLOSE-PWR
G23
2
R31
160KR2F-GP
2
1
GAP-CLOSE-PWR
G24
2
PWR_S5_EN
1
1
GAP-CLOSE-PWR
G6
2
1
21
DY
2
1
GAP-CLOSE-PWR
G5
2
GAP-CLOSE-PWR
G26
2
G
51125_ENTIP1
C26
Q5
2N7002-11-GP
G
PWR_S5_EN 21
S
20071122
1
GAP-CLOSE-PWR
G31
2
D
1
GAP-CLOSE-PWR
G12
2
1
GAP-CLOSE-PWR
G30
2
51125_ENTIP2
R24
100KR2J-1-GP
S
GAP-CLOSE-PWR
G11
2
DY
1
GAP-CLOSE-PWR
G29
2
1
1
1
2
D
5V_AUX_S5
2
2
1
GAP-CLOSE-PWR
G10
2
1
TC2
ST15U25VDM-1-GP
1
3D3V_S5
G27
D
1
GAP-CLOSE-PWR
G7
2
3D3V_PWR
SC18P50V2JN-1-GP
DCBATOUT_51125
G8
2
SC18P50V2JN-1-GP
1
2
S
DCBATOUT
3
20071121
GAP-CLOSE-PWR
GAP-CLOSE-PWR
GAP-CLOSE-PWR
DCBATOUT_51125
DCBATOUT_51125
DCBATOUT_51125
51125_DRVL2
12
DRVL2
DRVL1
19
51125_DRVL1
VFB2
VFB1
2
51125_FB1
PGOOD
23
51125_PGOOD
ENTRIP1
1
51125_ENTIP1
GND
25
SKIPSEL
VCLK
18
2
1
R32
3D3V_AUX_S5
0R2J-2-GP
2
DY
1
R27
1
R40
Close to VFB Pin (pin5)
3D3V_AUX_S5
0R2J-2-GP
2
1
R39
DY
0R2J-2-GP
2
SC10U10V5KX-2GP
2
0R2J-2-GP
1
1
2
2
1
2
5
6
7
8
D
D
D
D
G
S
S
S
DY
C22
SC18P50V2JN-1-GP
DY
R28
30KR2F-GP
51125_FB1_R
DY
2
R33
20KR2F-L-GP
Close to VFB Pin (pin2)
C34
SC10U10V5KX-2GP
C27
51125_VREF
1
1
2
R25
0R2J-2-GP
R35
GAP-CLOSE-PWR-3-GP
2
0R2J-2-GP
2
51125_VREF
G13
1
GAP-CLOSE-PWR
5V_AUX_S5
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
R38
Title
DY
TPS51125_5V/3D3V
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
B
1
2
1
1
3D3V_PWR
TPAD28
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
2
74.51125.073
3D3V_AUX_S5
VREG5
VREG3
TPS51125RGER-GP
51125_VCLK
17
14
51125_SKIPSEL
G9
R26
10KR2F-2-GP
51125_GND
1
TONSEL
S
2
GND
4
G
TC4
1
VREF
15
1 2
3
C55
DY
2
ENTRIP2
2
51125_TONSEL
EN0
1
2 51125_EN 13
820KR2F-GP
51125_ENTIP2 6
D
G15
2
1
5
5V_AUX_S5_51125
1
51125_FB2
3D3V_AUX_S5_5_51125 8
C948
SCD1U16V2KX-3GP
DYSC18P50V2JN-1-GP
51125_VO1
2
1 2
51125_FB2_R
C25
1/14
DY
24
2
1
1
2
1
2
3
4
SI4812BDY-T1-E3-GP
1
2
8
7
6
5
1
0R2J-2-GP
VO1
100KR2J-1-GP
Id=7.7A
Qg=8.5~13nC
Rdson=16.5~21mohm
C23
VO2
ST220U6D3VDM-20GP
51125_VREF
SCD22U6D3V2KX-1GP
R29
6K65R2F-GP
DYR34
G
7
SCD1U10V2KX-4GP
B
1
R37
G
S
S
S
S
51125_VO2
5V_PWR
U8
GAP-CLOSE-PWR-3-GP
G28
U6
L2
1
2
IND-3D3UH-57GP
1
51125_LL1
Iomax=6A
OCP>12A
2
20
1
LL1
2
LL2
1
11
2
51125_DRVH1
51125_LL2
4
3
2
1
51125_VBST1
21
5
6
7
8
22
DRVH1
D
D
D
D
VBST1
DRVH2
Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
S
G
S
S
S
VBST2
10
C
4
3
2
1
9
51125_DRVH2
D
D
D
D
2
1
2
1
2
VIN
51125_VBST2
1
SI4812BDY-T1-E3-GP
D
GAP-CLOSE-PWR-3-GP
ST220U6D3VDM-20GP
SCD1U10V2KX-4GP
2
16
8
7
6
5
1
2
1
1
2
2
1
2
3
4
2
SCD1U25V3KX-GP
G
SCD1U50V3KX-GP
SCD1U25V3KX-GP
C28
1
2
G
S
S
S
G
1
2
IND-3D3UH-57GP
A
U7
Id=7A
Qg=8.7~13nC SI4800BDY-T1
Rdson=23~30mohm
C31
L1
TC5
U4
C30
SC10U25V6KX-1GP
U5
SI4800BDY-T1
D
C33
SC10U25V6KX-1GP
D
D
D
D
Id=7A
Qg=8.7~13nC
Rdson=23~30mohm
C37
SCD01U50V2KX-1GP
D
S
3D3V_PWR
C74
SC10U25V6KX-1GP
C29
SC10U25V6KX-1GP
Cyntec 7*7*3
DCR=30mohm, Irating=6A
Isat=13.5A
C32
SC10U25V6KX-1GP
Iomax=6A
OCP>12A
SCD1U50V3KX-GP
C
C35
1
C38
C36
3
2
Rev
S13
SC
Sheet
1
36
of
44
5
4
3
2
1
DCBATOUT_51124
DCBATOUT
DCBATOUT_51124
1D8V_PWR
1D8V_S3
G53
G68
1
GAP-CLOSE-PWR
G54
2
1
GAP-CLOSE-PWR
G55
2
1
GAP-CLOSE-PWR
G56
2
1
GAP-CLOSE-PWR
G57
2
1
GAP-CLOSE-PWR
G58
2
S
2
R182
47KR2F-GP
1
1D8V_S3_PG
1
GAP-CLOSE-PWR
G59
2
1
GAP-CLOSE-PWR
G60
2
1
GAP-CLOSE-PWR
G61
2
33
1
GAP-CLOSE-PWR
G62
2
TC11
SANYO
ESR=9mohm
2
1D2V_PWR
1D8V_PWR
51124_VFB2
51124_VFB1
1
C310
DY
SI4634DY-T1-E3-GP
R184
3D3R3J-L-GP
1
2
2
2
51124_VFB1
1
2
3
20071016
C
1/31
1D2V_PWRGD 33
D
GAP-CLOSE-PWR
1
6
PGOOD1
PGOOD2
2
51124_VBST2
2
1
1
Id=5A
Qg=8.7~13nC,
Rdson=23~30mohm
DY
SCD1U16V2KX-3GP
51124_V5FILT
2
R187
30KR2F-GP
DY
1
2
C320
2
2
DY
51124_VFB2
SI4800BDY-T1
1
1
C315
1
U40
DY
1D2V_PWR
1
G
S
S
S
4
3
2
1
2
1
2
5
6
7
8
D
D
D
D
R185
0R2J-2-GP
R183
10KR2J-3-GP
IND-1D5UH-23-GP
R188
17K8R2F-GP
2
51124_LL2
C541
1
5
6
7
8
2
SCD1U16V2KX-3GP
1D2V_S0
G74
1
SANYO
Fujitsu
ESR=15mohm ESR=15mohm
2
B
1
GAP-CLOSE-PWR
G73
2
1
GAP-CLOSE-PWR
G72
2
1
GAP-CLOSE-PWR
G71
2
1
GAP-CLOSE-PWR
G70
2
1
GAP-CLOSE-PWR
G69
2
TC13
SE220U2D5VDM-6GP
51124_VBST1
1D2V_PWR
Vo(cal)=1.2077V
SC18P50V2JN-1-GP
2
2
1D2V Iomax=5A
OCP>10A
SCD1U10V2KX-4GP
51124_LL1
C527
1
L20
1
D
D
D
D
R186
20KR2F-L-GP
C321
Cyntec 6*6*3
DCR=14mohm, Irating=9A
Isat=18A
G
S
S
S
R181
8K66R2F-GP
2
1/31
Id=5A
Qg=8.7~13nC,
Rdson=23~30mohm
C550
4
3
2
1
B
U38
SI4800BDY-T1
TPS51124RGER-GPU1
74.51124.073
2
17
14
1
1
DY
51124_TRIP1
51124_TRIP2
51124_TONSEL
2
BC2
SCD47U6D3V2KX-GP
51124_DRVH2
51124_LL2
51124_DRVL2
10
11
12
1
1
C322
DRVH2
LL2
DRVL2
TONSEL
GND
GND
PGND2
PGND1
DCBATOUT_51124
4
3
25
13
18
51124_DRVH1
51124_LL1
51124_DRVL1
21
20
19
2
EN1
EN2
DRVH1
LL1
DRVL1
1
23
8
VBST1
VBST2
51124_EN1
51124_EN2
22
9
V5FILT
V5IN
R327
1KR2F-3-GP
1
VO1
VO2
VFB1
VFB2
15
16
SCD1U50V3KX-GP
51124_V5FILT
SC10U25V6KX-1GP
2
VCORE_EN
DY
Id=14.5A
Qg=25~35nC,
Rdson=5.9~7.25mohm
SC10U25V6KX-1GP
33,34
BC1
SCD47U6D3V2KX-GP
TRIP1
TRIP2
1
R322
1KR2F-3-GP
2
U34
2
SC1U10V3KX-3GP
1
24
7
C309
2
17,22,30,39 PM_SLP_S5#
2
5
1
2
SC4D7U6D3V5KX-3GP
2
C535
2
R179
63K4R2F-1-GP
4
10KR2J-3-GP
10KR2J-3-GP
1/31
DY
SCD1U10V2KX-4GP
1/31
2
1
1
1
D
SC18P50V2JN-1-GP
5V_S5
C308
5
6
7
8
G
R326
R316
COIL-1UH-33-GP
1
U35
Vo(cal)=1.8046V
2
ST330U2D5VDM-9GP
1
3D3V_S5
Iomax=12A
OCP>18A
1D8V_PWR
L19
GAP-CLOSE-PWR
C
2
1
2
1
2
5
6
7
8
Cyntec 10*10*4
DCR=3mohm, Irating=15A
Isat=40A
S
1
20071122
D
D
D
D
1
GAP-CLOSE-PWR
G63
2
Id=7.5A
G
Qg=4~5nC,
Rdson=26~30mohm
2
1
G
S
S
S
1
GAP-CLOSE-PWR
G64
2
4
3
2
1
1
GAP-CLOSE-PWR
G65
2
1
2
DY
U36
SI4800BDY-T1
C318
SCD1U50V3KX-GP
1
GAP-CLOSE-PWR
G66
2
C317
SC10U25V6KX-1GP
1
D
C544
SC10U25V6KX-1GP
D
TC14
ST15U25VDM-1-GP
2
GAP-CLOSE-PWR
G67
2
1
1
1
GAP-CLOSE-PWR
TONSEL
GND
OPEN
V5FILT
240k/CH1
300k/CH2
300k/CH1
360k/CH2
360k/CH1
420k/CH2
A
<Core Design>
A
Wistron Corporation
Vout=0.758V*(R1+R2)/R2 --> PWM mode
Vout=0.764V*(R1+R2)/R2 --> Skip Mode
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51124_1D8V/1D2V
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
37
of
44
5
4
3
2
1
1D1V_PWR
1D1V_S0
G47
1
DCBATOUT_51117
1
R135 0R2J-2-GP
1
2
51117A_EN_PSV
17,21,22,30,33 PM_SLP_S3#
51117A_TON
51117A_TRIP
1
1 R132
2
249KR2F-GP
14
5
VBST
VFB
1
2
11
EN_PSV
DRVH
LL
51117A_DRVH
12
51117A_LL
DRVL
VOUT
PGOOD
9
3
6
51117A_DRVL
GND
PGND
7
8
TON
TRIP
GAP-CLOSE-PWR
G45
2
2
GAP-CLOSE-PWR
G34
2
1
1
1
GAP-CLOSE-PWR
G43
2
1
GAP-CLOSE-PWR
G33
2
1
GAP-CLOSE-PWR
G42
2
1
GAP-CLOSE-PWR
G41
2
1
GAP-CLOSE-PWR
G40
2
1
GAP-CLOSE-PWR
G39
2
1
GAP-CLOSE-PWR
G38
2
1D1V Iomax=9A
OCP>18A
1
C93
1
1
1
1
C108
2
2
2
2
5
6
7
8
1
R115
31K6R2F-GP
2
V5FILT
V5DRV
13
TC7
SE330U2D5VDM-LGP
SANYO
ESR=15mohm
D
C
GAP-CLOSE-PWR
20071024
1D1V_PWR
3D3V_S5
20071016
1
K
51117A_VBST
51117A_VFB
4
10
1
2
GAP-CLOSE-PWR
G35
2
GAP-CLOSE-PWR
G44
2
1D1V_PWR
DY
D
D
D
D
Id=10A
Qg=9~13nC,
Rdson=12~15mohm
U26
G
S
S
S
1R3F-GP
R118
15KR2F-GP
51117A_VFB
4
3
2
1
2
1
2
SCD1U25V3KX-GP
GAP-CLOSE-PWR
G46
2
GAP-CLOSE-PWR
SCD1U10V2KX-4GP
A
1/31
C115
1
2
SC18P50V2JN-1-GP
2
SI4812BDY-T1-E3-GP
C416
SC1U10V2KX-1GP
D7
B0530WS-7-F-GP
C
U24
R675
1
2
2
1
5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1
1
1
51117A_V5FILT
1
Vo(cal)=1.1060V
1
2
IND-1D5UH-23-GP
1/31
5V_S5
Cyntec 10*10*4
DCR=4.2mohm, Irating=16A
Isat=33A
11/13
L3
R125
300R3F-GP
2
C109
SC1U10V2KX-1GP
C86
SC10U25V6KX-1GP
Id=7.5A
Qg=4~5nC,
Rdson=26~30mohm
SC10U25V6KX-1GP
SCD1U50V3KX-GP
5V_S5
C85
1
C87
D
U20
SI4800BDY-T1
1
DCBATOUT
G36
2
TPS51117PWR-GP
R113
Vout=0.75*(R1+R2)/R2
200KR2F-L-GP
2
2
R121
20KR2F-L-GP
B
B
C116
SCD1U10V2KX-4GP
2
DY
151117A_EN_PSV
1D1V_PWRGD 33
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
TPS51117_1D1V
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
38
of
44
5
4
3
2
1
D
D
1D2V_S5
Iomax=400mA
3D3V_S5
1D5V_S0
Iomax=1A
G957
1D2V_S5
1D5V_S0
G85
1
1
1
2
3D3V_S0
3
2
1
C88
G957T65UF-GP
74.95765.03C
1
2
GAP-CLOSE-PWR
VOUT
GND
VIN
Place near to SB700
C
2D5V_S0
Iomax=0.3A
B
5V_S5
GAP-CLOSE-PWR
G86
1
2
U21
DY
SC1U10V3KX-3GP
G9161-120U65U-GP
74.09161.E3C
C92
SC10U10V5KX-2GP
2
1
2
IN
GND
OUT
1
2
3
1
2
2
U59
C553
SC10U6D3V5MX-3GP
C
C556
SC10U6D3V5KX-1GP
DY
SC1U10V3KX-3GP
C576
SC10U10V5KX-2GP
1
C574
11/13
Iomax=1A
OCP>2A
1D8V_S3
2
2D5V/300mA
SCD1U10V2KX-4GP
2
GND
1
1
1
2
C501
VOUT
VIN
2
3
G9131-25T73UF-GP
74.09131.A31
2
GAP-CLOSE-PWR
C507
SC4D7U6D3V5KX-3GP
1
GAP-CLOSE-PWR
C271
SC10U10V5KX-2GP
1
11
SC1U10V3KX-3GP
A
2
11/13
C285
GAP-CLOSE-PWR
G51
1
2
1
2
3
4
5
2
VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
1
10
9
8
7
6
2
2
R166
9026_S5
1
0R2J-2-GP
9026_S3
1
0R2J-2-GP
1
DDR_VREF_S3
2
GND
R168
G52
2
GAP-CLOSE-PWR
G49
1
2
U30
17,22,30,37 PM_SLP_S5#
U57
G50
1
1
2
C290
SCD1U10V2KX-4GP
2D5V_S0
2D5V_LDO
0D9V_S3
DDR_VREF_PWR
2
C292
SC1U10V3KX-3GP
2
1
C293
SC10U10V5KX-2GP
1
3D3V_S0
11/13
B
C272
SC10U10V5KX-2GP
TPS51100DGQR-GP
11/13
<Core Design>
A
11/13
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
0D9V&2D5V&1D25V&1D5V
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
39
of
44
5
4
3
2
Adaptor in to generate DCBATOUT
D
1
D
AD+
AD_JK
DCIN1
1
C1
SCD1U50V3ZY-GP
D9
P4SSMJ27APT-GP
R2
DTC114EUA-1-GP
E
C
1
C3
R223
100KR2J-1-GP
2
PDTA124EU-1-GP
Q16
8
7
6
5
1
B
R1
AD_OFF#_JK
1 GND
2
R2
3 OUT
2
200KR2F-L-GP
Q15
R1
2
IN
AD_OFF
D
D
D
D
AO4433-GP
R226
DC-JACK135-GP
30
AD+_2
1
A
2
C2
SCD1U50V3ZY-GP
SC1U50V5ZY-1-GP
2
4
5
6
NP1
2
1
3
U44
S
S
S
G
1
2
3
4
K
1
C
C
3D3V_AUX_S5
BATTERY CONNECTOR
B
B
2
1
2
1
D13
1
D12
BAV99PT-GP-U
DY
RN28
1
2
BATA_SCL_1
BATA_SDA_1
4
3
8
1
2
3
4
5
6
7
9
2
BAV99PT-GP-U
30,41 BAT_SCL
30,41 BAT_SDA
30 BAT_IN#
CN7
R241
100KR2J-1-GP
3
DY
3
DY
3
D11
BAV99PT-GP-U
2
1
3D3V_AUX_S5
SRN33J-5-GP-U
2
1
1
2
1
1
2
1
2
2
EC41
DY
EC39
DY
SC10P50V2JN-4GP
EC2
SC1000P50V3JN-GP
A
EC1
SCD1U50V3ZY-GP
SC1000P50V3JN-GP
EC3
SCD1U50V3ZY-GP
SC10P50V2JN-4GP
1
EC40
DY
2
BT+
TYCO-CON7-11-GP
G14
1
41 BATT_SENSE
2
<Core Design>
A
GAP-CLOSE
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
AD_IN/ BTY SWITCH/GPURUN
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
40
of
44
5
4
1
GAP-CLOSE-PWR
2
2
G2
1
2
1
G1
GAP-CLOSE-PWR
A
K
1
24
BQ24745_BST
BQ24745_VDDP
1SS4000GPT-GP
2BQ24745_FBO
BQ24745_EAI
BQ24745_EAO
BQ24745_VREF
BQ24745_CHG_ON
C7
R14
SC2200P50V2KX-2GP
7K5R2F-1-GP
2
1BQ24745_EAO_RC2
1
1
2
C10
SC56P50V2JN-2GP
C9
SC1U10V3KX-3GP
1
6
5
4
3
7
12
2
1
C42
SC10U25V6KX-1GP
B
FBO
EAI
EAO
VREF
CE
GND
U3
BQ24745RHDR-GP
NC#16
16
VFB
15
CHG_AGND
BATT_SENSE
BATT_SENSE 40
BQ24745_CSIP
C18
BQ24745_CSIN
1
1 R17
2
200KR2F-L-GP
C19
2
2
BQ24745_FBO_RC
17
SCD1U50V3KX-GP
GND
2
CSON
VICM
SCD1U25V2ZY-1GP
C14
SC220P50V2KX-3GP
2
1
1
B
4K7R2J-2-GP
R13 1
8
18
29
C6
1
R21
0R0402-PAD
SC150P50V2JN-3GP
19
CSOP
4
3
2
1
CHG_AGND
BQ24745_IINP
2
2
1
PGND
S
S
S
G
AD_IA
NC#14
U2
FDS8884-GP
D
D
D
D
14
connect to KBC
30
IND-5D6UH-32-GP
C40
SC10U25V6KX-1GP
2
1
24745_LOW_G
connect to KBC
1
2
R20
D01R2512F-4-GP
C44
SC10U25V6KX-1GP
2
1
20
2BT+_R
C15
SC10U25V6KX-1GP
2
1
LGATE
BT+
L33
1
1
23
1
2
C16
SCD1U50V3KX-GP
BQ24745_LX1
C17
SC10U25V6KX-1GP
2
1
PHASE
SDA
CHG_AGND
CHG_AGND
C
24745_HIGH_G
SCL
G4
GAP-CLOSE-PWR
1
2
9
BAT_SDA
SC1U10V3KX-3GP
C12
SCD1U16V2KX-3GP
ACOK
connect to KBC
30,40
C389
1
2
A
1
UGATE
K
2
25
21
D10
G3
GAP-CLOSE-PWR
1
2
10
BAT_SCL
BOOT
VDDP
BQ24745_CSSN
TP1
2
30,40
27
26
5
6
7
8
R22
0R2J-2-GP
2
1BQ24745_ACOK 13
AC_OK
C387
SC1U10V3KX-3GP
VDDSMB
CSSN
ICOUT
2
ACIN
28
U1
FDS8884-GP
2
5
6
7
8
BQ24745_ACIN
CSSP
4
3
2
1
DCIN
1
C954
SCD1U50V3KX-GP
CHG_AGND
C11
SC10U25V6KX-1GP
EMI ADDED 11/16
2
C384
SC10U25V6KX-1GP
1
1
1
22
ICREF
BQ24745_DCIN
11
1
C385
SCD1U50V3KX-GP
CHG_AGND
3D3V_AUX_S5
2
1
2
1
4
5
6
2
C386
2
S
S
S
G
C8
SCD01U50V2KX-1GP
1
C
D
DCBATOUT
SCD1U50V3KX-GP
2
1 BQ24745_CSSP
D
D
D
D
309KR3F-GP
AC_OK
SC1U50V5ZY-1-GP
R12
8
7
6
5
R59
470KR2J-2-GP
2
2
2
1
AD+ C20
D
D
D
D
P2003EVG-GP
D5
1SS4000GPT-GP
Q18
2N7002DW-1-GP
S
S
S
G
1
2
3
4
AD+
AD+
3
2
1
DC_IN_D
2
2
D01R2512F-4-GP
AD+_G_2
AD+_G_1
R18
49K9R2F-L-GP
1
R10
1
AD+_TO_SYS
R232
10KR2F-2-GP
1
R231
2
D
10KR2F-2-GP
P2003EVG-GP
BT+
U10
C383
SC10U25V6KX-1GP
1
DCBATOUT
2
1
2
3
4
R233
100KR2J-1-GP
S
S
S
G
1
2
1
C21
SC10U25V6KX-1GP
U45
D
D
D
D
2
NEAR
AD+
8
7
6
5
3
CHG_AGND
3D3V_AUX_S5
1
3D3V_AUX_S5
1
Q19
2N7002-11-GP
AC_OK
31
CHG_ON#
connect to KBC
G
S
G
CHG_AGND
C13
SCD1U10V2KX-4GP
2
1
2
1
R234
100KR2J-1-GP
2
Q20
2N7002-11-GP
BQ24745_CHG_ON
D
1
Jeff Modify 1129
100KR2J-1-GP
R236
2
C388
SC1U10V3KX-3GP
2
R23
0R0402-PAD
3D3V_AUX_S5
DY
<Core Design>
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
S
2
1
A
AC_IN#
AC_IN#
D
30
2
AC_IN# to KBC
connect to KBC
1
100KR2J-1-GP
R19
R235
100KR2J-1-GP BQ24745_VREF
Title
CHARGER_BQ24745
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
41
of
44
5
4
3
CPU_CORE
Intersil ISL6265
D
Charger Max8725
VID Setting
CPU_SVD
Input Signal
Output Signal
SVD
CPU_SVC
2
PGOOD
VGATE_PWRGD
Adapter
Output Signal
MAX8725_VCTL
BATT
ICTL
BATT_SENSE
CHARGE_ON1#
PKPRES
Input Signal
PHASE0
Voltage Sense
CPU_VDD0_RUN_FB_H
ACOK
CPU_VDD0_RUN_FB_L
AD+
ACIN
BT+
DCBATOUT
VOUT (O)
BOOT_NB
Input Power
VCC(I)
TPS51124
1D8V_S3
1D2V_S0
TPS51117
GPU_CORE
5V_S0
VCC(I)
3D3V_S0
AD+
VCC(O)
VCC(I)
CPU_VDDNB
RTN1
DCBATOUT_6265
VOUT (O)
PHASE1
RTN0
CPU_VDD1_RUN_FB_L
Output Power
Input Power
VCC_CORE0
D
AD_IN
(O)
AC_IN#
Output Power
VCC_CORE1
VSEN1
Output Signal
(I)
AD_JK
VSEN0
CPU_VDD1_RUN_FB_H
Input Signal
VCC(I)
PM_SLP_S3#
Input Signal
Output Power
EN
PM_SLP_S5#
GPU_CORE_S0
VOUT (O)
C
Input Signal
Input Power
1D8V_S3
C
VOUT (O)
1D2V_S0
VIN
5V_S5
5V_S5
VIN
VCCA
3V/5V_POK
VOUT (O)
DCBATOUT_51124
DCBATOUT_51117
Output Signal
PGOOD1
Output Power
EN1
EN2
VCORE_EN
Input Power
TPS51125
5V/3D3V
51125_ENTRIP2
AD_OFF
Output Power
PGD_IN
Input Power
51125_ENTRIP1
Input Signal
SVC
VCORE_EN
1
ENTRIP1
ENTRIP2
Output Power
Input Power
3D3V(O)
TPS51117
1D1V_S0
RT9026PFP
0D9V_S3
5V_S5
5V(O)
3D3V_S5
Input Signal
PM_SLP_S5#
Input Signal
Output Signal
PM_SLP_S3#
EN
Output Signal
1D1V_PWRGD
EN
POK
3D3V_AUX_S5
DCBATOUT_51125
VREG3
VIN
VOUT (O)
5V_AUX_S5
0D9V_S3
Input Power
VREG5
1D8V_S3
5V_S5
5V_S5
VIN
DCBATOUT_51117
VIN
Input Power
VIN
Output Power
VOUT (O)
1D1V_S0
VIN
G9161
1D2V_S5
B
Input Power
3D3V_S5
VIN
Output Power
B
G957
1D5V_S0
VOUT
1D2V_S5
Input Power
3D3V_S0
VIN
Output Power
1D5V_S0
VOUT (O)
A
A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Power Block Diagram
Size
A2
Document Number
Rev
S13
Date: Friday, May 16, 2008
5
4
3
2
SC
Sheet
1
42
of
44
5
4
3
2
1
C728
1
2
SCD1U10V2KX-4GP
5V_S5
DCBATOUT
C729
1
DY DY
DY
1
DY
1
C720
C721
C735
1
2
1
1
C722
2
1
C702
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
1
1
1
DY
C701
SCD1U10V2KX-4GP
DY
C703
SCD1U10V2KX-4GP
DY
C700
SCD1U10V2KX-4GP
DY
C697
1D1V_S0
+VCC_CORE0
CPU_VDDNB
DCBATOUT
2
SCD1U10V2KX-4GP
DY
3D3V_S5
C733
1
2
DCBATOUT
SCD1U10V2KX-4GP
C734
1
1D8V_S3
+1.8V_MEM_VDDQ
2
1D2V_S0
SCD1U10V2KX-4GP
DY
C696
SCD1U10V2KX-4GP
DY
C698
SCD1U10V2KX-4GP
C699
SCD1U10V2KX-4GP
1
1D8V_S0
SCD1U10V2KX-4GP
C681
SCD1U10V2KX-4GP
DY
C679
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
H12
HOLE
DY
SCD1U10V2KX-4GP
H9
HOLE
C683
SCD1U10V2KX-4GP
H7
HOLE
DY
C682
SCD1U10V2KX-4GP
H15
HOLE
C680
SCD1U10V2KX-4GP
H16
HOLE
SCD1U10V2KX-4GP
DY
2
SCD1U10V2KX-4GP
C730
1
SCD1U10V2KX-4GP
3D3V_S5
H6
HOLE
1
H5
HOLE
2
H20
HOLE
DY
D
SCD1U10V2KX-4GP
C731
1
2
1
1
1
1
1
H17
HOLE
DCBATOUT
2
C717
3D3V_S0
5V_S0
H18
HOLE
C714
SCD1U10V2KX-4GP
C690
C713
SCD1U10V2KX-4GP
DY
C689
C715
SCD1U10V2KX-4GP
DY
C686
C716
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
C684
SCD1U10V2KX-4GP
DY
C688
SCD1U10V2KX-4GP
C678
C687
SCD1U10V2KX-4GP
C677
C685
SCD1U10V2KX-4GP
C676
SCD1U10V2KX-4GP
C674
SCD1U10V2KX-4GP
DY
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY
SCD1U10V2KX-4GP
H19
HOLE
SCD1U10V2KX-4GP
H4
HOLE
SCD1U10V2KX-4GP
H1
HOLE
1
5V_S5
D
H2
HOLE
2
SCD1U10V2KX-4GP
3D3V_S0
H3
HOLE
C727
1
2
+VCC_CORE1
SCD1U10V2KX-4GP
2
DY
DY
1
C719
2
1
C718
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
1
DY
C724
1
DY
C723
SCD1U10V2KX-4GP
DY
C725
SCD1U10V2KX-4GP
H21
HOLE
C726
SCD1U10V2KX-4GP
1
1D5V_S0
0D9V_S3
DY
SCD1U10V2KX-4GP
1
DY
C706
SCD1U10V2KX-4GP
1
DY
C705
SCD1U10V2KX-4GP
1
DY
C708
SCD1U10V2KX-4GP
DY
C709
SCD1U10V2KX-4GP
DY
C711
SCD1U10V2KX-4GP
C694
SCD1U10V2KX-4GP
C693
SCD1U10V2KX-4GP
H8
HOLE
C712
SCD1U10V2KX-4GP
H13
HOLE
C691
SCD1U10V2KX-4GP
H14
HOLE
DY
SCD1U10V2KX-4GP
H11
HOLE
C692
SCD1U10V2KX-4GP
H10
HOLE
DY
SCD1U10V2KX-4GP
1
C
1
C
BT+
B
B
14
9
U9C
SSAHCT125PWR-GP
8
7
10
14
SPR4
SPRING-57-GP
1
1
1
U9D
SSAHCT125PWR-GP
11
7
12
DY
1
13
1
C736
2
1
2
1
2
1
2
2
C732
SCD1U10V2KX-4GP
C737
SCD1U10V2KX-4GP
SPR3
SPRING-57-GP
C738
SCD1U10V2KX-4GP
SPR2
SPRING-58-GP
C710
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SPR1
SPRING-57-GP
1
AD+
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
MISC
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
43
of
44
5
4
3
2
1
NOTICE
D
D
Change List
Common Part
C
1.RS780M_A12
U55
71.RS780.M12
2.SB700_A12
U62 71.SB700.M06
3.KBC U29 71.00773.00G
4.CLKGEN U32 71.09480.A03
5.SIDE PORT U28 72.18512.M0U
6.MOSFET U52,U51 84.07686.037
7.MOSFET U13,U12,U49,U50
84.04634.037
8.H18,H19 34.4H802.001
9.CARD1 20.I0043.001
10.U61 71.00380.003
11. U11 74.06265.A73
12. U42 71.00888.E0G
13. U31 72.25X16.A01
C
B
B
<Core Design>
A
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CHANGE LIST
Size
A3
Document Number
Date: Friday, May 16, 2008
5
4
3
2
Rev
S13
SC
Sheet
1
44
of
44