Fundamentals of combinational logics

Fundamentals of
combinational logics
Michal Lucki
Author: Michal Lucki
Title: Fundamentals of combinational logics
Compiled by: České vysoké učení technické v Praze
Faculty of Electrical Engineering
Contact address: Technicka 2, Prague 6, Czech Republic
Inovace předmětů a studijních materiálů pro
e-learningovou výuku v prezenční a kombinované
formě studia
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EXPLANATORY NOTES
Definition
Interesting
Note
Example
Summary
Advantage
Disadvantage
ANNOTATION
The goal of this module is to introduce the principles of combinational logics. Minimization
of Karnaugh maps and rules of Boolean algebra are presented. Last but not least, selected
aspects of more advanced logic circuits and their design are discussed.
OBJECTIVES
After studying this module, a student should know the principles of operation of common
combinational components and circuits, such as logical gates, latches, and multiplexors. A
student should be able to minimize logical functions by using Boolean algebra as well as
Karnaugh maps. The student should be familiar with the approach to combinational logic
devices and should know the design steps used to solve practical tasks, beginning with the
specification of logical variables, going through determining truth tables, Karnaugh maps to
the final appearance of a logical circuit, which would control the considered process.
LITERATURE
[1]
GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the
Logic of Sets (IEEE Press Understanding Science & Technology Series) , Mar 16, 1998
[2]
WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer
Science), Mar 18, 2010
[3]
MENDELSON E.: Schaum's Outline of Boolean Algebra and Switching Circuits, Jun 1,
1970
[4]
ROTH, Ch.: Fundamentals of Logic Design by, Mar 13, 2009
Index
1 Boolean algebra .................................................................................................................... 6
1.1
Goals of Boolean algebra ........................................................................................... 6
1.2
Rules of Boolean algebra ........................................................................................... 7
1.3
Basic operations on logical statements ....................................................................... 8
2 Minimization of logical functions ....................................................................................... 9
2.1
Binary Coded Decimal ............................................................................................... 9
2.2
Gray code ................................................................................................................. 11
2.3
Expression of logical functions ................................................................................ 13
2.4
Specification of a logical function from a truth table ............................................... 14
2.5
Karnaugh maps ......................................................................................................... 15
2.6
Minimization of logical functions ............................................................................ 17
2.7
Shortcuts for minimizing Karnaugh maps (1/2) ....................................................... 18
2.8
Shortcuts for minimizing Karnaugh maps (2/2) ....................................................... 20
2.9
5-variable Karnaugh maps........................................................................................ 22
2.10
6-variable Karnaugh maps........................................................................................ 23
3 Logical components and blocks used in combinational logics ....................................... 24
3.1
Logical gates (1/2) .................................................................................................... 24
3.2
Logical gates (2/2) .................................................................................................... 26
3.3
2-input multiplexor with selection ........................................................................... 27
3.4
N-bit to m-bit parallel decoder ................................................................................. 29
4 More advanced logical circuits ......................................................................................... 31
4.1
Latches...................................................................................................................... 31
4.2
RS latch – principle of operation .............................................................................. 32
4.3
RS latch – NAND implementation ........................................................................... 35
4.4
D-type latch .............................................................................................................. 36
5 Combinational logic in circuits controlling practical devices ........................................ 37
5.1
Task – combinational logic ...................................................................................... 37
5.2
Case study – combinational logic in a factory ......................................................... 39
6 Final test .............................................................................................................................. 42
1 Boolean algebra
1.1 Goals of Boolean algebra
Boolean algebra has as its aim to use mathematical operations to represent and
rigorously test logical arguments. A logical statement is a declarative sentence
that is true or false. Logical statements can be combined by using operators (for
example AND, OR).
Logical conjunction is an operation on two logical values, typically two
propositions that produces a value of true if and only both its operands are true,
otherwise the value is false. In logic and mathematics, a two-place logical
operator AND is used to form a conjunction.
A disjunction is an operation on logical values that produces true whenever one or
more of its operands are true (a false value is produced if and only both operands
are false). A disjunction is known as inclusive disjunction or alternation. Literals
of a statement are separated by OR operator.
Because of the similarities to arithmetic operators, AND operator is known as
logical multiplication or product, while OR operator is known as logical addition
or sum.
A proposition can be an input variable that is assigned to a symbol. Then we can
express logical statements as functions:
Logical statements combined by using logical operators.
It is winter
Logical
expression
y=a
It is winter AND it is snowing
y=a&b
AND
It is winter OR it is night
y=a|b
OR
It is winter XOR it is summer
y=a^b
XOR
It is NOT true that it is winter
It is NOT true that: it is winter AND it is
snowing
It is NOT true that: It is winter OR it is
night
It is NOT true that: It is winter XOR it is
summer
y=a
NOT
y = a&b
NOT, AND
y = a|b
NOT, OR
y = a ^b
NOT, XOR
Statement
Used operator
BUF
1.2 Rules of Boolean algebra
Basic rules of Boolean algebra performed on a logical argument are summarized
in the following table:
Basic logical operations.
Symbolic expression Result
Comment
y=a&0
y=0
y=a&1
y=a
y=a|0
y=a
y=a|1
y=1
y=a&a
y=a
The idempotent rule
y=a|a
y=a
The idempotent rule
y = a&a
y=0
The complementary rule
y = a |a
y=1
The complementary rule
y = a | (a & b)
y=a
The absorption rule
y = a & (a | b)
y=a
The absorption rule
The precedence of operations in Boolean algebra are summarized in the following
table:
Equivalent expression of logical functions by using basic rules in binary logic.
Logical
function
w = a, y = w
Equivalent
expression
y=a
The involution rule
y=a&b
y=b&a
The commulative rule
y=a|b
y = (a & b) &
c
y = (a | b) | c
y=b|a
y = a & (b
& c)
y = a | (b | c)
y = a | (b &
c)
The commulative rule
y=a|b&c
Comment
The associative rule
The associative rule
Precedence of operators. AND has higher
precedence than OR
7
1.3 Basic operations on logical statements
Basic transformations possible in Boolean algebra in order to simplify logical
functions and expressions are presented in the following table:
Transformations of logical functions by using basic rules in binary logics.
Logical
function
Equivalent
expression
y = a & (b | c)
y = (a & b) |(a & c)
y = a | (b & c)
y = (a | b) & (a | c)
a&b
a|b
De Morgan transformation
a|b
a&b
De Morgan transformation
a&b
a| b
De Morgan transformation
a |b
a&b
De Morgan transformation
Comment
The distributive rule. It can be compared
to arithmetic operations:
6 x (5 + 2) = (6 x 5) + (6 + 2)
The distributive rule. It cannot be
compared to arithmetic operations:
6 + (5 x 2) ≠ (6 + 5) x (6 + 2)!!
The above operations refer to two-value logic (binary). A logical variable can
have two values: zero or one. In general, other possibilities are excluded.
However, some practical applications assume the existence of undefined states (high impedance can mean
that no values were produced yet), so-called „don’t know states“ (we do not know, if the value assigned is 0
or 1) and „don’t care states“ (no matter the value, the operation is identical).
Boolean algebra is a tool suitable for description of operation of digital devices. A
digital quantity is one that can be represented as being in one of a finite number of
states, such as 0 and 1, ON and OFF, UP and DOWN). These states are called
quanta.
Many electric devices act as analog, but in real, they are digital with dense quantization. However, the natural
processes are analog. Digital representation is its approximation.
8
2 Minimization of logical functions
2.1 Binary Coded Decimal
A BCD code (Binary Coded Decimal) is a code, which is a four-position Binary
Coded Decimal. A code word represents a binary value. 2-position BCD
represents the following code words: 00, 01, 10, 11. For a 3-position BCD, they
are: 000, 001, 010, 011, 100, 101, 110, 111.
4-position BCD
It is known as 8421, named after decimal values corresponding to particular bits
of a 4-bit binary string, starting with the most significant bit at the left hand (23,
22, 21, 20 = 8, 4, 2, 1). The following code words can be created in a 4-position
BCD. In brackets, we present decimal values corresponding to those binary
values:
•
0000 (0 in decimal)
•
0001 (1 in decimal)
•
0010 (2 in decimal )
•
0011 (3 in decimal)
•
0100 (4 in decimal)
•
0101 (5 in decimal)
•
0110 (6 in decimal)
•
0111 (7 in decimal )
•
1000 (8 in decimal )
•
1001 (9 in decimal)
•
1010 (10 in decimal )
•
1011 (11 in decimal)
•
1100 (12 in decimal)
•
1101 (13 in decimal )
•
1110 (14 in decimal )
•
1111 (15 in decimal)
In general, one can assign any values to particular code words. Since practical
applications require providing an algorithm to convert code words, a systematic
9
approach to code words is used. In addition, an encoding algorithm should have
the ability to detect or correct code words.
There is a shortcut for generating an n-position words in BCD, without the
necessity to convert decimal values into binary ones. Observe how the table is
being filled out gradually.
Shortcut for creating BCD code words.
10
2.2 Gray code
The Gray code is a binary system named after Frank Gray, in which two
successive code words differ in one bit.
It is used to facilitate error correction. In addition, many devices indicate position
by opening switches, which change their value synchronously in a sequence. It is
more likely that a sequence 011 → 001→ 101 → 100 is more expected than 011
→ 100.
2-position Gray code
•
00
•
01
•
11
•
10
3-position Gray code
•
000
•
001
•
011
•
010
•
110
•
111
•
101
•
100
4-position Gray code
•
0000
•
0001
•
0011
•
0010
•
0110
•
0111
11
•
0101
•
0100
•
1100
•
1101
•
1111
•
1110
•
1010
•
1011
•
1001
•
1000
Did you notice that neighbor rows differ in one bit? First and last row are also
neighbor rows. This is found as an advantage for potential minimization of logical
functions.
12
2.3 Expression of logical functions
A minterm is a logical expression using logical AND, for example a & b & c .
A maxterm is a logical expression using logical OR, for example a | b | c.
Logical functions can be expressed by using minterms and/or maxterms. The
particular states can be represented in truth tables or Karnaugh maps.
A truth table is a mathematical expression used in logics - specifically with
Boolean functions, to compute the functional values of logical expressions on
each of functional arguments. Truth tables specify, if a statement is true or false
for given input values.
Practically, a truth table contains a column for each input variable (for example a,
b), and one or more final columns for all of the possible results of the logical
operations. Each row contains one combination of input variables (0s and 1s), and
the result of the operation – true (1) or false (0).
Let us consider an exemplary logical function: y = a| b
The operation of a device implementing these functions can be described by the
following table:
Sample truth table.
13
2.4 Specification of a logical function from
a truth table
In some cases, when the truth table is given, but the mathematical expression of
a logical function is unknown, the function can be extracted from the truth table.
Minterms and maxterms are useful for determining Boolean equations from truth
tables. The minterms corresponding to each line of the truth table, for which the
output is 1 are combined using OR, creating the sum of products. Another
approach uses maxterms to create the product of sums – logical outputs being
logical 0s are combined by using AND.
Specification of logical function from a truth table as a sum of products.
Specification of logical function from a truth table as a product of sums.
Notice that the function obtained by extracting it directly from the truth table is not the simplest (canonic)
form. It can be simplified, still covering all the states of operation, either by using basic rules of Boolean
algebra, or, by minimizing so-called Karnaugh maps, which are one of the forms of expression of a logical
function.
14
2.5 Karnaugh maps
A Karnaugh map is a form of representation of logical functions used for
reduction of mathematical description of logical function and the minimization of
number of logical gates in practical implementations. Karnaugh maps offer a good
overview on the logical states that could be dropped, because they are covered by
some other minterm or maxterm.
A Karnaugh map is named after Maurice Karnaugh, pronounced like “car-no”.
Let us consider a 2-input logical AND gate:
2-input logical AND gate, corresponding truth table and Karnaugh map.
The Karnaugh map has a cell for every line in the truth table. The values “00”,
“01”, “11”, “10” are the possible combinations of values of logical variables “a"
and “b”. This ordering is known as a Gray code. Notice that each symbol differs
from the neighbor symbol in one digit. It is impossible to copy the following rows
from the truth table to the Karnaugh map – then we would have 01 after 10 – they
differ at both digits. The map is filled with 0s and 1s that correspond to logical
value of the output “y” for given combination of “a” and “b”. For a clearer view, I
present an organization 3-input Karnaugh map and a 4-input Karnaugh map.
3-input Karnaugh map.
15
4-input Karnaugh map.
16
2.6 Minimization of logical functions
Let us consider a truth table. We specify the function by using product-of-sums or
sum-of-products.
Truth table for determining a Karnaugh map.
To minimize the function to canonic form, let us map its input and output values,
as according to the rules presented at the previous slide. Variables are combined
by logical multiplication and particular states are combined by logical OR (we
find minterms and create the sum of products).
Karnaugh map determined from the truth table.
y = ( a & c )| ( a & b )
We notice that for the horizontal group of 1s, “a” is always 0 (for both cells), but
“b” is zero for the left cell or 1 for the right cell. Changing the value of “b” does
not affect the result of this group, which is always 1 (yellow digits). “b” is
redundant and can be dropped from the equation describing the logical state,
which can be expressed as the negation of “a” because it is always 0 for that
group, and “c”, which is always 1 for that group: y = ( a & c ) . Similarly, in the
vertical blue group “a” is assigned 1 for both cells, “b” is 0, and “c” can be
discarded because no matter the value of “c”, the result is always 1. Then, the
final group can be expressed as y = ( a & b) . We have two possible states that
appear alternatively; we can combine them by a logical sum.
17
2.7 Shortcuts for minimizing Karnaugh maps
(1/2)
The goal is to find minterms, for which redundant variables can be discarded from
a minterm. The following paragraph shows examples of grouping minterms.
Shortcut for minimization of logical functions by discarting variables from a minterm.
y = (c & d )
Two groups. One cell is used twice. In each minterm, two variables are discarded.
Notice that some cells belong to more than one minterm.
Cells used in many groups.
y = (a & b) | (c & d )
Two groups. Two cells used twice.
18
Cells used in many groups.
y = (a & b) | (b & c)
19
2.8 Shortcuts for minimizing Karnaugh maps
(2/2)
We group cells, which are not neighbors physically, but they are adjacent in terms
of logics.
Notice that first and last row (“c” and “d”) differ in one digit (00 versus 10). We
can group cells in those rows. The similar situation is for first and fourth column.
Neighbor cells in different rows and columns concurrently.
Diagonally adjacent minterms generally don’t form groups. However,
remembering that first and fourth column, as well as first and fourth row is
logically adjacent, we can form a group from four cells that make impression they
were formed at the diagonal.
The following figure presents diagonally adjacent cells:
Minimization of diagonal cells.
There are “unknown states” denoted by “?”. The logical value can be 0 or 1 and is
unknown, or “don’t-care” or impossible states denoted by “–” meaning that no
matter the logical value (from two possible states 0 or 1), the operation of a circuit
is not affected. They can be part of a group.
20
Minimization of unknown and don’t care states.
21
2.9 5-variable Karnaugh maps
Since neighbor (in other words: adjacent) columns are those, which differ in one
bit, it is necessary to check the column reflected by the mirror line (solid double
line). There are two groups, which are divided by this line. In addition, one group
is made of elements in the first and the last row, which are also considered as
neighbor rows. Rows/columns labeling correspond to the following code words of
a Gray code.
5-variable Karnaugh maps.
y = ( a & b & e) | (b & d e)
22
2.10 6-variable Karnaugh maps
An example of a 6-variable Karnaugh map. Notice that solid double lines are no
longer the lines of symmetry. Another approach is used. Labeling of columns and
rows also differs to the labeling of a 5-variable map (a Gray code is used only in
particular quarters). However, the basic rule to minimize neighbor cells (in terms
of logic) is still valid.
6-variable Karnaugh maps.
Please, notice that there is no line of symmetry, columns and rows are assigned
the values of 000, 001, 011, 010, 100, 101, 111, 110 instead of 000, 001, 011, 010,
110, 111, 101, 100 (both options are possible; this modifies the minimization
procedure). Think logic!
23
3 Logical components and blocks used in
combinational logics
3.1 Logical gates (1/2)
To express physical implementation and to represent the functionality of an
element for different input states, we use logical gates, called also primitive gates,
primitives, or simply gates.
BUF
An output has the same value as an input; in real systems it causes a time delay.
NOT
An output is the negation of an input. Two NOTs in series operates as BUF – they
cancel each other, but there is a time delay.
2-input AND
It operates as conjunction or logical multiplication. The output is true (1) if all the
inputs are true.
2-input OR
It operates as an alternative or logical sum. The output is true (1) if at least one of
the inputs (or more) is true.
2-input XOR
Known as an exclusive OR. It results with 1 if one of the inputs is 1 and the other
is 0. True output excludes the case when both inputs are true.
NAND
The negation of an AND (AND in series with NOT).
NOR
The negated OR.
24
XNOR
The negation of XOR. Known also as NXOR.
25
3.2 Logical gates (2/2)
Some gates can be considered as some modification of basic gates. For example
NAND is negated AND, NOR is negated OR. XNOR (also known as NXOR) is
the negated XOR.
However, combining two gates, for example NOT and AND to achieve the same function as NAND produces
greater delay of signals, since more components are used, and every component contributes to the delay.
Delays are not desired in many applications, since they affect synchronization and can result in dropping the
produced bits.
Symbolic representation of basic gates used in combinational logic.
In practice, many circuits require the minimum number of gates. Then, the same
function must be achieved by using the same gates. For example, a NAND can
operate as NOT, if both inputs are connected to each other, then both inputs
exhibit the same value and act as one-input negation.
26
3.3 2-input multiplexor with selection
A multiplexor is a device using a binary value that acts as an address to select
between numbers of inputs.
2-input multiplexor – the principle of operation
Considering the below circuit, if a control signal (select) is set to 0, the
multiplexor copies the binary value from data (d0) to the output, no matter the d1
value is. Since the control signal (select) is logic 1, the multiplexor copies the
value from d1 to the output, no matter the d0 value is.
“Select” decides, if data are copied from d0 (if set to 0) or d1 (if set to 1).
Block scheme and internal organization of a 2-input multiplexor.
Table of states of a 2-input multiplexor.
Splitting the “don’t know” or “don’t care” states to possible 0s and 1s, the truth
table could then be extended, as follows:
27
Extended table of states.
Karnaugh map and minimized logical functions describing the operation of a multiplexor.
Please, notice that a “table of states” differs from a “truth table” – outputs specified in a “table of states” is
derived from the operation of a device and sometimes relations resulting from Boolean algebra cannot be
observed directly, as it is in the case of “truth tables”.
28
3.4 N-bit to m-bit parallel decoder
A n-bit to m-bit decoder is a device using a binary value or address to select
between number of outputs. It converts an n-bit string into m-bit one, where
m > n.
Let us consider a decoder that converts two-bit combinations to 4-bit
combinations of logic values.
An n-bit to m-bit parallel decoder.
Table of states of an n-bit to m-bit parallel decoder.
N-bit to m-bit decoder – the principle of operation
At the input we have a vector containing two binary values. We have four possible
combinations: 00, 01, 10, and 11. Every combination must be assigned a unique
combination of four binary values. Four values can be produced at the output of
four OR gates. They sum all the combination of two variables select[1], select[0]
and their negations.
Select [0] means the logical value of the 0th element of a vector; select [1] means
the logical value of the 1st element of a vector. Depending on logical values of
select[1], select[0], only one of the OR gates is forced to zero, remaining three are
set to 1. For example, if select[1] and select[0] are set to 0, the last gate is forced
to 1, etc.
We decoded two bits into four bits: 00 to 1110; 01 to 1101 etc. Another advantage
achieved, is that each four-bit vector contains only one zero (the fact that it is on
diagonal is not essential). Then, the position of this zero value in a string could for
example be used for activation of one of four devices. The multiplexer could then
29
operate as a simple driver/controller: if a sequence “00” comes from the keyboard,
then activate device No.4, because there is a command from the fourth gate, if
there is a “01” sequence, activate the device No.3 etc. When a particular output is
selected, it is asserted to 0, if it is not selected, it returns to 1. Then, the device has
an active-low outputs.
An active-low signal is one, of which an active state is considered to be logic 0. (Similarly, an active-high
signal is assigned to 1). The active-low nature is indicated by bubbles “Ο”at the output in the block scheme or
by the tilde “~”, prefixing the output variable or output symbol~ y [3:0].
30
4 More advanced logical circuits
4.1 Latches
A latch is a circuit that has two stable states and can be used to set, store or clear
state information.
The circuit can be made to change state by signals applied to one or more control
inputs and will have one or two outputs. It is the basic storage element in logic
systems.
Consider an RS latch (reset, set), implemented with NOR gates.
Basic description of a block scheme
Both reset and set inputs are active-high, (there are no bobbles associated with
these inputs on the symbol). The names of inputs reflect their effect on q (output);
when “reset” is active q is reset to 0, and when “set” is active q is set to 1. The q
and ~q outputs are known as the true output and the complementary output,
respectively. In the latch’s normal mode of operation, the value on ~q is the
inverse or complement of the q value. This is also indicated by the bobble
associated with the ~q output on the symbol. The truth table column labels qn+1)
and ~qn+1 indicate that these columns refer to the future values on the outputs.
The n+ subscripts represent some future time. The RS latch has the ability to
remember previous input value basing on feedback.
Block scheme of an RS latch and its implementation by using NOR gates.
Table of states describing operation of an RS latch.
31
4.2 RS latch – principle of operation
RS latch – the principle of operation
Assume that both the RESET and SET inputs are initially in their inactive states,
and that some previous input sequence placed the latch in its set condition; that is,
q is 1 and ~q is 0. Consider, what occurs when the reset input is placed in its
active state and then returns to its inactive state. Thus, when reset is placed in its
active state (logic 1), the q output from the first gate is forced to 0. This 0 on q is
fed back into the second gate and, as both inputs to this gate are now 0, the ~q
output is forced to 1. The 1 on ~q is now fed back into the first gate.
When the reset input returns to its inactive (logic 0) state, the 1 from the ~q output
continues feeding back into the first gate, which means that the q output continues
to be forced to 0. Similarly, the 0 on q continues feeding back into the second
gate, and as both of this gate's inputs are now at 0, the ~q output continues to be
forced to 1. The latch has now been placed in its reset condition, and a loop has
been established. Even though both the reset and set inputs are now inactive, the q
output remains at 0, indicating that reset was the last input in its active state.
For better comprehension of how particular states are forced, we remind that if any input to a NOR is 1, its
output is forced to 0, if both inputs to a NOR are 0 that the output will be 1.
32
Selected aspects of operation of an RS latch – reset function.
In the same way, one could explain the operation of SET. A more complicated
situation comes into existence if both: SET and RESET going to active. There will
be greater number of automatic sequences that lead to q and ~q being set to 00 in
the first step, and 11, 00, … in the following sequences. Now consider that both
SET and RESET go active. Details:
When both RESET and SET are active at the same time, the 1 on RESET forces
the q output to 0 and the 1 on SET forces the ~q output to 0. The 0 on q is fed
back to the second gate, and the 0 on ~q is fed back to the first gate. Now consider
what occurs when reset and set go inactive simultaneously. When the new 0
values on RESET and SET are combined with the 0 values fed back from q and
~q, each gate initially sees both of its inputs at 0 and therefore both gates attempt
to drive their outputs to 1. After any delays associated with the gates have been
satisfied, both of the outputs will indeed go to 1. When the output of the first gate
goes to 1, this value is fed back to the input of the second gate. While this is
happening, the output of the second gate goes to 1, and this value is fed back to
33
the input of the first gate. Each gate now has its fed-back input at 1, and both gates
therefore attempt to drive their outputs to 0. As we see, the circuit has entered
a meta-stable condition, in which the outputs oscillate between 0 and 1 value.
34
4.3 RS latch – NAND implementation
An equivalent operation can be achieved by implementing NAND gates. Try to
derive an equivalent table of operation.
RS- latch NAND implementation.
Flip-flops and latches are a fundamental building block of digital electronics
systems used in computers, communications, and many other types of systems.
The word latch is mainly used for storage elements, while clocked devices are
described as flip-flops. Flip-flops can be either simple (transparent or opaque) or
clocked (synchronous or edge-triggered).
Synchronic and sequential logic is the topic of a separate teaching module.
35
4.4 D-type latch
D (data) latch is practically an RS latch with so-called ENABLE circuit.
Block scheme of a D latch.
Table of states for a D latch.
The combination of two ANDs and NOT produces three possible combination of
binary values: 00, 01, 10 (00,01,10,11 is converted to 00,01). The combination 11
at the output of two AND gates (being at the input of the RS part) doesn’t occur
and the meta-stable state is avoided. However, this is not the most important
feature.
When enable is placed in its active (logic 1), and if the data input changes while
enable being 1, the outputs will respond to reflect the new value. When enable
returns to its inactive state (0), both AND gates result with two zeros, no matter
the value of data. In other words, any change of data doesn’t have effect on
outputs (Data values are now “don’t care” values). The outputs remember their
values until the next activation of enable. The circuit is said to be level-sensitive.
It can be illustrated by waveforms for a D-type latch with active high-enable.
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5 Combinational logic in circuits controlling
practical devices
5.1 Task – combinational logic
We consider a heater with a temperature, minimum water level sensor, and
a flame indicator. It is switched automatically on if the temperature is below 15°C
or it can be switched on by manual switch. In both modes (automatic, manual), the
flame must be lighted (to open a gas pipe) and there must be minimum water lever
in the heater.
Schematic illustration of a heater.
Four variables are introduced:
A = 0, temp > 15°C OR 1, temp < 15°C
B = 0, water below min . OR 1, water above min .
C = 0, flame is OFF OR 1, flame is ON
D = 0, manual switch OFF OR 1, manual switch is ON
The output is:
y = 0, not heating OR 1, heating
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Table of states of a heater.
Karnaugh map describing the operation of a heater.
Practical implementation – designed circuit, which controls the considered heater.
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5.2 Case study – combinational logic in a factory
Task: assume there are four blocks (for example four pumps or four lifts) in
a factory. Only two of them can work concurrently because of the stability of the
whole system. An operator has at his desk two controls indicating the current state
of the system: a yellow-diode signaler indicating that two of four blocks are ON
and a red-diode signaler alarming, if more than two blocks are running. Design
a logical circuit, which provides the following function.
Schematic illustration of a combinational logic system in a factory.
Four variables describing operation of four blocks
x1,2,3,4 =  0, not working OR 1, working
A signaler indicating (by yellow light) that two blocks are running
y 2 =  0, nosignalization OR 1, yellow light
A signaler indicating by red light that three or four blocks are running
y3,4 = 0, nosignalization OR 1, red light
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Table of states of the considered system.
Karnaugh maps describing the operation of the considered system.
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Final circuit controlling the system.
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6 Final test
Please, verify your knowledge by solving the following final test.
1. Logical conjunction
a) is an operation on two logical values that produces a value of true if and only
both its operands are true
b) can be created by logical OR
c) is known as logical sum
Solution: a
2. The precedence of operators
a) AND has higher precedence than OR
b) OR has higher precedence than AND
c) in Boolean algebra there is no precedence of operators
Solution: a
3. 4-position BCD
a) is known as 8421 code
b) are 8-bit binary strings
c) assumes that neighbor code words must differ in one bit
d) means Boolean Code Decimal
Solution: a
4. Minterm
a) is a form of a logical expression using AND
b) is a form of a logical expression using OR
c) is a logical gate
d) is a logical disjunction
Solution: a
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5. Truth table
a) is a canonic form of a logical function
b) is a table, in which logical functions are minimized
c) specify true or false for given operands
d) are used to describe sequential states of a device
Solution: c
6. Karnaugh map
a) is used to minimize logical functions
b) is named after Thomas Carnaugh
c) cannot contain don’t know states
d) cannot cover more than 3 variables
Solution: a
7. Diagonal cells in Karnaugh maps
a) cannot form groups to be minimized
b) can be minimized because they are neighbor cell in terms of logics
c) are always empty
d) are used for output values
Solution: b
8. NOT gate
a) can be implemented by using NAND with its inputs being connected with
each other
b) is used to form a conjunction
c) does not insert time delay
d) can operate as a latch
Solution: a
9. OR gate
a) expresses logical conjunction
b) produces true if and only at least one operand is 1
c) operates as NOT and XOR in series
Solution: b
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10. XNOR gate
a) operates as NOR is series with XOR
b) produces true if and only at least one operand is 1
c) is equivalent to NXOR
Solution: No answer
11. 2:1 multiplexor
a) have serial data at the input and parallel data at the output
b) cannot be implemented by using AND and OR gates concurrently
c) can use a binary value to select between numbers of inputs
Solution: c
12. Latch
a) can store or clear state information
b) is a primitive gate
c) produces 1 at its output if and only both operands are 0
d) cannot be cleared or reset
Solution: a
13. Boolean algebra
a) has as its aim to use mathematical operations to represent logical arguments
b) has as its aim to rigorously test logical arguments
c) operates on logical arguments that can be assigned 0 or 1
d) is suitable to describe the operation of digital devices
Solution: a, b, c, d
14. Gray code
a) assumes that successive code words differ in one bit
b) is used to label columns in Karnaugh maps
c) can be used to faciliate error correction
d) is a 4-position BCD
Solution: a, b, c
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15. AND gate
a) can have more than two operands
b) is used to create logical multiplication
c) should have only two inputs
d) produces true if and only every operand is 1
Solution: a, b, d
16. NAND gate
a) produces the same outputs as AND in series with NOT
b) produces the same outputs as two NOT gates in series
c) is a multiplexor operating on more than two arguments
d) produces false if and only every argument is 1s
Solution: a
17. RS latch
a) assumes the presence of a clock
b) contains SET and RESET inputs
c) can be implemented by using NOR gates
d) can be implemented by using NAND gates
Solution: b, c, d
18. Active-low nature of signals
a) is indicated by a bobble in block schemes
b) assumes that an active state is considered to be 0
c) is indicated by the tilde ~ prefixing the output variable
Solution: a, b, c
19. D-latch
a) can be considered as RS latch with extra elements forbidding the occurrence
of unstable states
b) contains so-called „enabling“ circuit, which converts input values to 00, 01, 10
c) keeps the values until the next activation of „enable“ part
d) requires a clock added to RS latch
Solution: a, b, c
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20. Steps of design of a logical circuit contain:
a) specification of all the input variables
b) specification of a truth table
c) specification of a Karnaugh map
d) deriving the minimized function and the coresponding circuit
Solution: a, b, c, d
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