Confidential

Transcription

Confidential

2007
“Design Activities at LETI : New
developments for Power Efficient
SoC”
Edith BEIGNE
© CEA 2009. All rights reserved
Edith Beigné- June 22th, 2009
Confidential
Any reproduction in whole or in part on any medium or use of the information contained herein
is prohibited without the prior written consent of CEA
1
Power Trends
2007
Confidential
2
Transistor Integration & Power dissipation
2007
Confidential
3
Power sources
2007
Confidential
4
Power components in digital CMOS
Power due to switching capacitance Pdyn
Power due to short circuit currents PSC
Power due to leakage currents Pleakage
2007
P = α fCV
2
DD
+ I SCVDD + I leakageVDD
Confidential
5
CMOS Power – With Subthreshold, Gate and Bulk leakage
Dynamic Power
+ Active Leakage
Leakage Power
IBULK
PMOS
PMOS
Network
1
NMOS
2007
0
IDYN
Network
1
Network
IGATE
NMOS
0
ISC
IGATE
Network
ISUB
IBULK
Confidential
6
Power Aware Strategies
2007
Confidential
7
Power aware strategies
2007
Confidential
8
Reducing Power :
Real Application to a complex
power aware SoC
2007
Confidential
9
Reducing Power :
power aware SoC
2007
Chosen strategies
Confidential
10
Multiple Threshold Voltages - Hardware Means
Availability of Multi-VTH transistors in
actual technologies
Complete set of cells provided and
characterized
Logic levels remain unchanged
Higher threshold voltage for leakage
optimization
2007
Low threshold voltage to the most performance
critical blocks
Possible within cells
Confidential
11
Power Gating - Hardware Means
Per gate
only modified cell library needed
fine grained controllable
high area overhead
Per row
2007
only additional gating cell needed
delay penalty hard to predict
Per block
no changes in module design needed
temporal solution for IP reuse
Confidential
12
Power Gating – Gate Boosting and Super Cut-Off
Simplest : CCMOS
single transistor, Vcut = VDD
standby power determined by leakage floating
through the gating transistor
But :
High on-resistance in active mode
Not so small leakage in stand-by mode
Gate Boosting
In active mode, Vcut is increased (NMOS) or
decreased (PMOS)
2007
Super Cut-Off CMOS
In stand-by mode, Vcut can be increased above
VDD (PMOS) or deacreased below VSS (NMOS)
But :
longer wakeup times
Vcut limited due to possible oxide breakdown
Mainly for subthreshold current
Confidential
13
Dynamic Voltage Scaling (DVS) - Architectural Means
Supply Voltage and the effect on
Circuit
delay ≈
Dynamic
2007
asymptotical
Delay
Heavy increase
in delay
Heavy increase
in power
VDD
(V DD − VTH )α
quadratic
Power
2
P = α fCVDD
Leakage
I subth
Power
W −β
= αT ² e
L
exponential
VTH
T
VTH = VTH 0 − f DIBL ( L ) ⋅VDD
Confidential
14
Discrete DVFS - principle
Use only some discrete available voltage values
2 or 3 values are necessary
each one with its associated frequency
Easy integration (low area)
Hop between those discrete values
VDD Hopping and Voltage dithering (c)
2007
Confidential
15
Reducing Power :
power aware SoC
2007
ALPIN chip
Confidential
16
Global architecture : ALPIN circuit
An Asynchronous Low Power Innovative NoC implementing new design
techniques to reduce dynamic and static power consumption on a 65
65 nm
technology
cu t_off
IP U nit
Vco re
I N
E
ast
IN
We s t
OUT
E
ast
L S
L S
OUT
We s t
I N
a
Es t
IN
OUT
We s t
a
Es t
L S
L S
L S
L S
IP Uni t
Vhig h
Vnod
e
res et_ n
L S
L
L
se
l e
p
S
L
Vc ore
Node
Ac ti v it y
de
t e c tio n
IN No rt h OUT No rt h
OUT Re s
Local Clock
Generator
SL
SL
SL
SL
L
L
L
L
OU T
a
Es t
OU T S o u h
t
N
I Souh
t
L S
L S
L S
L S
OUT
We ts
IN
Es
at
n
V ode
se
l p
No d e
N
I
N ro h
t
O U T N o rt h
A c it v y
ti
e
dt ec
t o
i n
L
S
L
S
L
S
L
S
L
S
IN
We ts
OUT
Es
at
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
OUT S u
o t h IN o
Su h
t
L S
OU T
We s t
I N
a
Es t
N
I
OU T
We s t
a
Es t
OU T S o u h
t
L S
L S
L S
L S
N
I
We s t
L
S
L
S
L
S
L
S
L S
L S
L S
L S
L
S
L
S
L
S
L
S
L S
L S
L S
L S
L S
L S
L S
L S
I N
a
Es t
OU T R e
s
I NRe
s
Vhigh
Vhigh
OU T
We s t
Vh
i gh
S
S
S
S
IN e
Rs
I NRe
s
L
S
L
S
L
S
L
S
L S
S
SA
L S
L S
L S
L S
SL
SL
S
S L
L
S
S
S L
SL
LPM
SL S
L
S
SA
L S
L S
L S
L S
L oc al Clock
Generator
e
dt ec
t o
i n
ck
lo
S
L SL
Vc ore
A c it v y
ti
V core
MEM
SL
O U T N o rt h
Tl ow
S
L L S
SL
N ro h
t
Th g
i h (xN)
C
L S
L S
L S
L S
S
L
L S
L S
L S
L S
L S
L S
L S
L S
L S
re set_ n
se
l p
SL S
L
n
V ode
No d e
N
I
OU T R e
s
ck
SL S
L S
Vh
i gh
L
L S
L S
L S
L S
Vhigh
L S
L S
L S
L S
-
SL
SL
SL
SL
SL
SL
S L
L
Pow er
Switches
cu t_o ff
S
L L S
SL S
L
S
SA
S
L S
L S
L S
L S
Hopping
Unit
Clo
S
OUT
E
ast
L S
L S
L S
L S
UCO
cu t_o ff_cl k
L PM
S
L SL
Local Clock
Generator
IN
We s t
V low
V high
Vhigh
L S
L S
L S
L S
L S
L S
L S
L S
Vhigh
Vhig h
r eset_ n signals
SL
Vc ore
se
l p
Node
Ac it v y
ti
e
d t e tc o
in
I N
E
ast
S
L
S
L
S
L
S
L
OUT S o u h
t IN S o u h
t
80c51
cut_ off sig nals
dcdc_ctr l signal s
L S
L S
L S
L S
S
L
L S
L S
L S
L S
L S
L S
L S
OUT
We s t
OUT S o u th IN S o u th
LPM
rese t_n
L S
L S
L S
L S
S
L L S
SL
S
L L S
SL
S
L
S
L
S
L
S
L
L S
L S
S
L
S
L
S
L
S
L
L S
OUT
We s t
NoC
perf
ck
Vh
i gh
n
Vode
IN No
rh
t OUT No tr h
OUT Re
s
I N Re
s
L S
L S
L S
L S
L S
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
L S
L S
L S
L S
OUT S o u h
t IN S o u h
t
lo
C
S L
S L
S
S L
L
S
S L
L
SL
S L
Vhigh
Vhigh
Vh igh
S
SA
L ocal Clock
Generator
e
d t e tc io n
I N Re
s
I N Re
s
S
L
S
L
S
L
S
L
s le p
No d e
Ac ti v ity
OUT Re
s
L S
L S
L S
L S
rese t_n
L S
L S
L S
L S
L S
L S
L S
L S
L S
Vh
i gh
n
Vode
IN No
r th OUT No tr h
SL S
L
L
ck
SL
S
S L
S L
S L
SL
SL
SL
SL
lo
S
L SL
C
S
SA
L PM
Vcor e
FHT2
L S
L S
L S
L S
S
L SL
S
L SL
L S
SL
k
c
SL S
L
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L S
SL S
L
se
l p
Node
Ac it v y
ti
e
d t e tc o
in
IN No
rh
t OUT No tr h
OUT Re
s
lo
SL
rese t_n
S
L
n
Vode
L PM
S
L SL
N
I
C
Vh
i gh
L
DC-DC
Conv.
T arge t val ue
Local Clock
Generator
Vco re
S L
S L
SL
SL
SL
SL
S L
S
Co nt ro lled
S wit ch
Po wer
f ilte r
Cor rect or
Vcor e
S
SA
L S
L S
L S
L S
Automatic frequency scaling
Use of clock generation re-programming to find the optimal
V/F point of operation
ck
Local Clock
Vcore G enerator
A local fine grain Dynamic Frequency Scaling :
2007
Implementation of a local hardware controller to control
transitions between Vhigh and Vlow
Ensures smooth DVS transitions for IP safe computation
SD
mod ulator
dcdc _c ontrol
FHT1
NI
S
L
o
S
L L S
SL
Cl
rese t_n
Pow er
Switches
NI
LPM
I P U ni t
V core
OFDM
A local fine grain Dynamic Voltage Scaling :
To
l w
Hopp ing
Unit
Hopp ing
Unit
T hi gh (x N)
-
V high
Vlow
UCO
cu t_o ff_ cl k
Power
Switches
L S
L S
L S
L S
L S
L S
L S
N
I Souh
t
L S
L S
L S
L S
To
l w
N
I
T hi gh (x N)
N
I
cut_ off
-
Vh igh
Vlo w
Vhigh
UCO
cu t_o f _ cl k
NI
Each synchronous IP is an independant power
and frequency domain
ALPIN Architecture
Thanks to pausable clock technique, IP unit
continues its operation during DVFS phases
Local fine grain power management can be executed
during IP computation and communication independently
from the others
Confidential
17
Vhi gh
UCO
Th g
i h( N
x)
tv
i
y
c
ti
n
o
e
p
o
N e
d
A c
t iv
t y
d e
t c
ti n
o
N o
rt h U
O T
N o
r th
NI
S
SL
SL
I
R
N e
s
R
N e
s
N
I
W
e s
t
E a
s
N
I t
L
O U
T
E a
s
t
S
S
L
S
L
U
e
O T
W
s
t
L
S
E IN
a
s t
L
L
S
L
S
L
S
L
S
L
S
IN
e
W s
t
O T
U
E a
s t
S
L
S
S
L
S
S
N
T
or
N
I
oS
hut
ht
de
ct
tvi
y
et
ict
on
N
o e
d
I
O
U T
N rto
h
O
U N
T ro
O U
T o
S
tu
h
N
I o
S
th
A c
t
tv
i
y
d
c
ti
n
o
e
t
S
L
S
S
L
S
L
O
U T
t
L
S
L
W
e s
t
S
S
L
N
I
L
S
S
L
W
e s
t
t
L
S
N
I
E
No
C
S
S
S
SL
Vnode
IN No rth O UT North
IN
East
IN
West
OUT
East
LS
LS
LS
LS
LS
LS
LS
LS
LS
LS
LS
LS
O UT South IN So uth
LS
Level shifters + isolation cells
O UT
West
LS
LS
LS
Asynchronous Node
Confidential
S
L
S
L
S
L
S
S
L
S
L
S
L
Vhi gh
sl eep
Node
Activity
detection
OUT Res
LS
Network Link
S
I
Vhigh
LS
LS
S
L
esl
L
N
ort
h
O
U
N
T
or
O
TU
oS
hut
N
I
oS
hut
ht
E
18
S
L
S
L
S
L
S
L
Network Link
L
Vhigh
LS
LS
LS
I
esR
ep
oN
de
A
ct
tvi
y
d
et
ict
on
L
IN Res
LS
T
es
N
Ias
O
TU
E
as
S
t
L
L
S
t
L
S
L
eW st
L
L
S
S L
S L
S L
L
LS
LS
LS
V o
n e
d
LS
O
U
R
N
eW
O
U sTt
N
I
LS
us
S
V ig
h h
S
LS
LS
LS
LS
ol
oc
ot
LS
LS
LS
ch
yn
As
no
ro
pr
S
L
SL
L
L
LS
S
S
S
S
S
S
L
S
L
S
L
Vcore
Vcore
S
SA
LS
ri
ai
C
LS
LS
LS
Local Clock
Generator
No
LS
dl_cfg
us
S
SL
SL
SL
SL
S
Vhi gh
S
L
L
Vhigh
S
L
S
L
S
L
L
t
S
L
S
L
In
Da p u t
ta
Hopping Unit
LS
pwc_hl
Ou
Da tpu
ta t
h
nc
Sy
no
ro
ol
oc
ot
pr
LS
k
oc
Cl
LS
IP Core
Synchronous
Vcore
LS
IP Unit
Vcore
LS
Local
Power
Manager
Vref
Synchronous
Vcore
LS
L
L
a
s
S
LS
D2
?A
Network
Interface
reset_n
L
t
O U
T
E
tu
h
+
LS
2007 INIT : reset at Vhigh (1.2V)
HIGH : Vhigh supply
LOW : Vlow supply (0.8V)
HOPPING : switch Vhigh / Vlow for DVFS
IDLE : retention state at Vlow (no clock)
OFF : stand-by mode
a
s
S
S
L
TU
as
S
L
asN
I
O
E
S
L
eW st
R
N e
s
I
L
E
L
N
I
Tlow
pwc_cfgL
Hop
Clk
S
AS
Power
Switches
Thigh (xN)
L
N
S
LS
R
e
s
ck
Local Clo ck
G enera tor
Vc ore
S
e
p
es
eW
O
U sTt
LS
LS
Vlow
cut_off
L
I P Un it
re s e t_ n
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
e
s
l
LS
LS
V o
n e
d
LS
Vhigh
ULTRA Vuco
CUT-OFF
IP units have 5 supply modes
S
S
LP M
Vco re
I
V ig
h h
I
R
N
Vhigh
CONTROL
HOPPING
CONTROL
S
S
L
L
MEM
N
L
SL
L
LS
oN
A
d
L
S
L
O
U
hut
SL
SL
SL
SL
S
S
L
h
oS
P ower
Swit ch es
LS
ort
TU
Local C lock
Gener ator
Vc or e
LS
N
O
esR
Tlo w
LS
T
S
L
L
S
S
S
S
S
S
S
L
L
L
L
L
L
L
I
L
O
U
LS
S
re s e
t _n
ep
LS
S
esl
LS
S
S
V ig
h h
V o
n e
d
L
L
L
SL
SL
LS
SL
SL
S
SL
SL
Clo
AS
S
AS
L
: DC-DC converter
S
S
L
L
Hopp ing
Unit
NI
S
Th
i g h (x N)
-
LPM
ck
Cl o
Local Clock
G enerat or
Vco r e
L
S
L
S
L
u
c t _ fo f
reset_n si gnal s
ck
L
dcd c_ctrl si gna ls
UC O
u
c t _of _
cl k
80c51
cut_of f sign als
I
Optionnal
L
L
O T
U
E a
s t
Vl ow
V hi gh
S
NoC
perf
S
L
S
L
V hi gh
LS
SOFTSOFT
SWITCH
SWITCH
e
p
IN
E a
s t
IN
e
W s
t
S
L
Vhi gh
S
L
S
L
S
L
S
L
S
L
Vhi gh
Vhi gh
LS
Pausable Clock,
Power Supply Unit
e
s
l
o
N e
d
A c
t iv
t y
d e
t c
ti n
o
N o
rt h U
O T
N o
r th
U
O T
e
W s
t
L
S
L
S
S
L
L
O T
U o
S u
th IN o
S u
th
LS
Network Interface,
Test Wrapper,
S
L
S
L
S
S
L
L
O T
U o
S u
th IN o
S u
th
re s e t_ n
UCO
V o
n e
d
I
U
O T e
R
s
L
S
S
S
L
L
R
N e
s
Vhi gh
Vhigh
L
O
W
U
e s
T
t
S
L
S
L
LPM
cut_off_clk
S
L
L
L
SL
I
I
S
L
S
L
S
L
C lo
Each IP core encapsulated with
L
L
V ig
h h
S
S
S
L
S
S
S
S
S
S
S
e
s
l
L
L
L
L
L
V o
n e
d
L
L
I
U
O T e
R
s
S
L
NI
S
SL
SL
LS
e
t
AS
S
A c
t
d
S
Local Clock
G enerat or
Vco r e
LS
th
LS
LS
N rto
re s e t_ n
V ig
h h
LS
LS
O
U N
T ro
N
I o
S tu
h
L
h
O U
T o
S tu
h
R
e
s
SL
SL
S
SL
LS
e
p
N
o e
d
I
O
U T
k
S
S
re s e
t _n
S
S
S
S
S
S
e
s
l
L
L
L
L
L
S
S
V o
n e
d
L
S
SL
SL
L
LPM
FHT2
Cloc
SA
Local Clock
Generat or
Vc or e
LS
SL
S
L
V ig
h h
LS
L
L
SL
SL
S
Power Adaptive NoC Unit Design
k
S
SL
V core
LS
FHT1
oc
Cl
SA
S
ck
o
Cl
Local Clock
Gener ator
Vco r e
DC-DC
Co nv.
Ta
r get a
v lu e
LP M
V core
N
I
OFDM
C on rt o l ed
S wit ch
P ower
fi lt er
Correct or
I P Un it
IP Unit
LPM
SD
modu lat or
dcdc_c
on tr ol
Tlo w
LS
-
Hoppin g
Un it
Vcore
re s e t_ n
P ower
Swit ches
c u t_ o f
S
u
ct _
of _
f c lk
Tlo w
L
Th g
i h( N
x)
Hoppin g
Un it
L
-
Vl ow
Vh igh
Power
Switches
c u t_ o f f
LS
Vlo w
V hi gh
UCO
u
c t _ fo _
f c lk
S
S
S
UL T RA Vuco
ULTRA
CUTCUT - OFF
OF F
Power
S witches
Hopping Unit
c ut_off
Thigh
T
hig h (xN )
SOF
S
OFTTSWI TC
H
SWIT
CH
Tlow
T low
pwc_ cfg
LS
Hop
Clk
+
Synchronous
Vcore
Vcore
A
SL
L
l
co
o to
pr
S
L
SL
L
V h ig h
LS
LS
L
V n od e
LS
S
S
LS
C
S
L
L
LS
No
S
S
LS
s
ou
sl eep
No de
Acti vi ty
N
I No rth O U T No rt h
S
LS
L
Vc ore
S
n
ro
ch
sy n
LS
ri
ai
LS
Local Clock
Generator
LS
LS
SA
dl_cfg
re set_n
l
co
S
oto
pr
L
C
No
S
L
s
ou
on
hr
nc
Sy
LS
In
D a pu t
ta
O
u
D tpu
at t
a
k
oc
Cl
Network
Interface
Network Link
Vcore
IP Core
pwc_ hl
Loc al
Power
Manager
V r ef
Synchronous
V core
S
D2
?A
L
HO PPING
CO
NT RO L
CO NT RO L
LS
IP Unit
Power Supply Selector
Vh igh
Vlow
Vhigh
UCO
cut_o ff_clk
S
L
LS
d ete cti on
O U T Re s
I N R es
Vhigh
LS
LS
LS
LS
LS
O UT
West
IN
E ast
LS
UCO
ULTRA
LS
LS
LS
Vlow
CUT-OFF
2007
Power Supply Unit
HOPPING UNIT
Cut-Off
Thigh (xN)
SWITCH
POWER
SWITCHES
Hop
Clk
Tlow
+
CONTROL
D•A
Vref
Vcore
from LPM
Unit
Local Power Supply Unit offers a safe control of internal power supply
depending on pre-defined power modes
Confidential
LS
LS
Asynchronous Node
Vuco
SOFT-
LS
LS
LS
L evel shifte rs + iso lation cells
O UT
E ast
O U T So ut h I N S out h
LS
LS
Power Supply Unit manages Vcore
Two power switches Thigh and Tlow LVT transistors
A Hopping Unit
UCO clock
Vhigh
An Ultra Cut-Off Generator
LS
LS
LS
LS
IN
West
LS
LS
LS
LS
LS
Networ k Link
19
Vdd hopping vs DFS vs DVFS
Consommation totale (mW)
20
Vcore = 1,2 V
HIGH
18
DFS
16
Vcore à 1,2 V
Fclk variable
14
Vhigh = 1,2 V
1,1 V
12
DVS « parfait »
Vcore variable
Fclk ajustée en
conséquence
10
8
1,0 V
2007
LOW
6
Vlow = 0,9 V
4
2
HOPPING
0,9 V
sauts entre les modes
HIGH et LOW commandé
par un modulateur PWM
Vcore = 0,8 V
0
0
50
100
150
200
Fréquence du coeur (MHz)
Confidential
250
300
350
20
UCO vs MTCMOS
The proposed UCO generator automatically polarizes the gate of the
LVT Power switch to its point of minimum leakage
1,00E-07
25°C
45°C
1,00E-08
65°C
85°C
Current (A)
105°C
1,00E-09
125°C
1,00E-10
T
1,00E-11
1,00E-12
1, 20
1,30
1,40
1, 50
1,60
1, 70
1,80
Gate vol tag e (V)
Compensates for temperature variation, alleviates corners variations.
Mode
HIGH
RESET
2007
OFF
VCORE
1,166 V
1,195 V
1,6 mV
I(VCORE)
30,4 mA
691 µA
0,93 µA
Mode
HIGH
RESET
OFF
VCORE
1,194 V
1,192 V
10,5 mV
I(VCORE)
13,9 mA
883 µA
7,8 µA
Ioff gain Ioff (pA/µm)
169
743
TRX-OFDM Unit
using UCO
Ioff gain Ioff (pA/µm)
3000
113
MEM Unit using
MTCMOS
Confidential
21
Physical Implementation
3440
STM 65nm technology
9 power domains at the top level
6 frequency domains
Each block has its own frequency
generator and power suppply
Low block complexity
DC-DC
FHT1
FHT2
TRXOFDM
1200 µm
RAM1
RAM5
UCO Unit
Level Shifters
RAM3
NoC Interface
Power Rings
(VHIGH, VLOW, VSS, VCORE)
MEM
NoC Perf
RAM7
RAM9
Hopping Unit
RAM6
RAM12 RAM13
RAM2
TRX-OFDM
Unit
(250Kgates)
80c51
1600 µm
Power
Switches
RAM4
RAM8
650x50 µm
RAM0
RAM10 RAM11
Power Supply
2007 Unit
3480
Confidential
22
Power / Variability Commonalities
Towards the end of Worst-Case design
Worst case design in average too pessimistic (over-constrained
design) but optimistic in some cases
Need for statistical Design & Tools and variability monitoring
Towards self-adaptive systems
2007
AVFS (Adaptive Voltage & Frequency Scaling)
Knobs & Sensors
Adaptive & robust communication means
Global system optimization
Towards a power efficient and reliable system reaching
an optimal Performance/Yield trade-off
Confidential
23
Conclusion
Adaptive dynamic power reduction is possible through
voltage scaling :
VDD hopping or real DVS
Management of multi power domains in a complex SoC
GALS systems can lead to automatic frequency scaling
Synchronization interfaces
Asynchronous implementation
Leakage problems due to technology scaling are
handled through
2007
Insertion of power switches with UCO
An optimum Power/Performance/Yield has to be
reached today considering Variability issues
Confidential
24
Main References
E. Beigné, F. Clermidy, J. Durupt, H. Lhermet, S. Miermont, Y.
Thonnart, T. Tran Xuan, A. Valentian, D. Varreau, P. Vivet, C.
Chancel, X. Popon, H. Lebreton, “An Asynchronous Power Aware
and Adaptive NoC based Circuit”, IEEE Journal Of Solid State
Circuits April 2099 Vol 44.
E. Beigne, F. Clermidy, J. Durupt, H. Lhermet, S. Miermont, Y.
Thonnart, T. Tran-Xuan, A. Valentian, D. Varreau, P. Vivet. “An
Asynchronous Power Aware and Adaptive NoC based Circuit”,
Symposium on VLSI circuits, Honolulu, June 2008.
2007
E. Beigné, S. Miermont, A. Valentian, P. Vivet, S. Barasinski, F.
Blisson, N. Kohli, S. Kumar, « A Fully Integrated Power Supply Unit
for Fine Grain DVFS and Leakage Control Validated on LowVoltage SRAMs”, ESSCIRC’2008, Edinburg, UK, Sept 2008.
E. Beigné, F. Clermidy, S. Miermont, P. Vivet, “Dynamic Voltage
and Frequency Scaling Architecture for Units Integration within a
GALS NoC”, Proceedings of the 2nd IEEE International Symposium
on Networks-on-Chip, NOCS’2008, New-Castle, UK, April 2008.
Confidential
25
Innovation
for industry
2007
Confidential
26

Confidential

Transcription

Similar documents

Energy Efficient Lighting in Buildings Lighting Concepts