Ati RS600

Transcription

Ati RS600

RS600
Databook
Technical Reference Manual
Rev. 1.0
P/N: CHS-215RS600-10
© 2006 ATI Technologies Inc
CONFIDENTIAL MATERIAL
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periodic audit by ATI. This manual is subject to possible recall by ATI.
The information contained in this manual has been carefully checked and is believed to be
entirely reliable. No responsibility is assumed for inaccuracies. ATI reserves the right to make
changes at any time to improve design and supply the best product possible.
Please note that in this databook, references to "DVI" and "HDMI" may refer to: (1) the
function of the integrated DVI/HDMI interface described in details in section 2.3.1 and 3.8, as
well as in other sections; or (2) the capability of the TMDS interface, multiplexed on the PCIE external graphics interface, to enable HDMI through passive enabling circuitries. Any
statement in this databook on any DVI or HDMI-related functionality must be understood to
apply to (1), (2), or both, according to the immediate context of the reference.
ATI Technologies Inc. will not provide any indemnity, pay any royalty, nor provide any
license/sublicense to any:
(a) Intellectual property rights relating to any of the following: (i) Macrovision for its Analog
Protection System ("APS") technologies; (ii) Advanced Television Systems Committee
(ATSC) standard and related technologies; or (iii) the High Definition Multimedia Interface
(HDMI) standard and related technologies; or
(b) Audio and/or video codecs or any industry standard technology (e.g., technology or
specifications promulgated by any standards development organization, consortium, trade
association, special interest group or like entity) .
ATI, MOBILITY, and Radeon are trademarks of ATI Technologies Inc. All other
trademarks and product names are properties of their respective owners.
Table of Contents
Chapter 1: Overview
1.1 Introducing the RS600 ........................................................................................................................................................1-1
1.2 The RS600L ........................................................................................................................................................................1-1
1.3 RS600 Features ...................................................................................................................................................................1-2
1.3.1
CPU Interface .......................................................................................................................................................1-2
1.3.2
Memory Interface .................................................................................................................................................1-2
1.3.3
PCI Express Interface ...........................................................................................................................................1-2
1.3.4
A-Link Express II Interface..................................................................................................................................1-2
1.3.5
2D Acceleration Features .....................................................................................................................................1-2
1.3.6
3D Acceleration Features .....................................................................................................................................1-3
1.3.7
Motion Video Acceleration Features....................................................................................................................1-4
1.3.8
Multiple Display Features ....................................................................................................................................1-4
1.3.9
DVI/HDMI ...........................................................................................................................................................1-5
1.3.10 External Display Support by SDVO 1.0...............................................................................................................1-6
1.3.11 Power Management Features ...............................................................................................................................1-6
1.3.12 PC Design Guide Compliance..............................................................................................................................1-6
1.3.13 Test Capability Features .......................................................................................................................................1-6
1.3.14 Additional Features ..............................................................................................................................................1-7
1.3.15 Packaging .............................................................................................................................................................1-7
1.4 Software Features................................................................................................................................................................1-7
1.5 Branding Diagrams .............................................................................................................................................................1-7
1.6 Part Number Legend ...........................................................................................................................................................1-9
1.7 Conventions and Notations .................................................................................................................................................1-9
1.7.1
Pin Names.............................................................................................................................................................1-9
1.7.2
Pin Types ............................................................................................................................................................1-10
1.7.3
Numeric Representation .....................................................................................................................................1-10
1.7.4
Register Field......................................................................................................................................................1-10
1.7.5
Hyperlinks ..........................................................................................................................................................1-10
1.7.6
Acronyms and Abbreviations .............................................................................................................................1-10
Chapter 2: Functional Descriptions
2.1 Host Interface ......................................................................................................................................................................2-2
2.2 System Memory Interface ...................................................................................................................................................2-3
2.2.1
Memory Requests.................................................................................................................................................2-6
2.2.2
Supported Memory Components..........................................................................................................................2-6
2.2.3
Supported Memory Configurations......................................................................................................................2-6
2.2.4
Memory Banks .....................................................................................................................................................2-7
2.2.5
Row and Column Addressing...............................................................................................................................2-7
2.2.6
CAS Latency ........................................................................................................................................................2-8
2.2.7
Burst Type ............................................................................................................................................................2-8
2.2.8
Burst Length .........................................................................................................................................................2-8
2.2.9
Clock Enable, Chip Select, and On-Die Termination Distributions for DDR2/DDR3 SDRAMs ....................2-10
2.3 DVI/HDMI........................................................................................................................................................................ 2-11
2.3.1
Data Mapping for the Integrated DVI/HDMI Interface ..................................................................................... 2-11
2.3.2
Data Mapping on the TMDS Interface Multiplexed on the PCI-E Graphics Lanes ..........................................2-14
2.3.3
Support for HDMI Packet Types........................................................................................................................2-16
2.4 SDVO Interface.................................................................................................................................................................2-17
2.4.1
Symbol Replication ............................................................................................................................................2-17
© 2006 ATI Technologies Inc.
Proprietary and Confidential
RS600 Databook
Table of Contents-1
Table of Contents
2.4.2
2.4.3
2.4.4
Dual-link Mode.................................................................................................................................................. 2-17
I2C/DDC Support .............................................................................................................................................. 2-17
HPD Support...................................................................................................................................................... 2-17
2.5 VGA DAC Characteristics ............................................................................................................................................... 2-18
2.6 External Clock Chip ......................................................................................................................................................... 2-18
Chapter 3: Pin Descriptions and Strap Options
3.1 Pin Assignment Top View ................................................................................................................................................ 3-2
3.2 RS600 Interface Block Diagram ........................................................................................................................................ 3-4
3.3 CPU Interface ..................................................................................................................................................................... 3-5
3.4 DDR2/DDR3 Memory Interface ........................................................................................................................................ 3-7
3.5 PCI Express Interfaces ....................................................................................................................................................... 3-8
3.5.1
1 x16 Lane Interface for External Graphics ........................................................................................................ 3-8
3.5.2
1 x4 Lane A-Link Express II to IXP.................................................................................................................... 3-8
3.5.3
4 x1 Lane Interface for General Purpose External Devices ............................................................................... 3-8
3.5.4
Miscellaneous PCI Express Signals..................................................................................................................... 3-9
3.6 Clock Interface ................................................................................................................................................................... 3-9
3.7 CRT and TV Interface........................................................................................................................................................ 3-9
3.8 Integrated DVI/HDMI Interface....................................................................................................................................... 3-10
3.9 TMDS Interface Multiplexed on the PCI-E Graphics Lanes ............................................................................................3-11
3.10 SDVO Interface for External Displays............................................................................................................................3-11
3.11 Power Management Pins............................................................................................................................................... 3-12
3.12 Miscellaneous Pins......................................................................................................................................................... 3-12
3.13 Power Pins...................................................................................................................................................................... 3-13
3.14 Ground Pins.................................................................................................................................................................... 3-15
3.15 Strapping Options........................................................................................................................................................... 3-16
Chapter 4: Timing Specifications
4.1 Processor Front Side Bus Timing....................................................................................................................................... 4-1
4.2 Memory Timing ................................................................................................................................................................. 4-6
4.3 OSCIN Timing ................................................................................................................................................................... 4-6
4.4 Power Rail Power Up Sequence......................................................................................................................................... 4-7
Chapter 5: Electrical Characteristics and Physical Data
5.1 Electrical Characteristics.................................................................................................................................................... 5-1
5.1.1
Maximum and Minimum Ratings........................................................................................................................ 5-1
5.1.2
DC Characteristics ............................................................................................................................................... 5-1
5.2 RS600 Thermal Characteristics.......................................................................................................................................... 5-5
5.2.1
RS600 Thermal Limits ........................................................................................................................................ 5-5
5.2.2
Other Thermal Parameters................................................................................................................................... 5-5
5.3 Physical Package ................................................................................................................................................................ 5-6
5.4 Pressure Specifications....................................................................................................................................................... 5-8
5.5 Board Solder Reflow Process Recommendations .............................................................................................................. 5-8
5.5.1
Stencil Opening Size for Solderball Pads on PCB .............................................................................................. 5-8
5.5.2
Reflow Profiles .................................................................................................................................................... 5-9
Chapter 6: Power Management and ACPI
6.1 ACPI Power Management Implementation ....................................................................................................................... 6-1
6.2 Power Management for the Graphics Controller ............................................................................................................... 6-2
RS600 Databook
Table of Contents-2
Table of Contents
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
PCI Function Power States...................................................................................................................................6-2
PCI Power Management Interface........................................................................................................................6-2
Capabilities List Data Structure in PCI Configuration Space ..............................................................................6-3
Register Block Definition.....................................................................................................................................6-3
Capability Identifier: Cap_ID (Offset = 0)...........................................................................................................6-4
Next Item Pointer .................................................................................................................................................6-5
PMC - Power Management Capabilities (Offset = 2) ..........................................................................................6-6
Chapter 7: Testability
7.1 Test Capability Features......................................................................................................................................................7-1
7.2 Test Interface.......................................................................................................................................................................7-1
7.3 XOR Tree ............................................................................................................................................................................7-1
7.3.1
Brief Description of an XOR Tree .......................................................................................................................7-1
7.3.2
Description of the XOR Tree for the RS600 ........................................................................................................7-2
7.3.3
XOR Tree Activation ...........................................................................................................................................7-2
7.3.4
XOR Chain for the RS600....................................................................................................................................7-2
7.3.5
Unused Pins ..........................................................................................................................................................7-8
Appendix A: Pin Listings
A.1 Pin List Sorted by Ball Reference ......................................................................................................................................1-2
A.2 Pin List Sorted by Pin Name ............................................................................................................................................1-14
Appendix B: Revision History
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RS600 Databook
Table of Contents-4
List of Figures
Figure 1-1: RS600 Branding Diagram ........................................................................................................................................... 1-8
Figure 1-2: RS600L Branding Diagram ......................................................................................................................................... 1-8
Figure 1-3: RS600-Family ASIC Part Number Legend ................................................................................................................. 1-9
Figure 2-1: RS600 Internal Block Diagram ................................................................................................................................... 2-1
Figure 2-2: Host Interface Block Diagram ..................................................................................................................................... 2-2
Figure 2-3: RS600 Host Bus Interface Signals .............................................................................................................................. 2-3
Figure 2-4: RS600 System Memory Interface ............................................................................................................................... 2-5
Figure 2-5: CAS Latency Example ................................................................................................................................................ 2-8
Figure 2-6: Consecutive Read Bursts (4 Cycles) ........................................................................................................................... 2-8
Figure 2-7: Consecutive Write Bursts (4 Cycles) .......................................................................................................................... 2-9
Figure 2-8: Consecutive Read Bursts (8 Cycles) ........................................................................................................................... 2-9
Figure 2-9: Consecutive Write Burst (8 Cycles) ............................................................................................................................ 2-9
Figure 2-10: CKE, CS, and ODT Distributions for DDR2/DDR3 SDRAMs .............................................................................. 2-10
Figure 2-11: Data Transmission Ordering for the Integrated DVI/HDMI Interface .................................................................... 2-11
Figure 2-12: Data Transmission Ordering for the TMDS Interface Multiplexed on the PCI-E Graphics Lanes ........................ 2-14
Figure 3-1: Pin Assignment Top View (Left) ................................................................................................................................ 3-2
Figure 3-2: Pin Assignment Top View (Right) .............................................................................................................................. 3-3
Figure 3-3: RS600 Interface Block Diagram ................................................................................................................................ 3-4
Figure 4-1: Front Side Bus Timing for Data Signals ..................................................................................................................... 4-4
Figure 4-2: Front Side Bus Timing for Address Signals ................................................................................................................ 4-4
Figure 4-3: Front Side Bus Timing for Control Signals ................................................................................................................. 4-5
Figure 4-4: SYSCLK/SYSCLK# AC Specifications ..................................................................................................................... 4-6
Figure 4-5: Power Rail Power Up Sequence for the RS600 .......................................................................................................... 4-7
Figure 5-1: Front Side Bus DC Characteristics .............................................................................................................................. 5-2
Figure 5-2: DC Characteristics for HDMI ..................................................................................................................................... 5-4
Figure 5-3: RS600 Package Outline ............................................................................................................................................... 5-6
Figure 5-4: RS600 Detailed Ball Arrangement .............................................................................................................................. 5-7
Figure 5-5: Recommended Stencil Opening Sizes for Solderball Pads on PCB ........................................................................... 5-8
Figure 5-11: Eutectic Solder(Sn63/Pb37 Tin-Lead) Reflow Profile .............................................................................................. 5-9
Figure 5-12: Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile ..................................................................... 5-10
Figure 6-1: Linked List for Capabilities ......................................................................................................................................... 6-5
Figure 7-1: An Example of a Generic XOR Tree .......................................................................................................................... 7-1
RS600 Databook
List of Figures-1
List of Figures
RS600 Databook
List of Figures-2
List of Tables
Table 1-1: RS600-Family ASIC Part Numbers ...............................................................................................................................1-9
Table 1-2: Pin Type Codes ............................................................................................................................................................1-10
Table 1-3: Acronyms and Abbreviations ......................................................................................................................................1-10
Table 2-1: Front Side Bus Interface Transaction Phases ................................................................................................................2-2
Table 2-2: Supported DDR2 Components ......................................................................................................................................2-6
Table 2-3: Supported DDR3 Components ......................................................................................................................................2-6
Table 2-4: DIMM Configurations Supported by the RS600 ...........................................................................................................2-6
Table 2-5: DDR2 Memory Row and Column Addressing ..............................................................................................................2-7
Table 2-6: Single Link Signal Mapping for the Integrated DVI/HDMI Interface .......................................................................2-12
Table 2-7: Dual-Link Signal Mapping for the Integrated DVI Interface ......................................................................................2-13
Table 2-8: Single Link Signal Mapping for the TMDS Interface Multiplexed on the PCI-E Graphics Lanes .............................2-15
Table 2-9: Support for HDMI Packet Types .................................................................................................................................2-16
Table 2-10: VGA DAC Characteristics ........................................................................................................................................2-18
Table 3-1: CPU Interface ................................................................................................................................................................3-5
Table 3-2: Address Signals and Associated Strobes .......................................................................................................................3-6
Table 3-3: Grouping of CPU_D[63:0]# Signals .............................................................................................................................3-6
Table 3-4: Response Signals ...........................................................................................................................................................3-6
Table 3-5: DDR2/DDR3 Memory Interface ...................................................................................................................................3-7
Table 3-6: 1 x16 Lane PCI Express Interface for External Graphics ..............................................................................................3-8
Table 3-7: 1 x4 Lane A-Link Express II Interface for IXP .............................................................................................................3-8
Table 3-8: 4 x1 Lane PCI Express Interface for General Purpose External Devices ......................................................................3-8
Table 3-9: Miscellaneous PCI Express Signals ...............................................................................................................................3-9
Table 3-10: Clock Interface .............................................................................................................................................................3-9
Table 3-11: CRT and TV Interface .................................................................................................................................................3-9
Table 3-12: Integrated DVI/HDMI Interface ................................................................................................................................3-10
Table 3-13: TMDS Interface (Multiplexed with the PCI-E Graphics Interface) ..........................................................................3-11
Table 3-14: SDVO Interface for External Displays ......................................................................................................................3-11
Table 3-15: Power Management Pins ...........................................................................................................................................3-12
Table 3-16: Miscellaneous Pins ....................................................................................................................................................3-12
Table 3-17: Power Pins .................................................................................................................................................................3-13
Table 3-18: Ground Pins ...............................................................................................................................................................3-15
Table 3-19: Strap Definitions for the RS600 ..............................................................................................................................3-16
Table 4-1: Processor Front Side Bus Timing (for 1066 MHz Front Side Bus*) ............................................................................4-1
Table 4-2: Processor Front Side Bus Timing (for 800MHz Front Side Bus) .................................................................................4-2
Table 4-3: Processor Front Side Bus Timing (for 533MHz Front Side Bus) .................................................................................4-3
Table 4-4: System Clock AC Specifications ...................................................................................................................................4-5
Table 4-5: Timing Requirements for the OSCIN Pad .....................................................................................................................4-6
Table 4-6: Power Rail Power Up Sequence Timing for the RS600 ................................................................................................4-7
Table 5-1: Maximum and Minimum Ratings ..................................................................................................................................5-1
Table 5-2: DC Characteristics for Front Side Bus Signals ..............................................................................................................5-1
Table 5-3: DC Characteristics for PCI-E Differential Clock (GFX_CLK, SB_CLK) Input ..........................................................5-2
Table 5-4: DC Characteristics for TTL Signals ..............................................................................................................................5-3
Table 5-5: DC Characteristics for the DDR2/3 Interface ................................................................................................................5-3
Table 5-6: DC and Characteristics for OSCIN Pad .........................................................................................................................5-3
Table 5-7: Electrical Requirements for DVI/HDMI .......................................................................................................................5-4
Table 5-8: RS600 Thermal Limits ..................................................................................................................................................5-5
Table 5-9: Thermal Parameters for the RS600 ................................................................................................................................5-5
Table 5-10: RS600 1201-Pin FCBGA Package Physical Dimensions ...........................................................................................5-6
Table 6-1: ACPI States Supported by the RS600 ...........................................................................................................................6-1
Table 6-2: ACPI Signal Definitions ................................................................................................................................................6-1
Table 6-3: Standard PCI Configuration Space Header Type 0 .......................................................................................................6-2
Table 6-4: PCI Status Register ........................................................................................................................................................6-3
RS600 Databook
List of Tables-1
List of Tables
Table 6-5: Capabilities Pointer (CAP_PTR) ...................................................................................................................................6-3
Table 6-6: Power Management Register Block ..............................................................................................................................6-4
Table 6-7: Power Management Control/Status Register (PMCSR) ................................................................................................6-4
Table 6-8: Capability Identifier (Cap_ID) .......................................................................................................................................6-4
Table 6-9: Next Item Pointer (NEXT_ITEM_PTR) .......................................................................................................................6-5
Table 6-10: Power Management Capabilities – PMC .....................................................................................................................6-6
Table 7-1: Pins on the Test Interface ...............................................................................................................................................7-1
Table 7-2: Example of an XOR Tree ..............................................................................................................................................7-2
RS600 Databook
List of Tables-2
Chapter 1
Overview
1.1
Introducing the RS600
The RS600 is a seventh generation Integrated Graphics Processor (IGP) that integrates a DirectX 9.0 compliant 2D/3D
graphics core and a system controller in a single chip, supporting the Intel desktop platform.
The RS600 integrates an ATI Radeon X700-based graphics engine, dual display, a TV encoder, an integrated DVI/HDMI
interface, an integrated TMDS controller, and north bridge functionality into a single BGA package. This high level of
integration and scalability enables manufacturers to offer enthusiast level capabilities and performance while minimizing
board space and system cost.
Robust and Flexible Core Logic Features
The RS600 combines graphics and system logic functions in a single chip using a 35mm-body FCBGA package, reducing
overall solution area. For optimal system and graphics performance, the RS600 incorporates a dual-channel, 128-bit
system memory interface with support for both DDR2 and DDR3-SDRAM. The RS600 is ideally suited to 64-bit
operating systems, with 34-bit host addressing and support for up to 16 GB of system memory. The rich PCI Express
expansion capabilities of RS600, including support for PCI Express external graphics and up to six other PCI Express
peripherals, are complemented by the advanced I/O features of ATI’s SB600 south bridge.
Best for Windows Vista
The RS600 delivers the best Windows Vista experience of any integrated graphics and core logic products. It incorporates
an ATI RADEON X700-based graphics core, which provides the 3D rendering power needed to generate the Windows
Vista desktop even under the most demanding circumstances. In addition, dedicated hardware acceleration is provided for
key new Windows Vista features such as ClearType, Virtual Memory, Context Switching, and Privileged Operations. This
RADEON X700-based graphics technology also enables great 3D application performance through technologies such as
SmartShader™ HD, Smoothvision™ HD, and 3Dc.
Leading Multimedia Capabilities
The RS600 incorporates ATI’s innovative Avivo™ display architecture, providing users with visual quality which is
second to none. Advanced scaling and color correction capabilities, along with increased precision through the entire
display pipeline, ensure an optimal image on CRT monitors, LCD panels, and any other display devices. A new TV
encoder based on ATI’s Xilleon™ products provides unequalled quality, and fully integrated DVI/HDMI and HDCP
support allows compatibility with even the most modern high definition televisions without the additional cost of external
components.
Low Power Consumption and Industry Leading Power Management
The RS600 is manufactured using the power efficient 90nm technology, and it supports a whole range of industry
standards and all new proprietary power management features. In addition to comprehensive support for the ACPI
specification and Intel features such as SpeedStep, ATI's exclusive technologies including PowerOnDemand™ minimize
the RS600’s power consumption by adjusting graphics core performance and core voltage to the task and usage
environment. Integrated motion compensation and IDCT support reduce CPU loading and hence overall power
consumption.
Software Compatibility
The graphics driver for the RS600 is fully compatible with all other Radeon class graphics controllers from ATI. A single
driver can support multiple graphics configurations across ATI’s product lines, including the Radeon family and the
Radeon IGP family. In addition, this driver compatibility allows the RS600 to benefit immediately from ATI's software
optimization and from the advanced Windows XP and Windows Vista support available in the Radeon family drivers.
1.2
The RS600L
The RS600L is a variant of the RS600 that supports Front Side Bus speeds of up to 800 MHz. Unless otherwise specified,
all information in this databook is applicable to the RS600L.
RS600 Databook
1-1
RS600 Features
1.3
RS600 Features
1.3.1
CPU Interface
•
Supports the Intel Pentium 4, Pentium D, Pentium Extreme Edition, Celeron, Celeron D, Cedar Mill, Conroe, and
Allendale processors.
•
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Supports Front Side Bus (FSB) speeds 533, 800, and 1066MHz*.
Supports Front Side Bus Dynamic Bus Inversion (DBI).
Supports Intel Hyper-Threading Technology.
In-Order Queue (IOQ) of depth 12.
Supports Front Side Bus interrupt delivery.
Supports Intel Extended Memory 64 Technology (EM64T).
Supports Intel Execute Disable (XD) Bit Functionality.
Supports 34-bit host addressing.
*Note: 1066MHz FSB speed is not supported by the RS600L
1.3.2
Memory Interface
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1.3.3
128-bit dual-channel DDR2/DDR3 SDRAM interface.
Supports up to 16 GB of system memory.
Unified Memory Architecture, with 16 to 512 MB of the main memory configurable as display memory.
Supports DDR2-400, -533, -667, -800 SDRAM.
Supports DDR3-800, -1067.
Supports 256 Mbit, 512 Mbit, 1 Gbit, and 2 Gbit DDR2/DDR3 DIMMs.
Supports memory device widths of x8 and x16.
Supports industry-standard DDR SDRAM self refresh mechanism.
Supports pre-charge powerdown.
Supports independent CKE and ODT signals for each memory row (total of four CKEs and ODTs per channel).
PCI Express Interface
•
•
•
Compliant with the PCI Express 1.1a Specifications.
One x16 graphics interface. Instead of a graphics card, the interface can be configured to support an external display
(see section 1.3.10, “External Display Support by SDVO 1.0” below), plus a x1, x2, or x4 general purpose PCI-E link
at the same time. A TMDS interface, enabling HDMI, is also multiplexed on this interface. See section 1.3.9,
“DVI/HDMI” below for details).
Up to six* x1 PCI Express general purpose links.
*Note: Actual number of general purpose links available depends on the width of the A-Link Express II Interface. See
section 3.5.2“1 x4 Lane A-Link Express II to IXP” on page 3-8 for details.
1.3.4
A-Link Express II Interface
•
1.3.5
One x4 (reducible to x2) A-Link Express II interface (PCI Express 1.1 compliant) for connection to an ATI IXP,
providing more bandwidth than the older A-Link Express interface.
2D Acceleration Features
•
•
•
Highly-optimized 128-bit engine, capable of processing multiple pixels per clock.
Hardware acceleration of Bitblt, Line Draw, Polygon / Rectangle Fill, Bit Masking, Monochrome Expansion,
Panning/Scrolling, Scissoring, and full ROP support (including ROP3).
Optimized handling of fonts and text using ATI proprietary techniques.
RS600 Databook
1-2
RS600 Features
•
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1.3.6
Hardware acceleration for ClearType font rendering.
Game acceleration including support for Microsoft's DirectDraw: Double Buffering, Virtual Sprites, Transparent Blit,
and Masked Blit.
Supports a maximum resolution of 2048x1536 @ 32bpp (driver-limited).
Acceleration in 1/8/15/16/32 bpp modes:
•
ClearType mode for 1bpp
•
Pseudocolor mode for 8bpp
•
ARGB1555 and RGB565 modes for 16bpp
•
ARGB8888 mode for 32bpp
Significant increase in the High-End Graphics WinBench score due to capability for C18 color expansion.
Setup of 2D polygons and lines.
Support for new GDI extensions in Windows 2000 and Windows XP: Alpha BLT, Transparent BLT, Gradient Fill.
Hardware cursor (up to 64x64x32bpp), with alpha channel for direct support of Windows 2000 and Windows XP
alpha cursor.
3D Acceleration Features
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Multi-texturing via one texture blending unit per pixel pipes, allowing up to 512 texel reads per pixel in a single pass.
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Supports Z-compression.
3D Texture support, including projective 3D textures.
Comprehensive support for bump mapping: emboss, dot-product, and environment bump maps.
Improved precision in anisotropic filtering and bilinear filtering.
Complete 3D primitive support: points, lines, triangles, lists, strips and quadrilaterals and BLTs with Z compare.
Improved texture compositing.
Supports 2536x2536 @ 32bpp.
Hidden surface removal using 16, 24, or 32-bit Z-buffering (maximum Z-buffer depth is 24 bits when stencil buffer
enabled) and Early Z hardware.
8-bit stencil buffer.
Bilinear and trilinear texture filtering.
Full support of Direct3D texture lighting.
Dithering support in 16 bpp for near 24 bpp quality in less memory.
Extensive 3D mode support.
Anti-aliasing using multi-sampling algorithm with support for 2, 4, and 6 samples.
Optimized for full performance in true color triple buffered 32bpp acceleration modes.
New generation rendering engine provides top 3D performance.
Support for OpenGL format for Indirect Vertices in Vertex Walker.
Full DirectX 9.0 support (Vertex Shader version 2.0 and Pixel Shader version 2.0):
•
Full precision floating point pixel pipeline.
•
Support for up to 4 MRTs (Multiple-Render-Targets).
•
Support for writing all texture formats from render pipe in floating points (including cube mapes and 3D
textures).
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Support for up to 512b per pixel formats (4 color case).
•
Advanced setup engine, capable of processing 1 polygon (lit and textured) per cycle
RS600 Databook
1-3
RS600 Features
1.3.7
Motion Video Acceleration Features
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1.3.8
Enhanced MPEG-2 hardware decode acceleration, including support for:
•
Integrated general purpose iDCT engine for MPEG2 and DV decode acceleration.
•
Integrated MPEG motion compensation engine for decode acceleration.
•
Parallel operation of the iDCT and MC and high processing rates with minimal software overhead.
Provides dramatically reduced CPU utilization without incurring the cost of a full MPEG-2 decoder.
MPEG-4 simple profile support.
Hardware acceleration for H.264 playback.
Hardware acceleration for WMV9 playback.
Supports top quality DVD and time-shifted SDTV/HDTV television playback with the lowest CPU usage.
Hardware-based adaptive de-interlacing filter and scaler provide high quality full-screen and full-speed video
playback. Minimizes the aliasing artifacts along edges usually caused by a conventional deinterlacer/scaler.
Multiple Display Features
General
•
Dual independent displays. Possible configurations include:
•
CRT and DVI/HDMI
•
TV and DVI/HDMI
•
DVI and HDMI
•
CRT and CRT*
•
CRT and TV*
•
TV and TV*
*Note: These options require implementation of the external display interface; see section 1.3.10, “External Display
Support by SDVO 1.0,” on page 6.
•
•
•
Resolution, refresh rates, and display data can be completely independent for the two display paths.
•
•
•
•
•
•
•
Supports both interlaced and non-interlaced displays.
•
•
•
•
•
Both display controllers support true 30 bits per pixel throughout the display pipe.
Both display paths support VGA and accelerated modes, video overlay, hardware cursor, hardware icon, and palette
gamma correction.
Support for display modes up to 2880 pixels/line per display.
Full ratiometric expansion ability is supported for source desktop modes up to 1920 pixels/line.
HD TV support (with underscan) for display modes of 1920 or less pixels/line.
SD TV support (with underscan) for display modes of 1024 or less pixels/line.
Maximum DAC frequency of 400 MHz.
Supports 8, 16, 32 & 64-bpp depths for the main graphics layer:
•
For 32-bpp depth, supports xRGB 8:8:8:8, xRGB 2:10:10:10, sCrYCb 8:8:8:8, and xCrYCb 2:10:10:10 data
formats.
•
For 64-bpp depth, supports xRGB 16:16:16:16 data format.
Independent gamma, color conversion and correction controls for main graphics layer.
Supports display resolutions beyond 2560x1600.
Support for DDC1 and DDC2B+ for plug and play monitors.
8-bit alpha blending of graphics and video overlay.
Hardware cursor up to 64x64 pixels in 2bpp, full color AND/XOR mix, and full color 8-bit alpha blend.
RS600 Databook
1-4
RS600 Features
•
Hardware icon up to 128x128 pixels in 2bpp, with two colors, transparent, and inverse transparent. AND/XOR
mixing. Supports 2x2 icon magnification.
•
•
•
•
Virtual desktop support.
Support for flat panel displays and TVs via VGA, DVI, or HDMI.
Integrated HD Audio Controller for HDMI audio data.
Support for stereoscopic monitors.
TV Out
•
An integrated TV encoder from ATI’s Xilleon products, with an on-chip DAC (shared with the CRT analog output)
(Note: Simultaneous output for TV and CRT is not supported).
•
10-bit DAC with 10-tap filter producing scaled, flicker removed, artifact suppressed display on a PAL or NTSC TV
with composite, S-Video, component, and RGB output.
•
With the proper BIOS implementation, supports different TV standards including NTSC, NTSC-J, PAL-M, PAL-CN,
PAL-B, PAL-G, PAL-D, PAL-H, PAL-I, PAL-K, and PAL-N.
•
•
Supports Macrovision 7.1 copy protection standard (required by DVD players).
•
•
•
•
•
•
1024x768 support. Supports all standard resolutions for RGB-based TVs, including:
•
640 x 480i
•
720 x 480i
•
640 x 480p
•
720 x 480p
•
640 x 576i
•
720 x 576i
•
640 x 576p
•
720 x 576p
•
1280 x 720p
•
1980 x 1080i
Supports the following formats of YPbPr component output: 480i, 480p, 576i, 576p, 720p, and 1080i.
Internal adaptive flicker filtering available on both display paths for interlaced TV outputs.
Supports fully-programmable 2D, adaptive comb filter for composite output.
TV-out power management support.
Line 21 Closed Caption and Extended Data Service support for encoding in Vertical Blanking Interval (VBI) of TV
signal.
CGMS copy management support in VBI through Line-20 and/or Extended Data Service (Line-21 Field 2) for
NTSC, and through Wide Screen Signaling data (WSS) for PAL.
SURROUNDVIEW
•
1.3.9
RS600’s SURROUNDVIEW™ feature allows support for up to three independent monitors for systems equipped
with an additional ATI discrete graphics card (requires special BIOS and display driver support).
DVI/HDMI
•
•
•
•
Integrated DVI or HDMI 1.2 interface: single-link support only for HDMI‡, 30-bit dual-link support for DVI.
Also supports a TMDS interface, enabling HDMI 1.2, which is multiplexed on the PCI-E external graphics interface
(only available if no external graphics card is attached to the PCI-E external graphics interface).‡
1650 Mbps/channel† with 165 MHz† pixel clock rate per link.
Supports industry standard EVA-861B video modes including 480p, 720p and 1080i. For a full list of currently
supported modes, contact your ATI FAE representative.
RS600 Databook
1-5
RS600 Features
•
HDMI basic audio support at 32, 44.1 or 48 kHz. Supports two-channel uncompressed audio data and, for Windows
Vista platforms only, 5.1-channel AC3 compressed audio data. HD audio device compatible with the Microsoft HD
audio driver.
•
HDCP 1.1 support on data stream with on-chip key storage (available only on either one of the integrated
DVI/HDMI interface or the TMDS interface (multiplexed on the PCI-E graphics lanes) at any time; it is also
unavailable for dual-link DVI mode).
Notes: * CEC is not supported.
‡ The TMDS interface multiplexed on the PCI-E graphics lanes cannot enable HDMI when the integrated
DVI/HDMI interface is supporting HDMI, and vice versa.
† To be qualified.
1.3.10 External Display Support by SDVO 1.0
Note: External display support by SDVO is not available when an external graphics card is supported or when the TMDS
interface multiplexed on the PCI-E graphics lanes is used to enable HDMI.
•
•
•
Supports an external display (e.g., CRT, or TV) via a dual-channel SDVO 1.0 port.
Supports external analog TV encoders for NTSC, PAL, SECAM and SCART.
Supports external VGA DAC for external DVI-I connection.
1.3.11 Power Management Features
•
•
Fully supports ACPI states S1, S3, S4, and S5.
•
•
Support for Intel SpeedStep and Enhanced SpeedStep technology.
•
•
•
Self-refresh DDR2/DDR3 SDRAM in Suspend mode.
The Chip Power Management Support logic supports four device power states defined for the OnNow Architecture—
On, Standby, Suspend, and Off. Each power state can be achieved by software control bits.
Clocks to every major functional block are controlled by a unique dynamic clock switching technique that is
completely transparent to the software. By turning off the clock to the block that is idle or not used at that point, the
power consumption is significantly reduced during normal operation.
Supports ATI PowerOnDemand™.
Support dynamic lane reduction for the PCI-E interfaces, adjusting to the task the number of lanes employed.
1.3.12 PC Design Guide Compliance
The RS600 complies with all relevant Windows Logo Program (WLP) requirements from Microsoft for WHQL
certification.
1.3.13 Test Capability Features
The RS600 has a variety of test modes and capabilities that provide a very high fault coverage and low DPM (Defect Per
Million) ratio:
•
Full scan implementation on the digital core logic which provides about 99% fault coverage through ATPG
(Automatic Test Pattern Generation Vectors).
•
•
•
•
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
•
Improved access to the analog modules and PLLs in the RS600 in order to allow full evaluation and characterization
of these modules.
•
Improved IDDQ mode support to allow chip evaluation through current leakage measurements.
A JTAG test mode in order to allow board level testing of neighboring devices.
An EXOR tree test mode on all the digital I/O's to allow for proper soldering verification at the board level.
An EXTEST test mode in order to allow board level testing by sampling the inputs and controlling the outputs of
RS600.
RS600 Databook
1-6
Software Features
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
1.3.14 Additional Features
•
Integrated spread spectrum PLLs on the memory interface.
1.3.15 Packaging
•
•
1.4
1201-FCBGA package, 35mmx35mm.
Software Features
•
•
•
•
•
•
•
•
1.5
Single chip solution in 90nm, 1.0-1.2V CMOS technology.
Supports Microsoft Windows 2000, XP, and Vista.
BIOS ability to read EDID 1.1, 1.2, and 1.3.
Ability to selectively enable and disable several devices including CRT, LCD, TV, and DFP.
Register-compatible with VGA standards, BIOS-compatible with VESA VBE2.0.
Supports corporate manageability requirements such as DMI.
ACPI support.
Full Write Combining support for maximum performance of the CPU.
Full-featured, yet simple Windows utilities:
•
Calibration utility for WYSIWYG color
•
Independent brightness control of desktop and overlay
•
End user diagnostics
•
Drivers meet Microsoft's rigorous WHQL criteria and are suitable for systems with the "Designed for Windows"
logos.
•
•
•
•
•
•
•
Comprehensive OS and API support.
Hot-key support (Windows ACPI 1.0b or ATI Event Handler Utility where appropriate).
Extensive Power Management support.
Rotation mode support in software.
Dual CRTC, simultaneous view, extended desktop support (Win98, Win XP)
DirectX 9.0 support.
Switchable overlay support.
Branding Diagrams
Note: The branding diagrams below do not necessarily contain the latest ASCI revision numbers for the devices. Unless
specified otherwise, no information in this databook is specific to the ASIC revision numbers appearing in the diagrams.
RS600 Databook
1-7
Branding Diagrams
RS600
1021-FCBGA package
35mm X 35mm
ATI Artwork
RS600
215RPP6ALA11FK
XXXXXX.XX.XXX
YYWWSS
TAIWAN
RS600
215RPP6ALA11FK
XXXXXX.XX.XXX
YYWWSS
TAIWAN
ATI Code Name
Part Number (for ASIC revision A11)
Wafer Foundry’s Lot Number
Date and Other Codes*
Country of Origin
* YY - Assembly Start Year
WW - Assembly Start Week
XX - Assembly Location
Figure 1-1 RS600 Branding Diagram
RS600L
1021-FCBGA package
35mm X 35mm
ATI Artwork
RS600L
215RLP6ALA11FK
XXXXXX.XX.XXX
YYWWSS
TAIWAN
RS600L
215RLP6ALA11FK
XXXXXX.XX.XXX
YYWWSS
TAIWAN
ATI Code Name
Part Number (for ASIC revision A11)
Wafer Foundry’s Lot Number
Date and Other Codes*
Country of Origin
* YY - Assembly Start Year
WW - Assembly Start Week
XX - Assembly Location
Figure 1-2 RS600L Branding Diagram
RS600 Databook
1-8
Part Number Legend
1.6
Part Number Legend
Foundry Code
N – UMC
M– IBM
C- TSMC Fab3
S- TSMC Fab4
F- TSMC Fab5
G- TSMC Fab6
K- TSMC Fab12
L- TSMC Fab14
W- TSMC WSMC
Q- TSMC WSMC (8B)
T- TSMC Wafer Tech
Marketing
Brand Name
RPP6 – RS600
RLP6 – RS600L
RDP6 – RD600
MPP6 – RS600M
MLP6 – RS600ML
MDP6 – RS600MD
MEP6 – RS600ME
215
RPP6
Product Type
A
Substrate
Revision
215– Desktop
216– Mobile
A11
L
ASIC
Revision
Flip Chip
Blank – No
F– Yes
K
F
Package BOM
K – High Temp
G– Lead Free
Figure 1-3 RS600-Family ASIC Part Number Legend
Table 1-1 RS600-Family ASIC Part Numbers
1.7
Code Name
Part Number
RS600
215RPP6ALA11FK / 215RPP6ALA11FG
RS600L
215RLP6ALA11FK / 215RLP6ALA11FG
RD600
215RDP6ALA11FK / 215RDP6ALA11FG
RS600M
216MPP6ALA11FK / 216MPP6ALA11FG
RS600ML
216MLP6ALA11FK / 216MLP6ALA11FG
RS600MD
216MDP6ALA11FK / 216MDP6ALA11FG
RS600ME
216MEP6ALA11FK / 216MEP6ALA11FG
Conventions and Notations
The following conventions are used throughout this manual.
1.7.1
Pin Names
Pins are identified by their pin names or ball references. Multiplexed pins assume alternate “functional names” when they
perform their alternate functions, and these “functional names” are given in Chapter 3, “Pin Descriptions and Strap
Options.”
RS600 Databook
1-9
All active-low signals are identified by the suffix ‘#’ in their names (e.g., MEM_RAS#).
1.7.2
Pin Types
The pins are assigned different codes according to their operational characteristics. These codes are listed in Table 1-2.
Table 1-2 Pin Type Codes
Code
1.7.3
Pin Type
I
Digital Input
O
Digital Output
I/O
Bi-Directional Digital Input or Output
M
Multifunctional
Pwr
Power
Gnd
Ground
A-O
Analog Output
A-I
Analog Input
A-I/O
Analog Bi-Directional Input/Output
A-Pwr
Analog Power
A-Gnd
Analog Ground
Other
Pin types not included in any of the categories above
Numeric Representation
Hexadecimal numbers are appended with “h” (Intel assembly-style notation) whenever there is a risk of ambiguity. Other
numbers are in decimal.
Pins of identical functions but different trailing integers (e.g., “CPU_D0, CPU_D1, . . . CPU_D7”) are referred to
collectively by specifying their integers in square brackets and with colons (i.e., “CPU_D[7:0]”). A similar short-hand
notation is used to indicate bit occupation in a register. For example, NB_COMMAND[15:10] refers to the bit positions
10 through 15 of the NB_COMMAND register.
1.7.4
Register Field
A field of a register is referred to by the format of [Register Name].[Register.Field]. For example,
“NB_MC_CNTL.DISABLE_BYPASS” is the “DISABLE_BYPASS” field of the register “NB_MC_CNTL.”
1.7.5
Hyperlinks
Phrases or sentences in blue italic font are hyperlinks to other parts of the manual. Users of the PDF version of this manual
can click on the links to go directly to the referenced sections, tables, or figures.
1.7.6
Acronyms and Abbreviations
The following is a list of the acronyms and abbreviations used in this manual.
Table 1-3 Acronyms and Abbreviations
Acronym
ACPI
A-Link II
Full Expression
Advanced Configuration and Power Interface
A-Link Express II interface between the IGP and IXP.
BGA
Ball Grid Array
BIOS
Basic Input Output System. Initialization code stored in a ROM or Flash RAM used to start up a
system or expansion card.
BIST
Built In Self Test.
BLT
Blit
bpp
bits per pixel
CEC
Consumer Electronic Control
RS600 Databook
1-10
Table 1-3 Acronyms and Abbreviations (Continued)
Acronym
CPIS
Full Expression
Common Panel Interface Specification
CRT
Cathode Ray Tube
DAC
Digital to Analog Converter
DBI
Dynamic Bus Inversion
DDC
Display Data Channel. A VESA standard for communicating between a computer system and
attached display devices.
DDR
Double Data Rate
DFP
Digital Flat Panel. Monitor connection standard from VESA.
DPM
Defects per Million
DVI
Digital Visual Interface
DTV
Digital TV
DVD
Digital Video Disc
DVI
Digital Video Interface. Monitor connection standard from the DDWG (Digital Display Work
Group).
DVS
Digital Video Stream
EPROM
Erasable Programmable Read Only Memory
FIFO
First In, First Out
FPDI
Flat Panel Display Interface
FSB
Front Side Bus
GDI
Graphics Device Interface
GND
Ground
GPIO
General Purpose Input/Output
GTL+
Gunning Transceiver Logic
HDCP
High-Bandwidth Digital Content Protection
HDMI
High Definition Multimedia Interface
HDTV
High Definition TV. The 1920x1080 and the 1280x720 modes defined by ATSC.
HPD
Hot Plug Detect
iDCT
inverse Discrete Cosine Transform
IDDQ
IGP
Direct Drain Quiescent Current
Integrated Graphics Processor. A single device that integrates a graphics processor and a
system controller.
JTAG
Joint Test Access Group. An IEEE standard.
LVDS
Low Voltage Differential Signaling
MB
Mega Byte
MPEG
Motion Pictures Experts Group. Refers to compressed video image streams in either MPEG-1
or MPEG-2 formats.
NTSC
National Television Standards Committee. The standard definition TV system used in North
America and other areas.
PAL
Phase Alternate Line. The standard definition TV system used in Europe and other areas.
PCI
PCI-E
PCMCIA
Peripheral Component Interface
PCI Express
Personal Computer Memory Card International Association. It is also the name of a standard
for PC peripherals promoted by the Association.
PLL
Phase Locked Loop
POST
Power On Self Test
PD
Pull-down Resistor
PU
Pull-up Resistor
ROP
SDRAM
TMDS
UMA
RS600 Databook
1-11
Raster Operation
Synchronous Dynamic RAM
Transition Minimized Differential Signaling
Unified Memory Architecture
Table 1-3 Acronyms and Abbreviations (Continued)
Acronym
UV
UXGA
VBI
Full Expression
Chrominance (also CrCb). Corresponds to the color of a pixel.
Ultra Extended Graphics Array
Vertical Blank Interval
VESA
Video Electronics Standards Association
VGA
Video Graphics Adapter
VRM
Voltage Regulation Module
RS600 Databook
1-12
Chapter 2
Functional Descriptions
This chapter describes the functional operation of the major interfaces of the RS600 system logic chip. Figure 2-1,
“RS600 Internal Block Diagram,” illustrates the RS600 internal blocks and interfaces.
PCI-E
Interface
(1 x 16 Lanes)
Root
Complex
DDR2/3 SDRAM
Channel A
PCI-E
Interface
Memory Controller
(6 x 1 Lanes)
Expansion
Slots or
On-board
Devices
A-Link-E II
Interface
External
Graphics
CPU
BIU
(1 x 4 Lanes)
IXP
CPU
Interface
CPU
BIF
Register Interface
iDCT
Setup
Engine
DDR2/3 SDRAM
Channel B
2D
Engine
3D
Engine
TMDS, enabling HDMI
(multiplexed on PCI-E graphics lanes)
TV-Out
Display 1& 2
External Displays
through SDVO
MUX
Integrated DVI/HDMI
Overlay
CRT
Figure 2-1 RS600 Internal Block Diagram
RS600 Databook
2-1
Host Interface
2.1
Host Interface
The RS600 is optimized to interface with the CPUs it supports. This section presents an overview of the host interface.
For a detailed description of the interface, please refer to the specifications from the Intel Corporation. Figure 2-2, “Host
Interface Block Diagram,” illustrates the basic blocks of the host bus interface of the RS600.
Interface to CPU
Configuration
Registers
CPU
BIU
Data
Buffers
Root Complex
Memory Controller
Figure 2-2 Host Interface Block Diagram
The RS600 system logic implements the host address, control, and data bus interfaces within a single device. RS600 uses
a split transaction bus methodology, which implies that the communication between the processor and the rest of the
system is carried out by transactions that represent sequences of bus events following a certain protocol. Any transaction
may contain up to six phases as described in Table 2-1, “Front Side Bus Interface Transaction Phases.”
Table 2-1 Front Side Bus Interface Transaction Phases
Phase
Description
Arbitration
During this phase the bus requesters compete for bus ownership, and the requester that is granted the bus
proceeds to the request phase. There are two kinds of requesters agents: symmetric and priority. The CPU is a
symmetric agent and the RS600 is a priority agent. This gives the RS600 system logic the capability to grab the
bus at any time and guarantees low latency by preferred service. All bus agents track the bus arbitration state
internally. This reduces the number of signals required during this phase.
Request
The transaction is started by the current bus master asserting ADS#.
Error
This phase is entered on the second clock from ADS# asserted.
Snoop
Three clocks after ADS# is asserted or at least two clock cycles after the snoop phase of the previous
transaction. All caching agents (e. g. CPUs with internal cache) perform a snoop to their internal caches, using
the address sent out during the request phase. The result of the snoop operation is returned using the HIT#
and HITM# signals. The RS600 observes these returned signals and when a HITM# (hit into a dirty cache line)
signal is seen, the RS600 chip becomes the target for the cache writeback burst.
Response
RS600 delivers the response to the request agent during this phase. This phase will complete transaction with
no data transfer.
Data
During this phase the data transfer for a transaction is performed. Not all transactions have a data phrase.
The RS600 host bus interface consists of a bi-directional address interface, a bi-directional data interface, and a number of
control pins. The interface is illustrated in Figure 2.1, “Host Interface”. The signal name and direction for each signal is
shown with respect to the processor. Please note that the signal names may be different from those used in the pin listing
of the RS600. A detailed description of the signals is given in section 3.3, “CPU Interface‚’ on page 3-5.
RS600 Databook
2-2
System Memory Interface
CPU_A[33:3]#
CPU_CLKP
31
CPU_ADS#
CPU_BNR#
CPU_CLKN
CPU_BPRI#
CPU_BR0#
CPU_DBSY#
CPU_DEFER#
CPU_DRDY#
VDD_CPU
CPU_EDRDY#
CPU_COMP_N
CPU_COMP_P
CPU_D[63:0]#
64
CPU_DSTBN[3:0]#
4
CPU_DSTBP[3:0]#
4
CPU_ADSTB[1:0]#
2
CPU_DBI[3:0]
4
CPU
VDD_CPU
RS600
CPU_VREF
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_REQ[4:0]#
5
CPU_TRDY#
CPU_RS[2:0]#
3
CPU_CPURST#
Figure 2-3 RS600 Host Bus Interface Signals
2.2
The RS600 memory controller is a highly optimized unified memory controller. It arbitrates and optimizes the incoming
memory requests and accesses to the Graphics Address Remapping Table (GART). The RS600 memory controller
supports DDR2 and DDR3 SDRAM.
Figure 2-4, “RS600 System Memory Interface,” on page 5 illustrates the system memory interface of the RS600.
The RS600 memory controller supports a total of 16 GB of addressable physical memory. It controls up to two
un-buffered DDR2/DDR3 DIMMs per channel. It supports 256, 512, 1024, and 2048-Mbit memory devices. Device
widths of x8 and x16 are supported. Mixed banks are supported, allowing the mixing of x8 DIMM with x16 DIMM.
Please refer to Table 2-4, “DIMM Configurations Supported by the RS600,” on page 2-6 for the total memory sizes for
the various supported DIMM configurations.
RS600 Databook
2-3
Memory timing parameters are programmable via the RS600 memory controller configuration registers, allowing support
of different configurations and loadings. Refresh is also programmable, with support of various refresh rates as well as the
ability to queue up outstanding refreshes for effective execution.
The memory controller supports up to 32 open pages per memory channel. Memory page operations can be further
optimized by programming the number of idle cycles or the memory accesses to a bank before the bank is automatically
precharged. The number of idle cycles are either fixed or adaptively changed depending on the memory access pattern.
RS600 supports a maximum of two DIMMs per memory channel. Each DIMM can have two ranks, thus a maximum of
four ranks per channel are supported. The RS600 provides six differential clock pairs per memory channel (i.e., three for
each unbuffered DIMM).
RS600 Databook
2-4
Differential Clocks
24
MEMA_CK[5:0]P / MEMA_CK[5:0]N
0,1,2
3,4,5
Clock Enable MEMA_CKE[3:0]
4
0,1
2,3
Chip Select MEMA_CS[3:0]#
4
2,3
0,1
Memory Channel A
Column Address Strobe MEMA_CAS#
Write Enable MEMA_WE#
15
Address MEMA_A [14:0]
3
Bank Address MEMA_BA [2:0]
8
Data Mask MEMA_DM[7:0]
Data Strobes MEMA_DQS[7:0]P/
MEMA_DQS[7:0]N
16
64
Un-buffered DDR2/3 SDRAM DIMM
Row Address Strobe MEMA_RAS#
Data MEMA_DQ[63:0]
On-Die Termination MEMA_ODT[3:0]
4
0,1
2,3
RS600
DIMM 1
DIMM 0
24
Differential Clocks
MEMB_CK[5:0]P / MEMB_CK[5:0]N
0,1,2
4
3,4,5
Clock Enable MEMB_CKE[3:0]
0,1
4
2,3
Chip Select MEMB_CS[3:0]#
0,1
Memory Channel B
Write Enable MEMB_WE#
15
Address MEMB_A [14:0]
Bank Address MEMB_BA [2:0]
3
8
Data Mask MEMB_DM[7:0]
Data Strobes MEMB_DQS[7:0]P/
MEMB_DQS[7:0]N
16
64
Column Address Strobe MEMB_CAS#
Row Address Strobe MEMB_RAS#
2,3
Data MEMB_DQ[63:0]
On-Die Termination MEMB_ODT[3:0]
4
0,1
DIMM 0
2,3
DIMM 1
Figure 2-4 RS600 System Memory Interface
RS600 Databook
2-5
2.2.1
Memory Requests
For system memory requests, the RS600 memory controller takes the requests from the client interfaces and determines
the next request to be executed based on a number of factors. These factors include efficiency of the memory bus, urgency
of real-time requests, and request latency. Subsequently, the next request information is steered to the appropriate
memory channel and sent to the memory sequencer. The sequencer converts these requests into the signal and data
patterns required by a DDR SDRAM. In addition, the sequencer guarantees that all necessary DRAM refreshes are
performed.
The data bus is 64-bits wide per memory channel and may be configured for x8-bit or x16-bit memory components.
Coherency checking is performed on certain clients to ensure that read requests return the proper data.
2.2.2
Supported Memory Components
The memory controller supports DDR SDRAM chips in several configurations. These chips can be organized in banks,
rows, and columns. The supported memory components have either 4 or 8 banks for DDR2. All supported DDR3 memory
components have 8 banks. Only JEDEC timing is supported. Table 2-2 and Table 2-3 list the supported DDR2 and DDR3
components respectively.
Table 2-2 Supported DDR2 Components
DDR2 SDRAM
config
Mbits
Organization
banks bits
rows
Address Field Bits
columns
bank
row
col
16Mx16
256
4
16
8192
512
2
13
9
32Mx8
256
4
8
8192
1024
2
13
10
32Mx16
512
4
16
8192
1024
2
13
10
64Mx8
512
4
8
16384
1024
2
14
10
64Mx16
1024
8
16
8192
1024
3
13
10
128Mx8
1024
8
8
16384
1024
3
14
10
128Mx16
2048
8
16
16384
1024
3
14
10
256Mx8
2048
8
8
32768
1024
3
15
10
Table 2-3 Supported DDR3 Components
DDR3 SDRAM
config
2.2.3
Organization
Mbits
banks bits
rows
Address Field Bits
columns
bank
row
col
32Mx16
512
8
16
4096
1024
3
12
10
64Mx8
512
8
8
8192
1024
3
13
10
64Mx16
1024
8
16
8192
1024
3
13
10
128Mx8
1024
8
8
16384
1024
3
14
10
Supported Memory Configurations
RS600 supports up to two DIMMs per memory channel. It is possible to have different memory capacities on the two
memory channels. Table 2-4 below shows the DIMM configurations supported by the RS600.
Table 2-4 DIMM Configurations Supported by the RS600
Memory Part Type
config
16Mx16
32Mx8
RS600 Databook
2-6
banks
DIMM Configuration
Mbits
ranks
memory
chips
4
MBytes
4
256
1
128
2
8
256
4
256
1
8
256
2
16
512
Table 2-4 DIMM Configurations Supported by the RS600
Memory Part Type
config
Mbits
32Mx16
4 (DDR2)
8 (DDR3)
64Mx8
4 (DDR2)
8 (DDR3)
8
512
2048
8
256Mx8
512
1024
8
128Mx16
memory
chips
ranks
1024
8
128Mx8
2.2.4
DIMM Configuration
banks
64Mx16
(Continued)
2048
MBytes
1
4
256
2
8
512
1
8
512
2
16
1024
1
4
512
2
8
1024
1
8
1024
2
16
2048
1
4
1024
2
8
2048
1
8
2048
2
16
4096
Memory Banks
All supported DDR2 memories have 4 or 8 banks. Lower density DDR2 memories (256 Mb and 512 Mb memory parts)
have 4 banks, and higher density memory parts have 8 banks. For supported DDR3 parts (512 Mb and 1 Gb parts), all
memory components have 8 banks. The bank select bits are extracted from the physical address range [20:7]. Selection of
bank bits are register programmed.
2.2.5
Row and Column Addressing
Table 2-5 shows how the physical address P (after taking out the bank select bits) is used to provide the row and column
addressing for each size of DDR2/DDR3 memories.
Table 2-5 DDR2 Memory Row and Column Addressing
Address
A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode 4: 16Mx16 devices
Row
P12
P16
Column
P15
P14
PC
P13
P24
P23
P22
P21
P20
P19
P18
P17
P11
P10
P9
P8
P7
P6
P5
P4
P3
Mode 5: 32Mx8, 32Mx16 devices
Row
P25
P16
Column
P15
P14
P13
P24
P23
P22
P21
P20
P19
P18
P17
PC
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
Row
P26
P25
P16
Column
P15
P14
P13
P24
P23
P22
P21
P20
P19
P18
P17
PC
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
Row
P26
P25
P16
Column
P15
PC
P14
P13
P24
P23
P22
P21
P20
P19
P18
P17
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
Row
P27
P26
P25
Column
P16
P15
P14
P13
P24
P23
P22
P21
P20
P19
P18
P17
P27
PC
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
RS600 Databook
2-7
Address
A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Row
P16
Column
2.2.6
P15
P14
P13
P24
P23
P22
P21
P20
P19
P18
P17
PC
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
CAS Latency
The number of clock cycles that transpire between the availability of memory data and when the Read cycle was actually
registered is known as the CAS latency. This latency is programmable with delays of 3, 4, 5, 6, or 7 clock cycles. The
actual value chosen depends on the circuit implementation details and the memory speed (higher speeds require more
CAS latency). An example of CAS latency is given in Figure 2-5, “CAS Latency Example.”
0
1
2
3
4
5
6
7
8
9
Clock
Command
Read
Address
Addr A
Data (CAS = 3)
DA0
DA1
Data (CAS = 4)
DA2
DA3
DA0
DA1
Data (CAS = 5)
DA2
DA3
DA0
DA1
Data (CAS = 6)
DA2
DA3
DA0
DA1
Data (CAS = 7)
DA2
DA3
DA0
DA1
DA2
DA3
Figure 2-5 CAS Latency Example
2.2.7
Burst Type
There are two burst types used by DDR SDRAM chips: sequential and interleaved. The RS600 memory controller
supports only interleaved bursts.
2.2.8
Burst Length
Burst lengths are programmable with lengths of 4 cycles (for DDR2 only) or 8 cycles (for DDR2 or DDR3) per burst.
Consecutive read bursts are shown in Figure 2-6. Consecutive write bursts are handled in the same manner as read bursts,
and are shown in Figure 2-7.
0
1
2
3
4
5
6
7
Clock
Command
Address
Data (CAS = 2)
Read
Read
Addr A
Addr B
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
Figure 2-6 Consecutive Read Bursts (4 Cycles)
RS600 Databook
2-8
0
1
2
3
4
5
6
7
8
Clock
Command
Address
Write
Write
Addr A
Addr B
Data / Mask
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
Strobe
Figure 2-7 Consecutive Write Bursts (4 Cycles)
0
1
2
3
4
5
6
7
8
9
10
11
Clock
Command
Address
Read
Read
Addr A
Addr B
Data (CAS = 2)
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Figure 2-8 Consecutive Read Bursts (8 Cycles)
0
1
2
3
4
5
6
7
9
8
10
Clock
Command
Address
Write
Write
Addr A
Addr B
Data / Mask
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Strobe
Figure 2-9 Consecutive Write Burst (8 Cycles)
RS600 Databook
2-9
2.2.9
Clock Enable, Chip Select, and On-Die Termination Distributions for DDR2/DDR3 SDRAMs
The RS600 provides independent CKE and ODT signals for each memory row (total of four CKEs and ODTs per
channel). To take advantage of these features, follow the CKE, CS (Chip Select), and ODT (On-Die Termination)
distributions illustrated below for each memory channel.
RS600
DIMM 0
DIMM 1
RS600M
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_ODT0
MEM_ODT1
MEM_ODT2
MEM_ODT3
MEM_CS0#
MEM_CS1#
MEM_CS2#
MEM_CS3#
CKE0
CKE1
CKE0
CKE1
ODT0
ODT1
ODT0
ODT1
CS0#
CS1#
CS0#
CS1#
Figure 2-10 CKE, CS, and ODT Distributions for DDR2/DDR3 SDRAMs
RS600 Databook
2-10
DVI/HDMI
2.3
DVI/HDMI
2.3.1
Data Mapping for the Integrated DVI/HDMI Interface
The RS600 contains an integrated DVI/HDMI interface, which supports clock frequencies of up to 165 MHz on each link.
Figure 2-1 below shows the transmission ordering of the signals on the integrated DVI/HDMI interface in single-link
mode.
TXCP
TXCM
TX0P
TX0M
TB0
TB1
TG0
TG1
Depending upon state of PLL_SYNC and CTL1
TX2P
TX2M
TB4
TB5
TB6
TB7
TB8
TB9
TG2
TG3
TG4
TG5
TG6
TG7
TG8
TG9
Depending upon encoded Green channel pixel data
TR0
Depending upon state of CTL2 and CTL3
TB3
Depending upon encoded Blue channel pixel data
Depending upon state of HSYNC and VSYNC
TX1P
TX1M
TB2
TR1
TR2
TR3
TR4
TR5
TR6
TR7
TR8
TR9
Depending upon encoded Red channel pixel data
Figure 2-11 Data Transmission Ordering for the Integrated DVI/HDMI Interface
For dual-link mode, which is only supported for DVI, the same transmission order applies to data channels on the second
link, with the first link transmitting data for even pixels and the second link for odd pixels. See Table 2-7 below for
details.
The signal mapping for the transmission is shown in Table 2-6 (single link) and Table 2-7 (dual-link DVI) below.
RS600 Databook
2-11
DVI/HDMI
Table 2-6 Single Link Signal Mapping for the Integrated DVI/HDMI Interface
HDMI Functional
Name
TX0M/P
TX1M/P
TX2M/P
Data Phase
Signal
Phase 1
B9
Phase 2
B8
Phase 3
B7
Phase 4
B6
Phase 5
B5
Phase 6
B4
Phase 7
B3
Phase 8
B2
Phase 9
B1
Phase 10
B0
Phase 1
G9
Phase 2
G8
Phase 3
G7
Phase 4
G6
Phase 5
G5
Phase 6
G4
Phase 7
G3
Phase 8
G2
Phase 9
G1
Phase 10
G0
Phase 1
R9
Phase 2
R8
Phase 3
R7
Phase 4
R6
Phase 5
R5
Phase 6
R4
Phase 7
R3
Phase 8
R2
Phase 9
R1
Phase 10
R0
Note: H/VSYNC are transmitted on TX0M/P(Blue) channel during blank.
RS600 Databook
2-12
DVI/HDMI
Table 2-7 Dual-Link Signal Mapping for the Integrated DVI Interface
Link 1
HDMI
Functional
Name
TX0M/P
TX1M/P
TX2M/P
Data Phase
Link 2
Signal
HDMI
Functional
Name
TX3M/P
Data Phase
Signal
Phase 1
EVEN_B9
Phase 1
ODD_B9
Phase 2
EVEN_B8
Phase 2
ODD_B8
Phase 3
EVEN_B7
Phase 3
ODD_B7
Phase 4
EVEN_B6
Phase 4
ODD_B6
Phase 5
EVEN_B5
Phase 5
ODD_B5
Phase 6
EVEN_B4
Phase 6
ODD_B4
Phase 7
EVEN_B3
Phase 7
ODD_B3
Phase 8
EVEN_B2
Phase 8
ODD_B2
Phase 9
EVEN_B1
Phase 9
ODD_B1
Phase 10
EVEN_B0
Phase 10
ODD_B0
Phase 1
EVEN_G9
Phase 1
ODD_G9
Phase 2
EVEN_G8
Phase 2
ODD_G8
Phase 3
EVEN_G7
Phase 3
ODD_G7
Phase 4
EVEN_G6
Phase 4
ODD_G6
Phase 5
EVEN_G5
Phase 5
ODD_G5
Phase 6
EVEN_G4
Phase 6
ODD_G4
Phase 7
EVEN_G3
Phase 7
ODD_G3
Phase 8
EVEN_G2
Phase 8
ODD_G2
Phase 9
EVEN_G1
Phase 9
ODD_G1
Phase 10
EVEN_G0
Phase 10
ODD_G0
Phase 1
EVEN_R9
Phase 1
ODD_R9
Phase 2
EVEN_R8
Phase 2
ODD_R8
Phase 3
EVEN_R7
Phase 3
ODD_R7
Phase 4
EVEN_R6
Phase 4
ODD_R6
Phase 5
EVEN_R5
Phase 5
ODD_R5
Phase 6
EVEN_R4
Phase 6
ODD_R4
Phase 7
EVEN_R3
Phase 7
ODD_R3
Phase 8
EVEN_R2
Phase 8
ODD_R2
Phase 9
EVEN_R1
Phase 9
ODD_R1
Phase 10
EVEN_R0
Phase 10
ODD_R0
TX4M/P
TX5M/P
Notes:
- H/VSYNC are transmitted on TX0M/P(Blue) channel during blank.
- For DVI dual-link mode, the first active data pixel is defined as pixel#0 (an even pixel), as opposed to the DVI specifications.
RS600 Databook
2-13
DVI/HDMI
2.3.2
Data Mapping on the TMDS Interface Multiplexed on the PCI-E Graphics Lanes
The RS600 contains a TMDS interface, multiplexed on the PCI-E graphics lanes, which supports clock frequencies of up
to 165 MHz. Figure 2-1 below shows the transmission ordering of the signals on the interface. The multiplexing
relationships between the PCI-E graphics signals and the TMDS signals are given in section 3.9, “TMDS Interface
Multiplexed on the PCI-E Graphics Lanes‚’ on page 3-11
TXCP
TXCM
TX0P
TX0M
TR0
TR1
TG0
TG1
Depending upon state of PLL_SYNC and CTL1
TX2P
TX2M
TR4
TR5
TR6
TR7
TR8
TR9
TG2
TG3
TG4
TG5
TG6
TG7
TG8
TG9
Depending upon encoded Green channel pixel data
TB0
Depending upon state of CTL2 and CTL3
TR3
Depending upon encoded Red channel pixel data
Depending upon state of HSYNC and VSYNC
TX1P
TX1M
TR2
TB1
TB2
TB3
TB4
TB5
TB6
TB7
TB8
TB9
Depending upon encoded Blue channel pixel data
Figure 2-12 Data Transmission Ordering for the TMDS Interface Multiplexed on
the PCI-E Graphics Lanes
The signal mapping for the transmission is shown in Table 2-8 below.
RS600 Databook
2-14
DVI/HDMI
Table 2-8 Single Link Signal Mapping for the TMDS Interface Multiplexed on the PCI-E Graphics Lanes
TMDS
Functional
Name
TX0M/P
TX1M/P
TX2M/P
Data Phase
Signal
Phase 1
R9
Phase 2
R8
Phase 3
R7
Phase 4
R6
Phase 5
R5
Phase 6
R4
Phase 7
R3
Phase 8
R2
Phase 9
R1
Phase 10
R0
Phase 1
G9
Phase 2
G8
Phase 3
G7
Phase 4
G6
Phase 5
G5
Phase 6
G4
Phase 7
G3
Phase 8
G2
Phase 9
G1
Phase 10
G0
Phase 1
B9
Phase 2
B8
Phase 3
B7
Phase 4
B6
Phase 5
B5
Phase 6
B4
Phase 7
B3
Phase 8
B2
Phase 9
B1
Phase 10
B0
Note: H/VSYNC are transmitted on TX0M/P(Red) channel
during blank.
RS600 Databook
2-15
DVI/HDMI
2.3.3
Support for HDMI Packet Types
Table 2-9 Support for HDMI Packet Types
Packet
Value
Packet Type
0x00
Null
0x01
Audio Clock
Regeneration
0x02
Audio Sample
Supported Source
or Not
Comment
Yes
Sent when required to meet
Inserted by hardware if no packets in
horizontal active on line 2 (can be disabled maximum time between data island
specification.
by software).
Yes
Inserted by hardware or video driver.
Contents from register bits or combination
of register bits and hardware control.
Inserted in horizontal blank.
—
Yes
Audio samples come from HD audio DMA.
Channel status from HD audio and video
registers.
Inserted in horizontal blank whenever audio
FIFO contains data.
—
No
Sending and contents controlled by video
driver.
Inserted (on even frames only in interlaced
mode) when requested by software or
whenever AVMUTE status changes.
Inserted in horizontal active on line selected
by software.
—
—
Audio content protection information.
0x03
General Control
0x04
ACP Packet
Yes*
0x05
ISRC1 Packet
Yes
Controlled by video driver.
Inserted in horizontal active on line selected For transmitting UPC or ISRC codes.
by software.
0x06
ISRC2 Packet
Yes
Software controlled.
Inserted in horizontal active on line selected Implement if ISRC1 is used.
by software.
0x07
Reserved
N/A
N/A
N/A
InfoFrame Packet Type
HDMI ID
EIA-861B
ID
0x80
0x00
Vendor-Specific
Yes*
0x81
0x01
AVI
Yes
0x82
0x02
Source Product
Descriptor
Yes*
—
—
Controlled by video driver.
For colorimetry, repetition count,
video format, picture formatting.
by software.
—
—
0x83
0x03
Audio
Yes
by software.
For channel counts, sampling
Contents from registers written by video
frequency, etc.
and HD audio drivers.
Sent only when HD audio enables audio
(video driver can also disable).
0x84
0x04
MPEG Source
Yes
Software contolled.
Inserted in horizontal active on line selected For bit rate, field repeat, frame type
by software.
* Note: These packet types are supported using generic packet types. A maximum of two of them can be supported simultaneously.
RS600 Databook
2-16
SDVO Interface
2.4
SDVO Interface
The RS600 contains a dual-link SDVO interface, which supports clock frequencies of up to 165 MHz on each link.
SDVO is an Intel proprietary encoding scheme. On the RS600, the SDVO interface is multiplexed with the PCI-E
interface for external graphics. SDVO support is therefore unavailable if an external graphics card is attached. See section
3.10, “SDVO Interface for External Displays‚’ on page 3-11 for the mapping between the PCI-E and SDVO pins. An
SDVO compliant PCI-E add-on card, plugged into the external graphics/SDVO PCI-E interface, is responsible for
converting the SDVO signals to a variety of desired output formats including TMDS, S-video, composite video,
component video, CRT, etc.
2.4.1
Symbol Replication
The SDVO interface pixel clock rate has to fall within 100-200 MHz, regardless of resolution. Hence, for resolution with
pixel clock rate lower than 100 MHz, the RS600 provides data stuffing at 1X, 2X, 3X, 4X, or 5X to make the pixel clock
rate fall within the required range.
2.4.2
Dual-link Mode
For a resolution with pixel clock rate higher than 200 MHz, the SDVO data is transmitted in the dual-link mode: data
stream is split into two, one for the odd and the other for even pixels, and the clock frequency is reduced by half.
2.4.3
I2C/DDC Support
The RS600 SDVO interface has I2C/DDC support for transfer of opcodes and panel information read back.
2.4.4
HPD Support
The RS600 SDVO interface supports hot plug detect.
RS600 Databook
2-17
VGA DAC Characteristics
2.5
VGA DAC Characteristics
Table 2-10 VGA DAC Characteristics
Parameter
Resolution
Min
Typ
Max
Notes
10 bits
-
-
1
Maximum PS/2 setting Output Voltage
-
0.7V
-
1, 10
Maximum PS/2 setting Output Current
-
18.7mA
-
1, 10
+8% / -3%
-
+10%
2, 3
-2%
-
+2%
1, 4
Full Scale Error
DAC to DAC Correlation
Differential Linearity
-2 LSB
-
+2 LSB
1, 5
Integral Linearity
-2 LSB
-
+2 LSB
1, 5
Rise Time (10% to 90%)
0.58ns
-
1.7ns
1, 6
Full Scale Settling Time
-
TBA
-
1, 7, 8
Glitch Energy
-
TBA
-
1, 8
Monotonicity
-
-
-
9
Notes:
1 - Tested over the operating temperature range at nominal supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing
out of the RSET resistor).
2 - Tested over the operating temperature range at reduced supply voltage, with an Iref of -1.50mA (Iref is the level of the current flowing
out of the Rset resistor).
3 - Full scale error from the value predicted by the design equations.
4 - About the mid-point of the distribution of the three DACs measured at full scale deflection.
5 - Linearity measured from the best fit line through the DAC characteristics. Monotonicity guaranteed.
6 - Load = 37.5Ω + 20 pF with Iref = -1.50 mA (Iref is the current flowing out of the Rset resistor).
7 - Measured from the end of the overshoot to the point where the amplitude of the video ringing is down to +/-5% of the final steady state
value.
8 - This parameter is sampled, not 100% tested.
9 - Monotonicity is guaranteed.
10 - Levels are 7.8% higher with setup pedestal enabled.
2.6
External Clock Chip
On the RS600 platform, an external clock chip provides the CPU, Front Side Bus, PCI Express, and A-Link Express II
reference clocks. For more information about supported clock chips, please consult your ATI FAE representative.
RS600 Databook
2-18
Chapter 3
Pin Descriptions and Strap Options
This chapter gives the pin descriptions and the strap options for the RS600. To jump to a topic of interest, use the
following list of hyperlinked cross references:
“Pin Assignment Top View” on page 3-2
“RS600 Interface Block Diagram” on page 3-4
“CPU Interface” on page 3-5
“DDR2/DDR3 Memory Interface” on page 3-7
“PCI Express Interfaces” on page 3-8:
“1 x16 Lane Interface for External Graphics” on page 3-8
“1 x4 Lane A-Link Express II to IXP” on page 3-8
“4 x1 Lane Interface for General Purpose External Devices” on page 3-8
“Miscellaneous PCI Express Signals” on page 3-9
“Clock Interface” on page 3-9
“CRT and TV Interface” on page 3-9
“Integrated DVI/HDMI Interface” on page 3-10
“TMDS Interface Multiplexed on the PCI-E Graphics Lanes” on page 3-11
“SDVO Interface for External Displays” on page 3-11
“Power Management Pins” on page 3-12
“Miscellaneous Pins” on page 3-12
“Power Pins” on page 3-13
“Ground Pins” on page 3-15
“Strapping Options” on page 3-16
RS600 Databook
3-1
Pin Assignment Top View
3.1
The figures below do not show the actual ball positions on the package, for which one should refer to Figure 5-4, “RS600
Detailed Ball Arrangement,” on page 5- 7.
.
3
4
A
1
2
VSS_PCIE
VSS
B
VSS_PCIE VSS_PCIE
C
VSS_PCIE GFX_RX0N GFX_RX0P
D
VSS_PCIE GFX_TX0P
E
GFX_TX0N VSS_PCIE VSS_PCIE
GFX_REFC
LKN
10
11
12
17
18
GFX_REFC GPPSB_RE
CPU_CLKP VDD_PCIE
LKP
FCLKP
5
VDD_PCIE
PLLVSS
PLLVDD12
PLLVDD18
VDD_18CP
VDD_CORE
U
AVDD
VDDR3
AVSSDI TESTMODE LTPVSS18
GPPSB_RE
CPU_CLKN VDD_PCIE
FCLKN
VDD_PCIE
OSCIN
DDC_DATA
STRP_DAT VDD_18ME
VDD_CORE
A
M
AVDD
VDDR3
AVDDDI
VSS
6
VSS
7
8
9
13
14
15
16
19
VDD_PCIE
VSS
VSS
VSS
VDD_18ME
M
VDD_CORE
COMP
RED
VSS
VDD_PCIE
VSS
VSS
VDD_18CP
U
VDD_CORE
VSS
VSS
TXCLK_UN
TXOUT_U3 TXOUT_U1
N
P
VDD_PCIE
POWERGO
OD
VSS
VDD_18ME
M
VDD_CORE
Y
GREEN
TXCLK_UP
TXOUT_U3
P
VSSLT
VDD_PCIE
VDD_PCIE
VSS
VDD_18CP
U
VDD_CORE
VSS
VSS
TXOUT_U2
N
VDDLT33
VDDLT18
VSS
VDD_18ME
M
VDD_CORE
C
BLUE
TXOUT_U2
P
VDDLT33
VDDLT18
VDD_PCIE
VDD_PCIE
VDD_18CP
U
VSS
VSS
VSS
VSS
VSS
VDD_PCIE
VDD_PCIE
VDD_18ME
M
VSS
VSS
VSS
AVSSN
VSS
VDD_PCIE
VDD_18ME
M
VSS
VSS
VSS
AVSSN
VDD_18CP
U
VSS
J
VSS
VDD_PCIE
K
GFX_TX3N VSS_PCIE VSS_PCIE VSS_PCIE VSS_PCIE GFX_RX2N
L
GFX_TX4N GFX_TX4P VSS_PCIE
M
GFX_TX5N GFX_TX5P VSS_PCIE GFX_RX4N GFX_RX4P GFX_RX3N
GFX_RX2P VDD_PCIE
VDD_PLLP
CIE
GFX_RX3P VSS_PCIE
N
P
VSS_PCIE GFX_TX6P VSS_PCIE GFX_RX6P GFX_RX6N VSS_PCIE
R
GFX_TX6N VSS_PCIE VSS_PCIE
GFX_RX5N GFX_RX5P VSS_PCIE
VDD_PLLP VDD_PLLP
CIE
CIE
VSS_PCIE GFX_RX8P GFX_RX8N
VSS_PLLP VSS_PLLP
CIE
CIE
VSS
VDD_PCIE
VDD_18ME VDD_18CP VDD_18CP VDD_18CP
M
U
U
U
VDD_PCIE
VDD_18ME VDD_18CP VDD_18CP VDD_18CP
M
U
U
U
VDD_PCIE
VDD_18ME
VDD_COREVDD_COREVDD_CORE
M
T
GFX_TX7N GFX_TX7P VSS_PCIE VSS_PCIE GFX_RX7N GFX_RX7P
U
V
VDD_PCIE GFX_TX9P VDD_PCIE VSS_PCIE GFX_RX9P GFX_RX9N
VSS_PCIE
GFX_RX10 GFX_RX10
P
N
VSS_PLLP
VDD_PCIE
CIE
VDD_PCIE
VDD_18ME
VDD_COREVDD_CORE
M
W
GFX_TX9N VSS_PCIE VSS_PCIE VSS_PCIE VSS_PCIE VSS_PCIE
VSS_PCIE VSS_PCIE VSS_PCIE
VDD_PCIE VDD_PCIE
VDD_PCIE
VDD_18ME
VDD_CORE
M
Y
GFX_TX10 GFX_TX10
VSS_PCIE
N
P
AA
GFX_TX11 GFX_TX11
GFX_RX11 GFX_RX11
VSS_PCIE VSS_PCIE
N
P
N
P
AB
VSS_PCIE
VSS_PCIE
GFX_RX12 GFX_RX12
P
N
VDD_PCIE VDD_PCIE
AC
GFX_TX12
GFX_RX13 GFX_RX13
N
P
N
VSS_PCIE
GFX_RX14 GFX_RX14
P
N
VSS_PCIE VDD_PCIE
AD
GFX_TX13 GFX_TX13
VSS_PCIE VSS_PCIE VSS_PCIE VSS_PCIE
N
P
VSS_PCIE VDD_PCIE
AE
GFX_TX14 GFX_TX14
GFX_RX15 GFX_RX15
VSS_PCIE VSS_PCIE
N
P
N
P
VSS_PCIE GPP_TX3P GPP_TX3N
VSS_PCIE VDD_PCIE
AF
VSS_PCIE
GFX_TX12
VSS_PCIE
P
GFX_TX15
VSS_PCIE
P
AG
GFX_TX15
VSS_PCIE VSS_PCIE VSS_PCIE GPP_RX3P GPP_RX3N
N
AH
GPP_TX2N GPP_TX2P VSS_PCIE
AJ
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VSS
VDD_CORE
VSS
VDD_CORE
VDD_CORE
VSS
VDD_CORE
VSS
AK
VSS_PCIE GPP_TX1P VSS_PCIE VSS_PCIE GPP_RX0N GPP_RX0P
VSS_PCIE
VSS_PCIE VDD_PCIE
VDD_PCIE
VDD_18ME
VDD_CORE
M
AL
GPP_TX1N VSS_PCIE VSS_PCIE
VDD_PCIE
VDD_18ME
VDD_COREVDD_COREVDD_CORE
M
AM
GPP_RX1N GPP_RX1P VSS_PCIE VSS_PCIE SB_RX2P
VDD_PCIE
VDD_18ME VDD_18ME VDD_18ME VDD_18ME
M
M
M
M
VDD_PCIE
VDD_18ME
VDD_MEM VDD_MEM VDD_MEM
M
AN
SB_TX3N
AP
VDD_PCIE SB_TX2P VDD_PCIE VSS_PCIE VSS_PCIE VSS_PCIE
VDD_PCIE VDD_PCIE
VDD_PCIE VDD_PCIE
SB_TX3P VSS_PCIE
AR
AV
SB_TX0P
SB_TX0N
SB_RX0N
VSS
MEMB_DQ4 SUS_STAT#
MEMB_DQ MEMB_DQ MEMB_DQ
5
0
1
VSS
AY
BA
PCE_CALR PCE_CALR
PCE_CALI
P
N
BB
BC
MEMA_DQ MEMA_DQ MEMA_DQ
5
4
0
BD
MEMA_DQ MEMA_DM MEMA_DQ
1
0
S0N
BE
VSS
BG
1
MEMA_CK1
P
MEMB_DQ
6
VSS
2
VSS
3
4
VDD_MEM
VDD_MEM VDD_MEM
VDD_MEM
VDD_MEM VDD_MEM
VDD_MEM
VDD_MEM
MEMB_DQ
VDD_MEM
16
VDD_MEM
VDD_MEM
VSS
MEMB_DM
1
MEMB_DQ
S1N
VDD_MEM
MEMB_DQ
21
VDD_MEM
MEMB_DQ
VDD_MEM
25
VSS
MEMA_CK4
P
VSS
MEMB_DQ
S1P
VSS
MEMB_DQ
17
VSS
MEMB_DQ
18
VSS
MEMA_CK1
N
MEMA_CK4
N
MEMB_DQ
9
VSS
MEMB_DQ
20
VSS
MEMB_DQ
23
VSS
MEMB_DQ
19
MEMB_DQ
22
MEMB_DQ
24
VSS
VSS
MEMB_DQ
28
VSS
MEMB_DQ
S2N
VSS
MEMB_DQ
29
VSS
MEMB_CK
MEMB_A14 MEMB_A12
E2
VSS
VSS
VSS
MEMB_DQ
12
MEMB_DQ
14
MEMB_CK4
N
MEMB_CK1
N
VSS
MEMB_DQ
8
MEMB_DQ
11
MEMB_DQ
3
MEMB_CK4
P
MEMB_CK1
P
MEMB_DQ
13
VSS
VSS
7
2
8
VSS
VDD_MEM
VSS
MEMB_DQ
2
MEMA_DQ MEMA_DQ MEMA_DQ MEMA_DQ MEMA_DM MEMA_DQ MEMA_DQ1
S0P
6
3
13
1
14
0
VSS
BF
MEMB_DM MEMB_DQ MEMB_DQ
0
S0N
S0P
VSS
12
9
S1N
5
6
16
17
S2P
MEMA_DQ MEMA_DQ1
S1P
5
7
MEMA_DQ
20
VSS
8
9
VSS
VSS
MEMB_DQ7
AW
VDD_CORE
VDD_CORE
VDD_18ME
VDD_COREVDD_CORE
M
SB_RX1N
TXOUT_U1
N
VDD_CORE
VDD_PCIE
SB_RX1P
VSS
VSS
VSS_PCIE VDD_PCIE
VSS_PCIE
VSS
VDD_CORE
SB_RX2N
VSS
VSS
GPP_RX2N GPP_RX2P VSS_PCIE VSS_PCIE VSS_PCIE VSS_PCIE
SB_RX3N
I2C_CLK
VDD_CORE
VSS_PCIE VDD_PCIE
SB_RX3P
VSS
TXOUT_U0
N
VSS
VSS_PCIE GPP_TX0P GPP_TX0N
SB_RX0P
DACHSYN
C
SYSRESET
#
VSS_PCIE GFX_TX3P VSS_PCIE GFX_RX1N GFX_RX1P VSS_PCIE
SB_TX1P
LTPVDD18 I2C_DATA DACVSYNC
VDD_PCIE
H
SB_TX1N
24
AVSSQ
VDD_PCIE VDD_PCIE
AU
23
AVDDQ
VSS
GFX_TX1N GFX_TX1P VSS_PCIE VSS_PCIE
THERMALD THERMALD
IODE_N
IODE_P
22
DACSDA
VSS
F
SB_TX2N VSS_PCIE VSS_PCIE
21
VDD_18CP
VDD_CORE CPU_SLP#
U
G
AT
20
MEMB_DQ MEMB_DM
15
2
VSS
MEMB_DQ MEMB_DQ
10
S2P
MEMA_DQ MEMA_DQ MEMA_DQ MEMA_DM MEMA_DQ MEMA_DQ MEMA_DQ
22
19
29
3
S3P
31
27
MEMA_DQ
S2N
VSS
MEMA_DQ
18
MEMA_DQ MEMA_DQ MEMA_DM
11
21
2
VSS
23
28
24
10
VSS
11
12
VSS
13
14
15
VSS
16
25
S3N
26
17
VSS
VSS
MEMB_CK MEMB_CK
E3
E0
VSS
MEMA_DQ
30
VSS
VSS
VDD_MEM
18
19
20
21
22
MEMB_DM
3
VSS
MEMB_CK
MEMB_BA2
E1
23
24
Figure 3-1 Pin Assignment Top View (Left)
RS600 Databook
3-2
CPU Interface
CRT and TV Interface
GND
External graphics Interface
Others
Clock Interfaces
Integrated DVI/HDMI Interface
Memory Interface (Channel A)
General Purpose External Device Interface
Memory Interface (Channel B)
Power Pins
25
26
27
DACRSET
VSSLT
TXCLK_LN
TMDS_HPD TXCLK_LP
TXOUT_U0
P
VSS
28
29
TXOUT_L0 TXOUT_L2
P
P
30
VSSLT
31
TXOUT_L0 TXOUT_L2 TXOUT_L1
N
N
P
TXOUT_L3 TXOUT_L3
P
N
VSSLT
32
33
CPU_COM
CPU_VREF VDD_CPU
P_N
VSS
34
35
VSS
36
37
38
39
CPU_DBI3# CPU_D60# CPU_D57#
CPU_COM
VDD_CPU CPU_D62#
P_P
41
42
44
45
CPU_D49#
CPU_DSTB
3N#
CPU_D58# CPU_D48# CPU_D61#
CPU_D56#
CPU_DSTB
CPU_D51# CPU_D52#
3P#
VSS
CPU_D21#
VSS
VSS
CPU_D43#
VSS
CPU_D35#
VSS
CPU_D30#
VSS
VSS
VSS
CPU_D23#
CPU_D22#
VSS
CPU_D44#
VSS
CPU_D39#
VSS
CPU_D31#
CPU_D26#
CPU_D24#
CPU_D16#
CPU_D18#
CPU_D47#
CPU_D41#
CPU_D33#
CPU_D28#
CPU_D25#
VSS
CPU_D19#
CPU_DSTB
CPU_D38#
2P#
43
CPU_D55# CPU_D53# CPU_D14# CPU_D9#
CPU_D54#
CPU_D59#
TXOUT_L1
VDD_CPU VDD_CPU VDD_CPU CPU_D63#
N
40
VSS
VSS
VSS
CPU_DSTB
VDD_CPU
2N#
VDD_CPU
VSS
VSS
CPU_D29#
CPU_D46#
CPU_D45#
VDD_CPU CPU_DBI2#
CPU_D32#
CPU_D27#
CPU_DSTB
1P#
CPU_DSTB
1N#
CPU_CPUR
ST#
CPU_D42#
VDD_CPU CPU_D37#
CPU_D34#
VSS
CPU_DBI1#
VSS
CPU_D40#
CPU_D36# VDD_CPU
VDD_CPU
VDD_CPU
VSS
VDD_18CP
U
VDD_CPU
VDD_CPU VDD_CPU
VDD_CPU
VDD_CPU
CPU_D50# CPU_D13# CPU_D15#
VSS
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_CPU VDD_CPU
VSS
VDD_COR
E
VSS
VDD_COR
E
VDD_COR VDD_18CP
VDD_CPU
E
U
IOPLLVDD1
CPU_A20#
2
VDD_COR VDD_COR VDD_18CP
VDD_CPU
E
E
U
IOPLLVSS VDD_CPU
VSS
CPU_D10# CPU_D12#
D
E
VSS
CPU_D7#
F
CPU_D3#
CPU_D5#
CPU_D1#
G
CPU_D0#
VSS
H
CPU_REQ3
#
VSS
CPU_BPRI
CPU_D4#
#
VSS
CPU_REQ4
#
CPU_A4#
VSS
CPU_REQ2
CPU_DEFE
CPU_D2#
CPU_HIT#
#
R#
CPU_RS0#
L
CPU_A7#
CPU_REQ1
#
VSS
CPU_A3#
VSS
CPU_A5#
CPU_LOCK CPU_DBSY
CPU_BNR#
#
#
M
CPU_A10#
CPU_REQ0
#
VSS
CPU_A8#
VSS
CPU_A11#
CPU_DRDY CPU_HITM VDD_CPU_
#
#
PACKAGE
P
CPU_TRDY
CPU_ADS# CPU_RS1#
#
R
J
VSS
CPU_A6#
CPU_ADST
CPU_A9#
B0#
VSS
VSS
CPU_BR0#
CPU_A23#
VSS
VDD_CPU CPU_A13#
CPU_A14#
CPU_A16#
VSS
VSS
CPU_A15# CPU_A18#
CPU_A19#
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VDD_COR
E
VSS
VSS
T
U
MEMA_DQ MEMA_DQ
62
58
CPU_A25#
VSS
CPU_A21#
VDD_CPU VDD_CPU
VSS
CPU_A17#
VSS
VDD_18ME
CPU_A27#
M
CPU_A28#
VSS
CPU_A31#
VDD_MEM VDD_MEM
VDD_MEM
VSS
VSS
CPU_A24#
VSS
CPU_A26# CPU_A22#
VSS
CPU_A30# CPU_A33# CPU_A32#
VSS
VSS
VSS
VSS
VSS
VSS
VDD_COR VDD_COR VDD_18ME
VDD_MEM
E
E
M
VDD_MEM
MEMB_DQ
60
VSS
VSS
VSS
VDD_MEM
VSS
MEMB_DQ
S7P
MEMB_DQ MEMB_DQ
58
63
MEMB_DQ
S7N
VSS
VDD_MEM VDD_MEM
MEMB_DQ MEMB_DQ
56
62
VDD_MEM VDD_MEM
VDD_MEM
MEMB_DM MEMB_DQ
7
61
VSS
VDD_MEM
VDD_18ME
M
VDD_MEM VDD_MEM
VDD_MEM
VDD_MEM
MEMB_CK3
N
VDD_MEM
VDD_MEM
MEMB_CK0
P
MEMB_DQ
37
VDD_MEM
MEMB_DQ
50
MEMB_DQ
55
VSS
MEMA_DM
6
MEMA_DQ
49
AD
53
48
52
AE
VSS
VSS
AF
MEMA_DQ MEMA_DM
S5N
5
AH
VSS
41
40
45
MEMB_DQ MEMA_DQ MEMA_DQ
57
44
35
VSS
VSS
AL
MEMA_DQ MEMA_DQ
S4P
S4N
AM
MEMA_DM MEMA_DQ MEMA_DQ
4
33
37
AN
VSS
MEMB_DQ MEMA_DQ MEMA_DQ
S6P
32
36
VSS
AP
AR
MEMB_DM MEMB_DQ MEMB_DQ
6
51
49
VDD_MEM
MEMB_CK3
P
VDD_MEM
MEMB_DQ
33
VDD_MEM
VDD_MEM
MEMB_DQ
S3N
MEMB_DQ
S3P
VSS
MEMB_DQ
32
VSS
MEMB_DQ
34
VSS
MEMB_DM
5
VSS
VSS
MEMB_DQ
36
VSS
MEMB_DQ
39
VSS
MEMB_DQ
41
MEMB_DQ
42
MEMB_DQ
54
VSS
MEMB_DQ MEM_COM MEM_COM MEMA_OD
S6N
PN
PP
T3
MEMB_DQ MEMB_DQ
53
48
VSS
VSS
MEMA_OD
T1
MEMA_CK2 MEMA_CK2
MEMA_CS1 MEMA_OD
MEMA_A13
P
N
#
T2
MEMB_DQ
31
MEMB_DQ
30
VSS
VSS
MEMB_DQ
26
MEMB_A7 MEMB_A6 MEMB_A3
MEMB_A9 MEMB_A8 MEMB_A4
MEMB_A11 VDD_MEM MEMB_A5
25
26
27
MEMA_CK0 MEMA_CK0
N
P
VSS
VSS
MEMB_DQ
52
MEMA_CK3 MEMA_CK3
N
P
MEMB_DM
4
MEMB_DQ
38
MEMB_DQ
35
MEMB_DQ
44
MEMB_DQ
46
VSS
VSS
MEMB_DQ
45
MEMB_DQ
S5P
MEMB_DQ
43
MEMB_DQ
S4P
MEMB_DQ
S4N
VSS
MEMA_CK5 MEMA_CK5 MEMA_OD MEMA_CA
N
P
T0
S#
VSS
MEMA_CK
MEMA_A14 MEMA_A12
E0
VSS
MEMA_A6 MEMA_A4
MEMA_CK MEMA_CK
VDD_MEM MEMB_A1 MEMA_A9 MEMA_A8 VDD_MEM
E1
E2
28
29
30
31
32
33
34
MEMB_DQ
40
MEMB_DQ
S5N
MEMB_CS2
#
MEMB_WE
#
MEMA_A1
MEMB_RA
S#
MEMB_CS0 MEMB_CS1
#
#
VSS
MEMA_A2 MEMB_A10 MEMB_BA0
35
MEMB_CK2 MEMB_CK2 MEMB_OD
N
P
T3
MEMB_A0 MEMB_BA1
VSS
MEMA_CK
MEMB_A2 MEMA_BA2 MEMA_A11 MEMA_A7 MEMA_A5 MEMA_A3
E3
36
37
38
AT
AU
AV
AW
VSS
AY
MEMA_WE MEMA_CS0 MEMA_CS2
#
#
#
MEMB_DQ
27
AJ
AK
34
39
38
MEMA_CS3
#
MEMB_CK0
VDD_MEM
N
AB
AC
AG
VDD_MEM VDD_MEM VDD_MEM VDD_MEM VDD_MEM
VSS
Y
AA
MEMB_DQ MEMA_DQ MEMA_DQ MEMA_DQ
59
42
46
S5P
VDD_COR VDD_COR VDD_COR VDD_18ME
VDD_MEM
E
E
E
M
VDD_18ME VDD_18ME VDD_18ME VDD_18ME VDD_18ME
M
M
M
M
M
VSS
W
54
S6P
S6N
VSS
VDD_MEM VDD_MEM
V
MEMA_DQ MEMA_DQ
57
61
MEMA_DQ MEMA_DQ
43
47
VDD_MEM VDD_MEM
VSS
CPU_ADST MEMA_DQ MEMA_DQ MEMA_DQ
B1#
56
60
51
MEMA_DQ MEMA_DQ
50
55
VDD_COR VDD_18ME
VDD_MEM
E
M
K
MEMA_DQ CPU_RESE MEMA_DQ
63
RVED
59
VSS
IOPLLVDD1
CPU_A29#
8
VDD_MEM VDD_MEM
VDD_COR
E
VSS
MEMA_DM MEMA_DQ MEMA_DQ
7
S7P
S7N
VSS
VSS
VDD_COR
E
C
CPU_D20#
VDD_COR VDD_COR VDD_COR VDD_18CP
VDD_CPU
E
E
E
U
VDD_COR
E
B
VSS
CPU_DSTB CPU_DSTB
CPU_DBI0#
0P#
0N#
CPU_D17# CPU_D6#
VDD_CPU VDD_CPU VDD_CPU VDD_CPU VDD_CPU
VSS
A
N
VDD_CPU CPU_A12#
VDD_COR
E
47
VSS
CPU_D11# CPU_D8#
CPU_RS2#
VDD_18CP VDD_18CP VDD_18CP VDD_18CP
VDD_CPU
U
U
U
U
46
VSS
VDD_MEM
39
40
MEMB_DQ
47
VSS
MEMA_A0
VSS
VSS
VSS
MEMB_CA
MEMB_A13
S#
41
42
VSS
43
BA
MEMB_OD
T2
BB
MEMB_OD MEMB_OD MEMA_RA
T1
T0
S#
BC
MEMB_CK5
VDD_MEM MEMA_BA0 MEMA_BA1
N
BD
MEMB_CK5
VDD_MEM MEMA_A10
P
BE
VSS
VSS
VSS
MEMB_CS3
VDD_MEM
#
BF
MEM_VRE
VDD_MEM
F
44
45
BG
46
47
Figure 3-2 Pin Assignment Top View (Right)
CPU Interface
GND
External graphics Interface
Others
Clock Interfaces
Memory Interface (Channel A)
General Purpose External Device Interface
Memory Interface (Channel B)
Power Pins
RS600 Databook
3-3
RS600 Interface Block Diagram
3.2
RS600 Interface Block Diagram
Figure 3-3 shows the different interfaces on the RS600. Interface names in blue are hyperlinks to the corresponding
sections in this chapter.
CPU_A[33:3]#
CPU_ADS#
CPU_ADSTB[1:0]#
CPU_BNR#
CPU_BR0#
CPU_BPRI#
CPU_CPURST#
CPU_D[63:0]#
CPU_DBI[3:0]#
CPU_DBSY#
CPU_DEFER#
CPU_DRDY#
PCI-E
External
Graphics/
TMDS/
SDVO
Interface
PCI-E
Interface
for General
Purpose
External
Devices
CPU_EDRDY#
CPU_HIT#
CPU_HITM#
CPU_LOCK#
CPU_REQ[4:0]#
CPU_RESERVED
CPU_RS[2:0]#
CPU_SLP#
CPU_TRDY#
CPU_CLKP
CPU_CLKN
TXOUT_U0N, TXOUT_U0P
TXCLK_UN, TXCLK_UP
TXOUT_L0N, TXOUT_L0P
TXCLK_LN, TXCLK_LP
SB_TX[3:0]P, SB_TX[3:0]N
SB_RX[3:0]P, SB_RX[3:0]N
SYSRESET#
POWERGOOD
SUS_STAT#
CPU_VREF
MEM_VREF
TESTMODE
THERMALDIDOE_N,
THERMALDIODE_P
DDC_DATA
I2C_CLK
I2C_DATA
STRP_DATA
TMDS_HPD
GPIO[10:8]
VDD_CPU_PACKAGE
CPU_COMP_P, CPU_COMP_N
MEM_COMPP, MEM_COMPN
GFX_REFCLK
CPU
Interface
CPU_DSTBN[3:0]#, CPU_DSTBP[3:0]#
MEMA_A[14:0], MEMB_A[14:0]
MEMA_BA[2:0], MEMB_BA[2:0]
MEMA_RAS#, MEMB_RAS#
MEMA_CAS#, MEMB_CAS#
MEMA_WE#, MEMB_WE#
MEMA_CKE[3:0], MEMB_CKE[3:0]
MEMA_CK[5:0]P, MEMB_CK[5:0]P
MEMA_CK[5:0]N, MEMB_CK[5:0]N
MEMA_CS[3:0]#, MEMB_CS[3:0]#
MEMA_DQ[63:0], MEMB_DQ[63:0]
MEMA_DM[7:0], MEMB_DM[7:0]
MEMA_DQS[7:0]P, MEMB_DQS[7:0]P
MEMA_DQS[7:0]N, MEMB_DQS[7:0]N
MEMA_ODT[3:0], MEMB_ODT[3:0]
GFX_TX[15:0]P, GFX_TX[15:0]N
GFX_RX[15:0]P, GFX_RX[15:0]N
Misc. PCI-E
Signals
DDR2/DDR3
Memory
Interface
(2 Channels)
Integrated
DVI/HDMI
Interface
A-Link Express
II Interface
CRT and
TV-out
Interface
Clock
Interface
GPP_TX[3:0]P, GPP_TX[3:0]N
GPP_RX[3:0]P, GPP_RX[3:0]N
GPPSB_REFCLKP, GPP_SBREFCLKN
PCE_CALI
PCE_CALRP
PCE_CALRN
RED
GREEN
BLUE
DACVSYNC
DACHSYNC
DACSDA
C
Y
COMP
DACRSET
OSCIN
VDD_18CPU
VDD_18MEM
VDD_CORE
VDD_CPU
VDD_MEM
Power
Power
Management
Interface
Reference
Voltages
Misc. Signals
Grounds
Compensation
VDD_PCIE
VDD_PLLPCIE
VDDR3
IOPLLVDD18
IOPLLVDD12
AVDD
AVDDDI
AVDDQ
PLLVDD18
PLLVDD12
VDDLT18
VDDLT33
LTPVDD18
VSS
VSS_PCIE
VSS_PLLPCIE
VSSLT
LTPVSS18
AVSSN
AVSSQ
AVSSDI
PLLVSS
IOPLLVSS
Figure 3-3 RS600 Interface Block Diagram
RS600 Databook
3-4
CPU Interface
3.3
CPU Interface
Table 3-1 CPU Interface
Pin Name
Type
Power
Domain
Ground
Domain
Functional Description
CPU_A[33:3]#
I/O GTL+
VDD_CPU
VSS
Address Bus: A[33:3]# connect to the processor address bus. During host
cycles, the A[33:3]# are inputs. RS600 drives A[33:3]# during snoop cycles
on behalf of PCI-E initiators and during deferred reply transactions. Address
signals are source synchronous signals latched into receiving buffers by
CPU_ADSTB[1:0]#. The address signals are running at 2X rate.
Note that the address signals are inverted on the CPU bus.
CPU_ADS#
I/O GTL+
VDD_CPU
VSS
Address Strobe: The CPU bus owner asserts ADS# to indicate the request
phase of a transaction.
CPU_ADSTB[1:0]# I/O GTL+
VDD_CPU
VSS
Address strobes: Signals are used to latch the CPU_A[31:3]# address bus
and CPU_REQ[4:0]# request bus on the rising and falling edges. Strobes are
associated with signals as shown in Table 3-2.
VSS
Block Next Request: This signal is used to block the current request bus
owner from issuing a new request. It is also used to block requests during
CPU I/O calibration. This signal is used to dynamically control the CPU bus
pipeline depth
CPU_BNR#
I/O GTL+
VDD_CPU
CPU_BPRI#
O GTL+
VDD_CPU
VSS
Priority Agent Bus Request: The RS600 system logic is the only Priority Agent
on the CPU bus. This signal is used to obtain the ownership of the address
bus. Unless the LOCK# signal was asserted, BPRI# has priority over
symmetric bus requests and causes the current symmetric owner to stop
issuing new transactions.
CPU_BR0#
O GTL+
VDD_CPU
VSS
Bus Request
CPU_COMP_P
CPU_COMP_N
Other
VDD_CPU
VSS
Compensation pins for matching impedance of the address and data buses to
the motherboard bus traces (for push pull operation only). CPU_COMP_P is
connected to ground through a resistor and CPU_COMP_N is connected to
CPU I/O power through a resistor. Please refer to the RS600/RC610-Series
IGP Schematic Review Checklist for the recommended resistor values for
different CPUs.
CPU_CPURST#
O
VDD_CPU
VSS
CPU Reset. It is asserted by the RS600 following a de-assertion of
POWERGOOD or an assertion of SYSRESET#.
VSS
Host Data: These signals are connected to the CPU data bus. Data signals
are "quad-pumped" signals and will be driven four times in one clock period.
The falling edges of the CPU_DSTBN[3:0]# and CPU_DSTBP[3:0]# are used
to latch data. Table 3-3 shows how signals and strobes are grouped. Note
that the data signals are inverted on the CPU bus.
CPU_D[63:0]#
I/O GTL+
VDD_CPU
CPU_DBI[3:0]#
I/O GTL+
VDD_CPU
VSS
Data Bus Inversion. These signals indicate the polarity of the CPU_D[63:0]
signals. The bus agent will invert the data if more than half of the bits within the
covered group would change level in the coming cycle. Data bus inversion
signals are "quad-pumped”, source synchronous signals. Refer to the
description of CPU_D[63:0]# for more details.
CPU_DBSY#
I/O GTL+
VDD_CPU
VSS
Data Bus Busy: This signal is used by the data bus owner to hold the data bus
for transfers requiring more than one cycle.
CPU_DEFER#
O GTL+
VDD_CPU
VSS
Defer: The RS600 chip will generate a deferred response. The RS600 system
logic will also use the DEFER# signal to indicate a retry response on the CPU
bus.
CPU_DRDY#
I/O GTL+
VDD_CPU
VSS
Data Ready: Asserted for each cycle of data transfer to indicate that data on
the data bus is valid.
CPU_DSTBN[3:0]# I/O GTL+
VDD_CPU
VSS
Negative Data Strobes. These signals are used as strobe signals to latch
CPU_D host data bus as well as CPU_DBI data inversion signals. Refer to the
CPU_DSTBP[3:0]# I/O GTL+
VDD_CPU
VSS
Positive Data Strobes. These signals are used as strobe signals to latch
CPU_D host data bus as well as CPU_DBI data inversion signals. Refer to the
CPU_EDRDY#
VDD_CPU
VSS
Early Data Ready. This signal is used to notify the CPU that data will
be ready in the next clock.
O GTL+
RS600 Databook
3-5
CPU Interface
Table 3-1 CPU Interface
Pin Name
CPU_HIT#
CPU_HITM#
CPU_LOCK#
(Continued)
Power
Domain
Ground
Domain
VDD_CPU
VSS
Hit: Indicates that a caching agent holds an unmodified version of the
requested line. Also, the target may extend the snoop window by driving HIT#
in conjunction with HITM#.
VSS
Hit Modified: When asserted, this signal indicates that a caching agent holds a
modified version of the requested line and that this agent assumes
responsibility for providing the line. It is also driven in conjunction with HIT# to
extend the snoop window.
VSS
Host Lock: The signal provides a mechanism to ensure that cycles on the
Host bus are atomic. All cycles initiated while LOCK# is asserted are
guaranteed to be atomic. This implies that no PCI or AGP snoopable access
to DRAM is allowed when LOCK# signal is asserted by the CPU.
Type
I GTL+
I GTL+
I GTL+
VDD_CPU
VDD_CPU
CPU_REQ[4:0]#
I/O GTL+
VDD_CPU
VSS
Request Command: This signal is asserted during both clocks of the request
phase. Request command signals are source synchronous to the
CPU_ADSTB0#, meaning that they are running at 2X rate. In the first half of a
clock, the signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second half, the signals carry additional
information to define the complete transaction type.
CPU_RS[2:0]#
I/O GTL+
VDD_CPU
VSS
Response Signals: These signals indicate the type of response as described
in Table 3-4.
CPU_SLP#
I/O GTL+
VDD_CPU
VSS
Sleep. The RS600 uses the signal to put the CPU into the C3 state during C2
popdown.
CPU_TRDY#
O GTL+
VDD_CPU
VSS
Host Target Ready: When asserted, this signal indicates that the target of the
CPU bus transaction is able to enter the data transfer phase.
CPU_VREF
Power
–
–
CPU interface voltage reference. Voltage level for this pin should be set to
0.67 x VTT_CPU, where VTT_CPU is the CPU’s I/O voltage.
CPU_RESERVED
O
VDD_CPU
VSS
Reserved pin for achieving forward compatibility with the next generation of
Intel CPUs.
CPU_CLKP,
CPU_CLKN
I
IOPLLVDD12
IOPLLVSS
CPU Front Side Bus Clock Differential Pair. This pair is connected to the
external clock generator on the motherboard.
Table 3-2 Address Signals and Associated Strobes
Signals
Associated Strobes
CPU_A[16:3]#, CPU_REQ[4:0]#, CPU_ADSTB0#
CPU_RESERVED
CPU_A[33:17]#
CPU_ADSTB1#
Table 3-3 Grouping of CPU_D[63:0]# Signals
Data Group
Associated Strobes
Associated Bus Inversion Signal
CPU_D[15:0]#
CPU_DSTBN0#
CPU_DSTBP0#
CPU_DBI0#
CPU_D[31:16]#
CPU_DSTBN1#
CPU_DSTBP1#
CPU_DBI1#
CPU_D[47:32]#
CPU_DSTBN2#
CPU_DSTBP2#
CPU_DBI2#
CPU_D[63:48]#
CPU_DSTBN3#
CPU_DSTBP3#
CPU_DBI3#
Table 3-4 Response Signals
CPU_RS[2:0]
Response Type
000
Idle state
001
Retry response
010
Deferred response
011
Reserved
100
Hard Failure
RS600 Databook
3-6
DDR2/DDR3 Memory Interface
Table 3-4 Response Signals
3.4
(Continued)
CPU_RS[2:0]
Response Type
101
No data response
110
Implicit Writeback
111
Normal data response
DDR2/DDR3 Memory Interface
Table 3-5 DDR2/DDR3 Memory Interface
Pin Name
MEMA_A[14:0]
MEMB_A[14:0]
Type
O
Power
Domain
Ground
Domain
Integrated
Termination Functional Description
VDD_MEM
VSS
None
VDD_MEM
VSS
None
MEMA_BA[2:0]
O
VDD_MEM
VSS
None
MEMB_BA[2:0]
O
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
VDD_MEM
VSS
None
MEMA_RAS#
MEMB_RAS#
MEMA_CAS#
MEMB_CAS#
MEMA_WE#
MEMB_WE#
MEMA_CKE[3:0]
MEMB_CKE[3:0]
MEMA_CK[5:0]P
MEMB_CK[5:0]P
MEMA_CK[5:0]N
MEMB_CK[5:0]N
MEMA_CS[3:0]#
MEMB_CS[3:0]#
MEMA_DQ[63:0]
MEMB_DQ[63:0]
MEMA_DM[7:0]
MEMB_DM[7:0]
O
O
O
O
O
O
O
I/O
I/O
MEMA_DQS[7:0]P
MEMB_DQS[7:0]P
I/O
MEMA_DQS[7:0]N
MEMB_DQS[7:0]N
MEMA_ODT[3:0]
MEMB_ODT[3:0]
I/O
O
Channel A/B Address Bus . These are the multiplexed row
and column address bits for DDR2/DDR3 SDRAMs.
Channel A/B Bank Address Select
Channel A/B RAS#
Channel A/B CAS#
Channel A/B WE#
Channel A/B Clock Enable
Channel A/B Differential Positive Clock
Channel A/B Differential Negative Clock
Channel A/B Chip Selects
Channel A/B Data Bus
Channel A/B. data masks for each byte during memory write
cycles
Channel A/B DDR2/DDR3 Differential Positive Data Strobe.
These are bi-directional data strobes for latching read/write
data.
Channel A/B DDR2/DDR3 Differential Negative Data Strobe.
These are bi-directional data strobes for latching read/write
data.
On-die Termination
MEM_COMPP,
MEM_COMPN
Analog
–
VSS
None
DDR2 Memory interface compensation pins for N and P
channel devices. Connect through resistors to VDD_MEM
and ground respectively (refer to the reference schematics
for the proper resistor values).
MEM_VREF
Analog
–
VSS
None
Reference voltage. It supplies the threshold value for
distinguishing between “1” and “0” on a memory signal.
Typical value is 0.5* VDD_MEM.
RS600 Databook
3-7
PCI Express Interfaces
3.5
3.5.1
PCI Express Interfaces
1 x16 Lane Interface for External Graphics
The external graphics interface is also multiplexed with the SDVO interface for external displays and the TMDS
interface. See section 3.10, “SDVO Interface for External Displays,” on page 3- 11 and section 3.9, “TMDS Interface Multiplexed on
the PCI-E Graphics Lanes,” on page 3- 11 for details.
Table 3-6 1 x16 Lane PCI Express Interface for External Graphics
Pin Name
3.5.2
Type
Power
Domain
Ground
Domain
Integrated
GFX_TX[15:0]P,
GFX_TX[15:0]N
O
VDD_PCIE VSS_PCIE
50Ω between
complements
Transmit Data Differential Pairs. Connect to external connector for
an external graphics card on the motherboard (if implemented).
GFX_RX[15:0]P,
GFX_RX[15:0]N
I
VDD_PCIE VSS_PCIE
50Ω between
complements
Receive Data Differential Pairs. Connect to external connector for an
external graphics card on the motherboard (if implemented).
GFX_REFCLKP,
GFX_REFCLKN
I/O
VDD_PCIE VSS_PCIE
50Ω between
complements
Clock Differential Pairs. Connect to external clock generator when
an external graphics card is implemented.
1 x4 Lane A-Link Express II to IXP
The width of the A-Link Express II interface can be reduced from four lanes to two, with the extra two lanes configurable
to become general purpose links.
Table 3-7 1 x4 Lane A-Link Express II Interface for IXP
Pin Name
Type
SB_TX[3:2]P,
SB_TX[3:2]N
Ground
Domain
Integrated
VDD_PCIE VSS_PCIE
Transmit Data Differential Pairs. Connect to the corresponding
50Ω between Receive Data Differential pairs on the IXP.
complements Configurable to become GPP_TX[5:4]P/N to support general
purpose external devices.
SB_RX[3:2]P,
SB_RX[3:2]N
I
VDD_PCIE VSS_PCIE
Receive Data Differential Pairs. Connect to the corresponding
50Ω between Transmit Data Differential pairs on the IXP.
complements Configurable to become GPP_RX[5:4]P/N to support general
purpose external devices.
SB_TX[1:0]P,
SB_TX[1:0]N
O
VDD_PCIE VSS_PCIE
50Ω between Transmit Data Differential Pairs. Connect to the corresponding
complements Receive Data Differential pairs on the IXP.
SB_RX[1:0]P,
SB_RX[1:0]N
I
VDD_PCIE VSS_PCIE
50Ω between Receive Data Differential Pairs. Connect to the corresponding
complements Transmit Data Differential pairs on the IXP.
I/O
VDD_PCIE VSS_PCIE
50Ω between Clock Differential Pair. Connect to an external clock generator on
complements the motherboard.
GPPSB_REFCLKP,
GPPSB_REFCLKN
3.5.3
O
Power
Domain
4 x1 Lane Interface for General Purpose External Devices
Table 3-8 4 x1 Lane PCI Express Interface for General Purpose External Devices
Pin Name
Type
Power
Domain
Ground
Domain
Integrated
GPP_TX[3:0]P,
GPP_TX[3:0]N
O
VDD_PCIE VSS_PCIE
50Ω between Transmit Data Differential Pairs. Connect to external connectors on
complements the motherboard for add-in card or ExpressCard support.
GPP_RX[3:0]P,
GPP_RX[3:0]N
I
VDD_PCIE VSS_PCIE
50Ω between Receive Data Differential Pairs. Connect to external connectors on
complements the motherboard for add-in card or ExpressCard support.
RS600 Databook
3-8
Clock Interface
3.5.4
Miscellaneous PCI Express Signals
Table 3-9 Miscellaneous PCI Express Signals
3.6
Power
Domain
Ground
Domain
Pin Name
Type
PCE_CALI
Other
VDD_PCIE VSS_PCIE
Current Biasing. Connect to VSS_PCIE on the motherboard with an external resistor
of an appropriate value.
PCE_CALRN
Other
VDD_PCIE VSS_PCIE
RX Impedance Calibration. Connect to VDD_PCIE on the motherboard with an
external resistor of an appropriate value.
PCE_CALRP
Other
VDD_PCIE VSS_PCIE
TX Impedance Calibration. Connect to ground on the motherboard with an external
resistor of an appropriate value.
Clock Interface
Table 3-10 Clock Interface
Pin Name
OSCIN
3.7
Type
Power
Domain
I
VDDR3
Ground Integrated
Domain Termination Functional Description
VSS
Disabled
14.3181818 MHz Reference clock input from the External Clock chip
(3.3 volt signaling)
Table 3-11 CRT and TV Interface
Pin Name
Type
Power Ground Integrated
Domain Domain Termination Functional Description
RED
A-O
AVDD
AVSSN
–
Red for CRT monitor output, or Pr for component video TV output
GREEN
A-O
AVDD
AVSSN
–
Green for CRT monitor output, or Y for component video TV output
BLUE
A-O
AVDD
AVSSN
–
Blue for CRT monitor output, or Pb for component video TV output
Y
A-O
AVDD
AVSSN
–
SVID luminance output for TV out, or Y for component video TV output
C
A-O
AVDD
AVSSN
–
SVID chrominance output for TV out, or Pr for component video TV
output
COMP
A-O
AVDD
AVSSN
–
Composite video TV output, or Pb for component video TV output
DACHSYNC
A-O
VDDR3
VSS
50kΩ
Display Horizontal Sync. It is also used as a strap pin (see Table 3-19
programmable:
for details).
PU/PD/none
DACVSYNC
A-O
VDDR3
VSS
50kΩ
Display Vertical Sync. It is also used as a strap pin (see Table 3-19
programmable:
for details).
PU/PD/none
Other
N/A
AVSSQ
I/O
VDDR3
VSS
DACRSET
DACSDA
–
DAC internal reference to set full scale DAC current through 1%
resistor to AVSS
50kΩ
I2C data for display (to video monitor). It is also used as a strap pin
programmable:
(see Table 3-19 for details).
PU/PD/none
RS600 Databook
3-9
3.8
Table 3-12 Integrated DVI/HDMI Interface
Pin Name
DVI/HDMI
Functional
Name
Type
Power
Domain
TXOUT_L0N
TX0M
O
VDDLT33
VDDLT18
VSSLT
None
DVI/HDMI data channel 0 (-)
TXOUT_L0P
TX0P
O
VDDLT33
VDDLT18
VSSLT
None
DVI/HDMI data channel 0 (+)
TXOUT_L1N
TX1M
O
VDDLT33
VDDLT18
VSSLT
None
TXOUT_L1P
TX1P
O
VDDLT33
VDDLT18
VSSLT
None
TXOUT_L2N
TX2M
O
VDDLT33
VDDLT18
VSSLT
None
TXOUT_L2P
TX2P
O
VDDLT33
VDDLT18
VSSLT
None
TXOUT_L3N
TX3M
O
VDDLT33
VDDLT18
VSSLT
None
DVI data channel 3 (-). The channel is only used in
DVI dual-link mode and is not used for HDMI
support.
TXOUT_L3P
TX3P
O
VDDLT33
VDDLT18
VSSLT
None
DVI data channel 3 (+). The channel is only used in
support.
TXOUT_U0N
TX4M
O
VDDLT33
VDDLT18
VSSLT
None
support.
TXOUT_U0P
TX4P
O
VDDLT33
VDDLT18
VSSLT
None
DVI data channel 4 (+) The channel is only used in
support.
TXOUT_U1N
TX5M
O
VDDLT33
VDDLT18
VSSLT
None
support.
TXOUT_U1P
TX5P
O
VDDLT33
VDDLT18
VSSLT
None
DVI data channel 5 (+). The channel is only used in
support.
TXOUT_U2N
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
TXOUT_U2P
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
TXOUT_U3N
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
TXOUT_U3P
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
TXCLK_LN
TXCM
O
VDDLT33
VDDLT18
VSSLT
None
DVI/HDMI clock channel (-)
TXCLK_LP
TXCP
O
VDDLT33
VDDLT18
VSSLT
None
DVI/HDMI clock channel (+)
TXCLK_UN
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
TXCLK_UP
–
O
VDDLT33
VDDLT18
VSSLT
None
Unused
LTPVDD18
–
Pwr
–
–
–
Power for DVI/HDMI PLL macro (1.8V).
LTPVSS18
–
Gnd
–
–
–
DVI/HDMI PLL macro ground pin.
VDDLT18
–
Pwr
–
–
–
1.8V DVI/HDMI Digital Power, used for the digital
portions of the DVI/HDMI transmitter.
RS600 Databook
3-10
Ground Integrated
TMDS Interface Multiplexed on the PCI-E Graphics Lanes
Table 3-12 Integrated DVI/HDMI Interface (Continued)
DVI/HDMI
Functional
Name
Type
Power
Domain
VDDLT33
–
A-Pwr
–
–
–
3.3V DVI/HDMI Analog Power, used for the output
stage of the transmitter. This power supply needs to
be adequately filtered to prevent noise injection.
VSSLT
–
Gnd
–
–
–
DVI/HDMI IO ground pin.
Pin Name
Ground Integrated
* Note: The maximum pixel clock speed is to be qualified.
3.9
TMDS Interface Multiplexed on the PCI-E Graphics Lanes
The RS600 supports a TMDS interface, enabling HDMI, which is multiplexed with the PCI-E external graphics interface.
The TMDS interface is available only if no external graphics card is attached to the PCI-E graphics interface.
The interface cannot enable HDMI when the integrated DVI/HDMI interface is supporting HDMI, and vice versa.
Table 3-13, “TMDS Interface (Multiplexed with the PCI-E Graphics Interface),” shows the multiplexing relationships between
the PCI-E external graphics signals and the TMDS signals.
Table 3-13 TMDS Interface (Multiplexed with the PCI-E Graphics Interface)
3.10
Pin Name
Ball
Reference TMDS Function
GFX_TX0P
D2
TX0P - Red+
GFX_TX0N
E1
TX0M - Red-
GFX_TX1P
F2
TX1P - Green+
GFX_TX1N
F1
TX1M - Green -
GFX_TX2P
G2
TX2P - Blue+
GFX_TX2N
G1
TX2M - Blue-
GFX_TX3P
H2
TXCP - Clock+
GFX_TX3N
K1
TXCM - Clock-
SDVO Interface for External Displays
Note: The SDVO interface is multiplexed with the 1 x16 PCI-E external graphics interface. SDVO support is therefore
unavailable if an external graphics card or TMDS output is supported by that interface.
Table 3-14, “SDVO Interface for External Displays,” shows the multiplexing relationships between the PCI-E external
graphics signals and the SDVO signals.
Table 3-14 SDVO Interface for External Displays
Pin Name
Ball
SDVO
Reference Function
Control Signals
GFX_RX0P
C3
SDVO_TVClkIn+
GFX_RX0N
C2
SDVO_TVClkIn-
GFX_RX2P
K8
SDVO_Stall+
GFX_RX2N
K6
SDVO_Stall-
I2C_CLK
C21
SDVO_CtrlClk
DDC_DATA
B12
SDVO_CtrlData
GFX_TX0P
D2
SDVOB_Red+
GFX_TX0N
E1
SDVOB_Red-
First SDVO Device
RS600 Databook
3-11
Power Management Pins
Ball
SDVO
Reference Function
Pin Name
GFX_TX1P
F2
SDVOB_Green+
GFX_TX1N
F1
SDVOB_Green-
GFX_TX2P
G2
SDVOB_Blue+
GFX_TX2N
G1
SDVOB_Blue-
GFX_TX3P
H2
SDVOB_Clk+
GFX_TX3N
K1
SDVOB_Clk-
GFX_RX1P
H5
SDVOB_Int+
GFX_RX1N
H4
SDVOB_Int-
GFX_TX4P
L2
SDVOC_Red+
GFX_TX4N
L1
SDVOC_Red-
GFX_TX5P
M2
SDVOC_Green+
Second SDVO Device
3.11
GFX_TX5N
M1
SDVOC_Green-
GFX_TX6P
P2
SDVOC_Blue+
GFX_TX6N
R1
SDVOC_Blue-
GFX_TX7P
T2
SDVOC_Clk+
GFX_TX7N
T1
SDVOC_Clk-
GFX_RX5P
P9
SDVOC_Int+
GFX_RX5N
P8
SDVOC_Int-
Power Management Pins
Table 3-15 Power Management Pins
3.12
Pin Name
Type
Power
Domain
Ground
Domain
SYSRESET#
I
VDDR3
VSS
Global Hardware Reset. This signal comes from the south bridge.
SUS_STAT#
I
VDD_18MEM
VSS
Input from the south bridge whose assertion puts the RS600 into the S3 state.
POWERGOOD
I
VDDR3
VSS
Input from the motherboard signifying that the power to the RS600 is up and ready.
Signal High means all power planes are valid. It is not observed internally until it
has been high for more than 6 consecutive REFCLK cycles. The rising edge of this
signal is deglitched. The nominal input high voltage is 1.8V.
Miscellaneous Pins
Table 3-16 Miscellaneous Pins
Pin Name
Type
I2C_CLK
I/O
VDDR3
VSS
I2C interface clock signal. Can also be used simultaneously as
50kΩ
programmable: DDC interface clock for more than one display. It can also be used
PU/PD/none as GPIO.
I2C_DATA
I/O
VDDR3
VSS
50kΩ
programmable: I2C interface data signal. It can also be used as GPIO.
PU/PD/none
DDC_DATA
I/O
VDDR3
VSS
Pin for additional DDC Data Channel for displays. It makes use of
50kΩ
programmable: I2C_CLK to create an I2C interface. It is also used as a strap pin
PU/PD/none (see Table 3-19 for details).Can also be used as GPIO..
VSS
I2C interface data signal for external EEPROM based strap
50kΩ
loading. It is also used as a strap pin (see Table 3-19 for details).
programmable:
Can also be used as GPIO or NB Voltage throttling on mobile
PU/PD/none
platforms.
STRP_DATA
RS600 Databook
3-12
I/O
VDDR3
Power Pins
Table 3-16 Miscellaneous Pins (Continued)
Type
TESTMODE
I
VDDR3
VSS
–
When High, puts the RS600 in test mode and disables the RS600
from operating normally.
A-O
–
–
–
Diode connections to external SM Bus microcontroller for
monitoring IC thermal characteristics.
Other
VDD_CPU
VSS
–
The ball provides a power connection (via the package) to the
VDD_CPU plane for an area on the motherboard which may not
be connectable otherwise due to routing constraints.
TMDS_HPD
I
VDDR3
VSS
GPIO[10:8]
I/O
VDDR3
VSS
THERMALDIODE_P,
THERMALDIODE_N
VDD_CPU_PACKAGE
3.13
Pin Name
50kΩ
TMDS Hot Plug Detect. It monitors the hot-plug line for panel
programmable:
detection. It is a 3.3V CMOS compatible input.
PU/PD/none
–
General Purpose I/Os
Power Pins
Table 3-17 Power Pins
Pin Name
Pin Ball Reference
Voltage Count
Reference
Ground
Description
AVDD
3.3V
2
A17, B17
Dedicated power for the DAC. Effort should be made AVSSN
at the board level to provide as clean a power as
possible to this pin to avoid noise injection, which can
affect display quality. Adequate decoupling should
be provided between this pin and AVSS.
AVDDQ
1.8V
1
A23
DAC Bandgap Reference Voltage
AVDDDI
1.8V
1
B19
Dedicated digital power for the DAC
VDD_CORE
1.2V
78
Core power
A16, AB19, AB22, AB25,
AB28, AB30, AC18, AC20,
AC23, AC26, AC29, AE19,
AE22, AE25, AE28, AE30,
AF18, AF20, AF23, AF26,
AF29, AH19, AH22, AH25,
AH28, AH30, AJ17, AJ18,
AJ20, AJ23, AJ26, AJ29,
AJ31, AK17, AK19, AK22,
AK25, AK28, AK30, AK31,
AL17, AL18, AL19, AL29,
AL30, AL31, B16, C16, D16,
E16, F16, H16, ,J16, U17,
U18, U19, U29, U30, U31,
V17, V18, V20, V23, V26, V29,
V31, W17, W19, W22, W25,
W28, W30, W31, Y18, Y20,
Y23, Y26, Y29
VSS
VDD_18CPU
1.8V
20
A15, C15, E14, H14, K16, N24, I/O Transform Power for memory and CPU
N25, R17, R18, R19, T17, T18,
T19, T29, T30, T31, T32, U32,
V32, W32
VSS
VDD_PLLPCIE
1.2V
3
M10, P12, P13
PCI Express interface PLL power
VSS_PLLPCIE
VDD_PCIE
1.2V
48
A10, A8, AA12, AA13, AC13,
AD13, AE13, AG13, AJ13,
AJ15, AK13, AK15, AL15,
AM12, AM13, AM15, AN15,
AP1, AP12, AP13, AP3, B10,
B8, C10, C7, C8, D8 ,E8, F8,
H10, H8, J10, K12, K14, K9,
M12, M14, N14, R15, T15,
U15, V1, V13, V15, V3, W12,
W13, W15
PCI Express interface output driver I/O power
VSS_PCIE
RS600 Databook
3-13
AVSSQ
AVSSDI
Power Pins
Table 3-17 Power Pins
Pin Name
(Continued)
Pin Ball Reference
Voltage Count
Reference
Ground
Description
1.8V
29
Isolated IO power for memory interface
AD35, AJ16, AJ32, AK16,
AK32, AL16, AL32, AM16,
AM17, AM18, AM19, AM29,
AM30, AM31, AM32, AM33,
AN16, AR27, B15, D14, F14,
J14, M16, N16, R16, T16, U16,
V16, W16
VSS
VDD_MEM
1.5/1.8V
64
AE35, ,AE36, AE38, AG35,
AG36, AG38, AG39, AJ33,
AJ35, AJ36, AK33, AK35,
AK38, AL33, AM35, AM36,
AN17, AN18, AN19, AN29,
AN30, AN31, AN32, AN33,
AP35, AP36, AP38, AR14,
AR16, AR18, AR19, AR21,
AR23, AR24, AR25, AR29,
AR30, AR32, AR34, AT14,
AT16, AT19, AT21, AT23,
AT27, AT29, AT34, AT36,
AV18, AV21, AV24, AV27,
AV30, AV34, AV36, BD45,
BE45, BF46, BG22, BG26,
BG30, BG34, BG40, BG45
Isolated IO power for memory interface
VSS
VDD_CPU
Variable
33
A33, AC35, AC36, AR30, B33, IO power for CPU interface
BF46, C31, C32, C33, H30,
H32, J29, K29, M30, M32,
M34, N27, N29, N30, N32,
N34, P35, R29, R30, R31, R32,
R33, T33, T35, T36, U33, V33,
W33, W36, W38
VSS
VDD_CPU_PA
CKAGE
Variable
1
P47
The ball provides a power connection (via the
package) to the VDD_CPU plane for an area which
cannot be connected otherwise due to routing
constraints on a 4-layer motherboard.
VSS
VDDR3
3.3V
2
A18,B18
GPIO/clock 3.3V IO power
VSS
LTPVDD18
1.8V
1
B21
Power for PLL
LTPVSS18
VDDLT18
1.8V
2
H24, J24
1.8V Digital Power
VSSLT
VDD_18MEM
VDDLT33
3.3V
2
H23, J23
3.3V Analog Power
VSSLT
PLLVDD12
1.2V
1
A12
Power for system PLL
PLLVSS
PLLVDD18
1.8V
1
A14
Power for system PLL
PLLVSS
IOPLLVDD12
1.2V
1
V35
Power for CPU/memory interface PLL
IOPLLVSS
IOPLLVDD18
1.8V
1
AA35
Power for CPU/memory interface PLL
IOPLLVSS
Total Power Pin Count
RS600 Databook
3-14
291
Ground Pins
3.14
Ground Pins
Table 3-18 Ground Pins
Pin Name
Pin Count
Ball Reference
Description
AVSSN
2
M23, N23
Dedicated analog ground for the DAC
AVSSQ
1
A24
Dedicated ground for the Band Gap Reference. Effort should
be made at the board level to provide as clean a ground as
possible to this pin to avoid noise injection, which can affect
display quality. Adequate decoupling should be provided
between this pin and AVDD.
AVSSDI
1
A19
Dedicated digital ground for the DAC (1.8V)
LTPVSS18
1
A21
PLL macro ground pin.
A26, A30, C29, F24
Interface ground pin.
VSSLT
4
VSS
238
Common Ground
A34, A4, A40, A45, AA39, AA43, AB18,
AB20, AB23, AB26, AB29, AB47, AC19,
AC22, AC25, AC28, AC30, AC38, AC40,
AC44, AD39, AD46, AE18, AE20, AE23,
AE26, AE29, AE39, AE40, AE42, AE43,
AE44, AF19, AF22, AF25, AF28, AF30,
AF47, AG40, AG42, AG43, AH18, AH20,
AH23, AH26, AH29, AH45, AJ19, AJ22,
AJ25, AJ28, AJ30, AJ38, AJ39, AJ40,
AJ44, AK18, AK20, AK23, AK26, AK29,
AK39, AK43, AK47, AM40, AM44, AM45,
AP39, AP43, AP47, AT10, AT12, AT43,
AT6, AU46, AV12, AV42, AV8, AW10,
AW14, AW18, AW21, AW24, AW29, AW32,
AW36, AY16, AY19, AY23, AY25, AY27,
AY30, AY34, AY42, AY47, B31, B37, B42,
B46, B5, BB10, BB12, BB24, BB46, BB8,
BC12, BC18, BC19, BC21, BC24, BC27,
BC29, BC30, BC32, BC34, BD14, BD16,
BD23, BD25, BD36, BD4, BE1, BE21,
BE41, BE43, BE47, BF11, BF14, BF16,
BF2, BF20, BF21, BF24, BF28, BF32,
BF37, BF42, BF43, BF44, BF6, BG14,
BG18, BG20, BG21, BG3, BG4, BG43,
BG8, C11, C12, C14, C19, C20, C22 ,C23,
C26, C44, C47, C6, D12, D21, D23, D27,
D30, D34, D36, D38, D4, D45, D6, E10,
E12, E18, E19, E25, E29, E32, F12, F38,
F46, F5, H12, H18, H19, H25, H27, H34,
H36, H43, H47, J12, K18, K19, K21, K23,
K24, K34, K39, K43, L46, M18, M19, M21,
M24, M25, M36, M40, M43, N18, N19, N21,
P40, P43, T38, T40, T44, T46, V19, V22,
V25, V28, V30, V39, V43, V47, W18, W20,
W23, W26, W29, W40, W44, Y19, Y22,
Y25, Y28, Y30, Y45
VSS_PCIE
104
A3, AA3, AA4, AA8, AB1, AB3, AC12, AC2, PCI Express Interface Ground
AC3, AC4, AC8, AD10, AD12, AD3, AD4,
AD5, AD6, AD8, AD9, AE12, AE3, AE4,
AE8, AF1, AF3, AG12, AG2, AG3, AG4,
AG8, AH3, AJ10, AJ12, AJ3, AJ4, AJ5,
AJ6, AJ8, AJ9, AK1, AK12, AK3, AK4, AK8,
AL2, AL3, AM3, AM4, AM8, AN3, AP10,
AP4, AP5, AP6, AP8, AP9, AT2, AT3, AY1,
AY2, AY3, B2, B3, BB1, BB2, BB3, C1, D1,
E2, E3, F3, F4, G3, H1, H3, H6, K2, K3, K4,
K5, L3, M3, M9, P1, P10, P3, P6, R2, R3,
T3, T4, T8, U3, V4, V8, W10, W2, W3, W4,
W5, W6, W8, W9, Y3
VSS_PLLPCIE
RS600 Databook
3-15
3
T12, T13, V12
PCI Express Interface PLL Ground
Strapping Options
Table 3-18 Ground Pins
Pin Name
Pin Count
PLLVSS
IOPLLVSS
Total Ground
Pin Count
3.15
(Continued)
Ball Reference
Description
1
A11
Ground pin for system PLL
1
W35
Ground pin for CPU/memory interface PLL
356
Strapping Options
The RS600 provides strapping options to define specific operating parameters. The strap values are captured into internal
registers after the de-assertion of the SYSRESET# signal to the RS600. Table 3-19, “Strap Definitions for the RS600,” shows
the definitions of all the strap functions that can be set by board designers. These straps are set by pulling up (to VDDR3)
or pulling down the specific strap pins through resistors to set their values to “1” or “0.”
Table 3-19 Strap Definitions for the RS600
Strap Function
Strap Pin
Description
STRAP_INTGFX_DISABLE
DACHSYNC
Enable/Disable integrated graphics
0: Enable integrated graphics
1: Disable integrated graphics
STRAP_MEMSTRAPS
STRP_DATA
Debug strap configuration. This strap should not be set to “0” on production boards.
0: Select Memory Channel A to be a debug bus
1: Read debug straps from an external EEPROM, or disable debug mode when an
EEPROM is absent.
STRAP_MOBILE_GFX
DACVSYNC
Select configuration of the integrated graphics engine.
0: Required setting for the RS600
1: Reserved
STRAP_MEMVMODE
DDC_DATA
Select DDR2 or DDR3 signalling level for the memory interface.
0: DDR3. On DDR3, it is necessary to put an isolation FET in series with the pull-up
resistor on this strap to separate it from the I2C circuit during an NB reset.
1: DDR2
RS600 Databook
3-16
Chapter 4
Timing Specifications
4.1
Processor Front Side Bus Timing
Table 4-1 Processor Front Side Bus Timing (for 1066 MHz Front Side Bus*)
Timing Parameter
Symbol
Min
Max
Unit
Figure
Data output valid delay from SYSCLK (first data
only)
T1
274
1235
ps
4-1
Data output valid delay before Data Strobe
T2
122
—
ps
4-1
Data Signals (4x FSB clocks)
RS600 Driving
Data output valid delay after Data Strobe
T3
110
—
ps
4-1
First data strobe ‘p’ (CPU_DSTBP#) output valid
delay from SYSCLK
T4a
753
1702
ps
4-1
Second data strobe ‘n’ (CPU_DSTBN#) output
valid delay from SYSCLK
T4b
3419
4526
ps
4-1
T5
94
—
ps
4-1
RS600 Receiving
Data to Data Strobe setup time
Data to Data Strobe hold time
T6
137
—
ps
4-1
Data strobe to SYSCLK setup time
T7
1149
—
ps
4-1
Address output valid delay from SYSCLK (first
address only)
T8
241
1256
ps
4-2
Address output valid delay before Address Strobe
T9
546
—
ps
4-2
Address output valid delay after Address Strobe
T10
593
—
ps
4-2
Address strobe output valid delay from SYSCLK
T11
1180
2113
ps
4-2
Address to Address Strobe setup time
T12
49
—
ps
4-2
Address to Address Strobe hold time
T13
111
—
ps
4-2
Address Strobe setup time to SYSCLK
T14
1637
—
ps
4-2
T15
41
1276
ps
4-3
Common clock signal setup time
T16
690
—
ps
4-3
Common clock signal hold time
T17
149
—
ps
4-3
Address Signals (2x FSB clocks)
RS600 Driving
RS600 Receiving
Common Clock Signals (1x FSB or common clock)
RS600 Driving
Common clock signal output valid delay from
SYSCLK
RS600 Receiving
*Note: The 1066MHz FSB speed is NOT supported by the RS600L.
RS600 Databook
4-1
Table 4-2 Processor Front Side Bus Timing (for 800MHz Front Side Bus)
Timing Parameter
Symbol
Min
Max
Unit
Figure
only)
T1
274
1235
ps
4-1
T2
261
—
ps
4-1
T3
250
—
ps
4-1
delay from SYSCLK
T4a
908
1858
ps
4-1
T4b
4505
5612
ps
4-1
T5
94
—
ps
4-1
RS600 Driving
RS600 Receiving
T6
137
—
ps
4-1
T7
1149
—
ps
4-1
address only)
T8
241
1256
ps
4-2
T9
856
—
ps
4-2
T10
903
—
ps
4-2
T11
1490
2423
ps
4-2
T12
49
—
ps
4-2
RS600 Driving
RS600 Receiving
T13
111
—
ps
4-2
T14
1637
—
ps
4-2
T15
41
1276
ps
4-3
T16
690
—
ps
4-3
T17
149
—
ps
4-3
RS600 Driving
SYSCLK
RS600 Receiving
RS600 Databook
4-2
Table 4-3 Processor Front Side Bus Timing (for 533MHz Front Side Bus)
Timing Parameter
Symbol
Min
Max
Unit
Figure
only)
T1
274
1235
ps
4-1
T2
545
—
ps
4-1
RS600 Driving
T3
533
—
ps
4-1
delay from SYSCLK
T4a
1223
2172
ps
4-1
T4b
6709
7816
ps
4-1
RS600 Receiving
T5
94
—
ps
4-1
T6
137
—
ps
4-1
T7
1149
—
ps
4-1
T8
241
1256
ps
4-2
T9
1486
—
ps
4-2
T10
1533
—
ps
4-2
T11
2120
3053
ps
4-2
T12
49
—
ps
4-2
T13
111
—
ps
4-2
T14
1637
—
ps
4-2
T15
41
1276
ps
4-3
T16
690
—
ps
4-3
T17
149
—
ps
4-3
RS600 Driving
address only)
RS600 Receive
RS600 Driving
SYSCLK
RS600 Receiving
RS600 Databook
4-3
SYSCLK#
SYSCLK
T4a
CPU_DSTBP#
(@driver)
T4b
CPU_DSTBN#
(@driver)
T3
T3
T2
T2
CPU_D#
(@driver)
T1
VALID
T7
CPU_DSTBP#
(@receiver)
CPU_DSTBN#
(@receiver)
CPU_D#
(@receiver)
T5 T6
VALID
Figure 4-1 Front Side Bus Timing for Data Signals
SYSCLK#
SYSCLK
CPU_ADSTB#
(@driver)
T11
T9
T10
CPU_A#
(@driver)
T8
VALID
T14
CPU_ADSTB#
(@receiver)
CPU_A#
(@receiver)
T12
T13
VALID
Figure 4-2 Front Side Bus Timing for Address Signals
RS600 Databook
4-4
SYSCLK#
SYSCLK
T15
Control Signals
(@driver)
VALID
T16
Control Signals
(@receiver)
T17
VALID
Figure 4-3 Front Side Bus Timing for Control Signals
Table 4-4 System Clock AC Specifications
Timing Parameter
Symbol
SYSCLK/SYSCLK#
Period
133 MHz
200MHz
266MHz*
Unit
Figure
3751
ps
4-4
45
55
% of
SYSCLK
period
4-4
55
45
55
% of
SYSCLK
period
4-4
—
85
—
85
ps
4-4
700
175
700
175
700
ps
4-4
175
700
175
700
175
700
ps
4-4
T24
45
55
45
55
45
55
% of
SYSCLK
period
4-4
SYSCLK# low time
T25
45
55
45
55
45
55
% of
SYSCLK
period
4-4
SYSCLK# falling edge
(65-35%)
T26
175
700
175
700
175
700
ps
4-4
SYSCLK# rising edge
(35-65%)
T27
175
700
175
700
175
700
ps
4-4
Min
Max
Min
Max
Min
Max
T18
7498
7502
5000
5002
3749
SYSCLK high time
T19
45
55
45
55
SYSCLK low time
T20
45
55
45
SYSCLK/SYSCLK# jitter
(measured differentially)
T21
—
85
SYSCLK rising edge
(35-65%)
T22
175
SYSCLK falling edge
(65-35%)
T23
SYSCLK# high time
*Note: The 266 MHz FSB speeds are NOT supported by the RS600L.
RS600 Databook
4-5
Memory Timing
T23
T22
65%
SYSCLK
50%
35%
T21
T19
T20
T18
T24
T25
T21
65%
SYSCLK#
50%
35%
T26
T27
Figure 4-4 SYSCLK/SYSCLK# AC Specifications
4.2
Memory Timing
The memory interface on the RS600 complies with all the timing requirements specified in the JEDEC DDR standards.
On top of that, there are DLLs inside the RS600 that can delay the falling and rising edges of the write data, write data
mask, write data strobes, and also the read data strobes with respect to the relevant data byte. The delays will ensure
adequate hold and setup time for data transmission. These delays are programmable, and details on how to programme
them can be found in the RS600 Memory Interface Programming Guide. As a result, the only design requirements for
ensuring proper setup and hold time for the memory data are the length-matching requirements described in the
RS600/RC610-Series IGP System Layout and Design Guide.
4.3
OSCIN Timing
Table 4-5 Timing Requirements for the OSCIN Pad
Symbol
Parameter
TIP
REFCLK Period
Min
Typical
Max
Unit
Note
0.037
–
1.1
µs
1
2
FIP
REFCLK Frequency
0.9
–
27
MHz
TIR
REFCLK Rise Time
–
–
1.5
ns
TIF
REFCLK Fall Time
–
–
1.5
ns
TIJCC
REFCLK Cycle-to-Cycle Jitter Requirement
–
–
300
ps
FTOL
Frequency Tolerance
–
30
–
ppm
3
Notes:
1 Time intervals measured at 50% threshold point.
2 FIP is the reciprocal of TIP.
3 Of the desired frequency to generate expected PLL output frequencies.
RS600 Databook
4-6
Power Rail Power Up Sequence
4.4
VDD_MEM
(1.8V/1.5V memory)
T10
VDD18
(1.8V, see note)
VDDR3/ VDDLT33/
AVDD (3.3V)
T11
T12
IOPLLVDD12/
PLLVDD12
(1.2V)
T13
T14
VDD_CPU
(CPU I/O rail)
VDD_CORE
(ASIC core power)
T16
T15
Note: The following power supplies comprise “VDD18,” and will ramp together and will have the same timing requirements—
VDD18_MEM, VDD18_CPU, IOPLLVDD18, PLLVDD18, VDDLT18, LTPVDD18, AVDDDI, and, AVDDQ.
Figure 4-5 Power Rail Power Up Sequence for the RS600
Table 4-6 Power Rail Power Up Sequence Timing for the RS600
Symbol
Time Lag
Min.
VDD18 should not exceed
VDD_MEM by more than 0.6V
Max.
T10
VDD18 (1.8V) ramps high relative to
VDD_MEM (1.8V/1.5V)
T11
VDDR3/VDDLT33/AVDD must not
begin ramping until VDD18 has reach
VDDR3/VDDLT33/AVDD (3.3V) ramps 90% of its final voltage, and
No restriction
VDDR3/VDDLT33/AVDD must not
high relative to VDD18 (1.8V)
exceed VDD18 by more than 2.0V at
any time.
T12
IOPLLVDD12/PLLVDD12 (1.2V) ramps
high relative to VDD18 (1.8V
IOPLLVDD12/PLLVDD12 should not
exceed VDD18 by more than 0.6V
No restriction
T13
VDD_CORE (1.2V) ramps high relative
to VDDR3/VDDLT33/AVDD
VDD_CORE should not exceed
VDDR3/VDDLT33/AVDD by more
than 0.6V
No restriction
T14
VDD_CPU (CPU I/O rail) ramps high
relative to VDD_CORE (1.2V)
VDD_CPU must ramp up before or
with VDD_CORE
No restriction
T15
to IOPLLVDD12/PLLVDD12 (1.2V)
IOPLLVDD12/PLLVDD12 by more
than 0.6V
No restriction
T16
to VDD18 (1.8V)
VDD18 by more than 0.6V
No restriction
No restriction
Note: For power down, the rails should either be turned off simultaneously or in the reversed order of the above power up
sequence. Variations in speeds of decay due to different capacitor discharge rates can be safely ignored.
Shown here is the power up sequence for the power rails that the RS600 connects to. For a power up sequence for the
whole RS600 platform, please refer to the RS600/RC610-Series IGP System Layout and Design Guide, Section 5.
RS600 Databook
4-7
RS600 Databook
4-8
Chapter 5
Electrical Characteristics and Physical Data
5.1
Electrical Characteristics
5.1.1
Maximum and Minimum Ratings
Table 5-1 Maximum and Minimum Ratings
Minimum
Typical
Maximum
Unit
VDD_CORE
Pin
1.14
1.2
1.26
V
ASIC core power
VDD_18CPU
1.71
1.8
1.89
V
Core transform power for CPU
pads
VDD_18MEM
1.71
1.8
1.89
V
Core transform power for memory
pads
1.425/1.71
1.5/1.8
1.575/1.89
V
IO power for the DDR Memory
interface
0.8
Variable
1.35
V
IO power for the CPU interface
3.135
3.3
3.465
V
3.3 Volt IO power
VDD_MEM
VDD_CPU
VDDR3
5.1.2
Comments
VDD_PCIE
1.14
1.2
1.26
V
PCI Express Interface I/O Power
VDD_PLLPCIE
1.14
1.2
1.26
V
PCI Express Interface PLL Power
AVDDDI
1.71
1.8
1.89
V
Digital power for DAC
AVDDQ
1.71
1.8
1.89
V
Band gap reference voltage for
DAC
AVDD
3.135
3.3
3.465
V
IO power for DAC
LTPVDD18
1.71
1.8
1.89
V
Power for integrated DVI/HDMI
PLL
VDDLT18
1.71
1.8
1.89
V
1.8V integrated DVI/HDMI Digital
Power
VDDLT33
3.234
3.3
3.465
V
3.3V integrated DVI/HDMI Analog
Power
PLLVDD12
1.14
1.2
1.26
V
1.2V Power for SYSTEM PLLs
PLLVDD18
1.71
1.8
1.89
V
1.8V Power for SYSTEM PLLs
IOPLLVDD12
1.14
1.2
1.26
V
1.2V Power for IO PLLs
IOPLLVDD18
1.71
1.8
1.89
V
1.8V Power for IO PLLs
DC Characteristics
Table 5-2 DC Characteristics for Front Side Bus Signals
Parameter
VIL (Input Low)
Minimum
VIL (Input Low)
-0.1V
VIH (Input High)
GTLREF+0.1V
Overshoot
—
Undershoot
-0.1V
Maximum
Comment
GTLREF-0.1V
Figure Figure 5-1 below illustrates the parameters.
VDD_CPU+0.1V VDD_CPU is the voltage for the CPU I/O power.
VDD_CPU+0.1V GTLREF is the reference voltage for GTL+ signals on the
Front Side Bus.
—
RS600 Databook
5-1
Overshoot
VIH
GTLREF
VIL
Undershoot
Figure 5-1 Front Side Bus DC Characteristics
Table 5-3 DC Characteristics for PCI-E Differential Clock (GFX_CLK, SB_CLK) Input
Symbol
Description
VIL
Input Low Voltage
Minimum
–
VIH
Input High Voltage
VCROSS
Absolute Crossing Point
VMIN
Absolute Minimum Input Voltage
VMAX
Absolute Maximum Input Voltage
Maximum
Unit
Note
-0.150
V
1
0.150
–
V
1
0.250
0.550
V
- 0.300
–
V
2
–
1.15
V
3
Notes:
1 - The value specified is for the differential wave form.
2 - The value is defined as the minimum instantaneous voltage including undershoot, and is specified for the single-ended waveform.
3 - The value is defined as the maximum instantaneous voltage including overshoot, and is specified for the single-ended waveform.
RS600 Databook
5-2
Table 5-4 DC Characteristics for TTL Signals
Pins
Symbol
DACVSYNC
DACSDA
DACHSYNC
DDC_DATA
GPIO[10:8]
OSCIN
I2C_DATA, I2C_CLK
POWERGOOD *
SUS_STAT# *
STRP_DATA
SYSRESET#
TESTMODE
TMDS_HPD
Description
Minimum Maximum Unit
VILdc
DC voltage at PAD pin that will produce
a stable low at the Y pin of macro
–
0.728
V
VIHdc
DC voltage at PAD pin that will produce
a stable high at the Y pin of macro
1.329
–
V
VOL
Output low voltage
–
0.25
V
VOH
Output high voltage
2.65
–
V
IOL
Output low current at V=0.1V
3.95
–
mA
IOH
Output high current at V=VDDR-0.1V
4.95
–
mA
*Note: POWERGOOD and SUS_STAT# are input only, for which only the specifications for VILdc and VIHdc apply.
Table 5-5 DC Characteristics for the DDR2/3 Interface
Symbol
Description
Minimum
Maximum
Comments
VIL(dc)
DC Input Low Voltage
-0.3V
VREF-0.15V
For DQ and DQS
VIH(dc)
DC Input High Voltage
VREF + 0.15V
VDDQ + 0.3V
For DQ and DQS. (VDDQ is IO voltage
for memory device.)
VIL(ac)
AC Input Low Voltage
–
VREF - 0.31
For DQ and DQS
AC Input High Voltage
VIH(ac)
VREF + 0.31V
–
For DQ and DQS
VUSH
Minimum Voltage Allowed for
Undershoot
- 0.3V
–
For DQ and DQS
VOSH
Maximum Voltage Allowed for
Overshoot
–
VDDQ + 0.3V
0.186V
0.305V
I_out = 16.5mA
I_out = -16.5mA
VOI
Output Low Voltage
VOH
Output High Voltage
1.90V
2.50V
VREF
DC Input Reference Voltage
1.125V
1.375V
ILI
Input Leakage Current
10µA
15µA
ILO
Tri-state Leakage Current
10µA
15µA
CIN
Input Capacitance
3pF
5pF
For DQ and DQS. (VDDQ is IO voltage of
memory device.)
Table 5-6 DC and Characteristics for OSCIN Pad
Symbol
VIH
VIL
VIMAX
Parameter
Input High Voltage
Min
Typical
Max
Unit
2.5
2.6
–
V
Input Low Voltage
–
0
0.6
V
Maximum Input Voltage
–
–
3.3
V
Note
RS600 Databook
5-3
Table 5-7 Electrical Requirements for DVI/HDMI
Symbol
Min
Typical
Max
Unit
VCM
Differential Output Common-mode Voltage
Parameter
-0.5
–
4.0
V
DVCM
Differential Output Common-mode Voltage
Ripple
–
–
580
mV
Note
VH
Single-ended High Level Output Voltage
AVCC - 10
–
AVCC + 10
mV
2
VL
Single-ended Low Level Output Voltage
AVCC - 600
–
AVCC - 400
mV
2
400
–
600
mV
–
–
180
mV
VOD
Differential Output Swing
VOS
Differential Output Overshoot (Ringing)
Differential Output Undershoot (Ringing)
–
–
200
mV
IDDLP
VUS
Average Supply Current at LTPVDD18
–
10.0
–
mA
3
IDDLV
Average Supply Current at VDDLT18/33
–
100.0
–
mA
3
IPDLP
Power Down Current at LTPVDD18
–
10.0
–
µA
4
IPDLV
Power Down Current at VDDLT18/33
–
10.0
–
µA
4
Notes:
1 Figure 5-2 below illustrates some of the DC Characteristics for DVI/HDMI.
2 AVCC stands for the termination supply voltage of the receiver, which is 3.3V +/- 5%.
3 Measured under typical conditions, at minimum differential clock frequency and maximum DVI/HDMI PLL VOC frequency.
4 Measured under typical conditions, based on typical leakage values.
Single-ended Waveforms
VOD
VCM = -0.5
to 4V
Ground
Differential Waveform
VOD
+600 to
+400mV
0V
-400 to
-600mV
Figure 5-2 DC Characteristics for DVI/HDMI
RS600 Databook
5-4
RS600 Thermal Characteristics
5.2
RS600 Thermal Characteristics
This section describes some key thermal parameters of the RS600. For a detailed discussion on these parameters and
other thermal design issues, please consult the Thermal Design and Analysis Guidelines for the RS600 .
5.2.1
RS600 Thermal Limits
Table 5-8 RS600 Thermal Limits
Parameter
Operating Case Temperature
Minimum
Nominal
Maximum
—
—
103
Unit
°
C
1
2
3
Operating Junction Temperature
—
—
105
°C
Absolute Junction Temperature
—
—
125
°C
Note
Storage Temperature
-40
—
60
°
Ambient Temperature
5
—
45
°C
4
Thermal Design Power
—
17
—
W
5
C
Notes:
1 - The maximum operating case temperature is the maximum case temperature at which the functionality of the chip is qualified. The
temperature is measured using a fine thermocouple put between the thermal management device contact surface and the back side of
the die.
2 - The maximum operating junction temperature is the interpolated value of the junction temperature at the time when the maximum
operating case temperature is being measured.
3 - The maximum absolute junction temperature is the junction temperature at which the device can operate without causing damage to
the ASIC.
4 - The ambient temperature is defined as the temperature of the local intake air at the inlet to the thermal management device.
5 - The Thermal Design Power (TDP) is defined as the worst-case power dissipation while running currently available applications at
nominal voltages and at the maximum operating temperature. The TDP is intended only as a design reference. It is not an absolute
maximum power under all conditions. The value shown here is a preliminary estimate only, and it is measured at a core voltage of 1.2V.
5.2.2
Other Thermal Parameters
Two thermal parameters, θjc and θjb, are defined for the RS600 package under the “two-resistor” thermal model
(see the Thermal Design and Analysis Guidelines for the RS600 for details), and their definitions are as follows:
θjc = (Tj - Tc) / Qc
θjb = (Tj - Tb) / Qb
Where:
Tc = Mean case (package-air interface) temperature
Tb = Mean package-board interface temperature
Qc = Heat dissipated through the case (package-air interface)
Qb = Heat dissipated through the PCB.
Table 5-9 shows the measured values for θjb and θjc:
Table 5-9 Thermal Parameters for the RS600
Parameter
Value (°C/W)
θjb
22.85
θjc
0.12
However, the “two-resistor model,” under which these parameters are defined, is a highly simplified thermal model.
A Delphi model for the RS600 package, available from your ATI FAE representative, will allow more accurate
calculations and is preferred over the “two-resistor model.”
RS600 Databook
5-5
Physical Package
5.3
Physical Package
Figure 5-3 and Table 5-10 describes the physical dimensions of the RS600 package. Figure 5-4 shows the detailed
ball arrangement for the RS600.
POD-350350120108002_3-REVA
Figure 5-3 RS600 Package Outline
Table 5-10 RS600 1201-Pin FCBGA Package Physical Dimensions
Ref.
Min(mm)
Typical (mm)
Max. (mm)
c
0.96
1.06
1.16
A*
2.18
2.33
2.48
A1
0.30
0.40
0.50
A2
0.84
0.87
0.90
φb
0.40
0.50
0.60
D1
34.80
35.00
35.20
D2
-
9.43
-
E1
34.80
35.00
35.20
E2
-
9.35
-
F1
-
33.60
-
F2
-
33.60
-
e1
-
0.80
-
ddd
-
-
0.15
RS600 Databook
5-6
Physical Package
User of the PDF version of this document can zoom in on the figure to read the ball references better.
Figure 5-4 RS600 Detailed Ball Arrangement
RS600 Databook
5-7
Pressure Specifications
5.4
Pressure Specifications
To avoid damages to the ASIC (die or solder ball joint cracks) caused by improper mechanical assembly of the cooling
device, follow the recommendations below:
•
The ASIC device can withstand up to 98 Newtons of force when uniformly distributed; however, it is
recommended that the maximum force (evenly applied) across the contact area between the thermal
management device and the die does not exceed 40 psi. (Note that a contact pressure of 30-40 psi is adequate to
secure the thermal management device and achieve the lowest thermal contact resistance with a temperature
drop across the thermal interface material of no more than 3°C.)
•
Pre-test the assembly fixture with a strain gauge to make sure that the flexing of the final assembled board and
the pressure applying around the ASIC package will not exceed 600 micron strain under any circumstances.
•
Ensure that any distortion (bow or twist) of the board after SMT and cooling device assembly is within industry
guidelines (IPC/EIA J-STD-001). For measurement method, refer to the industry approved technique described
in the manual IPC-TM-650, section 2.4.22.
5.5
Board Solder Reflow Process Recommendations
5.5.1
Stencil Opening Size for Solderball Pads on PCB
A stencil opening size of 350µm is recommended for the six pads at each corner of the ASIC package, and a size of
300µm is recommended for all other pads (see Figure 5-5 below). This recommendation is based on ATI’s sample
land pattern design for the RS600, which is available from your ATI FAE representative.
350µm
openings
recommended
350µm
openings
recommended
300µm openings
recommended for all
other pads
350µm
openings
recommended
350µm
openings
recommended
Figure 5-5 Recommended Stencil Opening Sizes for Solderball Pads on PCB
RS600 Databook
5-8
5.5.2
Reflow Profiles
Two reference reflow profiles are given below—one for eutectic solder and the other for lead-free solder.
Please note the following:
•
The final reflow temperature profile will depend on the type of solder paste and chemistry of flux used in the SMT
process. Modifications to the reference reflow profile may be required in order to accommodate the requirements of
the other components in the application.
•
For eutectic solder, a reflow oven with 8 heating zones or above is recommended. For lead-free solder, an oven with
10 heating zones or above is recommended.
•
To ensure that the reflow profile meets the target specification on both sides of the board, different profiles and oven
recipes for the first and second reflow may be required.
•
Mechanical stiffening can be used to minimize board warpage during reflow.
•
The temperature ramp rate requirement is for minimizing board warpage.
•
Maximum number of reflows: 3.
Solder/Parts Surface Temperature( °C)
250
Peak Temp.
°
°
(215 C +/-5% typ., 225 C max.)
<2.0oC / sec.
200
183°C
150
Soaking Zone
100
60 – 120 sec. typical
Pre-heating Zone
50
Soldering Zone
45 - 90 sec. Max.
70-80 sec. typical
<2.0oC / sec.
2 min. to 4 min. Max.
Figure 5-11 Eutectic Solder(Sn63/Pb37 Tin-Lead) Reflow Profile
RS600 Databook
5-9
o
Solder/Part Surface Temp. ( C )
Peak Temp. (235 oC+/-5% typ., 245 oC max.)
250
220 deg.C
<2.0oC / Sec.
200
170 oC
150
130 oC
100
50
Soaking Zone
Soldering Zone
60 – 120 sec. max
60 – 80 sec. typical
45 - 90 sec. Max.
60 - 80 sec. typical
<2.0o.C / Sec.
Pre-heating Zone
2 min to 4 min Max.
Heating Time
Figure 5-12 Lead-Free Solder (SAC305/405 Tin-Silver-Copper) Reflow Profile
RS600 Databook
5-10
Chapter 6
Power Management and ACPI
6.1
ACPI Power Management Implementation
This chapter describes the support for ACPI power management provided by the RS600. The RS600 system controller
supports ACPI Revision 1.0b. The hardware, system BIOS, video BIOS, and drivers of the RS600 have all the logic
required for meeting the power management specifications of PC2001, OnNow, and the Windows Logo Program and
Device Requirements version 2.1. Table 6-1, “ACPI States Supported by the RS600,” describes the ACPI states
supported by the RS600 system controller. Table 6-2, “ACPI Signal Definitions,” describes the signals used in the ACPI
power management scheme of the RS600.
Table 6-1 ACPI States Supported by the RS600
ACPI State
Description
Graphics States:
D0
Full on, display active.
D1
Display Off. RS600 power on. Configuration registers, state, and main memory contents retained.
D3 Hot
Similar to D1, with memory put into self-refresh and graphics PLLs shut off.
D3 Cold
RS600 power off.
Processor States:
S0/C0: Working State
Working State. The processor is executing instructions.
S0/C1: Halt
CPU Halt state. No instructions are executed. This state has the lowest latency on resume and contributes
minimum power savings.
S0/C2: Stop Grant
Caches Snoopable
Stop Grant or Cache Snoopable CPU state. This state offers more power savings but has a higher latency
on resume than the C1 state.
S0/C3: Stop Grant
Caches Not Snoopable
Stop Grant or Cache not Snoopable Sleep state. The CPU’s caches maintain state but ignore any snoops.
This state offers more power savings but has a higher latency on resume than the C1 and C2 states.
S0/C4: Deeper Sleep
Deeper Sleep State. This is the lowest power state the CPU can enter.
System States:
S1: Standby
Powered On Suspend
System is in Standby mode. This state has low wakeup latency on resume. OEM support of this state is
optional.
S3: Standby
Suspend to RAM
System is off but context is saved to RAM. OEM support of this state is optional. System memory is put
into self-refresh.
S4: Hibernate
Suspend to Disk
System is off but context is saved to disk. When the system transitions to the working state, the OS is
resumed without a system re-boot.
S5: Soft Off
System is off. OS re-boots when the system transitions to the working state.
G3: Mechanical Off
Occurs when system power (AC or battery) is not present or is unable to keep the system in one of the
other states.
Table 6-2 ACPI Signal Definitions
Signal Name
Description
Source
A_RST#
PCI host bus reset
South bridge
CPU_CPURST#
CPU reset
RS600
CPU_STP#
Stop CPU clock
South Bridge
DPRSLP#
Deeper sleep
South bridge
DRPSLPVR
Deeper sleep voltage regulator
South bridge
INIT#
CPU initialization
South bridge
INTR
Interrupt to CPU
South bridge
NMI
Non-maskable Interrupt
South bridge
RS600 Databook
6-1
Power Management for the Graphics Controller
Table 6-2 ACPI Signal Definitions
(Continued)
Signal Name
6.2
Description
Source
PCIRST#
PCI bus reset
South bridge
POWERON#
Power on
Power switch
PWR_GOOD
South bridge power good
South bridge power
good circuit on
motherboard
SLP#
Sleep
South bridge/
RS600
SLP_S3#
S3 sleep power plane control
South bridge
SLP_S5#
S5 sleep power plane control
South bridge
SMI#
System management interrupt to CPU
South bridge
STPCLK#
Stop clock signal to CPU
South bridge
SUS_STAT#
Disable RS600 internal clock tree during S1-S3 states.
South bridge
The RS600 supports power management for the embedded graphics device as specified by the PCI Bus Power
Management Interface Specification version 1.0, according to which the integrated graphics core of the RS600 qualifies
as a device embedding a single function in the power management system.
6.2.1
PCI Function Power States
There are up to four power states defined for each PCI function associated with each PCI device in the system. These
power states are D0, D1, D2 and D3. D0 (on) consumes the most power while D3 (off) consumes the least. D1 and D2
enable levels of power savings in between those of D0 and D3. The concepts of these power states are universal for all
functions in the system. When transitioned to a given power management state, the intended functional behavior is
dependent upon the type (or class) of the function.
6.2.2
PCI Power Management Interface
The four basic power management operations are:
•
•
•
•
Capabilities Reporting
Power Status Reporting
Setting Power State
System Wakeup
All four of these capabilities are required for each power management function with the exception of wakeup event
generation.
This section describes the format of the registers in the PCI Configuration Space that are used by these power
management operations. The Status and Capabilities Pointer (CAP_PTR) fields have been highlighted to indicate where
the PCI Power Management features appear in the standard Configuration Space Header.
Table 6-3 Standard PCI Configuration Space Header Type 0
Register Fields (32bits)
MSB
Offset
LSB
Device ID
Vendor ID
00h (LSB)
Status (with Bit 4 set to 1)
Command
04h
Class Code
Revision ID
BIST
RS600 Databook
6-2
Header Type
Latency Timer
08h
Cache Line Size
0Ch
Table 6-3 Standard PCI Configuration Space Header Type 0
(Continued)
Register Fields (32bits)
MSB
Offset
LSB
Base Address Registers
10h
14h
18h
1Ch
20h
24h
CardBus CIS Pointer
28h
Subsystem ID
Subsystem Vendor ID
Expansion ROM Base Address
30h
Reserved
CAP_PTR
34h
Interrupt Line
3Ch
Reserved
38h
Max_Lat
6.2.3
2Ch
Min_Gnt
Interrupt Pin
Capabilities List Data Structure in PCI Configuration Space
The Capabilities bit in the PCI Status register (offset = 06h) indicates whether or not the subject function implements a
linked list of extended capabilities. Specifically, if bit 4 is set, the CAP_PTR register is implemented to give offset to the
first item in the Capabilities link list.
Table 6-4 PCI Status Register
Bits
Read/
Write
Default Value
Description
15:05
--
--
Refer to PCI Local Bus Specification, Revision 2.2
04
1b
Read Only
This bit indicates whether this function implements a list of extended capabilities
such as PCI power management. When set, this bit indicates the presence of
Capabilities. A value of 0 implies that this function does not implement
Capabilities.
03:00
0h
Read Only
Reserved
The location of the Capabilities Pointer (CAP_PTR) depends on the PCI header type. See PCI specification Revision 2.2
for specification of CAP_PTR offsets.
Table 6-5 Capabilities Pointer (CAP_PTR)
Bits
07:00
Default Value
5Ch
Read/
Write
Read Only
Description
The CAP_PTR provides an offset in the PCI Configuration Space of the
function to access the location of the first item in the Capabilities linked list. The
CAP_PTR offset is DWORD aligned, so that the two least significant bits are
always zeros.
The graphics core implements extended capabilities of the AGP and Power Management. It needs to provide the
standardized register interface. The first entry in the chain of descriptors has to be the PMI descriptor, as this functionality
will be supported even if the RS600 operates as a PCI device. The Capabilities Identifier for Power Management is 01h.
6.2.4
Register Block Definition
This section describes the PCI Power Management Interface registers. These registers are implemented inside the Host
Interface (HI) as part of the configuration space of the device (RS600).
RS600 Databook
6-3
Table 6-6 Power Management Register Block
Register Fields
Offset
Capabilities ID
00h
Next Item Ptr
01h
Power Management Capabilities (PMC)
02h
Power Management Control/Status Register (PMCSR)
04h
Reserved
06h
The first 16 bits (Capabilities ID [offset = 0] and Next Item Pointer [offset = 1]) are used for the linked list infrastructure.
The next 32 bits (PMC [offset = 2] and PMCSR registers [offset = 4]) are required for compliance with this specification.
As with all PCI configuration registers, these registers may be accessed as bytes, 16-bit words, or 32-bit DWORDs. All of
the write operations to the reserved registers must be treated as no-ops. This implies that the access must be completed
normally on the bus and the data should be discarded. Read accesses to the reserved or the unimplemented registers must
be completed normally and a data value of 0000h should be returned.
Table 6-7 Power Management Control/Status Register (PMCSR)
Field
Name
Default
(Reset)
Bits
Power State 1:0
00
Description
This field describes the power state of the graphics core.
States
Power State 15:2
0
Function
00 = D0
Normal operation, no power savings enabled
01 = D1
Sleeping state 1:
Display is off
Host access to DRAM is allowed
10 = D2
Sleeping state 2
Display is off.
All engines are off.
Graphics core does not respond to host accesses to the frame buffer.
11 = D3
Everything, except Host Interface, is turned off.
These Read Only bits will return the clock status of each clock tree, generated inside the clock
block.
The offset for each register is listed as an offset from the beginning of the linked list item that is determined either from
the CAP_PTR (if Power Management is the first item in the list) or the NEXT_ITEM_PTR of the previous item in the list.
6.2.5
Capability Identifier: Cap_ID (Offset = 0)
The Capability Identifier, when read by system software as 01h, indicates that the data structure currently being pointed to
is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list
with Cap_ID set to 01h.
Table 6-8 Capability Identifier (Cap_ID)
Bits
07:00
Default Value
01h
Read/
Write
Read Only
Description
This field, when set to 01h, identifies the linked list item as being the PCI Power
Management registers
Figure 6-1, ‘Linked List for Capabilities,” shows the implementation of the capabilities list. The CAP_PTR gives the
location of the first item in the list. PCI Power Management registers have been stated as example in this list (although the
capabilities can be in any order).
•
The first byte of each entry is required to be the ID of that capability. The PCI Power Management capability has an
ID of 01h.
RS600 Databook
6-4
•
•
The next byte is a pointer giving an absolute offset in the functions PCI Configuration Space to the next item in the
list and must be DWORD aligned.
If there are no more entries in the list, the NEXT_ITEM_PTR must be set to 0 to indicate an end of the linked list.
Each capability can then have registers following the NEXT_ITEM_PTR.
The definition of these registers (including layout, size, and bit definitions) is specific to each capability. The PCI Power
Management Register Block is defined in Figure 6-1, ‘Linked List for Capabilities,” below.
PCI Configuration Header
Offset 34h
Cap_Ptr = 50h
8 bits
Offset 50h
5Ch
02
AGP Capability
Offset 5Ch
00h
01
PM Registers
Figure 6-1 Linked List for Capabilities
6.2.6
Next Item Pointer
The Next Item Pointer register describes the location of the next item in the capability list of the function. The value given
is an offset in the PCI Configuration Space of that function. This register must be set to 00h if the function does not
implement any other capabilities defined by the PCI Specifications for inclusion in the capabilities list, or if power
management is the last item in the list.
Table 6-9 Next Item Pointer (NEXT_ITEM_PTR)
Bits
07:00
RS600 Databook
6-5
Default
Value
00h = PCI
mode
50h = AGP
mode
Read/
Write
Read Only
Description
This field provides an offset in the PCI Configuration Space of the function pointing to the location
of next item in the capability list of the function. For Power Management of the RS600, this
pointer must be set to zero if operating in PCI mode. This indicates that there is no additional
Capability (AGP) of the device (RS600). In AGP mode, this pointer has to reflect the start offset of
the AGP Capability Descriptor (50h).
6.2.7
PMC - Power Management Capabilities (Offset = 2)
The Power Management Capabilities register is a 16-bit Read Only register that provides information on the capabilities of the
function related to power management. The information in this register is generally static and is known at design time.
Table 6-10 Power Management Capabilities – PMC
Bits
Default Value
Read/
Write
Description
15:11
00111b
Read Only
This 5-bit field indicates the power states in which the function may assert PME#. A value of
0b for any bit indicates that the function is not capable of asserting the PME# signal while in
that power state.
bit(11) XXXX1b - PME# can be asserted from D0.
bit(12) XXX1Xb - PME# can be asserted from D1.
bit(13) XX1XXb - PME# can be asserted from D2.
bit(14) X0XXXb - PME# cannot be asserted from D3hot.
bit(15) 0XXXXb - PME# cannot be asserted from D3cold.
10
001b
Read Only
RS600 supports D2.
09
001b
Read Only
RS600 supports D1.
08:06
000b
Read Only
Reserved
05
1b
Read Only
The Device Specific Initialization bit indicates whether special initialization of this function is
required (beyond the standard PCI configuration header) before the generic class device
driver is able to use it. The RS600 requires device specific initialization after Reset; this field
must therefore return a value 1 to the system.
04
0b
Read Only
Reserved
03
0b
Read Only
Reserved
02:00
001b
Read Only
A value of 001b indicates that this function complies with Revision 1.0 of the PCI Power
Management Interface Specification.
RS600 Databook
6-6
Chapter 7
Testability
7.1
Test Capability Features
The RS600 system controller has integrated test modes and capabilities. These test features cover both the ASIC and
board level testing. The ASIC tests provide a very high fault coverage and low DPM (Defect Per Million) ratio of the part.
The board level tests modes can be used for motherboard manufacturing and debug purposes. The following are the test
modes of the RS600 system controller:
•
•
•
•
•
•
Full scan implementation on the digital core logic that provides approximately 99% fault coverage through ATPG
(Automatic Test Pattern Generation Vectors).
Dedicated test logic for the on-chip custom memory macros to provide complete coverage on these modules.
Improved access to the analog modules and PLLs in the RS600 system controller in order to allow full evaluation and
characterization of these modules.
A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) in order to allow board level testing
of neighboring devices.
An XOR TREE test mode on all the digital I/O’s to allow for proper soldering verification at the board level.
An EXTEST test mode in order to allow board level testing by sampling the inputs and controlling the output of the
RS600 system controller.
These test modes can be accessed through the settings on the instruction register of the JTAG circuitry.
7.2
Test Interface
Table 7-1 Pins on the Test Interface
Pin Name
Ball number
Type
Description
TESTMODE
A20
I
IEEE 1149.1 test port reset
DDC_DATA
B12
I
TMS: Test Mode Select (IEEE 1149.1 test mode select)
I2C_DATA
B22
I
TDI: Test Mode Data In (IEEE 1149.1 data in)
STRP_DATA
B14
I
TCLK: Test Mode Clock (IEEE 1149.1 clock)
I2C_CLK
C21
O
TDO: Test Mode Data Out (IEEE 1149.1 data out)
7.3
XOR Tree
7.3.1
Brief Description of an XOR Tree
An example of a generic XOR tree is shown in the figure below.
XOR Start Signal
1
2
A
3
4
5
6
Figure 7-1 An Example of a Generic XOR Tree
RS600 Databook
7-1
XOR Tree
Pin A is assigned to the output direction, and pins 1 through 6 are assigned to the input direction. It can be seen that after
all pins 1 to 6 are assigned to logic 0 or 1, a logic change in any one of these pins will toggle the output pin A.
The following is the truth table for the XOR tree shown in Figure 7-1 The XOR start signal is assumed to be logic 1.
Table 7-2 Example of an XOR Tree
7.3.2
Test Vector
number
Input Pin 1
Input Pin 2
Input Pin 3
Input Pin 4
Input Pin 5
Input Pin 6
Output Pin A
1
0
0
0
0
0
0
1
2
1
0
0
0
0
0
0
3
1
1
0
0
0
0
1
4
1
1
1
0
0
0
0
5
1
1
1
1
0
0
1
6
1
1
1
1
1
0
0
7
1
1
1
1
1
1
1
Description of the XOR Tree for the RS600
The XOR start signal is applied at the TDI Pin of the JTAG circuitry and the output of the XOR tree is obtained at the
TDO Pin. Refer to Section 7.3.4 for the list of the signals included on the XOR tree. There is no specific order to these
signals in the tree. A toggle of any of these balls in the XOR tree will cause the output to toggle.
7.3.3
XOR Tree Activation
The RS600 chip enters the XOR tree test mode by means of the JTAG. First, the 8-bit instruction register of the JTAG is
loaded with the XOR instruction (“00001000”). This instruction will assign the input direction to all the pins except pin
TDO, which is assigned the output direction to serve as the output of the XOR tree. After loading, the JTAG is taken to
the Run-Test state for completion of the XOR tree initialization.
Note: 10 MHz clock frequency is recommended for the XOR TREE test mode.
7.3.4
XOR Chain for the RS600
Note: In the XOR tree test mode, for certain differential pin pairs, opposite values should be applied to the pair (e.g.,
when “1” is applied to MEMA_DQS1P, “0” should be applied to MEMA_DQS1N). These pins are highlighted by the
shading in the table below.
Connection
Order
Pin Name
Ball
Ref.
1
CPU_LOCK#
M45
2
CPU_HITM#
P46
3
CPU_HIT#
K47
4
CPU_REQ0#
P39
5
CPU_REQ1#
M39
6
CPU_REQ2#
K44
7
CPU_REQ3#
H42
8
CPU_REQ4#
K40
9
CPU_RS0#
L47
10
CPU_RS1#
R47
11
CPU_RS2#
L45
RS600 Databook
7-2
Connection
Order
Pin Name
Ball
Ref.
12
CPU_TRDY#
R45
13
CPU_DRDY#
P45
14
CPU_DEFER#
K46
15
CPU_DSTB3N#
B41
16
CPU_DSTB2N#
H29
17
CPU_DSTB1N#
J38
18
CPU_DSTB0N#
E46
19
CPU_DSTB3P#
C41
20
CPU_DSTB2P#
F29
21
CPU_DSTB1P#
J36
22
CPU_DSTB0P#
E45
XOR Tree
Connection
Order
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
23
CPU_ADSTB0#
T42
59
CPU_D25#
F36
24
CPU_ADSTB1#
AA44
60
CPU_D26#
E36
25
CPU_DBSY#
M46
61
CPU_D27#
J34
26
CPU_DBI0#
E47
62
CPU_D28#
F34
27
CPU_DBI1#
K36
63
CPU_D29#
H38
28
CPU_DBI2#
J30
64
CPU_D30#
D32
29
CPU_DBI3#
A36
65
CPU_D31#
E34
30
CPU_EDRDY#
T47
66
CPU_D32#
J32
31
CPU_BPRI#
H44
67
CPU_D33#
F32
32
CPU_BNR#
M47
68
CPU_D34#
K32
33
CPU_ADS#
R46
69
CPU_D35#
D29
34
CPU_D0#
H46
70
CPU_D36#
M29
35
CPU_D1#
G47
71
CPU_D37#
K30
36
CPU_D2#
K45
72
CPU_D38#
F30
37
CPU_D3#
G45
73
CPU_D39#
E30
38
CPU_D4#
H45
74
CPU_D40#
M27
39
CPU_D5#
G46
75
CPU_D41#
F27
40
CPU_D6#
F45
76
CPU_D42#
K27
41
CPU_D7#
F47
77
CPU_D43#
D25
42
CPU_D8#
C46
78
CPU_D44#
E27
43
CPU_D9#
A44
79
CPU_D45#
J27
44
CPU_D10#
D46
80
CPU_D46#
J25
45
CPU_D11#
C45
81
CPU_D47#
F25
46
CPU_D12#
D47
82
CPU_D48#
C37
47
CPU_D13#
B44
83
CPU_D49#
B40
48
CPU_D14#
A43
84
CPU_D50#
B43
49
CPU_D15#
B45
85
CPU_D51#
C42
50
CPU_D16#
E40
86
CPU_D52#
C43
51
CPU_D17#
F44
87
CPU_D53#
A42
52
CPU_D18#
E42
88
CPU_D54#
B38
53
CPU_D19#
F40
89
CPU_D55#
A41
54
CPU_D20#
H40
90
CPU_D56#
C40
55
CPU_D21#
D44
91
CPU_D57#
A38
56
CPU_D22#
D42
92
CPU_D58#
C36
57
CPU_D23#
D40
93
CPU_D59#
B36
58
CPU_D24#
E38
94
CPU_D60#
A37
RS600 Databook
7-3
XOR Tree
Connection
Order
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
95
CPU_D61#
C38
131
MEMA_A2
BG36
96
CPU_D62#
B34
132
MEMA_A3
BE34
97
CPU_D63#
C34
133
MEMA_A4
BF34
98
CPU_A3#
M42
134
MEMA_A5
BE33
99
CPU_A4#
K42
135
MEMA_A6
BF33
100
CPU_A5#
M44
136
MEMA_A7
BE32
101
CPU_A6#
T39
137
MEMA_A8
BG33
102
CPU_A7#
M38
138
MEMA_A9
BG32
103
CPU_A8#
P42
139
MEMA_A10
BE46
104
CPU_A9#
T43
140
MEMA_A11
BE31
105
CPU_A10#
P38
141
MEMA_A12
BF31
106
CPU_A11#
P44
142
MEMA_A13
AV45
107
CPU_A12#
P36
143
MEMA_A14
BF30
108
CPU_A13#
W39
144
MEMA_BA0
BD46
109
CPU_A14#
V40
145
MEMA_BA1
BD47
110
CPU_A15#
W42
146
MEMA_BA2
BE30
111
CPU_A16#
V42
147
MEMA_CS0#
BA46
112
CPU_A17#
AC39
148
MEMA_CS1#
AV46
113
CPU_A18#
W43
149
MEMA_CS2#
BA47
114
CPU_A19#
V44
150
MEMA_CS3#
AU45
115
CPU_A20#
V36
151
MEMA_CKE0
BF29
116
CPU_A21#
AA40
152
MEMA_CKE1
BG28
117
CPU_A22#
AC43
153
MEMA_WE#
BA45
118
CPU_A23#
V38
154
MEMA_CAS#
AY46
119
CPU_A24#
AA42
155
MEMA_RAS#
BC47
120
CPU_A25#
AA38
156
MEMA_ODT0
AY45
121
CPU_A26#
AC42
157
MEMA_ODT1
AU47
122
CPU_A27#
AD36
158
MEMA_ODT2
AV47
123
CPU_A28#
AD38
159
MEMA_ODT3
AT47
124
CPU_A29#
AA36
160
MEMA_CKE3
BE28
125
CPU_A30#
AD42
161
MEMA_DQ0
BC3
126
CPU_A31#
AD40
162
MEMA_DQ1
BD1
127
CPU_A32#
AD44
163
MEMA_DQ2
BF4
128
CPU_A33#
AD43
164
MEMA_DQ3
BE4
129
MEMA_A0
BE42
165
MEMA_DQ4
BC2
130
MEMA_A1
BF36
166
MEMA_DQ5
BC1
RS600 Databook
7-4
XOR Tree
Connection
Order
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
167
MEMA_DQ6
BE3
203
MEMA_DQ42
AG45
168
MEMA_DQ7
BF3
204
MEMA_DQ43
AF45
169
MEMA_DQ8
BF5
205
MEMA_DQ44
AK45
170
MEMA_DQ9
BG6
206
MEMA_DQ45
AJ47
171
MEMA_DQ10
BE8
207
MEMA_DQ46
AG46
172
MEMA_DQ11
BG10
208
MEMA_DQ47
AF46
173
MEMA_DQ12
BG5
209
MEMA_DQ48
AE46
174
MEMA_DQ13
BE5
210
MEMA_DQ49
AD47
175
MEMA_DQ14
BE7
211
MEMA_DQ50
AB45
176
MEMA_DQ15
BF8
212
MEMA_DQ51
AA47
177
MEMA_DQ16
BE10
213
MEMA_DQ52
AE47
178
MEMA_DQ17
BE11
214
MEMA_DQ53
AE45
179
MEMA_DQ18
BF15
215
MEMA_DQ54
AC45
180
MEMA_DQ19
BE15
216
MEMA_DQ55
AB46
181
MEMA_DQ20
BF10
217
MEMA_DQ56
AA45
182
MEMA_DQ21
BG11
218
MEMA_DQ57
Y46
183
MEMA_DQ22
BE14
219
MEMA_DQ58
V46
184
MEMA_DQ23
BG15
220
MEMA_DQ59
U47
185
MEMA_DQ24
BG17
221
MEMA_DQ60
AA46
186
MEMA_DQ25
BF17
222
MEMA_DQ61
Y47
187
MEMA_DQ26
BF19
223
MEMA_DQ62
V45
188
MEMA_DQ27
BE20
224
MEMA_DQ63
U45
189
MEMA_DQ28
BG16
225
MEMA_DM0
BD2
190
MEMA_DQ29
BE16
226
MEMA_DM1
BE6
191
MEMA_DQ30
BG19
227
MEMA_DM2
BG12
192
MEMA_DQ31
BE19
228
MEMA_DM3
BE17
193
MEMA_DQ32
AP45
229
MEMA_DM4
AN45
194
MEMA_DQ33
AN46
230
MEMA_DM5
AH47
195
MEMA_DQ34
AL45
231
MEMA_DM6
AD45
196
MEMA_DQ35
AK46
232
MEMA_DM7
W45
197
MEMA_DQ36
AP46
233
MEMA_DQS0P
BE2
198
MEMA_DQ37
AN47
234
MEMA_DQS1P
BF7
199
MEMA_DQ38
AL47
235
MEMA_DQS2P
BE12
200
MEMA_DQ39
AL46
236
MEMA_DQS3P
BE18
201
MEMA_DQ40
AJ46
237
MEMA_DQS4P
AM46
202
MEMA_DQ41
AJ45
238
MEMA_DQS5P
AG47
RS600 Databook
7-5
XOR Tree
Connection
Order
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
239
MEMA_DQS6P
AC46
275
MEMB_A14
BE23
240
MEMA_DQS7P
W46
276
MEMB_BA0
BG38
241
MEMA_DQS0N
BD3
277
MEMB_BA1
BE37
242
MEMA_DQS1N
BG7
278
MEMB_BA2
BG24
243
MEMA_DQS2N
BF12
279
MEMB_CS0#
BF40
244
MEMA_DQS3N
BF18
280
MEMB_CS1#
BF41
245
MEMA_DQS4N
AM47
281
MEMB_CS2#
BE38
246
MEMA_DQS5N
AH46
282
MEMB_CKE1
BG23
247
MEMA_DQS6N
AC47
283
MEMB_CAS#
BG41
248
MEMA_DQS7N
W47
284
MEMB_RAS#
BF38
249
MEMA_CK0P
BB30
285
MEMB_ODT0
BC46
250
MEMA_CK1P
AY8
286
MEMB_ODT1
BC45
251
MEMA_CK2P
AV43
287
MEMB_ODT2
BB47
252
MEMA_CK3P
BD30
288
MEMB_ODT3
BB45
253
MEMA_CK4P
AW12
289
MEMB_CKE3
BF22
254
MEMA_CK5P
AY44
290
MEMB_DQ0
AV5
255
MEMA_CK0N
BB29
291
MEMB_DQ1
AV6
256
MEMA_CK1N
AY10
292
MEMB_DQ2
BC6
257
MEMA_CK2N
AV44
293
MEMB_DQ3
BD6
258
MEMA_CK3N
BD29
294
MEMB_DQ4
AT8
259
MEMA_CK4N
AY12
295
MEMB_DQ5
AV4
260
MEMA_CK5N
AY43
296
MEMB_DQ6
BB4
261
MEMB_A0
BE36
297
MEMB_DQ7
AV9
262
MEMB_A1
BG31
298
MEMB_DQ8
BC14
263
MEMB_A2
BE29
299
MEMB_DQ9
AY14
264
MEMB_A3
BE27
300
MEMB_DQ10
BD18
265
MEMB_A4
BF27
301
MEMB_DQ11
BC16
266
MEMB_A5
BG27
302
MEMB_DQ12
BB14
267
MEMB_A6
BE26
303
MEMB_DQ13
BD12
268
MEMB_A7
BE25
304
MEMB_DQ14
BB16
269
MEMB_A8
BF26
305
MEMB_DQ15
BB18
270
MEMB_A9
BF25
306
MEMB_DQ16
AT18
271
MEMB_A10
BG37
307
MEMB_DQ17
AW19
272
MEMB_A11
BG25
308
MEMB_DQ18
AW23
273
MEMB_A12
BE24
309
MEMB_DQ19
AY24
274
MEMB_A13
BG42
310
MEMB_DQ20
AY18
RS600 Databook
7-6
XOR Tree
Connection
Order
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
311
MEMB_DQ21
AV19
347
MEMB_DQ57
AK44
312
MEMB_DQ22
BB21
348
MEMB_DQ58
AJ42
313
MEMB_DQ23
AY21
349
MEMB_DQ59
AG44
314
MEMB_DQ24
BB23
350
MEMB_DQ60
AK36
315
MEMB_DQ25
AV23
351
MEMB_DQ61
AM43
316
MEMB_DQ26
BD27
352
MEMB_DQ62
AM39
317
MEMB_DQ27
BB25
353
MEMB_DQ63
AJ43
318
MEMB_DQ28
BC23
354
MEMB_DM0
AY4
319
MEMB_DQ29
BD24
355
MEMB_DM1
AV14
320
MEMB_DQ30
BC25
356
MEMB_DM2
BB19
321
MEMB_DQ31
BB27
357
MEMB_DM3
AT24
322
MEMB_DQ32
AW30
358
MEMB_DM4
BB32
323
MEMB_DQ33
AV32
359
MEMB_DM5
AW38
324
MEMB_DQ34
AW34
360
MEMB_DM6
AT38
325
MEMB_DQ35
BB36
361
MEMB_DM7
AM42
326
MEMB_DQ36
AY29
362
MEMB_DQS0P
AY6
327
MEMB_DQ37
AT32
363
MEMB_DQS1P
AW16
328
MEMB_DQ38
BB34
364
MEMB_DQS2P
BD19
329
MEMB_DQ39
AY32
365
MEMB_DQS3P
AW27
330
MEMB_DQ40
BD38
366
MEMB_DQS4P
BD32
331
MEMB_DQ41
AY36
367
MEMB_DQS5P
BC38
332
MEMB_DQ42
AY38
368
MEMB_DQS6P
AP44
333
MEMB_DQ43
BC40
369
MEMB_DQS7P
AK40
334
MEMB_DQ44
BB38
370
MEMB_DQS0N
AY5
335
MEMB_DQ45
BC36
371
MEMB_DQS1N
AV16
336
MEMB_DQ46
BB40
372
MEMB_DQS2N
BD21
337
MEMB_DQ47
BD42
373
MEMB_DQS3N
AW25
338
MEMB_DQ48
AV40
374
MEMB_DQS4N
BD34
339
MEMB_DQ49
AT40
375
MEMB_DQS5N
BD40
340
MEMB_DQ50
AP40
376
MEMB_DQS6N
AT44
341
MEMB_DQ51
AT39
377
MEMB_DQS7N
AK42
342
MEMB_DQ52
AY40
378
MEMB_CK0P
AT30
343
MEMB_DQ53
AV39
379
MEMB_CK1P
BD10
344
MEMB_DQ54
AT42
380
MEMB_CK2P
BB44
345
MEMB_DQ55
AP42
381
MEMB_CK3P
AV25
346
MEMB_DQ56
AM38
382
MEMB_CK4P
BD8
RS600 Databook
7-7
XOR Tree
Connection
Order
7.3.5
Pin Name
Ball
Ref.
Connection
Order
Pin Name
Ball
Ref.
383
MEMB_CK5P
BE44
413
GFX_RX11P
AA6
384
MEMB_CK0N
AV29
414
GFX_RX12N
AA10
385
MEMB_CK1N
BC10
415
GFX_RX12P
AA9
386
MEMB_CK2N
BB43
416
GFX_RX13N
AC6
387
MEMB_CK3N
AT25
417
GFX_RX13P
AC5
388
MEMB_CK4N
BC8
418
GFX_RX14N
AC10
389
MEMB_CK5N
BD44
419
GFX_RX14P
AC9
390
GFX_RX0N
C2
420
GFX_RX15N
AE5
391
GFX_RX0P
C3
421
GFX_RX15P
AE6
392
GFX_RX1N
H4
422
GPP_RX3N
AG6
393
GFX_RX1P
H5
423
GPP_RX3P
AG5
394
GFX_RX2N
K6
424
GPP_RX2N
AJ1
395
GFX_RX2P
K8
425
GPP_RX2P
AJ2
396
GFX_RX3N
M6
426
GPP_RX1N
AM1
397
GFX_RX3P
M8
427
GPP_RX1P
AM2
398
GFX_RX4N
M4
428
GPP_RX0N
AK5
399
GFX_RX4P
M5
429
GPP_RX0P
AK6
400
GFX_RX5N
P8
430
SB_RX0N
AV3
401
GFX_RX5P
P9
431
SB_RX0P
AU3
402
GFX_RX6N
P5
432
SB_RX1N
AM10
403
GFX_RX6P
P4
433
SB_RX1P
AM9
404
GFX_RX7N
T5
434
SB_RX2N
AM6
405
GFX_RX7P
T6
435
SB_RX2P
AM5
406
GFX_RX8N
T10
436
SB_RX3N
AK10
407
GFX_RX8P
T9
437
SB_RX3P
AK9
408
GFX_RX9N
V6
438
GPIO9
D3
409
GFX_RX9P
V5
439
GPIO8
C5
410
GFX_RX10N
V10
440
GPIO10
C4
411
GFX_RX10P
V9
441
DACHSYNC
B24
412
GFX_RX11N
AA5
442
DACVSYNC
B23
Unused Pins
When the XOR tree is activated, any pin on the XOR tree must be either pulled down or pulled up to the I/O voltage of the
interface to which the pin belongs. No pins on the XOR tree should be left floating. All pins that are not part of the XOR
tree can be left floating, except for the pin MEMB_CKE2, which must be pulled down due to special internal function
of the pin.
RS600 Databook
7-8
Appendix A
Pin Listings
This appendix contains pin listings for the RS600 sorted in different ways. To go to the listing of interest, use the linked
cross-references below:
“Pin List Sorted by Ball Reference” on page A-2
“Pin List Sorted by Pin Name” on page A-14
RS600 Databook
A-1
A.1
Pin List Sorted by Ball Reference
Table A-1 Pin List Sorted by Ball Reference
Ball
Ref.
Pin Name
A10
VDD_PCIE
A11
PLLVSS
A12
PLLVDD12
A14
PLLVDD18
A15
VDD_18CPU
A16
VDD_CORE
A17
AVDD
A18
VDDR3
A19
AVSSDI
A20
TESTMODE
A21
LTPVSS18
A22
DACSDA
A23
AVDDQ
A24
AVSSQ
A25
DACRSET
A26
VSSLT
A27
TXCLK_LN
A28
TXOUT_L0P
A29
TXOUT_L2P
A3
VSS_PCIE
A30
VSSLT
A31
CPU_COMP_N
A32
CPU_VREF
A33
VDD_CPU
A34
VSS
A36
CPU_DBI3#
A37
CPU_D60#
A38
CPU_D57#
A4
VSS
A40
VSS
A41
CPU_D55#
A42
CPU_D53#
A43
CPU_D14#
RS600 Databook
A-2
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
A44
CPU_D9#
AB23
VSS
A45
VSS
AB25
VDD_CORE
A5
GFX_REFCLKP
AB26
VSS
A6
GPPSB_REFCLKP
AB28
VDD_CORE
A7
CPU_CLKP
AB29
VSS
A8
VDD_PCIE
AB3
VSS_PCIE
AA1
GFX_TX11N
AB30
VDD_CORE
AA10
GFX_RX12N
AB45
MEMA_DQ50
AA12
VDD_PCIE
AB46
MEMA_DQ55
AA13
VDD_PCIE
AB47
VSS
AA2
GFX_TX11P
AC1
GFX_TX12N
AA3
VSS_PCIE
AC10
GFX_RX14N
AA35
IOPLLVDD18
AC12
VSS_PCIE
AA36
CPU_A29#
AC13
VDD_PCIE
AA38
CPU_A25#
AC18
VDD_CORE
AA39
VSS
AC19
VSS
AA4
VSS_PCIE
AC2
VSS_PCIE
AA40
CPU_A21#
AC20
VDD_CORE
AA42
CPU_A24#
AC22
VSS
AA43
VSS
AC23
VDD_CORE
AA44
CPU_ADSTB1#
AC25
VSS
AA45
MEMA_DQ56
AC26
VDD_CORE
AA46
MEMA_DQ60
AC28
VSS
AA47
MEMA_DQ51
AC29
VDD_CORE
AA5
GFX_RX11N
AC3
VSS_PCIE
AA6
GFX_RX11P
AC30
VSS
AA8
VSS_PCIE
AC35
VDD_CPU
AA9
GFX_RX12P
AC36
VDD_CPU
AB1
VSS_PCIE
AC38
VSS
AB18
VSS
AC39
CPU_A17#
AB19
VDD_CORE
AC4
VSS_PCIE
AB2
GFX_TX12P
AC40
VSS
AB20
VSS
AC42
CPU_A26#
AB22
VDD_CORE
AC43
CPU_A22#
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
AC44
VSS
AE2
GFX_TX14P
AF29
VDD_CORE
AC45
MEMA_DQ54
AE20
VSS
AF3
VSS_PCIE
AC46
MEMA_DQS6P
AE22
VDD_CORE
AF30
VSS
AC47
MEMA_DQS6N
AE23
VSS
AF45
MEMA_DQ43
AC5
GFX_RX13P
AE25
VDD_CORE
AF46
MEMA_DQ47
AC6
GFX_RX13N
AE26
VSS
AF47
VSS
AC8
VSS_PCIE
AE28
VDD_CORE
AG1
GFX_TX15N
AC9
GFX_RX14P
AE29
VSS
AG10
GPP_TX0N
AD1
GFX_TX13N
AE3
VSS_PCIE
AG12
VSS_PCIE
AD10
VSS_PCIE
AE30
VDD_CORE
AG13
VDD_PCIE
AD12
VSS_PCIE
AE35
VDD_MEM
AG2
VSS_PCIE
AD13
VDD_PCIE
AE36
VDD_MEM
AG3
VSS_PCIE
AD2
GFX_TX13P
AE38
VDD_MEM
AG35
VDD_MEM
AD3
VSS_PCIE
AE39
VSS
AG36
VDD_MEM
AD35
VDD_18MEM
AE4
VSS_PCIE
AG38
VDD_MEM
AD36
CPU_A27#
AE40
VSS
AG39
VDD_MEM
AD38
CPU_A28#
AE42
VSS
AG4
VSS_PCIE
AD39
VSS
AE43
VSS
AG40
VSS
AD4
VSS_PCIE
AE44
VSS
AG42
VSS
AD40
CPU_A31#
AE45
MEMA_DQ53
AG43
VSS
AD42
CPU_A30#
AE46
MEMA_DQ48
AG44
MEMB_DQ59
AD43
CPU_A33#
AE47
MEMA_DQ52
AG45
MEMA_DQ42
AD44
CPU_A32#
AE5
GFX_RX15N
AG46
MEMA_DQ46
AD45
MEMA_DM6
AE6
GFX_RX15P
AG47
MEMA_DQS5P
AD46
VSS
AE8
VSS_PCIE
AG5
GPP_RX3P
AD47
MEMA_DQ49
AE9
GPP_TX3P
AG6
GPP_RX3N
AD5
VSS_PCIE
AF1
VSS_PCIE
AG8
VSS_PCIE
AD6
VSS_PCIE
AF18
VDD_CORE
AG9
GPP_TX0P
AD8
VSS_PCIE
AF19
VSS
AH1
GPP_TX2N
AD9
VSS_PCIE
AF2
GFX_TX15P
AH18
VSS
AE1
GFX_TX14N
AF20
VDD_CORE
AH19
VDD_CORE
AE10
GPP_TX3N
AF22
VSS
AH2
GPP_TX2P
AE12
VSS_PCIE
AF23
VDD_CORE
AH20
VSS
AE13
VDD_PCIE
AF25
VSS
AH22
VDD_CORE
AE18
VSS
AF26
VDD_CORE
AH23
VSS
AE19
VDD_CORE
AF28
VSS
AH25
VDD_CORE
RS600 Databook
A-3
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
AH26
VSS
AJ42
MEMB_DQ58
AK4
VSS_PCIE
AH28
VDD_CORE
AJ43
MEMB_DQ63
AK40
MEMB_DQS7P
AH29
VSS
AJ44
VSS
AK42
MEMB_DQS7N
AH3
VSS_PCIE
AJ45
MEMA_DQ41
AK43
VSS
AH30
VDD_CORE
AJ46
MEMA_DQ40
AK44
MEMB_DQ57
AH45
VSS
AJ47
MEMA_DQ45
AK45
MEMA_DQ44
AH46
MEMA_DQS5N
AJ5
VSS_PCIE
AK46
MEMA_DQ35
AH47
MEMA_DM5
AJ6
VSS_PCIE
AK47
VSS
AJ1
GPP_RX2N
AJ8
VSS_PCIE
AK5
GPP_RX0N
AJ10
VSS_PCIE
AJ9
VSS_PCIE
AK6
GPP_RX0P
AJ12
VSS_PCIE
AK1
VSS_PCIE
AK8
VSS_PCIE
AJ13
VDD_PCIE
AK10
SB_RX3N
AK9
SB_RX3P
AJ15
VDD_PCIE
AK12
VSS_PCIE
AL1
GPP_TX1N
AJ16
VDD_18MEM
AK13
VDD_PCIE
AL15
VDD_PCIE
AJ17
VDD_CORE
AK15
VDD_PCIE
AL16
VDD_18MEM
AJ18
VDD_CORE
AK16
VDD_18MEM
AL17
VDD_CORE
AJ19
VSS
AK17
VDD_CORE
AL18
VDD_CORE
AJ2
GPP_RX2P
AK18
VSS
AL19
VDD_CORE
AJ20
VDD_CORE
AK19
VDD_CORE
AL2
VSS_PCIE
AJ22
VSS
AK2
GPP_TX1P
AL29
VDD_CORE
AJ23
VDD_CORE
AK20
VSS
AL3
VSS_PCIE
AJ25
VSS
AK22
VDD_CORE
AL30
VDD_CORE
AJ26
VDD_CORE
AK23
VSS
AL31
VDD_CORE
AJ28
VSS
AK25
VDD_CORE
AL32
VDD_18MEM
AJ29
VDD_CORE
AK26
VSS
AL33
VDD_MEM
AJ3
VSS_PCIE
AK28
VDD_CORE
AL45
MEMA_DQ34
AJ30
VSS
AK29
VSS
AL46
MEMA_DQ39
AJ31
VDD_CORE
AK3
VSS_PCIE
AL47
MEMA_DQ38
AJ32
VDD_18MEM
AK30
VDD_CORE
AM1
GPP_RX1N
AJ33
VDD_MEM
AK31
VDD_CORE
AM10
SB_RX1N
AJ35
VDD_MEM
AK32
VDD_18MEM
AM12
VDD_PCIE
AJ36
VDD_MEM
AK33
VDD_MEM
AM13
VDD_PCIE
AJ38
VSS
AK35
VDD_MEM
AM15
VDD_PCIE
AJ39
VSS
AK36
MEMB_DQ60
AM16
VDD_18MEM
AJ4
VSS_PCIE
AK38
VDD_MEM
AM17
VDD_18MEM
AJ40
VSS
AK39
VSS
AM18
VDD_18MEM
RS600 Databook
A-4
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
AM19
VDD_18MEM
AN33
VDD_MEM
AR30
VDD_MEM
AM2
GPP_RX1P
AN45
MEMA_DM4
AR32
VDD_MEM
AM29
VDD_18MEM
AN46
MEMA_DQ33
AR34
VDD_MEM
AM3
VSS_PCIE
AN47
MEMA_DQ37
AT1
SB_TX2N
AM30
VDD_18MEM
AP1
VDD_PCIE
AT10
VSS
AM31
VDD_18MEM
AP10
VSS_PCIE
AT12
VSS
AM32
VDD_18MEM
AP12
VDD_PCIE
AT14
VDD_MEM
AM33
VDD_18MEM
AP13
VDD_PCIE
AT16
VDD_MEM
AM35
VDD_MEM
AP2
SB_TX2P
AT18
MEMB_DQ16
AM36
VDD_MEM
AP3
VDD_PCIE
AT19
VDD_MEM
AM38
MEMB_DQ56
AP35
VDD_MEM
AT2
VSS_PCIE
AM39
MEMB_DQ62
AP36
VDD_MEM
AT21
VDD_MEM
AM4
VSS_PCIE
AP38
VDD_MEM
AT23
VDD_MEM
AM40
VSS
AP39
VSS
AT24
MEMB_DM3
AM42
MEMB_DM7
AP4
VSS_PCIE
AT25
MEMB_CK3N
AM43
MEMB_DQ61
AP40
MEMB_DQ50
AT27
VDD_MEM
AM44
VSS
AP42
MEMB_DQ55
AT29
VDD_MEM
AM45
VSS
AP43
VSS
AT3
VSS_PCIE
AM46
MEMA_DQS4P
AP44
MEMB_DQS6P
AT30
MEMB_CK0P
AM47
MEMA_DQS4N
AP45
MEMA_DQ32
AT32
MEMB_DQ37
AM5
SB_RX2P
AP46
MEMA_DQ36
AT34
VDD_MEM
AM6
SB_RX2N
AP47
VSS
AT36
VDD_MEM
AM8
VSS_PCIE
AP5
VSS_PCIE
AT38
MEMB_DM6
AM9
SB_RX1P
AP6
VSS_PCIE
AT39
MEMB_DQ51
AN1
SB_TX3N
AP8
VSS_PCIE
AT4
THERMALDIODE_N
AN15
VDD_PCIE
AP9
VSS_PCIE
AT40
MEMB_DQ49
AN16
VDD_18MEM
AR14
VDD_MEM
AT42
MEMB_DQ54
AN17
VDD_MEM
AR16
VDD_MEM
AT43
VSS
AN18
VDD_MEM
AR18
VDD_MEM
AT44
MEMB_DQS6N
AN19
VDD_MEM
AR19
VDD_MEM
AT45
MEM_COMPN
AN2
SB_TX3P
AR21
VDD_MEM
AT46
MEM_COMPP
AN29
VDD_MEM
AR23
VDD_MEM
AT47
MEMA_ODT3
AN3
VSS_PCIE
AR24
VDD_MEM
AT5
THERMALDIODE_P
AN30
VDD_MEM
AR25
VDD_MEM
AT6
VSS
AN31
VDD_MEM
AR27
VDD_18MEM
AT8
MEMB_DQ4
AN32
VDD_MEM
AR29
VDD_MEM
AT9
SUS_STAT#
RS600 Databook
A-5
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
AU1
SB_TX1N
AV9
MEMB_DQ7
AY36
MEMB_DQ41
AU2
SB_TX1P
AW10
VSS
AY38
MEMB_DQ42
AU3
SB_RX0P
AW12
MEMA_CK4P
AY4
MEMB_DM0
AU45
MEMA_CS3#
AW14
VSS
AY40
MEMB_DQ52
AU46
VSS
AW16
MEMB_DQS1P
AY42
VSS
AU47
MEMA_ODT1
AW18
VSS
AY43
MEMA_CK5N
AV1
SB_TX0P
AW19
MEMB_DQ17
AY44
MEMA_CK5P
AV12
VSS
AW21
VSS
AY45
MEMA_ODT0
AV14
MEMB_DM1
AW23
MEMB_DQ18
AY46
MEMA_CAS#
AV16
MEMB_DQS1N
AW24
VSS
AY47
VSS
AV18
VDD_MEM
AW25
MEMB_DQS3N
AY5
MEMB_DQS0N
AV19
MEMB_DQ21
AW27
MEMB_DQS3P
AY6
MEMB_DQS0P
AV2
SB_TX0N
AW29
VSS
AY8
MEMA_CK1P
AV21
VDD_MEM
AW30
MEMB_DQ32
B10
VDD_PCIE
AV23
MEMB_DQ25
AW32
VSS
B11
OSCIN
AV24
VDD_MEM
AW34
MEMB_DQ34
B12
DDC_DATA
AV25
MEMB_CK3P
AW36
VSS
B14
STRP_DATA
AV27
VDD_MEM
AW38
MEMB_DM5
B15
VDD_18MEM
AV29
MEMB_CK0N
AY1
VSS_PCIE
B16
VDD_CORE
AV3
SB_RX0N
AY10
MEMA_CK1N
B17
AVDD
AV30
VDD_MEM
AY12
MEMA_CK4N
B18
VDDR3
AV32
MEMB_DQ33
AY14
MEMB_DQ9
B19
AVDDDI
AV34
VDD_MEM
AY16
VSS
B2
VSS_PCIE
AV36
VDD_MEM
AY18
MEMB_DQ20
B21
LTPVDD18
AV39
MEMB_DQ53
AY19
VSS
B22
I2C_DATA
AV4
MEMB_DQ5
AY2
VSS_PCIE
B23
DACVSYNC
AV40
MEMB_DQ48
AY21
MEMB_DQ23
B24
DACHSYNC
AV42
VSS
AY23
VSS
B26
TMDS_HPD
AV43
MEMA_CK2P
AY24
MEMB_DQ19
B27
TXCLK_LP
AV44
MEMA_CK2N
AY25
VSS
B28
TXOUT_L0N
AV45
MEMA_A13
AY27
VSS
B29
TXOUT_L2N
AV46
MEMA_CS1#
AY29
MEMB_DQ36
B3
VSS_PCIE
AV47
MEMA_ODT2
AY3
VSS_PCIE
B30
TXOUT_L1P
AV5
MEMB_DQ0
AY30
VSS
B31
VSS
AV6
MEMB_DQ1
AY32
MEMB_DQ39
B32
CPU_COMP_P
AV8
VSS
AY34
VSS
B33
VDD_CPU
RS600 Databook
A-6
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
B34
CPU_D62#
BB3
VSS_PCIE
BC46
MEMB_ODT0
B36
CPU_D59#
BB30
MEMA_CK0P
BC47
MEMA_RAS#
B37
VSS
BB32
MEMB_DM4
BC6
MEMB_DQ2
B38
CPU_D54#
BB34
MEMB_DQ38
BC8
MEMB_CK4N
B4
GFX_REFCLKN
BB36
MEMB_DQ35
BD1
MEMA_DQ1
B40
CPU_D49#
BB38
MEMB_DQ44
BD10
MEMB_CK1P
B41
CPU_DSTB3N#
BB4
MEMB_DQ6
BD12
MEMB_DQ13
B42
VSS
BB40
MEMB_DQ46
BD14
VSS
B43
CPU_D50#
BB43
MEMB_CK2N
BD16
VSS
B44
CPU_D13#
BB44
MEMB_CK2P
BD18
MEMB_DQ10
B45
CPU_D15#
BB45
MEMB_ODT3
BD19
MEMB_DQS2P
B46
VSS
BB46
VSS
BD2
MEMA_DM0
B5
VSS
BB47
MEMB_ODT2
BD21
MEMB_DQS2N
B6
GPPSB_REFCLKN
BB8
VSS
BD23
VSS
B7
CPU_CLKN
BC1
MEMA_DQ5
BD24
MEMB_DQ29
B8
VDD_PCIE
BC10
MEMB_CK1N
BD25
VSS
BA1
PCE_CALRP
BC12
VSS
BD27
MEMB_DQ26
BA2
PCE_CALRN
BC14
MEMB_DQ8
BD29
MEMA_CK3N
BA3
PCE_CALI
BC16
MEMB_DQ11
BD3
MEMA_DQS0N
BA45
MEMA_WE#
BC18
VSS
BD30
MEMA_CK3P
BA46
MEMA_CS0#
BC19
VSS
BD32
MEMB_DQS4P
BA47
MEMA_CS2#
BC2
MEMA_DQ4
BD34
MEMB_DQS4N
BB1
VSS_PCIE
BC21
VSS
BD36
VSS
BB10
VSS
BC23
MEMB_DQ28
BD38
MEMB_DQ40
BB12
VSS
BC24
VSS
BD4
VSS
BB14
MEMB_DQ12
BC25
MEMB_DQ30
BD40
MEMB_DQS5N
BB16
MEMB_DQ14
BC27
VSS
BD42
MEMB_DQ47
BB18
MEMB_DQ15
BC29
VSS
BD44
MEMB_CK5N
BB19
MEMB_DM2
BC3
MEMA_DQ0
BD45
VDD_MEM
BB2
VSS_PCIE
BC30
VSS
BD46
MEMA_BA0
BB21
MEMB_DQ22
BC32
VSS
BD47
MEMA_BA1
BB23
MEMB_DQ24
BC34
VSS
BD6
MEMB_DQ3
BB24
VSS
BC36
MEMB_DQ45
BD8
MEMB_CK4P
BB25
MEMB_DQ27
BC38
MEMB_DQS5P
BE1
VSS
BB27
MEMB_DQ31
BC40
MEMB_DQ43
BE10
MEMA_DQ16
BB29
MEMA_CK0N
BC45
MEMB_ODT1
BE11
MEMA_DQ17
RS600 Databook
A-7
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
BE12
MEMA_DQS2P
BE5
MEMA_DQ13
BF42
VSS
BE14
MEMA_DQ22
BE6
MEMA_DM1
BF43
VSS
BE15
MEMA_DQ19
BE7
MEMA_DQ14
BF44
VSS
BE16
MEMA_DQ29
BE8
MEMA_DQ10
BF45
MEMB_CS3#
BE17
MEMA_DM3
BF10
MEMA_DQ20
BF46
VDD_MEM
BE18
MEMA_DQS3P
BF11
VSS
BF5
MEMA_DQ8
BE19
MEMA_DQ31
BF12
MEMA_DQS2N
BF6
VSS
BE2
MEMA_DQS0P
BF14
VSS
BF7
MEMA_DQS1P
BE20
MEMA_DQ27
BF15
MEMA_DQ18
BF8
MEMA_DQ15
BE21
VSS
BF16
VSS
BG10
MEMA_DQ11
BE22
MEMB_CKE2
BF17
MEMA_DQ25
BG11
MEMA_DQ21
BE23
MEMB_A14
BF18
MEMA_DQS3N
BG12
MEMA_DM2
BE24
MEMB_A12
BF19
MEMA_DQ26
BG14
VSS
BE25
MEMB_A7
BF2
VSS
BG15
MEMA_DQ23
BE26
MEMB_A6
BF20
VSS
BG16
MEMA_DQ28
BE27
MEMB_A3
BF21
VSS
BG17
MEMA_DQ24
BE28
MEMA_CKE3
BF22
MEMB_CKE3
BG18
VSS
BE29
MEMB_A2
BF23
MEMB_CKE0
BG19
MEMA_DQ30
BE3
MEMA_DQ6
BF24
VSS
BG20
VSS
BE30
MEMA_BA2
BF25
MEMB_A9
BG21
VSS
BE31
MEMA_A11
BF26
MEMB_A8
BG22
VDD_MEM
BE32
MEMA_A7
BF27
MEMB_A4
BG23
MEMB_CKE1
BE33
MEMA_A5
BF28
VSS
BG24
MEMB_BA2
BE34
MEMA_A3
BF29
MEMA_CKE0
BG25
MEMB_A11
BE36
MEMB_A0
BF3
MEMA_DQ7
BG26
VDD_MEM
BE37
MEMB_BA1
BF30
MEMA_A14
BG27
MEMB_A5
BE38
MEMB_CS2#
BF31
MEMA_A12
BG28
MEMA_CKE1
BE4
MEMA_DQ3
BF32
VSS
BG29
MEMA_CKE2
BE40
MEMB_WE#
BF33
MEMA_A6
BG3
VSS
BE41
VSS
BF34
MEMA_A4
BG30
VDD_MEM
BE42
MEMA_A0
BF36
MEMA_A1
BG31
MEMB_A1
BE43
VSS
BF37
VSS
BG32
MEMA_A9
BE44
MEMB_CK5P
BF38
MEMB_RAS#
BG33
MEMA_A8
BE45
VDD_MEM
BF4
MEMA_DQ2
BG34
VDD_MEM
BE46
MEMA_A10
BF40
MEMB_CS0#
BG36
MEMA_A2
BE47
VSS
BF41
MEMB_CS1#
BG37
MEMB_A10
RS600 Databook
A-8
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
BG38
MEMB_BA0
C33
VDD_CPU
D36
VSS
BG4
VSS
C34
CPU_D63#
D38
VSS
BG40
VDD_MEM
C36
CPU_D58#
D4
VSS
BG41
MEMB_CAS#
C37
CPU_D48#
D40
CPU_D23#
BG42
MEMB_A13
C38
CPU_D61#
D42
CPU_D22#
BG43
VSS
C4
GPIO10
D44
CPU_D21#
BG44
MEM_VREF
C40
CPU_D56#
D45
VSS
BG45
VDD_MEM
C41
CPU_DSTB3P#
D46
CPU_D10#
BG5
MEMA_DQ12
C42
CPU_D51#
D47
CPU_D12#
BG6
MEMA_DQ9
C43
CPU_D52#
D6
VSS
BG7
MEMA_DQS1N
C44
VSS
D8
VDD_PCIE
BG8
VSS
C45
CPU_D11#
E1
GFX_TX0N
C1
VSS_PCIE
C46
CPU_D8#
E10
VSS
C10
VDD_PCIE
C47
VSS
E12
VSS
C11
VSS
C5
GPIO8
E14
VDD_18CPU
C12
VSS
C6
VSS
E16
VDD_CORE
C14
VSS
C7
VDD_PCIE
E18
VSS
C15
VDD_18CPU
C8
VDD_PCIE
E19
VSS
C16
VDD_CORE
D1
VSS_PCIE
E2
VSS_PCIE
C17
CPU_SLP#
D10
SYSRESET#
E21
TXCLK_UN
C19
VSS
D12
VSS
E23
TXOUT_U3N
C2
GFX_RX0N
D14
VDD_18MEM
E24
TXOUT_U1P
C20
VSS
D16
VDD_CORE
E25
VSS
C21
I2C_CLK
D18
COMP
E27
CPU_D44#
C22
VSS
D19
RED
E29
VSS
C23
VSS
D2
GFX_TX0P
E3
VSS_PCIE
C24
TXOUT_U0N
D21
VSS
E30
CPU_D39#
C25
TXOUT_U0P
D23
VSS
E32
VSS
C26
VSS
D24
TXOUT_U1N
E34
CPU_D31#
C27
TXOUT_L3P
D25
CPU_D43#
E36
CPU_D26#
C28
TXOUT_L3N
D27
VSS
E38
CPU_D24#
C29
VSSLT
D29
CPU_D35#
E40
CPU_D16#
C3
GFX_RX0P
D3
GPIO9
E42
CPU_D18#
C30
TXOUT_L1N
D30
VSS
E45
CPU_DSTB0P#
C31
VDD_CPU
D32
CPU_D30#
E46
CPU_DSTB0N#
C32
VDD_CPU
D34
VSS
E47
CPU_DBI0#
RS600 Databook
A-9
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
E8
VDD_PCIE
H10
VDD_PCIE
J21
TXOUT_U2P
F1
GFX_TX1N
H12
VSS
J23
VDDLT33
F10
POWERGOOD
H14
VDD_18CPU
J24
VDDLT18
F12
VSS
H16
VDD_CORE
J25
CPU_D46#
F14
VDD_18MEM
H18
VSS
J27
CPU_D45#
F16
VDD_CORE
H19
VSS
J29
VDD_CPU
F18
Y
H2
GFX_TX3P
J30
CPU_DBI2#
F19
GREEN
H21
TXOUT_U2N
J32
CPU_D32#
F2
GFX_TX1P
H23
VDDLT33
J34
CPU_D27#
F21
TXCLK_UP
H24
VDDLT18
J36
CPU_DSTB1P#
F23
TXOUT_U3P
H25
VSS
J38
CPU_DSTB1N#
F24
VSSLT
H27
VSS
K1
GFX_TX3N
F25
CPU_D47#
H29
CPU_DSTB2N#
K12
VDD_PCIE
F27
CPU_D41#
H3
VSS_PCIE
K14
VDD_PCIE
F29
CPU_DSTB2P#
H30
VDD_CPU
K16
VDD_18CPU
F3
VSS_PCIE
H32
VDD_CPU
K18
VSS
F30
CPU_D38#
H34
VSS
K19
VSS
F32
CPU_D33#
H36
VSS
K2
VSS_PCIE
F34
CPU_D28#
H38
CPU_D29#
K21
VSS
F36
CPU_D25#
H4
GFX_RX1N
K23
VSS
F38
VSS
H40
CPU_D20#
K24
VSS
F4
VSS_PCIE
H42
CPU_REQ3#
K25
CPU_CPURST#
F40
CPU_D19#
H43
VSS
K27
CPU_D42#
F44
CPU_D17#
H44
CPU_BPRI#
K29
VDD_CPU
F45
CPU_D6#
H45
CPU_D4#
K3
VSS_PCIE
F46
VSS
H46
CPU_D0#
K30
CPU_D37#
F47
CPU_D7#
H47
VSS
K32
CPU_D34#
F5
VSS
H5
GFX_RX1P
K34
VSS
F8
VDD_PCIE
H6
VSS_PCIE
K36
CPU_DBI1#
G1
GFX_TX2N
H8
VDD_PCIE
K39
VSS
G2
GFX_TX2P
J10
VDD_PCIE
K4
VSS_PCIE
G3
VSS_PCIE
J12
VSS
K40
CPU_REQ4#
G45
CPU_D3#
J14
VDD_18MEM
K42
CPU_A4#
G46
CPU_D5#
J16
VDD_CORE
K43
VSS
G47
CPU_D1#
J18
C
K44
CPU_REQ2#
H1
VSS_PCIE
J19
BLUE
K45
CPU_D2#
RS600 Databook
A-10
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
K46
CPU_DEFER#
M43
VSS
P44
CPU_A11#
K47
CPU_HIT#
M44
CPU_A5#
P45
CPU_DRDY#
K5
VSS_PCIE
M45
CPU_LOCK#
P46
CPU_HITM#
K6
GFX_RX2N
M46
CPU_DBSY#
P47
K8
GFX_RX2P
M47
CPU_BNR#
VDD_CPU_PACKAG
E
K9
VDD_PCIE
M5
GFX_RX4P
P5
GFX_RX6N
L1
GFX_TX4N
M6
GFX_RX3N
P6
VSS_PCIE
L2
GFX_TX4P
M8
GFX_RX3P
P8
GFX_RX5N
L3
VSS_PCIE
M9
VSS_PCIE
P9
GFX_RX5P
L45
CPU_RS2#
N14
VDD_PCIE
R1
GFX_TX6N
L46
VSS
N16
VDD_18MEM
R15
VDD_PCIE
L47
CPU_RS0#
N18
VSS
R16
VDD_18MEM
M1
GFX_TX5N
N19
VSS
R17
VDD_18CPU
M10
VDD_PLLPCIE
N21
VSS
R18
VDD_18CPU
M12
VDD_PCIE
N23
AVSSN
R19
VDD_18CPU
M14
VDD_PCIE
N24
VDD_18CPU
R2
VSS_PCIE
M16
VDD_18MEM
N25
VDD_18CPU
R29
VDD_CPU
M18
VSS
N27
VDD_CPU
R3
VSS_PCIE
M19
VSS
N29
VDD_CPU
R30
VDD_CPU
M2
GFX_TX5P
N30
VDD_CPU
R31
VDD_CPU
M21
VSS
N32
VDD_CPU
R32
VDD_CPU
M23
AVSSN
N34
VDD_CPU
R33
VDD_CPU
M24
VSS
P1
VSS_PCIE
R45
CPU_TRDY#
M25
VSS
P10
VSS_PCIE
R46
CPU_ADS#
M27
CPU_D40#
P12
VDD_PLLPCIE
R47
CPU_RS1#
M29
CPU_D36#
P13
VDD_PLLPCIE
T1
GFX_TX7N
M3
VSS_PCIE
P2
GFX_TX6P
T10
GFX_RX8N
M30
VDD_CPU
P3
VSS_PCIE
T12
VSS_PLLPCIE
M32
VDD_CPU
P35
VDD_CPU
T13
VSS_PLLPCIE
M34
VDD_CPU
P36
CPU_A12#
T15
VDD_PCIE
M36
VSS
P38
CPU_A10#
T16
VDD_18MEM
M38
CPU_A7#
P39
CPU_REQ0#
T17
VDD_18CPU
M39
CPU_REQ1#
P4
GFX_RX6P
T18
VDD_18CPU
M4
GFX_RX4N
P40
VSS
T19
VDD_18CPU
M40
VSS
P42
CPU_A8#
T2
GFX_TX7P
M42
CPU_A3#
P43
VSS
T29
VDD_18CPU
RS600 Databook
A-11
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
T3
VSS_PCIE
U47
MEMA_DQ59
V6
GFX_RX9N
T30
VDD_18CPU
V1
VDD_PCIE
V8
VSS_PCIE
T31
VDD_18CPU
V10
GFX_RX10N
V9
GFX_RX10P
T32
VDD_18CPU
V12
VSS_PLLPCIE
W1
GFX_TX9N
T33
VDD_CPU
V13
VDD_PCIE
W10
VSS_PCIE
T35
VDD_CPU
V15
VDD_PCIE
W12
VDD_PCIE
T36
VDD_CPU
V16
VDD_18MEM
W13
VDD_PCIE
T38
VSS
V17
VDD_CORE
W15
VDD_PCIE
T39
CPU_A6#
V18
VDD_CORE
W16
VDD_18MEM
T4
VSS_PCIE
V19
VSS
W17
VDD_CORE
T40
VSS
V2
GFX_TX9P
W18
VSS
T42
CPU_ADSTB0#
V20
VDD_CORE
W19
VDD_CORE
T43
CPU_A9#
V22
VSS
W2
VSS_PCIE
T44
VSS
V23
VDD_CORE
W20
VSS
T45
CPU_BR0#
V25
VSS
W22
VDD_CORE
T46
VSS
V26
VDD_CORE
W23
VSS
T47
CPU_EDRDY#
V28
VSS
W25
VDD_CORE
T5
GFX_RX7N
V29
VDD_CORE
W26
VSS
T6
GFX_RX7P
V3
VDD_PCIE
W28
VDD_CORE
T8
VSS_PCIE
V30
VSS
W29
VSS
T9
GFX_RX8P
V31
VDD_CORE
W3
VSS_PCIE
U1
GFX_TX8N
V32
VDD_18CPU
W30
VDD_CORE
U15
VDD_PCIE
V33
VDD_CPU
W31
VDD_CORE
U16
VDD_18MEM
V35
IOPLLVDD12
W32
VDD_18CPU
U17
VDD_CORE
V36
CPU_A20#
W33
VDD_CPU
U18
VDD_CORE
V38
CPU_A23#
W35
IOPLLVSS
U19
VDD_CORE
V39
VSS
W36
VDD_CPU
U2
GFX_TX8P
V4
VSS_PCIE
W38
VDD_CPU
U29
VDD_CORE
V40
CPU_A14#
W39
CPU_A13#
U3
VSS_PCIE
V42
CPU_A16#
W4
VSS_PCIE
U30
VDD_CORE
V43
VSS
W40
VSS
U31
VDD_CORE
V44
CPU_A19#
W42
CPU_A15#
U32
VDD_18CPU
V45
MEMA_DQ62
W43
CPU_A18#
U33
VDD_CPU
V46
MEMA_DQ58
W44
VSS
U45
MEMA_DQ63
V47
VSS
W45
MEMA_DM7
U46
CPU_RESERVED
V5
GFX_RX9P
W46
MEMA_DQS7P
RS600 Databook
A-12
Ball
Ref.
Pin Name
W47
MEMA_DQS7N
W5
VSS_PCIE
W6
VSS_PCIE
W8
VSS_PCIE
W9
VSS_PCIE
Y1
GFX_TX10N
Y18
VDD_CORE
Y19
VSS
Y2
GFX_TX10P
Y20
VDD_CORE
Y22
VSS
Y23
VDD_CORE
Y25
VSS
Y26
VDD_CORE
Y28
VSS
Y29
VDD_CORE
Y3
VSS_PCIE
Y30
VSS
Y45
VSS
Y46
MEMA_DQ57
Y47
MEMA_DQ61
RS600 Databook
A-13
A.2
Pin List Sorted by Pin Name
Table A-2 Pin List Sorted by Pin Name
Pin Name
Ball
Ref.
AVDD
A17
AVDD
B17
AVDDDI
B19
AVDDQ
A23
AVSSDI
A19
AVSSN
M23
AVSSN
N23
AVSSQ
A24
BLUE
J19
C
J18
COMP
D18
CPU_A10#
P38
CPU_A11#
P44
CPU_A12#
P36
CPU_A13#
W39
CPU_A14#
V40
CPU_A15#
W42
CPU_A16#
V42
CPU_A17#
AC39
CPU_A18#
W43
CPU_A19#
V44
CPU_A20#
V36
CPU_A21#
AA40
CPU_A22#
AC43
CPU_A23#
V38
CPU_A24#
AA42
CPU_A25#
AA38
CPU_A26#
AC42
CPU_A27#
AD36
CPU_A28#
AD38
CPU_A29#
AA36
CPU_A3#
M42
CPU_A30#
AD42
CPU_A31#
AD40
RS600 Databook
A-14
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
CPU_A32#
AD44
CPU_D22#
D42
CPU_A33#
AD43
CPU_D23#
D40
CPU_A4#
K42
CPU_D24#
E38
CPU_A5#
M44
CPU_D25#
F36
CPU_A6#
T39
CPU_D26#
E36
CPU_A7#
M38
CPU_D27#
J34
CPU_A8#
P42
CPU_D28#
F34
CPU_A9#
T43
CPU_D29#
H38
CPU_ADS#
R46
CPU_D3#
G45
CPU_ADSTB0#
T42
CPU_D30#
D32
CPU_ADSTB1#
AA44
CPU_D31#
E34
CPU_BNR#
M47
CPU_D32#
J32
CPU_BPRI#
H44
CPU_D33#
F32
CPU_BR0#
T45
CPU_D34#
K32
CPU_CLKN
B7
CPU_D35#
D29
CPU_CLKP
A7
CPU_D36#
M29
CPU_COMP_N
A31
CPU_D37#
K30
CPU_COMP_P
B32
CPU_D38#
F30
CPU_CPURST#
K25
CPU_D39#
E30
CPU_D0#
H46
CPU_D4#
H45
CPU_D1#
G47
CPU_D40#
M27
CPU_D10#
D46
CPU_D41#
F27
CPU_D11#
C45
CPU_D42#
K27
CPU_D12#
D47
CPU_D43#
D25
CPU_D13#
B44
CPU_D44#
E27
CPU_D14#
A43
CPU_D45#
J27
CPU_D15#
B45
CPU_D46#
J25
CPU_D16#
E40
CPU_D47#
F25
CPU_D17#
F44
CPU_D48#
C37
CPU_D18#
E42
CPU_D49#
B40
CPU_D19#
F40
CPU_D5#
G46
CPU_D2#
K45
CPU_D50#
B43
CPU_D20#
H40
CPU_D51#
C42
CPU_D21#
D44
CPU_D52#
C43
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
CPU_D53#
A42
CPU_REQ2#
K44
GFX_RX3P
M8
CPU_D54#
B38
CPU_REQ3#
H42
GFX_RX4N
M4
CPU_D55#
A41
CPU_REQ4#
K40
GFX_RX4P
M5
CPU_D56#
C40
CPU_RESERVED
U46
GFX_RX5N
P8
CPU_D57#
A38
CPU_RS0#
L47
GFX_RX5P
P9
CPU_D58#
C36
CPU_RS1#
R47
GFX_RX6N
P5
CPU_D59#
B36
CPU_RS2#
L45
GFX_RX6P
P4
CPU_D6#
F45
CPU_SLP#
C17
GFX_RX7N
T5
CPU_D60#
A37
CPU_TRDY#
R45
GFX_RX7P
T6
CPU_D61#
C38
CPU_VREF
A32
GFX_RX8N
T10
CPU_D62#
B34
DACHSYNC
B24
GFX_RX8P
T9
CPU_D63#
C34
DACRSET
A25
GFX_RX9N
V6
CPU_D7#
F47
DACSDA
A22
GFX_RX9P
V5
CPU_D8#
C46
DACVSYNC
B23
GFX_TX0N
E1
CPU_D9#
A44
DDC_DATA
B12
GFX_TX0P
D2
CPU_DBI0#
E47
GFX_REFCLKN
B4
GFX_TX10N
Y1
CPU_DBI1#
K36
GFX_REFCLKP
A5
GFX_TX10P
Y2
CPU_DBI2#
J30
GFX_RX0N
C2
GFX_TX11N
AA1
CPU_DBI3#
A36
GFX_RX0P
C3
GFX_TX11P
AA2
CPU_DBSY#
M46
GFX_RX10N
V10
GFX_TX12N
AC1
CPU_DEFER#
K46
GFX_RX10P
V9
GFX_TX12P
AB2
CPU_DRDY#
P45
GFX_RX11N
AA5
GFX_TX13N
AD1
CPU_DSTB0N#
E46
GFX_RX11P
AA6
GFX_TX13P
AD2
CPU_DSTB0P#
E45
GFX_RX12N
AA10
GFX_TX14N
AE1
CPU_DSTB1N#
J38
GFX_RX12P
AA9
GFX_TX14P
AE2
CPU_DSTB1P#
J36
GFX_RX13N
AC6
GFX_TX15N
AG1
CPU_DSTB2N#
H29
GFX_RX13P
AC5
GFX_TX15P
AF2
CPU_DSTB2P#
F29
GFX_RX14N
AC10
GFX_TX1N
F1
CPU_DSTB3N#
B41
GFX_RX14P
AC9
GFX_TX1P
F2
CPU_DSTB3P#
C41
GFX_RX15N
AE5
GFX_TX2N
G1
CPU_EDRDY#
T47
GFX_RX15P
AE6
GFX_TX2P
G2
CPU_HIT#
K47
GFX_RX1N
H4
GFX_TX3N
K1
CPU_HITM#
P46
GFX_RX1P
H5
GFX_TX3P
H2
CPU_LOCK#
M45
GFX_RX2N
K6
GFX_TX4N
L1
CPU_REQ0#
P39
GFX_RX2P
K8
GFX_TX4P
L2
CPU_REQ1#
M39
GFX_RX3N
M6
GFX_TX5N
M1
RS600 Databook
A-15
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
GFX_TX5P
M2
LTPVDD18
B21
MEMA_CKE0
BF29
GFX_TX6N
R1
LTPVSS18
A21
MEMA_CKE1
BG28
GFX_TX6P
P2
MEM_COMPN
AT45
MEMA_CKE2
BG29
GFX_TX7N
T1
MEM_COMPP
AT46
MEMA_CKE3
BE28
GFX_TX7P
T2
MEM_VREF
BG44
MEMA_CS0#
BA46
GFX_TX8N
U1
MEMA_A0
BE42
MEMA_CS1#
AV46
GFX_TX8P
U2
MEMA_A1
BF36
MEMA_CS2#
BA47
GFX_TX9N
W1
MEMA_A10
BE46
MEMA_CS3#
AU45
GFX_TX9P
V2
MEMA_A11
BE31
MEMA_DM0
BD2
GPIO10
C4
MEMA_A12
BF31
MEMA_DM1
BE6
GPIO8
C5
MEMA_A13
AV45
MEMA_DM2
BG12
GPIO9
D3
MEMA_A14
BF30
MEMA_DM3
BE17
GPP_RX0N
AK5
MEMA_A2
BG36
MEMA_DM4
AN45
GPP_RX0P
AK6
MEMA_A3
BE34
MEMA_DM5
AH47
GPP_RX1N
AM1
MEMA_A4
BF34
MEMA_DM6
AD45
GPP_RX1P
AM2
MEMA_A5
BE33
MEMA_DM7
W45
GPP_RX2N
AJ1
MEMA_A6
BF33
MEMA_DQ0
BC3
GPP_RX2P
AJ2
MEMA_A7
BE32
MEMA_DQ1
BD1
GPP_RX3N
AG6
MEMA_A8
BG33
MEMA_DQ10
BE8
GPP_RX3P
AG5
MEMA_A9
BG32
MEMA_DQ11
BG10
GPP_TX0N
AG10
MEMA_BA0
BD46
MEMA_DQ12
BG5
GPP_TX0P
AG9
MEMA_BA1
BD47
MEMA_DQ13
BE5
GPP_TX1N
AL1
MEMA_BA2
BE30
MEMA_DQ14
BE7
GPP_TX1P
AK2
MEMA_CAS#
AY46
MEMA_DQ15
BF8
GPP_TX2N
AH1
MEMA_CK0N
BB29
MEMA_DQ16
BE10
GPP_TX2P
AH2
MEMA_CK0P
BB30
MEMA_DQ17
BE11
GPP_TX3N
AE10
MEMA_CK1N
AY10
MEMA_DQ18
BF15
GPP_TX3P
AE9
MEMA_CK1P
AY8
MEMA_DQ19
BE15
GPPSB_REFCLKN
B6
MEMA_CK2N
AV44
MEMA_DQ2
BF4
GPPSB_REFCLKP
A6
MEMA_CK2P
AV43
MEMA_DQ20
BF10
GREEN
F19
MEMA_CK3N
BD29
MEMA_DQ21
BG11
I2C_CLK
C21
MEMA_CK3P
BD30
MEMA_DQ22
BE14
I2C_DATA
B22
MEMA_CK4N
AY12
MEMA_DQ23
BG15
IOPLLVDD12
V35
MEMA_CK4P
AW12
MEMA_DQ24
BG17
IOPLLVDD18
AA35
MEMA_CK5N
AY43
MEMA_DQ25
BF17
IOPLLVSS
W35
MEMA_CK5P
AY44
MEMA_DQ26
BF19
RS600 Databook
A-16
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
MEMA_DQ27
BE20
MEMA_DQ6
BE3
MEMB_A14
BE23
MEMA_DQ28
BG16
MEMA_DQ60
AA46
MEMB_A2
BE29
MEMA_DQ29
BE16
MEMA_DQ61
Y47
MEMB_A3
BE27
MEMA_DQ3
BE4
MEMA_DQ62
V45
MEMB_A4
BF27
MEMA_DQ30
BG19
MEMA_DQ63
U45
MEMB_A5
BG27
MEMA_DQ31
BE19
MEMA_DQ7
BF3
MEMB_A6
BE26
MEMA_DQ32
AP45
MEMA_DQ8
BF5
MEMB_A7
BE25
MEMA_DQ33
AN46
MEMA_DQ9
BG6
MEMB_A8
BF26
MEMA_DQ34
AL45
MEMA_DQS0N
BD3
MEMB_A9
BF25
MEMA_DQ35
AK46
MEMA_DQS0P
BE2
MEMB_BA0
BG38
MEMA_DQ36
AP46
MEMA_DQS1N
BG7
MEMB_BA1
BE37
MEMA_DQ37
AN47
MEMA_DQS1P
BF7
MEMB_BA2
BG24
MEMA_DQ38
AL47
MEMA_DQS2N
BF12
MEMB_CAS#
BG41
MEMA_DQ39
AL46
MEMA_DQS2P
BE12
MEMB_CK0N
AV29
MEMA_DQ4
BC2
MEMA_DQS3N
BF18
MEMB_CK0P
AT30
MEMA_DQ40
AJ46
MEMA_DQS3P
BE18
MEMB_CK1N
BC10
MEMA_DQ41
AJ45
MEMA_DQS4N
AM47
MEMB_CK1P
BD10
MEMA_DQ42
AG45
MEMA_DQS4P
AM46
MEMB_CK2N
BB43
MEMA_DQ43
AF45
MEMA_DQS5N
AH46
MEMB_CK2P
BB44
MEMA_DQ44
AK45
MEMA_DQS5P
AG47
MEMB_CK3N
AT25
MEMA_DQ45
AJ47
MEMA_DQS6N
AC47
MEMB_CK3P
AV25
MEMA_DQ46
AG46
MEMA_DQS6P
AC46
MEMB_CK4N
BC8
MEMA_DQ47
AF46
MEMA_DQS7N
W47
MEMB_CK4P
BD8
MEMA_DQ48
AE46
MEMA_DQS7P
W46
MEMB_CK5N
BD44
MEMA_DQ49
AD47
MEMA_ODT0
AY45
MEMB_CK5P
BE44
MEMA_DQ5
BC1
MEMA_ODT1
AU47
MEMB_CKE0
BF23
MEMA_DQ50
AB45
MEMA_ODT2
AV47
MEMB_CKE1
BG23
MEMA_DQ51
AA47
MEMA_ODT3
AT47
MEMB_CKE2
BE22
MEMA_DQ52
AE47
MEMA_RAS#
BC47
MEMB_CKE3
BF22
MEMA_DQ53
AE45
MEMA_WE#
BA45
MEMB_CS0#
BF40
MEMA_DQ54
AC45
MEMB_A0
BE36
MEMB_CS1#
BF41
MEMA_DQ55
AB46
MEMB_A1
BG31
MEMB_CS2#
BE38
MEMA_DQ56
AA45
MEMB_A10
BG37
MEMB_CS3#
BF45
MEMA_DQ57
Y46
MEMB_A11
BG25
MEMB_DM0
AY4
MEMA_DQ58
V46
MEMB_A12
BE24
MEMB_DM1
AV14
MEMA_DQ59
U47
MEMB_A13
BG42
MEMB_DM2
BB19
RS600 Databook
A-17
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
MEMB_DM3
AT24
MEMB_DQ37
AT32
MEMB_DQS1P
AW16
MEMB_DM4
BB32
MEMB_DQ38
BB34
MEMB_DQS2N
BD21
MEMB_DM5
AW38
MEMB_DQ39
AY32
MEMB_DQS2P
BD19
MEMB_DM6
AT38
MEMB_DQ4
AT8
MEMB_DQS3N
AW25
MEMB_DM7
AM42
MEMB_DQ40
BD38
MEMB_DQS3P
AW27
MEMB_DQ0
AV5
MEMB_DQ41
AY36
MEMB_DQS4N
BD34
MEMB_DQ1
AV6
MEMB_DQ42
AY38
MEMB_DQS4P
BD32
MEMB_DQ10
BD18
MEMB_DQ43
BC40
MEMB_DQS5N
BD40
MEMB_DQ11
BC16
MEMB_DQ44
BB38
MEMB_DQS5P
BC38
MEMB_DQ12
BB14
MEMB_DQ45
BC36
MEMB_DQS6N
AT44
MEMB_DQ13
BD12
MEMB_DQ46
BB40
MEMB_DQS6P
AP44
MEMB_DQ14
BB16
MEMB_DQ47
BD42
MEMB_DQS7N
AK42
MEMB_DQ15
BB18
MEMB_DQ48
AV40
MEMB_DQS7P
AK40
MEMB_DQ16
AT18
MEMB_DQ49
AT40
MEMB_ODT0
BC46
MEMB_DQ17
AW19
MEMB_DQ5
AV4
MEMB_ODT1
BC45
MEMB_DQ18
AW23
MEMB_DQ50
AP40
MEMB_ODT2
BB47
MEMB_DQ19
AY24
MEMB_DQ51
AT39
MEMB_ODT3
BB45
MEMB_DQ2
BC6
MEMB_DQ52
AY40
MEMB_RAS#
BF38
MEMB_DQ20
AY18
MEMB_DQ53
AV39
MEMB_WE#
BE40
MEMB_DQ21
AV19
MEMB_DQ54
AT42
OSCIN
B11
MEMB_DQ22
BB21
MEMB_DQ55
AP42
PCE_CALI
BA3
MEMB_DQ23
AY21
MEMB_DQ56
AM38
PCE_CALRN
BA2
MEMB_DQ24
BB23
MEMB_DQ57
AK44
PCE_CALRP
BA1
MEMB_DQ25
AV23
MEMB_DQ58
AJ42
PLLVDD12
A12
MEMB_DQ26
BD27
MEMB_DQ59
AG44
PLLVDD18
A14
MEMB_DQ27
BB25
MEMB_DQ6
BB4
PLLVSS
A11
MEMB_DQ28
BC23
MEMB_DQ60
AK36
POWERGOOD
F10
MEMB_DQ29
BD24
MEMB_DQ61
AM43
RED
D19
MEMB_DQ3
BD6
MEMB_DQ62
AM39
SB_RX0N
AV3
MEMB_DQ30
BC25
MEMB_DQ63
AJ43
SB_RX0P
AU3
MEMB_DQ31
BB27
MEMB_DQ7
AV9
SB_RX1N
AM10
MEMB_DQ32
AW30
MEMB_DQ8
BC14
SB_RX1P
AM9
MEMB_DQ33
AV32
MEMB_DQ9
AY14
SB_RX2N
AM6
MEMB_DQ34
AW34
MEMB_DQS0N
AY5
SB_RX2P
AM5
MEMB_DQ35
BB36
MEMB_DQS0P
AY6
SB_RX3N
AK10
MEMB_DQ36
AY29
MEMB_DQS1N
AV16
SB_RX3P
AK9
RS600 Databook
A-18
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
SB_TX0N
AV2
VDD_18CPU
C15
VDD_18MEM
AR27
SB_TX0P
AV1
VDD_18CPU
E14
VDD_18MEM
B15
SB_TX1N
AU1
VDD_18CPU
H14
VDD_18MEM
D14
SB_TX1P
AU2
VDD_18CPU
K16
VDD_18MEM
F14
SB_TX2N
AT1
VDD_18CPU
N24
VDD_18MEM
J14
SB_TX2P
AP2
VDD_18CPU
N25
VDD_18MEM
M16
SB_TX3N
AN1
VDD_18CPU
R17
VDD_18MEM
N16
SB_TX3P
AN2
VDD_18CPU
R18
VDD_18MEM
R16
STRP_DATA
B14
VDD_18CPU
R19
VDD_18MEM
T16
SUS_STAT#
AT9
VDD_18CPU
T17
VDD_18MEM
U16
SYSRESET#
D10
VDD_18CPU
T18
VDD_18MEM
V16
TESTMODE
A20
VDD_18CPU
T19
VDD_18MEM
W16
THERMALDIODE_N
AT4
VDD_18CPU
T29
VDD_CORE
A16
THERMALDIODE_P
AT5
VDD_18CPU
T30
VDD_CORE
AB19
TMDS_HPD
B26
VDD_18CPU
T31
VDD_CORE
AB22
TXCLK_LN
A27
VDD_18CPU
T32
VDD_CORE
AB25
TXCLK_LP
B27
VDD_18CPU
U32
VDD_CORE
AB28
TXCLK_UN
E21
VDD_18CPU
V32
VDD_CORE
AB30
TXCLK_UP
F21
VDD_18CPU
W32
VDD_CORE
AC18
TXOUT_L0N
B28
VDD_18MEM
AD35
VDD_CORE
AC20
TXOUT_L0P
A28
VDD_18MEM
AJ16
VDD_CORE
AC23
TXOUT_L1N
C30
VDD_18MEM
AJ32
VDD_CORE
AC26
TXOUT_L1P
B30
VDD_18MEM
AK16
VDD_CORE
AC29
TXOUT_L2N
B29
VDD_18MEM
AK32
VDD_CORE
AE19
TXOUT_L2P
A29
VDD_18MEM
AL16
VDD_CORE
AE22
TXOUT_L3N
C28
VDD_18MEM
AL32
VDD_CORE
AE25
TXOUT_L3P
C27
VDD_18MEM
AM16
VDD_CORE
AE28
TXOUT_U0N
C24
VDD_18MEM
AM17
VDD_CORE
AE30
TXOUT_U0P
C25
VDD_18MEM
AM18
VDD_CORE
AF18
TXOUT_U1N
D24
VDD_18MEM
AM19
VDD_CORE
AF20
TXOUT_U1P
E24
VDD_18MEM
AM29
VDD_CORE
AF23
TXOUT_U2N
H21
VDD_18MEM
AM30
VDD_CORE
AF26
TXOUT_U2P
J21
VDD_18MEM
AM31
VDD_CORE
AF29
TXOUT_U3N
E23
VDD_18MEM
AM32
VDD_CORE
AH19
TXOUT_U3P
F23
VDD_18MEM
AM33
VDD_CORE
AH22
VDD_18CPU
A15
VDD_18MEM
AN16
VDD_CORE
AH25
RS600 Databook
A-19
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
VDD_CORE
AH28
VDD_CORE
V18
VDD_CPU
N34
VDD_CORE
AH30
VDD_CORE
V20
VDD_CPU
P35
VDD_CORE
AJ17
VDD_CORE
V23
VDD_CPU
R29
VDD_CORE
AJ18
VDD_CORE
V26
VDD_CPU
R30
VDD_CORE
AJ20
VDD_CORE
V29
VDD_CPU
R31
VDD_CORE
AJ23
VDD_CORE
V31
VDD_CPU
R32
VDD_CORE
AJ26
VDD_CORE
W17
VDD_CPU
R33
VDD_CORE
AJ29
VDD_CORE
W19
VDD_CPU
T33
VDD_CORE
AJ31
VDD_CORE
W22
VDD_CPU
T35
VDD_CORE
AK17
VDD_CORE
W25
VDD_CPU
T36
VDD_CORE
AK19
VDD_CORE
W28
VDD_CPU
U33
VDD_CORE
AK22
VDD_CORE
W30
VDD_CPU
V33
VDD_CORE
AK25
VDD_CORE
W31
VDD_CPU
W33
VDD_CORE
AK28
VDD_CORE
Y18
VDD_CPU
W36
VDD_CORE
AK30
VDD_CORE
Y20
VDD_CPU
W38
VDD_CORE
AK31
VDD_CORE
Y23
P47
VDD_CORE
AL17
VDD_CORE
Y26
VDD_CPU_PACKAG
E
VDD_CORE
AL18
VDD_CORE
Y29
VDD_MEM
AE35
VDD_CORE
AL19
VDD_CPU
A33
VDD_MEM
AE36
VDD_CORE
AL29
VDD_CPU
AC35
VDD_MEM
AE38
VDD_CORE
AL30
VDD_CPU
AC36
VDD_MEM
AG35
VDD_CORE
AL31
VDD_CPU
B33
VDD_MEM
AG36
VDD_CORE
B16
VDD_CPU
C31
VDD_MEM
AG38
VDD_CORE
C16
VDD_CPU
C32
VDD_MEM
AG39
VDD_CORE
D16
VDD_CPU
C33
VDD_MEM
AJ33
VDD_CORE
E16
VDD_CPU
H30
VDD_MEM
AJ35
VDD_CORE
F16
VDD_CPU
H32
VDD_MEM
AJ36
VDD_CORE
H16
VDD_CPU
J29
VDD_MEM
AK33
VDD_CORE
J16
VDD_CPU
K29
VDD_MEM
AK35
VDD_CORE
U17
VDD_CPU
M30
VDD_MEM
AK38
VDD_CORE
U18
VDD_CPU
M32
VDD_MEM
AL33
VDD_CORE
U19
VDD_CPU
M34
VDD_MEM
AM35
VDD_CORE
U29
VDD_CPU
N27
VDD_MEM
AM36
VDD_CORE
U30
VDD_CPU
N29
VDD_MEM
AN17
VDD_CORE
U31
VDD_CPU
N30
VDD_MEM
AN18
VDD_CORE
V17
VDD_CPU
N32
VDD_MEM
AN19
RS600 Databook
A-20
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
VDD_MEM
AN29
VDD_MEM
BD45
VDD_PCIE
E8
VDD_MEM
AN30
VDD_MEM
BE45
VDD_PCIE
F8
VDD_MEM
AN31
VDD_MEM
BF46
VDD_PCIE
H10
VDD_MEM
AN32
VDD_MEM
BG22
VDD_PCIE
H8
VDD_MEM
AN33
VDD_MEM
BG26
VDD_PCIE
J10
VDD_MEM
AP35
VDD_MEM
BG30
VDD_PCIE
K12
VDD_MEM
AP36
VDD_MEM
BG34
VDD_PCIE
K14
VDD_MEM
AP38
VDD_MEM
BG40
VDD_PCIE
K9
VDD_MEM
AR14
VDD_MEM
BG45
VDD_PCIE
M12
VDD_MEM
AR16
VDD_PCIE
A10
VDD_PCIE
M14
VDD_MEM
AR18
VDD_PCIE
A8
VDD_PCIE
N14
VDD_MEM
AR19
VDD_PCIE
AA12
VDD_PCIE
R15
VDD_MEM
AR21
VDD_PCIE
AA13
VDD_PCIE
T15
VDD_MEM
AR23
VDD_PCIE
AC13
VDD_PCIE
U15
VDD_MEM
AR24
VDD_PCIE
AD13
VDD_PCIE
V1
VDD_MEM
AR25
VDD_PCIE
AE13
VDD_PCIE
V13
VDD_MEM
AR29
VDD_PCIE
AG13
VDD_PCIE
V15
VDD_MEM
AR30
VDD_PCIE
AJ13
VDD_PCIE
V3
VDD_MEM
AR32
VDD_PCIE
AJ15
VDD_PCIE
W12
VDD_MEM
AR34
VDD_PCIE
AK13
VDD_PCIE
W13
VDD_MEM
AT14
VDD_PCIE
AK15
VDD_PCIE
W15
VDD_MEM
AT16
VDD_PCIE
AL15
VDD_PLLPCIE
M10
VDD_MEM
AT19
VDD_PCIE
AM12
VDD_PLLPCIE
P12
VDD_MEM
AT21
VDD_PCIE
AM13
VDD_PLLPCIE
P13
VDD_MEM
AT23
VDD_PCIE
AM15
VDDLT18
H24
VDD_MEM
AT27
VDD_PCIE
AN15
VDDLT18
J24
VDD_MEM
AT29
VDD_PCIE
AP1
VDDLT33
H23
VDD_MEM
AT34
VDD_PCIE
AP12
VDDLT33
J23
VDD_MEM
AT36
VDD_PCIE
AP13
VDDR3
A18
VDD_MEM
AV18
VDD_PCIE
AP3
VDDR3
B18
VDD_MEM
AV21
VDD_PCIE
B10
VSS
A34
VDD_MEM
AV24
VDD_PCIE
B8
VSS
A4
VDD_MEM
AV27
VDD_PCIE
C10
VSS
A40
VDD_MEM
AV30
VDD_PCIE
C7
VSS
A45
VDD_MEM
AV34
VDD_PCIE
C8
VSS
AA39
VDD_MEM
AV36
VDD_PCIE
D8
VSS
AA43
RS600 Databook
A-21
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
VSS
AB18
VSS
AH20
VSS
AW10
VSS
AB20
VSS
AH23
VSS
AW14
VSS
AB23
VSS
AH26
VSS
AW18
VSS
AB26
VSS
AH29
VSS
AW21
VSS
AB29
VSS
AH45
VSS
AW24
VSS
AB47
VSS
AJ19
VSS
AW29
VSS
AC19
VSS
AJ22
VSS
AW32
VSS
AC22
VSS
AJ25
VSS
AW36
VSS
AC25
VSS
AJ28
VSS
AY16
VSS
AC28
VSS
AJ30
VSS
AY19
VSS
AC30
VSS
AJ38
VSS
AY23
VSS
AC38
VSS
AJ39
VSS
AY25
VSS
AC40
VSS
AJ40
VSS
AY27
VSS
AC44
VSS
AJ44
VSS
AY30
VSS
AD39
VSS
AK18
VSS
AY34
VSS
AD46
VSS
AK20
VSS
AY42
VSS
AE18
VSS
AK23
VSS
AY47
VSS
AE20
VSS
AK26
VSS
B31
VSS
AE23
VSS
AK29
VSS
B37
VSS
AE26
VSS
AK39
VSS
B42
VSS
AE29
VSS
AK43
VSS
B46
VSS
AE39
VSS
AK47
VSS
B5
VSS
AE40
VSS
AM40
VSS
BB10
VSS
AE42
VSS
AM44
VSS
BB12
VSS
AE43
VSS
AM45
VSS
BB24
VSS
AE44
VSS
AP39
VSS
BB46
VSS
AF19
VSS
AP43
VSS
BB8
VSS
AF22
VSS
AP47
VSS
BC12
VSS
AF25
VSS
AT10
VSS
BC18
VSS
AF28
VSS
AT12
VSS
BC19
VSS
AF30
VSS
AT43
VSS
BC21
VSS
AF47
VSS
AT6
VSS
BC24
VSS
AG40
VSS
AU46
VSS
BC27
VSS
AG42
VSS
AV12
VSS
BC29
VSS
AG43
VSS
AV42
VSS
BC30
VSS
AH18
VSS
AV8
VSS
BC32
RS600 Databook
A-22
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
VSS
BC34
VSS
C14
VSS
H34
VSS
BD14
VSS
C19
VSS
H36
VSS
BD16
VSS
C20
VSS
H43
VSS
BD23
VSS
C22
VSS
H47
VSS
BD25
VSS
C23
VSS
J12
VSS
BD36
VSS
C26
VSS
K18
VSS
BD4
VSS
C44
VSS
K19
VSS
BE1
VSS
C47
VSS
K21
VSS
BE21
VSS
C6
VSS
K23
VSS
BE41
VSS
D12
VSS
K24
VSS
BE43
VSS
D21
VSS
K34
VSS
BE47
VSS
D23
VSS
K39
VSS
BF11
VSS
D27
VSS
K43
VSS
BF14
VSS
D30
VSS
L46
VSS
BF16
VSS
D34
VSS
M18
VSS
BF2
VSS
D36
VSS
M19
VSS
BF20
VSS
D38
VSS
M21
VSS
BF21
VSS
D4
VSS
M24
VSS
BF24
VSS
D45
VSS
M25
VSS
BF28
VSS
D6
VSS
M36
VSS
BF32
VSS
E10
VSS
M40
VSS
BF37
VSS
E12
VSS
M43
VSS
BF42
VSS
E18
VSS
N18
VSS
BF43
VSS
E19
VSS
N19
VSS
BF44
VSS
E25
VSS
N21
VSS
BF6
VSS
E29
VSS
P40
VSS
BG14
VSS
E32
VSS
P43
VSS
BG18
VSS
F12
VSS
T38
VSS
BG20
VSS
F38
VSS
T40
VSS
BG21
VSS
F46
VSS
T44
VSS
BG3
VSS
F5
VSS
T46
VSS
BG4
VSS
H12
VSS
V19
VSS
BG43
VSS
H18
VSS
V22
VSS
BG8
VSS
H19
VSS
V25
VSS
C11
VSS
H25
VSS
V28
VSS
C12
VSS
H27
VSS
V30
RS600 Databook
A-23
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
Pin Name
Ball
Ref.
VSS
V39
VSS_PCIE
AE3
VSS_PCIE
AT2
VSS
V43
VSS_PCIE
AE4
VSS_PCIE
AT3
VSS
V47
VSS_PCIE
AE8
VSS_PCIE
AY1
VSS
W18
VSS_PCIE
AF1
VSS_PCIE
AY2
VSS
W20
VSS_PCIE
AF3
VSS_PCIE
AY3
VSS
W23
VSS_PCIE
AG12
VSS_PCIE
B2
VSS
W26
VSS_PCIE
AG2
VSS_PCIE
B3
VSS
W29
VSS_PCIE
AG3
VSS_PCIE
BB1
VSS
W40
VSS_PCIE
AG4
VSS_PCIE
BB2
VSS
W44
VSS_PCIE
AG8
VSS_PCIE
BB3
VSS
Y19
VSS_PCIE
AH3
VSS_PCIE
C1
VSS
Y22
VSS_PCIE
AJ10
VSS_PCIE
D1
VSS
Y25
VSS_PCIE
AJ12
VSS_PCIE
E2
VSS
Y28
VSS_PCIE
AJ3
VSS_PCIE
E3
VSS
Y30
VSS_PCIE
AJ4
VSS_PCIE
F3
VSS
Y45
VSS_PCIE
AJ5
VSS_PCIE
F4
VSS_PCIE
A3
VSS_PCIE
AJ6
VSS_PCIE
G3
VSS_PCIE
AA3
VSS_PCIE
AJ8
VSS_PCIE
H1
VSS_PCIE
AA4
VSS_PCIE
AJ9
VSS_PCIE
H3
VSS_PCIE
AA8
VSS_PCIE
AK1
VSS_PCIE
H6
VSS_PCIE
AB1
VSS_PCIE
AK12
VSS_PCIE
K2
VSS_PCIE
AB3
VSS_PCIE
AK3
VSS_PCIE
K3
VSS_PCIE
AC12
VSS_PCIE
AK4
VSS_PCIE
K4
VSS_PCIE
AC2
VSS_PCIE
AK8
VSS_PCIE
K5
VSS_PCIE
AC3
VSS_PCIE
AL2
VSS_PCIE
L3
VSS_PCIE
AC4
VSS_PCIE
AL3
VSS_PCIE
M3
VSS_PCIE
AC8
VSS_PCIE
AM3
VSS_PCIE
M9
VSS_PCIE
AD10
VSS_PCIE
AM4
VSS_PCIE
P1
VSS_PCIE
AD12
VSS_PCIE
AM8
VSS_PCIE
P10
VSS_PCIE
AD3
VSS_PCIE
AN3
VSS_PCIE
P3
VSS_PCIE
AD4
VSS_PCIE
AP10
VSS_PCIE
P6
VSS_PCIE
AD5
VSS_PCIE
AP4
VSS_PCIE
R2
VSS_PCIE
AD6
VSS_PCIE
AP5
VSS_PCIE
R3
VSS_PCIE
AD8
VSS_PCIE
AP6
VSS_PCIE
T3
VSS_PCIE
AD9
VSS_PCIE
AP8
VSS_PCIE
T4
VSS_PCIE
AE12
VSS_PCIE
AP9
VSS_PCIE
T8
RS600 Databook
A-24
Pin Name
Ball
Ref.
VSS_PCIE
U3
VSS_PCIE
V4
VSS_PCIE
V8
VSS_PCIE
W10
VSS_PCIE
W2
VSS_PCIE
W3
VSS_PCIE
W4
VSS_PCIE
W5
VSS_PCIE
W6
VSS_PCIE
W8
VSS_PCIE
W9
VSS_PCIE
Y3
VSS_PLLPCIE
T12
VSS_PLLPCIE
T13
VSS_PLLPCIE
V12
VSSLT
A26
VSSLT
A30
VSSLT
C29
VSSLT
F24
Y
F18
RS600 Databook
A-25
RS600 Databook
A-26
Appendix B
Revision History
Note: The revision number of this manual reflects either one of the two release states defined below:
Preliminary Release - Revision numbers from 0.1 to 0.9. Generally with incomplete information and/or
information subject to change.
Full Release - Revision numbers from 1.0 onwards. Occurring after essential elements have been reviewed,
typically after tape-out.
Rev 0.1 (June 2006)
•
Preliminary release.
Rev 0.2 (Feb 2006)
•
First release (Rev 0.1 has not been released publicly).
Rev 1.0 (July 2006)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Corrected VDD_CORE to 1.2V. Affected: Table 3-17, “Power Pins,”and Table 5-1, “Maximum and Minimum
Ratings.”
Updated Section 1.3.9, “DVI/HDMI”: Added reference to the HDMI interface multiplexed on the PCI-E graphics
lanes; clarified features of HDMI and HDCP support.
Updated Table 2-2, “Supported DDR2 Components,” and Table 2-3, “Supported DDR3 Components”: Removed
“Refresh” columns from the tables.
Added Section 2.3.2, “Data Mapping on the TMDS Interface Multiplexed on the PCI-E Graphics Lanes.”
Updated Table 3-1, “CPU Interface”: Added voltage level for CPU_VREF.
Move description for VDD_CPU_PACKAGE from section 3.12 to 3.11, as it is not a power pin.
Updated Table 3-9, “Miscellaneous PCI Express Signals”: Corrected connection requirement for PCE_CALRP (to
ground through a resistor).
Added Section 3.9, “TMDS Interface Multiplexed on the PCI-E Graphics Lanes.”
Updated Table 3-17, “Power Pins”: Corrected voltage of VDD_PCIE to 1.2V.
Updated Table 3-18, “Ground Pins”: Corrected description for AVSSN.
Updated Table 3-19, “Strap Definitions for the RS600”: Added STRAP_MEMSTRAPS to the table.
Updated Section 4.1, “Processor Front Side Bus Timing”: Corrected common clock signal hold time (T17) to 149ps
min; corrected Figure 4-1, “Front Side Bus Timing for Data Signals.”
Updated Table 4-6, “Power Rail Power Up Sequence Timing for the RS600”: Corrected description for T11 min.
Updated Section 4.2, “Memory Timing.”
Updated Table 4-5, “Timing Requirements for the OSCIN Pad”: Changed maximum cycle-to-cylcle jitter to 300ps
and removed peak-to-peark and longe-term jitter specifications.
Updated Table 5-1, “Maximum and Minimum Ratings”: Corrected voltage of VDD_PCIE to 1.2V.
Added Table 5-2, “DC Characteristics for Front Side Bus Signals.”
Added Table 5-3, “DC Characteristics for PCI-E Differential Clock (GFX_CLK, SB_CLK) Input.”
Added Table 5-4, “DC Characteristics for TTL Signals.”
Updated Table 5-7, “Electrical Requirements for DVI/HDMI” with correct data.
Updated Section 5.5.1, “Stencil Opening Size for Solderball Pads on PCB”: Added stencil opening size
recommendations.
RS600 Databook
B-1
Appendix B: Revision History
•
•
Revised Section 5.2.1, “RS600 Thermal Limits”: Added new parameters, descriptions, as well as values for θjb and
θjc.
Updated Table 6-2, “ACPI Signal Definitions”: Revised list of ACPI signals coming from the SB.
RS600 Databook
B-2

Ati RS600

Transcription

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