GEM project, C-Band polarimetry using a full digital

Transcription

GEM project, C-Band polarimetry using a full digital
GEM Project, C-Band Polarimetry
using a full digital correlator
www.av.it.pt/gem
Miguel Bergano
GRIT – Aveiro
FCT Grants
• POCTI/CTE-AST/57209/2004
• PTDC/CTE-AST/65925/2006
08/11/25
2º Congresso URSI Portugal
Authors
Miguel Bergano1, Francisco Fernandes1,2, L. Cupido 4, D. Barbosa1,2, R.
Fonseca1,2,3, D. M. Santos1,3, G. Smoot5,6,Ivan S. Ferreira7, Luis Reitano7
1
Grupo de Radioastronomia, Instituto de Telecomunicações, Portugal
2 CENTRA, Instituto Superior Técnico, Lisboa, Portugal
3 DET Universidade Aveiro, Aveiro, Portugal
4 Centro de Fusão Nuclear, Lisboa, Portugal
5 Lawrence Berkeley National Laboratory, USA
6 Physics Dept., University of California, Berkeley, USA
7 INPE – Instituto Nacional de Pesquisas Espaciais, Brasil
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2º Congresso URSI Portugal
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Overview
Unveil the Sky to CMBR;
‹ Applicable to a Galactic Experiment;
‹ High sensitivity radiometer;
‹ Superheterodyne Receiver with
Double Down Conversion – Zero IF;
‹ IF chain developed and tested;
‹ Full Digital Back-end;
‹ Stokes Parameters Calculation.
‹
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2º Congresso URSI Portugal
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Superheterodyne Receiver
(Base-band Complex Correlator)
Novel approach to digital correlators!
The radiometer/polarimeter gain budget:
Antenna LNA
Input
(dBm)
-105,6
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IF Pre
Passive
IF
Mixer
Converter
Amplifier Amplifier
Filter
ADC
26
-4
-7
31
56
2
Output(
dBm)
-79,6
-83,6
-90,6
-59,6
-3,6
-1,6
-2
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Receiver characteristics
Bandwith of 200MHz around 4.9GHz; ADS designed
Tant ~10K - total power of -105.6dBm–TOTAL GAIN~104 dB;
RF Cryogenic PHEMT InP LNAs (@ 77K);
Image rejection filter;
Latest RF technology and microstrip lines
SMD components; central freq. 600MHz
Slope Compensation Network application;
Diode Mixers; IF Preamplifier – filter 31dB gain;
IF Amplfier 71dB gain with digital control attenuator;
Zero IF converter; I/Q modulation per polarization
Full Digital correlator:
ADC at 200 MSPS with 8 bits of resolution;
Altera Cylone II FPGA working at 100MHz with
Interleaving;
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2º Congresso URSI Portugal
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IF part designed and tested
B=200MHz; 31dB; Butterworth
MMIC (best response flatness)
Flat gain; 71dB;
Digital attenuation
4.9GHZ; B=600MHz
Coupled Line filter
IF Chain+RF Filter
120dB isolation between ports
08/11/25
Frequency 600MHz; VCO; MMIC Amp.;
PLL synthesyzer; 7dBm
2º Congresso URSI Portugal
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Microwave Passive Filter
‹
‹
‹
‹
Central Frequency = 4,9 GHz;
Bandwidth = 800 MHz;
Coupled Lines;
ADS Design aided;
Electromagnetic Simulation.
Substrate Thickness
H
20 mil
Relative Dielectric Constant
εr
3,38
Conductor Thickness
T
0,35μm
Dielectric Loss Tangent
tan δ
0,0021
S - parameter
10
dB(S(2,1))
dB(S(1,1))
dB(S(1,2))
0
Port
P1
Num=1
dB(S(2,2))
-10
MCFIL
CLin1
Subst="MSub1"
W=574.232 um
S=35.599 um
L=9263.161 um
MCFIL
CLin2
Subst="MSub1"
W=988.568 um
S=157.076 um
L=9012.943 um
-20
MCFIL
CLin3
Subst="MSub1"
W=988.568 um
S=157.076 um
L=9012.943 um
[dB]
‹
Substrate – RO4003C
MCFIL
CLin4
Subst="MSub1"
W=574.232 um
S=35.599 um
L=9263.161 um
Port
P2
Num=2
-30
-40
-50
-60
-70
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
frequency [GHz]
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2º Congresso URSI Portugal
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IF Pre - Amplifier
Filter
Amplifier
‹
‹
‹
‹
‹
Gain = 31 dB
Slope Compensation Network;
Gain variation with frequency;
Gain variation with
Temperature;
S-Parameters Simulation.
‹
‹
‹
‹
‹
‹
‹
P1dB = -24 dBm
High Q filter;
Central Frequency = 600 MHz;
Bandwidth = 200 MHz;
T configuration
Butterworth Prototype;
Hand made Inductances
ADS Design aided;
Vcc =8V
L1
C1
L3
C3
L2
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IF Amplifier
‹
‹
‹
‹
‹
‹
‹
Gain = 71 dB;
Flat gain;
Digital attenuation control;
Slope Compensation Network;
Gain variation with frequency;
Gain variation with Temperature;
S-Parameters Simulation.
P1dB = -61 dBm
IP3= -41 dBm
Vcc =8 V
4
4
µC
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2º Congresso URSI Portugal
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Converter
‹
‹
‹
‹
‹
‹
Zero – IF Conversion (LB = 100MHz);
Phase (I) and Quadrature (Q) Modulation;
Signal Amplification (GSINAL = 16 => 25 dB);
Port Isolation = 120 dB;
Suitable for Stokes Parameters Calculation;
Microstrip Lines with equal lengths;
Protection (outside interference & parasitics).
Converter output
2
-8
[dBm ]
‹
-18
-28
-38
5
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2º Congresso URSI Portugal
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145
Frequency [MHz]
210
10
Local Oscillator
‹
‹
‹
‹
‹
Frequency = 600 MHz with 7 dBm;
Provides the converter with 4 signals
PLL Sinthesized;
Microstrip Lines with equal lengths;
Protection (outside interference & parasitics).
R2
0 dBm
50Ω
0º
≈ 7 dBm
R3
50Ω
0,6 dBm
10 dBm
0º
≈ 7 dBm
VCO
R1
R2
0 dBm
50Ω
≈ 7 dBm
90º
PLL
R3
50Ω
≈ 7 dBm
90º
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2º Congresso URSI Portugal
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Full 4-channel Digital Correlator
Correlations computed in a
FPGA after signal digitalization
(ADC interleaving) and outputs
I,Q,U Stokes signals:
Why an FPGA Cyclone II from ALTERA?
• Embedded Multipliers;
• Number of pins;
• Frequency.
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2º Congresso URSI Portugal
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Digital Correlator
ISA Interface output
• ADCs AD9481 from Analog
Devices.
• 250 Msps
• 8 bits of resolution
Analog inputs
Active Serial mode
programming interface
Cristal Oscilator
100 MHz
• FPGA EP2C8Q208C7 Cyclone II from ALTERA
• 8256 LE.
• Number of 9 bits multipliers = 36;
• 208 pins
• Speedgrade 7
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Full Digital Correlator
FPGA calculates the Stokes parameters (I, Q, U).
(VHDL code implementation by Francisco Fernandes)
1. Signals correlation from the 4 ADCs, (8 bits sum and
multiplications every)
2. Integration of correlated signals.
FPGA is an
ALTERA
Cyclone II
and works at
100 MHz
3. Output Stokes parameters to PC104
8 bits of
resolution
200 MSPS
0,5Vpp
ADC 1
ADC 2
ADC 3
ADC 4
N
N+1
N
N+1
N
N+1
FPGA
Cyclone II
⊗ ∫
→
I, Q, U
PC104
N
N+1
100 MHz
I,Q,U,V=F(ADC1,ADC2,ADC3,ADC4)
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2º Congresso URSI Portugal
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Main Features of PC104 (MOPSlcdLX*)
‹
Hardware
‹
Software
• 500 MHz AMD LX800TM
Processor
• 256 MByte DDR-RAM
• ChipDisk IDE 1 GByte
• Support: ISA, Ethernet
• Power supply: 5V
• Linux, kernel 2.4
• Dedicated, custom-made
software for FPGA
communication via ISA
bus (C lang. –
implemented by Francisco
Fernandes).
• SSH File transfer.
* www.kontron.com/MOPS
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LIRAe
Linux for Radio Astronomy embedded
LIRAe is a microlinux distribution, to run on
CPU embedded systems and control
radioastronomy digital correlators based on
FPGA chips.
The system was tested and runs on a PC104
from Kontron, model MOPSlcdLX.
Download available soon.
LIRAe main developer: Francisco Fernandes
email : [email protected]
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Mechanical Layout
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Conclusion : Radiometer facts
‹
‹
‹
‹
‹
‹
‹
Tsys < 20 K; B = 200 MHz; 104 dB gain
High-performance IF strip
Latest RF tech+ microstrip design + MMIC
New Radioastronomy Design:
Zero-IF Converter + I,Q modulation
Digital Correlator : 4-channel, FPGA
implemented!
Dynamic Range: Total=20dB,
Instantaneous=80dB
Suitable for state of the art radioastronomy
applications.
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2º Congresso URSI Portugal
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