35th final - DAC Virtual Resources

Transcription

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general chair’s welcome
Welcome to the 35th Design Automation Conference!
This marks a significant milestone in the history of DAC. It started as a small special interest group at the
IBM SHARE meeting back in 1963, blossomed as the Design Automation Workshop in 1964, and finally
ripened as the Design Automation Conference in 1975. The vendor exhibits, as we know them today,
originated in 1983.
Ever since its beginning, DAC has maintained excellence in its technical program and has become the
premier conference for the presentation of research and development work in design automation of
integrated circuits and electronic systems. DAC has also become the premier forum for the EDA industry
to exhibit the leading edge products and make new product announcements.
For the past several years, the DAC Executive Committee has been focusing on expanding the technical
program to meet the needs of the design engineers. This year, we received a record number of technical papers
on design methodology. It gives me great pleasure to say that about 40% of the technical program now
concentrates on design methodology. To complement the expansion of the technical program, we have also
expanded the exhibit area by introducing a special area on the floor, called Silicon Village, which is dedicated
to Silicon vendors to address the growing interdependence between Silicon and EDA vendors. This will provide
an opportunity for the attendees to interact with both EDA vendors and Silicon vendors at the same venue.
Another new attraction at DAC this year is the University Design Contest, a competition where university
researchers submitted system designs to be judged on the basis of innovation in their design flows and
their use of EDA tools. The top contestants will present their designs in a special session - a great place
for the practicing design engineers to interact with the university researchers.
This technical program was assembled under the leadership of this year’s Technical Program Co-Chairs
Randy Bryant and Jan Rabaey. Three hundred ninety papers from around the world were submitted to the
design tools and design methods tracks, and were reviewed by over 700 professionals along with detailed
examination by the Technical Program Committee, yielding 142 papers presented at the conference. The
papers are complemented by nine panel sessions and 8 embedded tutorials. Special this year is a session
to commemorate the 35th Design Automation Conference which provides both a retrospective of our past
accomplishments and a view to the future.
I want to thank all the people who contributed to DAC maintaining the premier conference status that it
enjoys: the Executive Committee, the Technical Program Committee, the EDA Industry Committee, DAC’s
sponsors, MP Associates, and especially the exhibitors, authors, speakers, session organizers and
session chairs. DAC is sponsored by ACM/SIGDA, IEEE Circuits and Systems Society, and EDA
Consortium. Their members represent the breadth of DAC’s participants and we are thankful for their
continued and active support.
Welcome to San Francisco and the 35th Design Automation Conference. We wish you
a very productive and fun-filled week.
Basant R. Chawla
General Chair, 35th Design Automation Conference
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Women’s
Workshop
Two
Exciting
Keynotes
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program highlights
Women’s Workshop - Forget the Ceiling - Break the Glass
This Sunday workshop is designed to help women develop a personal plan for career development.
See details on page 4
TUESDAY KEYNOTE
William J. Spencer
THURSDAY KEYNOTE
George H. Heilmeier
Chairman of the Board
SEMATECH, Inc., Austin, TX
Tuesday, June 16 - 9:00 AM
Esplanade Ballroom
Executive
Panel
Chairman Emeritus
Bellcore, Morristown, NJ
Thursday, June 18 - 1:00 PM
Gateway Ballroom
Leaders from the EDA vendor industry, the design community, and universities discuss how EDA can
continue to support rapid innovation in the electronics industry.
Technical
Program
Over 160 papers, panels, and embedded tutorials in five parallel tracks, covering system design,
advanced verification techniques and issues in deep-submicron design.
See details on pages 7 - 33
35 Years of
Design
Automation
University Design
Contest
6 New
Tutorials
Friday,
June 19
A panel of design automation visionaries presents a retrospective of 35 years of DA, and a lookforward into the coming decade.
See session 49 on page 33
The best in university design and design methodology is presented in a special session and recognized
by a new award.
See session 3 on page 15
Tutorials
1) Design Validation Techniques
2) Design of Complex Mixed-Signal Systems on a Chip
3) CAD for System-Design: Models, Issues, and Some Emerging Tools
4) Interconnect Analysis in High-Frequency, Sub-Micron, Digital VLSI Design
5) Finding Design Errors and Locating Defects: The Same Detective Story
6) High Performance RTL Coding Styles for Synthesis
See details on pages 35 -39
DAC Sponsors
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Silicon Village
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DAC highlights
The newest feature of the exhibit floor. The area features silicon vendors offering ASIC, programmable logic,
foundry and IP solutions.
Silicon Village Exhibitors
ACTEL CORP.
ADVANCED RISC MACHINES (ARM)
ALBA CENTRE (THE)
ALPINE MICROSYSTEMS INC.
AMERICAN MICROSYSTEMS, INC.
CHIP EXPRESS CORP.
COREEL MICROSYSTEMS
CYPRESS SEMICONDUCTOR
IBM CORP.
INICORE
INTEGRATED SILICON SYSTEMS LTD.
LATTICE SEMICONDUCTOR CORP.
LIGHTSPEED SEMICONDUCTOR
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, FPGA
Exhibit
Information
Exhibitor
Presentations
Monday, June
15
Demo Suites
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, PSS
NEWPORT WAFER-FAB LTD.
PHILIPS SEMICONDUCTORS
PIVOTAL TECHNOLOGIES, INC.
QUICKLOGIC CORP.
RAPID
SEMICONDUCTORES INVESTIGATION Y DISENO (SIDSA)
SIERRA RESEARCH & TECHNOLOGY, INC.
SILICON STRATEGIES
SIMPLE SILICON INC.
TEXAS INSTRUMENTS
TOWER SEMICONDUCTOR LTD.
UNITED MICROELECTRONICS CORP. GROUP
VAUTOMATION INC.
The newest innovations at your fingertips with exhibitors highlighting their latest products.
Exhibitor Listing
Exhibitor Presentation Abstracts
Exhibitor Product Descriptions
Pages 61 - 62
Pages 67- 88
Pages 90 - 166
• A full day of 20-minute exhibitor presentations - choose from 132 presentations; see pages 65-88 for details.
• $40 full exhibit-only registration will allow you to attend exhibits Monday through Wednesday.
demo suite hours:
Monday - Wednesday, June 15 -17, 1998
Thursday, June 18, 1998
8:00 AM - 9:00 PM
8:00 AM - 5:00 PM
• Demo Suites will be in Halls D & E of the Moscone Center.
• Exhibiting companies will have the opportunity to give their customers private demos without leaving the
Convention Center.
• Demo Suites are available by invitation only.
WWW.DAC.COM
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The DAC Web page (http://www.dac.com) provides your connection to the conference and other information of
interest to the DA community.
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about the conference
The 35th Design Automation Conference provides a high-quality program facilitating technology interchange
among design automation researchers and developers, the engineers who use DA systems to design, test and
manufacture circuits and systems, the vendors who provide DA systems and tools, and new this year, silicon
vendors. Five full days of design automation activities are planned. New product introductions and application
notes will be highlighted on Monday in the Exhibitor Presentations, and more than 200 companies will exhibit the
latest commercially available products Monday through Wednesday. The latest technical innovations from DA
research and development and the use of DA will be presented in five parallel sessions, Tuesday through
Thursday, in the Technical Program. Six full-day tutorials will be offered on Friday.
The technical program opens with the Executive Plenary Panel, immediately following the Keynote Address. The
Executive Plenary Panel is a panel discussion featuring the CEOs of leading EDA companies, high level
executives of system/silicon companies and a world-renowned academician. The panel will discuss the issues
facing designers and the vision for their solutions.
The technical program consists of technical papers, embedded tutorials, and panel discussions, organized in 5
parallel sessions. The design tools sessions focus on new techniques for enhancing the performance and
capabilities of EDA tools. The design methods sessions focus on the results and insights gained by applying
EDA tools to actual system designs. Included in the technical program are 8 panel discussions covering topics
ranging from intellectual property issues to electrical noise and signal integrity.
new to the conference
This year, DAC introduces Silicon Village, a special area on the exhibit floor dedicated to silicon vendors to
address the growing interdependence between silicon and EDA vendors. This will provide an opportunity for the
attendees to interact with both the EDA vendors and silicon vendors concurrently.
Also new to the conference is the University Design Contest, a competition where university researchers
submitted system designs to be judged on the basis of innovativeness of their design flows and their use of
EDA tools. The top contestants will present their designs in a special session on Tuesday afternoon.
This being the 35th annual Design Automation Conference, a special session on Thursday afternoon will
provide both a retrospective of our past accomplishments and a view to the future. This session will consist of
presentations by three leading contributors to EDA.
conference survey
Again this year we would like you to voice your opinion on various aspects of the conference. DAC is conducting
surveys to determine how to best serve your needs. Please take a few moments to participate if you are
approached by one of our surveyors. Look for interviewers wearing “???” buttons at various locations around
the show. Help make a difference in DAC and receive a Swiss Army-style pocket knife for participating. All survey
participants will also be put in a raffle with a chance to win a “Leather Bomber Jacket” donated by Compaq.
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Sunday
June 14, 1998
9:00 to 4:00
Moscone Center
San Francisco, CA
Room 301
workshop for women in design automation
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“Forget the Ceiling – Break the Glass”
Women who acknowledge the "glass ceiling" but believe in themselves and their aspirations are breaking the barriers that
have traditionally kept women from advancing in technical fields. This workshop is designed to help women identify the
behaviors and attitudes in themselves that may be holding them back, learn how highly successful women made it to the
top of their chosen field, and develop a personal plan for career advancement.
Workshop Chair: Penny Herscher - President and CEO, Simplex Solutions, Inc.
Organizing Committee:
Steering Committee:
Barb Acosta - Group Director, Cadence Design Systems, Inc.
Lois DuBois - Communications Consultant
Jody Fast - Corporate Marketing, Simplex Solutions, Inc.
Deirdre Hanford - Vice President, Synopsys, Inc.
Leigh Huang - Director, Avant! Corp.
Jennifer Smith - Vice President, Robertson Stevens
Charlotte Acken - Consultant
Marie R. Pistilli - MP Associates, Inc.
Kathy Preas - CD-ROM Publications
Session 1: Keynote Speech Top 10 Ways Women Shoot Themselves in the Workplace
Nora M. Denzel - Senior Vice President, Legato Systems, Inc.
Nora M. Denzel
eynote Speaker
r. Vice President
Legato
Systems, Inc.
This exciting talk will acquaint you with the ten most common mistakes women make in trying to climb the corporate career
ladder. You will learn first hand what the mistakes are and how to combat them from someone who has been there. Using
a lot of humor and personal experience, Nora will share with you what she learned as she climbed the corporate ladder at
IBM to become one of their youngest executives at 33! She will talk candidly about how she did it, and how you can do it
at an even faster pace.
Session 2: Panel: The Habits of Highly Successful Women
Moderator: Penny Herscher - President and CEO, Simplex Solutions, Inc.
Speakers: Lily Chang - Mentor Graphics Corp.
Laila Razouk - Network Products Div. AMD
Richard Newton - Univ. of California, Berkeley
Cheryl Shavers - Intel Corp.
Vicki Pachera - Cadence Design Systems, Inc. Ellen Yoffa - IBM Corp./TJ Watson Research Ctr.
Penny Herscher
Workshop Chair
President & CEO
Simplex
Solutions, Inc.
The objective of this panel is to share successful habits that others have found work for them, and to create a dialog
through Q&A to address questions you may have about your personal challenges. Each panelist will share with you the
habits they have developed to succeed in the technical world, or have observed in others. They will then be available to
answer your questions during the Q&A session.
Session 3: Tutorial on Mentoring
Amy Gonzales - Vice President, Women Unlimited
Amy Gonzales is a member of a pioneering team of women who share a vision for mentoring. Amy will share with you
some of the benefits of mentoring and describe the ways that many U.S. professional women have taken advantage of
mentoring opportunities. She will help you discern whether having or being a mentor would be helpful for you, and describe
one of the mentoring programs available.
Session 4: Workshop
Ceiling
Identifying Changes You Can Make to Break Your Personal
The audience will break up into small work groups to each create a plan of action for their personal career challenges.
Session 5: Guest Speaker
Breaking Records Through Visualization
Barb Acosta - Group Director, Cadence Design Systems, Inc.
Information
can be
found at
www.dac.com.
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Barb is a three time Olympic trialist runner, with world class ranking from 5000 meters through marathon. She also
happens to work in EDA at Cadence! In an inspiring talk, Barb will share techniques to set and break personal records that
you can directly apply to setting and breaking your own career goals.
8:00 AM Registration & Breakfast
10:00 AM BREAK
1:00 PM Tutorial on Mentoring
9:00 AM Welcome by Penny Herscher
10:15 AM Successful Women Panel
1:45 PM BREAK
9:15 AM Keynote Speech, Nora Denzel 12:00 PM LUNCH
2:00 PM Identifying Changes Workshop
The Workshop registration fee includes: a continental breakfast, lunch and the reception.
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Tuesday
Opening
Keynote
Address
9:00 to
10:15
ESPLANADE
BALLROOM
no badge
required to
attend the
Tuesday
Keynote
Thursday
Keynote
Address
1:00 to
1:45
GATEWAY
BALLROOM
no badge
required to
attend the
Thursday
Keynote
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keynote addresses
Design Automation Can Help the Semiconductor
Industry Address Its Many Challenges
William J. Spencer
SEMATECH, Inc.
Austin, TX
Silicon technology has been the economic driver for much of the Information Age, by
providing a 25-30% year-over-year improvement in cost per unit of performance. This
amazing performance has been fueled by constantly improving semiconductor technology,
including major gains in design automation. For the industry to remain on this historic
productivity curve, break-throughs will be required in several aspects of semiconductor
manufacturing technology often linked strongly to design.
Bill Spencer is currently Chairman of SEMATECH, a research and development consortium consisting of sixteen
international corporations involved in semiconductor manufacturing. From 1990-1997, he served as President and
Chief Executive Officer of SEMATECH. Prior to 1990, he was Group Vice President and Senior Technical Officer at
Xerox Corporation in Stamford, Connecticut, as well as Vice President and Manager of the Xerox Palo Alto Research
Center (PARC). He was Director of Systems Development and also Director of Microelectronics at Sandia National
Laboratories from 1973 to 1981, prior to joining Xerox. He began his career at Bell Telephone Laboratories in 1959.
He received his Ph.D. and M.S. from Kansas State University, and an A.B. from William Jewell College in Missouri.
Spencer is also a Research Professor of Medicine at the University of New Mexico, where the first implantable
electronic drug delivery systems were developed jointly with Sandia National Labs. For this work, he received the
Regents Meritorious Service Medal and later a doctor of science degree from William Jewell College. He is currently
a Director of Adobe Systems, Investment Corporation of America, SRI International and the Austin Symphony. He
is also a member of the Board of Trustees of the Computer Museum and William Jewell College.
He has served on several National Research Council studies in the areas of technology, trade, corporation and
competition. In 1998, he will co-chair, with Dick Thornburgh, a NRC workshop on “Harnessing Technology for America’s
Future Economic Growth”. He will also serve as a Regents Professor at the University of California at Berkeley.
From POTS to PANS: Transition in the World of
Telecommunications for the Late 90s and Beyond
George H. Heilmeier
Chairman Emeritus
Bellcore
Morristown, NJ
The telecommunications industry is undergoing transitions at an unprecedented rate from a
provider of plain old telephone service (POTS) to a provider of "pretty awesome new services"
(PANS). This presentation will discuss the forcing factors and the technical/business
transitions that are occurring at the industry, network, service and operations systems level.
Key technical issues facing the industry as well as some agenda setting themes will also be
discussed along with some of the implications for the microelectronics industry.
Dr. Heilmeier, world renowned for his pioneering work in the development of liquid crystal displays (LCDs) and the
recipient of numerous awards including the National Medal of Science and the IEEE Medal of Honor, was drafted
out of Texas Instruments in 1991 to fill the top job at Bellcore. Over the past six years, Heilmeier has piloted the
company’s successful transition from the nation’s largest resource consortium to a competitive, profitable, growing,
commercial enterprise with an expanded client base of more than 800 customers in the U.S. and abroad.
Prior to joining Bellcore in March 1991, as the company’s President and Chief Executive Officer, Heilmeier was
Senior Vice President and Chief Technical Officer of Texas Instruments, Inc. Dr. Heilmeier, a native of Philadelphia,
holds a B.S. in electrical engineering from the University of Pennsylvania and M.A., M.S.E., and Ph.D. degrees in
solid-state electronics from Princeton University. He has also been awarded honorary doctorates from Stevens
Institute and Technion, the Israel Institute of Technology.
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important information at a glance
exhibit hours:
demo suite hours:
(badge required)
(by invitation only)
Monday, June 15
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
10:00 AM to 6:00 PM
10:00 AM to 6:00 PM
10:00 AM to 6:00 PM
–
8:00
8:00
8:00
8:00
AM
AM
AM
AM
to
to
to
to
9:00
9:00
9:00
5:00
PM
PM
PM
PM
at-conference registration hours
The registration desk will be located in the North Lobby of the Moscone Center and will be open at
the following times:
Sunday, June 14
Sunday, June 14
Monday, June 15
8:00 A M to 10:00 A M
4:00 PM to 6:00 PM
8:00 AM to 6:00 PM
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
7:30 AM to 5:00 PM
7:30 AM to 5:00 PM
7:30 AM to 3:00 PM
information desk/messages
The information desk is located in the concourse on the exhibit level. To receive a message at
conference, the DAC Information Desk must be contacted. A message board is located at the information
desk. (Attendees may also send email to one another via DACnet). There are also people available to
answer questions concerning the San Francisco area. For assistance please call (415) 978-3600.
first-aid rooms
The first-aid room for the South Hall is located outside of room 106. The first-aid room for the North Hall
is located outside of room 125. The first-aid room for the Esplanade Ballroom is located next to room 300.
For assistance please call the control room at (415) 974-4021, and ask for the first-aid room. A
nurse will be on duty at all times while meetings and exhibits are open.
business center
Packaging, UPS, photocopy/fax service, computer rental, and office supplies will be in the exhibit
level South Lobby outside Hall C.
• Coat and baggage check will be in the South Lobby.
DACnet -’98
DACnet workstations will be located in the South Lobby, Esplanade Lobby, the concourse, and the
Press room.
food services
Luncheon service is available Monday through Thursday. Food courts are located in room 206 on
the Mezzanine Level, and room 300 on the Esplanade Level. DAC hosted coffee breaks will be in
the Esplanade Lobby and meeting rooms 302, 309 and 310.
MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
(303) 530-4333 - DAC
(303) 530-4562 - MPA
(303) 530-4334 - Fax
[email protected] - Email
It has been our pleasure to serve you professionally this year. We wish to thank the DAC sponsors, and
the DAC Executive Committee for this opportunity. We also wish to thank the Session Chairs, Speakers,
the Program Committee, and the Exhibitors for their cooperation with MP Associates, Inc.
Marie R. Pistilli, Exhibit Manager & Pat O. Pistilli, Conference Manager
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chedule
tuesday, june 16
General Session and Keynote Speaker
(no badge required)
9:00
to
10:15
Design Automation Can Help the Semiconductor Industry Address Its Many Challenges
Break
BREAK
William J. Spencer
Chairman of the Board, SEMATECH, Inc., Austin, TX
Opening Remarks • Awards • Keynote Address • (Room: Esplanade Ballroom)
Executive Plenary Panel:
10:30
to
12:00
Customers, Vendors, and Universities:
Determining the Future of EDA Together
(No badge required)
Lunch
RM #
2:00
to
4:00
LUNCH 12:00 - 2:00
RM 102
RM 301
RM 305
RM 304
RM 103
Session 1
Session 2
Session 3
Session 4
Session 5
Interfaces for
Design Reuse
(Tutorial included)
Analog and MixedSignal Design
Tools
University Design
Contest
Embedded System
Design and
Exploration
Panel: Taming
Noise in DeepSubmicron Digital
Designs
(Tutorial included)
BREAK
Break
4:30
to
6:00
6:00
to
7:00
(Room: Esplanade Ballroom)
Session 6
Session 7
Session 8
Session 9
Session 10
Control and Data
Driven High Level
Synthesis
Synthesis Flow in
Deep Submicron
Technologies
(Tutorial included)
Environment for
Collaborative
Design
New Methods in
Functional
Verification
Panel: Hardware/
Software Co-Design The Next Embedded
System Design
Challenge
DAC Cocktail Party at the San Francisco Marriott 6:00PM - 7:00PM
(Yerba Buena Ballroom)
Exhibit Hours 10:00 AM – 6 : 0 0 P M / Demo Suite Hours 8:00 AM – 9 : 0 0 P M
• Design Methods Track is in shaded area.
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RM #
8:30
to
10:00
chedule
wednesday, june 17
RM 102
RM 301
RM 305
RM 304
RM 103
Session 11
Session 12
Session 13
Session 14
Session 15
Extraction and
Modeling for
Interconnect
Processor Design
and Simulation
Panel: How Much
Analog Does a
Designer Need to
Know for Successful
Mixed-Signal
Design?
System-Level Power Boolean Methods
Optimization
BREAK
Break
10:30
to
12:00
Session 16
Session 17
Session 18
Session 19
Session 20
Performance
Modeling and
Characterization for
Embedded Systems
Advances in
Placement and
Partitioning
Parasitic Device
Extraction and
Interconnect
Modeling
Design
Optimization for
DSP
Panel: User
Experience With
High Level Formal
Verification
Session 23
Session 24
Session 25
Routing for
Performance and
Crosstalk
Practical
Optimization
Methodologies for
High Performance
Design
RF IC Design
Methodology
(Tutorial included)
Session 29
Session 30
Low Power Design
Using Multiple
Thresholds and
Supplies
Panel: Technical
Challenges of IP
and Systems-onChip: The ASIC
Vendor Perspective
Lunch
LUNCH 12:00 - 2:00
Session 21
2:00
to
4:00
Session 22
Bridging the Gap Logic Optimization
Between Simulation
and Formal
Verification
(Tutorials included)
Break
BREAK
Session 26
4:30
to
6:00
Session 27
Session 28
Theory and Practice BDD Approximation
Interconnect
Techniques
in High Level
Modeling and
Synthesis
Timing Simulation
35 Years of DAC Anniversary Party
7:30PM - 10:00PM at the San Francisco Marriott (Yerba Buena Ballroom)
Exhibit Hours 10:00 AM – 6 : 0 0 P M / Demo Suite Hours 8:00 AM – 9 : 0 0 P M
8
S
RM #
8:30
to
10:00
chedule
thursday, june 18
RM 102
RM 301
RM 305
RM 304
RM 103
Session 31
Session 32
Session 33
Session 34
Session 35
Software Synthesis Formal Methods in
and Retargetable
Functional
Compilation
Verification
12:00
Lunch
2:00
2:00
to
4:00
Session 36
Session 37
Session 38
Timing Analysis
New Techniques
in State Space
Explorations
Advanced ATPG
Techniques
Session 39
Session 40
Practical Experience Panel: The EDA
of Functional
Startup Experience:
Verification for
The First Product
Complex ICs
KEYNOTE 1:00 - 1:45 (Lunch Not Included)
From POTS to PANS: Transition in the World of Telecommunications for the Late 90s and Beyond.
George H. Heilmeier - Chairman Emeritus, Bellcore, Morristown, NJ
Gateway Ballroom (no badge is required to attend)
Session 41
Session 42
Session 43
Session 44
Session 45
Fast Functional
Simulation
(Tutorial included)
Power Estimation
and Modeling
Technology
Mapping for
Programmable
Logic
Power Dissipation
and Distribution in
High Performance
Processors
Panel: Challenge
in the Test on
System-on-a-Chip
Era
(Tutorial included)
BREAK
Break
4:30
to
6:00
Interconnect
Panel: Design
Analysis and
Productivity: How to
Reliability in Deep Measure It, How to
Sub-micron
Improve It
BREAK
Break
10:30
to
12:00
Core Test
and BIST
RM 301
RM 305
RM 304
RM 103
Session 46
Session 47
Session 48
Session 49
Controller
Decomposition for
Power and Area
Minimization
IP Protection
Technologies
Case Studies of
New Design
Methods
Thirty-Five Years of Design Automation,
a Retrospective and a Look-Forward
(no badge required)
Demo Suite Hours 8:00 AM – 5 : 0 0 P M
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tutorials friday, june 19
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Tutorials will be held at the Moscone Center in the Esplanade Ballrooms 301 -306.
8:00 AM - Tutorial Registration Opens (Esplanade Lobby)
8:30 AM - Continental Breakfast
9:00 AM - Tutorials Begin
12:00 Noon - Lunch
5:00 PM - Tutorials End
Tutorial 1
Room 305
Design Validation Techniques
Organizer: Gitanjali Swamy - Boston Advanced Development Labs., Mentor Graphics Corp., Boston, MA
Tutorial 2
Room 302
Design of Complex Mixed-Signal Systems on a Chip
Organizer: Ken Kundert - Cadence Design Systems, Inc., San Jose, CA
Tutorial 3
Room 303
CAD for System Design: Models, Issues, and Some
Emerging Tools
Organizer: Gaetano Borriello - Univ. of Washington, Seattle, WA
Tutorial 4
Room 304
Interconnect Analysis in High-Frequency,
Sub-Micron, Digital VLSI Design
Organizer: Peter Feldmann - Lucent Technologies Bell Labs., Murray Hill, NJ
Tutorial 5
Room 301
Finding Design Errors and Locating Defects: The Same
Detective Story
Organizer: Miron Abramovici - Lucent Technologies Bell Labs., Murray Hill, NJ
Tutorial 6
Room 306
High Performance RTL Coding Styles for Synthesis
Organizer: Joseph Pick - Synopsys, Inc., Bethesda, MD
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topics and related sessions
If you are interested in the following topics please see the related
sessions listed below.
Silicon Village
Sessions: 1, 7, 24, 30, 33, 35, 39, 43, 45, 47
System Design and Optimization
Sessions: 3, 4, 10, 11, 14, 16, 19, 31, 33, 39, 45, 46, 48, Tutorial 3
Logic and High Level Synthesis and Optimization
Sessions: 6, 7, 22, 26, 31, 43, 48, Tutorial 6
Synthesis and Optimization Techniques
Sessions: 12, 27, 37
Design Verification
Sessions: 9, 14, 20, 21, 28, 32, 36, 39, 41, Tutorial 1
Test and Validation
Sessions: 2, 33, 38, 45, Tutorial 5
Deep Sub-Micron
Sessions: 5, 7, 13, 18, 23, 28, 34, Tutorial 4
Interconnect
Sessions: 13, 18, 23, 28, 34, Tutorial 4
Physical Design
Sessions: 7, 17, 23
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topics and related sessions
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If you are interested in the following topics please see the related
sessions listed below.
High-Performance Design Techniques
Sessions: 14, 24, 44
Low-Power Design Techniques
Sessions: 11, 29, 42, 44, 46
Mixed Signal & RF
Sessions: 2, 15, 25, Tutorial 2
Design Reuse & Intellectual Property
Sessions: 1, 30, 33, 47
Collaborative & Distributed Designs
Sessions: 8, 47
Product & Design Management
Sessions: 8, 35, 40
FPGAs
Sessions: 3, 12, 43
DSP, Communications & Consumer Applications
Sessions: 3, 19, 25, 29, 48
Microprocessors
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Sessions: 3, 14, 39, 44
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opening session
Opening remarks
9:00 AM
to
10:15 AM
Esplanade
Ballroom
Basant R. Chawla
General Chair
Randal E. Bryant
Design Tools Co-Chair
Jan M. Rabaey
Design Methods Co-Chair
Awards
James Cohoon
ACM Representative
Bing Sheu
Vice President for Conferences IEEE/CAS
Opening keynote address
William J. Spencer
SEMATECH, Inc., Austin, TX
10:30 AM
to
12:00 PM
Esplanade
Ballroom
Executive Plenary Panel: Customers, Vendors, and Universities:
Determining the Future of EDA Together
Chair: Thomas P. Pennino - Lucent Technologies, Bell Labs., Holmdel, NJ
Organizer: Mike Murray - Acuson Corp., Mountain View, CA
Progress in the the EDA industry depends on the cooperative efforts of customers, vendors, and
universities. DAC's opening panel brings together leaders from these communities to discuss how EDA
can continue to support rapid innovation in the electronics industry. What are the design challenges
ahead? What new EDA technologies and working relationships are required for customers and
universities to meet these challenges? What do customers want in a vendor? What do vendors want in
a customer? How can universities contribute, and what can customers and vendors do in return? Come
join us for a lively and thought-provoking session on the issues which will shape the future of EDA.
Panel Members:
Robert Brodersen - Univ. of California, Berkeley, CA
Johan Danneels - Alcatel Microelectronics, Zaventem, Belgium
Aart de Geus - Synopsys, Inc., Mountain View, CA
Jack Harding - Cadence Design Systems, Inc., San Jose, CA
Wally Rhines - Mentor Graphics Corp., Wilsonville, OR
Gadi Singer - Intel Corp., Santa Clara, CA
(No badge required for this session)
All Design Methods Sessions are shaded green.
Two Plenary Panels are shaded dark green.
(Page 13 and 33)
13
t
uesday, june 16
SESSION 1
2:00
to
4:00
§ - denotes
best paper
All speakers are
denoted in bold
S - denotes
short paper
presentation,
15 minutes
14
Room: 102
SESSION 2
Room: 301
INTERFACES FOR DESIGN
REUSE
ANALOG AND MIXED-SIGNAL
DESIGN TOOLS
Chair: Gaetano Borriello - Univ. of Washington,
Seattle, WA
Organizers: Timothy Kam, Luciano Lavagno
Chair: Joseph P. Skudlarek - Analogy, Inc.,
Beaverton, OR
Organizers: Alan Mantooth, Hidetoshi Onodera
Effective reuse of pre-designed components is a key
issue in system design, and interface design is an
essential technology for achieving it. In this session
we have a tutorial devoted to the state of the art in
asynchronous design and applications, showing that
this is no longer black magic, but a methodology
supported by analysis and synthesis tools. This is
followed by two papers devoted to synchronous
interface synthesis, based on specifications of the
interfaced protocols as regular expression and on a
fixed finite state machine-based architecture
respectively.
This session spans many different areas of tools for
analog and mixed-signal design. The first paper
describes a multi-grid method for solving integrated
equations that allow one to extract substitute coupling
parameters. Next, a paper is presented on phase noise
in oscillators. This paper covers both the theory and
methods for characterization. The third paper deals with
applying adaptive algorithms to analog test - specifically
for fault detection. The last paper describes an
automated constraint transformation procedure for topdown analog IC design.
1.1 Embedded Tutorial: Asynchronous
Interface Specification, Analysis and Synthesis
Michael Kishinevsky - Intel Corp., Hillsboro, OR
Jordi Cortadella - Univ. Politecnica de
Catalunya, Barcelona, Spain
1.2 Automatic Synthesis of Interfaces
Between Incompatible Protocols
Roberto Passerone - Univ. of California,
Berkeley, CA
James A. Rowson - Alta Group of Cadence
Design Systems, Inc., Sunnyvale, CA
Alberto L. Sangiovanni-Vincentelli - Univ. of
California, Berkeley, CA
1.3 Automated Composition of Hardware
Components
James Smith, Giovanni De Micheli - Stanford
Univ., Stanford, CA
2.1 Multilevel Integral Equation Methods for
the Extraction of Substrate Coupling
Parameters in Mixed-Signal ICs
Mike Chou, Jacob K. White - Massachusetts Inst.
of Tech., Cambridge, MA
2.2 Phase Noise in Oscillators: A Unifying
Theory and Numerical Methods for
Characterisation
Alper Demir - Bell Labs., Lucent Tech., Murray
Hill, NJ
Amit Mehrotra - Univ. of California, Berkeley, CA
Jaijeet S. Roychowdhury - Bell Labs., Lucent
Tech., Murray Hill, NJ
2.3 Efficient Analog Test Methodology Based
on Adaptive Algorithms
Luigi Carro, Marcelo Negreiros - Univ. Federal
do Rio Grande do Sul, Porto Alegre, Brazil
2.4 General AC Constraint Transformation for
Analog ICs
Bogdan Arsintescu - Delft Univ. of Tech., Delft,
The Netherlands
Edoardo Charbon, Enrico Malavasi, Umakanta
Choudhury, William H. Kao - Cadence Design
Systems, Inc., San Jose, CA
t
uesday, june 16
SESSION 3
Room: 305
UNIVERSITY DESIGN
CONTEST
Chair: Mary Jane Irwin - Penn State
Univ., University Park, PA
Organizer: Jan M. Rabaey
A first for DAC, this session presents original
electronic designs developed at Universities
and resulting in operational implementations.
The designs span a diversity of application
areas
including
wireless,
DSP,
microprocessors and multiprocessors and
use design methodologies and techniques
ranging from custom ICs, to ASICs, to
FPGAs, to PCBs.
3.1 Design Methodology Underlying a
Single-Chip CMOS 900 MHz SpreadSpectrum Wireless Transceiver
J. Rael, A. Rofougaran, G. Chang, J. Y.-C.
Chang, M. Rofougaran, M. Djafari, P.J.
Chang, Asad Abidi - Univ. of California, Los
Angeles, CA
3.2 A Video Signal Processor for
MIMD Multiprocessing
Joerg Hilgenstock, Klaus Herrmann, Jan
Otterstedt, Dirk Niggemeyer, Peter Pirsch Univ. of Hannover, Hannover, Germany
3.3 Realization of a Programmable
Parallel DSP for High Performance Image
Processing Applications
Jens Peter Wittenburg, Willm Hinrichs,
Johannes Kneip, Martin Ohmacht, Mladen
Berekovic, Hanno Lieske, Helge Kloos,
Peter Pirsch - Univ. of Hannover, Hannover,
Germany
3.4S A Multiprocessor DSP System
Using PADDI-2
R.A. Sutton, Vason P. Srini, Jan M.
Rabaey - Univ. of California, Berkeley, CA
3.5S The Design and Implementation of
The Numachine Multiprocessor
Alex Grbic, Stephen Dean Brown, Steve
Caranci, Robin Grindley, Mitch R. Gusat,
Guy Lemieux, Kelvin Loveless, - Univ. of
Toronto, Toronto, ON, Canada
Naraig Manjikian - Queen’s Univ., Kingston
Canada
Sinisa Srbljic - Univ. of Zagreb, Zagreb,
Croatia
Michael Stumm, Zvonko Vranesic - Univ. of
Toronto, Toronto, ON, Canada
Zeljko Zilic - Lucent Tech., Allentown, PA
SESSION 4
Room: 304
SESSION 5
Room: 103
EMBEDDED SYSTEM
DESIGN AND
EXPLORATION
TAMING NOISE IN
DEEP-SUBMICRON
DIGITAL DESIGNS
Chair: Ivo Bolsens - IMEC, Leuven,
Belgium
Organizers: James A. Rowson,
Anders Forsen
Chair: Kenneth L. Shepard - Columbia
Univ., New York, NY
Organizers: Kenneth L. Shepard,
Takahide Inoue
The first paper discusses successive formal
reinforcement of embedded systems,
starting from the general purpose language,
JAVA. The second paper explains the
mapping of abstract data types into an
optimal memory architecture and control.
The third paper proposes a new algorithm for
mapping a specification on a heterogeneous
multiprocessor architecture. The last paper
discusses control composition of distributed
systems.
5.1 Embedded Tutorial: Design
Methodologies for Noise in Digital
Integrated Circuits
Kenneth L. Shepard - Columbia Univ.,
New York, NY
4.1 Design and Specification of
Embedded Systems in Java Using
Successive, Formal Refinement
James Shin Young, Josh MacDonald,
Michael Shilman, Abdallah Tabbara,
Paul Hilfinger, A. Richard Newton - Univ.
of California, Berkeley, CA
4.2 Efficient System Exploration and
Synthesis of Applications with Dynamic
Data Storage and Intensive Data Transfer
Julio Leao da Silva Jr., Chantal Y k m a n Couvreur, Miguel Miranda, Kris Croes,
Sven Wuytack - IMEC, Leuven, Belgium
Gjalt de Jong - Alcatel Telecom,
Antwerpen, Belgium
Francky Catthoor, Diederik Verkest,
Paul Six, Hugo De Man, - IMEC,
Leuven, Belgium
4.3 Design Space Exploration
Algorithm for Heterogeneous MultiProcessor Embedded System Design
Ireneusz Karkowski, Henk Corporaal Delft Univ. of Tech., Delft, The Netherlands
4.4 Modal Processes: Towards
Enhanced Retargetability Through
Control Composition of Distributed
Embedded Systems
Pai Chou, Gaetano Borriello - Univ. of
Washington, Seattle, WA
Panel: Taming Noise in
Deep Submicron
Digital ICs
Chair: Nagaraj NS - Texas Instruments,
Dallas, TX
Organizer: Takahide Inoue - Sony
Corp., Milpitas, CA
As technology scales into the deep
submicron regime, noise immunity is
becoming a metric of comparable
importance to area, timing, and power for the
analysis and design of digital VLSI chips.
Noise has two deleterious effects on digital
design. In the most serious cases, it can
produce functional failures in hardware.
Even when noise is not severe enough to
cause hardware fails, it can have an impact
on timing, affecting both delay and slew. This
panel will consider the noise issues involved
in the design of circuits and interconnect as
well as the important trade-offs that exist
between noise immunity and performance.
PANEL MEMBERS:
Barbara Chappell - Intel Corp.,
Hillsboro, OR
John MacDonald - Sun Microsystems,
Palo Alto, CA
Bob Masleid - IBM Corp., Austin, TX
John McBride - Hewlett-Packard, Fort
Collins, CO
Chris Noughton - Digital Equipment,
Hudson, MA
Kenneth L. Shepard - Columbia Univ.,
New York, NY
Xiaonan Zhang - Metaflow
Technologies, Inc., La Jolla, CA
15
t
uesday, june 16
SESSION 6
4:30
to
6:00
§ - denotes
best paper
Room: 102
Room: 301
CONTROL AND DATA DRIVEN
HIGH LEVEL SYNTHESIS
SYNTHESIS FLOW IN DEEP
SUBMICRON TECHNOLOGIES
Chair: Kayhan Kucukcakar - Motorola, Inc.,
Tempe, AZ
Organizers: David Ku, Timothy Kam
Chair: Ralph H.J.M. Otten - Delft Univ. of Tech.,
Delft, The Netherlands
Organizers: Sharad Malik, Randal E. Bryant
This session contains papers that describe novel
advances in the theory and practice of high level
synthesis. The first paper describes a transformational
approach to control-intensive designs. The second
paper incorporates speculative execution in the
scheduling of control-flow descriptions. The third paper
reformulates synthesis in terms of data transfers, and
the last paper describes rate optimal design of
recursive dataflow graphs.
This session examines the impact of deep
submicron technologies. It starts with an embedded
tutorial on possible approaches for dealing with this
impact. It is followed by a paper that presents a
methodology for combining technology mapping with
floorplanning and placement.
6.1 Fact: A Framework for the Application of
Throughput and Power Optimizing
Transformations to Control-Flow Intensive
Behavioral Descriptions
Ganesh Lakshminarayana, Niraj K. Jha Princeton Univ., Princeton, NJ
6.2 Incorporating Speculative Execution into
Scheduling of Control-Flow Intensive Behavioral
Descriptions
Ganesh Lakshminarayana - Princeton Univ.,
Princeton, NJ
Anand Raghunathan - NEC USA, C&C
Research Labs., Princeton, NJ
Niraj K. Jha - Princeton Univ., Princeton, NJ
6.3S The DT-Model: High-Level Synthesis Using
Data Transfers
Shantanu Tarafdar, Miriam Leeser Northeastern Univ., Boston, MA
6.4S Rate Optimal VLSI Design from Data
Flow Graph
Moonwook Oh, Soonhoi Ha - Seoul National
Univ., Seoul, Korea
16
SESSION 7
7.1 Embedded Tutorial: Logic Synthesis for
Ultra Deep Sub-Micron (UDSM)
Robert K. Brayton - Univ. of California,
Berkeley, CA
7.2 A DSM Design Flow: Putting
Floorplanning, Technology-Mapping, and GatePlacement Together
Amir H. Salek, Jinan Lou, Massoud Pedram Univ. of Southern California, Los Angeles, CA
t
uesday, june 16
SESSION 8
Room: 305
SESSION 9
Room: 304
ENVIRONMENT FOR
COLLABORATIVE
DESIGN
NEW METHODS IN
FUNCTIONAL
VERIFICATION
Chair: Takahide Inoue - Sony Corp.,
Milpitas, CA
Organizers: Richard Smith, Takahide
Inoue
Chair: Rajesh K. Gupta - Univ. of
California, Irvine, CA
Organizers: Vivek Tiwari, Kenji Yoshida
The design of large systems-on-a-chip
introduces some new problems with
respect to the management of very
diversified design teams including system
designers, IP providers and semiconductor
chip designer. These designers want to use
the best in their class tools but also need to
collaborate to make the overall design real.
This session introduces some new ideas
for very large scale collaborative design
environments, H/S codesign and tool
encapsulation.
8.1 Framework Encapsulations: A
New Approach to CAD Tool
Interoperability
Peter Sutton - Queensland Univ. of
Tech., Brisbane, Australia
Stephen W. Director - Univ. of Michigan,
Ann Arbor, MI
8.2 A Geographically Distributed
Framework for Embedded System
Design and Validation
Ken Hines, Gaetano Borriello - Univ. of
8.3 Weld - An Environment for WebBased Electronic Design
Francis L. Chan, Mark D. Spiller, A.
Richard Newton - Univ. of California,
Berkeley, CA
Design verification is one of the most
complex and time consuming components
of the design process. Functional
verification continues to be the most
popular method for verifying designs early
and often. The papers in this session
present methods to improve the speed and
effectiveness of functional verification.
§ 9.1 OCCOM: Efficient Computation
of Observability-Based Code Coverage
Metrics for Functional Verification
Farzan Fallah, Srinivas Devadas Massachusetts Inst. of Tech.,
Cambridge, MA
Kurt Keutzer - Univ. of California,
Berkeley, CA
9.2 User Defined Coverage - A Tool
Supported Methodology for Design
Verification
Raanan Grinwald, Eran Harel, Michael
Orgad, Shmuel Ur, Avi Ziv - IBM Corp.,
Haifa, Israel
9.3S Enhanced Visibility and
Performance in Functional Verification
by Reconstruction
Joshua Marantz - IKOS Systems, Inc.,
Waltham, MA
9.4S Virtual Chip: Making Functional
Models Work on Real Target Systems
Namseung Kim, Hoon Choi, Seungjong
Lee, Seungwang Lee, In-Cheol Park,
Chong-Min Kyung - KAIST, Taejon,
Korea
SESSION 10
Room: 103
PANEL:
HARDWARE/SOFTWAR
E CO-DESIGN – THE
NEXT EMBEDDED
SYSTEM DESIGN
CHALLENGE
Chair: Pete Heller - Collett International,
Inc., Santa Clara, CA
Organizers: Diane Orr, Kristin Hehir Tsantes & Associates,
Campbell, CA
Issues, challenges, tradeoffs and solutions
being employed in the design of systems
with increasing amounts of functionality
implemented in software will be explored in
this panel. Perspectives from system
designers and tool vendors in hardware and
software development domains will be
shared. This panel's goal is to identify
challenges embedded designers face and
determine if design tools offered provide
true hardware/software co-design solutions.
Without an interface to synthesis, can
hardware/software co-design provide
meaningful value? Can automatic hardware
and software partitioning tools replace
humans? Who is responsible for
hardware/software co-design? System
architects? Hardware designers? Software
designers? Can tools optimize system
functionality and performance tradeoff s
between
hardware
and
software
implementation? Are commercial real time
operating systems impacting hardware and
software tradeoff decisions?
PANEL MEMBERS:
Guido Arnout - CoWare, Inc., Santa
Clara, CA
John Fogelin - Wind River Systems,
Alameda, CA
Vess L. Johnson - Omniview Design,
Inc., Pittsburgh, PA
Mark Medovich - Sun Microsystems,
Palo Alto, CA
Fred Rose - Honeywell, Inc.,
Minneapolis, MN
James A. Rowson - Alta Group of
Cadence Design Systems, Inc.,
Sunnyvale, CA
17
w
ednesday, june 17
SESSION 11
Room: 102
SYSTEM-LEVEL POWER
OPTIMIZATION
Chair: Vivek Tiwari - Intel Corp., Santa Clara, CA
Organizers: Rajesh K. Gupta, Sunil D. Sherlekar
Power optimization at the system level must address
a diverse array of issues ranging from choice of
system hardware and software components,
memory system design and appropriate policies for
use of system resources. Papers in this session
report on the progress in methodologies, frameworks
and policy optimization for power reduction at the
system level.
8:30
to
10:00
§ - denotes
best paper
18
11.1 Power Optimization of Variable Voltage
Core-Based Systems
Inki Hong, Darko Kirovski, Gang Qu, Miodrag M.
Potkonjak, Mani Srivastava - Univ. of California,
Los Angeles, CA
11.2 Policy Optimization for Dynamic Power
Management
Giuseppe Paleologo, Luca Benini - Stanford
Univ., Stanford, CA
Alessandro Bogliolo - Univ. of Bologna,
Bologna, Italy
Giovanni De Micheli - Stanford Univ., Stanford, CA
11.3 A Framework for Estimating and
Minimizing Energy Dissipation of Embedded
HW/SW Systems
Yanbing Li - Princeton Univ., Princeton, NJ
Joerg Henkel - NEC USA, C&C Research Labs.,
Princeton, NJ
SESSION 12
Room: 301
BOOLEAN METHODS
Chair: Fabio Somenzi - Univ. of Colorado,
Boulder, CO
Organizers: Sharad Malik, Randal E. Bryant
This session examines new an alysis techniques for
Boolean functions. The first paper presents an
innovative instance-specific hardware acceleration
for SAT formulas using configurable logic. The
second paper presents a technique for exact
minimization of BDD representations of functions.
Finally, the last paper presents a canonical NPN
representation of functions for the use in
technology mapping.
12.1 Using Reconfigurable Computing
Techniques to Accelerate Problems in the CAD
Domain: A Case Study with Boolean
Satisfiability
Peixin Zhong - Princeton Univ., Princeton, NJ
Pranav Ashar - NEC USA, C&C Research Labs.,
Princeton, NJ
Sharad Malik, Margaret Martonosi - Princeton
Univ., Princeton, NJ
12.2 Fast Exact Minimization of BDDs
Rolf Drechsler, Nicole Drechsler, Wolfgang
Günther - Univ. of Freiburg, Freiburg, Germany
12.3 Boolean Matching for Large Libraries
Uwe Hinsberger, Reiner Kolla - Univ.
Wuerzburg, Wuerzburg, Germany
w
ednesday, june 17
SESSION 13
Room: 305
EXTRACTION AND
MODELING FOR
INTERCONNECT
Chair: Hidetoshi Onodera - Kyoto Univ.,
Kyoto, Japan
Organizers: Hidetoshi Onodera,
Alan Mantooth
Fast and accurate analysis of interconnect is
crucial for the performance estimation of
deep sub-micron circuits. This session
discusses methods for interconnect parasitic
extraction using integral equation approaches.
The first paper presents 3-D capacitance
extraction based on a hierarchical algorithm for
the N-body problem. The second paper
proposes a BEM formulation for generating
macromodels used in 2-D hierarchical
capacitance extraction. The last paper
describes a computationally efficient method
for parasitic extraction using a multi layered
3-D Green’s function.
§ 13.1 A Fast Hierarchical Algorithm for
3-D Capacitance Extraction
Weiping Shi, Jianguo Liu, Naveen Kakani Univ. of North Texas, Denton, TX
Tiejun Yu - Univ. of North Carolina,
Charlotte, NC
13.2 Boundary Element Method
Macromodels for 2-D Hierarchical
Capacitance Extraction
E. Aykut Dengi - Motorola, Inc., Austin, T X
Ronald A. Rohrer - Intersouth Partners,
Research Triangle Park, NC
13.3 Efficient Three-Dimensional
Extraction Based on Static and Full-Wave
Layered Green’s Functions
Jinsong Zhao - Univ. of California, Santa
Cruz, CA
Sharad Kapur, David E. Long - Bell Labs.,
Lucent Tech., Murray Hill, NJ
Wayne W.M. Dai - Univ. of California,
Santa Cruz, CA
SESSION 14
Room: 304
PROCESSOR DESIGN
AND SIMULATION
Chair: Randolph E. Harr - Synopsys,
Inc., Mountain View, CA
Organizers: Anantha Chandrakasan,
Randolph E. Harr
Embedded and single-chip processors are
the core element for all new computing
platforms. Unique design problems inherent
to these processors are finally emerging.
This session covers some recent tool and
methodology developments applied to the
design of DSPs and microprocessors.
14.1 Robust Elmore Delay Models
Suitable for Full Chip Timing
Verification of a 600 MHz CMOS
Microprocessor
Nevine Nassif - Digital Equipment
Corp., Hudson, MA
Madhav P. Desai - Indian Inst. of Tech,
Powai, Mumbai, India
Dale H. Hall - Digital Equipment Corp.,
Hudson, MA
14.2 A Top-Down Design Environment
for Developing Pipelined Datapaths
Robert M. McGraw - RAM Labs.,
Encinitas, CA
Robert H. Klenke, James H. Aylor Univ. of Virginia, Charlottesville, VA
14.3S Validation of an Architectural
Level Power Analysis Technique
Rita Yu Chen, Robert M. Owens, Mary
Jane Irwin - Penn State Univ., University
Park, PA
Raminder S. Bajwa - Hitachi America
Ltd., San Jose, CA
14.4S Design Methodology of a 200MHz
Superscalar Microprocessor: SH-4
Toshihiro Hattori, Yusuke Nitta,
Mitsuho Seki, Susumu Narita, Kunio
Uchiyama, Tsuyoshi Takahashi, Ryuichi
Satomura - Hitachi Ltd., Tokyo, Japan
SESSION 15
Room: 103
PANEL: HOW MUCH
ANALOG DOES A
DESIGNER NEED TO
KNOW FOR
SUCCESSFUL MIXEDSIGNAL DESIGN?
Chair: Stephan Ohr - EE Times,
Westfield, NJ
Organizers: Georgia Marszalek Marketing Consultant,
Foster City, CA
Nanette Collins Consultant, Boston, MA
With today’s mixed-signal designs, there
has to be a team of analog and digital
designers working on distinct parts of the
projects – analog designers need to train
themselves as digital designers, or digital
designers need to train themselves as
analog designers.
For mixed-signal
design, do analog designers know enough
to control voltages and current in digital
CMOS or is a different orientation required?
Do digital designers know enough about
what an analog circuit is supposed to do to
replicate its functions in digital CMOS? Are
either analog or digital tool sets adequate
for mixed-signal design? Is something
different required? Can analog designers
master high-level design languages? And
will this help or hinder the design process?
PANEL MEMBERS:
Bob Dobkin - Linear Technology,
Milpitas, CA
Felicia James - Texas Instruments,
Dallas, TX
Ken Kundert - Cadence Design
Lavi Lev - Silicon Graphics, Inc.,
Mountain View, CA
Maqsoodul Mannan - DSM
Technologies, San Jose, CA
Rob A. Rutenbar - Carnegie Mellon
Univ., Pittsburgh, PA
19
w
ednesday, june 17
SESSION 16
Room: 102
PERFORMANCE MODELING
AND CHARACTERIZATION
FOR EMBEDDED SYSTEMS
Chair: Sunil D. Sherlekar - Silicon Automation
Systems, Bangalore, India
Organizers: Sunil D. Sherlekar, Rajesh K. Gupta
10:30
to
12:00
§ - denotes
best paper
20
Design of embedded systems, particularly in timeconstrained signal processing applications, requires
accurate performance characterization. The first two
papers present probabilistic characterization of
performance and its use in signal processing
applications. The last paper addresses the problem
of deterministic detailed performance constraints
from interface specifications using a deterministic
method.
16.1 Hierarchical Algorithms for Assessing
Probabilistic Constraints on System
Performance
Gustavo De Veciana, Margarida Jacome, JianHuei Guo - Univ. of Texas, Austin, TX
16.2 A Tool for Performance Estimation of
Networked Embedded Systems
Asawaree Kalavade, Pratyush Moghe - Lucent
Tech., Bell Labs., Holmdel, NJ
16.3 Rate Derivation and its Applications to
Reactive, Real-Time Embedded Systems
Ali Dasdan - Univ. of Illinois-Champaign,
Urbana, IL
Dinesh Ramanathan - Synopsys, Inc., Mountain
View, CA
Rajesh K. Gupta - Univ. of California, Irvine, CA
SESSION 17
Room: 301
ADVANCES IN PLACEMENT
AND PARTITIONING
Chair: Antun Domic - Synopsys, Inc., Mountain
View, CA
Organizers: Patrick Groeneveld, Andrew B.
Kahng
This session opens with two powerful advances in
the quadratic placement approach. Next, the novel
application of placement with incomplete netlist
information is introduced. The last two papers
address new multi-way partitioning and clustering
formulations.
§ 17.1 Generic Global Placement and
Floorplanning
Hans Eisenmann, Frank M. Johannes Technical Univ. of Munich, Munich, Germany
17.2S Congestion Driven Quadratic Placement
Phiroze N. Parakh, Richard B. Brown, Karem A.
Sakallah - Univ. of Michigan, Ann Arbor, MI
17.3S Potential_NRG: Placement with
Incomplete Data
Maogang Wang, Prithviraj Banerjee, Majid
Sarrafzadeh - Northwestern Univ., Evanston, IL
17.4S Performance-Driven Multi-FPGA
Partitioning Using Functional Clustering and
Replication
Wen-Jong Fang, Allen C.-H. Wu - Tsing Hua
Univ., Hsinchu, Taiwan ROC
17.5S Multi-Pad Power/Ground Network Design
for Uniform Distribution of Ground Bounce
Jaewon Oh, Massoud Pedram - Univ. of
Southern California, Los Angeles, CA
w
ednesday, june 17
SESSION 18
Room: 305
PARASITIC DEVICE
EXTRACTION AND
INTERCONNECT
MODELING
Chair: David D. Ling - IBM Corp.,
Yorktown Heights, NY
Organizers: Alan Mantooth, Hidetoshi
Onodera
This session includes papers focused on
layout extraction. The first paper deals with
the extraction and verification of CMOS I/O
Circuits, which involves the extraction of
SCR’s, parasitic bipolar transistors, etc. The
next two papers deal with interconnect
extraction and modeling. One involves
efficient reduced order models for 3-D
interconnects. The other involves extraction
of frequency dependent behavior for timing
analysis.
18.1 Layout Extraction and Verification
Methodology for CMOS I/O Circuits
Tong Li, Sung-Mo Kang - Univ. of Illinois,
Urbana, IL
18.2 A Mixed Nodal-Mesh Formulation
for Efficient Extraction and Passive
Reduced-Order Modeling of 3D
Interconnects
Nuno Marques - INESC/Cadence
European Labs., Lisboa, Portugal
Mattan Kamon, Jacob K. White Massachusetts Inst. of Tech.,
Cambridge, MA
L. Miguel Silveira - INESC/Cadence
European Labs., Lisboa, Portugal
18.3 Layout Based Frequency
Dependent Inductance and Resistance
Extraction for On-Chip Interconnect
Timing Analysis
Byron Krauter, Sharad Mehrotra - IBM
Corp., Austin, TX
SESSION 19
Room: 304
DESIGN OPTIMIZATION
FOR DSP
Chair: James A. Rowson - Alta Group
of Cadence Design Systems,
Inc., Sunnyvale, CA
Organizers: Anders Forsen, Ivo Bolsens
Computationally intensive DSP problems
can be optimized early in the design cycle.
These papers show their approaches:
interactive optimization at the behavioral
level, a methodology based on C++, and an
architectural approach for image processing.
19.1 A Methodology for Guided
Behavioral-Level Optimization
Lisa Marie Guerra - Rockwell
Semiconductor Systems, Newport
Beach, CA
Miodrag M. Potkonjak - Univ. of
California, Los Angeles, CA
Jan M. Rabaey - Univ. of California,
Berkeley, CA
19.2 A Programming Environment for
the Design of Complex High
Speed ASICs
Patrick R. Schaumont, Serge
Vernalde, Luc Rijnders, Marc Engels,
Ivo Bolsens - IMEC, Leuven, Belgium
19.3 Media Architecture: General
Purpose vs. Multiple Application
Specific Programmable Processor
Chunho Lee, Johnson S. Kin, Miodrag
M. Potkonjak, William H. MangioneSmith - Univ. of California,
Los Angeles, CA
SESSION 20
Room: 103
PANEL: USER
EXPERIENCE WITH
HIGH LEVEL FORMAL
VERIFICATION
Chair: Gerry Musgrave - Brunel Univ.,
Uxbridge, UK
Organizers: Gerry Musgrave - Brunel
Univ., Uxbridge, UK
Randal E. Bryant Carnegie Mellon Univ.,
Pittsburgh, PA
Formal verification methods are beginning to
be used by leading edge industries. How
effective are they, how easy it is to embed
them in the design flow and what are the
future requirements are questions the
industry wishes to have answered. The
panel will attempt to answer these and other
aspects of model checking or parameter
validation techniques by sharing their
experience in using a variety of tools. The
emphasis will be on what has been achieved
and how design teams cope with changes in
design flow. They will also describe how they
have been able to transform from using the
tools as a post design checker to be a
proactive design aid in achieving quality
designs in a shorter time.
PANEL MEMBERS:
Pierre Aulagnier - Cisco Systems,
San Jose, CA
Fumiyasu Hirose - Fujitsu Labs., Ltd.,
Kawasaki, Japan
Michael Payer - Siemens AG, Munich,
Germany
Alan Silbert - Nortel, Ottawa,
ON, Canada
John Van Tassel - Texas Instruments,
Inc., Dallas, TX
21
w
ednesday, june 17
SESSION 21
Room: 102
BRIDGING THE GAP
BETWEEN SIMULATION AND
FORMAL VERIFICATION
Chair: Andreas Kuehlmann - IBM Corp.,
Organizers: Randal E. Bryant, Sharad Malik
2:00
to
4:00
Neither of the two extremes of design validation:
endless simulation runs over ad hoc tests sets or
rigorous mathematical proofs of correctness,
represent cost effective methods to ensure quality
designs. Instead, it is better to find intermediate
approaches combining good engineering practice
with the mathematical reasoning capabilities of
formal verification. The result can be to either run
simulations that will achieve high coverage or to use
formal verification tools to analyze critical aspects of
the behavior over abstracted system models. This
session, consisting of two embedded tutorials,
provides an overview of the state of the art and the
future opportunities for both of these intermediate
approaches.
21.1 Embedded Tutorial: What’s Between
Simulation and Formal Verification?
David L. Dill - Stanford Univ., Stanford, CA
21.2 Embedded Tutorial: Targeted Formal
Verification
Ken McMillian - Cadence Design Systems, Inc.,
Berkeley, CA
SESSION 22
Room: 301
LOGIC OPTIMIZATION
Chair: Albert Wang - Synopsys, Inc., Mountain
View, CA
Organizers: Jason Cong, TingTing Hwang
This session presents recent advances on various
aspects of logic optimization. The first paper presents
a novel method for optimal mapping combined with
forward retiming to guarantee efficient initial state
computation. The second paper presents on-the-fly
technology mapping during logic optimization. The
third paper presents new techniques for efficient
Boolean division. The fourth paper extends efficient
delay-optimal mapping techniques for FPGAs to
library-based designs. The last paper presents an
e fficient solution for fanout optimization.
22.1 Optimal FPGA Mapping and Retiming with
Efficient Initial State Computation
Jason Cong, Chang Wu - Univ. of California,
Los Angeles, CA
22.2 M32: A Constructive Multilevel Logic
Synthesis System
Karem Sakallah, Victor N. Kravets - Univ. of
Michigan, Ann Arbor, MI
22.3 Efficient Boolean Division and
Substitution
Shih-Chieh Chang - National Chung-Cheng
Univ., Chiayi, Taiwan ROC
David I. Cheng - Ultima Interconnect Tech.,
Sunnyvale, CA
22.4S Delay-Optimal Technology Mapping by
DAG Covering
Yuji Kukimoto, Robert K. Brayton - Univ. of
Prashant Sawkar - Intel Corp., Hillsboro, OR
22.5S A Fast Fanout Optimization Algorithm for
Near-Continuous Buffer Libraries
David S. Kung - IBM Corp., Yorktown Heights, NY
22
w
ednesday, june 17
SESSION 23
Room: 305
ROUTING FOR
PERFORMANCE AND
CROSSTALK
Chair: Sachin S. Sapatnekar - Univ. of
Minnesota, Minneapolis, MN
Organizers: Patrick Groenveld,
Andrew B. Kahng
Routing today is more than making all
connections DRC correct in minimum area. In
addition a sub-micron router must maximize
performance and minimize undesired effects
such as crosstalk. This session is dedicated
to new methods for routing that optimize for
these new concerns.
23.1 Performance Driven Multi-Layer
General Area Routing for PCB/MCM
Designs
Jason Cong, Patrick H. Madden - Univ.
of California, Los Angeles, CA
23.2 Buffer Insertion for Noise and Delay
Optimization
Charles J. Alpert, Anirudh Devgan,
Stephen T. Quay - IBM Corp., Austin, TX
23.3 Table-Lookup Methods for Improved
Performance-Driven Routing
John Lillis - Univ. of Illinois, Chicago, IL
Premal Buch - Magma Design
Automation, Inc., Mountain View, CA
23.4S Global Routing with Crosstalk
Constraints
Hai Zhou, D.F. Wong - Univ. of Texas,
Austin, TX
23.5S Timing and Crosstalk Driven Area
Routing
Hsiao-Ping Tseng - Univ. of Washington,
Seattle, WA
Louis Scheffer - Cadence Design
Carl Sechen - Univ. of Washington,
Seattle, WA
SESSION 24
Room: 304
PRACTICAL OPTIMIZATION
METHODOLOGIES FOR
HIGH PERFORMANCE
DESIGN
Chair: Vivek Tiwari - Intel Corp., Santa
Clara, CA
Organizers: Vivek Tiwari, Kenji Yoshida
The push for high performance design
continues to stress the capabilities of
conventional tools. This motivates the
development
of
innovative
design
methodologies. The first paper describes a
unified methodology for process and circuit
optimization. The other papers present
practical solutions for the problems of timing
improvement of std cell circuits, repeater
insertion and datapath synthesis.
24.1 Process/Multi-Circuit Optimization
Arun N. Lokanathan, Jay B. Brockman Univ. of Notre Dame, Notre Dame, IN
24.2S Migration: A New Technique to
Improve Synthesized Designs Through
Incremental Customization
Rajendran V. Panda, Abhijit
Dharchoudhury - Motorola, Inc., Austin, T X
Tim Edwards, Joe Norton, David T.
Blaauw - Motorola, Inc., Austin, TX
24.3S A Practical Repeater Insertion
Method Using Elmore Delay in High
Speed VLSI Circuits
Julian Culetu, Chaim Amir, John
MacDonald - Sun Microsystems, Inc.,
SESSION 25
Room: 103
RF IC DESIGN
METHODOLOGY
Chair: Mojy C. Chian - Harris
Semiconductor, Melbourne, FL
Organizers: Bryan D.Ackland,
Mojy C. Chian
RF design has long been considered a black
art. Historically design tools have been
unable to provide an integrated environment
for RF IC design. This session describes
specific constraints and challenges faced by
RF IC designers and CAD tool developers,
including the strong coupling between signal
integrity and design.
25.1 Embedded Tutorial: RF IC Design
Challenges
Behzad Razavi - Univ. of California,
Los Angeles, CA
25.2 Tools and Methodology for RF IC
Design
Alfred E. Dunlop, Alper Demir, Peter
Feldmann, Sharad Kapur, David E.
Long, Robert C. Melville, Jaijeet S.
Roychowdhury - Bell Labs., Lucent
Tech., Murray Hill, NJ
25.3 Electromagnetic Modeling and
Signal Integrity Simulation of Power/
Ground Networks in High Speed Digital
Packages & Printed Circuit Boards
Frank Y. Yuan - Viewlogic Systems
Group, Inc., Camarillo, CA
Palo Alto, CA
24.4 Practical Experiences with
Standard-Cell Based Datapath Design
Tools — Do We Really Need Regular
Layouts?
Paolo Ienne, Alexander Griessing Siemens AG, Munich, Germany
24.5 A Statistical Performance
Simulation Methodology for VLSI Circuits
Michael Orshansky, James C. Chen,
Chenming Hu - Univ. of California,
Berkeley, CA
23
w
ednesday, june 17
SESSION 26
Room: 102
24
Room: 301
THEORY AND PRACTICE IN
HIGH LEVEL SYNTHESIS
BDD APPROXIMATION
TECHNIQUES
Chair: Steve Tjiang - Synopsys, Inc., Mountain
View, CA
Organizers: David Ku, Timothy Kam
Chair: Andreas Kuehlmann - IBM Corp.,
Organizers: Andreas Kuehlmann, Kunle
Olukotun
This session concentrates on advances in
fundamental algorithms and applications for high
level synthesis. The first paper presents
improvements in graph coloring using a combination
of new techniques. The second paper presents a
technique of transforming arithmetic circuits into
ones using carry-save-adders. The third paper
describes a behavioral synthesis system that
optimizes for power and area.
4:30
to
6:00
SESSION 27
26.1 Efficient Coloring of a Large Spectrum
of Graphs
Darko Kirovski, Miodrag M. Potkonjak - Univ. of
26.2 Arithmetic Optimization Using
Carry-Save-Adders
Taewhan Kim - Synopsys, Inc.,
Mountain View, CA
William Jao - Aimfast Corp., Sunnyvale, CA
Steve Tjiang - Synopsys, Inc., Mountain View, CA
26.3 Synthesis of Power-Optimized and AreaOptimized Circuits from Hierarchical Behavioral
Descriptions
Ganesh Lakshminarayana, Niraj K. Jha Princeton Univ., Princeton, NJ
This session presents three papers that use
approximation and decomposition of BDD’s to
enhance the current state of the art in reachability
analysis.
27.1 Approximation and Decomposition of
Binary Decision Diagrams
Kavita Ravi - Univ. of Colorado, Boulder, CO
Kenneth L. McMillan - Cadence Design Systems,
Inc., Berkeley, CA
Thomas R. Shiple - Synopsys, Inc., Mountain
View, CA
Fabio Somenzi - Univ. of Colorado, Boulder, CO
27.2 Approximate Reachability with BDDs
Using Overlapping Projections
Shankar G. Govindaraju, David L. Dill Stanford Univ., Stanford, CA
Alan J. Hu - Univ. of British Columbia,
Vancouver, BC, Canada
Mark A. Horowitz - Stanford Univ., Stanford, CA
27.3 Incremental CTL Model Checking Using
BDD Subsetting
Abelardo Pardo - Mentor Graphics Corp.,
Billerica, MA
Gary D. Hachtel - Univ. of Colorado, Boulder, CO
w
ednesday, june 17
SESSION 28
Room: 305
INTERCONNECT
MODELING AND TIMING
SIMULATION
Chair: Andrew T. Yang - Univ. of
Organizers: Andrew T. Yang, Hidetoshi
Onodera
Non-linear electrical-level circuit and timing
simulation play an important role in the
design and analysis of large scale ICs. The
first three papers in this session address a
variety of interconnect modeling techniques
which can be used in circuit simulation and
timing analysis. The last paper presents a
method for computing adjoint transient
sensitivity in an event-driven PWL simulator.
28.1 Primo: Probability Interpretation of
Moments for Delay Calculation
Rony Kay, Lawrence T. Pileggi Carnegie Mellon Univ., Pittsburgh, PA
28.2S FTD: An Exact Frequency to Time
Domain Conversion for Reduced Order
RLC Interconnect Models
Ying Liu, Lawrence T. Pileggi, Andrzej J.
Strojwas - Carnegie Mellon Univ.,
Pittsburgh, PA
28.3S Extending Moment Computation
to 2-Port Circuit Representations
Fang-Jou Liu, Chung-Kuan Cheng - Univ.
of California, San Diego, La Jolla, CA
28.4 Adjoint Transient Sensitivity
Computation in Piecewise Linear
Simulation
Tuyen V. Nguyen, Anirudh Devgan - IBM
Corp., Austin, TX
Ognen J. Nastov - Massachusetts Inst. of
Tech., Cambridge, MA
SESSION 29
Room: 304
LOW POWER DESIGN
USING MULTIPLE
THRESHOLDS AND
SUPPLIES
Chair: Bryan D. Ackland - Bell Labs.,
Lucent Tech., Holmdel, NJ
Organizers: Anantha Chandrakasan,
Bryan D. Ackland
Techniques for optimally assigning supply
voltage and selecting threshold voltages so
as to provide desired tradeoff between
performance, active power and standby
power dissipation are presented.
29.1 Design Methodology of Ultra LowPower MPEG4 Codec Core Exploiting
Voltage Scaling Techniques
Kimiyoshi Usami, Mutsunori Igarashi,
Takashi Ishikawa, Masahiro Kanazawa,
Masafumi Takahashi, Mototsugu
Hamada, Hideho Arakida, Toshihiro
Terazawa, Tadahiro Kuroda - Toshiba
Corp., Kawasaki, Japan
29.2 Design and Optimization of Low
Voltage High Performance Dual
Threshold CMOS Circuits
Liqiong Wei, Zhanping Chen, Kaushik
Roy, Vivek De - Purdue Univ., West
Lafayette, IN
29.3 MTCMOS Hierarchical Sizing
Based on Mutual Exclusive Discharge
Patterns
James Kao, Siva Narendra, Anantha
Chandrakasan - Massachusetts Inst. of
SESSION 30
Room: 103
PANEL: TECHNICAL
CHALLENGES OF IP
AND SYSTEM-ON-CHIP:
THE ASIC VENDOR
PERSPECTIVE
Chair: Richard Newton - Univ. of
Organizers: Andrew Graham - Si2,
Austin, TX
Andrew B. Kahng - Univ. of
The demand for system-on-chip solutions is
creating
vast
changes
in
reuse
methodology and EDA technology.
Traditional roles of foundries, ASIC
suppliers, and EDA vendors are blurring.
For the end customer, the situation presents
correspondingly
greater
risks
and
opportunities. This panel brings together
today's leading providers of embedded
silicon IP solutions.
The panelists will
discuss practical expectations for systemon-chip design, and the key pieces of
industry infrastructure that must be
addressed to realize the full potential of
system-on-chip. These include: customer
expectations, EDA technology implications;
standards; legal barriers and associated
risks facing ASIC suppliers and EDA
vendors; challenges of incorporating 3rdparty IP; and practical reuse methodologies.
PANEL MEMBERS:
Bruce Beers - IBM Corp., Essex
Junction, VT
Jeffery Hilbert - LSI Logic, Milpitas, CA
Michael Jackson - Motorola, Inc.,
Austin, TX
Anand Naidu - Sand Microelectronics,
Santa Clara, CA
Bob Payne - VLSI Technology,
San Jose, CA
Mark Stibitz - Lucent Technologies,
Allentown, PA
Hitoshi Yoshizawa - NEC Corp.,
Kawasaki, Japan
25
t
hursday, june 18
SESSION 31
Room: 102
SOFTWARE SYNTHESIS AND
RETARGETABLE
COMPILATION
Chair: Kurt Keutzer - Univ. of California,
Berkeley, CA
Organizers: Luciano Lavagno, Sharad Malik
8:30
to
10:00
§ - denotes
26
This session explores aggressive techniques for
meeting tight space and time constraints for
embedded software. These are applicable at
different levels of the design process. At the high
level, these include C-code synthesis with quasistatic scheduling, as well as don’t care based
optimization. At compile time, the next paper
explores integrated instruction selection, resource
allocation and data routing for parallel architectures.
Finally, the last paper examines how compressed
code can be used with runtime decompression to
achieve code size reduction.
31.1S Software Synthesis of Process-Based
Concurrent Programs
Bill Lin - Univ. of California, San Diego,
La Jolla, CA
31.2S Don’t Care-Based BDD Minimization for
Embedded Software
Youpyo Hong, Peter Beerel - Univ. of Southern
Luciano Lavagno - Cadence Design Systems,
Inc., Berkeley, CA
Ellen M. Sentovich - Cadence Berkeley Labs.,
Berkeley, CA
31.3 Instruction Selection, Resource
Allocation, and Scheduling in the AVIV
Retargetable Code Generator
Silvina Hanono, Srinivas Devadas Massachusetts Inst. of Tech., Cambridge, MA
31.4 Code Compression for Embedded Systems
Haris Lekatsas, Wayne Wolf - Princeton Univ.,
Princeton, NJ
SESSION 32
Room: 301
FORMAL METHODS IN
FUNCTIONAL VERIFICATION
Chair: Kunle Olukotun - Stanford Univ.,
Stanford, CA
Organizers: Kunle Olukotun, Andreas
Kuehlmann
This session explores techniques for functional-level
verification. The first paper adds support for bitvector arithmetic to a formal verification environment
that combines theorem proving and model checking.
The second paper presents a new technique for
generating functional test vectors. The last two
papers demonstrate the industrial use of symbolic
trajectory evaluation.
§ 32.1 A Decision Procedure for Bit-Vector
Arithmetic
Clark W. Barrett, David L. Dill, Jeremy R. Levitt Stanford Univ., Stanford, CA
32.2 Functional Vector Generation for HDL
Models Using Linear Programming and 3Satisfiability
Farzan Fallah, Srinivas Devadas Massachusetts Inst. of Tech., Cambridge, MA
Kurt Keutzer - Univ of California, Berkeley, CA
32.3S Automatic Generation of Assertions for
Formal Verification of PowerPC Microprocessor
Arrays Using Symbolic Trajectory Evaluation
Li-C. Wang, Magdy S. Abadir, Nari
Krishnamurthy - Motorola, Inc., Austin, TX
32.4S Combining Theorem Proving and
Trajectory Evaluation in an Industrial
Environment
Mark D. Aagaard, Robert B. Jones, Carl-Johan
H. Seger - Intel Corp., Hillsboro, OR
t
hursday, june 18
SESSION 33
Room: 305
CORE TEST AND BIST
Chair: Janusz Rajski - Mentor Graphics
Corp., Wilsonville, OR
Organizers: Yervant Zorian, Janusz Rajski
This session addresses test issues at higherlevels of design abstraction. The papers
introduce new methodologies for testing of
core-based systems and optimized BIST
schemes inserted at register transfer and
behavioral levels.
33.1 A Fast and Low Cost Testing
Technique for Core-Based System-on-a-Chip
Indradeep Ghosh - Princeton Univ.,
Princeton, NJ
Sujit Dey - Univ. of California, San Diego,
La Jolla, CA
Niraj K. Jha - Princeton Univ., Princeton, NJ
33.2 Introducing Redundant
Computations in a Behavior for Reducing
BIST Resources
Ishwardutt Parulkar - Sun Microsystems,
Sunnyvale, CA
Sandeep K. Gupta, Melvin A. Breuer Univ. of Southern California,
Los Angeles, CA
33.3 A BIST Scheme for RTL ControllerData Paths Based on Symbolic
Testability Analysis
Indradeep Ghosh, Niraj K. Jha Princeton Univ., Princeton, NJ
Sudipta Bhawmik - Bell Labs., Lucent
Tech., Princeton, NJ
SESSION 34
Room: 304
SESSION 35
Room: 103
INTERCONNECT
ANALYSIS AND
RELIABILITY IN DEEP
SUB-MICRON
PANEL: DESIGN
PRODUCTIVITY: HOW
TO MEASURE IT, HOW
TO IMPROVE IT
Chair: Kenji Yoshida - Toshiba Corp.,
Kawasaki, Japan
Organizers: Kenji Yoshida,
David T. Blaauw
Chair: Carlos Dangelo - Semiconductor
Research Corp., San Jose, CA
Organizers: Ronald E. Collett - Collett
International, Inc., Santa
Clara, CA
Andrew B. Kahng - Univ. of
In designing deep sub-micron LSIs, new
issues need to be carefully considered for
high performance and reliability. In this
session, design considerations and
analysis of inductance and electromigration
of deep sub-micron interconnect will be
discussed.
34.1 Figures of Merit to Characterize
the Importance of On-Chip Inductance
Yehea I. Ismail, Eby G. Friedman Univ. of Rochester, Rochester, NY
Jose L. Neves - IBM Corp., East
Fishkill, NY
34.2 Layout Techniques for Minimizing
On-Chip Interconnect Self Inductance
Yehia Massoud - Massachusetts Inst.
of Tech., Cambridge, MA
Steve Majors - Rockwell Semiconductor
Systems, Austin, TX
Tareq Bustami - Motorola Inc., Austin, TX
Jacob K. White - Massachusetts Inst. of
34.3 A Practical Approach to Static
Signal Electromigration Analysis
Nagaraj NS - Texas Instruments Inc.,
Dallas, TX
Frank Cano, Haldun Haznedar, Duane
Young - Texas Instruments Inc.,
Stafford, TX
This panel will discuss factors that have the
greatest impact on design productivity and
time-to-market. Panelists will review the
practices and strategies that they use today
to improve productivity and time-to-market
(impact of EDA tools, library strategy,
design team composition and dynamics,
etc.), as well as the results of these
practices and strategies. The panel will also
discuss and present approaches to
measuring productivity, from both a
quantitative and qualitative perspective.
Questions that will be addressed include the
following. (1) What kind of measurements,
if any, are being used today? (2) What have
been the results? (3) Are they useful? (4) Is
there a consensus about the kinds of
measurements that should be taken? (5)
What kind of metrics are needed?
PANEL MEMBERS:
Andy Bechtolsheim - Cisco Systems,
San Jose, CA
Ronald E. Collett - Collett International,
Santa Clara, CA
Jeff Hilbert - LSI Logic, Milpitas, CA
Chris Malachowsky - NVidia Corp.,
Sunnyvale, CA
Leif Rosqvist - Cadence Spectrum
Design, San Jose, CA
Jim Thomas - Motorola M-Core
Technology Ctr., Austin, TX
27
t
hursday, june 18
SESSION 36
Room: 102
Thursday
Keynote
Address
1:00 to 1:45
GATEWAY
BALLROOM
no badge
required to
attend the
Thursday
Keynote
§ - denotes
28
Room: 301
HIERARCHICAL FUNCTIONAL
TIMING ANALYSIS
NEW TECHNIQUES IN STATE
SPACE EXPLORATIONS
Chair: Tom Szymanski - Bell Labs., Lucent
Tech., New Providence, NJ
Organizers: Sharad Malik, Farid N. Najm
Chair: Carl-Johan H. Seger - Intel Corp.,
Hillsboro, OR
Organizers: Andreas Kuehlmann, Kunle
Olukotun
This session examines new techniques in timing
analysis at various levels of abstraction: accurate
modeling for interconnect analysis; hierarchical
modeling and analysis at the gate level; register
transfer level timing estimation and analysis of
system level timing diagrams.
10:30
to
12:00
SESSION 37
36.1 Hierarchical Functional Timing Analysis
Yuji Kukimoto, Robert K. Brayton - Univ. of
36.2 Making Complex Timing Relationships
Readable: Presburger Formula Simplification
Using Don’t Cares
Tod Amon - Southwest Texas State Univ., San
Marcos, TX
Gaetano Borriello - Univ. of Washington, Seattle, WA
Jiwen Liu - Southwest Texas State Univ., San
Marcos, TX
36.3S Delay Estimation of VLSI Circuits from a
High-Level View
Mahadevamurty Nemani, Farid N. Najm - Univ.
of Illinois, Urbana, IL
36.4S TETA: Transistor-Level Engine for Timing
Analysis
Florentin Dartu, Lawrence T. Pileggi - Carnegie
Mellon Univ., Pittsburgh, PA
This session presents four verification approaches
based on state space exploration. The first paper
describes a search scheme to uncover bad
reachable states. The next two papers present
verification methods which are based on classifying
the state space of systems. The last paper describes
a method for test case generation which cause
heavy controller interactions.
37.1 Validation with Guided Search of the
State Space
C. Han Yang, David L. Dill - Stanford Univ.,
Stanford, CA
37.2 Efficient State Classification of Finite
State Markov Chains
Aiguo Xie, Peter A. Beerel - Univ. of Southern
37.3S An Implicit Algorithm for Finding Steady
States and its Application to FSM Verification
Gagan Hasteer - Ambit Design Systems,
San Jose, CA
Anmol Mathur - Silicon Graphics Corp., Mountain
View, CA
Prithviraj Banerjee - Northwestern Univ.,
Evanston, IL
37.4S Hybrid Verification Using Saturated
Simulation
Adnan Aziz - Univ. of Texas, Austin, TX
Thomas R. Shiple, James H. Kukula - Synopsys,
Inc., Mountain View, CA
t
hursday, june 18
SESSION 38
Room: 305
ADVANCED ATPG
TECHNIQUES
Chair: Yervant Zorian - LogicVision, Inc.,
San Jose, CA
Organizers: Yervant Zorian, Janusz Rajski
Advanced techniques developed for automatic
test pattern generation frequently find
applications in design verification. Papers
presented in this session introduce new
efficient techniques to generate input/output
sequences for functional testing, new highperformance method for sequential learning
of implications and a fault simulation-based
method for diagnosing general design errors
in sequential circuits.
38.1 Fast State Verification
Bapiraju Vinnakota, Dechang Sun, Wanli
Jiang - Univ. of Minnesota, Minneapolis, MN
38.2 A Fast Sequential Learning
Technique for Real Circuits with
Application to Enhancing ATPG
Performance
Aiman H. El-Maleh, Mark A. Kassab,
Janusz Rajski - Mentor Graphics Corp.,
Wilsonville, OR
38.3 General Design Error Diagnosis for
Sequential Circuits
Shi-Yu Huang - National Semiconductor
Corp., Santa Clara, CA
Kwang-Ting Cheng - Univ. of California,
Santa Barbara, CA
Kuang-Chien Chen - Verplex Systems,
Inc., Fremont, CA
Juin-Yeu Lu - National Semiconductor
Corp., Santa Clara, CA
SESSION 39
Room: 304
PRACTICAL
EXPERIENCE OF
FUNCTIONAL
VERIFICATION FOR
COMPLEX ICs
Chair: Rajesh Raina - Motorola, Inc.,
Austin, TX
Organizers: David T. Blaauw, Kenji
Yoshida
Functional verification of large ICs is
consuming an increasingly large portion of
the design resource and design time. This
session examines experiences and results
with functional verification methods of two
high-performance microprocessor designs
and a large ASIC design.
§ 39.1 Functional Verification of a
Multiple-Issue, Out-of-Order,
Superscaler Alpha Processor—The DEC
Alpha 21264 CPU Chip
Michael Quinn, Scott Taylor, Darren
Brown, Nathan Dohm, Scot Hildebrandt,
James Huggins, Carl Ramey - Digital
Equipment Corp., Hudson, MA
39.2 Design Reliability - Estimation
Through Statistical Analysis of Bug
Discovery Data
Yossi Malka, Avi Ziv - IBM Corp.,
Haifa, Israel
39.3 Functional Verification of
Large ASICs
Adrian Evans, Allan Silburt, Gary
Vrckovnik, Thane Brown, Mario
Dufresne, Geoffrey Hall, Tung Ho, Ying
Liu - Nortel, Ottawa, ON, Canada
SESSION 40
Room: 103
PANEL: THE EDA
STARTUP EXPERIENCE:
THE FIRST PRODUCT
Chair: Erach Desai - SoundView
F i n a n c i al Group, Inc., Austin, TX
Organizer: Mike Murray - Acuson Corp.,
Mountain View, CA
How does a novel EDA idea get transformed
into a commercially successful product? Six
veteran EDA entrepreneurs will discuss their
experiences in bringing their companies' first
products to market. Where did their ideas
come from? How did they know their ideas
would meet real customer needs? And how
many customers would there be? How are
evolutionary and revolutionary products
developed and marketed differently? When
did the entrepreneurs stop developing and
start shipping? Who were their competitors
and their partners? Did they adopt industry
standards or create new ones? How did they
use advertising, DAC, and the WWW to
promote the product? What are the relative
merits of direct, VAR, and OEM selling?
PANEL MEMBERS:
Rick Carlson - Synplicity, Inc.,
Sunnyvale, CA
Lorne Cooper - Sente, Inc., Acton, MA
Dean Drako - Design Acceleration, Inc.,
San Jose, CA
Rajeev Madhavan - Magma Design
Automation, Inc., Palo Alto, CA
John Sanguinetti - Chronologic, Los
Altos, CA
Curt Widdoes - 0-In Design Automation,
Inc., San Jose, CA
29
t
hursday, june 18
SESSION 41
Room: 102
Room: 301
FAST FUNCTIONAL
SIMULATION
POWER ESTIMATION AND
MODELING
Chair: Patrick C. McGeer - Cadence Berkeley
Labs., Berkeley, CA
Organizers: Rajesh K. Gupta, David Ku
Chair: Farid N. Najm - Univ. of Illinois, Urbana, IL
Organizers: Farid N. Najm, Andrew T. Yang
Papers in this session examine recent advances in
fast functional simulation. We begin with an
embedded tutorial followed by two short papers
demonstrating efficient simulation methods using
hybrid modeling and reconfigurable hardware.
2:00
to
4:00
SESSION 42
41.1 Embedded Tutorial: System Simulation:
Methodologies and Examples
Kunle Olukotun, Mark Heinrich, David Ofelt Stanford Univ., Stanford, CA
41.2S Hybrid Techniques for Fast Functional
Simulation
Yufeng Luo - Synopsys, Inc., Mountain View, CA
Tjahjadi Wongsonegoro, Adnan Aziz - Univ. of
Texas, Austin, TX
41.3S A Reconfigurable Logic Machine for Fast
Event-Driven Simulation
Jerry Bauer, Michael Bershteyn, Ian Kaplan,
Paul Vyedin - Quickturn Design Systems, Inc.,
San Jose, CA
State of the art integrated circuits are known to
dissipate large amounts of power. In order to
manage the power dissipation during the design
process, CAD approaches are required to estimate
and model the power at all levels of abstraction. The
papers in this session cover a variety of topics,
including parallelized and statistical simulationbased power estimation, high-level power
macromodeling, maximum power estimation, and
low-power signal encoding.
42.1 Parallel Algorithms for Power Estimation
Victor Kim, Prithviraj Banerjee - Northwestern
Univ., Evanston, IL
42.2 A Novel Power Macromodeling Technique
Based on Power Sensitivity
Zhanping Chen, Kaushik Roy - Purdue Univ.,
West Lafayette, IN
42.3 Maximum Power Estimation Using the
Limiting Distributions of Extreme Order
Statistics
Qinru Qiu, Qing Wu, Massoud Pedram - Univ. of
Southern California, Los Angeles, CA
42.4S An Optimization-Based Error Calculation
for Statistical Power Estimation of CMOS Logic
Circuits
Byunggyu Kwak - Samsung Data Systems.,
Seoul, Korea
Eun Sei Park - Hanyang Univ.,
Kyunggi-do, Korea
42.5S Using Complimentation and
Resequencing to Minimize Transitions
Rajeev Murgai, Masahiro Fujita - Fujitsu Labs.
of America, Inc., Santa Clara, CA
Arlindo Oliveira - Cadence Eur Labs./INESC/IST,
Lisboa, Portugal
30
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hursday, june 18
SESSION 43
Room: 305
TECHNOLOGY MAPPING
FOR PROGRAMMABLE
LOGIC
Chair: Jonathan Rose - Univ. of Toronto,
Toronto, ON, Canada
Organizers: Jason Cong, TingTing Hwang
This session presents new technology mapping
algorithms for complex PLDs and FPGAs. The
first paper presents synthesis and mapping
methods for PLA-style logic blocks. The second
and third papers study the technology mapping
problems for FPGAs with heterogeneous LUTs.
The fourth paper presents a new function
decomposition formulation and solution. The fifth
and sixth papers present post-layout re-synthesis
methods for power reduction in FPGA designs.
43.1 Technology Mapping for Large
Complex PLDs
Jason Helge Anderson, Stephen Dean
Brown - Univ. of Toronto, Toronto, ON,
Canada
43.2S Delay-Optimal Technology Mapping
for FPGAs with Heterogeneous LUTs
Jason Cong, Songjie Xu - Univ. of
43.3S Exact Tree Based FPGA
Technology Mapping for Logic Blocks
with Independent LUTs
Madhukar K. Korupolu, K.K. Lee, D.F.
Wong - Univ. of Texas, Austin, TX
43.4 Compatible Class Encoding in Hyperfunction Decomposition for FPGA Synthesis
Jie-Hong Jiang, Jing-Yang Jou, JuinnDar Huang - National Chiao Tung Univ.,
Hsinchu, Taiwan ROC
43.5S In-Place Power Optimization for
LUT-Based FPGAs
Balakrishna Kumthekar - Univ. of Colorado,
Boulder, CO
Luca Benini - Univ. of Bologna, Bologna, Italy
Enrico Macii - Politecnico di Torino,
Torino, Italy
Fabio Somenzi - Univ. of Colorado, Boulder, CO
43.6S A Re-Engineering Approach to Low
Power Design Using SPFD
Janmin Hwang, Fengyi Chiang,TingTing
Hwang - Tsing Hua Univ., Hsinchu, Taiwan
ROC
SESSION 44
Room: 304
POWER DISSIPATION
AND DISTRIBUTION IN
HIGH PERFORMANCE
PROCESSORS
Chair: David T. Blaauw - Motorola, Inc.,
Austin, T X
Organizers: Anatha Chandrakasan,
Jan M. Rabaey
As feature sizes shrink and clock rates grow,
power dissipation is rapidly becoming a limiting
factor. Sources of power dissipation and power
management techniques for high performance
processors will be discussed. With high power
levels, also comes the challenge of reliably
distributing power on the chip.
44.1 Power Considerations in the Design
of the Alpha 21264 Microprocessor
Michael K. Gowan, Larry L. Biro,
Daniel B. Jackson - Digital Equipment
Corp., Hudson, MA
44.2 Reducing Power in HighPerformance Microprocessors
Vivek Tiwari, Deo Singh, Suresh
Rajgopal, Gaurav Mehta, Junju
Sugisawa, Franklin Baez - Intel Corp.,
Santa Clara, CA
44.3 Design and Analysis of Power
Distribution Networks in PowerPC™
Microprocessor
Abhijit Dharchoudhury, Rajendran V.
Panda, David T. Blaauw, Ravi
Vaidyanathan - Motorola, Inc., Austin, T X
Bogdan Tutuianu, David Bearden Somerset Design Center, Austin, TX
44.4 Full-Chip Verification Methods for
DSM Power Distribution Systems
Gregory Steele - Simplex Solutions,
Inc., Sunnyvale, CA
David Overhauser - Simplex Solutions,
Inc., San Jose, CA
Steffen Rochel - Simplex Solutions,
Inc., Sunnyvale, CA
Syed Zakir Hussain - Simplex Solutions,
Inc., San Jose, CA
SESSION 45
Room: 103
TEST CHALLENGES IN
THE SYSTEM CHIP ERA
Chair: Prab Varma - Duet Technologies,
San Jose, CA
Organizers: Prab Varma - Duet
Technologies Inc.,
San Jose, CA
Takahide Inoue - Sony
Corp., Milpitas, CA
45.1 Embedded Tutorial: System-Chip
Test Strategies
Yervant Zorian - LogicVision, Inc.,
San Jose, CA
PANEL: System Chip
Test Challenges: Are
There Solutions Today
The panel will discuss the challenges
associated with testing system chips
containing pre-designed virtual components
and will address the question of whether
there are viable solutions today. It will
discuss whether the time to market gains
offered by design re-use will be realized
without test re-use. It will also debate the
impact of the SIA Roadmap on test
requirements and the limitations in ATE and
the issues in performance testing that will
have to be addressed to test tomorrow's
system chips.
PANEL MEMBERS:
Sujit Dey - Univ. of California, San
Diego, CA
Rudy Garcia - Schlumberger
Te c h n o l o g i e s, San Jose, CA
Erik Jan Marinissen - Philips Research
Labs., Eindhoven, The Netherlands
Bruce Mathewson - Advanced RISC
Machines Ltd., Cambridge, UK
Rob Roy - Intel Corp., Hillsboro, OR
Prab Varma - Duet Technologies,
San Jose, CA
Yervant Zorian - LogicVision, Inc.,
San Jose, CA
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hursday, june 18
SESSION 46
Room: 102
CONTROLLER
DECOMPOSITION FOR
POWER AND AREA
MINIMIZATION
Chair: Fabio Somenzi - Univ. of Colorado,
Boulder, CO
Organizers: Timothy Kam, Luciano Lavagno
4:30
to
6:00
32
Decomposition of finite state controllers is essential to
minimize both area and power. The first two papers
are devoted to identification and separation of highand low-activity portions of a finite state machine,
respectively at the state graph and at the logic level,
in order to significantly increase the opportunities for
clock gating. The third paper tackles a classical
problem, decomposition for minimum area, by
exploiting a hierarchical grammar-based specification
style, and providing partitioned controllers that are
easier to understand and debug.
46.1 Finite State Machine Decomposition for
Low Power
Jose Monteiro - INESC/IST, Lisboa, Portugal
Arlindo Oliveira - Cadence Eur Labs./INESC/IST,
Lisboa, Portugal
46.2 Computational Kernels and Their
Application to Sequential Power Optimization
L. Benini, Giovanni De Micheli - Stanford Univ.,
Stanford, CA
Antonio Lioy, Enrico Macii, G. Odasso, Massimo
Poncino - Politecnico di Torino, Torino, Italy
46.3 Partitioning and Optimizing Controllers
Synthesized from Hierarchical High-Level
Descriptions
Andrew Seawright, Wolfgang Meyer Synopsys, Inc., Mountain View, CA
SESSION 47
Room: 301
IP PROTECTION
TECHNOLOGIES
Chair: Tom VandenBerge - Texas Instruments,
Dallas, TX
Organizers: Richard Smith, Takahide Inoue
The requirement for the exchange of Intellectual
Property in the design of systems on a chip is well
documented. Protection of IP is needed to support
this exchange. This session presents techniques
for watermarking IP to prove ownership and
encrypting IP to discourage reverse engineering.
47.1 Watermarking Techniques for
Intellectual Property Protection
Gregory Wolfe, Miodrag M. Potkonjak, John
Lach, William H. Mangione-Smith, Andrew B.
Kahng, Stefanus Mantik , Paul Tucker, Huijuan
Wang - Univ. of California, Los Angeles, CA
Igor L. Markov - Univ. of California, Beverly
Hills, CA
47.2 Robust IP Watermarking Methodologies
for Physical Design
Andrew B. Kahng, Stefanus Mantik - Univ. of
Igor L. Markov - Univ. of California, Beverly
Hills, CA
Miodrag M. Potkonjak - Univ. of California, Los
Angeles, CA
Paul Tucker - Univ. of California, San Diego, CA
Huijuan Wang, Gregory Wolfe - Univ. of
47.3 Data Security for Web-Based CAD
Scott Hauck, Stephen Knol - Northwestern
Univ., Evanston, IL
t
hursday, june 18
SESSION 48
Room: 305
CASE STUDIES OF NEW
DESIGN METHODS
Chair: Anders Forsen - Ericsson Radio Systems
AB, Stockholm, Sweden
Organizers: Ivo Bolsens, James A. Rowson
New methods are difficult to evaluate without real data.
The papers in this session provide real case studies and
benchmarking approaches for four novel design
methods.
48.1 Design of a SPDIF Receiver Using Protocol
Compiler
Ulrich Holtmann - Synopsys, Inc.,
Mountain View, CA
Peter Blinzer - Technical Univ. of Braunschweig,
Braunschweig, Germany
48.2S Metacore: An Application Specific DSP
Development System
Jin-Hyuk Yang, Byung-Woon Kim, Sang-Jun Nam,
Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu,
Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee,
Jong-Sun Kim, Hyun-Dong Yoon, Jae-Yeol Kim,
Kun-Moo Lee, Chan-Sik Hwang, In-Jung Hwang,
Jun-Sung Kim, Kwang-Il Park, Kyu-Ho Park, YongHoon Lee, Seung-Ho Hwang, In-Cheol Park,
Chong-Min Kyung - KAIST, Taejon, Korea
48.3S A Case Study in Embedded System Design:
An Engine Control Unit
Attila Jurecska, Antonino Damiano - Magneti Marelli,
Venaria Reale, Italy
Tullio Cuatto, Claudio Passerone, Luciano
Lavagno, Claudio Sansoe - Politecnico di Torino,
Torino, Italy
48.4S HW/SW Coverification Performance
Estimation & Benchmark for a 24 Embedded Risc
Core Design
Thomas W. Albrecht, Johann Notbauer, Stefan
Rohringer - Siemens AG, Vienna, Austria
48.5S System-Level Exploration with Specsyn
Daniel D. Gajski - Univ. of California, Irvine, CA
Frank Vahid - Univ. of California, Riverside, CA
Sanjiv Narayan - Ambit Design Systems, Inc.,
Santa Clara, CA
Jie Gong - Motorola, Inc., Tempe, AZ
SESSION 49
Room: 103
THIRTY-FIVE YEARS OF
DESIGN AUTOMATION, A
RETROSPECTIVE AND A
LOOK-FOWARD
(no badge is required to attend)
Chair: Paul Weil - Intel Corp., Santa Clara, CA
Organizer: Jan M. Rabaey
This session will celebrate thirty five years of design
automation with three presentations by long time
contributors to the field. These presentations will review
the past accomplishments and views of the future. There
will be a panel session after the talks.
49.1 CAD Through EDA to RIP
Ron Rohrer - Intersouth Partners, Research
Triangle Park, NC
49.2 Physical Design Automation: A Look Back
and the Challenges Ahead
Bryan Preas - Xerox Parc, Palo Alto, CA
49.3 The New Frontier: From Logic Synthesis to
System Design
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university design contest
New this year DAC has created the University Design Contest. Attend Session 3 to see the top
entries of original electronic designs (circuits or system) that have resulted in operational
implementation. This competition among University researchers was judged on the level of
innovation in the design flow and their use of EDA tools. The top contestants have produced
outstanding work that is detailed in the Session 3 – University Design Contest.
Do you have a hot design? Tell the world about it by submitting a proposal to the 36th DAC
University Design Contest. Submissions of original electronic designs (circuit or system) developed
at Universities and research organizations after June, 1997 and resulting in operational
implementations are invited. All entries should provide a complete description of the design and
clarify the originality, distinguishing features and measured performance metrics of the design.
Proof-of-implementation in the form of die or board photographs and measurement data is a must.
See the 36th DAC Call for Papers for complete details on pages 46 - 47.
notes
34
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riday, june 19
35th DAC full day tutorials
Tutorials will be held at the Moscone Center in the Esplanade Ballrooms 301 - 306.
8:00 AM - Tutorial Registration Opens (Esplanade Lobby)
8:30 AM - Continental Breakfast
9:00 AM - Tutorials Begin
Tutorial
One
12:00 Noon - Lunch
5:00 PM - Tutorials End
Design Validation Techniques
Room 305
Organizer: Gitanjali Swamy - Boston Advanced Development Labs., Mentor Graphics Corp., Boston, MA
Presenters:
Adnan Aziz - Univ. of Texas, Austin, TX
Rajeev Muragi - Fujitsu Labs. of America, Inc., Santa Clara, CA
Amit Narayan - Univ. of California, Berkeley, CA
Gitanjali Swamy - Boston Advanced Development Labs., Mentor Graphics, Boston, MA
Audience: The tutorial will be of interest to the following audiences.
Digital designers, and design project managers: in understanding and choosing validation techniques that are
best suited for different design stages. This will assist evaluation of commercial validation offerings, and help
devise a comprehensive validation strategy in which bugs are caught early in the design cycle.
CAD vendors: in identifying technologies that are relatively mature in the research community and are ready
to be commercialized.
Researchers: in identifying open research problems, where significant advances can be made.
What distinguishes this tutorial from previous ones is that it provides a complete and comprehensive survey
of methods for functional validation, rather than focus on a particular technology alone.
Description: The increasing complexity of VLSI systems has made their functional validation extremely difficult.
Indeed, verification has become the bottleneck in the IC design process today, with validation teams often being
comparable in size to design teams. This tutorial covers state-of-the-art validation techniques. These include the
traditional methods of simulation and emulation, as well as the emerging formal verification technologies. We will
summarize many of the university CAD tools that incorporate these ideas.
Specifically, the tutorial will cover the following topics: Computational models for designs, State-of-the-art
simulation techniques, Emulation technology, Formal equivalence of combinational and sequential gate and
RTL level designs, Formal property verification using model checking, language containment, symbolic
trajectory evaluation and theorem proving. Techniques for advancing the frontiers of verification ranging from
approximation techniques to combining formal verification with simulation for better coverage. Theory will be
reinforced by practice through the use of software demonstrations of public domain tools. Emphasis will be
placed on techniques which can handle large scale designs.
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Tutorial
Two
riday, june 19
Design of Complex Mixed-Signal
Systems on a Chip
Room 302
Organizer: Ken Kundert - Cadence Design Systems, Inc., San Jose, CA
Presenters:
Henry Chang - Cadence Design Systems, San Jose, CA
Felicia James - Texas Instruments, Dallas, TX
Dan Jefferies - Cadence Design Systems, Inc., San Jose, CA
Ken Kundert - Cadence Design Systems, Inc., San Jose, CA
Lee Stoian - SiPCore, San Jose, CA
Richard Trihy - Cadence Design Systems, Inc., San Jose, CA
Audience: The primary audience would be circuit designers and CAD engineers involved in complex mixed-signal design.
Description: Shrinking transistor sizes and product lifetimes require engineers to design chips that contain more and more
of the system while doing so in less and less time. As more of the system is included on a single chip, it is increasingly
likely that that chip will contain both analog and digital sections. These systems are often quite large and complex. For
example, a modern read channel IC may have in excess of fifty thousand digital gates and ten thousand analog transistors.
In order to manage these more complex designs, many development teams are finding they need to move from traditional
"bottom-up" design approaches to more system-oriented "top-down" design style with verification using "mixed-level"
simulation. Difficulties in designing and verifying these designs will be discussed and an evolving methodology for reliably
designing these large mixed-signal chips with a minimum number of design turns is presented.
In 1998 and 1999 several commercial implementations of the Verilog-AMS and VHDL-AMS standards are expected to
become available. Both the Verilog-AMS and VHDL-AMS languages are introduced and contrasted using simple
examples. Features and pitfalls are identified. Mixed-level verification using V*-AMS is discussed.
Tutorial
Three
36
CAD for System Design: Models, Issues,
and Some Emerging Tools
Room 303
Organizer: Gaetano Borriello - Univ. of Washington, Seattle, WA
Presenters:
Gaetano Borriello - Univ. of Washington, Seattle, WA
Jan M. Rabaey - Univ. of California, Berkeley, CA
James A. Rowson - Alta Group of Cadence Design Systems, Inc., Sunnyvale, CA
Alberto L. Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA
Audience: This tutorial is intended for engineers and managers involved directly in design or in CAD who want to gain
a perspective on the critical issues regarding emerging tools to support system-level design.
Description: System design issues are gaining more and more importance as time-to-market shrinks and complexity
rises. Isolated attempts have been made to address portions of the system design problem, but a more holistic
approach is needed. The relatively independent approaches need to be related and the critical links to current
implementation approaches for both hardware and software need to be created.
Industry is now clamoring for tools to help system designers evaluate at ever higher levels of abstraction to permit more
effective exploration of the design space and the tradeoffs between functionality and implementation constraints.
Moreover, there is a corresponding need for increased automation in generating many of the details of a system
implementation so that designs can be more quickly prototyped and produced. A fundamental part of this is realizing the
promise of design reuse and facilitating the growth of a market for intellectual property in both embedded hardware and
software. There are four principal elements to realizing the vision of system-level tools: modeling and abstraction, software
and hardware reuse, estimation and evaluation, synthesis and compilation. In this tutorial, we will review these issues
and highlight some promising directions with some examples of the types of tools that are emerging.
f
Tutorial
Four
riday, june 19
Interconnect Analysis in High-Frequency,
Sub-Micron, Digital VLSI Design
Room 304
Organizer: Peter Feldmann - Lucent Technologies Bell Labs., Murray Hill, NJ
Presenters:
Peter Feldmann - Lucent Technologies Bell Labs., Murray Hill, NJ
Roland W. Freund - Lucent Technologies Bell Labs., Murray Hill, NJ
Tak Young - Synopsys, Inc., Mountain View, CA
Audience: This tutorial is intended for CAD tool developers and researchers, for engineers responsible for
design methodologies, and for VLSI designers who need to understand the capabilities and limitations of the
tools they use.
Description: This tutorial focuses on the principal problems related to interconnect-parasitics extraction and
analysis in advanced, high-frequency, digital VLSI applications. First, we review the parasitic effects of
interconnect: capacitance, resistance, inductance, transmission-line effects, and substrate noise. We
discuss when the various interconnect aspects become important, when some of them can be safely ignored,
and future trends.
Next, we discuss the various extraction approaches and their domains of applicability. We cover the entire
spectrum from simple capacitance to resistance-capacitance extraction, to full-wave analysis. We describe
specific techniques, including formula-based approaches, 2D analysis, 2 1/2D analysis, 3D methods, the
use of field solvers such as finite elements and the method of moments, and fast algorithms such as
multiple techniques.
The next challenging task then is to handle the enormous amount of data generated by extraction at the chip
level. This requires smart screening techniques, efficient data reduction, and fast and accurate simulation. We
cover these techniques in the context of two important interconnect-analysis problems: verification against
cross-talk and reliability analysis. For the analysis and reduction of the interconnect models, Krylov-subspace
techniques have emerged as the methods of choice. These methods generate reduced-order models based on
Pade or Pade-type approximations of the frequency-domain transfer function. We survey the state-of-the art in
Krylov-subspace methods for interconnect analysis. In particular, we discuss important issues, such as
accuracy, stability, and passivity of the reduced-order models.
Finally, we illustrate the incorporation of interconnect extraction and analysis in the VLSI design flow with two
examples: transistor-level design and cell-based design. Here, the design flows include signal screening,
critical-path selection, and delay calculation. The inclusion of interconnect-parasitics effects in clock-skew
analysis, power calculation, in cross-talk analysis, and in reliability simulation will also be discussed.
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Tutorial
Five
riday, june 19
Finding Design Errors and Locating Defects:
The Same Detective Story
Room 301
Organizer: Miron Abramovici - Lucent Technologies Bell Labs., Murray Hill, NJ
Presenters:
Miron Abramovici - Lucent Technologies Bell Labs., Murray Hill, NJ
Robert Aitken - Hewlett-Packard, Palo Alto, CA
Audience: Designers, researchers, managers, and anyone determined to find out where those puzzling errors
are coming from.
Suggested Prerequisites: Logic and circuit design, basic testing concepts, and a strong desire to discover if
indeed the butler did it.
Description: Locating design errors is a key factor in the logic verification process. Errors can result from
incorrect specifications, erroneous logic implementation, and/or timing problems. Just as accurate error
location is needed to meet time-to-market goals, accurate physical defect location is essential in improving
the quality of the manufacturing process, and rapid identification of a defective replaceable part is essential
in achieving a cost-effective field maintenance and repair process. The efficiency of all forms of diagnosis has
a great economic impact on the cost of a product during its entire life-cycle (cost-of-ownership). Unlike fault
and defect diagnosis, the practice of logic debugging is more of an engineering art than a science, and tools
for diagnosis in the logic domain are still in experimental/prototype stage.
The tutorial will present methods for finding design implementation errors and techniques for locating defects
in circuits. We will point out the many similarities between logical and physical diagnosis, and we will
emphasize the common principles that guide each diagnosis process. After a review of the basic concepts in
diagnosis, we will present the established defect diagnosis procedures - fault dictionary, post-test fault
simulation, and guided-probe/E-beam testing. Then we will focus on advanced diagnosis topics such as critical
path tracing, deductive analysis, diagnosis for delay-faults, AI techniques, and methods for locating defects
such as opens, shorts, and leakage in transistor-level circuits.
In the logic domain, we will present several techniques to automatically generate design verification tests, and
several methods that locate the logic error(s) that cause mismatches between implementation and
specification. We will also discuss techniques that automatically correct the located errors. The models where
errors are located range from VHDL to transistor-level designs. In addition to logic errors, we will discuss
techniques to locate timing problems in circuits, and discuss design-for-debug methods to simplify this process.
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Tutorial
Six
riday, june 19
High Performance RTL Coding
Styles for Synthesis
Room 306
Organizer: Joseph Pick - Synopsys, Inc., Bethesda, MD
Presenters:
J. Bhasker - Lucent Technologies Bell Labs., Allentown, PA
Egbert Molenkamp - Univ. of Twente, Enschede, The Netherlands
Joseph Pick - Synopsys, Inc., Bethesda, MD
Audience: This tutorial is intended for current and future synthesis users who wish to accumulate a collection
of coding style tricks and techniques that will improve their overall synthesis productivity. A basic
understanding of either the VHDL or Verilog hardware description language is assumed.
Description: Having attended an introductory VHDL or Verilog simulation based class digital designers must
then subsequently, by themselves, discover the interplay and duality between software coding styles and their
hardware counterparts as derived via synthesis. These engineers must, on their own, rapidly master the
fundamentals of synthesizable RTL coding styles and then, through trial and error, explore the best way to write
their VHDL/Verilog models so that they will have optimum synthesis results. This steep and often lonely learning
curve can be a very frustrating experience, especially when a project deadline is just a few months away.
Lack of education in the area of coding styles for RTL synthesis will have a negative impact on an engineer’s
overall productivity. The main thrust of this tutorial is to overcome many of these design barriers by spanning
the full spectrum of synthesis RTL coding styles, from fundamental principles to advanced techniques. This
innovative, examples oriented tutorial will be an educational and entertaining experience for both current and
future synthesis users. The first half of this tutorial will present numerous real-world examples from the
following topics: synthesizable and non-synthesizable VHDL/Verilog constructs, duality between VHDL/Verilog
models and synthesized hardware, importance of VHDL/Verilog coding styles for efficient hardware synthesis,
simulation and synthesis mismatches, relying on hardware design experiences, and advanced VHDL/Verilog
strategies and techniques. The second half of this tutorial will present a detailed exploration of FSMs and test
benches. The migration path from device specification to synthesizable code will be shown for numerous,
complex devices. Experiencing the derivation of these complex, synthesizable models will further improve the
productivity of synthesis users.
39
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birds-of-a-feather
DAC will provide conference rooms for informal groups to discuss items of common technical interest.
These very informal non-commercial meetings, held after hours, are referred to as “Birds-of-a-Feather”.
how do you set up a “BOF” meeting?
DAC will facilitate common interest group meetings to discuss DA related topics. To arrange a BOF
sign up at the Information Desk on-site. A room will only be assigned if ten or more people sign up.
A viewgraph projector and screen will be provided on request. Wednesday evening June 17, from
6:00PM to 7:30PM is reserved for these meetings. These meetings will be held at the San Francisco
Marriott (prior to the Wednesday night DAC party at the San Francisco Marriott). The room locations
will be announced at the conference; check DACnet and the Birds-of-a-Feather board at the
Information Desk.
verilog-AMS
Verilog supports digital event driven simulation. Verilog-A describes analog continuous time
behavior. Verilog-AMS supports mixed-signal hardware description and simulation by specifying how
analog and digital descriptions may be combined and how the analog and digital domains interact.
A summary of the latest version of the Language Reference Manual for Verilog-AMS will be
presented by a member of the OVI technical subcommittee working group. Examples of mixed
signal hardware descriptions will be shown.
use of the open library API (OLA) in deep submicron design
methodologies
OLA is an Application Procedural Interface (API) based mechanism for exchanging technology
specific information between an ASIC vendor library and EDA tools. This Birds of a Feather session
will focus on the use and migration to OLA by ASIC and EDA vendors. The Open Library API along
with the underlying ALF (standardized by OVI) and DCL (under standardization by IEEE) language
syntax will also be described.
is a standard interface to on-chip buses a solution for the mix and
match of virtual components
The On-Chip Bus Development Working Group of VSI Alliance is developing a specification for a
Virtual Component Interface, a simple point-to-point protocol which will allow Virtual Components to
be connected to an On-Chip Bus. In certain cases, it could incur some gate and performance
overhead. While this may not be a problem for low-speed peripheral buses, will it pose a problem
for high performance system buses? VSI’s On-Chip Bus Working Group is attempting to cover all
the major characteristics of peripheral and system buses in one extendable Virtual Component
Interface standard.
40
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additional meetings
Ph.D forum at DAC - follow-up session
Organizers: Soha Hassoun - Tufts Univ., Medford, MA
Oliver Coudert - Synopsys, Inc., Mountain View, CA
This session will feature a few parallel tracks. In each track, a number of students will present to
academic and industrial researchers a 20-minute overview of their Ph.D thesis work. The goal is to
provide students with detailed feedback on their work. Invitations will be issued at the open poster
session during the SIGDA member meeting, Tuesday, June 16, 7:00PM - 9:00PM. For more
information about the Ph.D Forum at DAC, please visit:
http://www.cs.washington.edu/homes/soha/forum/
SIGDA member meeting
SIGDA will hold a semi-annual member meeting at the San Francisco Marriott in Golden Gate room
A on Tuesday evening, June 16, from 7:00 PM to 9:00 PM. This meeting is open to all. A light
dinner will be served.
IFIP working group 10.5
Integrated Electronic Systems Design. Thursday evening, June 18 at the Moscone Center in room 114.
CANDE meeting
Wednesday, June 17, 6:00-7:30PM, in room Pacific H, on the 4th floor, at the Marriott hotel.
41
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proceedings
ACM/SIGDA (Association for Computing Machinery/Special Interest Group on Design
Automation) and the Design Automation Conference will jointly publish the proceedings of
DAC’98 on CD-ROM. Papers can be accessed using Adobe Acrobat Reader 3.0 (included on
the CD-ROM) or through an HTML browser and PostScript viewer (furnished by the user).
DAC Proceedings will also be available on the World Wide Web after the conference.
A compendium CD-ROM, containing the conference proceedings from the previous year, is
published annually, beginning with Compendium94 (containing DAC, EURO-DAC and ICCAD).
Compendium96 contains ED&TC’96, DAC’96, EURO-DAC’96, ICCAD’96, and proceedings from
three symposia (FPGA’96, ISLPED’96, ISSS’96). Compendium97 contains ASP-DAC’97
ED&TC’97, DAC’97, ICCAD’97 and proceedings from four symposia (FPGA’97, ISLPED’97 and
ISPD’97, ISSS’97.)
SIGDA conference proceedings on CD-ROM and Compendium CD-ROMs are available from
ACM. Stop by the ACM booth for further information.
35th DAC proceedings
The 35th DAC proceedings will contain 148 papers. This year, DAC is offering each conference
and student registrant the proceedings in both the hard bound edition and the CD-ROM edition.
Should you wish to purchase any additional copies you may do so at the ACM booth for $40.00.
After the conference, mail orders should be sent to the ACM. ACM should be contacted before
placing your order to determine cost and availability of the proceedings.
The address is:
ACM Order Department
P.O. Box 11315
New York, NY 10286-1315
1 (800) 342-6626 (U.S.A. and Canada)
1 (212) 626-0500 (all other countries)
Fax: 1 (212) 944-1318
e-mail: [email protected]
ACM/TODAES (transactions on design automation
of electronic systems)
Quarterly—ACM Member: $37.00, ACM/SIGDA Member $25.00, Non-member: $160.00—
TODAES will be your pulse in the rapidly changing field of design technology of electronic
systems. Distributed in three formats—hardcopy, electronic distribution via an internet server
and an annual CD-ROM. TODAES will keep you current in areas of: •system design •high level
synthesis •physical layout •design verification •system reliability •high performance circuits.
42
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san francisco attractions
The lure of historic San Francisco has attracted thousands of visitors every year to experience the
unique charm and beauty of this “City by the Bay”. No other city in the world can boast of the variety
of attractions that makes San Francisco famous.
By simply crossing a street, you can leave Hong Kong and visit Naples, Chinatown, North Beach,
Japantown, Pacific Heights, and The Mission District all offering enough cultural variety that you will
feel like you’ve traveled around the world instead of around the city.
Of course there is always the Golden Gate Bridge, Lombard Street, Alcatraz, Fisherman’s Wharf, Coit
Tower, the Cable Cars and a few hundred other famous attractions to keep you occupied. The Wine
Country (Napa and Sonoma) is only a short drive and Sausalito is an enjoyable ferry ride across the
Bay. If you still have the time and energy, San Francisco provides some of the finest dining and
shopping to be found anywhere. You will find this city a treat for every member of your family.
35 years of DAC anniversary party
The DAC party this year revisits seven of the cities where the Conference took place. Cuisines and
themes will be featured from: Atlantic City (1964), Washington DC (1968), Portland (1973), Las
Vegas (1978), Miami Beach (1983), Anaheim (1988) and Dallas (1993). In the main ballroom, the
Rich Martini Orchestra will play swing dance music, as well as popular hits from the past 35 years.
Local musician and DAC attendee, Subha, will perform his original music in the Nob Hill Ballroom.
future sites of DAC
36th
37th
38th
39th
40th
DAC
DAC
DAC
DAC
DAC
-
New Orleans, LA - June 21-25, 1999
Los Angeles, CA - June 5-9, 2000
San Francisco, CA - June 4-8, 2001
New Orleans, LA - June 10-14, 2002
Anaheim, CA - June 2-6, 2003
guest/family program
A $45 registration fee will admit each guest or family member to the following:
1.Tuesday night Cocktail Party in the Yerba Buena Ballroom at the San Francisco Marriott.
2. Wednesday night 35 Years of DAC Anniversary Party in the Yerba Buena Ballroom at the
San Francisco Marriott.
3.Use of the complimentary shuttle bus services between all DAC participating hotels and the
Moscone Center.
4. Admission to the exhibit hall when accompanied by an attendee.
REGISTRATION for the Guest/Family Program will be at the Conference Registration desk on Sunday,
June 14 through Wednesday, June 17. A badge will be provided for each registered guest or family
member. This badge must be worn to participate in the above activities. Look for the Guest
Registration sign in the registration area. Children under the age of 14 are not allowed in the
exhibit hall.
43
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busing
rental cars - DAC is not recommending the use of rental cars or cars in general this year due
to the limited space and prohibitive cost of parking in San Francisco. DAC encourages attendees
to leave their cars at home and utilize the excellent transportation system available in San
Francisco and the Bay Area.
busing - Complimentary shuttle bus service is provided by the Design Automation Conference
(DAC) for all registered conference attendees, exhibitors and guest program participants.
conference shuttle bus service - Day & Evening Route busing will be provided to and
from the Moscone Center and all appropriate participating DAC Hotels. Hours will be extended to
accommodate the DAC Demo Suite attendees.
wednesday night party - At 7:00 PM Wednesday night the buses will run from all
appropriate participating hotels to the San Francisco Marriott until 12:00 midnight.
Day route schedule (pick-up every 20 minutes)
Sunday, June 14
Monday, June 15
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
3:45
7:45
7:45
7:15
7:15
PM
AM
AM
AM
AM
-
6:30 PM
10:00 PM
10:00 PM
12:00 AM
6:30 PM
Day Busing routes and designated stops
Route A
*Best Western Canterbury Hotel
*Hotel Nikko
*King George
*Ramada Inn @ Union Square
*San Francisco Hilton
*Westin St. Francis
*The Handlery - Union Square
*Holiday Inn Select Union Square
*The Sir Francis Drake
*Villa Florence Hotel
*Parc Fifty-Five Hotel
*Powell Hotel
Drop-Off/Pick-Up
Hilton, Taylor Street
Westin St. Francis, Post
Cyril Magnin
Cyril Magnin
Route B
Grand Hyatt Union Square
Drop-Off/Pick-Up
Stockton Street
Route C
CALTRAIN Train Station
Holiday Inn Civic Center
* Indicates boarding location
Drop-Off/Pick-Up
4th & Townsend
8th
Easy walking distance:
ANA Hotel San Francisco
44
San Francisco Marriott
St.
St.
St.
St.
St.
Pickwick Hotel
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san francisco hotel map
45
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call for papers
36th design automation conference® • june 21 - 25, 1999
ernest n. morial convention center • new orleans, la
DAC is the premier conference devoted solely to the field of Design Automation. All aspects of the use of computers
as aids to the design process are welcome, from conceptual design to manufacturing. Five types of submissions
are invited: regular papers, special topic sessions, panels, tutorials, and design contest entries. All types of
submissions should be sent to the Program Chair, postmarked NO later than October 9, 1998.
requirements for submissions of papers
Previously published papers, including workshop proceedings, will not be considered. Each submission should include
one cover page and eleven (11) stapled copies of the complete manuscript.
The one cover page should include:
• Name, affiliation, and complete address for each author
• A designated contact person including his/her telephone number, fax number, and email address
• A designated presenter, should the paper be accepted
• A list of topic numbers preceded by the letter T (Tools Track) or M (Methods Track), ordered by relevancy, most clearly
matching the content of the paper
• The following signed statement: “All appropriate organizational approvals for the publication of this paper have been
obtained. If accepted, the author(s) will prepare the final manuscript in time for inclusion in the Conference
Proceedings and will present the paper at the Conference”.
To permit a blind review, do not include name(s) or affiliation(s) of the author(s) on the manuscript. Include:
• Title of paper
• 60-word abstract indicating significance of contribution
• The complete text of the paper in English, including all illustrations and references, not exceeding 4000 words. The
papers will be reviewed as finished papers. Preliminary submissions will be at a disadvantage.
Notice of acceptance will be mailed to the contact person by February 19, 1999. Authors of accepted papers must
sign a copyright release form.
panels, tutorials, special topic sessions
Proposals should not exceed two pages in length and should describe the topic and intended audience. They must include
a list of all participants, including the moderator for panels. For proposal instructions, send a one-line email message
to [email protected] with “proposal” in the subject field, or www.dac.com.
Special Topic Sessions may be either independent papers with a common theme or a set of closely related papers
describing an overall system. In both cases, independent reviews of each paper and evaluation of the session as a whole
will be used to select sessions. Proposals for Special Topic Sessions should be submitted along with the list of papers
to be included in the session and should describe the session’s theme. These proposals and paper submissions must
be postmarked no later than October 9, 1998.
university design contest
Submissions of original electronic designs (circuit or system), developed at universities and research organizations after
June 1997 and resulting in operational implementations are invited. Submissions should contain the title of the project,
a 60-word abstract and a complete description of the design, not exceeding 4000 words in text. The submission should
clarify the originality, distinguishing features, and the measured performance metrics of the design. Proof-ofimplementation in the form of die or board photographs and measurement data is a must. Submitted designs should not
have received awards in other contests. Submissions will be reviewed by a special committee of experts. Selected
designs will be presented and exhibited at the conference.
MP Associates, Inc.
ATTN: Technical Program Co-Chairs
Randal E. Bryant/Bryan D. Ackland
46
5305 Spine Rd., Suite A
Boulder, CO 80301
For information call: (303) 530-4333
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call for papers
topics of interest
Authors are invited to submit original technical papers describing recent and novel research or engineering developments
in all areas of design automation. The DESIGN TOOLS TRACK (T) is devoted to contributions to the research and
development of design tools and the supporting algorithms. The DESIGN METHODS TRACK (M) deals with contributions
to the research and development of design methodologies and applications of design automation tools to designs. Topics
of interest include, but are not limited to:
design tools track
T0.1 Fundamental CAD Algorithms, e.g., BDDs, graph
coloring, partitioning
T1.1 Electrical-level circuit and timing simulation
T1.2 Discrete simulation
T1.3 Critical path analysis and timing verification
T1.4 Power estimation
T2.1 Testing, fault modeling and simulation, TPG, test
validation and DFT
T2.2 Design and implementation verification (excluding
layout verification)
T3.1 Floorplanning and placement
T3.2 Global and detailed routing
T3.3 Module generation and compaction, transistor sizing
and cell library optimization, layout verification
T4.1 Technology independent, combinational logic
synthesis
T4.2 Technology dependent logic synthesis, library mapping,
interactions between logic design and layout
T4.3 Sequential and asynchronous logic synthesis and
optimization
T4.4 High-level synthesis
T5.1 Hardware Description Languages
T5.2 Hardware/Software co-design, partitioning, systemlevel specification and design aids
T5.3 Software synthesis and retargetable compilation
T5.4 Hardware/Software co-simulation
T6.1 Interconnect and packaging modeling and extraction
T6.2 Signal integrity and reliability analysis
T6.3 Analog and mixed-signal design tools and RF
T6.4 Microsensor and microactuator design tools
T6.5 Statistical design and yield maximization
T7.1 Frameworks, intertool communication, WWW-based
tools and databases
design methods track
The Design Methods track (M) deals with innovative methodologies for the design of electronic circuits and systems, as well as
creative experiences with design automation in state-of-the-art designs. Submissions for this track will be judged on how effectively
they teach new art in the development and application of new tools and techniques to real-world design problems.
M1
M1.1
M1.2
M1.3
M1.4
M1.5
M1.6
M1.7
M2
M2.1
M2.2
M2.3
M2.4
M2.5
Design methodologies and case studies for specific
design tasks
Design entry and specification
Simulation, analysis, modeling and estimation
Verification, test and debugging
Physical design, module generation, design for
manufacturing
Logic and high-level synthesis and optimization
System-level design, embedded-system design and
co-design
Other
Design methodologies and case studies for specific
application domains and platforms
Configurable computing, FPGA and rapid prototyping
Systems on a chip
Microprocessor and multiprocessor
DSP, data-paths, multimedia and communication
Wireless and data networking
M2.6 Other (MCM, optical, consumer)
M3 Performance and technology driven design
techniques
M3.1 Deep sub-micron: signal integrity, interconnect and
modeling
M3.2 High-performance design: timing, clocking and power
distribution
M3.3 Low power design
M3.4 Mixed-signal, analog, and RF
M3.5 Process technology development, extraction,
modeling
M3.6 Other (MEMS, sensors, new devices)
M4 Integration and management of DA systems
M4.1 Management of DA systems, design interfaces,
standards
M4.2 Distributed, networked, and collaborative design
M4.3 Intellectual property, design re-use and design
libraries
47
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awards
design automation conference graduate scholarships
Each year the Design Automation Conference sponsors several $24,000 scholarships to support graduate research and
study in Design Automation (DA), with emphasis in "design and test automation of electronic and computer systems".
Each scholarship is awarded directly to a university for the Faculty Investigator to expend in direct support of one or more
DA graduate students.
The criteria for granting such a scholarship expanded in 1996 to include financial need. The criteria are: the academic
credentials of the student(s); the quality and applicability of the proposed research; the impact of the award on the DA
program at the institution; and financial need. Preference is given to institutions that are trying to establish new DA
research programs.
Information on next year's DAC scholarship award program will be available on the DAC World Wide Web page at:
http://www.dac.com/scholarship.html.
design automation conference graduate scholarship awards
• Prof. Rajesh K. Gupta of the University of California, Irvine, CA, for Ali Dasdan. Their project is entitled,
Framework for Timing Constraint Analysis and Debugging for Embedded Systems.
• Prof. John Lillis of the University of Illinois, Chicago, IL, for Sung-Woo Hur and Prashanthi Malireddy. Their
project is entitled, New Techniques for Timing-Driven Placement.
• Prof. Frank Vahid of the University of California, Riverside, CA, for Tony Givargis. Their project is entitled,
Interface Exploration for Core-Based Systems.
The IEEE CAS supported DAC Graduate Scholarship is awarded to:
• Prof. Soha Hassoun of the Tufts University, Medford, MA, for Alexndros Margomenos, Terry Orfanos and
Edmund Sullivan. Their project is entitled, Microarchitectural Optimizations and Synthesis.
design automation conference graduate scholarship committee
James P. Cohoon
University of Virginia (Chair)
Michael Lightner
University of Colorado
Jeffrey S. Salowe
Cadence Design Systems, Inc.
1998 SIGDA meritorious service awards
For contributions in producing SIGDA CD ROM’s - Archiving the knowledge of the Design Automation Community
Jason Cong, University of California, Los Angeles, CA
Bryan Preas, Xerox PARC, Palo Alto, CA
Kathy Preas, KP Publications on CD-ROM, Palo Alto, CA
Cheng-Kok Koh, University of California, Los Angeles, CA
Chong-Chian Koh, University of California, Los Angeles, CA
advancement in computer science and electrical engineering undergraduate scholarships
The objective of the ACSEE Scholarship program is to increase the pool of professionals in Electrical Engineering and
Computer Science from under-represented groups (Women, African American, Hispanic, Native American, and Physically
Challenged). In 1989, ACM Special Interest Group on Design Automation (SIGDA) began providing the program. Beginning in
1993, the Design Automation Conference provides the funds for the scholarship and SIGDA continues to administer the
program for DAC. DAC normally funds two $4000 scholarships renewable up to 5 years to graduating high school seniors.
In 1997 three awards were made. The 1998 winners will be announced at the Conference.
1997 DAC ACSEE undergraduate scholarships
48
DAC $4K: Bryan Neil Ramirez, Crook, CO - attending Colorado School of Mines
DAC $4K: Christine Joyce Mina, Minot, MA - attending Worcester Polytechnic Institute
DAC $4K: Diala William Abboud, Charlotte, NC - attending Univ. of N. Carolina at Charlotte
d
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sponsorship
The 35th Design Automation Conference is sponsored by the ACM/SIGDA (Association for Computing
Machinery/Special Interest Group on Design Automation), IEEE/CAS (Institute of Electrical and
Electronics Engineers/Circuits and Systems Society) and EDAC (Electronic Design Automation
Consortium). Membership information is available at the ACM and IEEE booth.
EDA Consortium
The EDA Consortium is an international association of companies engaged in the development,
manufacture and sale of electronic design automation tools to the electronics engineering
community. Its goal is to promote the EDA industry by increasing awareness of the value of EDA tool
usage and by addressing industry-wide issues.
In addition, the EDA Consortium offers benefits such as:
• Maintains a centralized website for all member companies
• Develops standardized contracts for EDA tools sales, thereby reducing negotiation time
• Drives EDA standards through coordination and implementation
• Addresses issues specific to non-US EDA companies
• Sponsors and represents the interests of EDA companies at the DAC and DATE (Europe)
conferences
• Offers a 10% discount on booth and suites at DAC
• Reports on EDA market statistics for market share, industry trends and business forecasts
• Bestows the Design Achievement Awards to recognize outstanding integrated circuit and
electronic system development through the use of EDA tools
• Sponsors the Phil Kaufman Award to honor individuals for their exceptional innovative
contributions to design tool technology
For more information, contact the EDA Consortium • 111 West Saint John Street, Suite 200 • San
Jose, CA 95113, USA. • Phone: 408-287-3322 • email: [email protected] • http://www.edac.org.
49
d
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sponsorship
ACM / SIGDA
ACM, the Association for Computing Machinery, is an international scientific and educational
organization dedicated to advancing the arts, sciences, and applications of information
technology. With a worldwide membership of 80,000, ACM functions as a focus for computing
professionals and students working in the various fields of Information Technology. ACM
publishes and distributes books, magazines, and peer reviewed journals targeted to particular
computing fields, as well as the monthly magazine Communications of the ACM, the most cited
publication in computing. In late 1997 ACM launched its Digital Library, an invaluable online
resource of over 200,000 fully searchable pages of text from ACM's high quality journals and
proceedings dating back to 1991.
ACM has 37 Special Interest Groups that focus on different computing disciplines. More than half
of all ACM members join one or more of these Special Interest Groups. The SIGs publish
newsletters and sponsor important conferences such as SIGGRAPH, DAC, OOPSLA and CHI, giving
members opportunities to meet experts in their fields of interest and network with other
knowledgeable members.
Become an ACM member today and join thousands of other leading professionals, researchers
and academics who are benefiting from all ACM has to offer.
For further information, visit ACM on the web at http://www.acm.org/.
IEEE
The IEEE Circuits and Systems Society (CAS) is one of the largest societies within IEEE and in the
world devoted to the analysis, design, and applications of circuits, networks, and systems. Its
publication activities span over five archival journals, namely the IEEE Trans. on CAS-Part I
(Fundamentals); Part II (Analog and Digital Signal Processing); Trans. on CAD; Trans. on VLSI; and
Trans. on CAS for Video Technology. A newly formatted Newsletter provides the membership with
short articles on emerging technologies, such as wireless, mixed-mode IC design, and
hardware/software co-design. Also, the Society is cosponsoring with the SP-S, COM-S, and C-S a
new Trans. on Multimedia, expected to appear in early 1999. This periodicals activity of the highest
quality is supplemented by a number of international conferences, sponsored or co-sponsored by
the Society, which include ISCAS, ICCAD, and DAC. A worldwide comprehensive program of
advanced workshops and continuing education short courses, brings to the membership in various
regions the latest developments in cutting-edge technologies of interest to industry and academia
alike. Worthy of special note are the 1st CAS Workshop on Wireless-Communication Circuits &
Systems, to be held in Zurich on June 22-24, 1998 and the CAS 2nd International Workshop on
Design of Mixed-Mode Integrated Circuits and Applications to be held in Guanajuato, Mexico on July
27-29, 1998. For more information please contact the IEEE CAS Society.
50
Mail: IEEE CAS Society
15 W. Marne Ave.
P.O. Box 265
Beverly Shores, IN 46301-0265
Phone: 1-219-871-0210
E-mail: [email protected]
Web: http://www.ieee-cas.org
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technical program committee
TECHNICAL PROGRAM
CO-CHAIR, DESIGN TOOLS
Randal E. Bryant
Carnegie Mellon Univ.
School of CS
Pittsburgh, PA 15213
(412) 268-8821
[email protected]
Bryan D. Ackland
Lucent Technologies
Rm. 4E 508
101 Crawfords Corner Rd.
Holmdel, NJ 07733-1900
(908) 949-7248
[email protected]
David T. Blaauw
Motorola, Inc.
Advanced Design Tech.
Bridgepoint, Plaza 1
5918 W. Crtyrd. Dr., Ste. 330
Austin, TX 78730
(512) 794-4356
[email protected]
Ivo Bolsens
IMEC
VSDM, Kapeldreef 75
Leuven, BE B-3001 Belgium
(32) 16-281-211
[email protected]
Anantha Chandrakasan
Massachusetts Inst. of Tech.
Dept. of EE, Rm. 38-107
50 Vassar St.
Cambridge, MA 02139
(617) 258-7619
[email protected]
Mojy C. Chian
Harris Semiconductor
P.O. Box 883
MS 62BO22
Melbourne, FL 32902
(407) 724-7782
[email protected]
Nanette Collins
Consultant
37 Symphony Rd., Unit A
Boston, MA 02115
(617) 437-1822
[email protected]
Jason Cong
Univ. of California
4711 Boelter Hall
Dept. of CS
Los Angeles, CA 90095
(310) 206-2775
[email protected]
TECHNICAL PROGRAM
CO-CHAIR, DESIGN METHODS
Jan M. Rabaey
Univ. of California
Dept. of EECS
511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
[email protected]
Anders Forsen
Ericsson Radio Systems AB
RCUR-T/N, Kista
Stockholm, S-16480 Sweden
(46) 8-7572-541
[email protected]
David Ku
Escalade Corp.
2575 Augustine Dr.
Santa Clara, CA 95054
(408) 654-1617
[email protected]
Patrick Groeneveld
Magma Design Automation
1025A Terra Bella Ave.
Mountain View, CA 94043
(415) 938-6970
[email protected]
Andreas Kuehlmann
IBM Corp.
T.J. Watson Research Ctr.
P.O. Box 218
Yorktown Heights, NY 10598
(914) 945-3458
[email protected]
Rajesh K. Gupta
Univ. of California
444 Computer Science, 208B IREF
Irvine, CA 92697
(714) 824-8052
[email protected]
Luciano Lavagno
2001 Addison St., 3rd Fl.
Berkeley, CA 94704-1103
(510) 647-2810
[email protected]
Randolph E. Harr
Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA 94043-4033
(415) 694-1927
[email protected]
Sharad Malik
Princeton Univ.
Dept. of EE
Princeton, NJ 08544
(609) 258-4625
[email protected]
TingTing Hwang
Tsing Hua Univ.
Dept. of Computer Science
Hsin-Chu, 30043 Taiwan ROC
(886) 35-715-131
[email protected]
Alan Mantooth
Analogy, Inc.
9205 SW Gemini Dr.
Beaverton, OR 97075-1669
(503) 626-9700
[email protected]
Takahide Inoue
Sony Corp.
530 Cottonwood Dr.
Milpitas, CA 95035
(408) 955-4279
[email protected]
Teresa Meng
Stanford Univ.
Gates Computer Science
Bldg. 301
Stanford, CA 94028
(415) 725-3636
[email protected]
Andrew B. Kahng
Univ. of California
Dept. of CS, 3713 Boelter Hall
Los Angeles, CA 90024-1596
(310) 206-7073
[email protected]
Timothy Y. Kam
Intel Corp.
Strategic CAD Labs., JFT-102
5200 NE Elam Young Pkwy.
Hillsboro, OR 97124-6497
(503) 264-7536
[email protected]
Mike Murray
Acuson
1220 Charleston Rd.
MS L-1, Box 7393
(415) 694-5876
[email protected]
Farid N. Najm
Univ. of Illinois
1308 W. Main St.
Urbana, IL 61801
(217) 333-7678
[email protected]
51
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technical program committee (cont.)
Kunle Olukotun
Stanford Univ.
Gates 3A, Rm. 302
Stanford, CA 94305-9030
(415) 725 3713
[email protected]
Louis Scheffer
555 River Oaks Pkwy.
Bldg. 2, MS 2B1
San Jose, CA 95134
(408) 944-7114
[email protected]
Kazutoshi Wakabayashi
NEC Corp.
C&C Research Labs.
4-1-1 Miyazaki
Kawasaki, 216 Japan
(81) 44-856-2134
[email protected]
Hidetoshi Onodera
Kyoto Univ.
Dept. of Electronics & Comm.
Sakyo-ku
Kyoto, 606-01 Japan
(81) 75-753-5314
[email protected]
Sunil D. Sherlekar
Silicon Automation Systems
3008, 12th B Main, 8th Cross
HAL 2nd Stage, Indiranagar
Bangalore, 560008 India
(91) 80-528-1461
[email protected]
Neil Weste
Macquarie Univ.
Electronics Dept.
Sydney, 2109 Australia
(61) 2-850-9149
[email protected]
Janusz Rajski
Mentor Graphics Corp.
8005 SW Boeckman Rd.
Wilsonville, OR 97070-7777
(503) 685-4797
[email protected]
Richard Smith
5215 N. O'Connor Rd., Ste. 1000
Irving, TX 75039
(972) 889-0033
[email protected]
James A. Rowson
Alta Group of
555 N. Matilda Ave.
Sunnyvale, CA 94086
(408) 523-4157
[email protected]
Vivek Tiwari
Intel Corp.
2200 Mission College Blvd.
MS-RN 5-09
Santa Clara, CA 95052-8119
(408) 765-0589
[email protected]
Andrew T. Yang
Univ. of Washington
Dept. of EE, FT-10
Seattle, WA 98195
(206) 543-2932
[email protected]
Kenji Yoshida
Toshiba Corp.
580-1 Horikawa-Cho Saiwai-ku
Kawasaki, 210 Japan
(81) 44 548 2400
[email protected]
Yervant Zorian
LogicVision, Inc.
101 Metro Dr., Third Fl.
San Jose, CA 95110
(408) 453-0146
[email protected]
panel sub-committee
Nanette Collins
Consultant
Boston, MA 02115
(617) 437-1822
[email protected]
Takahide Inoue
Sony Corp.
530 Cottonwood Dr.
Milpitas, CA 95035
(408) 955-4279
[email protected]
Andrew B. Kahng
Univ. of California
Dept. of CS, 3713 Boelter Hall
Los Angeles, CA 90024-1596
(310) 206-7073
[email protected]
Mike Murray
Acuson
1220 Charleston Rd.
MS L-1, Box 7393
(415) 694-5876
[email protected]
design contest review committee
Bryan D. Ackland
Lucent Technologies
Rm. 4E 508
(908) 949-7248
[email protected]
David T. Blaauw
Motorola, Inc.
Advanced Design Tech.
Bridgepoint, Plaza 1
5918 W. Crtyrd. Dr., Ste. 330
Austin, TX 78730
(512) 794-4356
[email protected]
52
Ivo Bolsens
IMEC
VSDM, Kapeldreef 75
Leuven, BE B-3001 Belgium
(32) 16-281-211
[email protected]
Mary Jane Irwin
Penn State Univ.
Dept. of CS and Engr.
220 Pond Lab.
University Park, PA
16802-6106
(814) 865-1802
[email protected]
Teresa Meng
Stanford Univ.
Bldg. 301
Stanford, CA 94028
(415) 725-3636
[email protected]
Vivek Tiwari
Intel Corp.
2200 Mission College Blvd.
MS-RN 5-09
Santa Clara, CA 95052-8119
(408) 765-0589
[email protected]
d
ac
DAC executive committee
GENERAL CHAIR
Basant R. Chawla
Lucent Technologies
283 King George Rd.
E4D43
Warren, NJ 07059
(908) 559-5281
[email protected]
VICE CHAIR
Mary Jane Irwin
Penn State Univ.
Dept. of CS and Engr.
220 Pond Lab.
University Park, PA
16802-6106
(814) 865-1802
[email protected]
FINANCE CHAIR
Giovanni De Micheli
Stanford Univ.
Gates Computer
Science Bldg.
Rm. 333
Stanford, CA 94305-9030
(650) 725-3632
[email protected]
TECHNICAL PROGRAM
CO-CHAIR, DESIGN TOOLS
Randal E. Bryant
School of CS
(412) 268-8821
[email protected]
TECHNICAL PROGRAM
CO-CHAIR, DESIGN METHODS
Jan M. Rabaey
Univ. of California
Dept. of EECS
511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
[email protected]
EDA INDUSTRY CHAIR
Thomas P. Pennino
Lucent Technologies,
Bell Labs.
Rm. 1M-415
Holmdel, NJ 07733
(732) 949-7340
[email protected]
ELECTRONIC MEDIA
CHAIR
Michael Lorenzetti
(503) 685-0740
[email protected]
TUTORIAL CHAIR
Antun Domic
Synopsys, Inc.
(650) 943-5088
[email protected]
PUBLICITY CHAIR
Abbie Kendall
OrCAD
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
[email protected]
ELECTRONIC SYSTEMS
INDUSTRY CHAIR
Bryan D. Ackland
Lucent Technologies
101 Crawfords Corners Rd.
Rm. 4E-508
(732) 949-7248
[email protected]
PAST CHAIR
Ellen J. Yoffa
IBM Corp.
T.J. Watson Research Ctr.
Rm. 33-109, P.O. Box 218
10598
(914) 945-3270
[email protected]
EUROPE/MIDDLE EAST
REPRESENTATIVE
Gerry Musgrave
Brunel Univ.
Dept. of EEE
Uxbridge, UB8 3PH, UK
(44) 1-895-203-251
gerry.musgrave@
brunel.ac.uk
ASIA/INDIA/S. PACIFIC
REPRESENTATIVE
Fumiyasu Hirose
Fujitsu Labs. Ltd.
CAD Lab.
4-1-1 Kamikodanaka
Nakahara-ku
Kawasaki 211, Japan
(81) 44-754-2663
[email protected]
ACM REPRESENTATIVE
James Cohoon
Univ. of Virginia
Dept. of Computer Science
Olsson Hall
Charlottesville, VA 22903
(804) 982-2210
[email protected]
IEEE-CAS REPRESENTATIVE
Michael Lightner
Univ. of Colorado
Dept. of ECE
Campus Box 425
Boulder, CO 80309-0425
(303) 492-5180
[email protected]
EDAC REPRESENTATIVE
Lorie Bowlby
111 W. St. John St.
Ste. 200
San Jose, CA 95123-1104
(408) 226-7240
[email protected]
EXHIBIT MANAGER
Marie R. Pistilli
MP Associates, Inc.
Boulder, CO 80301
(303) 530-4562
[email protected]
CONFERENCE MANAGER
P.O. Pistilli
MP Associates, Inc.
Boulder, CO 80301
(303) 530-4562
[email protected]
53
Moscone
Center
Floorplan
54
Moscone
Center
Floorplan
55
Exhibit Floor
Center Map
56
Exhibit Floor
Center Map
57
SILICON VILLAGE VENDOR INDEX
Exhibit Floor
Center Map
PG 104
58
ACTEL CORP.
ALBA CENTRE (THE)
ALPINE MICROSYSTEMS INC.
CHIP EXPRESS CORP.
COREEL MICROSYSTEMS
DESIGN AND REUSE
IBM CORP.
INICORE
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, FPGA
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, PSS
QUICKLOGIC CORP.
RAPID
SILICON STRATEGIES
SIMPLE SILICON INC.
TEXAS INSTRUMENTS
VAUTOMATION INC.
WESTERN DESIGN CENTER, INC. (THE)
XILINX, INC.
SV18
SV28
SV2
SV26
SV27
SV32
SV23
SV38
SV11
SV1
SV15
SV14
SV39
SV8
SV5
SV6
SV12
SV21
SV16
SV22
SV4
SV37
SV36
SV13
SV17
SV25
SV31
SV10
SV20
SV35
SV19
Pacific
Numerix Ad
System
Science Ad
d
exhibitor listing
ac
The Design Automation Conference continues to combine its outstanding technical program with exhibits
featuring over 200 of the world’s top CAD/CAE companies. Exhibits are located in Halls A, B and C, and room
104 of the Moscone Center. We are pleased to have the following exhibitors this year.
COMPANY NAME
sv
sv
All Companies
in BOLD are
NEW DAC
Exhibitors
sv
sv
sv
sv
denotes
silicon
village
exhibitor
sv
sv
Children under 14
will not be allowed
in the Exhibit Hall.
sv
sv
BOOTH #
0-IN DESIGN AUTOMATION
1434
ABSTRACT INC.
1346
ACCEL TECHNOLOGIES, INC.
812
ACEO TECHNOLOGY, INC.
1842
ACTEL CORP.
SV18
SV28
ADVANCED TECHNOLOGY CENTER, COVERMETER DIVISION 556
ALBA CENTRE (THE)
SV2
ALDEC, INC.
1222
ALPINE MICROSYSTEMS, INC.
SV26
ALTERA CORP.
118
ALTERNATIVE SYSTEM CONCEPTS, INC.
2250
AMBIT DESIGN SYSTEMS, INC.
300
SV27
ANALOGY, INC.
944
ANASIFT TECHNOLOGY INC.
12
ANSOFT CORP.
930
APPLIED SIMULATION TECHNOLOGY
923
APTIX CORP.
2042
ARCADIA DESIGN SYSTEMS, INC.
2318
ARGONAUT RISC CORES INC.
2332
ARISTO TECHNOLOGY
80
ARTISAN COMPONENTS, INC.
1336
ARTWORK CONVERSION SOFTWARE, INC.
1254
ASPEC TECHNOLOGY, INC.
2340
ATG TECHNOLOGY
1854
AUSPY DEVELOPMENT INC.
10
AUTOMATA DESIGN, INC.
1554
AVANT! CORP.
1308 & 1718
AXIS SYSTEMS
1640
BTA TECHNOLOGY, INC.
109
CAD-MIGOS SOFTWARE TOOLS, INC.
1638
CADABRA
1442
CADENCE DESIGN SYSTEMS, INC.
1508
CAE PLUS, INC.
212
CAHNERS BUSINESS INFORMATION
808
CAST, INC.
1652
CHINA INTEGRATED CIRCUIT DESIGN CENTER
18
CHIP EXPRESS CORP.
SV32
CHRONOLOGY CORP.
744
CHRYSALIS SYMBOLIC DESIGN
844
CIRCUIT SEMANTICS, INC.
81
COMPAQ COMPUTER CORP.
2118
COMPILOGIC CORP.
67
COMPUTER DESIGN
1550
COMSYSTEMS INTEGRA, INC.
449
CONCURRENT CAE SOLUTIONS, INC.
1152
COREEL MICROSYSTEMS
SV23
COWARE, INC.
65
CSELT SPA
2542
344
SV38
DENALI SOFTWARE, INC.
428
DERIVATION SYSTEMS, INC.
1542
DESIGN ACCELERATION
818
DESIGN AND REUSE
SV11
sv
sv
sv
sv
sv
COMPANY NAME
BOOTH #
DESIGNSOFT
15
DUET TECHNOLOGIES
1418
DYNACHIP CORP.
21
ECN MAGAZINE/EITD
1538
EDA STANDARDS
438
EE TIMES/EDTN/CMP MEDIA
1518
ELECTRONIC TOOLS CO.
1934
ENGINEERING DATAXPRESS, INC.
825
EONIC SYSTEMS INC.
754
ESCALADE CORP.
128
ESPERAN
252
EVEREST DESIGN AUTOMATION
2538
EXEMPLAR LOGIC
318
FINTRONIC USA, INC.
1524
FORMALIZED DESIGN INC.
78
FREQUENCY TECHNOLOGY, INC.
2200
FRONTIER DESIGN
62
FTL SYSTEMS, INC.
256
FUJITSU/ICL
328
GAMBIT AUTOMATED DESIGN, INC.
544
GATEFIELD CORP.
908
GDA TECHNOLOGIES, INC.
2532
GENESYS TESTWARE
1154
GENIAS SOFTWARE GMBH
154
GLOBETROTTER SOFTWARE, INC.
139
HEWLETT - PACKARD CO.
1530
HYPERLYNX
632
IBM CORP.
1318
IBM CORP.
SV1
IKOS SYSTEMS INC.
1328
INCASES NORTH AMERICA
636
INFOQUICK
88
INICORE
SV15
INTEGRATED INTELLECTUAL PROPERTY INC.
656
SV14
INTEGRATED SYSTEM DESIGN
1050
INTELLITECH CORP.
1350
INTELLX
956
INTERACTIVE IMAGE TECHNOLOGIES LTD.
1930
INTERCEPT TECHNOLOGY INC.
1752
INTERHDL, INC.
1918
INT’L COMPUTEX INC./INFO. HANDLING SERVICES
64
INTERRA, INC.
1546
INTRINSIX CORP.
2528
INTUSOFT
141
K2 TECHNOLOGIES/SHEARWATER GROUP
2308
KLUWER ACADEMIC PUBLISHERS
926
SV39
LEDA SA
445
LEGEND DESIGN TECHNOLOGY, INC.
752
LIBRARY TECHNOLOGIES, INC.
2150
1156
SV8
LINIUS TECHNOLOGIES
444
LOGICVISION, INC.
218
LSI LOGIC CORP.
536
61
d
exhibitor listing (cont.)
ac
COMPANY NAME
sv
sv
All Companies
in BOLD are
NEW DAC
Exhibitors
sv
sv
sv
sv
sv
sv
denotes
silicon
village
exhibitor
sv
sv
Children under 14
will not be allowed
in the Exhibit Hall.
62
sv
sv
BOOTH #
LUCENT TECHNOLOGIES, BELL LABS DA
LUCENT TECH., MICROELECTRONICS GROUP, FPGA
LUCENT TECH., MICROELECTRONICS GROUP, PSS
MENTOR GRAPHICS CORP.
MICROCODE ENGINEERING INC.
MICROMAGIC, INC.
MINC/SYNARIO
MODEL TECHNOLOGY, INC.
MORGAN KAUFMANN PUBLISHERS, INC.
MORPHOLOGIC, INC.
MOSCAPE INC.
MYCAD, INC.
NOVAS SOFTWARE, INC.
NU THENA SYSTEMS, INC.
NUMERICAL TECHNOLOGIES, INC.
NURLOGIC DESIGN, INC.
OEA INTERNATIONAL, INC.
OMNIVIEW DESIGN, INC.
OPEN VERILOG INTERNATIONAL (OVI)
OPMAXX, INC.
OPTEM ENGINEERING INC.
ORCAD
PACIFIC NUMERIX CORP.
PADS SOFTWARE, INC.
PALMCHIP CORP.
PENTON PUBLISHING
PHOENIX TECHNOLOGIES LTD., VIRTUAL CHIPS
PINEBUSH TECHNOLOGIES, INC.
PLATFORM COMPUTING CORP.
PRENTICE HALL-PTR
PRINTED CIRCUIT DESIGN MAG., MILLER FREEMAN, INC.
PROVIS CORP.
QUICKLOGIC CORP.
QUICKLOGIC CORP.
QUICKTURN DESIGN SYSTEMS, INC.
RAPID
RELAY DESIGN AUTOMATION
RUBICAD CORP.
RUNTIME DESIGN AUTOMATION
SAGANTEC
SAND MICROELECTRONICS
SANDSTROM ENGINEERING
SAPIEN DESIGN
SENTE INC.
SES INC.
SEVA TECHNOLOGIES, INC.
SICAN MICROELECTRONICS CORP.
SILICON ACCESS INC.
SILICON FOREST RESEARCH
SILICON INTEGRATION INITIATIVE, INC. (SI2)
SILICON STRATEGIES
SILICON VALLEY RESEARCH, INC.
SILVACO INTERNATIONAL
SIMPLE SILICON INC.
SIMPLEX SOLUTIONS, INC.
1008
SV5
SV6
1108
348
93
1824
1830
2530
552
22
2030
SV12
23
1850
96
16
2034
530
1540
338
1522
1018
228
630
20
822
SV21
1846
936
SV16
1700
827
451
84
736
SV22
2108
SV4
448
2000
452
518
1450
2546
349
SV37
208
1622
1654
453
SV36
108
68
918
SV13
1730
127
SV17
644
COMPANY NAME
sv
sv
sv
sv
sv
sv
SIMPOD, INC.
SIMUCAD, INC.
SIMUTEST, INC.
SNAKETECH
SPECTRA LOGIC
STANZA SYSTEMS, INC.
SUMMIT DESIGN, INC.
SUN MICROSYSTEMS
SYCON DESIGN, INC.
SYNAPTICAD INC.
SYNCHRONICITY INC.
SYNOPSYS, INC.
SYNPLICITY, INC.
SYNTEST TECHNOLOGIES, INC.
SYNTYX TECHNOLOGY
SYSTEMS SCIENCE, INC.
TANNER EDA
TAU SIMULATION INC.
TEMENTO SYSTEMS
TERA SYSTEMS, INC.
TERADYNE, INC.
TEXAS INSTRUMENTS
TIMBERWOLF SYSTEMS, INC.
TIME-ROVER INC.
TOPDOWN DESIGN SOLUTIONS, INC.
TRANSCENDENT DESIGN TECHNOLOGY, INC.
TRANSEDA, INC.
TRANSLOGIC USA CORP.
TSA
TSSI
ULTIMA INTERCONNECT TECHNOLOGY
UNIFIED DESIGN AUTOMATION, INC.
UNIVERSITY BOOTH
VALOR COMPUTERIZED SYSTEMS
VAMP, INC.
VANTIS
VAUTOMATION INC.
VERIBEST, INC.
VERISITY DESIGN, INC.
VERITOOLS, INC.
VERPLEX SYSTEMS, INC.
VERYSYS DESIGN AUTOMATION, INC.
VIEWLOGIC SYSTEMS, INC.
VIRAGE LOGIC
VIRTUAL SILICON TECHNOLOGY, INC.
VSI ALLIANCE
WESTERN DESIGN CENTER, INC. (THE)
X-TEK CORP.
XENTEC INC.
XILINX, INC.
XILINX, INC.
XYNETIX DESIGN SYSTEMS, INC.
YOKOGAWA ELECTRIC CORP.
ZUKEN-REDAC, INC.
ZYCAD TSS CORP.
BOOTH #
2534
1122
1624
1054
1118
19
1808
618
950
90
1800
2130
1742
1646
91
1218
1600
11
94
145
152
SV25
824
13
2350
SV31
86
233
2518
925
2300
144
850
SV10
830
24
87
236
SV20
608
600
1818
151
100
1428
244
1354
115
SV35
2522
153
508
SV19
730
2052
308
77
interHDL Ad
1/2 page
Silicon
Village
1/2 page
Ad
Electronic
Tools
m
onday, june 15
Time
Rm 102
exhibitor presentations
Rm 103
Rm 301
Rm 304
11:00
QUICKTURN DESIGN APPLIED SIMULATION
VIRAGE LOGIC
MORPHOLOGIC, INC.
SYSTEMS, INC.
TECHNOLOGY
ADVANCED TECH.
LUCENT TECH.,
PHOENIX
SIMUTEST, INC.
CENTER
BELL LABS DA
TECHNOLOGIES LTD.
ACEO
ASPEC
AVANT! CORP.
SES INC.
TECHNOLOGY, INC.
TECHNOLOGY, INC.
SYNTEST
DESIGN
LATTICE
TERA SYSTEMS, INC.
TECHNOLOGIES, INC.
ACCELERATION
SEMICONDUCTOR
DUET
ENGINEERING
ESCALADE CORP.
XILINX, INC.
TECHNOLOGIES
DATA XPRESS, INC.
DENALI SOFTWARE, MENTOR GRAPHICS
SICAN MICROSYNPLICITY, INC.
INC.
CORP.
ELECRONICS CORP.
SYNCHRONICITY
ELECTRONIC
ZUKEN-REDAC, INC.
RUBICAD CORP.
INC.
TOOLS CO.
11:20
TEMENTO SYSTEMS
ORCAD
CADABRA
11:40
LEDA SA
EXEMPLAR
LOGIC, INC.
EONIC
SYSTEMS INC.
Rm 102
Rm 103
9:00
9:20
9:40
10:00
10:20
10:40
Exhibit hours 10:00am - 6:00pm
Rm 305
IBM CORP.
GATEFIELD CORP.
INTERHDL, INC.
FREQUENCY
TECHNOLOGY, INC.
VIEWLOGIC
SYSTEMS, INC.
MINC/SYNARIO
Rm 306
PLATFORM
COMPUTING CORP.
XYNETIX DESIGN
SYSTEMS, INC.
ULTIMA
INTERCONNECT
SENTE INC.
CHRYSALIS
SYMBOLIC DESIGN
YOKAGAWA
ELECTRIC CORP.
SYSTEMS
SCIENCE, INC.
VERITOOLS, INC.
VAUTOMATION INC.
CAE PLUS, INC.
EVEREST DESIGN
AUTOMATION
LINIUS
TECHNOLOGIES
0-IN DESIGN
AUTOMATION
TANNER EDA
Rm 305
Rm 306
12:00 – 2:00 LUNCH BREAK
2:00
ATG TECHNOLOGY
3:40
SILVACO
INTERNATIONAL
OMNIVIEW DESIGN,
INC.
LEGEND DESIGN
TECHNOLOGY, INC.
DERIVATION
SYSTEMS, INC.
K2 TECH./
SHEARWATER
4:00
FTL SYSTEMS, INC.
4:20
CAST, INC.
4:40
ALTERA CORP.
5:00
SNAKETECH
5:20
INTRINSIX CORP.
5:40
NU THENA
SYSTEMS, INC.
6:00
MOSCAPE INC.
2:20
2:40
3:00
3:20
Rm 301
Rm 304
CADENCE DESIGN
ARCADIA DESIGN
GENESYS
SUMMIT DESIGN,
APTIX CORP.
SYSTEMS, INC.
SYSTEMS, INC.
TESTWARE
INC.
SILICON INTEGRATION
SEVA
PADS SOFTWARE,
ESPERAN
DYNACHIP CORP.
INITIATIVE, INC. (Si2) TECHNOLOGIES, INC.
INC.
AMBIT DESIGN
TIMBERWOLF
VERYSYS DESIGN
MODEL
SIMUCAD, INC.
SYSTEMS, INC.
SYSTEMS, INC.
AUTOMATION, INC.
TECHNOLOGY, INC.
OPTEM
CAD-MIGOS
CHRONOLOGY
SYNOPSYS, INC.
TRANSEDA, INC.
ENGINEERING INC.
SOFTWARE TOOLS
CORP.
SIMPLEX
NOVAS SOFTWARE,
CYPRESS
HYPERLYNX
SAPIEN DESIGN
SOLUTIONS, INC.
INC.
SEMICONDUCTOR
SILICON VALLEY
ARTISAN
INTERCEPT
SIDSA
ANSOFT CORP.
RESEARCH, INC.
COMPONENTS, INC.
TECHNOLOGY INC.
COMPAQ COMPUTER VERISITY DESIGN,
FINTRONIC USA, INC. LOGICVISION, INC.
FUJITSU/ICL
CORP.
INC.
OEA INTERNATIONAL, TOPDOWN DESIGN
GLOBETROTTER
ABSTRACT INC.
AXIS SYSTEMS
INC.
SOLUTIONS, INC.
SOFTWARE, INC.
LIBRARY
GAMBIT AUTOMATED
ACCEL
ANALOGY, INC.
OPMAXX, INC.
TECHNOLOGIES, INC.
DESIGN, INC.
TECHNOLOGIES, INC.
SUN
INTEG. INTELL.
CIRCUIT
INTERRA, INC.
QUICKLOGIC CORP.
MICROSYSTEMS
PROPERTY INC.
SEMANTICS, INC.
CHIP EXPRESS
VERIBEST, INC.
EDA STANDARDS
SIMPOD, INC.
IKOS SYSTEMS INC.
CORP.
VIRTUAL SILICON
ALTERNATIVE SYS.
SAGANTEC
INTELLITECH CORP.
SPECTRA LOGIC
TECHNOLOGY, INC.
CONCEPTS, INC.
ARISTO
SAND M I C R O TOWER
TRANSLOGIC
COWARE, INC.
TECHNOLOGY
ELECTRONICS, INC.
SEMICONDUCTOR
USA CORP.
These 20-minute presentations by DAC Exhibitors are intended to efficiently introduce you to new product and application information.
Badges are not required for admission to the Exhibitor Presentations.
65
Advance
Tech. Ad
m
9:00
am
onday
Virage Logic
rm. 102
Learn how to rapidly design high quality embedded memories and integrate them into a system on
chip.  A new generation of memory compilers create highly optimized low power and high speed
memories, taking full advantage of deep submicron design.
Quickturn Design Systems, Inc.
rm. 103
Quickturn, the leader in design verification, unveils its newest products suite aimed at complex chips
and systems resulting from deep submicron and system-on-chip. These products are based on the
latest emulation and simulation technology, offering unprecedented performance and ease-of-use.
Applied Simulation Technology
rm. 301
Applied Simulation Technology offers leading edge software solutions for high speed digital and analog
circuits and systems. Parasitic extraction and simulation of the physical interconnects for Signal
Integrity and EMI analysis is the company focus.
Morphologic, Inc.
rm. 304
Morphologic will demonstrate Evolution: a multi-device, multi-vendor FPGA design tool set. See how
Evolution’s combination of requirements tracking, floorplanning, and data base management yield
deterministic, repeatable results that set the stage for a complete route on the first pass.
IBM Corp.
rm. 305
Exciting solutions ranging from IBM Blue Logic technology to Deep Blue to e-commerce will give you a
competitive advantage.
Platform Computing Corp.
rm. 306
9:20
am
LSF enables design and simulation engineers to fully utilize their computing resources to significantly
shorten design cycles, reduce time to market, and improve product quality by completing more design
iterations in less time. Platform’s LSF Suite has helped design engineers derive maximum advantage
from distributed computing environments.
Advanced Technology Center, CoverMeter Division
rm. 102
CoverMeter is a complete Verilog code coverage analysis tool that helps designers determine which
portions of application code have yet to be exercised in simulation test cases. CoverMeter offers
facilities to assure coverage of statements, conditions, toggles and state machines.
Lucent Technologies, Bell Labs Design Automation
rm. 103
Running out of time to verify your systems-on-silicon? We can help you glide through your next design
project with leading-edge standards-based tools and technologies supporting formal verification, mixedsignal design and DSM parasitic extraction. Look to us for solutions to your toughest verification problems.
Phoenix Technologies Ltd., Virtual Chips
rm. 301
At Phoenix our experience is your advantage. We now offer immediate availability on hundreds of
Virtual Components™ for 1394, USB, AGP, IrDA and PCI standards. Our silicon-proven synthesizable
cores, extensive verification environments, and firmware are 100% compliant with the standards and
backed by over 800 Phoenix employees worldwide.
67
m
onday
Simutest, Inc.
rm. 304
Simutest presents WaveTools a simulation analysis and test program generation tool used to create
test benches and to display, edit, compare and analyze simulation vectors. WaveTools can also import
simulation vectors and automatically generate and verify test programs for test systems.
GateField Corp.
rm. 305
Looking for the ideal, reprogrammable ASIC solution? GateField is excited to introduce a paradigm
shift in programmable logic technology based on a .25µ embedded FLASH process. GateField’s
ProASIC™ capabilities enable reprogrammable system-on-a-chip solutions that set new
price/performance standards in the PLD market.
Xynetix Design Systems, Inc.
rm. 306
9:40
am
“...getting signals in the GHz frequency range off-chip and into the system after packaging is perhaps
even greater than the challenge of on-chip performance.” (SIARoadmap). Xynetix discusses tools and
techniques for IC packaging and PCB design to optimize overall system performance.
ACEO Technology, Inc.
rm. 102
See the most advanced ASIC design technology featuring One-Pass Hierarchical Synthesis™ for high
performance single pass synthesis with industry leading gate-count optimization and timing. The next
generation of ASIC design debuts with Layout Driven Synthesis for the most accurate interconnect
modeling.
Avant! Corp.
rm. 103
Avant! will present its newest additions to its suite of TCAD-to-ECAD solutions including, advances in
symbolic layout editing and top level routing, crosstalk analysis, VDSM place and route and its
Milkyway database.
ASPEC Technology, Inc.
rm. 301
Aspec’s Semiconductor Intellectual Property (SIP) library services help accelerate design-to-fabrication
time for complex ICs. Aspec provides physical IP, design workflows, design automation tools and
design services to reduce the time and costs for bringing deep sub-micron designs to silicon
fabrication.
SES Inc.
rm. 304
The Intel® Portable Simulation Initiative (PSI) is an Intel-led group of companies which share
performance models of components of Intel architecture servers. The PSI uses SES/workbench®
technology. This presentation discusses the PSI and another initiative in the Fibre Channel community.
interHDL, Inc.
rm. 305
The leader in HDL analysis presents advanced verification capabilities such as: clock domain analysis,
asynchronous loop detection, power analysis, and code purification. Synopsys and interHDL partnering
to enable automatic verification and compliance to the Design Reuse Methodology as specified in the
Synopsys-Mentor Reuse Methodology Manual.
Ultima Interconnect Technology
rm. 306
To account for coupling noise and power net IR drop/rise, our already best-in-the-class delay calculator
integrated with newly introduced 3D net parasitic extractor provides a critical link in DSM cell-based
IC design flow.
68
m
10:00
am
onday
SynTest Technologies, Inc.
rm. 102
SynTest provides high performance test and verification tools and services for improving ASIC quality.
Tools include the industry’s fastest fault simulation (TurboFault), verify RTL testability analysis, scan
synthesis, ATPG, boundary scan, memory BIST and core test. Services combine these tools with
SynTest engineering, allowing for high level of quality and testability.
Design Acceleration
rm. 103
Discuss product line updates. DAI Signalscan DX, the highest performance/capacity waveform viewing
and source code debugging tool for digital/analog simulators; DAI Coverscan a Verilog verification
coverage analysis tool, DAI Comparescan, a rules-based analysis program, and DAI SST2 Database,
a high-performance simulation database with TurboCompression.
Lattice Semiconductor Corp.
rm. 301
Lattice Semiconductor Corporation, the leader in ISP™ technology, is driving design tools and CPLD
densities in excess of 1000 macrocells. The focus of this presentation is on high performance ispLSI ®
devices and Lattice’s complete ispHDL™ tools solution.
Tera Systems, Inc.
rm. 304
Tera Systems unveils TeraForm™, the revolutionary RTL design-planning system that solves your deepsubmicron-IC timing convergence and complexity problems. TeraForm automates structured-ASIC
design, delivering the density and performance benefits of hierarchical, structured-custom chips while
maintaining the productivity and turn-around-time benefits of traditional ASIC design.
Frequency Technology, Inc.
rm. 305
Frequency Technology blends CAD tools and process physics to help you break the Interconnect
Barrier. Columbus Parasitic Extractor is unsurpassed in accuracy. Our, Interconnect Performance
Characterization service enhances accuracy by creating Verified Interconnect Performance
Parameters, VIPPs, which accurately predict the electrical behavior of interconnects.
Sente Inc.
rm. 306
10:20
am
Sente is the IC Power expert, with tools and consulting to identify power problems, and eliminate
them. Sente technology rapidly analyzes Architectural-level Verilog HDL or VHDL before synthesis and
produces accurate, detailed full-chip power estimates for deep submicron design.
Escalade Corp.
rm. 102
Escalade introduces an IP protection product, IP Guard, that provides unbreakable protection for
popular VHDL and Verilog simulators. IP Guard is the only multi-language input tool that generates
VHDL, Verilog, and C. It complements Escalades’s DesignBook and DesignExplorer products to create
a complete IP authoring environment.
Xilinx, Inc.
rm. 103
There is only one answer to the digital design challenge: Software-enabled high-level design flows that yield
high-density, high-performance results for field programmable and ASIC devices. This software, integrated
with sub-micron silicon, is available today. Rich Sevcik will present an overview of the Xilinx solution.
Duet Technologies
rm. 301
Duet provides state-of-the-art semiconductor IP infrastructure components including high performance
IC physical libraries (standard cells, I/O cells, and memory compilers) and comprehensive IP services
including custom library development, library migration, EDA tool integration and validation, IP silicon
verification services, and system-on-chip test services.
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Engineering DataXpress, Inc.
rm. 304
Focus your attention on having DataXpress solve your interoperability needs. We provide solutions for
schematic, netlist, HDL, PCB/MCM layout design data, EDIF 2 0 0, 3 0 0, 4 0 0, Verilog, VHDL and
most EDA vendors. We offer data translators, translator development environments, conversion
services, outsourcing services, etc.
VIEWlogic Systems, Inc.
rm. 305
Focused on the Systems Designer, providing the industry’s hottest engineering tools and solutions for
high-speed system design; system simulation and analog design; language-based FPGA design
environments; and Internet-based enterprise solutions for design re-use. Available on UNIX and NT.
Chrysalis Symbolic Design, Inc.
rm. 306
10:40
am
The Formal Design Company™ - Design VERIFYer® is the industry standard formal equivalence
checking software. Design INSIGHT® is the practical model checking solution for design engineers.
Chrysalis delivers a complete family of formal tools, in use by 75 customers at 100+ sites worldwide.
Denali Software, Inc.
rm. 102
With over 1000 licenses sold, Denali Software offers the industry-leading memory simulation solution for
authoring, publishing and verifying memory models of both discrete and embedded memory components.
Denali proudly announces its enhanced technology for verifying memory subsystems and controllers.
rm. 103
Mentor Graphics is a technology leader in deep submicron design, providing the tools and
methodologies designers need to meet the challenges of system verification and intellectual property.
Synplicity, Inc.
rm. 301
Synplicity will discuss methodologies for high-density FPGA and CPLD design.
SICAN Microelectronics Corp.
rm. 304
Learn about SICAN’s latest DesignObjects™ and design service solutions. Synthesizable ASIC cores
combined with SICAN’s abundant and highly skilled engineering resources enable its customers to meet
today’s market requirements and to focus scarce internal resources on areas of highest added-value.
MINC/Synario
rm. 305
MINC/Synario offers a complete line of schematic capture, logic synthesis, and simulation tools for
programmable logic and board design. This tightly integrated tool suite provides a complete design
environment for FPGAs, CPLDs, and PLDs. MINC’s broad product line answers the needs of any budget
or environment.
Yokogawa Electric Corp.
rm. 306
11:00
am
70
VirtualICE™ is a hardware/software co-design tool that reduces development time and ASIC respins.
VirtualICE enables you to solve the problems across the boundaries of hardware and software. VMlink
(Verilog-MATLAB interface) provides new design methodology of digital signal processing system.
Synchronicity Inc.
rm. 102
Synchronicity delivers on the promise of better project management and design reuse with
ProjectSync®, a web-based project issue tracking and communications infrastructure. Synchronicity
will present a description of this revolutionary new technology and how it can be used with
Synchronicity’s DesignSync™ product to deliver design reuse infrastructures.
Synplicity, Inc. Ad
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Zuken-Redac, Inc.
rm. 103
The challenges of time-to-market, quality expectation, and product complexity require alternative
approaches to electronic design. Through the provision of exciting new solutions, Zuken-Redac is
helping companies change the way they design, and bring innovative new products rapidly into the
market.
RUBICAD Corp.
rm. 301
LACE is the only IC Layout Conversion Environment that allows hierarchical layout migration for design
reuse in systems-on-a-chip in deep-submicron technologies.
Electronic Tools Co.
rm. 304
Learn about our IP exchange solutions. ETC provides solutions for schematic, netlist, PCB/MCM
design data. We use standards like EDIF, Verilog, VHDL, and GENCAM to provide smooth migration,
interoperability, archiving and IP transfer from CAD to CAD and CAD to CAM.
Systems Science, Inc.
rm. 305
INTRODUCING VERA-SV! System Science will present the latest verification and test solutions. VERASV™ is a powerful solution for complete system verification that offers automated stimulus generation
with dynamic coverage feedback, self-checking tests, and hardware and software coverification in a
single environment.
Veritools, Inc.
rm. 306
11:20
am
Veritools has the most powerful productivity tools in the world. Veritools’ waveform analysis program,
Undertow, views digital and analog simulation output from Verilog, TIMEMILL, POWERMILL, HSpice,
Anagram and a variety of VHDL simulators.
Temento Systems
rm. 102
Visit Temento Systems’ exhibit to hear about Diatem, the First ES Design and Test Platform on the
market. From DFT insertion to prototype debug you will learn during the presentation how to reduce
your test time and improve your design methodology.
OrCAD
rm. 103
Make your design process a competitive advantage with OrCAD. Join us for an overview on our new
9.0 Release of NT applications for Internet-enabled component information management; FPGA/CPLD
and PCB system design; analog and mixed-signal design; and PCB layout.
Cadabra
rm. 301
CADABRA provides physical synthesis tools to automate the transistor level layout of standard cell,
gate array cells, and IO cell libraries as well as full and semi-custom macros.
VAutomation Inc.
rm. 304
VAutomation, one of the first companies to recognize the need for re-usable IP when designing
complex ICs, provides synthesizable cores for popular microprocessors (e.g. 8086) and serial
communications controllers (e.g. USB). Its silicon-proven cores shorten development time and enable
system-on-chip integration.
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CAE Plus, Inc.
rm. 305
Come see how Toshiba, NEC, and Motorola are designing their next-generation embedded system-ona-chip ICs using CAE Plus Tools. RTL-accurate ‘C’ models, automatically synthesized from CAE Plus’
ArchGen™ tool, enable early functional and performance verification of control-intensive system ICs.
Everest Design Automation
rm. 306
11:40
am
Everest Design Automation’s first product, a gridless, hierarchical routing and floorplanning system,
is more than an order of magnitude faster than current gridless routers. An innovative approach
enables accurate pin assignment and over the block routing, reducing chip area and wire length.
LEDA SA
rm. 102
LEDA offers complete compilation and elaboration solutions for VHDL’87/93. VHDL-AMS and Verilog,
and designer tools such as its new VHDL Programmable Design Rule Checker (Proton), a VHDL
source-to-source encryptor (Krypton), and a VHDL/Verilog Source and Library Manager (VHDL*Verilog
Design Studio).
Exemplar Logic
rm. 103
Spectrum blends the industries hottest design creation, simulation, synthesis and implementation
technology into a simple, seamless process designed to do the same job as you - design an FPGA or
ASIC. Come see What FlowTabs™ PowerTabs™, DesignInsight™, HDLIntegrator™, and much more.
Eonic Systems Inc.
rm. 301
Rapid movement towards flexible, programmable RISC ASIC and DSP cores for embedded applications
means time to market is now dominated by software application development. Eonic Systems
presents the Virtuoso™ v4.0 real-time operating system (RTOS) and tool set employing innovative
SoftStealth™ technology to satisfy this challenge.
Linius Technologies
rm. 304
Specialists in wire harness design automation. EMbassy is a 3-D virtual prototyping environment for
correct-by-construction wire harness design and manufacture. EMbassy combines 2-D logical connectivity
and 3-D mechanical data using industry standard file formats, including EDIF, VRML, and IGES.
0-In Design Automation
rm. 305
0-In’s white-box verification zeros-in on corner cases where bugs like to hide. It’s fast, efficient, and
extremely thorough—without design, testbench, or simulation changes. Find out how 0-In is turning
verification inside-out to find the world’s toughest bugs!
Tanner EDA
rm. 306
2:00
pm
74
Tanner EDA offers feature-rich, easy-to-use physical design and verification tools for analog and mixedsignal ICs. With Windows® platforms at Windows® prices you can afford to put a powerful tool suite
on the desk of every member of your design team.
ATG Technology
rm. 102
Presenting Designer Friendly Test. INTELLECT, the industry’s most powerful sequential ATPG tool,
offers flexible and easy-to-use solutions for full, partial and no-scan design. Consistently outperforms
all others with higher coverage and simpler design integration. Technology, comparisons and results
will be discussed.
Escalade Ad
EE Times Ad
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rm. 103
The rapid evolution to system-on-a-chip (SOC) is forcing the convergence of systems, IC, and mixedsignal design. Cadence Design Systems, Inc. will discuss its most recent product announcements in
each of these areas and the resulting impact on SOC methodologies.
Arcadia Design Systems, Inc.
rm. 301
Arcadia Design Systems presents Mustang Datapath Placement Engine with breakthrough technology
for increasing chip performance. An overview of Mustang’s innovative approach to optimizing datapath
will be given. The presentation will describe how Mustang integrates into existing design flows and the
key features, functionality and benefits of Mustang.
Genesys Testware
rm. 304
Genesys Testware provides test solutions for systems on chip. TestCores™ provide BIST of embedded
memories (Memory BistCore™), BIST of on-chip logic (Logic BistCore™), and board testability and core
test integration (Boundary ScanCore™). New features include self-test and repair of embedded DRAMs
and FIFOs.
Summit Design, Inc.
rm. 305
Summit Design will discuss an extensive range of HDL-based solutions for verification, analysis, legacy
code reuse and capture. Supporting ASSP, ASIC and FPGA methodologies, Summit’s products include
Code Coverage, HW/SW Co-verification, Graphical Capture/Reuse, Legacy Code Management, and
Behavioral Synthesis.
Aptix Corp.
rm. 306
2:20
pm
Reconfigurable prototyping technology enables designers to build and verify entire systems at or near
actual speed. This is key for verification of systems based on audio, video and print quality, requiring
high performance verification that simulation cannot provide.
Silvaco International
rm. 102
Silvaco presents “TCAD-Driven-CAD” a unique solution for linking process technology to the sub
quarter micron design environment. Presented will be “Celebrity” - a set of powerful NT-based layout
and verification tools, “STORM” - technology driven parasitic interconnect extraction and “SmartSpice”
- a new standard in circuit simulation.
Silicon Integration Initiative, Inc. (Si2)
rm. 103
Si2 provides engineering consultation and services to industry-leading silicon, electronic systems, and
EDA companies for synergistic multi-company efforts focused on improving productivity and costs in
the design and production of integrated silicon systems. Si2 and over 25 companies, including the
EDA Industry Council, will present in-depth interoperability demonstrations.
SEVA Technologies, Inc.
rm. 301
SEVA Technologies now offers an evaluation service to assess new and existing Intellectual Property. Its
IP Evaluation Service helps designers assess which model is appropriate for a given design project —
system simulation, design in, synthesis or inclusion in an end product.
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Esperan
rm. 304
Antony Dennis will explain how Esperan’s VHDL and Verilog training courses can have a major impact
on productivity and design quality, by presenting the real world issues using real engineers who can
really teach.
PADS Software, Inc.
rm. 305
PADS presents PowerBGA, our universal solution for high density interconnect packaging. Power BGA
automates the interconnect process between bare die and its underlying substrate and supports COB,
BGA, CSP, and laminate-based MCM, as well as PCB design based on PADS-PowerPCB technology.
DynaChip Corp.
rm. 306
2:40
pm
DynaChip’s FPGAs remove the speed barriers from FPGA design. Short, predictable routing delays
enable system-level operation from 66 to 266 MHz. On-chip PLLs allow clock multiplication, division
and latency reduction, 8 ns dual-port RAM enables FIFO performance over 100 MHz and blinding fast
I/O feature selectable LV-TTL/GTL/PECL/LVDS levels.
Omniview Design, Inc.
rm. 102
Omniview Design, Inc. provides solutions to the problems of rapidly increasing design complexity and
shrinking product life cycles. Omniview products focus specifically on the problems of design reuse,
preservation of intellectual property and hardware/software performance analysis at the architectural
level.
Ambit Design Systems, Inc.
rm. 103
Looking for a synthesis alternative? Then look at Ambit. We’ll show you why our next-generation
synthesis tool has been successful at more than 40 customer sites, gained support from leading ASIC
vendors, and will help you design your next generation of technology.
Simucad, Inc.
rm. 301
SILOS HyperFault’s ultra-high performance fault simulation system supports Verilog HDL for fault
simulation at multiple levels of abstraction. HyperFault’s architecture incorporates an exclusive set
of performance enhancing utilities coupled with Distributed Multi-Pass Fault Simulation that provides
unsurpassed runtime performance.
TimberWolf Systems, Inc.
rm. 304
TimberWolf is a complete timing driven placement and routing tool that can be used to completely
place and route integrated circuits. See a demonstration of TimberWolf and how its newly completed
detailed routing package can help you with all your IC designs.
Verysys Design Automation, Inc.
rm. 305
The Formal Viewpoint. After a brief introduction to formal verification and its benefits, we will expound
on the ease with which such tools can be integrated into a standard design flow. The most appropriate
and effective use of model and equivalence checking will be then described with illustrative examples.
Model Technology, Inc.
rm. 306
ModelSim - The Ultimate Tool for HDL Simulation. Whether it is VHDL or Verilog, PCs or Unix
workstations, multi-million gate ASICs or mainstream FPGAs - come see why over 18,000 designers
have chosen ModelSim for their HDL simulation needs.
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Legend Design Technology, Inc.
rm. 102
To characterize IP designs efficiently, Legend Design Technology, Inc. provides the following EDA products:
GDS-Cut : layout reduction • SpiceCut : circuit reduction • RC-Cut : AWE-based RC reduction
The products are successfully used for characterizing both timing and power of memory designs.
Synopsys, Inc.
rm. 103
Synopsys’ CTO will discuss how Synopsys is attacking IC design barriers with state-of-the-art design
flows. These flows include Synopsys’ comprehensive verification tool suite that spans system-level,
hardware/software, functional, and nanometer IC design, plus advanced design implementation tools.
OptEM Engineering Inc.
rm. 301
OptEM Engineering - a pioneer in developing CAE software and services that focus exclusively on the
fundamentals of interconnect analysis - will present their latest interconnect extraction and analysis
software tools for submicron ICs, advanced IC packages, and cable/connector systems.
CAD-Migos Software Tools, Inc.
rm. 304
SPICE-IT! solves problems. Make it a point to come to this presentation to see a full-featured, mixedmode simulation tool specifically created to solve your design problems. Don’t miss this opportunity.
Visit Booth #1638!
Chronology Corp.
rm. 305
Verification Reuse answers the functional challenge posed by the functional verification crisis.
Simulation speed, emulation, and formal verification cannot address the explosion in designs with IP
and design reuse. Chronology’s new QuickBench® delivers Verification Reuse in easy-to-implement
stages while preserving your functional verification methodology.
TransEDA, Inc.
rm. 306
3:20
pm
TransEDA announces a major breakthrough in logic design verification with a new, unique solution that
is a ‘first’ in EDA. StateSure is an auto-interactive statemachine verification tool for Verilog/VHDL
designers. StateSure combines static and dynamic analysis and simplifies the verification process for
complex controllers.
Derivation Systems, Inc.
rm. 102
The Formal Synthesis Company™. Derivation Systems introduces its DERIVATION technology for
synthesizing formally verified designs from high-level behavioral specifications. Come see DRS Derivational Reasoning System™, a design environment that supports system-level codesign in a
formal framework.
Simplex Solutions, Inc.
rm. 103
Have you seen it? With Simplex there’s no more waiting for silicon to see the problems. Designers
now have visibility into physical design problems such as interconnect parasitics, clock skew, IR
(voltage) drop, signal coupling, and electromigration. Come see it in Simplex!
HyperLynx
rm. 301
HyperLynx, the leading-supplier of Signal Integrity and EMC tools under $20K, announces the addition
of crosstalk to the HyperSuite, a bundling of their SI and EMC tools. Come see how the HyperSuite
can solve your high-speed design problems.
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Novas Software, Inc.
rm. 304
Debussy™, The Engineer’s Desktop™ - integrated debug & analysis environment for Verilog
HDL/VHDL and mixed-signal designs. Debussy accelerates HDL source code, state machine, and
internal/external IP design debugging. Debussy significantly enhances productivity from architectural
concept, implementation, through tape-out.
Sapien Design
rm. 305
Sapien Design offers IP products including USB-compliant Function and Host Controller macros, and
a USB Test Environment. All are available in Verilog or VHDL. The macros are also available in netlist
for popular FPGAs or synthesizable RTL for ASIC.
Cypress Semiconductor
rm. 306
3:40
pm
Cypress will highlight the industry’s fastest In-System Reprogrammable (ISR™) CPLD family —
Ultra37000™, Jam programming support, and Warp™ VHDL and Verilog development tools that make
designing today a simpler task. Get to market faster with Cypress programmable logic.
K2 Technologies/Shearwater Group
rm. 102
K2’s products present a highly automated approach to design finishing including physical verification,
reticle design synthesis, wafer layout, OPC, fracturing, jobdeck generation and the generation of
mask/wafer fab, documentation. Benefits include reduced cost, faster cycle times and elimination of
errors.
Silicon Valley Research, Inc.
rm. 103
Silicon Valley Research, Inc. provides leading-edge IC physical design software for floorplanning,
placement, routing, custom layout and parasitic extraction of deep submicron ASICs, ASSPs, mixed
signal ICs and microprocessors. SVR also provides design consulting services and support to its
customers.
Artisan Components, Inc.
rm. 301
Artisan Components, Inc., a leading physical Intellectual Property (IP) developer, provides ProcessPerfect™ embedded memories, standard cells, and I/Os to semiconductor, ASIC ASSP and COT
suppliers who need the highest performance, lowest power and highest density, achievable for their
silicon process.
Semiconductores Investigation Y Diseno (SIDSA)
rm. 304
SIDSA offers ASIC design solutions and a variety of reusable IP modules, as well as EDA tools
featuring soft-cores design management and rule checking. SIDSA is also introducing a Field
Programmable System-on-Chip, consisting of a mixed-signal FPGA with on-chip microprocessor.
ANSOFT Corp.
rm. 305
Ansoft Corporation, the leading electromagnetics and wireless EDA company, offers solutions for
parasitic extraction, field solving and signal integrity with an emphasis on IC packages, cables,
connectors, printed circuit boards and on chip interconnects. Recently released features for signal
integrity analysis with enhanced productivity will be displayed.
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Intercept Technology Inc.
4:00
pm
rm. 306
Join Steve Klare, President of Intercept Technology Inc., for a detailed presentation on the features of
Pantheon, an integrated PCB/Hybrid/MCM design application. The presentation includes the
Pantheon Database (PDB) native file format, Breakout Router capabilities, and the direct output of
Pantheon design information in Mitron’s GenCAD manufacturing file format.
FTL Systems, Inc.
rm. 102
Your high-performance, full-language VHDL and VHDL-AMS simulation is now affordable with Auriga.
Auriga’s technology firsts include fully parallel compilation, parallel embedded scheduling combining
event-driven accuracy with cycle-driven performance and optimizing HDL compiler technology.
Compaq Computer Corp.
rm. 103
Today’s Pentium II Workstations make a compelling argument to move from proprietary UNIX systems
to industry-standard Windows NT-based environment. This presentation will discuss the performance
benefits of Compaq Professional Workstations over ordinary PCs, and discuss how Wintel
Workstations match and exceed performance levels of RISC/UNIX systems.
Verisity Design, Inc.
rm. 301
Verisity Design offers Specman, high-level verification automation (HLVA) solutions for the functional
verification of electronic systems and chips. Specman, provides a complete solution for functional
verification integrated with today’s leading HDL simulators - both VHDL and Verilog, event-driven, and
cycle-based simulators.
Fintronic USA, Inc.
rm. 304
FinSwHw is a co-simulation Verilog-C environment, supported by Super FinSim, the fastest Verilog
simulator. Pure C-code is transformed automatically into code that can be used in Verilog simulations.
Detailed timing information regarding the execution of the C-code is produced.
LogicVision, Inc.
rm. 305
LogicVision will describe icBIST3.0™, the most complete suite of test and diagnostic solutions for
complex systems, SOCs and ASICs that depend on very deep sub-micron technology. icBIST3.0™
saves engineering time and manufacturing costs by significantly reducing the test development effort
and ATE requirements for at-speed test and diagnostics of leading-edge products. Put us to the Test!
Fujitsu/ICL
rm. 306
4:20
pm
82
Thought about the Silicon Explosion and its impact on current design methods? Come and learn about
SuperVISE, the Fujitsu/ICL solution for SYSTEM design. SuperVISE delivers a proven solutions and
has been shown to reduce time-to-market by at least 25%.
CAST, Inc.
rm. 102
NEW VHDL CORES AND MODELS? From the exciting new synthesizable cores and simulation models
we’re announcing here to our existing broad libraries of proven devices (www.cast-inc.com), CAST
delivers high-quality, ready-to-use, cost-effective solutions for practical IP-based design.
OEA International, Inc.
rm. 103
OEA is demonstrating the newest, CELL-AN cell SPICE extraction tool, NET-AN critical multi-net
extraction and P-GRID power network analysis tool, all powered by the most accurate and fastest
“Cheetah II” 3D field solver, and the new SPIRAL inductance design tool.
Verisity Ad
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Topdown Design Solutions, Inc.
rm. 301
Topdown delivers System-on-Chip design solutions using our core model generation technology.
TopProtect™ generates protected models for securely distributing Intellectual Property. Cyclops™
generates cycle-based models of your designs that run 10 to 50 times faster with your existing
simulator and testbenches.
GLOBEtrotter Software, Inc.
rm. 304
FLEXlm from GLOBEtrotter is used by most all EDA vendors. See how GLOBEtrotter’s FLEXadmin helps
you get the most out of your software budget, and justify your spending to management. Simplify
license administration efforts while gaining greater understanding of how your organization uses
software. GLOBEtrotter will also discuss the essential Software Asset Management practices for EDA
customers.
Abstract Inc.
rm. 305
Abstract Inc., the world’s technological leader in formal verification tools and methodologies for ASICs
and systems-on-a-chip presents the leading-edge CheckOff tools for complete equivalence and
property checking.
Axis Systems
rm. 306
4:40
pm
The Ultimate Verification Systems Company makes its product debut - Xcite-1000. Using its patented
and revolutionary ReConfigurable Computing (RCC) technology, Xcite-1000 achieves superior
simulation performance while preserving debugging flexibility. Come to our booth for a full description
of the breakthrough in verification technology.
Altera Corp.
rm. 102
Altera will present its comprehensive design solution, including device densities up to 250,000 gates,
the industry’s best development software, and the broadest range of megafunctions.
Analogy, Inc.
rm. 103
Analogy extends its simulation offerings with Saber®/ModelSim™, a mixed-signal product connecting
the powerful Saber mixed-signal simulator with ModelSim™ PLUS, Model Technology, Inc.’s
VHDL/Verilog simulator. Analogy also introduces TESTIFY, the first product to offer mixed-signal fault
simulation for functional test development.
Library Technologies, Inc.
rm. 301
LibChar, UnBlock, IcPower, Verilog, BlockChar and some of their siblings get together for Breakthrough
Dynamic Timing Analysis of custom blocks with full state dependent power and timing models. As
expected no compromise accuracy. A MUST SEE EVENT, DON’T MISS IT.
OPMAXX, Inc.
rm. 304
OPMAXX is demonstrating software for yield analysis and improvement, mismatch analysis, analog
fault coverage and testability analysis and introducing Oscilation-based Built-in Self-test (BIST) focused
on solving critical functional and structural test problems of IP and analog design blocks.
Gambit Automated Design, Inc.
rm. 305
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You Can use any P&R tool to start your VDSM design, but if you want to finish it, you better have
GRANDMASTER™. Its advanced algorithms, flexibility, and user-friendliness make it the fastest way
to build VDSM silicon real estate.
Gambit Ad
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ACCEL Technologies, Inc.
5:00
pm
rm. 306
Presenting product data management software. Personal PDM promotes collaborative design efforts,
managing project data, providing a single electronic vault. DesignFlow organizes projects, streamlines
communication, facilitates effective design management. ViewCenter allows viewing, storing and
printing of Schematic and PCB files on Intranet or network locations.
Snaketech
rm. 102
Substrate Noise Problems? Following a brief discussion on the basics of substrate noise, Snaketech
will explain how you can quantify and understand substrate noise problems using Layin, a unique
substrate noise modeling program. All technologies and feature sizes are modeled.
Sun Microsystems
rm. 103
Engineering productivity demands more than acquiring the next generation desktop computer to the
engineering environment. Many companies are looking to “compute ranches” as a tool for engineering
productivity. Sun’s presentation will examine the implementation of such a compute facility.
Interra, Inc.
rm. 301
Interra’s EDA-IP toolkit offers customizable software components for EDA tool developers and
semiconductor vendors. Modules are available for VHDL/Verilog analysis, translation, test, debugging
and RTL synthesis. Interra is introducing two new components: Concorde™ Super Fast RTL Synthesis
and NOM™-Netlist Object Model.
Integrated Intellectual Property Inc.
rm. 304
A case study presents how our IP Integration and Consulting Services unit works actively with
customers to follow the IP all the way to tape-out. Our products are dedicated to help customers create
large designs using IP and to take them to silicon very quickly. The SuperCore series and SuperSim
series offers solutions for IEEE-1394, AGP, USB and PCI.
QuickLogic Corp.
rm. 305
QuickLogic designs the fastest FPGAs in the industry along with comprehensive design software. The
company’s products provide engineers a low-cost path to rapidly transfer high-performance custom
circuitry into physical silicon at their desktop. This significantly shortens the design cycle times of
electronic systems, accelerating time-to-market.
Circuit Semantics, Inc.
rm. 306
5:20
pm
86
Circuit Semantics, Inc. (CSI) is the industry leading provider of transistor-level characterization tools
for intellectual property cores, custom design, memories and standard cells. CSI’s presentation will
highlight our proven Timed-Boolean Extraction technology for characterization of multi-million transistor
designs with pico-second accuracy.
Intrinsix Corp.
rm. 102
Intrinsix is the leading independent provider of design services for ASIC and High Integration
Embedded Systems. At DAC’98 Intrinsix is introducing its proprietary microPlatform design paradigm
which combines ASIC design, verification, embedded software, and integration of IP cores.
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VeriBest, Inc.
VeriBest®,
rm. 103
Windows ® NT®,
Inc. the leading provider of EDA systems solutions on
introduces integrated
design software products to address the needs of all levels of CAE and PCB designers, with FPGA and
Expedition PCB. Full functionality at a great price.
EDA Standards
rm. 301
The EDA Standards booth is a collaboration of companies and organizations that will be demonstrating
the latest releases dealing with CAD design transfer; CAD/CAM transfer and other programs
concerning interoperability. Participants include: Ecce, EIA/EDIF, EIA/IBIS, EIA/CMC, and EDAC.
Simpod, Inc.
rm. 304
Modeling for Co-Development: Introducing DeskPOD™, a family of high-performance modeling systems
for the co-development of digital electronic systems. DeskPOD™ offers hardware and software teams
scalable, simulation acceleration and rapid time-to-modeling solutions which significantly shorten
product design and verification schedules.
Chip Express Corp.
rm. 305
ChipExpress’ LPGA technology offers the best of both worlds: flexibility/time-to-market of FPGAs and
density/performance of traditional gate arrays. Fast-turn LPGAs allow smooth design-to-production
transition and speeding of ASIC design cycle. Further, ChipExpress’ alliance with Lucent provides
complete system-on-chip solutions.
IKOS Systems Inc.
rm. 306
5:40
pm
IKOS Systems, the design verification company, will update you on the status of our three businesses:
simulation acceleration, emulation, and verification services. The update will use customer
successes to demonstrate the return that IKOS’ high performance verification products and services
provide.
Nu Thena Systems, Inc.
rm. 102
Nu Thena introduces its new FORESIGHT FOR CODESIGN product. A significant new product based on
the industry-leading FORESIGHT system design toolset, FORESIGHT FOR CODESIGN is the only proven
systems engineering solution for system-on-a-chip designers.
Sagantec
rm. 103
Come learn how Sagantec enables reuse and optimization of existing silicon intellectual property for
deep submicron design. Its software ensures efficient silicon IP reuse to implement system on
silicon; meet time-to-market and time-to-volume requirements; and take advantage of new process
technology.
Intellitech Corp.
rm. 301
Intellitech will present 3rd generation Scan Tools for silicon debug. The enterprise-wide (Unix &
Windows) solution will reduce your prototype debug time. If you’re using BIST, IP CORES or performing
path delay tests, Intellitech Scan Tools can help!
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Virtual Silicon Technology, Inc.
rm. 304
Virtual Silicon develops, markets, and supports Silicon Ready™ libraries and physical design
components for complex integrated circuits in 0.25 and 0.18 micron process technologies. The
company’s Diplomat™ product line offers world-class standard cells, I/Os, and memories that are
manufacturable at multiple foundry partners.
Spectra Logic
rm. 305
Spectra Logic manufactures both reliable, scalable, affordable and widely supported tape libraries,
and a powerful backup and archival software solution. Alexandria Backup and Archive Librarian
software and the Spectra 10000 AIT tape library won Unix Review’s 1997 Outstanding Product award.
Alternative System Concepts, Inc.
rm. 306
6:00
pm
VHDL or Verilog translation tools expand IP market and simplify single-chip design flow. VBIT® inserts
boundary and embedded JTAG. ASC announces PowerBuster™.
Moscape Inc.
rm. 102
Moscape will be premiering state of the art products aimed at improving performance and reliability of
complex deep submicron IC designs. It performs assertion based analysis of static and dynamic
circuits, tightly integrates logic and physical designs and significantly reduces design iterations.
Aristo Technology
rm. 103
Aristo Technology is a new startup offering block-level interconnect design automation tools for system
ICs. Aristo’s products help reduce overall design cycle time 20-35% when used within an interconnectcentric flow featuring a novel “topology and interconnect hardening” methodology.
Sand Microelectronics, Inc.
rm. 301
Accelerate your design with Sand’s latest silicon-proven synthesizable cores for IEEE 1394, USB, and
PCI connectivity standards.
Tower Semiconductor Ltd.
rm. 304
As a semiconductor foundry with a recently-implemented customer-dedicated design center, Tower
Semiconductor will address the issue of embedded Flash opportunities in today’s marketplace.
CoWare, Inc.
rm. 305
CoWare, Inc. provides EDA software and services to meet the growing performance demands of
today’s IC designers, by offering tools and methods that provide an entirely new, top-down solution for
system-level design for this new generation of increasingly-complex ICs–systems-on-a-chip.
Translogic USA Corp.
rm. 306
Translogic’s EASE/HDL offers easy graphical entry for complex chip design. It automatically generates
Verilog or VHDL code which inputs to the industry’s most popular simulators and synthesis tools. At
DAC, Translogic introduces graphical display of existing Verilog or VHDL code, a key component for
design reuse.
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Simplex Solutions
Ad
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product descriptions
0-In Design Automation
Booth 1434
1784 Technology Dr.
San Jose, CA 95110
(408) 487-3644
http://www.0-in.com
EP Time Slot: 11:40 am
One-in-a-trillion-cycle bugs—you can’t simulate them, you can’t emulate
them, but your silicon will hit them every few hours. Black-box techniques
simply cannot find low-probability bugs. 0-In’s white-box verification zerosin on corner cases where they like to hide. It’s fast, it’s efficient, and it’s
extremely thorough—all without design, testbench, or simulation
changes. At 0-In, we’re turning verification inside-out to find the world’s
toughest bugs!
Abstract Inc.
Booth 1346
46613 Fremont Blvd.
Fremont, CA 94538
(510) 360-2700
http://www.abstract-inc.com
EP Time Slot: 4:20 pm
Abstract Inc. presents a breakthrough in equivalency-checking technology
with its latest CheckOff range of products for enabling verification of
multi-million gates Systems-on-a-Chip design. CheckOff-S, the lightning
fast structural equivalence checking tool, can now compile and compare
2-million gate designs in less than 10 minutes using under 400MB of
RAM. We invite you to visit our booth and our suites to see this exciting
breakthrough technology and our model-checking technology, CheckOffM, being demonstrated live in front of you.
ACCEL Technologies, Inc.
Booth 812
6825 Flanders Dr.
San Diego, CA 92121
(619) 554-1000
http://www.acceltech.com
New Version 14 ACCEL EDA user-suggested enhancements! TrueType
fonts; customizable toolbars; drill reports for plated, non-plated holes;
refined selection box; enhanced Copper island removal; connect unique
nets together with polygon ties; Windows Print Preview; user-defined
fields. ACCEL PDM product data management software. Personal PDM
promotes collaborative design efforts, manages all project data, provides
single electronic vault. DesignFlow organizes projects, steamlines
communication, facilitates design management. ViewCenter allows
viewing, printing of Schematic, PCB files on Intranet or network.
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DAC Space
Selection Ad
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ACEO Technology, Inc.
Booth 1842
46750 Lakeview Blvd.
Fremont, CA 94538
(510) 668-1700
http://www.aceo.com
For Verilog and VHDL logic synthesis, Asyn™ features One-Pass
Hierarchical Synthesis™ to handle large deep submicron ASICs. Asyn
offers an extremely fast compile with industry leading gate-count
optimization, without requiring RTL partitioning. Asyn handles the entire
design in a single pass - saving days of extra work and costly iterations.
For your ASIC prototyping needs, Gatran® features The IntelliTrans™
System for intelligent design migration - solving the difficult challenges of
design reuse and technology upgrading, and SoftWire™ for multi-FPGA
partitioning. Unix and WindowsNT supported.
Advanced RISC Machines (ARM)
Booth SV28
985 University Ave., Ste. 5
Los Gatos, CA 95032
(408) 399-5199
http://www.arm.com
ARM is a leader in microprocessor Intellectual Property. ARM designs and
licenses fast, low cost, power efficient RISC processors, peripherals and
“system-chip” solutions for embedded control, consumer/educational
multimedia, DSP and portable applications. The ARM EDA group is
dedicated to providing quality models to the EDA industry to ensure
designers have the widest possible choice of performance tools available
to speed their products to market.
Advanced Technology Center,
CoverMeter Division
Booth 556
22982 Mill Creek Dr.
Laguna Hills, CA 92653
(714) 583-9119
http://www.covermeter.com
CoverMeter is the industry’s most complete, most flexible and highestthroughput Verilog code coverage analysis tool. Supporting PLIconforming Verilog simulators, CoverMeter is used by designers and
verification engineers to determine which portions of application code
have yet to be exercised in simulation test cases (jumping with just a
mouse click to uncovered code). CoverMeter is a precision “calibration”
tool, useful at each stage of the design verification process, measuring
code coverage for statements, conditions, toggles and user-specified
expressions, including state machines.
ACEO Ad
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Alba Centre (The)
Booth SV2
Altera Corp.
Booth 118
Cairgorm House, Almondvale Blvd.
Livingstoni, EH54 6QN West Lothian, UK
(44) 1506-449500
101 Innovation Dr.
San Jose, CA 95134
(408) 544-8214
http://www.altera.com
ALDEC, Inc.
Booth 1222
2230 Corporate Cr.
Henderson, NV 89014
(800) 487-8743
http://www.aldec.com
ALDEC will be demonstrating its completely integrated, Windows NT/95
based, VHDL and Verilog design environment. The products provide
complete support for VHDL and Verilog and include an HDL editor,
Automatic Test Bench Generation, Design Manager and Language Based
Simulator (Behavioral and Structural). Aldec’s innovations in the area of
ready-to-use VHDL/Verilog software solutions for supporting high density
FPGA and CPLD devices will be demonstrated in its booth, stop-by and
receive your Free VHDL Evaluation Kit.
Alpine Microsystems, Inc.
Booth SV26
200 E. Hacienda Ave.
Campbell, CA 95008
(408) 364-8000
http://www.alpinemicro.com
Alpine Microsystems has invented a new microelectronic interconnect
technology to eliminate the system bandwidth bottleneck facing the
electronics industry. The company’s “Complex IC Technology” offers
inter-chip speed and I/O bandwidth equal to single-chip solutions, yet at
lower cost and vastly higher levels of integration. It is now possible to
integrate the fastest microprocessors, memory and other state-of-the-art
chips to create dense, high-performance “system-in-a-package”
solutions — while maintaining existing design, fabrication, assembly and
test infrastructure.
Altera offers the broadest line of CMOS PLDs, including device densities
up to 250,000 gates and system speeds up to 250 MHz. These devices
combine the time-to-market advantages of PLDs with the density, speed,
and cost once associated exclusively with gate arrays. The FLEX 10K
embedded PLD family is optimized for mid- to high-density designs; the
low-cost FLEX 6000 family offers a volume alternative to gate arrays in
the 10,000 to 24,000 gate range. All device families are supported by
Altera’s architecture-independent MAX+PLUS II software. Altera also
offers the broadest IP portfolio, including functions from the AMPP and
MegaCore libraries.
Alternative System Concepts, Inc.
Booth 2250
P.O. Box 128
22 Haverhill Rd.
Windham, NH 03087
(603) 437-2234
http://www.ascinc.com
ASC's verilog2vhdl™ and VHDL2verilog™ are used worldwide by IP
suppliers and users to translate behavioral HDL and synthesizable RTL
designs in minutes versus weeks, when done manually. Both translators,
in addition to Sun and HP, now support NT. VBIT® inserts RTL IEEE
1149.1 boundary scan before gate synthesis, enabling single-pass
verification. VBIT® will soon support embedded IP cores. ASCs low
power optimization tool PowerBuster™ to support data flow and control
flow circuits is ready for beta test; partnerships are invited.
Ambit Design Systems, Inc.
Booth 300
2500 Augustine Dr.
(408) 988-3232
http://www.ambit.com
It’s time to switch to BuildGates, Ambit’s next-generation synthesis tool
for multi-million-gate ASIC design. BuildGates integrates fast, full-chip
static timing analysis, automatic time budgeting and an advanced,
programmable architecture to deliver superior synthesis results in
dramatically shorter turnaround times. We’ll show you why leading-edge
ASIC vendors like IBM, LSI Logic, Lucent and Toshiba have added
BuildGates to their supported flows. And, you’ll see why leading
customers like Cisco Systems, Silicon Graphics, and Toshiba have
started using BuildGates in their design flows.
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American Microsystems, Inc.
Booth SV27
ANSOFT Corp.
Booth 930
2300 Buckskin Rd.
Pocatello, ID 83201
(208) 234-6890
4 Station Sq., Ste. 660
(412) 261-3200
http://www.ansoft.com
ALL ROADS LEAD TO AMI for FPGA to ASIC to ASIC migration services. For
cost-reductions or ASIC second-sourcing, AMI’s NETRANS™ offers fast,
reliable prototyping for all types of digital IC designs. Vectorless FPGA
translations to gate array are now available with AMI’s Vectorless
NETRANS. AMI also offers 20+ years of mixed-signal design expertise, a
virtual mixed-signal interface option and flexible CMOS manufacturing
processes making mixed-signal ASIC solutions easy and cost-effective.
Analogy, Inc.
Booth 944
9205 SW Gemini St.
Beaverton, OR 97008
(503) 626-9700
http://www.analogy.com
Analogy introduces Saber®/ModelSim™, a new, high-performance
Saber/VHDL/Verilog mixed-signal simulation product based on Analogy’s
Saber mixed-signal simulator and Model Technology, Inc.’s industryleading ModelSim™ PLUS Simulator. This is the only mixed-signal product
in the industry to offer statistical analysis of analog circuits combined
with digital elements described in VHDL or Verilog. Also new at DAC is
TESTIFY™, an analog and mixed-signal test product for analyzing design
behavior through analog fault analysis.
Anasift Technology Inc.
Booth 12
44160 Old Warm Springs Blvd.
Fremont, CA 94538
(510) 445-0688
http://www.anasift.com
Anasift’s Anascope is a symbolic analysis and AC behavior modeling tool
for analog IC and RF analog IC design. It calculates simplified symbolic
transfer functions, simplified symbolic pole/zero expressions, reduced
Laplace variable expansion of circuit functions, root locus analysis, and
much more. Anascope can significantly increase design efficiency. It also
helps analog designers design circuits which operate at higher frequency,
require less area, and consume less power.
94
Ansoft Corporation, the leading electromagnetics and wireless EDA
company, offers solutions for parasitic extraction, field solving and signal
integrity. We recently released our third generation signal integrity
analysis tool for high speed digital systems. In addition to creating SPICE
models and performing simulations, the current distribution in complex
3D interconnect structures can be viewed and IBIS models for connectors
and packages can be created. A new seamless interface to Xynetix EDA
Navigator and Cadence Allegro will be shown. If signal integrity is a
problem, Ansoft has a solution for you.
Applied Simulation Technology
Booth 923
2188 Bering Dr.
San Jose, CA 95131
(408) 434-0967
http://www.apsimtech.com
Applied Simulation Technology provides software solutions for the
modeling and simulation of high speed digital and analog circuits and
systems. Apsim’s products are well suited for Signal Integrity and EMI
simulation. The products are well integrated into industry standard CAD
environments. Applications of the products range from parasitic LCR
extraction to full board simulation of EMI and Signal Integrity. Other
capabilities include design software for LCD panels. Web Site URL
http://www.apsimtech.com.
Aptix Corp.
Booth 2042
2880 N. First St.
San Jose, CA 95134
(408) 428-6200
http://www.aptix.com
Aptix’ System Explorer extends rapid system prototyping into real-time
verification of software and hardware for embedded systems. The flexible
open architecture of the System Explorer enables design engineers to
prototype an entire complex electronic system, by combining FPGAs,
representing the custom logic, Intellectual Property blocks, I/O functions,
memories, DSPs, microprocessors, analog and RF components in a
reconfigurable environment. Prototyping gives the design teams the
ability to guarantee functional correctness, explore the subtleties of the
algorithms and refine performance and features.
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xhibit guide
Arcadia Design Systems, Inc.
Booth 2318
2700 Augustine Dr., Ste. 298
(888) 393-1688
http://www.ArcadiaDesign.com
Mustang is a fully automatic Datapath Placement Engine that has helped
deliver dozens of high performance designs to silicon. Designed to
integrate seamlessly into your existing design flow, Mustang performs an
upfront regularity analysis from a Verilog or EDIF netlist to determine what
percentage of your design is regular. Mustang then automatically
identifies, extracts and optimizes datapath structures to generate a
placement file that can be read by standard P&R tools. Equipped with
powerful controls, Mustang enables you to explore alternatives and
achieve your target performance.
Argonaut RISC Cores Inc.
Booth 2332
Argonaut House
369 Burnt Oak Broadway
Edgware, Middlesex, HA8 5XZ UK
(44) 181951-6170
http://www.risccores.com
ARC is a small, fast, flexible, easy to use, synthesizable processor core
designed for embedding into Systems On Silicon products to perform all
programmable functions replacing DSP, CISC, RISC and hardwired logic
blocks. Targeted at engineers trying to solve performance, cost and
functionality issues in their product designs. ARC will be demonstrating
the ARC install wizard, which makes custom processor design a simple
point and click exercise.
Aristo Technology
Booth 80
20111 Stevens Creek Blvd.
Ste. 200
Cupertino, CA 95014
(408) 342-9083
http://www.aristotech.com
Aristo Technology, Inc., Cupertino, CA. is a newly announced EDA vendor
entering the block-level system IC planning and implementation tool
market. The company’s products will target complex ASIC, ASSP, and
microprocessor design projects employing block-level design techniques.
Ansoft Ad
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Artisan Components, Inc.
Booth 1336
1195 Bordeaux Dr.
Sunnyvale, CA 94089-1210
(408) 734-5600
http://www.artisan.com
ATG Technology
Booth 1854
Artisan Components is a leading developer of high-performance, lowpower and high-density physical Intellectual Property (IP) products for the
design and manufacture of System-on-a-Chip ICs. The company offers
highly differentiated Process-Perfect™ embedded memory, standard cell
and I/O components that meet semiconductor, ASIC, ASSP and COT
suppliers’ acute performance, power and density needs. Every product is
optimized for each customer’s manufacturing process and includes
popular and custom design views delivered ready for use with industry
standard and proprietary design tools.
Artwork Conversion Software, Inc.
Booth 1254
1320 Mission St., Ste. 5
Santa Cruz, CA 95060
(408) 426-6163
http://www.artwork.com
145 N. Franklin Turnpike
Ramsey, NJ 07446
(201) 236-3635
http://www.atgtech.com
Supplier of the latest ATPG tools. INTELLECT, the industry’s most
powerful sequential ATG engine, allows designers to actively address
testability without radically altering their design style. INTELLECT is
designed to handle the structures that cripple other test tools: almost full
scan designs, complex clocks, derived sets and resets, tristate busses,
bi-directional pads and embedded RAM and ROM. Combined with truly
exceptional testability analysis, INTELLECT offers unmatched power and
flexibility to improve testability while minimizing area and timing impact.
Auspy Development Inc.
Booth 10
10430 S. De Anza Blvd., Ste. 275
Cupertino, CA 95014
(408) 252-5813
http://www.auspy.com
Artwork will be exhibiting a variety of CAD translators for GDSII, AutoCAD,
Mann, Mentor BoardStation, Cadence Allegro and Virtuoso, CIF and
Gerber. We will also be demonstrating our GDSPLOT IC plotting software
and GDSVU our GDSII viewing software. We’ll also be showing a new BGA
design program that works with either AutoCAD or Cadence Allegro. All
translators and plotter drivers are available on Windows 95/NT, Sun, HP
and IBM workstations. For more DAC related information see our web site
at www.artwork.com.
Auspy Partition System (APS) partitions an ASIC or FPGA netlist into
multiple FPGA implementation. APS, working interactively or
automatically, handles million+ gate designs, honors timing and capacity
constraints, supports popular FPGA’s, manages design changes and
debugging probes. Auspy Programmable Board Router (APBR), with
matching features as APS, maps a partitioned FPGA netlist into a
programmable system custom-made with pre-planned wiring in-between
FPGA’s, non-FPGA components and switching devices. APS, together with
APBR, makes the backbone of your ASIC prototyping solution.
ASPEC Technology, Inc.
Booth 2340
Automata Design, Inc.
Booth 1554
830 E. Arques Ave.
Sunnyvale, CA 94086
(408) 328-9638
http://www.aspec.com
Aspec’s Semiconductor Intellectual Property (SIP) library services help
accelerate design-to-fabrication time for complex ICs. Aspec provides
architectures for Intellectual Property (IP) creation, design workflows and
methodologies, design automation tools and a range of design
services—helping customers reduce the time and costs associated with
bringing deep sub-micron (DSM) designs to silicon fabrication. Aspec’s
physical IP libraries provide the essential building blocks for ICs and
system-on-chip (SoC) products, including I/Os, memories and core cells
for both array and cell-based ICs.
950 Herndon Pkwy., Ste. 260
Herndon, VA 20170
(703) 742-9400
http://www.adiva.com
ADI produces a full range of DFM software tools. Artwork analysis,
CAD netlist verification, remote engineering artwork display &
signal analysis, bare board test fixture generation, component
assembly planning & simulation, loaded board test fixture
generation.
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Avant! Corp.
Booth 1308 & 1718
46871 Bayside Pkwy.
Fremont, CA 94538
(510) 413-8697
http://www.avanticorp.com
CAD-Migos Software Tools, Inc.
Booth 1638
Avant! Corporation develops, markets and supports integrated circuit
design automation (ICDA) software for deep and very deep submicron ICs,
microprocessors, microcontrollers, ASSPs and complex ASICs. Avant!
delivers the most comprehensive front-to-back design solution. With our
complete TCAD-to-ECAD tool suite, Avant! offers solutions for all your
deep-submicron technology and design needs.
CAD-Migos Software creates powerful, fast, easy-to-use CAE tools. The
flagship product, SPICE-IT!, was built by engineers for engineers under
the maxim: A powerful quality, mixed-mode simulation tool should be both
fully-featured and reasonably priced - not stratospherically priced. CADMigos Software can provide a clear solution to your needs. Please inquire
and find out how!
Axis Systems
Booth 1640
Cadabra
Booth 1442
209 Java Dr.
Sunnyvale, CA 94089
(408) 588-2000
http://www.axiscorp.com
Axis Systems presents the next generation in design verification - Xcite1000. Using its patented ReConfigurable Computing (RCC) technology,
Xcite-1000 achieves superior simulation performance while preserving
debugging flexibility. Applications for Xcite-1000 range from high-speed
regression runs to software/hardware co-design. Whether the design is
described as either Verilog behavioral, RTL or gate level, Xcite-1000 will
custom configure its computing elements to maximize parallel processing
while minimizing communication. Further, Xcite-1000 directly plugs into
workstations for compactness and high-speed communication. Xcite1000 offers the highest simulation throughput without having to change
design methodology.
BTA Technology, Inc.
Booth 109
4633 Old Ironsides Dr., Ste. 200
(408) 986-1011
http://www.btat.com
Full chip, gate level reliability simulator for timing, clock skew and design
margin verification due to hot carrier effect. Transistor level reliability
simulators (BTABERT, EMWorks, TDDBWorks) for failure rate, lifetime
prediction, and layout analysis due to hot carrier, electromigration and
oxide breakdown. SPICE modeling tools (BSIMPro, SIGMAPro, NoisePro,
S-Pro) for DC, AC, Flicker noise, S-parameters and RF modeling for
MOSFETs and BJTs. Accurate, robust SPICE model extraction for
BSIM3v3, MM9, EKV, GP BJT. Silicon-based interconnect
characterization. Custom test chip design.
98
499 Seaport Ct., Ste. 201
Redwood City, CA 94063
(650) 369-5853
http://www.cadmigos.com
2350 Mission College Blvd., Ste. 400
(408) 982-9446
http://www.cadabratech.com
Cadabra offers fast, cost-effective solutions for automating the layout of
standard cells, gate array cells, IO libraries and macrocells. The
CLASSIC™ family of products—a suite of physical synthesis tools that
create transistor-level GDSII layouts from SPICE netlists—dramatically
increases your productivity by automating cell layout. CLASSIC’s design
space exploration features enable you to quickly evaluate layout tradeoffs
to develop more efficient cell architectures. You can quickly and easily
regenerate cells to accommodate design rule changes and technology
migration with CLASSIC.
Booth 1508
555 River Oaks Pkwy.
San Jose, CA 95134
(408) 943-1234
http://www.cadence.com
Make it smaller, faster, better, cheaper. Whatever the request, Cadence
technology enables you to do whatever needs to be done. Stop by the
Cadence booth for complete solutions to system-level design, deep
submicron design, custom IC design, logic design and verification, and
high-speed board design. Our Testimonial Theater presentations will tell
you how our technologies got products to market on time, on spec, and
on budget.
Avant! Ad
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CAE Plus, Inc.
Booth 212
9130 Jollyville Rd., Ste. 340
Austin, TX 78759
(512) 338-0165
http://www.cae-plus.com
China Integrated Circuit Design Center
Booth 18
CAE Plus’ Pro-Active™ virtual prototyping tools and verification services
support the development and verification of embedded system ICs. The
ArchGen™ model development tool synthesizes fast, RTL-accurate ‘C’
models; consistent, synthesizable HDL models; and ISS models (new!)
from a single graphical, behavioral-level specification. The ASVP Lab™
tool provides an open environment for constructing application-specific
virtual prototypes (ASVPs) incorporating processor models, (RTL-C and
ISS), other core models, application-specific software and stimulus, and
interfaces to hardware and software debugging tools. Pro-Active™
Verification Services support customers’ system IC verification efforts by
providing customized access to CAE Plus’ tools and verification expertise.
Cahners Business Information
Booth 808
275 Washington St.
Newton, MA 02158
(617) 964-3030
http://www.cahners.com
Cahners Business Information is the publisher of more than 120
specialized business and professional publications as well as CD-ROM
and online services. Cahners Business Information serves the vital
information needs of over 7.6 million business managers and
professionals around the world. In addition to its publications, our
company also provides publication and industry-based research,
economic forecasting, reprints, direct mail services, database marketing
plus custom publishing projects in all its served markets. We will be
offering free subscriptions to EDN, EDN Asia, EDN China, Electronic
Business, Electronic Business Asia, ECN and Electronic News.
See Duet Technologies in booth #1418.
CAST, Inc.
Booth 1652
VHDL CORES AND MODELS - Come see why CAST is your best source for
practical IP that’s cost-effective, quality-tested, and ready-to-use. Our
synthesizable cores provide the solutions you need when consolidating
designs with ASICs or FPGAs, or creating new systems with off-the-shelf
functions. Our simulation models range from economical standard part
and memory libraries to sophisticated devices and components. Review
our catalog (www.cast-inc.com), then come for a demo and discussion of
how you can best put CAST IP to work.
100
Panda VDE, a visualized high-level design capture and
debugging/simulation environment, accepts data/control diagram, PSM,
etc. The output is synthesizable or simulatable VHDL/Verilog code.
PolarSLE has many popular editing utilities, on-line DRC, etc. Moreover,
it provides features for layout reuse and net tracing, and handles layout
with millions of gates very fast. PolarVeri is a layout verification package
including DRC, ERC, NE, LVS. Its advantage lies on its performance and
less resource consumption. All available on UNIX and NT.
Chip Express Corp.
Booth SV32
2323 Owen St.
(408) 988-2445
http://www.chipexpress.com
CHIP EXPRESS offers fast turnaround gate arrays with comprehensive
engineering services, in a smooth migration path from net-list to rapidturn prototypes and then quickly into any volume production. Siliconverified cores from IP partners is available for fast implementation. The
product services include one-day turn LPGA (Laser Programmable Gate
Array) prototypes; one-week turn low volume production with OneMask®
process (single-wafer personalization); and one-month turn high-volume
HardArray™/TwoMask® production using state-of-the art fabs. Current
offering: 0.35micron with up to 1.5 million logic gates plus 416K bits
embedded memory.
Chronology Corp.
Booth 744
14715 NE 95th St.
Redmond, WA 98052
(425) 869-4227
http://www.chronology.com
Cascade Design Automation
24 White Birch Dr.
Pomona, NY 10970
(914) 354-4945
http://www.cast-inc.com
P.O. Box 8545
Beijing, 100015 China
(86) 1064-393294
Products: Chronology is a leading provider of software for specificationdriven verification. QuickBench® is a suite of products for creating
reusable testbenches in Verilog or VHDL. QuickBench Modeler uses
graphical interface specifications and optionally native HDL to generate
reusable bus-functional models. Come to our booth for a demo of our new
QuickBench products. TimingDesigner® models and analyzes digital
circuit behavior with timing diagrams. The built in static timing analysis
engine continuously checks for timing/protocol violations. Interface
models and specifications are available through Chronology’s Synchrony
program.
Cadabra Ad
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Chrysalis Symbolic Design
Booth 844
101 Billerica Ave.
N. Billerica, MA 01862
(978) 436-9909
http://www.chrysalis.com
Compass Design Automation
The Formal Design Company™ - Register at the Chrysalis booth for a
VERIFICATION SEMINAR - “THE FORMAL DESIGN FLOW - MAKING
SIMULATION HISTORY.” Sign up & WIN A FREE PDA. Learn how leading
companies have replaced gate-level regression simulation with Design
VERIFYer®, the industry standard in FORMAL EQUIVALENCE CHECKING.
See how Design INSIGHT®, practical MODEL CHECKING for design
engineers, finds RTL bugs faster and easier than with simulation alone.
Chrysalis offers a complete family of formal tools, in use at 125+ sites
worldwide.
Circuit Semantics, Inc.
Booth 81
4 North 2nd St., Ste. 576
San Jose, CA 95113
(408) 885-9250
Circuit Semantics, Inc. (CSI) is the industry leading provider of transistorlevel characterization tools for intellectual property cores, multi-million
transistor custom designs, memories and standard cells. DynaBlock is
CSI’s proven high-capacity solution for SPICE-accurate characterization of
high-performance designs such as microprocessors, multimedia
accelerators and DSPs. DynaCore generates a reusable timing model for
IP cores. CSI’s products plug-and-play with all popular static timing
analyzers and circuit simulators.
Compaq Computer Corp.
Booth 2118
P.O. Box 692000
Houston, TX 77269
(281) 927-8467
http://www.compaq.com
Looking for powerful workstations for your EDA applications? Plug into
Compaq. Compaq Professional Workstations combine industry-standard
components with advanced technology, such as an innovative Highly
Parallel System Architecture, to deliver superior performance,
functionality and Unix/NT interoperability. From design to verification,
Compaq Professional Workstations can support your compute intensive
applications, such as those offered by Cadence Design Systems, Mentor
Graphics, Synopsys, and VeriBest. Join us in booth #2118 for powerful
software and hardware demonstrations and highly informative technical
presentations.
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Compass Design Automation was acquired by Avant! in September 1997.
Former Compass libraries are offered through Galax!’s, a wholly owned
subsidiary of Avant! Corporation. Galax!’s mission is to enable system-onchip designers to create Silicon Intellectual Property (SIP) by providing
libraries, value-added IC design solutions, and EDA methodologies.
Computer Design
Booth 1550
10 Tara Blvd., 5th Fl.
Nashua, NH 03062
(603) 891-9125
http://www.computer-design.com
Computer Design magazine is the primary source of “why-to” information
for engineering managers, senior engineers and engineers responsible
for the design and development of today’s computer-based “smart”
products. Each monthly issue contains in-depth items and features
written by experienced senior editors who concentrate on the critical
technologies, components and tools needed to design microprocessor
and computer-based OEM products and systems.
ComSystems Integra, Inc.
Booth 449
Dongwha Bldg., Dogok-dong, 5th Fl.
Kangnam-ku
Seoul, 135-270 Korea
(82) 2-5786831
http://www.csieda.com
New version of CSiEDA, high-performance EDA solution, is now available.
CSiEDA 3 becomes much easier, faster, and more powerful. CSiEDA 3
supports various new features solving complex problems of EDA work
environment including autoplacement and auto router. CSiEDA 3 allows
the efficiency, the convenience, and the stability of work. CSiEDA 3
supports both standalone and networked environment. CSiEDA 3
comprises *WinSchematic (schematic capture), *WinPCB (PCB layout
editor), *Win3DView (3D modeling analyzer), *WinRoute (shape-based
autorouter), *WinMCM (MCM layout editor), and *EDA manager (EDA
project data manager).
Concurrent CAE Solutions, Inc.
Booth 1152
520 Valley Way
Milpitas, CA 95035
(408) 934-1116
http://www.ccaes.com
EDA Publisher® and EDA Browser® leverage design re-use throughout the
enterprise. Full schematic, symbols, PCB packaging and parts
information, and layouts, can be published in a common format for
access over company Intranet, or the public Internet. EDA Browser®
extends access to all forms of the intelligent design information, allowing
organizations including engineering, test, manufacturing, and
procurement access to the same design information.
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CoreEl Microsystems
Booth SV23
46750 Fremont Blvd., Ste. 208
Fremont, CA 94538
(510) 770-2277
http://www.coreel.com
CoreEl MicroSystems Inc. is a leading provider of Silicon Intellectual
Cores for the communication marketplace. A complete range of IP cores
are available in the fields of Ethernet, SONET and ATM for ASIC design.
CoreEl provides cores for the ethernet market namely Gigabit MAC,
10/100 MAC, RMON counters, VLAN support, RMII adapters, etc. In
SONET CoreEl provides framers for OC-3, 12 and 48 and a “IP over
Sonet” solution. For ATM single chip NIC solutions, SAR-622, ATM switch,
ABR, Utopia, etc. are available.
CoWare, Inc.
Booth 65
2900 Gordon Ave., Ste. 205
(408) 617-1613
http://www.coware.com
The CoWare N2C™ design system enables engineering teams to take
their system-on-a-chip design concepts from “napkin-to-chip™” in half the
time required using traditional IC design methods. CoWare N2C provides
language and architecture independent methods for system specification
and capture, support for parallel development by hardware and software
teams, and capabilities for reusing a complete system specification in
next-generation designs. CoWare N2C has been proven in customer
designs ranging from consumer electronics to multimedia devices to
telecommunications equipment.
CSELT SpA
Booth 2542
Via G. Reiss Romoli 274
Torino, 10148 Italy
(39) 11 2285220
http://www.cselt.it/cselt/
CSELT is the Telecom Italia Group’s centre for research in the field for
Telecommunications and Information Technology. VIP is a
synthesizable Very High Level Intellectual Property Library composed of
customizable system level of soft macros for designing application
oriented integrated circuits. The VIP application areas are: Information
and Communication Technologies, mainly in Fast Packet Switching
(ATM, TCP/IP), Video and Multimedia. A high performance IP Hard
macro library including low power memories, low swing pads, PLLs,
phase aligners, CAMs is also available.
Coware Ad
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Booth 344
3901 N. First St.
San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Derivation Systems, Inc.
Booth 1542
Cypress offers the most flexible In-System Reprogrammable (ISR™)
CPLDs and easy-to-use industry-standard design tools allowing you to get
your design right the first time. From SPLDs to 512-macrocell
Ultra37000™ CPLDs, Cypress makes your logic choice simple. New
architecture-independent Warp™ Verilog development tools enhance the
software suite of highly popular Warp VHDL tools which interface with
many EDA products. Since Cypress develops and owns its HDL synthesis
technology, you get the best results every time.
Booth SV38
See Cypress Semiconductor in SV38 and Booth #344. See the product
description in previous listing.
Denali Software, Inc.
Booth 428
Visit the Denali Software Exhibit to see why designers have adopted
Denali as the preferred solution in VHDL and Verilog for modeling
memories and for the verification of memory controllers. Denali’s toolset
enables designers to instantly create models of new memories and
embedded cores. The unique class-based architecture ensures the
reliability and structure necessary for modeling your key memory
specifications. Memory Modeler provides a powerful simulation
environment, accurate models, and interactive debugging features with
all HDL simulators.
104
The Formal Synthesis Company™. Derivation Systems introduces its
DERIVATION technology for synthesizing formally verified designs from
high-level behavioral specifications. Pre-verified synthesis steps are used
to refine a specification to a gate-level netlist or VHDL. The company will
debut DRS - Derivational Reasoning System™, a formal synthesis design
environment that supports an executable specification language, systemlevel codesign, interactive formal synthesis, and simulation.
Design Acceleration
Booth 818
1590 The Alameda
San Jose, CA 95126-2300
(408) 885-1885
http://www.designacc.com
3901 N. First St.
San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
644 Emerson St., Ste. 7
Palo Alto, CA 94301
(650) 325-7241
http://www.denalisoft.com
5963 La Place Ct., Ste. 208
Carlsbad, CA 92008
(760) 431-1400
http://www.derivation.com
DAI Signalscan DX is the highest performance/highest capacity waveform
viewing and source code debugging environment for Verilog, VHDL and
analog simulation. DAI Coverscan is a Verilog verification coverage
analysis tool providing state machine, statement execution, and decision
coverage information. DAI Comparescan is a rules-based analysis and
comparison program that is tightly integrated with DAI Signalscan DX for
efficient error analysis. The DAI SST2 Database is a high-performance
simulation database with TurboCompression for integrating into a custom
environment.
Design And Reuse
Booth SV11
5 Place Robert Schuman
Grenoble Cedex, 38025 France
(33) 476574687
http://www.design-reuse.com
Design And Reuse has launched its Yellow Pages on the web containing
over 1200 IPs from 76 providers. Design And Reuse is announcing at
DAC a key product which is an Internet/Intranet customized catalog
generator. As dedicated subproducts, D&R offers a VSI Alliance
compliant Internet/Intranet IP Java Catalog as well as a prototyping
version management system. In parallel, D&R proposes a software
environment for design and prototyping on multi FPGAs. It uses
exhaustively design hierarchy and offers an efficient mixmatch of
automatic/manual partitioning.
Cypress Ad
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DesignSoft
Booth 15
DynaChip Corp.
Booth 21
Csengery u.53.
Budapest, 1067 Hungary
(36) 1269-1206
http://www.designsoftware.com
1255 Oakmead Pkwy.
Sunnyvale, CA 94086
(408) 481-3100
http://www.dyna.com
TINA PRO is a powerful yet affordable software package for designing,
simulating and analyzing electronic circuits. It works equally well with
linear and non-linear analog circuits, digital and mixed circuits. The
standard library contains over 10,000 components and can be extended
by the user. Analysis results can be displayed as sophisticated diagrams
or on a range of virtual instruments. The new 32 bit version now includes
model parameter estimation, manufactures model library, advanced nonlinear magnetic models and schematic symbol editor.
DynaChip’s Active Repeater FPGA Architecture provides short, predictable
routing delays enabling 66 to 266 MHz operation. Two analog PLLs
multiply and divide clocks while reducing latency to 900 ps. On-chip dual
port RAM allows FIFO operation over 100 MHz, selectable LVTTL/GTL/PECL/LVDS interface levels feature 1.3 ns setup and 2.7 ns
clock-to-out delays and 10 clock trees provide 150 ps worst case skew.
Choose from a high-density, high-speed CMOS or super high-speed
BiCMOS
family
for
applications
in
telecommunications,
datacommunications, graphics, emulation, test and instrumentation.
Duet Technologies
Booth 1418
2833 Junction Ave., Ste. 100
San Jose, CA 95134
(408) 432-9200
http://www.duettech.com
Duet Technologies, Inc. is a leading provider of intellectual property (IP)
infrastructure solutions for high technology companies in the
semiconductor, computer, and networking industries. With the global
resource of more than 350 technical professionals, Duet specializes in
providing state-of-the-art semiconductor IP infrastructure components
including high performance IC physical libraries (standard cells, I/O cells,
and memory compilers) and comprehensive IP services including custom
library development, library migration, EDA tool integration and validation,
IP silicon verification services, and system-on-chip test services.
ECN Magazine/EITD
Booth 1538
201 King of Prussia Rd.
Radnor, PA 19089
(610) 964-4342
http://www.ecnmag.com
ECN provides product news and literature updates for design engineers
and engineering manager, in the electronic OEM. Published monthly, ECN
covers discrete and integrated circuits, components, computer software,
test equipment, power sources, packaging and materials. EITD, The
Electronic Industry Telephone Directory, is the only single volume national
directory for the EOEM. EITD lists over 30,000 sources of electronic
products and services. Check us out on the web—www.ecnmag.com.
EDA Standards
Booth 438
2500 Wilson Blvd.
Arlington, VA 22201
(703) 907-7545
http://www.eia.org/eig
The Electronic CAD to CAM Exchange (Ecce) program is developing a
solution to the CAD to CAM data exchange problem. Contract
manufacturers rarely receive an initial electronic data package that is
correct. A neutral format, based on the EDIF 4 0 0 information model (IM),
has been developed to ensure high-reliability of “first pass” data transfer.
See tools, which support the transfer of an Ecce message, demonstrated
by Mentor Graphics, GraphiCode, Orbotech, and Zuken Redac.
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EE Times/EDTN/CMP Media
Booth 1518
600 Community Dr.
Manhasset, NY 11030
(516) 562-7694
http://www.eet.com
EE Times is the community newspaper for design engineers and technical
and corporate managers in the EOEM industry. Its weekly coverage of
product and technology developments provides its 160,000 readers with
in-depth discussions of the applications and market segments where
these products and technologies are used. The Electronics Design,
Technology & News (EDTN) Network provides a comprehensive
collection of job critical information for electronics professionals. Industry
specific information is categorized into a News Center, EE Design Center,
E-Search, Career Center and includes content from EE Times, EBN, SBN.
Electronic Tools Co.
Booth 1934
928 First St. West
Sonoma, CA 95476
(707) 996-3320
http://www.e-tools.com
ETC’s mission is to produce the highest quality, most interoperable
interface software in the EDA industry, using widely accepted standards
such as EDIF, Verilog, VHDL, SI2, and IPC GENCAM. The EDA Interchange
Series™ alone offers over fifty different EDIF Version 2 0 0, 3 0 0, and
4 0 0 translators that interface with most EDA vendors. ETC’s tools can
be used to make a smooth transfer of Intellectual Property (IP) for CAD to
CAD and from CAD to CAM.
Engineering DataXpress, Inc.
Booth 825
2910 Stevens Creek Blvd., #109-736
San Jose, CA 95128
(408) 243-8786
http://www.dataxpress.com
Fo•cus (fo kes) v. 1. To concentrate attention or energy. Engineering
DataXpress focuses on our customers and their needs. Because we
realize that customer’s needs are unique, we offer a wide variety of
interoperability solutions. We have products for the integration, migration,
translation and reuse of schematic, netlist, HDL and PCB/MCM layout
design data. We also support EDIF 2 0 0, 3 0 0, 4 0 0, Verilog, VHDL and
most EDA vendors such as Cadence, Mentor, OrCAD, PADS, Synario,
Synopsys, VeriBest, Viewlogic, etc.
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Engineering
Data Xpress
Ad
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Eonic Systems Inc.
Booth 754
Rock Hill Rd., Ste. 120
Herndon, VA 20170
(703) 707-9500
http://www.eonic.com
Eonic Systems is an internationally recognized leader in the development
of innovative real-time system development tools targeted to the unique
needs of DSP and embedded RISC Core applications. Eonic Systems will
be demonstrating Virtuoso™ v.4, a complete RTOS development toolset
for designing scalable single and multiprocessor real-time applications.
Virtuoso™ includes: SoftStealth™ Technology which automatically
generates an application specific, optimized kernel with a minimum
memory footprint; Project Manager with easy to use development and
debugging tools; and, Host Server capability, which facilitates
communication with externel host computers.
Escalade Corp.
Booth 128
2475 Augustine Dr.
(408) 654-1605
http://www.escalade.com
Escalade creates powerful products for the authoring, delivery and end
use of IP for systems-on-a-chip designs. IP Guard provides unbreakable
protection and faster simulation for IP modules on all popular VHDL and
Verilog simulators. IP Guard is the only multi-language input tool that
generates VHDL, Verilog, and C. DesignBook offers block diagrams,
state diagrams, truth tables, flow charts and timing diagrams in addition
to HDLs. It is the tool of choice for multi-vendor IP integration. Design
Explorer automates multi-dimensional design space exploration.
Esperan
Booth 252
45 N. First St., Ste. 139
San Jose, CA 95113-1295
(408) 279-1300
http://www.esperan.com
Esperan is the world’s leading Verilog and VHDL training company. It is
an independent company, specializing in delivering classes which cover
the real issues, taught by trainers who are experienced in real design
work and who have the ability to really teach. Both standard and
customized courses can be delivered and group training can be given on
your site. Visit our booth to discuss your specific needs and to test drive
the latest MasterClass CD-Rom Verilog and VHDL tutorials.
Frequency
Tech. Ad
Fintronic Ad
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Everest Design Automation
Booth 2538
46563 Fremont Blvd.
Fremont, CA 94538
(510) 668-0640
http://www.everest-da.com
Formalized Design Inc.
Booth 78
Everest Design Automation’s first product, a multi-layer, gridless,
hierarchical unified routing and floorplanning system, is more than an
order of magnitude faster than current gridless routers. Integrated
floorplanning and timing driven functionality allow a design team to utilize
the same physical design tool from project conception through tape-out.
A graphical user interface makes the floorplanning and routing features
easy to use. An innovative hierarchical approach makes possible
accurate pin assignment and over the block routing, reducing chip area
and wire length.
EXD Technologies
Exemplar Logic
Booth 318
Leonardo Spectrum picks up where traditional Synthesis tools leave off.
It does more than begin with an RTL file or end with a netlist to place and
route. Leonardo Spectrum blends the industries hottest design creation,
simulation, synthesis and implementation technology into a simple,
seamless process designed to do the same job as you - design an FPGA
or ASIC. It’s a synthesis environment that views the world from the most
important perspective - Yours. Come see What FlowTabs™ PowerTabs™,
DesignInsight™, HDLIntegrator™, and much more.
Fintronic USA, Inc.
Booth 1524
1119 Chess Dr.
Foster City, CA 94404
(650) 349-0108
http://www.fintronic.com
3 Integrated Formal IC Verification Software Packages; LEQ Equivalency & Property Verification; integrated in one low priced
package for up to 32 million transistor Verilog or VHDL Designs. 10x - 50x
faster than ALL competitors. Labs - Logic Abstraction; input EDIF, Spice,
or Verilog transistors / gates and automatically output RTL Verilog or
VHDL. Layout to RTL Verification or re-target transistors / schematics to
RTL. MC-Check - Multi-Cycle Model Checking; verifies within specified
or infinite cycle periods that design properties, and design behavior are
implemented correctly using a temporal “Verilog” language called
Assertion Assistant.
Frequency Technology, Inc.
Booth 2200
See Silicon Access Inc. in Booth #108.
6503 Dumbarton Cr.
Fremont, CA 94555
(510) 789-3333
http://www.exemplar.com
3140 N. Arizona Ave., Ste. 116
Chandler, AZ 85224
(888) 303-CHIP
http://www.formalized.com
With over 1000 licenses sold, and between zero and two outstanding
bugs at any one time over the last twelve months, Fintronic’s FinSim
family of Verilog simulators is the first choice for people who care about
the quality and performance of the tools they are buying. Fintronic’s latest
product, FinSwHw, is a co-simulation Verilog-C environment, supported by
Super FinSim, the fastest Verilog simulator, reaching 100 million cycles
per second. Detailed timing information regarding the execution of the Ccode is produced.
100 Park Ctr. Plaza, Ste. 365
San Jose, CA 95113
(408) 938-9300
http://www.frequency.com
Frequency Technology, Inc. was founded to provide technology necessary
for designers to implement chips beyond the interconnect barrier. Unlike
existing EDA tool makers who are approaching the interconnect barrier by
tweaking their existing tools, Frequency has created a new way of
modeling integrated circuits which addresses the interconnect problem at
both the design and process level. Using Frequency’s True-3D™
Technology, designers will be able to accurately predict the performance
of interconnect wires in a deep submicron design, from a true, physical,
three-dimensional perspective, to accuracies within 10%.
Frontier Design
Booth 62
9000 Crow Canyon Rd., Ste. S-221
Danville, CA 94506
(510) 648-2683
http://www.frontierd.com
Frontier Design’s A|RT™ (Algorithm to Register Transfer) EDA tools
provide the ability to drive any HDL-based hardware design flow
directly from a C-code specification of the algorithm, enormously
increasing design productivity. A|RT™ Library facilitates the
development of fixed-point algorithms required for a silicon
implementation. A|RT™ Builder directly and automatically converts fixedpoint C-algorithms to VHDL or Verilog. Frontier Design also helps
customers in the wireless telecom, consumer audio and multimedia
areas to implement ASICs and FPGAs using its “Algorithm-to-Silicon™”
design methodology.
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FTL Systems, Inc.
Booth 256
1620 Greenview Dr. SW
Rochester, MN 55902
(507) 288-3154
http://www.ftlsystems.com
GateField Corp.
Booth 908
Your high-performance, full-language VHDL and VHDL-AMS simulation is
now affordable with Auriga (product shipments late 1998). Auriga’s many
technology firsts include:
* fully parallel compilation,
* parallel embedded scheduling combining event-driven accuracy with
cycle-driven performance,
* optimizing HDL compiler technology and
* semi-automated design translation from SPICE to VHDL-AMS.
Auriga’s analyzer is available for leading-edge OEMs via the draft AIRE/CE
standard interface.
Fujitsu/ICL
Booth 328
Wenlock Way West Gorton
Manchester, M12 5DR UK
(44) 161230-5757
http://www.icl.com/da
Fujitsu/ICL displays its leading technology solutions that support Systemlevel design, provide third generation formal verification and offer Highspeed PCB & MCM design tools. Visit our booth, listen to our
presentations and hear how we can accelerate your design time.
“SuperVISE” with VHDL+ introduces system specification, re-use
capabilities and interface-based design into your current methodology.
“ASSURE” offers a robust formal verification environment used
throughout Fujitsu. “Design Theater” offers an integrated PCB & MCM
design tool with its effective analysis of timing, heat and noise
capabilities.
Gambit Automated Design, Inc.
Booth 544
1101 S. Winchester Blvd.
Ste. C-120
San Jose, CA 95128
(408) 345-3555
http://www.gambit.com
Grandmaster™3.2 is packaged to give you unprecedented performance
and breakthrough technology for all of your VDSM Place and Route
needs. It is tightly integrated with Forecast™, the floorplanner that
facilitates timing driven design. Forecast works with OnTime™, the built
in timing analysis and synthesis engine, which acts as an early warning
system for your designs. With Gambit’s powerful clock tree synthesis
product, Synchron™, you will never again have to worry about meeting
your clock skew requirements.
112
47100 Bayside Pkwy.
Fremont, CA 94538-9942
(800) 818-5052
http://www.gatefield.com
GateField’s Programmable ASIC (ProASIC™) technology combines the
standard ASIC design flow with re-programmability and non-volatility.
ProASIC devices allow faster time-to-market than ASICs and have a cost
advantage over FPGAs. With GateField’s patented FLASH-based field
programmable technology, users can design and implement complex
solutions instantly at the desktop. ProASIC’s non-volatility, design reuse,
and bit stream protection make an ideal solution for IP delivery. See our
.25µ technology capability demo and test out the software yourself.
You’ll want your next design to be “Powered by ProASIC™”!
Genesys Testware
Booth 1154
181 Ottawa Way
Fremont, CA 94539
(510) 661-0791
http://www.genesystest.com
Genesys Testware is a leading provider of system on chip test solutions.
The TestCore family of parameterized, synthesizable, RTL designs provide
easy to use, flexible and feature rich Built-In Self-Test (BIST) and
boundary scan solutions. Memory BistCore supports BIST of all types of
embedded memories. Logic BistCore provides BIST of on-chip logic and
enables test re-use in re-usable designs. Boundary ScanCore simplifies
testing of surface mount technology boards. It also provides capabilities
to integrate test capabilities of different cores in a system on chip.
Genias Software GmbH
Booth 154
Erzgebirgstr. 2
Neutraubling, D-93073 Germany
(49) 9401-92000
http://www.genias.de
CODINE is a software suite which optimizes resource utilization and
computer run times in a heterogeneous computing environment (i.e. a
pool of workstations and servers with different operating systems) and
provides a single-system image (virtual mainframe) to users and systems
administrators. In EDA, CODINE can speed the verification cycles without
sacrificing the accuracy needed.
Esperan Ad
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GLOBEtrotter Software, Inc.
Booth 139
1530 Meridian Ave.
San Jose, CA 95125
(408) 445-8100
http://www.globetrotter.com
IBM Corp.
Booth 1318
Take control of licensing with FLEXadmin. FLEXadmin is the leading
software asset manager that fully works with your FLEXlm licensed
managed applications. FLEXadmin also manages applications without
FLEXlm when you wrap them with FLEXwrap. Simplify your software
license administration and maintenance efforts, while gaining greater
understanding of how your organization uses software. FLEXadmin gives
you the ability to put your budget for software licenses, upgrades and
service to its best use.
IBM features next-generation solutions for EDA from concept through
manufacturing. The array of choices from IBM to solve your business
challenges is unrivaled in the industry. See how IBM can assist you in
evaluating and integrating your UNIX and NT requirements. See our
RS/6000 SP servers, AIX Workstations, and IntelliStations deploying
solutions from our partners. Visit the IBM Blue Logic Technology kiosk
and see our multimillion gate designs for System-Level-Silicon. Let IBM
help you make the right move!
Hewlett-Packard Co.
Booth 1530
IBM Corp.
Booth SV1
3404 E. Harmony Rd.
Fort Collins, CO 80528-9599
(800) 637-7740
http://www.hp.com
1798 NW 40th St.
Boca Raton, FL 33431
(561) 443-8108
http://www.ibm.com/MFG/
Need to solve BIG design problems? NOW YOU CAN at HP’s DAC booth
#1530.
See IBM Corp. in SV1 and Booth #1318. See the product description in
previous listing.
HP provides the most powerful UNIX & NT, workstations and servers for
your critical design bottlenecks. Come talk to our system designers. Find
out about HP’s technology roadmap for 64-bit HP-UX and learn about
upcoming PA-RISC processors. They are your best path to MERCED and IA64. Stop by and eliminate annoying design flaws by playing our new EDA
game and compete for prizes against your friends! Then take a copy home.
IKOS Systems Inc.
Booth 1328
HyperLynx
Booth 632
17641 NE 67th Ct.
Redmond, WA 98052
(425) 869-2320
http://www.hyperlynx.com
HyperLynx is the leading supplier of signal-integrity and EMC analysis
software for Windows PCs. HyperLynx tools solve high-speed problems
before fabricating PCBs, preventing costly board revisions.
Products:
•LineSim
- Pre-layout signal-integrity analysis. Design for high-speed
effects before layout even begins.
•BoardSim - Post-route signal-integrity analysis. Reads routed PCBs from
15 different layout packages.
•EMC add-on - Adds EMC analysis to BoardSim/LineSim.
•Cross Talk add-on - Adds CrossTalk analysis to BoardSim/LineSim.
•HyperSuite - An integrated combination of pre and post layout HyperLynx
software.
114
1798 NW 40th St.
Boca Raton, FL 33431
(561) 443-8108
http://www.ibm.com/MFG/
19050 Pruneridge Ave.
Cupertino, CA 95014
(408) 255-4567
http://www.ikos.com
IKOS Systems, Inc. is a technology leader in high-performance design
verification solutions including hardware and software simulation for
language-based design, logic emulation for hardware/software coverification, and verification services. The Company’s mission is to help
customers realize their high complexity electronic systems through
innovative design verification solutions. IKOS supports direct sales
operations in North America, UK, France, Germany, and Japan, and a
distribution network throughout Europe and Asia.
FTL
Systems Ad
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xhibit guide
INCASES North America
Booth 636
Integrated Intellectual Property Inc.
Booth 656
301 Commerce St., Ste. 1320
Fort Worth, TX 76102
(817) 332-7422
http://www.incases.com
Gambord Plaza
1765 Scott Blvd., Ste. 208
(408) 260-3970
http://www.i2p.com
Indus Consulting Services, Inc.
Indus Consulting Services, Inc. has changed their name to Integrated
Intellectual Property Inc. see Booth 656.
InfoQuick
Booth 88
2 Executive Cr., Ste. 150
Irvine, CA 92614
(714) 221-0535
http://www.info-quick.com
InfoQuick introduces WebStir™ for Workgroups, an affordable tool that
hosts an on-line subscription service for obtaining the latest electronic
component information quickly and easily, enabling designers to make
the best component decisions for their designs. Using WebStir in a
Microsoft® Windows® 95 or NT environment, designers can access
component information from many Websites without having to launch a
Web browser. Talon™, the patent-pending backend suite of tools
continually discovers, maintains and relinks specific information on
manufacturers’ Websites to InfoQuick’s Web server.
Inicore
Booth SV15
44350 Grimme Blvd.
Fremont, CA 94528
(510) 445-1529
http://www.inicore.com
Inicore is a system design house that is specialized in the development
and implementation of system-level turnkey projects. It also has
pioneered the concept of easy-to-use, intellectual property cores for FPGA
and ASIC technologies due to its proven design methodology. Cores are
provided for applications such as DSP, CANbus, CPU, UART, VME, I2C,
HDLC, UTOPIA, G704, xDSL. These easy-to-use cores are optimized for
time-to-market sensitive high-level system integration. The company
provides products and services, which support the entire integrated
circuit design process from system analysis to working products.
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Integrated Intellectual Property, Inc. provides cores for standard bus inter
connectivity market. SuperLINKCore™ and SuperPHYCore™ are a Firewire
IEEE 1394 synthesizable cores. Super1394Sim™ is a Firewire IEEE
1394 verification environment designed for maximum flexibility and can
be used to exhaustively verify your 1394 LINK or PHY design under test.
SuperAGPTargetCore™ and SuperAGPMasterCore™ are AGP synthesizable
cores. SuperAGPMasterSim™ and SuperAGPTargetSim™ are a fully
compliant AGP simulation model package. SuperPCICore™ provides the
most comprehensive PCI 2.1 synthesizable core.
Integrated Silicon Systems Ltd.
Booth SV14
50 Malone Rd.
Belfast, BT9 5BS N. Ireland
(44) 1232664664
http://www.iss-dsp.com
ISS is the leading provider of DSP and Telecommunications IP cores for ASIC
and programmable logic implementation. The company has an exciting
range of high quality, hard, firm and soft cores which it will customize to the
exact requirements of target applications and implementations.
Integrated System Design
Booth 1050
954 San Rafael Ave.
(650) 988-9677
http://www.isdmag.com
Integrated System Design is the only magazine dedicated to design
methodology for engineers dealing with next generation design issues,
including system on a chip, embedded systems, test, design reuse,
intellectual property, and the use of Unix and NT workstations. We are
located in the heart of Silicon Valley, and reach a highly-targeted audience
of 70,000 leading edge designers. Our editorial, all written by and for real
system engineers, has earned us the reputation as the definitive user
advocate in the world of electronic design.
IKOS Ad
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Intellitech Corp.
Booth 1350
70 Main St.
Durham, NH 03824
(603) 868-7116
http://www.intellitech.com
Intercept Technology Inc.
Booth 1752
Intellitech will demonstrate 3rd generation Scan Tools for silicon debug.
The enterprise-wide (Unix & Windows) solution provides an efficient user
interface, scan vector creation and high-speed vector application to
reduce your prototype debug and development time. If you’re using BIST,
designing with IP cores or performing path delay tests, Intellitech Scan
Tools can help!
Intellx
Booth 956
3481 Dayton-Xenia Rd.
Dayton, OH 45432
(937) 426-3111
http://www.intellx.com
MISTIE, a mixed signals design environment developed by the team of
MTL Systems, Inc. and the University of Cincinnati, will be demonstrated.
Funded by the Air Force Research Laboratory and the Defense Advanced
Research Projects Agency (DARPA), MISTIE is a Mixed-Signal Technology
Integration Environment providing the designer an environment for
analog and mixed signal design. MISTIE provides the same design
automation capability VHDL provides for digital systems designers and
meets the need for multi-level abstraction and compliance with the VHDLAMS standard.
Interactive Image Technologies Ltd.
Booth 1930
111 Peter St., Ste. 801
Toronto, ON M5V 2H1 Canada
(416) 977-5550
http://www.interactive.com
Interactive Image Technologies specializes in developing and marketing
electronic design and automation tools for windows-based computing
platforms. The flagship product, Electronics Workbench, is the world’s
most widely used circuit design software. Electronics Workbench offers
fully integrated schematic capture, mixed analog-digital simulation and
waveform capabilities all in one comprehensive package. Electronics
Workbench Layout, completes the design cycle as an integrated printed
circuit board design software package. EWB Layout comes with powerful
features common to most high-end PCB design tools, including on-line
design-rule-check and advanced auto-routing capabilities. More than
90,000 copies of Electronics Workbench have been sold and the product
has been translated into 8 languages.
118
1819 Peachtree Rd.
Atlanta, GA 30309
(404) 352-0111
http://www.intercept.com
Intercept Technology’s integrated Pantheon PCB/Hybrid/MCM
application provides a high technology design solution. Features include
artwork verification, full WYSIWYG, buried vias, blind pins, split power
planes, embedded traces, circular cutouts, and area fill with plowing and
healing. Modify net connectivity and add or delete components with
automatic database and layout updates for rapid prototyping. Pantheon
interfaces with cross-probing to OrCAD Capture™ for Windows®, CCT
SPECCTRA® ShapeBased Autorouter, HP EEsof’s MDS™ and Series IV RF
design software. UNIX and Windows 95/NT supported.
interHDL, Inc.
Booth 1918
4984 El Camino Real, Ste. 210
Los Altos, CA 94022
(650) 428-4200
http://www.interhdl.com
The leader in HDL analysis presents advanced verification capabilities.
Offering more than just an RTL syntax and style checking. interHDL now
provides new HDL analysis and verification capabilities such as: power
analysis, testability analysis, clock domain analysis, asynchronous loop
detection, analysis of coding errors, and identification of questionable
coding constructs and semantics which can impact simulation and
synthesis results. Synopsys endorses interHDL’s support for Design Reuse Methodology as specified in the Reuse Methodology Manual.
International CompuTex Inc./Information
Handling Services
Booth 64
15 Inverness Way East
Englewood, CO 80112-5704
(303) 397-2300
http://www.ihs.com
International Computex, Inc. (ICL), and Information Handling Services (IHS)
deliver the newest alternative for Component Supplier Management. ICL’s
ItemQuest distributed virtual CSM system enables engineering,
procurement, and manufacturing to integrate disparate information on
components, suppliers, and product design. Now, users can quickly
access product-related information located anywhere within a corporation:
legacy systems, remote departments, content providers (such as IHS),
supplier databases, other business systems, even the Internet. This
enables Best Practices such as preferred parts reuse, parts
standardization, and supplier and parts consolidation.
Hewlett
Packard Ad
Formalized
Design Ad
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xhibit guide
Interra, Inc.
Booth 1546
2001 Gateway Pl., Ste. 440W
San Jose, CA 95110
(408) 573-1400
http://www.interrainc.com
The fastest road to EDA tool development is through “Interragration”.
Interra’s EDA-IP toolkit offers customizable software components for EDA
tool developers and semiconductor vendors. These components help to
rapidly turn ideas into quality products. Modules are available for
VHDL/Verilog analysis, translation, test, debugging and RTL synthesis.
Interra is introducing two new components: Concorde™ Super Fast RTL
Synthesis and NOM™-Netlist Object Model. Interra also offers
comprehensive consulting services to develop custom modules. See
what partnering with Interra can do for you. Visit us at booth #1546.
Intrinsix Corp.
Booth 2528
33 Lyman St.
Westboro, MA 01581
(508) 836-4100
http://www.intrinsix.com
Intrinsix is the leading independent provider of design services for ASIC
and High Integration Embedded Systems. At DAC ‘98 Intrinsix is
introducing its proprietary microPlatform design paradigm which
combines ASIC design, verification, embedded software, and integration
of IP cores. With over 150 designers, Intrinsix has outsourcing models
for ASIC design and verification in its 15 design centers. Through
extensive relationships with every provider of ASIC/EDA/IP technology,
Intrinsix offers unbiased and unparalleled design solutions.
Intusoft
Booth 141
222 W. Sixth St., Ste. 1070
San Pedro, CA 90731
(310) 833-0710
http://www.intusoft.com
Established in 1985, Intusoft is a leading supplier of circuit simulation
and test synthesis and sequencing software to Fortune 500 Electronics
companies worldwide. Products include: Power Designer (NEW), the most
comprehensive design synthesis and analog/mixed-signal circuit
simulation software package for Power Engineers; Intusoft’s flagship
product - ICAP/4 Windows, and IsSpice-based simulation program with
separate product options for OrCAD, Intusoft or Protel schematic entry;
Test Designer, a revolution in Test, performs fault diagnostics, fault tree
generation, acceptance test design.
Interra Ad
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xhibit guide
K2 Technologies/Shearwater Group
Booth 2308
LEDA SA
Booth 445
P.O. Box 2423
Vashon, WA 98070
(206) 463-6288
http://www.shearwater.com
35 Avenue Du Granier
Meylan, 38240 France
(33) 47641-9243
http://www.leda.com
K2 presents a full suite of products for IC physical verification, automated
reticle design synthesis, and tape-out. Product functions include:
sophisticated, full featured DRC, LVS and parasitic extraction, frame
generation, wafer layout, paperwork generation, manufacturing layer
derivation, OPC, fracturing, PG jobdeck generation, and fast display and
overlay of data in its various formats from GDSII through jobdeck. Benefits
include reduced cost, faster cycle times and elimination of errors.
Kluwer Academic Publishers
Booth 926
101 Philip Dr.
Norwell, MA 02061
(781) 871-6600
http://www.wkap.nl
Visit Kluwer Academic Publisher’s Booth No. 926 to browse through
newly published books offering the latest research and developments in
design automation. Featured books include the NEW Fourth Edition of
the classic THE VERILOG® HARDWARE DESCRIPTION LANGUAGE by D.E.
Thomas and P.R. Moorby; VHDL Answers to Frequently Asked Questions,
SECOND EDITION by Ben Cohen; VHDL and FPLDs in DIGITAL SYSTEMS
DESIGN, PROTOTYPING AND CUSTOMIZATION by Zoran Salcic; REUSE
METHODOLOGY MANUAL FOR SYSTEM-ON-A-CHIP DESIGNS by Michael
Keating and Pierre Bricaud, along with many others!
Lattice Semiconductor Corp.
Booth SV39
5555 NE Moore Ct.
Hillsboro, OR 97124
(503) 693-0567
http://www.latticesemi.com
Lattice Semiconductor Corporation, the pioneer of In-System
Programmable (ISP) products, provides the broadest range of high-density
ISP™ complex programmable logic devices (CPLDs) and powerful
Development Software. Lattice’s ISP CPLDs have revolutionized the
electronics industry, shortening design cycles and reducing development
costs, while featuring speeds as high as 180 MHz (Fmax), and offering
5V and true 3.3V versions. With its ispDS+™ HDL Synthesis-Optimized
Logic Fitter, combined with leading CAE tools from Synopsys/Viewlogic,
Synplicity and Minc/Synario, Lattice offers the strongest ISP and
ispHDL™ solutions in the industry.
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LEDA offers complete HDL front-end solutions on UNIX and Windows-NT
platforms that integrate fast and reliable compilers for VHDL’87/93,
VHDL-AMS and Verilog, and generic elaborators for VHDL’97/93 and
VHDL-AMS. LEDA also offers designer tools such as its new VHDL
Programmable Design Rule Checker (Proton), VHDL source-to-source
encryptor (Krypton) and elaborator (Helios), and a customizable
VHDL/Verilog Source and Library Manager (VHDL *Verilog Design Studio).
Finally LEDA proposes technology partnerships for the development of
advanced HDL-based CAD tools.
Legend Design Technology, Inc.
Booth 752
168 Alvarado Ave.
Los Altos, CA 94022
(650) 941-5168
http://www.legenddesign.com
IP (mega-cell) characterization, especially memory design, requires EDA
tools for performance, accuracy and feasibility. Legend Design
Technology, Inc. provides following IP characterization products:
GDS-Cut: layout reduction to reduce layout extraction time
SpiceCut: circuit reduction to reduce circuit simulation time
RC-Cut: AWE-based RC reduction to reduce circuit size
SpiceCut-Memory is a characterization program for timing and power. Not
only access time, but also setup/hold time and minimum clock width can
be accurately characterized.
Library Technologies, Inc.
Booth 2150
19959 Lanark Ln.
Saratoga, CA 95070
(408) 741-1214
http://www.libtech.com
BlockChar is a Dynamic Timing and Power Analyzer which generates state
dependent high accuracy timing and power models for custom blocks.
UnBlock is a custom block partitioning and verification tool. IcPower is a
dynamic accurate power simulator integrated into Verilog. Pli-CalcRC is a
simulation based interconnect analysis tool. LibChar is the most advanced
cell timing and power characterizer, with functional verification, stimuli and
state dependency generation capabilities. SynGen and VeriGen are
Synopsys and Verilog library generators. DocGen generates data-sheets.
Integrated
System
Design Ad
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xhibit guide
LightSpeed Semiconductor
Booth 1156
LogicVision, Inc.
Booth 218
1151 Sonora Ct.
Sunnyvale, CA 94086
(408) 616-3200
http://www.lss-asic.com
101 Metro Dr., Third Fl.
San Jose, CA 95110
(408) 453-0146
http://www.logicvision.com
LightSpeed Semiconductor targets mainstream ASIC designs with an
innovative Module Based Array architecture that can dramatically reduce
both design and production cycles for complex, high-performance
systems. LightSpeed uses standard ASIC tools and flows, yet
significantly reduces design time by (1) eliminating test development
while providing 100% stuck-at fault coverage, and (2) offering place, route
and delay in as little as one day. LightSpeed significantly reduces ramp
time for production volumes, delivering overall time to production savings
of eight to 24 weeks.
LogicVision will be showing icBIST3.0™, the most complete suite of test
and diagnostic solutions for complex systems, SOCs and ASICs that
depend on very deep sub-micron semiconductor technology. icBIST3.0
provides at-speed test and diagnostic capabilities for user logic,
embedded memories, mixed-signal cores and legacy cores at the chip
level, and for interconnects and memory modules at the board level.
icBIST3.0 saves engineering time and manufacturing costs by
significantly reducing the test development effort and the ATE
requirements for at-speed test and diagnostics of high-end products.
LogicVision is a proven supplier of test solutions to over 40 leading
companies in computers, communications, mil/aero and
semiconductors. Put us to the Test!
LightSpeed Semiconductor
Booth SV8
1151 Sonora Ct.
Sunnyvale, CA 94086
(408) 616-3200
http://www.lss-asic.com
LSI Logic Corp.
Booth 536
See LightSpeed Semiconductor in SV8 and Booth #1156. See the
product description in previous listing.
Linius Technologies
Booth 444
276 Turnpike Rd.
Westborough, MA 01581
(508) 616-9360
http://www.linius.com
Linius Technologies presents EMbassy - a complete wire harness design
environment that enables harness routing within the context of a 3-D
assembly while maintaining the electrical characteristics of the signals.
EMbassy merges 2-D logical connectivity with 3-D mechanical data
creating a 3-D virtual prototyping environment. EMbassy imports electrical
and mechanical information using industry standards, including EDIF,
VRML, and IGES. This environment ensures that key design and
manufacturing information is captured once and used consistently
throughout the entire harness design process.
1551 McCarthy Blvd.
Milpitas, CA 95035
(408) 433-8000
http://www.lsilogic.com
Ever wish you could tour a design center prior to starting a new design?
Now you can. Stop by LSI Logic’s booth to meet engineers from our
worldwide design centers and discuss your biggest design issues. Our
engineers will talk from experience about integrating ASIC technology and
IP into multi-million gate system-on-a-chip solutions. Come see how our
design center engineers use the FlexStream™ Design Solution to make
system on a chip a reality.
Lucent Technologies, Bell Labs Design
Automation
Booth 1008
600 Mountain Ave., Rm. 3B-433
Murray Hill, NJ 07974-0636
(800) 875-6590
http://www.bell-labs.com/org/blda
Bell Labs Design Automation is a provider of a complete line of leadingedge verification products for systems-on-silicon and other advanced
applications. FormalCheck™, a formal verification product, makes modelchecking of complex designs a reality. ATTSIM™, our single-process
mixed signal simulator, utilizes a unique architecture and an efficient
partitioning scheme to tackle your most troublesome mixed signal
designs. We also offer a comprehensive set of DSM parasitic extraction
tools. Look to BLDA to continue to harness tomorrow’s technologies to
solve today’s problems.
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EDAC Ad
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Lucent Technologies, Microelectronics
Group, FPGA
Booth SV5
555 Union Blvd., Rm. 30L-15P
Allentown, PA 18103
(610) 712-5164
http://www.lucent.com/orca
Discover the Freedom to Create™ with Lucent programmable solutions.
Our ORCA® Foundry Development System is an ASIC-quality, timing-driven
tool suite for ORCA FPGA Design. Customer Solution Cores are fully
verified soft IP solutions for popular functions like PCI, ATM, and UTOPIA
interfaces. Our Series 3 FPGAs offer 48,000 to 340,000 gates capable
of 160 MHz clock speeds. The new ORCA Series 3+ field-programmable
system-on-a-chip combines 40,000 programmable gates and a 64-bit PCI
interface in a single solution.
Lucent Technologies, Microelectronics
Group, PSS
Booth SV6
555 Union Blvd., Rm. 30L-15P
Allentown, PA 18103
(610) 712-5164
http://www.lucent.com/orca
Mechtronix, Inc. has changed their name to Linius Technologies, see
Booth #444.
Booth 1108
Welcome to the age of deep submicron - a new area in IC technology. As
designers dive ever deeper into the submicron depths, they encounter a
strange new world filled with fantastic pressures and novel design
methodologies. To successfully navigate this new abyss, Mentor
Graphics brings you its technology leadership in design verification and
intellectual property. Featured products will include a front-to-back
collection of tools for design creation, design for test, analog/mixedsignal, physical extraction, hardware/software co-verification and high
speed printed circuit board design.
126
927 W. Center St.
Orem, UT 84057
(801) 226-4470
http://www.microcode.com
CircuitMaker PRO®-Professional schematic capture and simulation
software program at a fraction of the price of “high-end” tools. Supports
analog, digital and mixed-mode simulation, with 11 advanced analyses
and 8 virtual instruments. Features over 6,000 devices, and built-in
symbol editor and macro feature. TraxMaker PRO®-The most affordable
professional-quality PCB design tool available. Supports 8 layers, boards
up to 32” X 32”, and includes a fully-documented library of 5,400
component footprints. Imports most PCB netlist formats. Outputs
RS274X Gerber files, Excellon N/C drill files.
MicroSim Corp.
It’s A Whole New World of EDA with the merger of OrCAD and MicroSim.
Join us to learn how to make your design process a competitive
advantage for your company with the new 9.0 Release of OrCAD and
PSpice brand products.
MINC/Synario
Booth 1824
Mechtronix, Inc.
(503) 685-1183
http://www.mentorg.com
MicroCode Engineering Inc.
Booth 348
6755 Earl Dr.
Colorado Springs, CO 80918
(719) 590-1155
http://www.synario.com
MINC Incorporated, makers of the Synario® line of “Ready-to-Use”
Windows EDA software, offers a variety of schematic capture, logic
synthesis, and simulation tools for programmable logic and board design.
This tightly integrated tool suite provides a complete design environment
for FPGAs, CPLDs, and PLDs. MINC’s VHDL EASY and VHDL EASY SIM
offer full VHDL synthesis and simulation delivering a complete design
environment at a very low cost. MINC’s broad product line answers the
needs of any budget or environment.
Mentor Ad
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xhibit guide
Model Technology, Inc.
Booth 1830
8905 SW Nimbus Ave., Ste. 155
Beaverton, OR 97008
(503) 641-1340
http://www.model.com
Moscape Inc.
Booth 22
Model Technology Incorporated (a Mentor Graphics Company) is the
leading HDL simulation provider with over 18,000 designers using
M o d e lSim for VHDL, Verilog, and mixed-HDL simulation. With the
industry’s only single-kernel, dual-language simulator - ModelSim enables
a language neutral simulation strategy. Its Optimized Direct Compile
architecture provides the fastest compile times, leading-edge runtime
performance, and hardware platform independence. Whether it is VHDL
or Verilog, PCs or Unix workstations, multi-million gate ASICs or
mainstream FPGAs - ModelSim is The Ultimate Tool for HDL Simulation.
Morgan Kaufmann Publishers, Inc.
Booth 2530
340 Pine St., Sixth Fl.
San Francisco, CA 94104
(415) 392-2665
Morgan Kaufmann publishes the finest technical information resources
for computer science and engineering professionals. We publish in book
and digital form in such areas as computer architecture, databases,
networking, human computer interaction, computer graphics, multimedia
information systems, artificial intelligence, and software engineering.
Many of our books are considered to be the definitive works in their fields
such as Peter Ashenden’s The Designer Guide to VHDL and The
Students Guide to VHDL.
Morphologic, Inc.
Booth 552
131 D.W. Hwy., Ste. 470
Nashua, NH 03060
(603) 880-4263
http://www.morphologic.com
Morphologic’s Evolution is a multi-device, multi-vender FPGA tool set that
provides the fastest path between design concept and working hardware.
By capturing design requirements up front, Evolution automates the task
of tracking performance and resource constraints. Even when design
elements are moved among devices using the included multi-chip
floorplanner, Evolution’s advanced features yield deterministic,
repeatable results that set the stage for a complete route on the first
pass. (Win 95/NT; Supports all LCA & NCD-based designs.)
128
Box 360260
Milpitas, CA 95036
(408) 946-2850
http://www.moscape.com
Moscape will be premiering state of the art products aimed at improving
performance and reliability of complex deep submicron IC designs. It
performs assertion based analysis of static and dynamic circuits, prevents
circuit failures and repairs detected problems. It tightly integrates logic
and physical designs and significantly reduces design iterations. These
products are based on a proprietary and proven static analysis technology.
Custom and standard cell based designs are analyzed using a unified
engine working on mixed gate and transistor level representations.
MyCAD, Inc.
Booth 2030
574 Weddell Dr., Ste. 6
Sunnyvale, CA 94089
(408) 745-6785
http://www.mycad.com
MyCAD, Inc. is well known for the MyChip Station, a powerful full custombased IC layout and verification package in windows. This year we are
very excited to show a preview of MyChip Station V3.5 and also a
schematic entry of SPICE generation package, MyLogic Station™ V3.5.
The last but not least, VHDL modeling and simulator which supports IEEE
1076-1987 standard, MyVHDL Station™ V3.5 will be introduced.
Newport Wafer-Fab Ltd.
Booth 14
San Jose, CA 95131
(408) 436-3050
http://www.newportwafer.com
Novas Software, Inc.
Booth 23
826 N. Hillview Dr.
Milpitas, CA 95035
(408) 941-0988
http://www.novassoft.com
Debussy™, The Engineer’s Desktop™ is an integrated debug & analysis
environment for Verilog HDL/VHDL and mixed-signal simulation,
including: nTrace: Most advanced HDL source debug, edit & analysis.
nWave: Object-oriented-context-sensitive drag-n-drop, mixed-level
simulation comparisons.
nSchema: Automatic HDL source visualization, 10x faster debug of
synthesis results, back-tracing.
FSDB: Fast Signal Data Base & Open-API.
nState: NEW!
Debussy accelerates source code & state machine debug of HDL designs
and internal/external IP designs. Debussy significantly enhances
productivity from architectural concept, implementation through tape-out.
Model Tech
Ad
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Nu Thena Systems, Inc.
Booth 1850
1430 Spring Hill Rd., Ste. 220
McLean, VA 22102
(703) 356-5056
http://www.nuthena.com
Nu Thena’s flagship product, FORESIGHT, is a systems design toolset
which incorporates a systems-level design language and a
comprehensive simulation and analysis environment. FORESIGHT
enables system design engineers to verify functional requirements early,
optimize system architectures, and perform hardware/software codesign.
FORESIGHT’s seamless integrations with downstream EDA tools and
embedded software design tools ensures an accelerated design flow.
Example applications in which FORESIGHT has demonstrated excellent
returns on investment include avionics, satellite communications,
telecommunication switches, and set-top boxes.
Numerical Technologies, Inc.
Booth 71
2630 Walsh Ave.
(408) 919-1920
http://www.numeritech.com
The complete solution to advanced mask software - design, verification,
analysis and inspection. Numerical Technologies provides the world’s
fastest optical proximity correction (OPC) and phase-shifting mask (PSM)
design and verification tools for reducing transistor gate lengths, shrinking
die sizes and improving process yield. The suite also includes advanced
process analysis, fast simulation and parameter optimization tools.
Numerical Technologies’ architectural approach simplifies integration of the
suite into exisiting EDA software applications including layout verification,
and extraction tools. From IC design through manufacturing, Numerical
Technologies’ solution enables manufacturers to develop and deliver costeffective, high-yield deep sub-micron technology.
NurLogic Design, Inc.
Booth 16
6450 Lusk Blvd., Ste. E206
San Diego, CA 92121
(619) 455-7570
http://www.nurlogic.com
NurLogic provides a full line of leading-edge Physical Intellectual Property
components. These process-specific building blocks include high
performance digital and mixed signal standard cell libraries, I/Os,
memories, and analog components. In addition, NurLogic offers ASIC
backend services utilizing our products. We differentiate our advanced
product portfolio by offering customers solutions that: 1) offer improved
performance, 2) focus on accurate characterization, 3) maximize the
performance of customers current EDA tool investment, and 4) are a
reliable and quality solution.
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ACM Ad
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OEA International, Inc.
Booth 2034
3235 Kifer Rd., Ste. 300
(408) 738-5972
http://www.oea.com
OEA offers the industry’s fastest 2D/3D field simulators for accurate
parasitic extraction and a consulting service for IC and packaging
designers. The latest NET-AN, CELL-AN & P-GRID utilize the new ‘Cheetah
II’ solver technology to deliver the only true full 3D field solutions
available for accurate 3D critical multi-net extraction, full 3D cell SPICE
extraction, and 3D power distribution network analysis. For the analog
and mixed signal designers, the latest SPIRAL inductor design tool, will
make it’s premiere release showing.
Omniview Design, Inc.
Booth 530
100 High Tower Blvd., Ste. 201
(412) 788-9492
http://www.omnivw.com
Omniview Design, Inc. provides solutions to the problems of rapidly
increasing design complexity combined with shrinking product life cycles.
Omniview Cosmos™ provides a hardware/software performance analysis
environment where engineers can model hardware and software
subsystems separately at the architectural level and perform tradeoff
analysis to determine the optimal architecture and allocation of
functions. Omniview Galaxy™ provides a complete design reuse
environment where parameterized designs and design fragments can be
captured along with rules and constraints for future design reuse.
Open Verilog International (OVI)
Booth 1540
15466 Los Gatos Blvd., Ste. 109071
Los Gatos, CA 95032
(408) 358-9510
http://www.ovi.org
Open Verilog International is a not-for-profit standards organization with
the mission of furthering the evolution, enhancement and usage of Verilog.
OVI has made a great deal of progress in standards activities over the past
few years, and is widely recognized as one of the most proven and
effective organizations in moving ahead standards that shape the Verilog
language and impact the future of the design automation industry.
DAC Survey
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OPMAXX, Inc.
Booth 338
8209 SW Cirrus Dr.
Beaverton, OR 97008
(503) 520-9200
http://www.opmaxx.com
Pacific Numerix Corp.
Booth 228
OPMAXX delivers a family of Mixed-signal Design & Test Automation software
for yield analysis and improvement, mismatch analysis, analog fault
coverage and testability analysis aimed at helping engineers create designs
for a targeted manufacturing process. OPMAXX is introducing Oscillationbased Built-in Self-test (BIST) focused on solving critical functional and
structural test problems of IP and analog design blocks thus providing
extremely high performance testing with very low overhead and cost. A
common design methodology is applied to analog and digital blocks.
OptEM Engineering Inc.
Booth 1522
100 Discovery Pl. One
3553-31 St. NW
Calgary, AB T2L 2K7 Canada
(403) 289-0499
http://www.optem.com
Interconnects play a significant role in the design of today’s highperformance digital systems. OptEM Engineering is a pioneer in
developing CAE software and services that focus on the fundamentals of
interconnect analysis - fundamentals that include RLCG parasitic
extraction, signal interaction between interconnects, design rule
definition, and SPICE model generation and analysis. OptEM offers a
comprehensive suite of software tools for submicron ICs, advanced IC
packages, and cable/connector systems. Stop by and find out how we
can provide solutions to your design challenges.
OrCAD
Booth 1018
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
http://www.orcad.com
Visit OrCAD and we’ll show you how your design process can become a
real competitive advantage for your company. You’ll see our new,
integrated 9.0 Release of design applications for the Windows NT
enterprise. These powerful products are ideal for designing FPGAs,
CPLDs, and PCB systems; analog and mixed-signal design and
simulation; PCB layout, including options for high-speed design; and, for
Internet-enabled design with OrCAD’s unique Component Information
System products.
132
7333 E. Doubletree Ranch Rd., Ste. 280
Scottsdale, AZ 85258
(602) 483-6800
http://www.pnc.com
Pacific Numerix Corporation markets the Electronic Design Validation
System (EDVS) product, a simulation based global integrated engineering
communications system. “EDVS” improves a company’s design-tomanufacturing process by accurately accounting for the 3D physical
effects on signal integrity, EMC, ground bounce, thermal management,
vibrational structural integrity, interconnect fatigue, and manufacturability.
“EDVS” performs virtual prototyping and manufacturing.
PADS Software, Inc.
Booth 630
165 Forest St.
Marlborough, MA 01752
(800) 554-7253
http://www.pads.com
PADS introduces PowerBGA, our universal solution for high density
interconnect packaging. PowerBGA automates the interconnect process
between bare die and its underlying substrate. It supports chip on board,
ball grid arrays, chip scale packages, and laminate-based multi-chip
modules, as well as printed circuit board design, based on PADSPowerPCB technology. Includes features such as Bare Die Definition,
Automatic Wire Bond Fanout, and comprehensive layout editing support,
to eliminate the manual design process which saves time and simplifies
your complex packaging efforts.
Palmchip Corp.
Booth 20
2055 Gateway Pl., Ste. 240
San Jose, CA 95110
(408) 487-8690
http://www.palmchip.com
Palmchip Corporation is a developer and supplier of System-on-Chip
(SOC) solutions, including synthesizable IP cores, embedded software,
and design services. Plamchip’s CoreFrame Architecture provides a highperformance on-chip bus scheme allowing quick and easy integration of
silicon IP blocks. Combined with our extensive IP portfolio, CoreFrame
dramatically reduces SOC design and verification time. Palmchip also
offers a range of silicon and software design services specialized in the
design of high-integration SOC devices using the ARM RISC processor
core family. Palmchip’s web site is at www.palmchip.com.
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Penton Publishing
Booth 822
Pivotal Technologies, Inc.
Booth SV16
611 Rte. 46 West
Hasbrouck Heights, NJ 07604
(201) 393-6060
http://www.penton.com
87 E. Green St., Ste. 303
Pasadena, CA 91105
(800) 896-7770
http://www.pivotaltech.com
Penton Publishing’s Electronics Information Group features the following
publications: Electronic Design, Electronic Design China, EE Product News,
Wireless Systems Design, and Penton’s Embedded Systems Development.
Pivotal Technologies is a leading source of analog and mixed-signal
components, digital libraries and IP cores, which can be embedded into
today’s System-on-a-Chip designs. Our products are optimized and
available for the leading semiconductor foundary processes. If you are
looking for PLL Clock synthesizers, A/D and D/A converters, voltage
regulators, standard cell libraries that are mixed-signal friendly or
microprocessor cores, please visit us at our booth in the Silicon Village.
Philips Semiconductors
Booth SV21
811 E. Arques Ave.
Sunnyvale, CA 94088
(505) 822-7629
http://www.coolpld.com
Platform Computing Corp.
Booth 1700
Introducing Philips CoolRunner™ 960 CPLD, the world’s highest density
CPLD. 960 macrocells with 384 I/O, high speed 3V. High level system
integration without the performance sacrifice. Philips XPLA™ design tools
and software solutions partners design tools.
Phoenix Technologies Ltd., Virtual Chips
Booth 1846
411 E. Plumeria Dr.
San Jose, CA 95134
(408) 570-1000
http://www.phoenix.com
Phoenix Technologies provides a complete hardware, firmware and driver
solution for interface standards. All standards are available in
synthesizeable Verilog and VHDL RTL. Additionally, extensive verification
environments, which guarantee adherence to industry standards, are
available for each core. Current products from the Phoenix
Technologies’ Virtual Chips Group include: 1394 Link Layer, 1394 Phy
Layer, USB OHCI Host, USB Hub, USB Function, IrDA, PCI Satellite and Host
Bridge cores for 32 and 64 bit PCI and application interfaces, AGP Master
1.0 and 2.0, AGP Host 1.0 and 2.0.
Pinebush Technologies, Inc.
Booth 936
Pine West 2, Washington Ave.
Albany, NY 12205
(518) 452-0927
If you’re not using HyperPlot, find out how you can join 20,000 of the world’s
most sophisticated IC and PCB designers. HyperPlot is the EDA industrystandard, high performance, printing and plotting solution. HyperPlot quickly
prints any size file, to any size paper, using any (8.5” X 54”) output device.
With plot previewing and queue monitoring, you can save time and money by
never wondering what happened to your submitted jobs. With HyperPlot’s list
of common inputs, ALL your printing needs can be met, not just electronic
designs. It is truly the Enterprise Printing solution.
134
5001 Yonge St., Ste. 1401
North York, ON M2N 6P6 Canada
(416) 512-9587
http://www.platform.com
Platform’s LSF Suite enables enterprises to effectively manage their
computing workloads to deliver compelling business results, including
faster design cycles, shorter time to market, better products, improved IT
services, and significant cost savings. The latest release of LSF offers
comprehensive support for batch processing, workload analysis,
mainframe-class job scheduling, and Windows NT, as well as user friendly
graphical user interfaces (GUIs). LSF is ideal for companies or
departments looking to get the most from their distributed heterogeneous
Windows NT and UNIX computing resources.
Prentice Hall-PTR
Booth 827
1 Lake St.
Upper Saddle River, NJ 07458
(201) 236-7238
http://www.prenhall.com
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Printed Circuit Design Magazine, Miller
Freeman, Inc.
Booth 451
2000 Powers Ferry Ctr., Ste. 450
Marietta, GA 30067
(770) 952-1303
http://www.PCDmag.com
PRINTED CIRCUIT DESIGN magazine is the monthly publication focused
on techniques, tips and tools for designers, engineers and managers
involved in PCB and hybrid/MCM design. Free magazines and
subscriptions are available to qualified industry professionals. Visit our
stand for complimentary issues and to fill out a subscription form.
Provis Corp.
Booth 84
5251 Program Ave., Ste. 100
Mounds View, MN 55112
(612) 785-2000
http://www.provis.com
Provis ensures that your designs are functionally verified and have highquality manufacturing tests. Within our framework are advanced tools for
functional test coverage, network distributed simulation, process
automation, and high-speed fault coverage analysis. At the framework
core are software and accelerated hardware simulators that cover the
complete spectrum of simulation needs. Provis has many new products
at DAC: the ProLog and ProGrade software simulators, the new XPrime
environment, Fault Manager 2.0, and ...our revolutionary new
simulator...Construct.
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QuickLogic Corp.
Booth 736 & SV22
1277 Orleans Dr.
Sunnyvale, CA 94089
(408) 990-4000
http://www.quicklogic.com
pASIC 3 is QuickLogic’s latest family, manufactured on a 0.35 micron 4layer metal. There are five devices in the family, ranging from 12,000 to
100,000 usable gates, from 84 to 456 package pins, and feature 3.3
volt operation with 5 volt compatibility. In 1998, QuickLogic will add
embedded blocks of RAM to the family. QuickLogic’s QuickWorks design
tools provides designers with a very low cost schematic-entry based tool,
and the free QuickChip tools enable engineers to use third party
environments such as Synopsys, Cadence, Mentor Graphics, Viewlogic,
Veribest, Synario, and many others, to generate QuickLogic designs.
Quickturn Design Systems, Inc.
Booth 2108
55 W. Trimble Rd.
San Jose, CA 95131-1013
(408) 914-6524
http://www.quickturn.com
Quickturn, the leader in design verification, unveils its newest products
suite aimed at complex chips and systems resulting from deep submicron
and system-on-chip. These products are based on the latest emulation
and simulation technology, offering unprecedented performance and
ease-of-use. They offer a high-performance continuous verification
environment that encompasses design style checking, cycle-based
simulation, mixed mode functional acceleration and in-circuit emulation.
Floor demonstrations will show designs for the multimedia,
telecommunications and computing segments.
RAPID
Booth SV4
P.O. Box 779003-299
Dallas, TX 75379
(972) 503-0066
http://www.rapid.org
RAPID is an industry trade association chartered with meeting the needs
of companies and organizations that develop and sell IP. The
association’s primary function is to promote the acceptance and use of
third party IP products within the electronics industry. Additional
objectives include establishing guidelines and promoting the use of good
business and design practices among members. RAPID works with EDA,
semiconductor companies and industry standard organizations to make
IP easier and more accessible to designers.
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Relay Design Automation
Booth 448
Sagantec
Booth 518
1153 Bordeaux Dr., Ste. 208
Sunnyvale, CA 94089
(408) 745-1285
558 Valley Way
Milpitas, CA 95035
(408) 934-1157
http://www.sagantec.com
RUBICAD Corp.
Booth 2000
San Jose, CA 95112
(408) 995-3334
http://www.edac.org/Rubicad
Macros, cores and libraries are being reused and resized for different
fabs and as part of complex systems-on-silicon. To address this, Rubicad
offers LACE 3.0, the world leading LAyout Conversion Environment. LACE
3.0 facilitates system-level integration (SLI) and hierarchical compaction
of existing system-level macros (SLMs) and cores for use with various
submicron technologies. A major breakthrough in compaction technology
now enables designers to maintain the original hierarchy of RAMs, ROMS,
SRAM, DRAM, datapath, etc. during the compaction process.
Runtime Design Automation
Booth 452
1208 Apollo Way, Ste. 508
Sunnyvale, CA 94086
(408) 524-0460
http://www.rtda.com
Runtime Design Automation provides tools that speed your design times
by automatically managing hardware and software design flows and
leveraging your distributed computing resources. Our tool suite, called
VOV, is the only product that dynamically detects all dependencies and
conflicts which ensures accuracy, consistency and completeness
throughout the design cycle. Our customers are experiencing a speedup
in the execution of each design cycle by a factor of 10 to 20.
Stop by Sagantec’s Exhibit for a demonstration of DREAM (Design Rule
Enforcement and Migration), the most widely used physical design
migration tool in the industry, according to Gary Smith of Dataquest.
DREAM enables silicon design reuse for efficient system on silicon using
silicon-proven design. Its Companion works seamlessly with Virtuoso
layout editor from Cadence for rapid cell and IP development to
significantly reduce the number of DRC iterations. A new wirespacer tool
broadens Sagantec’s offering to include solutions for improving reliability
and reducing crosstalk.
Sand Microelectronics
Booth 1450
2121 Ringwood Ave.
San Jose, CA 95131
(408) 321-8200
http://www.sandmicro.com
Sand Microelectronics, Inc. is the leading provider of silicon-proven
intellectual property (IP) with a focus on connectivity standards, such as
IEEE 1394, USB, and PCI. Sand delivers IP as synthesizable cores in
Verilog and VHDL. In addition to cores, Sand’s TymeWare™ toolkits
include simulation models that facilitate system simulation and
verification, bus analysis tools that enable customers to optimize designs
for maximum performance, and optional validation boards for system
level core verification.
SANDSTROM Engineering
Booth 2546
3611 Vista Dr.
Manhattan Beach, CA 90266
(310) 545-7108
http://www.sandstrom.org
Write better hardware NOW! You’ve got a “pretty” good design, but you
suspect there are some problems. Don’t settle for “pretty good.” Have
a design that is going to synthesize without the problems that you will
have to solve farther down the line. Sanstrom Engineering’s PreSynth.vhd
makes VHDL synthesizable and checks for nonsense constructs, the
dreaded ‘reset’ problem, registered outputs, and much more.
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Sapien Design
Booth 349
45335 Potawatami Dr.
Fremont, CA 94539
(510) 668-0200
http://www.sapiendesign.com
SES Inc.
Booth 1622
Sapien Design IP products include USB-compliant Function and Host
Controller macros, and a USB Test Environment. All are available in
Verilog or VHDL. The macros are also available in netlist for popular
FPGAs or synthesizable RTL for ASIC. The Function Controller features
application-specific End Points and configuration file. The Host is OHCIcompliant and interfaces to processor busses. The Test Environment
includes a test bench with Host and Function models and over 150 USB
Checklist test cases.
Semiconductores Investigation Y Diseno
(SIDSA)
Booth SV37
Parque Tecnologico de Madrid
Torres Quevedo , 1-2 a
Tres Cantos, Madrid, 28760 Spain
(415) 550-1652
http://www.sidsa.es
A global leader in simulation, modeling analysis, and design technology,
SES Inc. provides world-class solutions for analysis, implementation, and
operation management of complex software and hardware systems. As
SES’s founding simulation product, SES/workbench® is state-of-the-art,
system-level simulation software focusing on behavioral and performance
modeling. The Common Modeling Framework (CMF) is based upon
SES/workbench technology (licensed by SES from IBM). CMF allows
designers to connect individual component models in building-block
fashion to create system-level models, sharing models without revealing
proprietary information.
SEVA Technologies, Inc.
Booth 1654
200 Brown Rd., Ste. 103
Fremont, CA 94539
(510) 249-9085
http://www.seva.com
SIDSA offers complete ASIC design solutions from system specifications
to layout, as well as a variety of reusable IP modules. SIDSA’s new EDA
product offering, VHDL-ICE, is an Integrated Common Environment for
managing VHDL-based Virtual Components, without forcing developers to
change their tools or the way they work. SIDSA is also introducing
FIPSOC, a new Field Programmable System-on-Chip consisting of a mixedsignal FPGA with on-chip microprocessor. Founded in 1992, SIDSA is a
emerging leader in Europe’s microelectronics and EDA industries.
Visit SEVA Technologies Exhibit during DAC to learn about its consulting
services, innovative training and design solutions, hardware and software
benchmarking, and tool and methodology assessment. Its IP Evaluation
Service helps designers assess which model is appropriate for a given
design project — system simulation, design in, synthesis or inclusion in
an end product. Through its experience using IP from various third-party
sources, SEVA Technologies has developed the expertise to evaluate IP
models from PCI and USB to IEEE 1394 Firewire and MPEG.
Sente Inc.
Booth 208
SICAN Microelectronics Corp.
Booth 453
31 Nagog Pk.
Acton, MA 01720
(978) 635-9080
http://www.senteinc.com
Sente is a company focussed on IC Power problems and their resolution.
Its unique software technology provides control of IC power dissipation
throughout the entire design process. Sente’s Watt Watcher/Architect
analyzes Architectural-level Verilog HDL or VHDL, before synthesis, and
produces accurate full-chip power estimates. Sente has expanded the
capability of its power analysis software suite by offering Peak Watcher.
Peak Watcher identifies peak power consumption by leveraging
Architectural-level Verilog or VHDL for fast simulation speed, making
possible the analysis of many thousands of simulation.
140
4301 Westbank Dr., Bldg. A
Austin, TX 78746-6564
(800) 759-6333
http://www.ses.com
400 Oyster Point Blvd., Ste. 512
S. San Francisco, CA 94080
(650) 871-1494
http://www.sican-micro.com
SICAN Microelectronics Corp. your Partner for “Systems Integration for
Communications And New Media Applications”. SICAN is one of the
largest independent Technology Licensing and Design Services
Companies worldwide. Our core offerings - DesignObjects™- include
Multimedia (MPEG-2, AC-3, etc.), Networking (HDLC, Utopia, AAL),
Processors (8051, PIC) and Bus Interfaces (PCI, CAN, I2C,1394, etc.).
Design Services range from digital to analog ASIC Design and Systems
Design. SICAN’s design engineers are experienced in the fields of
Telecommunications, Digital Signal Processing, Video, Audio, Bus
Interfaces, Medical Applications, Industrial Applications and Encryption.
PADS
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Sierra Research & Technology, Inc.
Booth SV36
Silicon Integration Initiative, Inc. (Si2)
Booth 918
465 Fairchild Dr., Ste. 130
(650) 988-4800
http://www.srti.com
4030 W. Braker Ln., Ste. 550
Austin, TX 78759
(512) 342-2244
http://www.si2.org
SRTI, the global leader in Ethernet Intellectual Property, is dedicated to
developing high-end IP for the networking and data communications
semiconductor markets. Sierra’s products include 622 Mb/s ATM SAR,
10/100 Mb/s Ethernet MAC, 10/100 Mb/s PCI-based Ethernet
Controller (with software drivers), 10 Mb/s Base T Ethernet PHY, 10/100
Mb/s Base TX Ethernet PHY, Quad 10/100 Mb/s Base TX Ethernet PHY,
1Gb/s Ethernet MAC, P1394 PHY, R3000 Microprocessor, 68XX
Microcontrollers and 14-bit 5 MSPS AD/DA converters for ADSL.
Silicon Integration Initiative, Inc. (Si2) provides engineering consultation
and services to industry-leading silicon, electronic systems, and EDA
companies for synergistic multi-company efforts focused on improving
productivity and costs in the design and production of integrated silicon
systems. Through collaborative services and technologies Si2 actively
supports constituent initiatives such as the ASIC Council, Electronic
Component Information Exchange (ECIX), EDA Industry Council, EDAC,
EIAJ, and VSIA. With Si2’s neutral legal and financial infrastructure, the
members of Si2 are together accomplishing what no single company can
achieve alone.
Silicon Access Inc.
Booth 108
2025 Gateway Pl., Ste. 380
San Jose, CA 95110-1014
(408) 441-7390
http://www.silicon access.com
Silicon Access provides proprietary deep submicron embedded DRAM
technology combined with advanced 0.25-micron I/O and standard cell
libraries to enable true SOC capabilities. These embedded DRAMs and
cell libraries are process specific to multiple major foundries giving
designers the best cost, design turnaround-time and process
alternatives. Silicon Access also provides advanced DRAM compilers,
ASIC design flow expertise and physical design services to enable
designers to break through the performance bottleneck for true systemlevel integration.
Silicon Forest Research
Booth 68
14463 Pfeifer Dr.
Lake Oswego, OR 97035
(503) 675-0121
http://www.sifr.com
Assertion Compiler helps VLSI designers find hard-to-detect bugs in their
Verilog designs. Assertion Compiler first analyzes a design to find the
best test points for detecting errors. Then Assertion Compiler
automatically synthesizes assertions that check the circuit’s behavior at
each test point during simulation. Design bugs show up as assertion
failures reported from Assertion Compiler’s error database. Test
coverage problems are also reported. To summarize, startup Silicon
Forest Research’s new technology improves design verification without
changing engineers’ designs or their design methodology!
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Silicon Strategies
Booth SV13
954 San Rafael Ave.
(650) 988-9677
http://www.isdmag.com
Silicon Strategies magazine is the premier information source for
technical, project, and corporate management on the strategies, issues,
and products relating to the use of virtual components and intellectual
property in creating systems on a chip. This unique trade journal reports
on the market’s evolving technical and business trends, including legal
issues surrounding the use and abuse of IP, pricing strategies, IP design
management, and standardization efforts. It also provides product
coverage on cores of all types, tools for IP integration, and foundry and
design services.
Silicon Valley Research, Inc.
Booth 1730
6360 San Ignacio Ave.
San Jose, CA 95119
(408) 361-0333
http://www.svri.com
Silicon Valley Research, Inc. provides leading-edge IC physical design
software for floorplanning, placement, routing, custom layout and
parasitic extraction of deep submicron ASICs, ASSPs, mixed signal ICs
and microprocessors. SVR also offers expert design services to handle
even the most difficult designs and expedite your time-to-market, easily
and on budget. Our production-proven tools results in denser, higher
yielding, high performance chips. Stop by our booth to find out how we
can get you on the fast track to timing correct designs.
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Silvaco International
Booth 127
4701 Patrick Henry Dr., Bldg. 2
(408) 654-4376
http://www.silvaco.com
Simpod, Inc.
Booth 2534
Silvaco introduces a unique “TCAD-Driven-CAD” toolset to provide the
necessary access to process technology required for successful subquarter micron designs. “SmartSpice” is the rapidly emerging standard in
circuit simulation with unprecedented accuracy including the industry’s
best BSIM3v3.1 model. “Celebrity” provides a powerful and affordable
NT-based layout and verification toolset including “Expert” layout editor
and “Savage” DRC. “STORM” brings the accuracy of process simulation
to interconnect parasitic extraction with a series of tools from cell level
to full chip extraction.
Simpod provides a family of high-performance modeling systems for the
co-development of digital electronic systems. Simpod products and
services offer hardware and software teams scalable, simulation
acceleration and rapid time-to-modeling solutions which significantly
shorten product design and verification schedules. The company’s
patented and patent pending technologies are incorporated in the
DeskPOD™ family, which can be used for SoC, ASIC, silicon intellectual
property (SIP), and embedded systems design. API libraries are available
for HDL-based simulators and embedded software development tools.
Simple Silicon Inc.
Booth SV17
Simucad, Inc.
Booth 1122
10430 S. DeAnza Blvd., Ste. 195
Cupertino, CA 95014
(408) 873-2260
http://www.simplesi.com
32970 Alvarado-Niles Rd., Ste. 744
Union City, CA 94587
(510) 487-9700
http://www.simucad.com
Simple Silicon provides digital and mixed signal IPs which enable you to
design for high speed connectivity between PCs, Consumer Electronic
devices, Networking Equipment and Home Appliances. Using our silicon
proven USB, IEEE1394 (firewire) and Low Power Analog Cores can save
the user several months of ASIC design time, enabling them to get to the
market quicker. Our drag and drop silicon components are available as
ASIC-HDL, PLD functions and Physical Layout.
The SILOS HyperFault Simulation System is the latest technology
available for fault simulation users who require scalable runtime
performance. It is the next logical step in fault simulation evolution,
developed to meet the demanding needs of today’s deep-submicron
technologies and their large-scale testing and verification requirements.
HyperFault is the only fault simulator that supports behavioral models as
well as gate and switch level modules directly in the source file.
Simplex Solutions, Inc.
Booth 644
Simutest, Inc.
Booth 1624
521 Almanor
Sunnyvale, CA 94086
(408) 617-6100
http://www.simplex.com
Simplex interconnect verification tools let you see deep submicron
problems before you see them in silicon. Fire & Ice is a fast full-chip 3-D
parasitic extraction tool that efficiently captures all the RC data you need
for accurate timing, signal, and power analysis. Fire & Ice’s extraction
speed is obtained through distributed processing. Thunder & Lightning is
a full-chip analysis tool for analyzing power grid IR drop, clock skew,
effects of IR drop on clock delay, signals sensitive to coupling, and EM
risk on signals and the power grid.
144
3080 Olcott St., Ste. 100A
(408) 330-9300
http://www.simpod.com
39420 Liberty St., Ste. 270
Fremont, CA 94538
(510) 739-0735
http://www.simutest.com
WaveTools is a complete simulation analysis and test program
generation environment. WaveTools creates test programs and verifies
tester compatibility, from simulation vectors or test benches in a virtual
test environment eliminating the need to use expensive tester time for
program development. You can also import, display, edit and compare
test vectors from more than 30 simulators and 70 test systems. For
ASIC design you can analyze and verify simulation vectors for
compatibility with the foundry specific test system thereby saving resimulations and time.
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Snaketech
Booth 1054
Place de la Chaffardiere
St. Geoire en Valdaine, F-38620 France
(33) 476-071408
http://www.snaketech.com
Summit Design, Inc.
Booth 1808
Substrate Noise Problems? Layin will aid you in analyzing substrate noise
concerns and help ensure first silicon success. Layin can be used to
model designs in all technologies and all feature sizes. Our new Cadence
interface and SPICE netlist integration make the program easy to
integrate into any design flow. High end place and route has become
affordable for both PC and UNIX platforms with cellSnake and gateSnake
V1.4, which include zero-skew clocktree synthesis and path-based timing
constraints.
Spectra Logic
Booth 1118
1700 N. 55th St.
Boulder, CO 80301
(303) 449-6400
http://www.spectralogic.com
Spectra Logic makes a cost-effective variety of scalable tape libraries,
and best-of-class, full-featured automated librarian software. Spectra
Logic’s Alexandria Backup and Archive Librarian software and the Spectra
10000 AIT tape library won Unix Review’s 1997 Outstanding Product
award. Alexandria Backup Librarian Software manages tape libraries and
optical jukeboxes to provide complete, automated, backup including live
database backup. Spectra Logic Bullfrog™ and Treefrog™ tape libraries
feature Sony AIT or DDS-3 tape technology, and SCSI-2 connection.
Stanza Systems, Inc.
Booth 19
10062 Miller Ave., Ste. 220
Cupertino, CA 95014
(408) 873-0160
http://www.stanzas.com
Focusing on new generation of custom IC layout tools for DSM needs,
Stanza offers PolarSLE and PolarVerify. PolarSLE provides comprehensive
edit functions and exceptional capacity for multi-million gate layout
designs. Its built-in modules for automated layout editing, hierarchy recreation, post P&R editing, antenna diode insertion and cell-based
migration significantly boost layout productivity. PolarVerify includes
interactive DRC and LVS that are integrated with PolarSLE. The DRC can
accept Dracula compatible command format and the unique LVS
debugger greatly improves debugging efficiency.
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9305 SW Gemini Dr.
Beaverton, OR 97008
(503) 643-9281
http://www.summit-design.com
Summit Design, a market and technology leader, will demonstrate an
extensive range of HDL-based solutions for verification, analysis, legacy
code reuse and capture. Supporting ASSP, ASIC and FPGA
methodologies, demonstrations feature Code Coverage (HDLScore™ and
VeriCov™), HW/SW Co-verification (V-CPU™), Graphical Capture/ Reuse
(Visual HDL™), Legacy Code Management (Text2Graphics), Waveform
Viewing and Source Code Debugging (VirSim™), and Behavioral Synthesis
(Dasys RapidPath™). Summit’s tools promote early and complete
verification through cause and effect debugging, graphical code
inspections, code coverage metrics and HW/SW co-verification.
Sun Microsystems
Booth 618
901 San Antonio Rd.
Palo Alto, CA 94303
(650) 786-3744
http://www.sun.com
Cost concerns and shortened products life cycles demand a highly
effective EDA compute environment. Visit Sun’s booth for a
demonstration of how Sun addresses this requirement with high
performance, cost effective EDA desktop hardware, closely integrated
with high-speed networking, storage solutions, compute ranches and
resource management software provides a competitive advantage to
electronic product manufacturers. Additional demonstrations will show
how office productivity tools such as word processor, spreadsheet and
presentation graphics can be seemlessly deployed on the engineering
(UNIX) desktop.
Sycon Design, Inc.
Booth 950
20454 Blauer Dr.
Saratoga, CA 95070
(408) 868-0610
http://www.sycon-design.com
Sycon Design, Inc. provides physical synthesis tools for high performance
designs that require the quality of hand crafted full custom and the
productivity of automated solutions. Sycon targets the leading edge IC
houses with the most demanding requirements for their very deep submicron designs. Sycon is currently focusing on a partnership business
model to guarantee success of the most challenging projects.
Summit
Design Ad
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xhibit guide
SynaptiCAD Inc.
Booth 90
Synplicity, Inc.
Booth 1742
P.O. Box 10608
Blacksburg, VA 24060
(800) 804-7073
http://www.syncad.com
624 E. Evelyn Ave.
Sunnyvale, CA 94086
(408) 617-6049
http://www.synplicity.com
SynaptiCAD offers a complete line of HDL and timing visualization tools:
WaveFormer Pro is a new type of HDL simulator that interactively
generates HDL code and incrementally simulates your design as it is
entered. TestBencher Pro is a VHDL/Verilog testbench generator that
creates bus-functional HDL models from timing diagrams, VCD, and logicanalyzer data. Timing Diagrammer Pro is a graphical timing diagram
editor. And a Verilog simulator with integrated editor, debugger, waveform
viewer, and project management. Can’t wait to see our demos? Download
at www.syncad.com!
Synplicity® brings leading edge, easy to use, extremely productive design
tools to hardware designers using FPGA and CPLD devices. Synplicity’s
synthesis and HDL analysis products (Synplify® & HDL Analyst™) have
rapidly become the technology of choice for high-density FPGA and CPLD
design. The introduction of two new products, HDL Floorplanner™ and
HDL Partitioner™, positions Synplicity to lead next generation FPGA
design methodologies. Visit booth #1742 to see the B.E.S.T.™ synthesis
tools including our innovative new approach to RTL floorplanning and
partitioning.
Synchronicity Inc.
Booth 1800
SynTest Technologies, Inc.
Booth 1646
153 Monaco Ct.
Pleasanton, CA 94566
(510) 462-4993
http://www.syncinc.com
Synchronicity offers a flexible suite web-based tools providing superior
Project and Design Management for teams of IC Designers. Its clientserver architecture allows design teams to make the most of project
Intranets and/or the Internet as the “backbone” of their design projects.
See demonstrations featuring real-world applications based on
Synchronicity technology. See how Synchronicity’s tools can help you
develop and deliver a corporate IP Reuse environment. Experience firsthand how Synchronicity’s family of Project and Design management tools
deliver improved productivity to your design teams by enabling secure
creation, management and distribution of reusable IP.
Synopsys, Inc.
Booth 2130
Mountain View, CA 94043-4033
(650) 694-4418
http://www.synopsys.com
Come see how 12 leading-edge electronics companies have broken down
their IC design barriers with state-of-the-art design flows from Synopsys.
These flows include Synopsys’ comprehensive verification tool suite that
spans system-level, hardware/software, functional, and nanometer IC
design. Check out Synopsys’ expanded (datapath and protocol synthesis)
and improved (DC’98, FPGA Express) synthesis product line. This is also
your chance to see how your counterparts at other companies have
implemented Synopsys’ static verification flow, virtual system
verification, design for reuse methodology, and much more!
148
505 S. Pastoria Ave., Ste. 101
Sunnyvale, CA 94086
(408) 720-9956
http://www.edac.org/Syntest
SynTest is a leader in fault simulation. TurboFault is the fastest
commercially available fault simulator. This software-based solution is
two to 100 times faster than competitive products, including hardware
accelerators. SynTest also provides high-performance test automation
tools and services for Testability Analysis, Test Synthesis, and Test
Pattern Generation. The tools support full-scan, partial-scan, and on-scan
modes using stuck-at/Iddq/transition fault models. They produce
industry-leading results in fault coverage, vector size, and performance.
JTAG and RAM BIST, and multi-core test solutions are also available.
Systems Science, Inc.
Booth 1218
1860 Embarcadero Rd., Ste. 260
Palo Alto, CA 94303
(650) 812-1808
http://www.systems.com
Systems Science will be showcasing VERA-SV™ and PowerFault-IDDQ™.
VERA-SV is a powerful new solution for verifying the complete system,
including hardware and software in a single environment. PowerFaultIDDQ is IDDQ test technology with push-button automation.
Synopsys Ad
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xhibit guide
Tanner EDA
Booth 1600
2650 Foothill Blvd.
Pasadena, CA 91107
(626) 792-3000
http://www.tanner.com/eda
Temento Systems
Booth 94
Tanner EDA offers feature-rich, easy to use physical design and
verification tools for analog and mixed-signal ICs. Tanner Tools Pro offers
an integrated IC design solution including schematic capture, SPICE
simulation, standard cell place and route, layout editing, design rule
checking, and layout versus schematic comparison. With Windows®
platforms at Windows® prices you can afford to put a powerful tool suite
on the desk of every member of your design team.
Tau Simulation Inc.
Booth 11
450 San Antonio Rd., Ste. 64
Palo Alto, CA 94306
(650) 424-8308
http://www.tausim.com
Tau provides simulation products and services for complex ASIC and full
custom IC development. The TauSim™ cycle based simulator for Verilog
designs includes support for X and Z signal values. TauSim runs on
SPARC and Pentium computers and features processor independent
compilation to support mixed architecture design environments. Services
provided by Tau include: installation and maintenance of simulation
processor arrays, PLI code and test script development, and porting of
existing designs to cycle based simulation. Visit us in Booth 11 to see
the performance achieved with TauSim and discover what Tau can do for
you.
Technology Modeling Associates, Inc.
Technology Modeling Associates was acquired by Avant! in January 1998.
Former TMA tools are now part of Avant!’s TCAD (Technology Computer
Aided Design) division including Raphael, an interconnect simulator, and
OPC simulator Proteus. Avant!’s line of EDA software provides the
industry’s only complete TCAD-to-ECAD offering.
15 Rue des Martyrs
Grenoble, Cedex 9, 38054 France
(33) 476889438
http://www.temento.com
Temento Systems provides Electronic Test Automation (ETA) Software
Tools for the test of ASICs, MCMs, boards and systems. Diatem, the first
Electronic Systems Design and Test lab on the market is the most
advanced tool dedicated to the DFT insertion, the test the debug and the
analysis of electronic devices. Dialite, more dedicated to the debug of
MCMs and boards provides the most powerful debugging environment for
the bring-up your prototypes. Already proven in Europe and soon coming
here your ASICs, MCMs and boards systems design can benefit from
Temento Systems’ products.
Tera Systems, Inc.
Booth 145
2105 S. Bascom Ave., Ste. 185
Campbell, CA 95008
(408) 879-1990
http://www.terasystems.com
Tera Systems unveils TeraForm™, the revolutionary RTL design-planning
system that solves your deep-submicron-IC timing convergence and
complexity problems. TeraForm automates structured-ASIC design,
delivering the density and performance benefits of hierarchical,
structured-custom chips while maintaining the productivity and turnaround-time benefits of traditional ASIC design. The integrated TeraForm
environment supports interactive full-chip hierarchical partitioning, virtualsilicon prototyping, design visualization, and performance analysis.
Industry-standard interfaces connect TeraForm to existing top-down tools,
enabling an RTL sign-off methodology and secure IP reuse. Please
contact Tera Systems at www.terasystems.com.
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xhibit guide
Teradyne, Inc.
Booth 152
Time-Rover Inc.
Booth 13
321 Harrison Ave.
Boston, MA 02118
(617) 422-2567
http://www.teradyne.com
11425 Charsan Ln.
Cupertino, CA 95014
(408) 252-2808
http://www.time-rover.com
VX test simulation software links IMAGE™ to industry design simulators
Saber/Verilog and Spectre/Verilog, providing a familiar test environment
for validating test development in advance of completed designs. VX
software identifies pre-silicon design and test issues before device
fabrication with a closed-loop information exchange that creates a
transparent linkage to an EDA atmosphere. VX software simulates
models of the DUT, loadboard and ATE instruments while utilizing IMAGE
ExChange ™ technology to mirror the test engineer’s complete
development environment.
The Temporal-Rover is a specification and testing tool. Code generation
(Verilog, C, C++, Java) creates code which verifies, during testing, that
your code conforms to your specification after design changes or
synthesis. The specification language is your existing modeling language
(e.g. Verilog) augmented with a few simple temporal operators. The
Knowledge-Rover is a knowledge management tool for project and
corporate managers. With KR, you and everyone else can see, certify and
record who knows what facts at any given time.
Texas Instruments
Booth SV25
P.O. Box 660199, MS 8678
Dallas, TX 75266
(972) 480-7963
71 SpitBrook Rd., Ste. 301
Nashua, NH 03060
(603) 888-8188
http://www.topdown.com
System Level Integration is enabled by the silicon capacity of deep
submicron technology. Its future will be characterized by multiple CPUs,
large memory content, reconfigurability, and heterogeneous subsystems.
Radical changes must occur in today’s EDA flow to permit parallel HW-SW
development, more optimal partitioning, timing closure, reduced at-speed
test vectors, and new signoff paradigms. TI is uniquely positioned to
address these needs with our experience designing advanced single-chip
DSP Solutions in 0.18µm for applications, such as digital cell phones and
ADSL modems in a pure ASIC methodology. TI is the world leader in DSP
Solutions and the world leader in Analog & Mixed Signal.
Come see Topdown’s core model generation technology, which enables
two exciting solutions for System-on-Chip design. TopProtect™ produces
protected, accelerated simulation models for the secure distribution of
Intellectual Property. Cyclops™ produces optimized, cycle-based models
of your designs that simulate 10 to 50 times faster with your
conventional event-driven simulator. Both offer easy integration with
existing tools and methodologies, VHDL and Verilog support, and
simulator independence. Learn more from www.topdown.com, then come
see for yourself with live demos in our booth.
TimberWolf Systems, Inc.
Booth 824
10880 Cassandra Way
Dallas, TX 75228-2493
(972) 613-6772
http://www.twolf.com
TimberWolf is a complete timing driven placement and routing tool that is
applicable to row based and building block design styles. TimberWolf is
capable of handling any of the row-based design styles, namely, standard
cell circuits, gate arrays and sea-of-gate circuits. TimberWolf can also be
applied to floorplanning problems. It can be used to completely place
and detail route mixed macro/standard cell circuits. See how TimberWolf
can help you with all your integrated circuit designs.
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Topdown Design Solutions, Inc.
Booth 2350
Tower Semiconductor Ltd.
Booth SV31
4320 Stevens Creek Blvd., #195
San Jose, CA 95129
(408) 551-6500
http://www.towersemi.com
Tower Semiconductor, a provider of leading-edge foundry services for
embedded non-volatile memory and high-density CMOS products, will
introduce its newly pioneered CMOS Image Sensor Technology. CMOS
processes, which are designed for optical applications, incorporate
qualified and continuous monitoring of optical parameters to ensure high
product quality and repeatability. Features such as deposition of color
filters, design services and stitching enable Tower’s CMOS Image
Sensors to provide superior & cost-effective optical sensor solutions.
Future CMOS Image Sensors will be turnkey operational, including optical
sort, packaging and final test.
Temento Ad
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xhibit guide
Transcendent Design Technology, Inc.
Booth 86
TSA
Booth 925
1383 Del Norte Rd.
Camarillo, CA 93010
(805) 278-7185
http://www.tdes.com
2040 W. Sam Houston Pkwy. North
Houston, TX 77043
(713) 935-1500
http://www.tsa.com
Transcendent Design Technology is a focused solutions provider of
EM/EDA capture, analysis and simulation tools. TransCable is a “correct
by construction” logical and physical design capture product for electronic
distribution systems such as wire harness and cable systems.
TransAnalysis is a suite of analysis tools that includes TransAnalysis SI,
used to detect and resolve signal distortion and crosstalk problems; and
TransAnalysis EMI, for the detection of EMI compliance problems.
Products are available for UNIX and NT platforms.
TSA is a Hewlett-Packard Authorized Rental Company. TSA carries an
extensive line of refurbished Hewlett-Packard hardware for rental and
resale including 9000/800-700-500-400-300-200 and DN series
workstations. Our inventory also includes series 3000 and 1000
equipment, netservers, disc drives, memory, plotters, printers, PC’s, data
acquisition, and test equipment. All equipment carries a 90-day
parts/labor warranty. Workstations are automatically guaranteed for an
HP maintenance contract. All equipment is available for long or short term
rental and lease/purchase.
TransEDA, Inc.
Booth 233
16795 Lark Ave., Ste. 125
Los Gatos, CA 95032
(408) 395-5014
http://www.transeda.com
TransEDA announces a major breakthrough in logic design verification
with a new and unique solution that is a ‘first’ in the EDA market.
Delivering a powerful methodology in statemachine verification,
StateSure simplifies the process and allows designers to autointeractively verify interactions between complex controllers, previously a
manual task. StateSure reduces verification time and the risk of costly
ASIC failures, and is available for all design flows. It uses a plug-and-play
approach to integrate with leading Verilog / VHDL simulators and code
coverage products. Also on show: VeriSure, VHDLCover, CoverPlus.
Translogic USA Corp.
Booth 2518
573 Maude Ct.
Sunnyvale, CA 94086
(408) 746-0707
http://www.translogiccorp.com
215 Fourier Ave.
Fremont, CA 94539
(510) 623-5137
http://www.tessi.com
TSSI is a leading provider of test automation software technology and
solutions. Over 200 of the world’s top electronics companies guarantee
high quality products while reducing time to market by using TSSI’s
innovative products, support, and services. With technology based on
VHDL, Verilog, WGL, and STIL, TSSI is unique in providing an independent
bridge between ASIC, EDA, and ATE suppliers. Sales offices and
distributors are located throughout the world. TSSI Headquarters is
located in Beaverton, Oregon. Please visit our web site at www.tessi.com.
Ultima Interconnect Technology
Booth 144
Chip designers play to win. So, don’t gamble with your tools! Translogic’s
EASE/HDL offers easy graphical entry and automatic Verilog or VHDL
code generation. EASE/HDL also interfaces to the industry’s most
popular simulators and synthesis tools, so it fits easily into your existing
design flow. And, EASE/HDL now offers graphical representation of
existing Verilog or VHDL code. Save time and money through design
reuse. Translogic is your wild card to success! See for yourself at booth
#2518.
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TSSI
Booth 2300
525 Almanor
Sunnyvale, CA 94086
(408) 328-9149
http://www.ultimatech.com
To achieve first pass silicon success, Ultima-DC, integrated with UltimaPE, a 3D net parasitic extractor, is the first delay calculator taking into
account for coupling noise and power net IR drop/rise in DSM cell-based
IC design flow. Ultima-PE achieves accuracy close to 3D solver and speed
approaching to 2D extraction. Being the leading supplier of the standardalone parasitic reduction tool, Ultima-PR provides best solution for large
digital circuits as well as complex memory and mixed signal circuits.
Silicon
Valley
Research Ad
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xhibit guide
Unified Design Automation, Inc.
Booth 850
VALOR Computerized Systems
Booth 24
P.O. Box 161211
Austin, TX 78716-1211
(512) 263-9370
http://www.udai.com
1601 Trapelo Rd.
Waltham, MA 02154
(781) 890-3311
http://www.valor.com
Unified Design Automation will be showing the latest version of Silicon
Arena™, the high-productivity TEAM environment for ASIC and semicustom IC design. Silicon Arena integrates all of a design team’s existing
tools into an easy-to-use graphical system. Fully integrated task control,
in addition to the usual revision control and configuration management,
makes Silicon Arena the best solution for today’s complex projects. Also
in the UDAI booth, Techmate Inc. will be available to discuss meeting your
contract engineering needs with their stable of highly qualified, Silicon
Arena-trained design and methodology experts!
Enterprise 3000 is a world class DFM review system. This high
performance producibility engineering solution for the Electronic OEM, or
Contract Manufacturer delivers a complete solution for DFx. The
Enterprise 3000 combines assembly (DFA), bare board fabrication (DFF),
testability (DFT) analysis, and design review.
The Valor virtual
manufacturing system enables you to simulate the entire production
process, pinpointing potential problems, and solve them before design
release. The Enterprise 3000 interfaces directly with the most popular
PCB Layout systems such as Cadence, Mentor, Pads, Zuken Redac,
VeriBest, CADIX, and many more.
United Microelectronics Corp. Group
Booth SV10
6753 Selma Ave.
Los Angeles, CA 90028
(213) 466-5533
UMC Group is a dedicated foundry conglomerate including United
Microelectronics Corp. (UMC), United Semiconductor Corp. (USC),
United Integrated Circuits Corp. (UICC) and United Silicon, Inc. (USIC).
UMC Group offers 8” wafer production and has 0.25-micron production
capability and 0.18-micron technology in development. UMC Group is
headquartered in Hsin-Chu City, Taiwan, and has marketing and customer
service operations in the United States, the Netherlands, Japan, and
Singapore. UMC Group companies can be located through the Internet
address www.umc.com.tw, or contact [email protected].
Vamp, Inc. is the publisher of McCAD E.D.S. software, a complete family
of integrated electronic design systems for the Mac OS, Power PC and
Windows 95/NT platforms. The McCAD Electronic Design System offers
a choice of design environments with a wide range of system
configurations tailored to the specific needs of the designer. McCAD
modules take the designer through the complete design cycle; schematic
capture, simulation, standard & SMT PCB layout, autorouting & Gerber
generation for board fabrication. McCAD software gives the electronic
designer the technical range needed, and at the same time, provides
control & flexibility.
University Booth
Booth 830
Univ. of Colorado at Denver
Campus Box 110
Denver, CO 80217-3364
(303) 556-2357
http://www.acm.org/sigda
The University Booth features state-of-the-art demonstrations of research
projects by university researchers and DAC authors. Both EDA, as well as
design and instructional demonstrations are featured at the University
Booth. In addition, at the University Booth’s program corner DAC
exhibitors provide brochures on their discounted university hardware and
software programs.
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Vamp, Inc.
Booth 87
788 Palomar Ave.
Sunnyvale, CA 94086
(408) 733-8881
http://www.umc.com.tw
Vantis
Booth 236
995 Stewart Dr.
Sunnyvale, CA 94088
(888) Vantis2
http://www.vantis.com
The Vantis VF1™ Family offers designers a new level of FPGA
performance. The VF1 Variable-Grain-Architecture™ delivers the best
performance in a cost-effective 12K to 36K gate FPGA solution.
Developed concurrently with the VF1 FPGA Family, the VF1 DesignDirect™
software ensures successful design implementation with its Ease-ofSuccess™ timing driven tools and graphical interfaces. In addition, Vantis
is setting higher standards in the CPLD industry with its MACH 4 and
MACH 5 families with features such as SpeedLocking™, 3-Volt, ISP and
high performance. Stop by booth #236 to receive a copy of the VantisSynario Starter software CD.
Vantis Ad
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xhibit guide
VAutomation Inc.
Booth SV20
20 Trafalgar Sq., Ste. 443
Nashua, NH 03063
(603) 882-2282
http://www.vautomation.com
Veritools, Inc.
Booth 1818
VAutomation
provides,
high-quality,
technology-independent
synthesizable cores based on VHDL and Verilog HDL for true system-ona-chip design. Its reusable, silicon-proven cores offer high performance
through increased integration, faster time-to-market and reduced
development costs. Cores are available for the industry-standard 8086,
80186, Z80, and 65C02 microprocessors and VAutomation’s own ultralow gate count, 8-bit RISC microprocessor, the V8-uRISC. Serial
communication cores are available for USB host, hub and device
controllers, a High-Level Data Link Controller (HDLC) and an Ethernet LAN
controller.
VeriBest, Inc.
Booth 608
6101 Lookout Rd.
Boulder, CO 80301
(303) 581-2432
http://www.veribest.com
VeriBest®, Inc. is the leading provider of EDA development environments
on Windows® NT®. VeriBest offers fully integrated software for CAD, PCB,
Analog, Library and Process Management design, for high density FPGA’s
(VHDL/Verilog), complex PCB implementation (high speed design), and
design process management (PDM,CIS). This year, VeriBest introduced
software products to address the needs of all levels of designers, with
FPGA and Expedition PCB. VeriBest’s integrated system design consulting
experts align world class technology with your corporate business
objectives.
Verisity Design, Inc.
Booth 600
1943 Landings Dr.
(650) 961-5200
http://www.verisity.com
Verisity offers Specman™, a spec-based verification solution for
functional verification of electronic systems and chips. Specman provides
a complete verification solution integrated with today’s leading HDL
simulators. Spec-based verification does for verification what synthesis
did for design. It raises the level of abstraction, automates the manual
processes, and improves quality of results. To see how your engineers
can drastically reduce the overall verification cycle, drop by and see
Specmania in action at booth #600.
158
459 Hamilton Ave., Ste. 100
Palo Alto, CA 94301
(650) 462-5590
http://www.veritools-web.com
UNDERTOW VII SUITE:
Includes Undertow VII, Interactive_tool and Optimizing_tool...now
providing the most powerful tools in the world for Verilog, VHDL, mixed
mode and analog simulation.
*Undertow is now available on Windows 95, Windows NT and Linux.
VERIPOWER:
Compared to power calculations from transistor level simulators,
Veripower is 50-100 times faster, within 3% of their accuracy and at onetenth their cost.
For more information visit Veritools booth at location #1818, or visit
our web site at www.veritools-web.com.
Verplex Systems, Inc.
Booth 151
3350 Scott Blvd., Bldg. 46
(408) 980-8300
http://www.verplex.com
Hot Formal Verification startup is previewing its logic equivalence
verification product. Armed with $1 million seed funding, Verplex has
successfully developed advanced formal verification technologies with a
mission to become the superior solution provider for the formal
verification market. If you are looking for fast turnaround time; a unified
environment which supports RTL, gate-level, and transistor-level; and
easy-to-use debugging capabilities, then come to discuss your needs with
Verplex. We’ll show you how to improve your overall design and
verification productivity.
Verysys Design Automation, Inc.
Booth 100
42707 Lawrence Pl.
Fremont, CA 94538
(510) 445-3830
http://www.verysys.com
Verysys will exhibit its complete palette of formal verification tools
including PropertyProver, a powerful model checker, DesignProver, an
efficient sequential equivalence checker, and StructureProver, a potent
and robust combinational equivalence checker. These tools can certify
the correctness of an HDL design and in the case that errors are detected
can provide error diagnosis through an easy to use GUI and an automatic
schematic generator.
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Booth 1428
293 Boston Post Rd. West
Marlboro, MA 01752
(508) 303-5434
http://www.viewlogic.com
Systems Designers, see the industry’s hottest engineering tools and
solutions for designing high-speed systems with ISIS PreVUE™
interconnect planning, and XTK™ signal integrity analysis. Enhance
teamwork and improve design re-use with Design Exchange™ intra- and
inter-enterprise solutions. The most widely used solutions for languagebased FPGA design just got better with the addition of the world’s leading
FPGA synthesis tool, FPGA Express™. World-class verification products
include Fusion VCS™ Verilog and SpeedWave™ VHDL simulators.
Solutions are available on UNIX and NT.
Virage Logic
Booth 244
1641A S. Main St.
Milpitas, CA 95035
(408) 263-0160
http://www.virlog.com
Custom-Touch™ Memory Compilers quickly create a complete, high
quality embedded memory optimized for semiconductor processes.
Products include; ULP (Ultra Low Power) which draws .1 mw/MHz and
operates down to 1.0 V and HS (High Speed) which runs up to 700 MHz
(0.25-micron typical). In addition, Virage offers STMC (Self Testable
Memory Core) which integrates an optimized memory design with BIST
and Diagnostics. STMC provides the same high quality, yield and
reliability offered by stand alone memory components.
Virtual Silicon Technology, Inc.
Booth 1354
1200 Crossman Ave., Ste. 200
Sunnyvale, CA 94089
(408) 747-1950
http://www.virtualsilicon.com
Virtual Silicon’s mission is to provide the largest, most robust inventory
of Silicon Ready (“hard”) libraries, components, and services. VST has
developed its own Diplomat™ 0.25 micron design rules with leading
worldwide foundries. Working with independent vendors of semiconductor
Intellectual Property (IP), VST promotes its Diplomat family of foundry
portable cells as the foundation technology for optimum reuse and
exchange of IP. Customers and IP partners benefit by gaining access to
multiple foundries.
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VSI Alliance
Booth 115
15495 Los Gatos Blvd., Ste. 3
Los Gatos, CA 95032
(408) 356-8800
http://www.vsi.org
The VSI Alliance is an open organization comprised of all segments of the
system-chip industry segments: Electronic Design Automation (EDA), IP
providers, semiconductor vendors and system companies. (Meet the
member companies in our booth: http://www.vsi.org/. VSI’s goal is
accelerated growth of the system-chip market by developing open
technical standards, enabling the mix-and-match of IP exchanged on an
intra-and inter-company basis. Industry-wide participation is sought with
membership open to any corporation interested in development and
promotion of standards for system chip design.
Western Design Center, Inc. (The)
Booth SV35
2166 E. Brown Rd.
Mesa, AZ 85213
(602) 962-4545
http://www.design.com
WDC is the original source and Intellectual Property (IP) owner of the
patented CMOS 65C02 8-bit and 65C816 16-bit microprocessors. As an
industry-standard microprocessor family, these microprocessors have
been designed for reuse and are available in soft, firm and hard core
versions. Our licensees include foundries, library companies, design
service companies and system companies. Chips, developer boards and
a software development system are available from WDC for system-chip
development. WDC has provided microprocessor IP to the electronics
industry since 1981.
X-Tek Corp.
Booth 2522
4439 W. Fallen Leaf Ln.
Glendale, AZ 85301
(602) 879-6731
http://www.x-tekcorp.com
X-Tek unveils X-CDE, the radically new Comprehensive Design
Environment. Exceed your limitations, break away from dead-end HDLbased methodologies, and blast into the millennium with the state of the
art technology. X-CDE offers development of language independent
models using either stochastic or deterministic techniques. Intuitive
graphical design entry, coupled with simulation and formal verification
capabilities, allows fast paced engineers to successfully perform design
and analysis with ease. Succeed with X-CDE, stop at Booth 2522, get
your diploma, and let X-Tek blow you away!
Western
Design
Center Ad
e
xhibit guide
Xentec Inc.
Booth 153
Xynetix Design Systems, Inc.
Booth 730
301-2908 S. Sheridan Way
Oakville, ON L6J 7J8 Canada
(905) 829-8889
http://www.xentec-inc.com
7796 Victor-Mendon Rd.
Fishers, NY 14453
(716) 924-9303
http://www.xynetix.com
Xentec is a full-service provider of engineering services, IP and tools to
assist electronics companies moving to System-on-Chip. Capabilities
include digital, analog, mixed-signal, FPGA, and DSP design; resulting in
faster time-to-market, and faster time-to-revenue. Xentec offers the
following services:
System-on-Chip Services - turnkey design assistance
IP Core Creation and Integration - digital and analog cores
Design Environment Services - Ianguage training and design
flow/methodology development
Engineering Design Automation (EDA) Software - sales and support of
the latest high-level design tools
System performance isn’t determined by the IC alone. IC package design
and early PCB planning and analysis can have a significant performance
impact in telecom and high speed applications. Xynetix’s Encore™
software for advanced IC package design optimizes IC/package
performance for ball grid array, chip scale packaging and flip chip
interconnect. EDAn a v i g a t o r enables early analysis of boards and
systems, optimizing electrical, thermal, EMI and assembly cost tradeoffs. Sign up at booth 730 for new “Tech Talks” on advanced packaging
and high speed system design.
Xilinx, Inc.
Booth 508
2-9-32 Nakacho, Musashino-shi
Tokyo, 180-8750 Japan
(81) 422-52-5589
http://www.yokogawa.co.jp/eda/
2100 Logic Dr.
San Jose, CA 95124
(408) 559-7778
http://www.xilinx.com
Xilinx builds performance and technology leadership for all your
programmable logic needs including fast software runtimes, increased
turns-per-day, performance-optimized architectures, and predictable highperformance for IP implementation. Xilinx invented and commands more
than half of the market for FPGAs, which bring time-to-market advantages
to designers in many computer-related markets. As the leading innovator,
Xilinx offers complete programmable logic solutions, including advanced
integrated circuits, software design tools, predefined system functions,
or cores, and unparalled field engineering support.
Xilinx, Inc.
Booth SV19
2100 Logic Dr.
San Jose, CA 95124
(408) 559-7778
http://www.xilinx.com
Xilinx builds performance and technology leadership in all areas of
programmable logic including fast software runtimes, increased turns-perday, performance-optimized architectures, and predictable highperformance for IP implementation. On display in the Silicon Village booth
is evidence of the Xilinx process, density, and performance leadership
through devices built on leading-edge 0.25 processes, industry-leading
densities to half-million gates, and robust and cost-optimized FPGA and
CPLD architectures. Drop by and see how Xilinx complete programmable
logic solutions will build your future successes.
162
Yokogawa Electric Corp.
Booth 2052
VirtualICE™ is a hardware/software co-design tool that reduces
development time and ASIC respins. VirtualICE enables you to solve the
problems across the boundaries of hardware and software. VMlink
(Verilog-MATLAB interface) provides new design methodology of digital
signal processing system.
Zuken-Redac, Inc.
Booth 308
2041 Mission College Blvd., Ste. 260
(888) 332-7227
http://www.redac.co.uk
Zuken-Redac will be exhibiting world leading Unix and PC-based
PCB/MCM toolsets, focusing this year on two new products: Hot-Stage
and Intraprise solutions. Hot-Stage is a set of tools designed to increase
productivity by breaking down the boundaries of traditional PCB/MCM and
design engineering. The Intraprise bridges the gap between the EDA user
and the Enterprise. Project leaders are given increased visibility and
control over the design process, and users are given guidance, leading to
a more productive environment.
Xilinx Ad
e
xhibit guide
Zycad Corp.
See GateField Corp. in Booth #908.
Zycad TSS Corp.
Booth 77
4061 Clipper Ct.
Fremont, CA 94538
(800) 852-7318
http://www.zycad.com
Zycad TSS provides engineering and support services for the Zycad
Paradigm XP family of gate level and fault simulations accelerators that
are used in high speed verification and test of complex ASIC and large
system designs. The product supports a Verilog XL compatible interface
through industry standard VXI and VM interfaces. The Paradigm Library
Tools allow users to convert Verilog based libraries to the Paradigm XP.
Standard Interfaces are also available for Mentor, Synopsys and
Viewlogic design environments. Zycad TSS provides full range of
engineering services to assist users in design verification, fault
simulation, model generation, and library generation.
164
Verplex Ad
e
xhibit guide
Actel Corp.
Booth SV18
MicroMagic, Inc.
Booth 93
955 E. Arques Ave.
Sunnyvale, CA 94086
(408) 739-1010
http://www.actel.com
333 W. El Camino, Ste. 240
Sunnyvale, CA 94087
(408) 735-9200 x-200
http://www.micromagic.com
Actel is dedicated to providing logic designers with the capability and
confidence to successfully move up to higher complexity designs. The
company is the world’s leading supplier of antifuse-based field
programmable gate arrays (FPGAs) and associated software development
tools. FPGAs are used by designers of communications, computer, medical,
military/aerospace, industrial control, and other electronic systems to
differentiate their products and get them to market faster.
Micro Magic’s business model is:
1. Design Services specializing in high speed digital design and
embedded module generation (SRAMs, RAMs, ROMs, etc.).
2. Intellectual Property including SRAMs, ROMs, Libraries, ALUs and advanced
memory redunduncy scheme.
3. Design tools, front and back, and design environment management.
Our designer staff is mostly PhDs from Stanford, Berkeley and MIT.
Compilogic Corp.
Booth 67
SyntyX Technology
Booth 91
2105 Hamilton Ave., Ste. 310
San Jose, CA 95125
(408) 369-0555
http://www.compilogic.com
46 Avenue Felix Viallet
Grenoble Cedex, F-38031 France
33 476 574 615
http://www.syntyx.com
C2Verilog: Only full-featured ANSI C to synthesizable RTL Verilog compiler
yielding comparable hardware efficiencies as manual RTL coding. Also
automatic C to Verilog Test-Bench generation for Verilog simulation.
SyntyX Technology develops and markets System Level Design Tools for
HW/SW co-design and IP Creation and Reuse, characterized by the
following features:
• Standard SDL, behavioral VHDL and C entry.
• Unique solution for SDL to VHDL+C interactive system architecture
synthesis.
• High performance behavioral synthesis (from standard B-VHDL to
standard RT-VHDL).
• Inter-module interface synthesis.
• Multilanguage co-simulation back-plane.
SyntyX tools output results are both human readable and compatible with
most logic synthesis tools available on the market.
GDA Technologies, Inc.
Booth 2532
491 Macara Ave., #1002
Sunnyvale, CA 94086
(408) 730-9076
http://www.gdatech.com
166
supplemental listing
d
ac
demo suite list
Located in Halls D and E of the Moscone Center.
COMPANY NAME
BOOTH #
0-IN DESIGN AUTOMATION
ABSTRACT INC.
ADVANCED TECHNOLOGY CENTER, COVERMETER DIVISION
ALDEC, INC.
ALTERA CORP.
ALTERNATIVE SYSTEM CONCEPTS, INC.
AMBIT DESIGN SYSTEMS, INC.
ANALOGY, INC.
APTEQ DESIGN SYSTEMS, INC.
APTIX CORP.
ARCADIA DESIGN SYSTEMS, INC.
ARISTO TECHNOLOGY
ARTISAN COMPONENTS, INC.
ASPEC TECHNOLOGY, INC.
AVANT! CORP.
AXIS SYSTEMS
CADABRA
CADENCE DESIGN SYSTEMS, INC.
CADMOS DESIGN TECHNOLOGY, INC.
CAE PLUS, INC.
CAST, INC.
CHRONOLOGY CORP.
CHRYSALIS SYMBOLIC DESIGN
CIRCUIT SEMANTICS, INC.
COMPAQ COMPUTER CORP.
COWARE, INC.
DESIGN ACCELERATION
DESIGN AND REUSE
DUET TECHNOLOGIES
DYNACHIP CORP.
EE TIMES/EDTN/CMP MEDIA
ESCALADE CORP.
EVEREST DESIGN AUTOMATION
EXEMPLAR LOGIC
FREQUENCY TECHNOLOGY, INC.
FUJITSU/ICL
GAMBIT AUTOMATED DESIGN, INC.
GATEFIELD CORP
HEWLETT-PACKARD CO.
IBM CORP.
IKOS SYSTEMS INC.
IMODL, INC.
IN-CHIP SYSTEMS, INC.
INCASES NORTH AMERICA
INFOQUICK
INTEGRATED SYSTEM DESIGN
INTRINSIX CORP.
LEGEND DESIGN TECHNOLOGY, INC.
LOGICVISION, INC.
LSI LOGIC CORP.
LUCENT TECHNOLOGIES, BELL LABS DESIGN AUTOMATION
4750
4510
4435
4272
4320
4840
4625
4710
4245
4065
4050
4548
4620
4755
4705
4005
4525
4730
4280
4735
4260
4230
4405
4310
4830
4712
4265
4714
4042
4075
4665
4810
4540
4765
4080
4410
4035
4415
4085
4645
4430
4605
4030
4825
4835
4650
4720
4120
4052
4555
4040
4530
4325
COMPANY NAME
MENTOR GRAPHICS CORP.
MEROPA, INC.
MODEL TECHNOLOGY, INC.
MONTEREY DESIGN SYSTEMS, INC.
MOSCAPE INC.
NOVAS SOFTWARE, INC.
NURLOGIC DESIGN, INC.
OMNIVIEW DESIGN, INC.
OPC TECHNOLOGY INC.
OPMAXX, INC.
ORCAD
PADS SOFTWARE, INC.
PROVIS CORP.
QUICKTURN DESIGN SYSTEMS, INC.
RELAY DESIGN AUTOMATION
RUBICAD CORP.
SAGANTEC
SENTE INC.
SILICON INTEGRATION INITIATIVE, INC. (SI2)
SILICON RESOURCES
SILVACO INTERNATIONAL
SIMPLEX SOLUTIONS, INC.
SIMPOD, INC.
SUMMIT DESIGN, INC.
SUN MICROSYSTEMS
SUREFIRE VERIFICATION INC.
SYCON DESIGN, INC.
SYNCHRONICITY INC.
SYNOPSYS, INC.
SYNPLICITY, INC.
SYNTYX TECHNOLOGY
SYSTEMS SCIENCE, INC.
TARGET COMPILER TECHNOLOGIES N.V.
TAVEREN TECHNOLOGY, INC.
TERA SYSTEMS, INC.
TOPDOWN DESIGN SOLUTIONS, INC.
TRANGATE TECHNOLOGY, INC.
TRANSCENDENT DESIGN TECHNOLOGY, INC.
TRANSLOGIC USA CORP.
ULTIMA INTERCONNECT TECHNOLOGY
VANTIS
VERIBEST, INC.
VERISITY DESIGN, INC.
VERITOOLS, INC.
VERPLEX SYSTEMS, INC.
VERYSYS DESIGN AUTOMATION, INC.
VIEWLOGIC SYSTEMS, INC.
VIRAGE LOGIC
VIRTUAL SILICON TECHNOLOGY, INC.
VISUAL SOFTWARE SOLUTIONS
XILINX, INC.
XYNETIX DESIGN SYSTEMS, INC.
Y EXPLORATIONS, INC.
BOOTH #
4090
4740
4670
4640
4820
4250
4815
4425
4125
4210
4685
4330
4805
4205
4675
4560
4315
4715
4255
4760
4420
4450
4130
4285
4615
4235
4565
4745
4305
4505
4445
4550
4215
4070
4660
4105
4220
4290
4845
4270
4025
4725
4060
4225
4275
4045
4015
4135
4545
4240
4010
4020
4055
16
Demo Suite
Map
168
Demo Suite
Map
169
d
ac
EDA industry committee (EIC)
Chair
Thomas P. Pennino
Lucent Technologies, Bell Labs.
Rm. 1M-415
Holmdel, NJ 07733
(732) 949-7340
[email protected]
Lorie Bowlby
111 W. St. John St., Ste. 200
San Jose, CA 95113-1104
(408) 226-7240
[email protected]
Randal E. Bryant
School of CS
(412) 268-8821
[email protected]
Basant R. Chawla
Lucent Technologies
283 King George Rd.
Rm. E4D43
Warren, NJ 07059
(908) 559-4070
[email protected]
Ronald E. Collett
Collett International, Inc.
5201 Great America Pkwy.
Ste. 3238
(408) 562-6167
[email protected]
Nanette Collins
Consultant
Boston, MA 02115
(617) 437-1822
[email protected]
170
Denise Dres
OrCAD
16275 Laguna Canyon Rd.
Irvine, CA 92618
(714) 788-6080
[email protected]
Marie R. Pistilli
MP Associates, Inc.
Boulder, CO 80301
(303) 530-4562
[email protected]
Dave Guinther
Chrysalis Symbolic Design, Inc.
101 Billerica Ave., Bldg. 5
North Billerica, MA 01862
(508) 436-9909
[email protected]
Jan M. Rabaey
Univ. of California
Dept. of EECS - 511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
[email protected]
Abbie Kendall
OrCAD
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
[email protected]
Dottie Wanat
Sun Microsystems
3060 N. First St.
San Jose, CA 95134
(408) 544-0417
[email protected]
Jim Lochmiller
2655 Seely Rd.
San Jose, CA 95134
(408) 944-8095
[email protected]
Dave Orecchio
293 Boston Post Rd. West
Marlboro, MA 01752-4615
(508) 480-0881
[email protected]
d
ac
notes page
171
d
ac
index
About the Conference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Birds-of-A-Feather/Additional Meetings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40-41
Busing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Call for Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46-47
Conference Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Convention Center / Hotel Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Convention Center Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54-55
DAC Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
DAC on the WWW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
DACnet-98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Demo Suite Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Demo Suite Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Demo Suite Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168-169
Electronic Design Automation Industry Committee (EIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Executive Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Exhibit-Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Exhibit Floor Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56-58
Exhibit Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Exhibitor Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61-62
Exhibitor Presentation Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Exhibitor Presentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67-88
Exhibitor Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90-164
Exhibitor Supplemental Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
First Aid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Food Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
General Chair’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .inside front cover
Guest Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Important Information at a Glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Information Desk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
New to the Conference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Opening Keynote Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Proceedings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Program Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Program Session Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
Registration Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
San Francisco Attractions/Weather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
SIGDA Meeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Sponsorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49-50
Technical Program Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51-52
Technical Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-33
Thursday Keynote Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Topics and Related Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12
Tutorial Descriptions/Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 35-39
University Design Contest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Wednesday Night 35 Years of DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Workshop for Women in Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
172

35th final - DAC Virtual Resources

Transcription

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