SBC320 3U VPX SBC Hardware Reference Manual

Transcription

GE
Intelligent Platforms
Hardware Reference Manual
SBC320 3U VPX Single Board Computer
Second Edition
Publication No. SBC320-0HH/2DF
Document History
Edition
First
Second
2DF
Date
January 2009
March 2009
May 2010
Board Artwork Revision
Rev 2
Rev 2
No technical content change, rebranding only
Waste Electrical and Electronic Equipment (WEEE) Returns
GE Intelligent Platforms Ltd. is registered with an approved Producer Compliance Scheme (PCS) and,
subject to suitable contractual arrangements being in place, will ensure WEEE is processed in
accordance with the requirements of the WEEE Directive.
GE Intelligent Platforms Ltd. will evaluate requests to take back products purchased by our customers
before August 13, 2005 on a case by case basis. A WEEE management fee may apply.
2 SBC320 3U VPX Single Board Computer
Contents
1 • Introduction............................................................................................................................................................................. 8
1.1 Features......................................................................................................................................................................................................8
1.2 Safety Notices..........................................................................................................................................................................................9
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
Flammability...............................................................................................................................................................................................10
EMI/EMC Regulatory Compliance.....................................................................................................................................................10
Cooling..........................................................................................................................................................................................................10
Handling.......................................................................................................................................................................................................10
Heatsink .......................................................................................................................................................................................................10
1.3 Conventions Used in this Manual................................................................................................................................................ 11
1.4 Associated Documents .................................................................................................................................................................... 12
1.5 Web Sites ................................................................................................................................................................................................ 12
1.6 Technical Support............................................................................................................................................................................... 13
2 • Unpacking ............................................................................................................................................................................. 14
2.1 Box Contents Checklist..................................................................................................................................................................... 14
2.2 Identifying Your Board...................................................................................................................................................................... 15
3 • Configuration....................................................................................................................................................................... 16
3.1 Link Configuration .............................................................................................................................................................................. 16
3.2 Inspection ............................................................................................................................................................................................... 16
3.3 Link Descriptions ................................................................................................................................................................................. 17
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
Main Boot Flash Write Disable Link (E1) ........................................................................................................................................17
Flash Hard Drive Write Disable Link (E2) .......................................................................................................................................17
NVMRO Link (E11).....................................................................................................................................................................................17
E12 and E13 Links....................................................................................................................................................................................18
BANC Boot Image Select Link (E14) .................................................................................................................................................18
CMOS Default Settings Select Link (E7) ..........................................................................................................................................18
3.4 PMC Installation................................................................................................................................................................................... 19
4 • Installation and Power Up/Reset ................................................................................................................................ 20
4.1 Board Keying......................................................................................................................................................................................... 20
4.2 Board Installation Notes.................................................................................................................................................................. 20
4.3 Power Requirements......................................................................................................................................................................... 21
4.4 Connecting to SBC320...................................................................................................................................................................... 21
4.5 Power-up................................................................................................................................................................................................. 23
4.6 Inter-board Sequencing................................................................................................................................................................... 24
5 • Functional Description..................................................................................................................................................... 25
5.1 Microprocessor Subsystem............................................................................................................................................................ 25
5.2 Memory.................................................................................................................................................................................................... 27
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
SDRAM...........................................................................................................................................................................................................27
Flash Hard Drive.......................................................................................................................................................................................27
Boot Flash....................................................................................................................................................................................................27
NVRAM ..........................................................................................................................................................................................................29
E2PROMs.......................................................................................................................................................................................................29
Static RAM ...................................................................................................................................................................................................29
5.3 I/O ............................................................................................................................................................................................................... 30
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Gigabit Ethernet .......................................................................................................................................................................................30
SATA ...............................................................................................................................................................................................................30
Serial I/O.......................................................................................................................................................................................................30
GPIO................................................................................................................................................................................................................34
USB 2.0..........................................................................................................................................................................................................35
PCI Express..................................................................................................................................................................................................35
5.4 PMC............................................................................................................................................................................................................ 36
Contents 3
5 • Functional Description (continued)
5.5 Real Time Clock.................................................................................................................................................................................... 37
5.6 I2C Bus ...................................................................................................................................................................................................... 37
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Temperature Sensor...............................................................................................................................................................................39
PSU Monitor................................................................................................................................................................................................40
Elapsed Time Indicator..........................................................................................................................................................................40
Clocks ............................................................................................................................................................................................................40
Board Management Microcontroller ..............................................................................................................................................42
5.7 CPLD .......................................................................................................................................................................................................... 42
5.8 LEDs ........................................................................................................................................................................................................... 43
5.8.1
5.8.2
5.8.3
BIT LEDs (DS200 to DS203) ..................................................................................................................................................................43
Power LEDs (DS205 and DS206)........................................................................................................................................................44
Activity LEDs ...............................................................................................................................................................................................44
5.9 Write Protection................................................................................................................................................................................... 45
5.10 JTAG........................................................................................................................................................................................................ 46
5.11 Control and Status Registers...................................................................................................................................................... 47
5.11.1
5.11.2
5.11.3
5.11.4
5.11.5
5.11.6
5.11.7
5.11.8
5.11.9
5.11.10
5.11.11
5.11.12
5.11.13
5.11.14
5.11.15
5.11.16
5.11.17
5.11.18
5.11.19
5.11.20
5.11.21
5.11.22
5.11.23
Board ID Register (0x600).....................................................................................................................................................................47
Board Revision Register (0x601)........................................................................................................................................................48
Board Configuration Register 1 (0x602) ........................................................................................................................................48
VPX Geographical Address Register (0x605)...............................................................................................................................51
Alarm Status Register (0x606)............................................................................................................................................................52
Link Settings Register (0x607) ............................................................................................................................................................53
Board ID String Registers (0x610 to 0x615) .................................................................................................................................53
Control Register 1 (0x620)....................................................................................................................................................................53
IRQ Enable Register (0x623) ................................................................................................................................................................56
Drive Links Low Register (0x624) ......................................................................................................................................................56
GPIO Out Register (0x640)....................................................................................................................................................................57
GPIO In Register (0x641) .......................................................................................................................................................................57
GPIO Direction Register (0x642) ........................................................................................................................................................58
GPIO Interrupt Enable Register (0x643) .........................................................................................................................................58
GPIO Level/Edge Register (0x644) ....................................................................................................................................................60
GPIO Active Low/High Register (0x645).........................................................................................................................................60
GPIO Both Edges Register (0x646)....................................................................................................................................................62
GPIO Interrupt Status Register (0x647) ..........................................................................................................................................62
BIT Address/Data Read Back Registers (Firmware ID7 + 0x42000)..................................................................................63
5.12 Front Panel .......................................................................................................................................................................................... 63
6 • Connectors............................................................................................................................................................................ 64
6.1 VPX Connector Pinouts..................................................................................................................................................................... 66
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
P0.....................................................................................................................................................................................................................66
J0 (Backplane) ...........................................................................................................................................................................................66
P1.....................................................................................................................................................................................................................67
J1 (Backplane) ...........................................................................................................................................................................................67
P2.....................................................................................................................................................................................................................68
J2 (Backplane) ...........................................................................................................................................................................................68
Signal Descriptions..................................................................................................................................................................................69
6.2 PMC Connectors .................................................................................................................................................................................. 70
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
J11 ..................................................................................................................................................................................................................70
J12 ..................................................................................................................................................................................................................70
J13 ..................................................................................................................................................................................................................70
J14 ..................................................................................................................................................................................................................71
Signal Descriptions..................................................................................................................................................................................72
6.3 Test Connector ..................................................................................................................................................................................... 73
Appendix A - Specifications .................................................................................................................................................. 75
A.1 Electrical Specification ..................................................................................................................................................................... 75
A.2 Reliability (MTBF).................................................................................................................................................................................. 77
A.3 Build Levels ............................................................................................................................................................................................ 77
A.4 Environmental Specifications ....................................................................................................................................................... 79
A.5 Mechanical Specification................................................................................................................................................................ 80
A.5.1 Dimensions ........................................................................................................................................................................................................80
A.5.2 Weight..................................................................................................................................................................................................................80
A.6 Product Codes...................................................................................................................................................................................... 80
A.6.1 Software Support............................................................................................................................................................................................81
A.6.2 I/O Modules .......................................................................................................................................................................................................81
Glossary......................................................................................................................................................................................... 82
Index................................................................................................................................................................................................ 83
Contents 5
List of Tables
Table 5-1 Microprocessor Options........................................................................................................................................................................................................... 25
Table 5-2 Hub IDs in Boot Modes ............................................................................................................................................................................................................. 28
Table 5-3 Basic Memory Map..................................................................................................................................................................................................................... 28
Table 5-4 NVRAM Address Decoding...................................................................................................................................................................................................... 29
Table 5-5 RS232 Configuration Connections against VPX Connector Pins ........................................................................................................................... 32
Table 5-6 RS232 Configuration Connections against LE3100 Serial I/O Signals ................................................................................................................ 32
Table 5-7 RS422/485 Configuration Connections against VPX Connector Pins ................................................................................................................. 33
Table 5-8 RS422/485 Configuration Connections against LE3100 Serial I/O Signals....................................................................................................... 33
Table 5-9 GPIO Pin Electrical Characteristics at the VPX Connector ........................................................................................................................................ 35
Table 5-10 I2C Device Address Map ........................................................................................................................................................................................................ 38
Table 5-11 PSU Rail Monitoring................................................................................................................................................................................................................. 40
Table 5-12 Clock Summary ......................................................................................................................................................................................................................... 41
Table 5-13 BIT LED Meanings..................................................................................................................................................................................................................... 43
Table 5-14 Power LED Meanings.............................................................................................................................................................................................................. 44
Table 5-15 Activity LED Meanings............................................................................................................................................................................................................ 44
Table 5-16 Write Protection ........................................................................................................................................................................................................................ 45
Table 5-17 Test Connector JTAG Chains............................................................................................................................................................................................... 46
Table 5-18 Control/Status Registers ....................................................................................................................................................................................................... 47
Table 5-19 Geographic Addressing......................................................................................................................................................................................................... 51
Table 6-1 Connector Functions ................................................................................................................................................................................................................. 64
Table 6-2 P0 Connector Pin Assignments............................................................................................................................................................................................. 66
Table 6-3 J0 Connector Pin Assignments ............................................................................................................................................................................................. 66
Table 6-8 Signal Descriptions..................................................................................................................................................................................................................... 69
Table 6-9 J11 Connector Pin Assignments .......................................................................................................................................................................................... 70
Table 6-10 J12 Connector Pin Assignments........................................................................................................................................................................................ 70
Table 6-13 PMC Signal Descriptions........................................................................................................................................................................................................ 72
Table 6-14 Test Connector Pin Assignments....................................................................................................................................................................................... 73
Table 6-15 Test Connector Signal Descriptions ................................................................................................................................................................................. 74
Table A-1 Power Supply Requirements.................................................................................................................................................................................................. 75
Table A-2 SBC320-x211x Power Consumption Example............................................................................................................................................................... 76
Table A-3 SBC320-x111x Power Consumption Example............................................................................................................................................................... 76
Table A-4 MTBF Figures................................................................................................................................................................................................................................. 77
Table A-5 Convection-cooled Environmental Specifications....................................................................................................................................................... 79
Table A-6 Conduction-cooled Environmental Specifications ...................................................................................................................................................... 79
Table A-7 Product Codes.............................................................................................................................................................................................................................. 80
List of Figures
Figure 1-1 SBC320..............................................................................................................................................................................................................................................9
Figure 1-2 ESD Label (Present on Board Packaging) ....................................................................................................................................................................... 10
Figure 2-1 Box Contents............................................................................................................................................................................................................................... 14
Figure 2-2 Product Label (Packaging)..................................................................................................................................................................................................... 15
Figure 2-3 Product Label (Product) .......................................................................................................................................................................................................... 15
Figure 2-4 Product Label (Conduction-cooled Product)................................................................................................................................................................. 15
Figure 2-5 Ethernet Address Label (Product)....................................................................................................................................................................................... 15
Figure 3-1 Link Positions............................................................................................................................................................................................................................... 16
Figure 3-2 E7 Link ............................................................................................................................................................................................................................................ 18
Figure 3-3 PMC Position................................................................................................................................................................................................................................ 19
Figure 4-1 I/O Module Set-up..................................................................................................................................................................................................................... 22
Figure 5-1 Block Diagram ............................................................................................................................................................................................................................ 25
Figure 5-2 COM1 .............................................................................................................................................................................................................................................. 31
Figure 5-3 COM1 and COM2 ....................................................................................................................................................................................................................... 31
Figure 5-4 COM2 Off....................................................................................................................................................................................................................................... 31
Figure 5-5 BMM (RS232)................................................................................................................................................................................................................................ 31
Figure 5-6 GPIO Signal Isolation................................................................................................................................................................................................................ 34
Figure 5-7 PCI Express Connection.......................................................................................................................................................................................................... 36
Figure 5-8 I2C Bus Devices (7-bit Addressing) ..................................................................................................................................................................................... 37
Figure 5-9 Temperature Interrupts.......................................................................................................................................................................................................... 39
Figure 5-10 SBC320 Basic Clock Structure........................................................................................................................................................................................... 41
Figure 5-11 Rear LED Positions ................................................................................................................................................................................................................. 43
Figure 5-12 Front Panel ................................................................................................................................................................................................................................ 63
Figure 6-1 Front Connector Positions and Numbering................................................................................................................................................................... 64
Figure 6-2 Rear Connector Position and Numbering ...................................................................................................................................................................... 65
List of Figures 7
1 • Introduction
GE Intelligent Platforms’ SBC320 is a rugged Pentium M processor‐based Single Board Computer in the 3U VPX form factor, aimed at processing, communications and display applications in the military and aerospace market. The PC‐like SBC320 implements the 1.5 GHz L7400 Intel Core Duo processor architecture, and has I/O interfaces including Gigabit Ethernet, USB 2.0, SATA and GPIO. An Intel LE3100 Whitmore Lake single integrated bridge provides a DDR2 SDRAM interface with ECC, along with SATA, two USB 2.0 ports and two UART COM ports. Dual 10/100/1000Base Ethernet is provided on‐board, together with a single PMC site running at up to 133 MHz PCI‐X with full 64‐bit I/O connected directly to the VPX backplane. The SBC320 supports eight PCI Express lanes with various configurations to the backplane for connection to other cards in the system. The SBC320 is supplied with a BIOS, supporting operating systems such as Microsoft Windows XP, Windows XP Embedded, Linux and VxWorks. 1.1 Features
•
Intel Pentium M processor‐based SBC •
1.5 GHz Intel Core Duo L74001 •
Intel LE3100 chipset •
Up to 2 GBytes DDR2 SDRAM •
Dual 10/100/1000 Ethernet •
8 lanes of PCI Express in various configurations to the backplane with non‐
transparent operation •
3U VPX form factor •
PMC site 64‐bit/133 MHz PCI‐X with full 64‐bit I/O to backplane •
On‐board 512 MByte Flash drive2 •
Air‐ and conduction‐cooled variants 1
2
Contact the factory for latest processor offerings.
Contact the factory for current Flash drive capacities.
Figure 1-1 SBC320
1.2 Safety Notices
The following general safety precautions represent warnings of certain dangers of which GE Intelligent Platforms is aware. Failure to comply with these or with specific Warnings and/or Cautions elsewhere in this manual violates safety standards of design, manufacture and intended use of the equipment. GE Intelligent Platforms assumes no liability for the user’s failure to comply with these requirements. Also follow all warning instructions contained in associated system equipment manuals. WARNINGS
Use extreme caution when handling, testing and adjusting this equipment. This device may operate in
an environment containing potentially dangerous voltages.
Ensure that all power to the system is removed before installing any device.
To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground.
If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must
meet IEC safety standards.
Introduction 9
1.2.1
Flammability
The circuit board is made by a UL‐recognized manufacturer and has a flammability rating of UL94V‐1. 1.2.2
EMI/EMC Regulatory Compliance
CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to EMI if not installed and used in a cabinet with adequate EMI protection.
The SBC320 is designed using good EMC practices and, when used in a suitably EMC‐compliant chassis, should maintain the compliance of the total system. The SBC320 also complies with EN60950 (product safety), which is essentially the requirement for the Low Voltage Directive (73/23/EEC). Air‐cooled build levels of the SBC320 are designed for use in systems meeting VDE class B, EN and FCC regulations for EMC emissions and susceptibility. Conduction‐cooled build levels of the SBC320 are intended for integration into EMC hardened cabinets/boxes. 1.2.3
Cooling
CAUTION
The SBC320 requires air-flow of at least 300 feet/minute for build levels 1 and 2, and at least
600 feet/minute for build level 3. If a conduction-cooled (level 4 or 5) SBC320 is operating on an
extender card, it requires air-flow of at least 300 feet/minute across it.
1.2.4
Handling
Figure 1-2 ESD Label (Present on Board Packaging)
1.2.5
Heatsink
CAUTIONS
Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so
users should have no reason to remove it.
Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws
attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage
components beneath it. Removal and re-attachment of the heatsink should only be carried out by
the factory.
1.3 Conventions Used in this Manual
All numbers are expressed in decimal, except addresses and memory or register data, which are expressed in hexadecimal. Where confusion may occur, decimal numbers have a “D” subscript and binary numbers have a “b” subscript. The prefix “0x” shows a hexadecimal number, following the ‘C’ programming language convention. Thus: One dozen = 12D = 0x0C = 1100b The multipliers “k”, “M” and “G” have their conventional scientific and engineering meanings of *103, *106 and *109 respectively. The only exception to this is in the description of the size of memory areas, when “K”, “M” and “G” mean *210, *220 and *230 respectively. NOTE
When describing transfer rates, “k”, “M” and “G” mean *103, *106 and *109 not *210, *220 and *230.
Multiple bit fields are numbered from 0 to n, where 0 is the LSB and n is the MSB. Signal names ending with a tilde (~) denote active low signals; all other signals are active high. Filenames are shown in bold, e.g. apps/code.exe. Code excerpts, function names etc. are shown in courier typeface. When showing user interaction on a terminal, messages from the system are shown in courier typeface, i.e. messages, and user input is shown in bold courier typeface, i.e. user input. The symbol “↵” is used to represent the ‘↵’, ‘enter’, ‘return’ etc. key on the keyboard. This manual uses the following types of notice: NOTE
Notes call attention to important features or instructions.
WARNING
Warnings alert you to the risk of severe personal injury.
CAUTION
Cautions alert you to system danger or loss of data.
TIP
Tips give helpful hints on how to achieve things.
LINK
Links go to other manuals or web sites.
Introduction 11
1.4 Associated Documents
Due to the complexity of some of the parts used on the SBC320, it is not possible to include all the detailed data on all such devices in this manual. A list of the specifications and data sheets that provide additional information follows: VPX Standard, VITA 46.0 – 2007. VPX Power Sequencing and System Management VITA 46.13. LINK
Available at http://www.vita.com.
NOTE
Registration may be required for access to standards.
1.4.1
GE Intelligent Platforms Associated Documents
This document is distributed via CD‐ROM and the internet. The CD‐ROM allows privileged access to an Internet resource containing the latest updated documents. Alternatively, you may register for access to all manuals via the website whose link is given below. LINKS
PMC Installation Note, publication number HN4/3-99.
VPX I/O Modules Manual, publication number VPXIOM-0HH.
Linux Software Developer’s Kit Software Reference Manual, publication number VPXSDK-LIN0HL.
1.5 Web Sites
Information regarding all GE Intelligent Platforms products can be found on the following website: LINK
http://www.ge-ip.com/products/family/embedded-systems/
Manufacturers of many of the devices used on the SBC320 maintain FTP or web sites. Some useful sites are: LINKS
http://www.intel.com for processor and chip set information.
http://www.plxtech.com for PCIe bridge/switch information.
http://www.latticesemi.com for CPLD information.
http://www.pcisig.org for PCI Bus standards.
http://www.vita.com/vso for VPX (VITA 46) and PMC (VITA 32) standards.
NOTE
Registration may be required for access to standards.
1.6 Technical Support
1.6.1
Contact Information
Technical assistance contact details can be found on the web site Support Locator page. The appropriate location is headed “DSP, SBCs, Multiprocessors and Graphics (formerly Radstone)”. LINK
http://www.ge-ip.com/support/embeddedsupport/locator.
Queries will be logged on the Technical Support database and allocated a unique Service Request (SR) number for use in future correspondence. Alternatively, you may also contact GE Intelligent Platforms’ Technical Support via: LINK
[email protected]
TELEPHONE
+44 (0) 1327 322760
1.6.2
Returns
If you need to return a product, there is a Return Materials Authorization (RMA) request form that can be printed out and filled in, available via the web site Repairs page. LINK
http://www.ge-ip.com/support/embeddedsupport/rmalocator.
Follow the “Download RMA Request Form (Word Doc)” hyperlink under “DSP, SBCs, Multiprocessors and Graphics (Formerly Radstone)”. Do not return products without first contacting the factory. Publication No. SBC320-0HH/2DF
Introduction 13
2 • Unpacking
On receipt of the shipping container, if there is any evidence of physical damage, the Terms and Conditions of Sale (provided with your delivery) give information on what to do. If you need to return the product, contact your local GE Intelligent Platforms Sales Office or Agent. The SBC320 is sealed into an antistatic bag and housed in a padded cardboard box. Failure to use the correct packaging when storing or shipping the board may invalidate the warranty. 2.1 Box Contents Checklist
1. SBC320 in antistatic packaging. 2. Manual CD‐ROM (design may vary). 3. Embedded Software License Agreement (GFJ‐353). Figure 2-1 Box Contents
2.2 Identifying Your Board
The SBC320 is identified by labels at strategic positions. These can be cross‐checked against the Advice Note provided with your delivery. Identification labels, similar to the example shown in Figure 2‐2, attached to the shipping box and the antistatic bag give identical information: product code, product description, equipment number and board revision. Figure 2-2 Product Label (Packaging)
On the board within the antistatic bag, there is an identifying label, similar to the example shown in Figure 2‐3, attached to the PCB. Figure 2-3 Product Label (Product)
On conduction‐cooled versions of the board (build levels 4 and 5), there is also a label, similar to the example shown in Figure 2‐4, attached to the front panel. Figure 2-4 Product Label (Conduction-cooled Product)
A label, similar to the example shown in Figure 2‐5, giving the board’s hardware Ethernet address is also attached to the rear of the printed wiring board. Figure 2-5 Ethernet Address Label (Product)
00-80-8E
00-50-93
See the Product Codes section in Appendix A for more details on the product code (SBC320‐xxxxx). Publication No. SBC320-0HH/2DF
Unpacking 15
3 • Configuration
3.1 Link Configuration
The SBC320 has push‐on jumpers included in the standard kit of parts; additional jumpers may be obtained on request. These are suitable for level 1 to 3 low vibration applications. TIP
For Level 4 and 5 products, make links by wire-wrapping between the pin posts and then cover these
wire wrapped links with the same conformal coating as that used on the board. This will provide a
reliable connection under heavy shock and vibration conditions and further prevent oxidation of the
connection due to moisture ingress.
Figure 3-1 Link Positions
Figure 3‐1 shows standard 2.54 mm pitch headers for general use. This manual refers to jumper settings as In or Out. Meanings are as follows: In = jumper fitted ‐ Out = jumper not fitted ‐ 3.2 Inspection
The SBC320 is shipped from the factory with no jumpers fitted. 16 SBC320 3U VPX Single Board Computer
3.3 Link Descriptions
NOTES
1.
Ordinary operation requires no jumpers to be fitted.
2.
The states of all the links can be read from the CPLD Link Settings Register (offset 0x607).
3.3.1
Main Boot Flash Write Disable Link (E1)
This link disables writes to the Main boot Flash, as follows: Setting
In
Out
Meaning
Main boot Flash write protected
Main boot Flash write enabled (default)
If the SBC320 is a VPX slave card, then if the VPX NVMRO signal is active, writes to the Main boot Flash are inhibited, regardless of the setting of this link. 3.3.2
Flash Hard Drive Write Disable Link (E2)
This link disables writes to the Flash hard drive, as follows: Setting
In
Out
Meaning
USB Flash disk write protected
USB Flash disk write enabled (default)
If the SBC320 is a VPX slave card, then if the VPX NVMRO signal is active, writes to the Flash hard drive are inhibited, regardless of the setting of this link. 3.3.3
NVMRO Link (E11)
This link controls the overall write protection for the non‐volatile memory devices on the SBC320 that are not Flash‐type devices, as follows: Setting
In
Out
Meaning
The system’s non-volatile memory is write protected
The system’s non-volatile memory is write enabled if either the
VPX NVMRO signal is low or the SBC320 is System Controller (default)
NOTE
The System Controller function of the SBC320 is enabled (pin low) or disabled (pin high) by the VPX
SYS_CON backplane signal.
Configuration 17
3.3.4
E12 and E13 Links
Software can read the states of these links in the Board Configuration Register 1 (offset 0x602). The default is jumpers out. During ‘normal’ operation, they are used by BIT (see the SBC320 BIT manual for more details). LINK
VPXT3BIT on SBC320 Software Reference Manual, publication number VPXT3BIT-SBC320–0HL.
These links also provide E7 (see below). 3.3.5
BANC Boot Image Select Link (E14)
This link selects boot from the image in the BANC boot Flash, as follows: Setting
In
Out
Meaning
SBC320 boots from the BANC boot image
SBC320 boots from the main boot image (default)
3.3.6
CMOS Default Settings Select Link (E7)
When the CMOS settings have become corrupted, this link makes the BIOS use the default CMOS settings, as follows: Setting
In
Out
Meaning
BIOS uses default CMOS settings
BIOS uses saved CMOS settings (default)
This link is made by linking E12 pin 2 to E13 pin 2, as shown below, and needs to be removed after defaulting the CMOS, to allow BIT to use E12 and E13 correctly. Figure 3-2 E7 Link
During this operation, software may use the Drive Links Low Register (offset 0x624) in determining the link state. NOTE
For the BIOS to detect link E7 fitted, the SBC320 must be completely power cycled - including standby
and AUX supplies.
3.4 PMC Installation
One single width PMC may be fitted to the SBC320, which is fixed at 3.3 V signaling only. Figure 3‐3 shows the position of this PMC. CAUTION
The SBC320 does not support 5 V signaling only PMCs. Fitting a 5 V signaling PMC may cause damage
to the board and/or the PMC.
PMCs supplied by GE Intelligent Platforms are delivered with a full kit of parts for mounting them, fitting instructions and a manual (on CD‐ROM). A PMC ordered with an SBC320 can be supplied factory fitted, if required. LINK
PMC Installation Note, publication number HN4/3-99.
CAUTION
Observe handling and anti-static precautions when fitting the PMC.
It will usually be necessary to install driver software or implement other firmware configuration to achieve full functionality of a PMC (see the specific PMC manual for the exact procedure). TIP
Where a PMC is not pre-installed, prove operation of the SBC320 before installing the PMC.
Figure 3-3 PMC Position
Configuration 19
4 • Installation and Power Up/Reset
Review the Safety Notices section before installing the board. The following notices also apply: CAUTIONS
The SBC320 has been specifically designed for use with 3U VPX backplanes and is not compatible with
6U backplanes. Plugging the board into a 6U backplane may cause permanent component damage.
Consult the enclosure documentation to ensure that the SBC320’s power requirements are
compatible with those supplied by the backplane.
See overleaf for SBC320 power supply requirements. 4.1 Board Keying
The 3U VPX backplane specification requires all backplane slots to have two guide pins: one above the J0 connector and one below the J2 connector. As well as providing correct alignment, these pins are keyed to prevent cards being inserted into incorrect backplane slot(s) to avoid electrical incompatibility. The SBC320 has receptacles for these guide pins (see the Connectors section). By default, these are not keyed. Please contact the factory to discuss keying requirements. 4.2 Board Installation Notes
1. Keying may dictate the backplane slot(s) into which the SBC320 can be inserted. 2. Air‐cooled versions have an injector/ejector handle to ensure that the backplane connectors mate properly with the backplane. The captive screws at the top and bottom of the front panel allow the SBC320 to be tightly secured in position, which provides continuity with the chassis ground of the system. 3. Conduction‐cooled versions have screw‐driven wedgelocks at the top and bottom of the board to provide the necessary mechanical/thermal interface. Correct adjustment requires a calibrated torque wrench with a hexagonal head of size 3/32” (2.38 mm), set to between 0.6 and 0.8 Nm. 4. In an air‐cooled development enclosure, when taking I/O connections from the backplane connectors, use of GE Intelligent Platforms’ I/O modules (or some equivalent system) ensures optimum operation with regard to EMI. See overleaf for more details on the I/O modules. 20 SBC320 3U VPX Single Board Computer
4.3 Power Requirements
The SBC320 may require up to 5 A from the +3.3 V supply and up to 12 A from the +5 V supply. For more details, see the Electrical Specification in Appendix A. 4.4 Connecting to SBC320
To interact with on‐board firmware requires the SBC320 to have, as a minimum, a control terminal or HyperTerminal connection present on the serial COM1 port. A VGA monitor connected to the RGB outputs, USB keyboard/mouse and Ethernet connection may also be required for Host/Target interaction. For development systems, connection to the Serial, USB keyboard/mouse, Ethernet and Graphics ports can be achieved using a rear transition module. This converts the condensed pin out of the backplane connectors to pinouts suitable for use by industry standard connectors. The following items are required: •
The SBC320 •
A rear transition module (VPX3UX600) •
A null‐modem 9‐way micro D to 9‐way micro D‐type cable for connecting COM1 to a control terminal or HyperTerminal •
A USB keyboard/mouse •
For the Ethernet port, a CAT5 (or better) straight‐through patch cable for 10/100/1000BaseTX •
A PMC graphics card or a VPX graphics card •
A VGA monitor and suitable cables Figure 4‐1 shows an example of how the relevant parts connect. The VPX I/O Modules manual contains more details on fitting backplane modules. LINK
VPX I/O Modules Manual, publication number VPXIOM-0HH
Similar antistatic and safety precautions apply when handling and/or installing I/O modules as for the SBC320. COM1 is configured as DTE with default settings of 115200 baud, 8 bits/character, 1 stop bit, parity disabled and no flow control. Publication No. SBC320-0HH/2DF
Installation and Power Up/Reset 21
Figure 4-1 I/O Module Set-up
4.5 Power-up
As the SBC320 runs through its boot sequence, the LEDs light, and the serial terminal should display the BIOS POST codes. The LEDs section describes the function of the LEDs. LINK
The BIOS POST codes are detailed in
http://www.ami.com/support/downloaddoc.cfm?DLFile=support/doc/AMIBIOS8_Checkpoint_and_Bee
p_Code_List_PUB.pdf&FileID=928.
4.5.1
Power-up/Reset Sequence
From the application of 3.3 V and 5 V power to all components being out of reset typically takes 250 ms. Since the ramp‐up times of the 3.3 V and 5 V system PSU and the on‐board PSUs will vary with load, the time taken for the SBC320 to come out of reset will vary from system to system. It is the software’s responsibility to account for this. The SBC320’s power‐on/reset sequence has the following order: 1. Wait for the 3.3 V Auxiliary supply (P3V3_AUX), main 3.3 V (P3V3) and 5 V (VCC) VPX power rails to be within specification. 2. Wait for VPX SEQ_IN to go high or 500 mS timeout. 3. Start all on‐board power supplies except the core supply. 4. Wait for the 1.05 V supply to be with specification. 5. Start the core supply. 6. Wait for all power supplies to stabilize and be with in specification. 7. Wait 100 mS. 8. The power supply control drives PWROK to the Intel LE3100. 9. Wait for the Intel LE3100 to de‐assert Platform Reset to the rest of the chip set. 10. The processor fetches the first instruction from the Firmware Hub and runs the BIOS. Publication No. SBC320-0HH/2DF
Installation and Power Up/Reset 23
4.6 Inter-board Sequencing
The SBC320 supports inter‐board sequencing as defined by the VPX Power Sequencing and System Management specification VITA46.13. This allows for the sequencing of power between several boards in a system to be controlled. The power manager holds off all on‐board supplies (except the 3.3 V AUX supply) when the PSU_SEQ_IN signal is held low. The power manager initiates the power‐
on sequence if the PSU_SEQ_IN signal remains low 500 ms after the off‐board supplies are within specification (allowing for the possibility that the previous board in the chain has failed). The power manager drives the PSU_SEQ_OUT signal low when the backplane supplies are out of specification and until it is deemed that inrush currents associated with power‐on have subsided. The PSU_SEQ_OUT signal is not driven low when the power is removed as a result of the BMM_OFF signal being asserted. 24 SBC320 3U VPX Single Board Computer
5 • Functional Description
Figure 5-1 Block Diagram
5.1 Microprocessor Subsystem
The core chipset is based on Intel’s LE3100 mobile technology and consists of: •
1.5 GHz Intel Core 2 Duo L7400 processor •
LE3100 Bridge (Whitmore Lake) LINKS
For more details on the processors, see http://www.intel.com/design/intarch/core2duo/index.htm.
For more details on the chipset, see http://www.intel.com/design/chipsets/embedded/LE3100.htm.
Table 5‐1 shows the processor options (at the time of writing) that could be fitted. Contact your nearest GE Intelligent Platforms Sales Office or Agent for the latest processor options and speeds. Table 5-1 Microprocessor Options
Processor
Type
ULV423
U2500
L2400
T2500
L7400
T7400
Celeron
Yonah
Yonah
Yonah
Merom
Merom
Speed
(GHz)
1.06
1.2
1.66
2
1.5
2.16
Cache Size
(MBytes)
1
2
2
2
4
4
Typical CPU Power
(Watts)
5.5
9
15
31
17
34
Front Side Bus
133 MHz (533)
133 MHz (533)
166 MHz (667)
166 MHz (667)
166 MHz (667)
166 MHz (667)
Due to the high power dissipation of some of the processors, their use on the SBC320 may be limited to certain build levels. Publication No. SBC320-0HH/2DF
Functional Description 25
5.2 Memory
5.2.1
SDRAM
The SBC320 can have 0.5, 1 or 2 GBytes of SDRAM, using DDR2 single channel supporting full ECC running at 200 MHz. This interface gives a theoretical maximum burst bandwidth of 3.2 GBytes per second. The ECC logic in the Intel LE3100 is capable of correcting single bit errors and detecting multi‐bit errors. The Intel LE3100 also supports hardware ECC scrubbing for all populated SDRAM memory space. This hardware detects, logs and corrects any single‐bit ECC errors, and logs any uncorrectable error that it encounters. There are various mechanisms for reporting these errors, which are all under software control. NOTE
The 2 GByte version of the SBC320 uses the PMC 'Keep Out’ area to fit the extra bank of SDRAM. This
may preclude the use of some PMC cards.
5.2.2
Flash Hard Drive
An embedded Flash hard disk drive is provided to hold user data or an operating system. The drive capacity is currently 512 MBytes arranged and residing as a USB Flash drive. Contact your nearest GE Intelligent Platforms Sales Office or Agent for latest USB Flash capacities. Write protection is achieved by the Flash Hard Drive Write Disable Link (E2). 5.2.3
Boot Flash
The SBC320 has two firmware hubs: Main and BANC. Each of these is 16 Mbits, organized as 2 MBytes x 8 bits. There is a BANC Boot Image Select Link (E14) that swaps the two devices to allow selection of different boot firmware. If the hardware detects that the SBC320 has not started running the BIOS within four seconds, it automatically swaps the Main and BANC images over. The BIOS running is detected by a BIOS post code of 0xD3. With the standard factory BIOS, this means that the BIOS has passed the basic checksum test. If non factory boot code is programmed into the firmware hubs, the value 0xD3 needs to be written to I/O port 80 during the boot process to stop the hardware resetting the SBC320. The status of the “Auto Boot Swap” can be read back from the Board Configuration Register 1 (0x602) bit 4. “Auto Boot Swap” is disabled when the SBC320 is booted from the Test Adapter card. The Main Boot Flash Write Disable Link (E1) controls write protection for the Main boot Flash. Writes to the BANC boot flash are enabled by carrying out the following two stage write cycle (this protects the BANC area from being corrupted by a crash, as it requires a hardware jumper to be moved during the cycle): •
Fit a jumper across the Main Boot Flash Write Disable link (E1) •
Write 0x25 to I/O register 0x670 26 SBC320 3U VPX Single Board Computer
•
Remove the jumper from the Main Boot Flash Write Disable link (E1) •
Write 0x08 to I/O register 0x671 •
Refit the jumper on the Main Boot Flash Write Disable link (E1) Writes to the BANC boot flash are now enabled. NOTE
Writes to the BANC boot Flash can also be enabled by fitting the Test Adapter card, but this is for
Factory/Field Application Engineer use only.
If the SBC320 is System Controller, the NVMRO Link (E11) does not affect the Flash write protection. If the SBC320 is a VPX Slave, and the VPX NVMRO signal is active, all writes to both the firmware hubs are inhibited regardless of link settings. Bit 4 of the Board Configuration Register 3 (offset 0x604) shows the status of the software write enable. Table 5‐2 shows how the firmware hub IDs change under different Boot Flash modes: Table 5-2 Hub IDs in Boot Modes
Boot Mode
Default
BANC
Test Adapter card
Main Hub ID
0
1
2
BANC Hub ID
1
0
3
Test Adapter Hub ID
4
4
0
By default, the LE3100 sets up the memory map shown in Table 5‐3 for the LPC IDs: Table 5-3 Basic Memory Map
Start Address
0xFFF0 0000
0xFFE0 0000
0xFFD0 0000
0xFFC0 0000
0xFFB0 0000
0xFFA0 0000
0xFF90 0000
0xFF80 0000
0xFF70 0000
0xFF60 0000
0xFF50 0000
0xFF40 0000
0xFF30 0000
0xFF20 0000
0xFF10 0000
0xFF00 0000
End Address
0xFFFF FFFF
0xFFEF FFFF
0xFFDF FFFF
0xFFCF FFFF
0xFFBF FFFF
0xFFAF FFFF
0xFF9F FFFF
0xFF8F FFFF
0xFF7F FFFF
0xFF6F FFFF
0xFF5F FFFF
0xFF4F FFFF
0xFF3F FFFF
0xFF2F FFFF
0xFF1F FFFF
0xFF0F FFFF
Size (MBytes)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ID
0
1
2
3
0
1
2
3
4
5
6
7
4
5
6
7
5.2.4
NVRAM
The Intel LE3100 has an LPC interface, which is like a 4‐bit wide PCI bus running at 33 MHz and may be used to connect Firmware Hubs and devices like SuperIOs. This interface is used, with some support from on‐board logic, to give a simple parallel bus, which provides software with a faster interface than a serial I²C bus. As well as the Boot Flash firmware hubs, this parallel bus also connects to a 128 KByte non‐volatile static RAM using a Simtek STK14CA8 part, configured in Autostore mode. This part is mapped into the memory map as ID7 with the address base of 0x0. By default, the LE3100 decodes 0xFF00 0000 to 0xFF0F FFFF and 0xFF40 0000 to 0xFF4F FFFF as ID7 (see Table 5‐3). The SBC320 decodes these address ranges to the areas shown in Table 5‐4: Table 5-4 NVRAM Address Decoding
Address Range
0xFF00 0000 to 0xFF01 FFFF
0xFF02 0000 to 0xFF0F FFFF
0xFF44 0000 to 0xFF4F FFFF
Area
Simtek 128 KByte non-volatile RAM
Reserved
CPLD registers aliased on 128-byte boundaries (read only)
16-bit access reflects the address of access as data (read only)
Reserved
Depending on whether the SBC320 is System Controller, the NVRAM is write‐
protected by the VPX NVMRO signal or the NVMRO Link (E11). 5.2.5
E2PROMs
There are two Serial E²PROMs on the SBC320 I²C bus. The addresses 0xA0, 0xA2, 0xA4 and 0xA6 are reserved for the memory timing data of the SDRAM banks, so the SDRAM memory E²PROM is at address 0xA6. The other E²PROM can be used to store the BIOS settings; its address is set to 0xAC. Both of these devices are 2 Kbits (256 bytes) and use the M24C02 part or equivalent. Depending on whether the SBC320 is System Controller, these devices are write‐
protected by the VPX NVMRO signal or the NVMRO Link (E11). CAUTION
BIOS uses the parameters stored in the DDR2 memory E²PROM to configure the Intel LE3100 correctly.
Changing these values could inhibit board operation and result in the SBC320 having to be returned to
the factory for reprogramming.
5.2.6
Static RAM
The RTC module in the Intel LE3100 has 242 bytes of Static RAM. This is divided into two sections: a lower bank of 114 bytes and an upper bank of 128 bytes. This Static RAM is powered from the VPX 3.3 Volt Auxiliary supply (P3V3_AUX), so data will be lost if that supply is removed. The BIOS uses this Static RAM for its data storage, so it is not normally available for user data. There is no write protection on this memory; it is always writable. 28 SBC320 3U VPX Single Board Computer
5.3 I/O
5.3.1
Gigabit Ethernet
An Intel 82571EB network controller provides two channels of 10/100/1000BaseT Ethernet through the VPX P1 connector. LINK
For more details on this device, see the web site
http://www.intel.com/design/network/products/lan/controllers/82571eb.htm.
A serial E²PROM (ST M95020) is connected to the Intel 82571EB to store data required by the Ethernet driver. This device is write‐protected by the VPX NVMRO signal or the NVMRO Link (E11), depending on whether the SBC320 is System Controller. 5.3.2
SATA
The SBC320 provides a single SATA 150 interface to the VPX P1 connector for connection to off‐board peripherals such as hard disk drives or CD/DVD drives. 5.3.3
Serial I/O
The standard 16550 UART interfaces of the Intel LE3100 are used to provide two RS232 debug ports (COM1 and COM2). The Intel LE3100 supports the standard six modem control functions (CTS, RTS, DSR, DTR, DCD and RI) with Baud rates up to 115200 Baud. The ports are connected to separate ISL41334 serial transceivers capable of generating RS232 or RS422/485 signal levels under software control. There are also software options to disable or loopback the transceivers for test purposes. See the CPLD Control Register 2 (offset 0x621) for more details. To give a usable range of serial options while keeping the VPX pin count low (8 pins), there are 4 basic serial I/O configurations (none of which support the RI modem signal): •
COM1 (TX, RX, DTR, DCD, RTS, CTS and DSR). See Figure 5‐2 •
COM1 and COM2 (TX, RX, RTS and CTS for both COM ports). See Figure 5‐3 •
COM2 Off (TX, RX, RTS and CTS for COM1 only, COM2 is routed to the BMM). See Figure 5‐4 •
BMM (TX, RX, RTS and CTS for COM1 only, COM2 is routed to the BMM and also output to VPX) See Figure 5‐5 Publication No. SBC320-0HH/2DF
Figure 5-2 COM1
Figure 5-3 COM1 and COM2
Figure 5-4 COM2 Off
Figure 5-5 BMM (RS232)
COM2 from the Intel LE3100 is connected to the Board Management Microcontroller (BMM). When the COM2 transceiver is enabled, the BMM serial port is disabled and vice‐versa. The enabling/disabling of the BMM serial port is controlled by bits 4 and 5 of the CPLD Control Register 2 (0x621). Normal operation of the BMM is internal (COM2 Off), meaning that BMM data is not transmitted out of the SBC320. However, to aid debug, the BMM mode reflects TX data from the LE3100 to the BMM out on the COM2 TX pin and RX data from the BMM to the LE3100 out on the COM2 RTS pin. There is no way to input data from the VPX backplane into the BMM. When the SBC320 detects that the Test Adapter card is fitted (i.e. when the ‘BOOT_DEBUG~’ signal on the Test connector is active), it automatically sets the COM buffer as enabled in COM2 mode. NOTE
The Test Adapter card is for Factory/Field Application Engineer use only.
Tables 5‐5 to 5‐8 show the serial pins from the LE3100 (SIU_XXX) and the VPX connections for the various output configurations: Table 5-5 RS232 Configuration Connections against VPX Connector Pins
VPX Pin
P1/G9
P1/G11
P1/G13
P1/G15
P2/G3
P2/G5
P2/G7
P2/G9
COM1
SIU_TX(1)
SIU_RX(1)
SIU_DTR(1)
SIU_DCD(1)
SIU_RTS(1)
SIU_CTS(1)
Unused
SIU_DSR(1)
COM1 & COM2
SIU_TX(1)
SIU_RX(1)
SIU_TX(2)
SIU_RX(2)
SIU_RTS(1)
SIU_CTS(1)
SIU_RTS(2)
SIU_CTS(2)
COM2 Off
SIU_TX(1)
SIU_RX(1)
Unused
Unused
SIU_RTS(1)
SIU_CTS(1)
Unused
Unused
BMM (TX Only)
SIU_TX(1)
SIU_RX(1)
SIU_TX(2) (BMM_RXD)
Unused
SIU_RTS(1)
SIU_CTS(1)
BMM_TXD
Unused
Table 5-6 RS232 Configuration Connections against LE3100 Serial I/O Signals
LE3100 Signal
SIU_TX(1)
SIU_RX(1)
SIU_RTS(1)
SIU_CTS(1)
SIU_DTR(1)
SIU_DSR(1)
SIU_DCD(1)
SIU_TX(2)
SIU_RX(2)
SIU_RTS(2)
SIU_CTS(2)
COM1
P1/G9
P1/G11
P2/G3
P2/G5
P1/G13
P2/G9
P1/G15
Unused
Unused
Unused
Unused
COM1 & COM2
P1/G9
P1/G11
P2/G3
P2/G5
Unused
Unused
Unused
P1/G13
P1/G15
P2/G7
P2/G9
COM2 Off
P1/G9
P1/G11
P2/G3
P2/G5
Unused
Unused
Unused
BMM_RXD
BMM_TXD
BMM_CTS2
BMM_RTS2
BMM (TX Only)
P1/G9
P1/G11
P2/G3
P2/G5
Unused
Unused
Unused
BMM_RXD & P1/G13
BMM_TXD & P2/G7
BMM_CTS2
BMM_RTS2
Table 5-7 RS422/485 Configuration Connections against VPX Connector Pins
VPX Pin
P1/G9
P1/G11
P1/G13
P1/G15
P2/G3
P2/G5
P2/G7
P2/G9
COM1
SIU_TX(1)~
SIU_RX(1)~
SIU_DTR(1)~†
SIU_DCD(1)~
SIU_TX(1)
SIU_RX(1)
SIU_DTR(1)†
SIU_DCD(1)
COM1 & COM2
SIU_TX(1)~
SIU_RX(1)~
SIU_TX(2)~
SIU_RX(2)~
SIU_TX(1)
SIU_RX(1)
SIU_TX(2)
SIU_RX(2)
COM2 Off
SIU_TX(1)~
SIU_RX(1)~
Unused
Unused
SIU_TX(1)
SIU_RX(1)
Unused
Unused
BMM (TX Only)
SIU_TX(1)~
SIU_RX(1)~
SIU_TX(2)~†
Unused
SIU_TX(1)
SIU_RX(1)
SIU_TX(2)†
Unused
Table 5-8 RS422/485 Configuration Connections against LE3100 Serial I/O Signals
LE3100 Signal
SIU_TX(1)
SIU_RX(1)
SIU_RTS(1)
SIU_CTS(1)
SIU_DTR(1)
SIU_DSR(1)
SIU_DCD(1)
COM1
P1/G9 & P2/G3
P1/G11 & P2/G5
SIU_TX(1)_OE
Unused
P1/G13 & P2/G7†
Unused
P1/G15 & P2/G9
COM1 & COM2
P1/G9 & P2/G3
P1/G11 & P2/G5
SIU_TX(1)_OE
Unused
Unused
Unused
Unused
COM2 Off
P1/G9 & P2/G3
P1/G11 & P2/G5
Unused
Unused
Unused
Unused
Unused
SIU_TX(2)
Unused
P1/G13 & P2/G7
BMM_RXD
SIU_RX(2)
SIU_RTS(2)
SIU_CTS(2)
Unused
Unused
Unused
P1/G15 & P2/G9
SIU_TX(2)_OE
Unused
BMM_TXD
BMM_CTS2
BMM_RTS2
BMM (TX Only)
P1/G9 & P2/G3
P1/G11 & P2/G5
Unused
Unused
Unused
Unused
Unused
BMM_RXD &
P1/G13 & P2/G7
BMM_TXD
BMM_CTS2
BMM_RTS2
† Outputs always enabled. NOTE
RS485 with full COM1 is not supported, as the DTR(1) output pins are always enabled.
5.3.4
GPIO
The SBC320 provides 6 lines of General Purpose I/O through the P1 connector. The lines are able to tolerate 5V input voltages and the signals are isolated whenever the SBC320 is powered down. The in‐board sides of the GPIO signals are pulled up to 3.3 Volts with 4.7 kΩ resistors. NOTE
The on-board logic of the SBC320 supports 8 bits of GPIO, however only 6 bits are routed to the VPX
connector.
Figure 5-6 GPIO Signal Isolation
3.3 Volt
4K7
On
board
Logic
(CPLD)
Isolator
VPX
connector
PWROK
The GPIO signals are sourced from the CPLD and any reset clears all output pins to inputs. To help prevent GPIO output pins glitching during board reset, the GPIO Out Register (offset 0x640) is only reset on power‐up. Always write this register before enabling GPIO output pins. NOTE
Although every effort has been made in the GPIO design to prevent glitches during power-up and
board reset, the outputs cannot be guaranteed to be glitch free during these events.
Under software control, the Port 80 LEDs can be switched to show the status of the GPIO pins (see the Activity LEDs section). Under software control, each GPIO signal can be used to generate an interrupt to the CPU on either level, either edge or both edges (see the GPIO Registers). All GPIO interrupts are connected to the LE3100 via the SERIRQ (Serial Interrupt Request) signal and appear to the Interrupt Handler as IRQ5. When using level interrupts, the LE3100 interrupt (IRQ5) also needs to be set to level sensitive. The GPIO interrupt using the SERIRQ signal means that the maximum update of the GPIO interrupt to the Interrupt Handler is around 2.25 μS. If the time that the ISR takes to write to the GPIO Interrupt Status Register (0x640) to clear the interrupt and return from the interrupt routine is very short (<2.25 μS), then it is possible to receive spurious GPIO interrupts. Publication No. SBC320-0HH/2DF
All GPIO inputs are double sampled at 33 MHz before being used by any internal logic of the CPLD. For valid operation, input states must be valid for longer than 33 nS; pulses shorter than this may be missed due to the sampling of the inputs at 33 MHz. If rise and fall times of the GPIO are slow (>10μS), then edge mode should not be used as any noise on the edges can cause false triggering. On really slow edges, software may need to filter the inputs. Table 5-9 GPIO Pin Electrical Characteristics at the VPX Connector
Input Sense
VIL
Min (V) Max (V)
-0.2
0.7
Output Drive
VIH
Min (V)
2.2
Max (V)
5
VOL Max
(V)
VOH Min
(V)
IOL
(mA)
IOH
(mA)
0.55
2.6
16
-14
BIT may use GPIO0 to select different operating modes. LINK
For more details on how to use this feature, see the VPXC3BIT on SBC320 Software Reference Manual,
publication number VPXT3BIT-SBC320-0HL.
5.3.5
USB 2.0
The Intel LE3100 provides four channels of high speed USB 2.0. Two of these ports are routed to the VPX P1 connector. One of the other ports is used for the USB Flash array. A National Semiconductor LM3526 provides power to the USB ports. This device provides power switching, over current protection, thermal protection and supply fault flag for each port independently. Output current threshold is limited to 1.2 A typical and 1 mS fault flag delay. LINK
For more details see http://www.national.com/mpf/LM/LM3526.html.
5.3.6
PCI Express
As shown in Figure 5‐7, the Intel LE3100 provides two PCIe ports: •
Port A is an 8 lane port, configured as 2 x 4 wide ports. One of these is connected to the Ethernet device and the other to a PCIe switch (PLX PEX8518) •
Port B is a 4 lane port that can be used as either a x4 wide port or as 4 x 1 ports and is connected directly to the P1 connector The PCIe switch also provides 4 lanes to the P1 connector, which can be configured as either a 1 x 4 port or 2 x2 ports. The PCIe switch also provides an x 4 wide port to the PCIe to PMC interface and supports non‐transparent bridging. It has a local serial E²PROM (Atmel AT252556A) to store configuration information. This E²PROM is write‐protected by the VPX NVMRO signal or the NVMRO Link (E11), depending on whether the SBC320 is System Controller. 34 SBC320 3U VPX Single Board Computer
Figure 5-7 PCI Express Connection
5.4 PMC
CAUTION
The SBC320 does not support 5 Volt-only PMCs. Fitting a 5 Volt PMC may cause damage to the board
and/or the PMC.
As shown in Figure 5‐7, a PCIe four lane port is routed to a PCIe to PCI bridge (PLX PEX8114). The PEX8114 has a local serial E²PROM (Atmel AT252556A) to store configuration information. This E²PROM is write‐protected by the VPX NVMRO signal or the NVMRO Link (E11), depending on whether the SBC320 is System Controller. The PEX8114 provides a 64‐bit PCI bus that is 133 MHz PCI‐X capable. The PEX8114 device is not 5 Volt tolerant, so there is no support for any 5 Volt‐only PMCs on the SBC320. The bridge provides all bus arbitration, clocking and interrupt handling, and is configured in forward mode (PCIe is the primary with the PCI bus being the secondary). The PMC site can support 32‐ or 64‐bit PMCs and 33/66/133 MHz PCI bus speeds. All 64 user I/O lines from the PMC J14 connector are tracked directly to the rear VPX P2 connector using 50Ω impedance tracking. All tracking is single ended, with no allowance for any differential signals from the PMC. All tracks are matched in length (better than ±50 thousandths of an inch) between the J14 connector and where the VPX connector is soldered onto the PWB, so if matched track lengths are required, then the different VPX connector pin/trace lengths need to be taken into account. The SBC320 power supply controller controls all power to the PMC except the ±12 Volt supplies (supplied direct from VPX), so when the SBC320 is shut down, power to the PMC is removed (apart from the ±12 Volt supplies). Publication No. SBC320-0HH/2DF
5.5 Real Time Clock
The RTC is part of the Intel LE3100 device and is powered from the P3V3_AUX rail over the backplane or by the VPX VBAT supply. As long one of these is present, the system clock is maintained; if all power is removed, the RTC function is reset. The RTC module comprises a clock that has resolutions down to seconds, two banks of static RAM (see the Static RAM section) and the following interrupt features: •
Time of day alarm with once a second to once a month range •
Periodic rate 122 μS to 500 mS •
End of update The RTC section uses the first 14 bytes of the lower static RAM block, with the first 10 bytes being used for time and date information and the last 4 bytes being used to configure and report the RTC function. The leap year determination for adding a 29th day to February does not take into account the end‐of‐the‐century exceptions. 5.6 I2C Bus
As shown in Figure 5‐8, there are two I2C buses. This allows the SBC320 to be powered down but an external I2C master to access the board temperature, PSU status and the BMM. Figure 5-8 I2C Bus Devices (7-bit Addressing)
Table 5-10 I2C Device Address Map
Device
LE3100 (IICH – Master/Slave)
Temperature Sensor
PSU Monitor
LE3100 (IMCH – Slave only)
E²PROM (SDRAM)
E²PROM (BIOS)
PEX8518 (default)
CK409 (ICS952601)
ETI
DB800 (ICS9DB108)
7-Bit Address
0x44 (default)
0x4C
0x4E
0x30
0x53
0x56
0x70
0x69
0x6B
0x6E
8-Bit Address
0x88 (default)
0x98
0x9C
0x60
0xA6
0xAC
0xE0
0xD2
0xD6
0xDC
Bus
2
2
2
1
1
1
1
1
1
1
The above 8‐bit addresses are the value that would be used to write to the device on the bus (i.e. the 7‐bit device address and the LSB set to ‘0’). NOTE
The PEX8518 responds to a valid I²C address cycle from the LE3100 by driving an ACK, but it is not
possible to generate data transfers, as the PEX8518 requires a defined cycle type that the LE3100
cannot generate.
5.6.1
Temperature Sensor
The SBC320 provides an ADT7481 temperature sensor capable of monitoring the core temperatures of the L7400 CPU and the LE3100 Bridge and also monitoring the ambient temperature. LINK
For more details on this device, see http://www.onsemi.com/PowerSolutions/product.do?id=ADT7481.
The ADT7481 can generate interrupts to the CPU, via the CPLD IRQ Enable Register (offset 0x623) and the Alarm Status Register (offset 0x606). The BIOS routes the ADT7481 outputs as follows: •
ALERT/THERM2 (Thermal Alarm) to the LE3100 GPI5 input so that it can trigger Operating System shutdown when any temperature goes out of (user defined) bounds •
THERM (Temperature Alarm) to the LE3100 THRM~ input for automated throttling (degrade performance by 75% through STPCLK throttling) Figure 5-9 Temperature Interrupts
5.6.2
PSU Monitor
The SBC320 uses an ispPAC‐POWR1014/A programmable power supply supervisor. LINK
More details on this device can be found at
http://www.latticesemi.com/products/powermanager/powermanageriipowr1014a.cfm.
This device can be accessed from the I²C, which allows all of the on‐board and off‐
board supplied voltage rails to be monitored and read back. The voltages are returned as 12‐bit values, which need to be multiplied by 2mV to give the real value. The device allows for up to ten power supplies to be monitored, as shown in Table 5‐11: Table 5-11 PSU Rail Monitoring
Monitor
1
2
3
4
5
6
7
8
9
10
Voltage
0.7 -> 1.3
1
1.05
1.1
1.5
1.8
2.5
3.3
3.3
5
SBC320 Function Using Supply
CPU core supply
PEX8114 and PEX8518
FSB, AGTL
Dual Ethernet
CPU PLL, LE3100 Core, PEX8114 and PEX8518
SDRAM, Dual Ethernet
LE3100
Main 3.3 Volt input from VPX
Auxiliary 3.3 Volt input from VPX
5 Volt input from VPX
NOTE
The SBC320 does not use the ±12 Volt supplies, so these are not monitored.
5.6.3
Elapsed Time Indicator
The SBC320 provides a Dallas DS1682 Elapsed Time Indicator (ETI) to log the amount of time for which the board has been powered and the number of power cycles. The SBC320 does not implement the Alarm output from the DS1682. LINK
For more details on this device, see http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2756.
5.6.4
Clocks
As shown in Figure 5‐10, all on‐board clocks are derived from a single 14.31818 MHz clock source. This clock is then fed into an ICS952601 (referred to as “CK409”) to produce the FSB, 33 MHz and USB frequencies. A feed from CK409 is fed into an ICS9DB108 (referred to as “DB800”) to produce the differential PCIe and SATA clocks. The Intel LE3100 produces the DDR2 clocks, which are fed to each SDRAM bank and buffered using a PI6CU877 PLL Clock driver before being fed on to the SDRAM devices. The VPX and PMC PCI clocks are produced by the PCIe to PCI (PEX8114) device. The drive parameters of these clock devices can be changed via the I2C bus, but see the caution below. Publication No. SBC320-0HH/2DF
CAUTION
Changing these values without consulting the factory may result in unpredictable behavior of the
SBC320.
Table 5-12 Clock Summary
Device or Function
CPU
ITP
LE3100 (IMCH)
DDR
LE3100 (IMCH)
LE3100 (USB)
LE3100 (SATA)
LE3100 (SIU)
LE3100 (LPC)
FWHs
CPLD
PCIe
PCIe
PMC
Clock Speed (MHz)
133/166
133/166
133/166
200
14.31818
48
100
48
33
33
33
100
100
33/66/100/133
Clock Source
CK409
CK409
CK409
LE3100
CK409
CK409
DB800
CK409
CK409
CK409
CK409
DB800
DB800
PEX8114
Figure 5-10 SBC320 Basic Clock Structure
5.6.5
Board Management Microcontroller
The SBC320 contains a Board Management Microcontroller (BMM) as defined by the GE Intelligent Platforms document “Requirements Specification for a Board Management Microcontroller” to enable sharing of BIT results and remote monitoring of board health. The BMM is connected to the following interfaces: •
COM2 (to Intel LE3100 DUART) •
On‐board I2C Bus 1 (for access to on‐board devices) •
VPX geographic address •
Backplane System Management bus The BMM is powered from the VPX P3V3_AUX supply. This enables communication with the BMM when the main VPX supplies are switched off or the SBC320 has been shut down. 5.7 CPLD
The CPLD is a Lattice LCMXO1200C device that provides the on‐board registers (see the Control and Status Registers section) and sources the GPIO signals (see the GPIO section). The CPLD also control write protection (see the Write Protection section). Publication No. SBC320-0HH/2DF
5.8 LEDs
Figure 5‐11 shows the LEDs mounted on the rear of the SBC320: Figure 5-11 Rear LED Positions
5.8.1
BIT LEDs (DS200 to DS203)
The SBC320 has four software‐controlled LEDs (1 red, 2 yellow and 1 green) to reflect the status of BIT or other boot software. When used by BIT, these LEDs have the meanings shown in Table 5‐13: Table 5-13 BIT LED Meanings
LED
DS201
DS203
DS200 & DS202
Color
Red
Green
Yellow
Meaning
BIT Fail
BIT Pass
BIT status (see BIT documentation)
Status After Reset
Lit
Unlit
Unlit
LINK
For more details on BIT, see the VPXT3BIT on SBC320 Software Reference Manual, publication number
VPXT3BIT-SBC320-0HL.
The red BIT LED is normally driven by the BMM under software control. It is powered from the auxiliary power supply, so it can then be lit even when the main power supplies are not active or have failed. When the red BIT LED is lit, the BIT_FAIL~ (P2 G1) backplane signal is driven active low using an open‐drain driver. The two yellow and one green BIT LEDs are driven by the CPLD Control Register 3 under software control. 42 SBC320 3U VPX Single Board Computer
5.8.2
Power LEDs (DS205 and DS206)
The Power Manager drives DS205 (green) and DS206 (red). These indicate various power states of the SBC320 as shown in Table 5‐14: Table 5-14 Power LED Meanings
DS206
Off
Off
On
On
DS205
Off
On
Off
On
5.8.3
Meaning
No power to board
Board powered up and all PSUs are in specification
PSU unit failed
Board PSU is inhibited
Activity LEDs
Board Reset The red LED DS204 lights up when the SBC320 is in reset. USB Flash The green LED DS207 shows access to the USB Flash drive. Ethernet The two yellow LEDs DS208 and DS209 show the state of the two Ethernet channels (DS209 for Ethernet 0 and DS208 for Ethernet 1). The LEDs light up when a valid link is detected and flash as data is received. SATA The green LED DS210 shows access to SATA. PORT 80 The SBC320 latches writes to the I/O address 0x80. The BIOS uses this I/O port to output status information to aid debug of software and hardware configuration. By default, this data (lower byte) is shown on the SBC320 PORT 80 yellow LEDs. LINK
The BIOS POST codes are detailed in
http://www.ami.com/support/downloaddoc.cfm?DLFile=support/doc/
AMIBIOS8_Checkpoint_and_Beep_Code_List_PUB.pdf&FileID=928.
When the value 0x00 is written to I/O port 80 on the SBC320, all LEDs are extinguished. Using the CPLD Control Register 3, these 8 LEDs can also be switched to show the status of the 8 GPIO pins3 or the Ethernet Status. Table 5-15 Activity LED Meanings
Mode
LEDs
DS211
DS118
DS216
DS215
DS214
DS213
DS212
DS217
PORT80
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
100 Mbit
Receive
GPIO
Ethernet
3
Ethernet Channel 1
Link
1000 Mbit
Ethernet Channel 0
100 Mbit
Receive
Link
1000 Mbit
The on-board logic of the SBC320™ supports 8 bits of GPIO, however only 6 bits are routed to the VPX connector.
5.9 Write Protection
Logic built into the CPLD controls write protection of the SBC320. Table 5‐16 shows the basic write protection operation. Table 5-16 Write Protection
Device
FLASH_WE_INTERNAL
NVRAM_WE_INTERNAL (general non
volatile RAM write enable signal)
Flash Hard Drive
BANC Boot FWH
Main Boot FWH
Parallel NVRAM
SDRAM E2PROM (I²C bus address 0xA6)
PEX8114 E2PROM
PEX8518 E2PROM
BIOS E2PROM (I²C bus address 0xAE)
Ethernet E2PROM
BMM programming
RTC and SRAM
Circumstances for Device to be Writeable
This internal signal goes valid (write/read) if the SBC320 is a VPX
Master or the VPX NVMRO signal indicates that Writes are
enabled
This internal signal goes valid (write/read) if:
•
The SBC320 is a VPX Master and the NVMRO Link (E11) is
not fitted
•
The SBC320 is a VPX Slave and the NVMRO Link (E11) is not
fitted and the VPX NVMRO signal is low
•
The Test Adapter card is fitted
When the Flash Hard Drive Write Disable Link (E2) is not fitted
and FLASH_WE_INTERNAL is valid, or the Test Adapter card is
fitted
When Software unlock is completed and FLASH_WE_INTERNAL
is valid, or the Test Adapter card is fitted
When the Main Boot Flash Write Disable Link (E1) is not fitted
and FLASH_WE_INTERNAL is valid, or the Test Adapter card is
fitted
NVRAM_WE_INTERNAL is valid
This is write protected unless the Test Adapter card is fitted
Always writeable (internal to LE3100)
NOTE
When fitted, the Test Adapter card overrides the link settings and VPX NVMRO signal. It is for
Factory/Field Application Engineer use only.
5.10 JTAG
There are five JTAG chains on the SBC320, four of which can only be accessed via the test connector and so cannot be used in a deployed system. The chain that is routed to the VPX P0 connector consists of four devices in the following order: •
Ethernet Controller (Intel 82571) •
PCIe Switch (PEX8518) •
PCIe to PCI‐X Bridge (PEX8114) •
PMC (this is automatically bypassed when there is no PMC fitted) The signaling level used on the chain is 3.3 Volts and is not 5 Volt tolerant. The four chains routed to the test connector are as shown in Table 5‐17: Table 5-17 Test Connector JTAG Chains
Function
CPLD
PSU Controller
Bridge
CPU
Device
LCMXO1200C
ispPAC-POWR1014A
Intel LE3100
Intel L7400
JTAG Interface Voltage
3.3
3.3†
1.5
1.05
† Powered from P3V3_AUX Publication No. SBC320-0HH/2DF
5.11 Control and Status Registers
These registers are provided by the CPLD and appear in the I/O memory map (for reading and writing) starting at address 0x600. They can also be read back in memory space under ID7 + address 0x04000000. Table 5-18 Control/Status Registers
ISA I/O Port (Hex)
600
601
602
603
604
605
606
607
610 to 615
620
621
622
623
624
640
641
642
643
644
645
646
647
Description
Board ID
Board Revision
Board Configuration 1
VPX Geographical address
Alarm status
Link Settings
Board ID String
Control 1
Control 2
Control 3
IRQ Enable
Drive Links Low
GPIO Out
GPIO In
GPIO Direction
GPIO Interrupt Enable
GPIO Level/Edge
GPIO Active Low/High
GPIO Both Edges
GPIO Interrupt Status
Access
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write to clear IRQ
The control and status registers exist for controlling or reading the status of the hardware. The addresses are as seen by the processor. In the following register descriptions, the bit significance is shown in little‐endian mode (i.e. from the viewpoint of the processor). MSB = D7, LSB = D0 5.11.1
Board ID Register (0x600)
This reads back 0x3E. 46 SBC320 3U VPX Single Board Computer
5.11.2
Board Revision Register (0x601)
This provides information on the build state of the SBC320. Bits
D7 to D5
D4 to D0
5.11.3
Meaning
Number revision (artwork level) of the hardware build state:
1 = Revision 1
2 = Revision 2
3 = Revision 3
4 = Revision 4
Letter revision of the hardware build state:
0x0 = Revision A
0x1 = Revision B
...
0x18 = Revision Y
0x19 = Revision YA
...
0x1F = Revision YG
Board Configuration Register 1 (0x602)
This provides information on hardware options. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
Reserved. Reads ‘0’
E13 Link
1 = Jumper fitted
0 = No jumper fitted
E12 Link
1 = Jumper fitted
0 = No jumper fitted
Auto Boot Swap
1 = FWHs swapped by hardware
0 = Firmware selected normally
Boot
1 = Boot from Test Adapter card FWH
0 = Boot from on-board FWHs
BANC Boot (shows setting of E14)
1 = Boot from BANC FWH
0 = Boot from Main FWH
PMC fitted
1 = A PMC card is fitted
0 = No PMC card is fitted
Two SDRAM banks
1 = Two SDRAM banks fitted
0 = One SDRAM bank fitted
NOTES
1.
2.
Bit D2 only shows the link setting of the BANC Boot Image Select Link (E14). It should be used in
conjunction with bit D4 when determining the cause for a boot mode swap. See the Boot Flash
section for more details.
The Test Adapter card is for Factory/Field Application Engineer use only.
5.11.4
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
PMC EREADY
1 = Not ready
0 = Ready
SDRAM E2PROM write protection
1 = Write protected
0 = Writes enabled
SDRAM E2PROM address swap
1 = Address is swapped
0 = Normal operation
Clocks valid (only for factory use)
1 = PSU clocks are running and CPU clock enabled
0 = Problems with clocks
DBA~ (unused signal that comes from the Test connector)
1 = Not active
0 = Active
VPX NVMRO pin (shows status of VPX connector pin P0 A4)
1 = Non-volatile Memory is read-only
0 = Non-volatile Memory is read/write
VPX System Controller
1 = SBC320 is System Controller
0 = SBC320 is not System Controller
5.11.5
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
ISP DATA (read)
1 = Signal high
0 = Signal low
Test Adapter carda Write Protect Override
1 = Board Write Protect overridden
0 = Normal board write protection
BANC Boot Flash Write Protect
1 = Write-protected
0 = Writes enabled
BANC Boot Flash Write Enable by Software Lock
1 = Write-protected
0 = Writes enabled
Flash Hard Drive fitted
1 = Flash Hard Drive is fitted
0 = Flash Hard Drive is not fitted
NVRAM Write Protect
1 = Write-protected
0 = Writes enabled
Flash Hard Drive Write Protect
1 = Write-protected
0 = Writes enabled
Main Boot Flash Write Protect
1 = Write-protected
0 = Writes enabled
a. The Test Adapter card is for Factory/Field Application Engineer use only.
5.11.6
VPX Geographical Address Register (0x605)
This returns the VPX Geographical address status. Bits
D7 and D6
D5
D4
D3
D2
D1
D0
Meaning
Reserved. Read ‘0’
Reads back the status of the VPX GAP~ pin
Reads back the status of the VPX GA4~ pin
All bits read logic ‘0’ for a grounded pin and logic ‘1’ for open circuit pin (pulled up with 4.7 kΩ resistors on the SBC320). Table 5-19 Geographic Addressing
GAP
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
GA4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
GA3
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
GA2
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
GA1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
GA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Hex
3E
3D
1C
3B
1A
19
38
37
16
15
34
13
32
31
10
2F
0E
0D
2C
0B
2A
Slot Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
5.11.7
Alarm Status Register (0x606)
This provides status information about the Alarms that are driven into the LE3100 on either the GPI5 (PIRQH~) interrupt pin or the THRM~ pin. These status signals show the state of the Alarm source and do not include the mask for the enabling register (the IRQ Enable Register at offset 0x623). NOTE
The LE3100 can also use GPI5 as PIRQH~. The BIOS sets and uses the PIRQH~ input as GPI5.
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
PEX8518 Fatal Error, GPI5 input
1 = Fatal error
0 = No error
CPU to Hot (direct from CPU), GPI5 input
1 = Alarm
0 = No alarm
Temperature Alarm (ADT7481 THERM output), GPI5 input
1 = Alarm
0 = No alarm
Thermal Alarm (ADT7481 ALERT/THERM2 output), GPI5 input
1 = Alarm
0 = No alarm
CPU to Hot (direct from CPU), THRM~ input
1 = Alarm
0 = No alarm
Temperature Alarm (ADT7481 THERM output), THRM~ input
1 = Alarm
0 = No alarm
Thermal Alarm (ADT7481 ALERT/THERM2 output), THRM~ input
1 = Alarm
0 = No alarm
5.11.8
Link Settings Register (0x607)
This reads back all link settings. Bits
D7 and D6
D5
D4
D3
D2
D1
D0
Meaning
Reserved. Read ‘0’
NVMRO Link (E11)
1 = Jumper not fitted
0 = Jumper fitted
BANC Boot Image Select Link (E14)
0 = Jumper fitted
Main Boot Flash Write Disable Link (E1)
0 = Jumper fitted
Flash Hard Drive Write Disable Link (E2)
0 = Jumper fitted
E13 Link
0 = Jumper fitted
E12 Link
0 = Jumper fitted
See also the Drive Links Low Register (0x624). LINK
For more details on the use of E12 and E13, see the VPXT3BIT on SBC320 Software Reference Manual,
publication number VPXT3BIT-SBC320-0HL.
5.11.9
Board ID String Registers (0x610 to 0x615)
These read back “SBC320”. 5.11.10 Control Register 1 (0x620)
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
Sticky BIT (used by BIOS to know when the board has been power cycled)
This bit is cleared to logic ‘0’ by a power cycle
Sticky BIT (used by BIT to know when the board has been power cycled)
This bit is cleared to logic ‘0’ by a power cycle
Watchdog WDT_TOUT Reset enable
1 = Enabled
0 = Disabled (default)
ISP Data buffer enable
1 = Enabled
BMM_PS0_ISP_VPP
Used to program the BMM, consult the factory for use
BMM_PS1_ISP_CLK
BMM_PROGRAM_EN
ISP Data out
5.11.11 Control Register 2 (0x621)
This controls the USB power and the COM ports. Bits
D7
D6
D5 and D4
D3
D2
D1
D0
Meaning
USB Power enable 1
1 = Power on
0 = Power off (Default)
USB Power enable 2
1 = Power on
0 = Power off (Default)
COM mode, as follows:
D5
D4
COM Mode
0
0
COM2
0
1
COM2 OFF
1
0
BMM
1
1
COM1
COM2 RS422 select
1 = RS422 mode
0 = RS232 (default)
COM1 RS422 select
1 = RS422 mode
0 = RS232 (default)
COM buffer loopback
1 = Loopback enabled
0 = Loopback off (default)
COM buffer enable
1 = COM buffer enabled
0 = COM buffer disabled (default)
5.11.12 Control Register 3 (0x622)
This controls the LEDs. Bits
D7
D6
D5
D4
D3 and D2
D1 and D0
Meaning
BIT Pass
1 = LED lit
0 = LED off (default)
BIT Fail
1 = LED lit (default)
0 = LED off
BIT Status 1
1 = LED lit
BIT Status 0
1 = LED lit
LED Flash mode
D3
D2
Operation
0
0
Normal BIT LED operation (default)
0
1
Flash alternate BIT Pass & BIT Status 1 (Fast)
1
0
Smooth Flash alternate BIT Pass & BIT Status 1 (Slow)
1
1
Flash pattern on BIT Pass, BIT Status 1 & BIT Status 0
PORT 80 LED display control, as follows:
D1
D0
Display
0
0
PORT 80 status (default)
0
1
GPIO status
1
X
Ethernet status
5.11.13 IRQ Enable Register (0x623)
This enables the alarms to the LE3100. NOTES
Bit
D7
D6
D5
D4
D3
D2
D1
D0
1.
The LE3100 can also use GPI5 as PIRQH~. The BIOS sets and uses the PIRQH~ input as GPI5.
2.
All of the GPI5 enables are set so that they enable a 90nS pulse on the GPI5 pin when a low going
edge is detected on the appropriate input.
Meaning
PEX8518 Fatal Error to IOCHCK
1 = Enabled
0 = Masked
CPU to Hot (direct from CPU) to GPI5 input
1 = Enabled
0 = Masked
Temperature Alarm (ADT7481 THERM output) to GPI5 input
1 = Enabled
0 = Masked
Thermal Alarm (ADT7481 ALERT/THERM2 output) to GPI5 input
1 = Enabled
0 = Masked
PEX8518 Fatal Error to GPI5 input
1 = Enabled
0 = Masked
CPU to Hot (direct from CPU) to THRM~ input
1 = Enabled
0 = Masked
Temperature Alarm (ADT7481 THERM output) to THRM~ input
1 = Enabled
0 = Masked
Thermal Alarm (ADT7481 ALERT/THERM2 output) to THRM~ input
1 = Enabled
0 = Masked
5.11.14 Drive Links Low Register (0x624)
E7 is a ‘virtual’ link comprising pin 2 of E12 and pin 2 of E13 (see Figure 3‐2). To allow software to determine whether E7 is linked, this register allows E12 or E13 to be driven low. When (pin 2 of) one of these links is driven low, if the pin 2 of the other link also goes low, then E7 is linked. Bits
D7
D6
D5 to D2
D1
D0
Meaning
Drive NVMRO Link (E11) low
1 = Drive link low
0 = Not driven (default)
Drive VPX SYSRESET~ low when System Controllera
1 = Drive SYSRESET~ low
Not used
Drive E12 link low
1 = Drive link low
Drive E13 link low
1 = Drive link low
a This does not reset the SBC320, and is not driven out when the SBC320 is a system slave.
5.11.15 GPIO Out Register (0x640)
This holds the GPIO out data. Although the CPLD supports 8 bits of GPIO, only 6 bits of GPIO are currently routed to the VPX P1 connector. Bit
D7
D6
D5
D4
D3
D2
D1
D0
GPIO Pin
GPIO7 (not connected)
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
NOTE
This register is only cleared on a power cycle.
5.11.16 GPIO In Register (0x641)
This reflects the current state of the GPIO pins regardless of whether they are configured as inputs or outputs. Although the CPLD supports 8 bits of GPIO, only 6 bits of GPIO are currently routed to the VPX P1 connector. Bit
D7
D6
D5
D4
D3
D2
D1
D0
GPIO Pin
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
5.11.17 GPIO Direction Register (0x642)
This defines which GPIO pins are used as outputs and which are inputs. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 direction
1 = Output
0 = Input (default)
GPIO6 direction
1 = Output
0 = Input (default)
GPIO5 direction
1 = Output
0 = Input (default)
GPIO4 direction
1 = Output
0 = Input (default)
GPIO3 direction
1 = Output
0 = Input (default)
GPIO2 direction
1 = Output
0 = Input (default)
GPIO1 direction
1 = Output
0 = Input (default)
GPIO0 direction
1 = Output
0 = Input (default)
5.11.18 GPIO Interrupt Enable Register (0x643)
This defines which GPIO cells can generate interrupts. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 interrupt enable
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
5.11.19 GPIO Level/Edge Register (0x644)
This defines whether GPIO interrupts are edge or level sensitive. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 interrupt sensitivity
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
1 = Edge
0 = Level (default)
5.11.20 GPIO Active Low/High Register (0x645)
This defines the level or edge to which the GPIO interrupts are sensitive. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 interrupt high or low
1 = Active high or going-high edge
0 = Active low or going-low edge (default)
5.11.21 GPIO Both Edges Register (0x646)
This allows the GPIO interrupts to be sensitive to both edges when in edge mode. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 both edges
1 = Both edges
0 = Off (default)
GPIO6 both edges
1 = Both edges
0 = Off (default)
GPIO5 both edges
1 = Both edges
0 = Off (default)
GPIO4 both edges
1 = Both edges
0 = Off (default)
GPIO3 both edges
1 = Both edges
0 = Off (default)
GPIO2 both edges
1 = Both edges
0 = Off (default)
GPIO1 both edges
1 = Both edges
0 = Off (default)
GPIO0 both edges
1 = Both edges
0 = Off (default)
5.11.22 GPIO Interrupt Status Register (0x647)
This indicates which GPIO is causing an interrupt. Writing a logic ‘1’ to a Bit in this register will clear that pending interrupt. Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
GPIO7 interrupt status
1 = Interrupt is active
0 = No interrupt
0 = No interrupt
0 = No interrupt
0 = No interrupt
0 = No interrupt
0 = No interrupt
0 = No interrupt
0 = No interrupt
5.11.23 BIT Address/Data Read Back Registers (Firmware ID7 +
0x42000)
These are for BIT to test out the LPC/CPLD interface connection and only exist for Firmware read cycles. When read, they return address bits 16 down to 1. 5.12 Front Panel
Only build levels 1 to 3 are fitted with a front panel. This has an injector/ejector handle and a removable bezel covering the PMC aperture. Figure 5-12 Front Panel
6 • Connectors
Table 6‐1 shows the function of the connectors on the SBC320. Table 6-1 Connector Functions
Connector
P0, P1, P2
J11, J12
J13
J14
TEST1
Function
VPX interface
32-bit PCI interface
64-bit PCI interface extension
PMC rear I/O
Test interface
Figure 6-1 Front Connector Positions and Numbering
NOTE
The SBC320’s guide pin receptacles are unkeyed by default, but may be keyed to customer
requirements. Contact the factory for more details.
Figure 6-2 Rear Connector Position and Numbering
Connectors 61
6.1 VPX Connector Pinouts
6.1.1
P0
Table 6-2 P0 Connector Pin Assignments
1
2
3
4
5
6
7
8
A
P3V3
P3V3
VCC
NVRMO
SM1
GA0~
TRST~
GND
6.1.2
B
P3V3
P3V3
VCC
SYSRESET~
SM0
GA1~
TMS
Unused
C
P3V3
P3V3
VCC
GND
GND
GND
GND
Unused
D
None
None
None
N12V_AUX
P3V3_AUX
P12V_AUX
TDI
GND
E
Unused
Unused
VCC
GND
GND
GND
TDO
Unused
F
Unused
Unused
VCC
Unused
GA4~
GA2~
GND
Unused
G
Unused
Unused
VCC
Unused
GAP~
GA3~
TCLK
GND
J0 (Backplane)
Table 6-3 J0 Connector Pin Assignments
1
2
3
4
5
6
7
8
A
P3V3
P3V3
VCC
GND
GND
GND
TRST~
GND
B
P3V3
P3V3
VCC
NVMRO
SM1
GA0~
TMS
GND
C
P3V3
P3V3
VCC
SYSRESET~
SM0
GA1~
GND
Unused
D
P3V3
P3V3
VCC
GND
GND
GND
GND
Unused
E
None
None
None
N12V_AUX
P3V3_AUX
P12V_AUX
TDI
GND
F
Unused
Unused
VCC
GND
GND
GND
TDO
GND
G
Unused
Unused
VCC
Unused
GA4~
GA2~
GND
Unused
H
Unused
Unused
VCC
Unused
GAP~
GA3~
GND
Unused
I
Unused
Unused
VCC
GND
GND
GND
TCK
GND
6.1.3
P1
A
B
C
D
E
F
G
1
PCIE_RXP0
PCIE_RXN0
GND
PCIE_TXP0
PCIE_TXN0
GND
Unused
2
GND
PCIE_RXP1
PCIE_RXN1
GND
PCIE_TXP1
PCIE_TXN1
GND
3
PCIE_RXP2
PCIE_RXN2
GND
PCIE_TXP2
PCIE_TXN2
GND
VBAT
4
GND
PCIE_RXP3
PCIE_RXN3
GND
PCIE_TXP3
PCIE_TXN3
GND
5
PEG_RXP0
PEG_RXN0
GND
PEG_TXP0
PEG_TXN0
GND
SYS_CON~
6
GND
PEG_RXP1
PEG_RXN1
GND
PEG_TXP1
PEG_TXN1
GND
7
PEG_RXP2
PEG_RXN2
GND
PEG_TXP2
PEG_TXN2
GND
Unused
8
GND
PEG_RXP3
PEG_RXN3
GND
PEG_TXP3
PEG_TXN3
GND
9
SATA0_RXP
SATA0_RXN
GND
SATA0_TXP
SATA0_TXN
GND
COM1_TXD
10
GND
USB_P0P
USB_P0N
GND
USB_P1P
USB_P1N
GND
11
P5V_USBP0
P5V_USBP1
GND
GPIO0
GPIO1
GND
COM1_RXD
12
GND
GPIO2
GPIO3
GND
GPIO4
GPIO5
GND
13
ETH_B_0P
ETH_B_0N
GND
ETH_B_1P
COM2_TXD
GND
GND
ETH_A_1P
GND
GND
ETH_A_0P
GND
ETH_B_2N
GND
ETH_A_2N
ETH_B_3N
15
16
ETH_B_2P
ETH_A_0N
ETH_A_2P
ETH_B_1N
ETH_B_3P
GND
14
ETH_A_1N
ETH_A_3P
GND
ETH_A_3N
COM2_RXD
GND
6.1.4
J1 (Backplane)
Positions 1, 3, 5 and 7 on fin I are specified by the VITA 46 specification. Table 6-5 J1 Connector Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PCIE_RXP0
GND
PCIE_RXP2
GND
PEG_RXP0
GND
PEG_RXP2
GND
SATA0_RXP
GND
P5V_USBP0
GND
ETH_B_0P
GND
ETH_A_0P
GND
B
PCIE_RXN0
GND
PCIE_RXN2
GND
PEG_RXN0
GND
PEG_RXN2
GND
SATA0_RXN
GND
P5V_USBP1
GND
ETH_B_0N
GND
ETH_A_0N
GND
C
GND
PCIE_RXP1
GND
PCIE_RXP3
GND
PEG_RXP1
GND
PEG_RXP3
GND
USB_P0P
GND
GPIO2
GND
ETH_B_2P
GND
ETH_A_2P
D
GND
PCIE_RXN1
GND
PCIE_RXN3
GND
PEG_RXN1
GND
PEG_RXN3
GND
USB_P0N
GND
GPIO3
GND
ETH_B_2N
GND
ETH_A_2N
E
PCIE_TXP0
GND
PCIE_TXP2
GND
PEG_TXP0
GND
PEG_TXP2
GND
SATA0_TXP
GND
GPIO0
GND
ETH_B_1P
GND
ETH_A_1P
GND
F
PCIE_TXN0
GND
PCIE_TXN2
GND
PEG_TXN0
GND
PEG_TXN2
GND
SATA0_TXN
GND
GPIO1
GND
ETH_B_1N
GND
ETH_A_1N
GND
G
GND
PCIE_TXP1
GND
PCIE_TXP3
GND
PEG_TXP1
GND
PEG_TXP3
GND
USB_P1P
GND
GPIO4
GND
ETH_B_3P
GND
ETH_A_3P
H
GND
PCIE_TXN1
GND
PCIE_TXN3
GND
PEG_TXN1
GND
PEG_TXN3
GND
USB_P1N
GND
GPIO5
GND
ETH_B_3N
GND
ETH_A_3N
I
Unused
GND
VBAT
GND
Unused
GND
Unused
GND
COM1_TXD
GND
COM1_RXD
GND
COM2_TXD
GND
COM2_RXD
GND
NOTE
COM port pins are shown for COM2 operation; see the Serial I/O section for alternate serial
configurations.
Connectors 63
6.1.5
P2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PMC_IO4
GND
PMC_IO12
GND
PMC_IO20
GND
PMC_IO28
GND
PMC_IO36
GND
PMC_IO44
GND
PMC_IO52
GND
PMC_IO60
GND
6.1.6
B
PMC_IO2
PMC_IO8
PMC_IO10
PMC_IO16
PMC_IO18
PMC_IO24
PMC_IO26
PMC_IO32
PMC_IO34
PMC_IO40
PMC_IO42
PMC_IO48
PMC_IO50
PMC_IO56
PMC_IO58
PMC_IO64
C
GND
PMC_IO6
GND
PMC_IO14
GND
PMC_IO22
GND
PMC_IO30
GND
PMC_IO38
GND
PMC_IO46
GND
PMC_IO54
GND
PMC_IO62
D
PMC_IO3
GND
PMC_IO11
GND
PMC_IO19
GND
PMC_IO27
GND
PMC_IO35
GND
PMC_IO43
GND
PMC_IO51
GND
PMC_IO59
GND
E
PMC_IO1
PMC_IO7
PMC_IO9
PMC_IO15
PMC_IO17
PMC_IO23
PMC_IO25
PMC_IO31
PMC_IO33
PMC_IO39
PMC_IO41
PMC_IO47
PMC_IO49
PMC_IO55
PMC_IO57
PMC_IO63
F
GND
PMC_IO5
GND
PMC_IO13
GND
PMC_IO21
GND
PMC_IO29
GND
PMC_IO37
GND
PMC_IO45
GND
PMC_IO53
GND
PMC_IO61
G
BIT_FAIL~
GND
COM1_RTS
GND
COM1_CTS
GND
COM2_RTS
GND
COM2_CTS
GND
Unused
GND
SEQ_IN
GND
SEQ_OUT
GND
J2 (Backplane)
Table 6-7 J2 Connector Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
PMC_IO4
GND
PMC_IO12
GND
PMC_IO20
GND
PMC_IO28
GND
PMC_IO36
GND
PMC_IO44
GND
PMC_IO52
GND
PMC_IO60
GND
B
PMC_IO2
GND
PMC_IO10
GND
PMC_IO18
GND
PMC_IO26
GND
PMC_IO34
GND
PMC_IO42
GND
PMC_IO50
GND
PMC_IO58
GND
C
GND
PMC_IO8
GND
PMC_IO16
GND
PMC_IO24
GND
PMC_IO32
GND
PMC_IO40
GND
PMC_IO48
GND
PMC_IO56
GND
PMC_IO64
D
GND
PMC_IO6
GND
PMC_IO14
GND
PMC_IO22
GND
PMC_IO30
GND
PMC_IO38
GND
PMC_IO46
GND
PMC_IO54
GND
PMC_IO62
E
PMC_IO3
GND
PMC_IO11
GND
PMC_IO19
GND
PMC_IO27
GND
PMC_IO35
GND
PMC_IO43
GND
PMC_IO51
GND
PMC_IO59
GND
F
PMC_IO1
GND
PMC_IO9
GND
PMC_IO17
GND
PMC_IO25
GND
PMC_IO33
GND
PMC_IO41
GND
PMC_IO49
GND
PMC_IO57
GND
G
GND
PMC_IO7
GND
PMC_IO15
GND
PMC_IO23
GND
PMC_IO31
GND
PMC_IO39
GND
PMC_IO47
GND
PMC_IO55
GND
PMC_IO63
H
GND
PMC_IO5
GND
PMC_IO13
GND
PMC_IO21
GND
PMC_IO29
GND
PMC_IO37
GND
PMC_IO45
GND
PMC_IO53
GND
PMC_IO61
I
BIT_FAIL~
GND
COM1_RTS
GND
COM1_CTS
GND
COM2_RTS
GND
COM2_CTS
GND
Unused
GND
SEQ_IN
GND
SEQ_OUT
GND
NOTE
COM port pins are shown for COM2 operation; see the Serial I/O section for alternate serial
configurations.
6.1.7
Signal Descriptions
Table 6-8 Signal Descriptions
Mnemonic
VCC
P3V3
P3V3_AUX
GND
None
Unused
P12V_AUX
N12V_AUX
GA0~ to GA4~
GAP~
SM0
SM1
SYSRESET~
NVRMO
TCLK
TDO
TDI
TMS
TRST~
VBAT
PCIE_TXxx
PCIE_RXxx
PEG_TXxx
PEG_RXxx
SATA0_TXx
SATA0_RXx
USB_P0x
USB_P1x
P5V_USBPx
GPIO0 – GPIO5
ETH_A_xx
ETH_B_xx
COMx_TXD
COMx_RXD
BIT_FAIL~
PMC_IOxx
COM1_RTS
COM1_CTS
COM2_CTS
COM2_RTS
SEQ_IN
SEQ_OUT
SYS_CON~
Signal Description
+5V DC supply from backplane
+3.3V DC supply from backplane
+3.3V DC supply – permanently present from backplane
The DC voltage reference for the system
No signals specified in VPX specification
Unused by SBC320
+12V DC supply from backplane. Unused by SBC320, but routed directly to PMC
-12V DC supply from backplane. Unused by SBC320, but routed directly to PMC
Geographic Address. These are used to set the slave address of the SBC320
Geographic Address Parity
Serial Management – Clock. Defined in the VPX Specification
Serial Management – Data. Defined in the VPX Specification
System Reset. When this is low, it causes the system to be reset
System Control – Non Volatile Memory – Read Only
Test Clock: JTAG Clock
Test Data Out: JTAG Data Out (Tx from SBC320)
Test Data In: JTAG Data In (Rx to SBC320 from test device)
Test Mode Select: JTAG select line
Test Reset. JTAG Reset
3 V battery supply input to back up CMOS and RTC
PCIe lanes from the LE3100. Can be configured as 1 x 4 or 4 x 1
PCIe lanes to the LE3100. Can be configured as 1 x 4 or 4 x 1
x4 PCIe transmit lines from PEX8518. Can be configured as 1 x 4 or 2 x 2
x4 PCIe receive lines to PEX8518. Can be configured as 1 x 4 or 2 x 2
SATA interface from SBC320 to external SATA device
SATA interface from external SATA device to SBC320
USB interface port 0
USB interface port 1
USB port power. Individually controlled
GPIO
Gigabit Ethernet connection channel A
Gigabit Ethernet connection channel B
Serial COM port Transmit Data
Serial COM port Receive Data
Open drain BIT Fail drive for system level BIT Fail
I/O connections from the PMC J14 connector
Serial COM1 port flow control
Power supply sequencing for rack systems
Power supply sequencing for rack systems
System Controller function enable
Connectors 65
6.2 PMC Connectors
6.2.1 J11
6.2.2 J12
6.2.3 J13
Table 6-9 J11 Connector Pin
Assignments
Assignments
Assignments
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal
TCK
GND
INTB~
BUSMODE1~
INTD~
GND
CLK
GND
REQA~
VIO
AD28
AD25
GND
AD22
AD19
VIO
FRAME~
GND
DEVSEL~
XCAP
N/C
PAR
VIO
AD12
AD09
GND
AD06
AD04
VIO
AD02
AD00
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Signal
-12V
INTA~
INTC~
+5V
N/C
VPX_P3V3_AUX
GND
GNTA~
+5V
AD31
AD27
GND
C/BE3~
AD21
+5V
AD17
GND
IRDY~
+5V
LOCK~
N/C
GND
AD15
AD11
+5V
C/BE0~
AD05
GND
AD03
AD01
+5V
REQ64~
Signal
+12V
TMS
TDI
GND
N/C
BUSMODE2~
RST~
3.3V
N/C
AD30
GND
AD24
IDSELA
3.3V
AD18
AD16
GND
TRDY~
GND
PERR~
3.3V
C/BE1~
AD14
M66EN
AD08
AD07
3.3V
N/C
N/C
GND
ACK64~
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Signal
TRST~
TDO
GND
N/C
N/C
3.3V
BUSMODE3~
BUSMODE4~
GND
AD29
AD26
3.3V
AD23
AD20
GND
C/BE2~
IDSELB
3.3V
STOP~
GND
SERR~
GND
AD13
AD10
3.3V
REQB~
GNTB~
GND
EREADY
RESETOUT~
3.3V
MONARCH~
Signal
Reserved†
GND
C/BE6~
C/BE4~
VIO
AD63
AD61
GND
AD59
AD57
VIO
AD55
AD53
GND
AD51
AD49
GND
AD47
AD45
VIO
AD43
AD41
GND
AD39
AD37
GND
AD35
AD33
VIO
Reserved†
Reserved†
GND
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Signal
GND
C/BE7~
C/BE5~
GND
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
GND
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
GND
AD40
AD38
GND
AD36
AD34
GND
AD32
Reserved‡
GND
Reserved‡
† Reserved by the PCI Specification. ‡ Reserved by the PMC. CAUTION
Do not fit a PMC that requires more than 8 Watts from the 3.3 V supply.
6.2.4
J14
J14 is routed to the VPX P2 connector. Table 6-12 J14 Connector Pin Assignments
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
Signal
PMC_IO1
PMC_IO3
PMC_IO5
PMC_IO7
PMC_IO9
PMC_IO11
PMC_IO13
PMC_IO15
PMC_IO17
PMC_IO19
PMC_IO21
PMC_IO23
PMC_IO25
PMC_IO27
PMC_IO29
PMC_IO31
PMC_IO33
PMC_IO35
PMC_IO37
PMC_IO39
PMC_IO41
PMC_IO43
PMC_IO45
PMC_IO47
PMC_IO49
PMC_IO51
PMC_IO53
PMC_IO55
PMC_IO57
PMC_IO59
PMC_IO61
PMC_IO63
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Signal
PMC_IO2
PMC_IO4
PMC_IO6
PMC_IO8
PMC_IO10
PMC_IO12
PMC_IO14
PMC_IO16
PMC_IO18
PMC_IO20
PMC_IO22
PMC_IO24
PMC_IO26
PMC_IO28
PMC_IO30
PMC_IO32
PMC_IO34
PMC_IO36
PMC_IO38
PMC_IO40
PMC_IO42
PMC_IO44
PMC_IO46
PMC_IO48
PMC_IO50
PMC_IO52
PMC_IO54
PMC_IO56
PMC_IO58
PMC_IO60
PMC_IO62
PMC_IO64
Connectors 67
6.2.5
Signal Descriptions
Table 6-13 PMC Signal Descriptions
Mnemonic
AD0 to AD63
C_BE0 to C_BE7
FRAME~
DEVSEL~
PAR
PARR64
IRDY~
LOCK~
BUSMODE1~
BUSMODE2~ to
BUSMODE4~
RST~
TRDY~
PERR~
SERR~
STOP~
INTA~ to INTD~
CLK
REQA/B~
GNTA/B~
IDSELA/B
REQ64~
ACK64~
M66EN
TCK
TMS
TRST~
TDI
TDO
+5V
3.3V
GND
VIO
N/C
–12V
+12V
VPX_P3V3_AUX
EREADY
RESETOUT~
MONARCH~
Signal Description
Address/Data bits. Multiplexed address and data bus
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry out on
the PCI bus. During the data phase the signals are byte enables that specify the active bytes on the bus
FRAME. Driven low by the current master to signal the start and duration of an access
Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of the current
access
Parity. Parity protection bit for AD0 to AD31 and BE0 to BE3
Parity. Parity protection bit for AD32 to AD63 and BE4 to BE7
Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
LOCK. Driven low to indicate an atomic operation that may require multiple transactions to complete
Bus Mode 1. Driven low by a PMC if it supports the current bus mode
Bus mode. Driven by the host to indicate the bus mode. On the SBC320 this is always PCI. BUSMODE2~ is
only connected to a 4.7 kΩ pull-up. BUSMODE3~ and BUSMODE4~ are connected to GND
Reset. Driven low to reset the PCI bus
Target Ready. Driven low by the current target to signal its ability to complete the current data phase
Parity Error. Driven low by a PCI agent to signal a parity error
System Error. Driven low by a PCI agent to signal a system error
STOP. Driven low by a PCI target to signal a disconnect or target-abort
Interrupt lines. Level-sensitive, active-low interrupt requests
Clock. All PCI bus signals except RST~ are synchronous to this clock
Request. Driven low by a PCI agent to request ownership of the PCI bus
Grant. Driven low by the arbiter to grant PCI bus ownership to a PCI agent
Initialization Device Select. PCI Device chip select used during PCI configuration cycles
Request 64 Bit. Driven low by a PCI master to request 64-bit transfer
Acknowledge 64 Bit. Driven low by PCI agent in response to REQ64
66 MHz Operation. Connected to GND by the host for 33 MHz operation or left high for 66 MHz
Test Clock. Clock for the PMC JTAG
Test Mode Select. Select Test Mode for PMC JTAG
Test Reset. Reset any PMC JTAG devices
Test Data In. Input data for PMC JTAG chain
Test Data Out. Data from a PMC JTAG chain
+5 Volts DC power
The 3.3V pins are connected to the SBC320 main 3.3V switched supply
The supply rail for the PCI bus I/O voltage. For I/O signaling only, not main supply
No connection
-12 Volts DC power from the backplane
+12 Volts DC power from the backplane
P3V3_AUX supply from the backplane
A PMC may hold off PCI emulation till it has completed configuration by driving this pin low
MONARCH PMC Reset out. Not supported on SBC320
Defines the SBC320 as enumerator and interrupt handler (signal pulled up)
NOTE
The SBC320 supports PMC clocking at speeds up to 133 MHz. However, if a PMC is fitted to the SBC320
that does not support the 133 MHz clocking speed, then the Clock will slow down to the fastest speed
that the PMC supports.
6.3 Test Connector
This 80‐way connector (where fitted) is for Factory/Field Application Engineer use only. It provides an interface to on‐board programmable devices and allows the Test Adapter card to be fitted to aid debugging software using the Intel ITP700 (In Target Probe) or to recover SBC320s that have had all boot firmware erased. Table 6-14 Test Connector Pin Assignments
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
Signal
ENET_DIODE_P
ENET_DIODE_N
P3V3
CPLD_TDO
CPLD_TDI
CPLD_TCK
CPLD_TMS
FWH_INIT~
3100_TDO
3100_TDI
3100_TCK
3100_TMS
3100_TRST~
GND
PSU_TDO
PSU_TDI
PSU_TCK
PSU_TMS
GND
2BANKS_FITTED~
HTDI
HTMS
HTRST~
HTCK
GND
HTDO
BCLK~
BCLK
GND
HBPM5~
GND
HBPM4~
GND
HBPM3~
GND
HBPM2~
GND
HBPM1~
GND
HBPM0~
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
Signal
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME~
CLK_33MHZ
SMB1_CLK
VCC
SWITCH_LANE_GOOD0
SWITCH_LANE_GOOD1
SWITCH_LANE_GOOD2
SWITCH_LANE_GOOD3
SWITCH_LANE_GOOD8
SWITCH_LANE_GOOD9
SWITCH_LANE_GOOD10
SWITCH_LANE_GOOD11
GND
P1V5
DDR_NVRAM_WP
DDR_NVRAM_ADD_SWAP
PEX8114_LANE_GOOD0
PEX8114_LANE_GOOD1
PEX8114_LANE_GOOD2
PEX8114_LANE_GOOD3
GND
RESET~
ADS~
BREQ0~
SMB1_DATA
P2V5
BOOT_DEBUG~
HTCK
No connection
RS422_SEL~
PWROK
P3V3_AUX
P3V3_AUX
DBA~
DBR~
P1V05
Connectors 69
Table 6-15 Test Connector Signal Descriptions
Mnemonic
ENET_DIODE_x
CPLD_Txx
3100_Txx
PSU_Txx
FWH_INIT~
LPC_ADx
LPC_FRAME~
CLK_33MHZ
2BANKS_FITTED~
SMB1_CLK
SMB1_DATA
DDR_NVRAM_WP
DDR_NVRAM_ADD_SWAP
SWITCH_LANE_GOODx
PEX8114_LANE_GOODx
ADS~
BREQ0~
BOOT_DEBUG~
RS422_SEL~
PWROK
RESET~
DBA~
DBR~
HBPMx~
BCLK/BCLK~
HTDI
HTMS
HTRST~
HTDO
HTCK
VCC
P3V3_AUX
P3V3
P2V5
P1V5
P1V05
GND
Signal Description
Ethernet thermal diode
CPLD JTAG chain
LE3100 JTAG chain
Power supply controller JTAG chain
Firmware hub init
LPC address/data bus
LPC Frame
33 MHz clock source for LPC bus
Shows that 2 banks of DDR are fitted
I²C bus 1 clock
I²C bus 1 data
Allows writes to on-board DDR NVRAM
Changes the on-board DDR NVRAM address from 0xA6 to 0xAE
Status outputs from PEX8518 to show PCIe link good
Status outputs from PEX8114 to show PCIe link good
Main processor ADS with voltage level translation to 3.3 V
Main processor Bus request with voltage level translation to 3.3 V
Tells the SBC320 to use boot code found on the Test Adapter card
When booting from the Test Adapter card, this allows the COM ports to use RS422 automatically
Shows that all SBC320 power supplies are in specification
CPU FSB reset (defined by ITP700)
Not used on SBC320 (defined by ITP700)
Causes a board reset when driven low (defined by ITP700)
Pins come directly from the CPU (defined by ITP700)
Clock from SBC320 running same phase/speed as FSB CLK (defined by ITP700)
CPU JTAG Data in (defined by ITP700)
CPU JTAG Test mode select (defined by ITP700)
CPU JTAG Reset (defined by ITP700)
CPU JTAG Data out (defined by ITP700)
CPU JTAG Clock (2 pins routed independently for ITP700) (defined by ITP700)
Main +5 V supply direct from VPX
+3.3 V AUX supply from VPX
Switched 3.3 V from VPX. Only present when SBC320 is powered up
SBC320 generated 2.5 V supply. Only present when SBC320 is powered up
Appendix A - Specifications
A.1 Electrical Specification
A.1.1 VPX Power Supply Requirements
For correct operation of the SBC320 the VPX power supply requirements are as shown in Table A‐1: Table A-1 Power Supply Requirements
Supply
Typical
Maximum
Ramp Time
Minimum
Maximum
(mS)
(mS)
VBAT
+3.3V_AUX
+3.3 V
+5 V
±12V_AUX
6 μA
80 mA
2A
5A
10 μA
120 mA
5A
12 A
1A
5
5
5
300
300
300
Inrush
(A)
2.5 A
3.2 A
Input Voltage
Min, inclusive
of ripple (V)
2.2
3.14
3.25
4.87
±11.4
Max, inclusive
of ripple (V)
3.2
3.46
3.45
5.25
±12.6
Ripple Peak-to-Peak
(mV)
50
50
50
50
50
NOTES
1.
The CPU load strongly affects the power taken from the +5 V supply, which can be very dynamic.
2.
The VPX requirement for the ramp time is 20 mS to 150 mS.
3.
The SBC320 does not use the ±12V_AUX supplies, but these are routed to the PMC connectors.
The above table does not show PMC power requirements from these supplies.
4.
The SBC320 does not have any particular requirements with respect to phasing of the input
power rails (+3.3V_AUX, +3.3 V and +5 V).
A.1.2 Power Consumption
Table A‐2 shows the power taken by an SBC320‐x211x (T7400 processor – see Product Codes for variant details) during various operations, and is for guidance only. Table A‐3 shows the power taken by an SBC320‐x111x (L7400 processor – see Product Codes for variant details) during various operations, and is for guidance only. Unless specified otherwise, the SBC320 was tested with a PMC graphics card (using an ATI Rage XL graphics chip) fitted and included in the power measurements. When used, the hard disk power was provided by an independent power supply. All results were measured at 23 °C with all supplies set to normal. The SBC320 tested was fitted with either a T7400 processor running at 2 GHz or an L7400 processor running at 1.5 GHz (FSB 166 MHz), and with 1 GByte of DDR running at 200 MHz (DDR‐3200). ‘Performance Test 6.1’ is a Passmark product. LINK
http://www.passmark.com.
Specifications 71
Table A-2 SBC320-x211x Power Consumption Example
Operation
Power up to BIOS complete (without graphics card)
Power up to BIOS complete
Power up to DOS using on-board USB Flash drive and
COM port (without graphics card)
DOS idle, using on board USB Flash drive and COM port
(without graphics card)
Power up to Windows XP
Windows Idle
Peak power taken running Performance Test 6.1
Running Intel Thermal Analysis Tool with both CPU cores
running at 100%
Input Voltage
+ 3.3 V (Main)
Minimum (A)
1.4
1.9
Peak (A)
2
2.4
+5V
Minimum (A)
2.4
2.4
Average (A)
4.7
4.7
Peak (A)
5.7
5.7
1.4
2.1
2.4
4.7
5.7
1.9
2.1
5.1
5.3
5.7
1.9
1.9
2.4
2.3
2.4
2.6
3.2
4.2
3.3
6.3
6
8.2
2
2.4
8
8.3
8.4
Input Voltage
+ 3.3 V (Main)
Minimum (A)
1.4
1.4
Peak (A)
2.1
2.3
+5V
Minimum (A)
2.6
2.6
Average (A)
4.0
4.0
Peak (A)
4.6
4.7
1.4
2.1
2.4
4.0
4.7
2.0
2.1
2.4
4.3
4.3
1.4
2.3
2.4
2.3
2.3
2.5
3.4
3.7
3.4
5.8
3.5
5.8
Table A-3 SBC320-x111x Power Consumption Example
Operation
Power up to BIOS complete (without graphics card)
Power up to BIOS complete
Power up to DOS using on-board USB Flash drive and
COM port (without graphics card)
DOS idle, using on-board USB Flash drive and COM port
(without graphics card)
Power up to Windows XP
Windows Idle
Peak power taken running Performance Test 6.1
running at 100% (23°C)
2.35
7.7
2.63
8.65
2.6
7.7
A.1.3 3.3 V Auxiliary Supply
The following functions are powered from the 3.3 V Auxiliary supply (VPX P3V3_AUX line): •
Board Management Microcontroller and System Management bus •
Power supply sequencing/monitoring •
BIT Fail LED •
Real Time Clock (this can also be powered from the VPX VBAT supply) NOTE
A standard SBC320 requires the Auxiliary supply to be present, otherwise it will not start up. There is a
build option to configure the board to use the main VPX 3.3 Volt supply instead. Consult the factory
about this option.
A.2 Reliability (MTBF)
Table A‐4 shows the predicted values for reliability as Mean Time Between Failures (MTBF) and failures per million hours (fpmh) for the SBC320‐x211x see Product Codes for variant details). Table A-4 MTBF Figures
Environment
Ground Benign 30°C
Fail Rate (Failures Per Million Hours)
4.87791
MTBF (Hours)
205 006
Ground Fixed 40°C
12.81146
78 055
Ground Mobile 45°C
24.13897
41 427
Naval Sheltered 40°C
20.7523
48 187
Naval Unsheltered 45°C
35.09739
28 492
Airborne Inhabited Cargo 55°C
27.40918
36 484
Airborne Inhabited Fighter 55°C
35.16546
28 437
Airborne Uninhabited Cargo 70°C
46.24713
21 623
Airborne Uninhabited Fighter 70°C
67.11729
14 899
Airborne Rotary Wing 55°C
50.19362
19 923
Space Flight 30°C
4.51070
221 695
Missile Flight 45°C
44.63419
22 404
Missile Launch 55°C
105.1321
9512
The predictions are carried out using MIL‐HDBK‐217F Notices 1 and 2, parts count method. To complement the 217 failure rates, some manufacturers’ data is included where appropriate; πQ values have been modified according to industry practice. A.3 Build Levels
The SBC320 is available in five electrically compatible build levels, each of which is carefully tailored to a particular set of requirements and environments. All five levels fully support the power and versatility of VPX, so no matter how large or diversified your project, absolute compatibility is assured at all stages of development. The five build levels have two basic mechanical configurations, both in accordance with the VITA 46.0 VPX Standard: •
Air (convection)‐cooled (build levels 1 to 3), intended for use in standard industrial chassis •
Conduction‐cooled (build levels 4 and 5), intended for use in sealed Air Transportable Racking (ATR) and other conduction‐cooled environments In addition to these Commercial‐Off‐The‐Shelf (COTS) configurations, the SBC320 may be supplied to meet the mechanical and thermal requirements of specific platforms with the addition of mission specific, to‐type mechanics. Advanced thermal and mechanical designs are used in the PCB, metal work and assembly process to build‐in the required levels of ruggedness. Build level 2 and higher circuit card assemblies include conformal coating as standard. Publication No. SBC320-0HH/2DF
Specifications 73
A brief description of each build style follows, with more detailed specifications after that. Level 1 Intended for use in benign environments, the level 1 board also provides the ideal cost effective method of complete system development. The level 1 assembly comprises a Eurocard‐sized printed wiring board with high quality commercial grade (plastic encapsulated) components. As software compatibility throughout the build styles is absolute, a system intended for final implementation in a severe tactical environment can be developed and debugged at low cost, switching over to the target style only in the final stages of system integration. Level 2 As level 1, but conformally coated and tested in manufacture to provide an extended operating range. Level 3 Level 3 boards are intended for applications that have extended temperature, shock and vibration requirements, but can be served by conventional, forced‐air cooled, racking systems. These rugged boards comprise a Eurocard‐sized printed wiring board fitted with wide temperature range components. Level 4 Designed primarily for use in sealed ATR chassis and other conduction‐cooled environments, the level 4 board features wide temperature range devices, an integral thermal management layer and incorporates a central stiffening bar for additional strength. Cooling is achieved through conduction of heat from the thermal management layer to the cold wall of the rack, to which the boards are secured by screw driven wedgelocks. Level 4 boards are temperature‐characterized during manufacture. Level 5 As level 4, but tested in manufacture to provide an extended operating range. 74 SBC320 3U VPX Single Board Computer
A.4 Environmental Specifications
A.4.1 Convection-cooled Boards
Table A-5 Convection-cooled Environmental Specifications
Build Style
Standard
(Level 1)
Temperature (°C)
Operating: 0 to +55
with airflow of 300
feet/minute.
Storage: -50 to +100
Extended
Temperature
(Level 2)
Operating: -20 to
+65 with airflow of
300 feet/minute
Rugged Aircooled
(Level 3)
Operating: -40 to
+75 with airflow of
600 feet/minute
Vibration
Random:
0.002g2/Hz from 10
to 2000 Hz
Sine: 2g from 5
to 500 Hz
Random:
0.002g2/Hz from 10
to 2000 Hz
Sine: 2g from 5
to 500 Hz
Random:
0.04g2/Hz from 20
to 2000 Hz, with a
flat response to
1000 Hz. 6db/Octave
roll-off from 1000 to
2000 Hz.
Shock
20g peak
sawtooth,
11 ms
duration
Humidity
Up to 95% RH
Comments
Commercial grade cooled by forced
air, for use in benign environments
and software development
applications. Optional conformal
coating
20g peak
sawtooth,
11 ms
duration
Up to 95% RH
with varying
temperature.
10 cycles,
240 hours
As Standard but conformally coated
and temperature characterized
20g peak
sawtooth,
11 ms
duration
Up to 95% RH
with varying
temperature.
10 cycles,
240 hours
Wide temperature rugged, cooled by
forced air. Conformally coated for
additional protection
Shock
40g peak
sawtooth,
11 ms
duration
Humidity
Up to 95% RH
with varying
temperature.
10 cycles,
240 hours
40g peak
sawtooth,
11 ms
duration
Up to 95% RH
with varying
temperature.
10 cycles,
240 hours
Comments
Designed for severe environment
applications with high levels of shock
and vibration, small space envelope
and restricted cooling supplies.
Conformally-coated as standard.
Optional ESS.
Designed for severe environment
applications with high levels of shock
and vibration, small space envelope
and restricted cooling supplies.
Conformally-coated as standard.
Optional ESS.
A.4.2 Conduction-cooled Boards
Table A-6 Conduction-cooled Environmental Specifications
Build Style
Rugged
Conductioncooled (Level 4)
Rugged
Conductioncooled (Level 5)
Temperature (°C)
Operating: -40 to
+75 at the thermal
interface
Storage: -50 to
+100
Vibration
Random: 0.1g2/Hz
Operating: -40 to
+85 at the thermal
interface
Storage: -50 to
+100
Random: 0.1g2/Hz
from 15 to 2000 Hz per
MIL-STD-810E
Fig 514.4 – 8 for high
performance aircraft.
12g RMS
from 15 to 2000 Hz per
MIL-STD-810E
Fig 514.4 – 8 for high
performance aircraft.
12g RMS
Specifications 75
A.5 Mechanical Specification
A.5.1 Dimensions
The VITA 46.0 VPX Standard gives full convection‐cooled and conduction‐cooled 3U VPX dimensions. A.5.2 Weight
The approximately weight of the SBC320 is: Levels 1 to 3 = 460 g Levels 4 and 5 = 525 g A.6 Product Codes
The product code is specified as shown in Table A‐7: Table A-7 Product Codes
x
x
On-board
Firmware
x
I/O options
x
Memory
x
Processor
-
Build Level
SBC320
0 = BIOS
0 = No USB Flash
1 = 512 Mbytes USB Flash
0 = 512 MBytes
2 = 2 GBytes
1 = 1 GByte
1 = L7400 @ 1.5 GHz
2 = T7400 @ 2 GHz
1 = Level 1
4 = Level 4
2 = Level 2
5 = Level 5
3 = Level 3
See the Environmental Specifications section for more details on the build styles. Examples: SBC320‐41100 = Level 4 SBC320 with 1.5 GHz L7400 processor, 1 GByte of SDRAM, no USB Flash. SBC320‐12000 = Level 1 SBC320 with 2.0 GHz T7400 processor, 512 MBytes of SDRAM and 512 MBytes of USB Flash. NOTE
The above table represents the available codes/variants at the time of writing. Contact the factory or
your nearest Sales representative for details of the latest codes/variants.
A.6.1 Software Support
BIT maintenance for the SBC320 is available under product code VPXC3BIT‐1M. Workbench/Platforms/VxWorks BSP maintenance for the SBC320 is available under product code VPXC3BSP‐WBV1M. Workbench/Platforms/VxWorks ESP & BSP maintenance for the SBC320 is available under product code VPXC3BESP‐WBV1M. Linux Software Developer’s Kit (SDK) maintenance for the SBC320 is available under product code VPXC3SDK‐LIN1M. The SBC320 is an AXIS software‐enable computer, so the range of AXIS software is also available. LINKS
AXISFlow Programmer’s Guide, publication number AXISFLOW-0HU.
AXISView EventView API Programmer’s Guide, publication number AXISVIEW-0HU.
Radstone Signal Processing Library Manual, publication number AXISLIB-RSPL-0HL.
Vector, Signal and Image Processing Library Manual, publication number AXISLIB-VSIPL-0HL.
A.6.2 I/O Modules
For use with chassis, Rear Transition Modules are available to convert the condensed P0, P1 and P2 pinouts to industry‐standard formats, plus 3U breakout panels offering a variety of industry standard connectors such as Serial I/O. Internal cables and a basic set of external cables are available. These rear transition and breakout modules are intended for development use in a benign environment, and so are only available in level 1 or 2 build standards. For more details on the I/O modules, see the VPX I/O Modules manual. LINK
VPX I/O Modules Manual, publication number VPXIOM-0HH.
The Rear Transition Module for the SBC320 is the VPX3UX600. Publication No. SBC320-0HH/2DF
Specifications 77
Glossary
NOTE
The connector signals are explained in Section 6.
LINK
This glossary only features terms special to this manual. Explanations of more general terms can be
found in the Glossary, publication number GLOS1.
AGTL Advanced Gunning Transceiver Logic BANC Boot Area Non‐Corruptible. EDMA Enhanced DMA FSB Front Side Bus. The interface between the processor and the system core logic. IICH Integrated I/O Control Hub. IMCH Integrated Memory Control Hub. ITP In Target Probe. LPC Low Pin Count. SIU Serial Interface Unit. 78 SBC320 3U VPX Single Board Computer
Index
A
D
Airflow....................................................................................... 10
Auxiliary Supply.................................................................... 72
Dimensions............................................................................. 76
Documentation Conventions ........................................ 11
DRAM..................................................................................26, 47
B
BANC Boot Flash.................................................................. 26
BIOS ........................................................................................... 18
BIT........................................................................................18, 59
Block Diagram ...................................................................... 25
BMM........................................................................................... 41
Board Identification ........................................................... 15
Board Installation................................................................ 20
Boot Flash ............................................................................... 26
Build Levels ............................................................................ 73
C
Cautions................................................................................... 10
Chassis Ground.................................................................... 20
Clocks........................................................................................ 39
CMOS Default Settings Selection................................. 18
Configuration
Board ............................................................................................ 19
Link..........................................................................................16, 51
Descriptions ....................................................................................17
E1 ........................................................................................................17
E11 ......................................................................................................17
E12 ......................................................................................................18
E13 ......................................................................................................18
E14 ......................................................................................................18
E2 ........................................................................................................17
E7 ........................................................................................................18
Positions ....................................................................................16, 18
Connecting to SBC320...................................................... 21
Connectors............................................................................. 60
J11.................................................................................................. 66
J12.................................................................................................. 66
J13.................................................................................................. 66
J14.................................................................................................. 67
P0 ................................................................................................... 62
P1 ................................................................................................... 63
P2 ................................................................................................... 64
PMC................................................................................................ 66
Positions and Pin Numbering .....................................60, 61
Signal Descriptions.................................................. 65, 68, 70
Test ................................................................................................ 69
VPX................................................................................................. 62
E
E2PROM .............................................................................28, 37
Electrical Specification ..................................................... 71
EMI/EMC................................................................................... 20
Regulatory Compliance ........................................................10
Environmental Specifications ....................................... 75
Equipment Number............................................................ 15
Ethernet ............................................................................29, 43
Number ........................................................................................15
ETI ............................................................................................... 39
F
Features......................................................................................8
Flammability.......................................................................... 10
Flash
BANC Boot Flash ......................................................................26
Select..................................................................................................18
Boot Flash....................................................................................26
Flash Hard Drive................................................ 26, 34, 43, 48
Write Disable ..................................................................................17
Main Boot Flash........................................................................26
Write Disable ..................................................................................17
Front Panel ............................................................................. 59
See Also .................................................. Chassis Ground
Functional Description...................................................... 25
G
Geographical Addressing................................................ 49
GPIO....................................................................................33, 43
Registers ......................................................................................55
H
Handling .................................................................................. 10
Heatsink................................................................................... 10
Humidity .................................................................................. 75
Cooling ..............................................................................10, 75
CPLD .......................................................................................... 41
Index 79
I
I/O ............................................................................................... 29
I/O Modules.....................................................................21, 77
I2C Bus....................................................................................... 36
Identifying Product............................................................. 15
Inspection ............................................................................... 16
Inter-board Sequencing................................................... 24
Introduction ..............................................................................8
J
JTAG........................................................................................... 45
K
Keying ....................................................................................... 20
L
Label.......................................................................................... 15
LEDs ........................................................................................... 53
Activity.......................................................................................... 43
BIT................................................................................................... 42
Locations..................................................................................... 42
Power............................................................................................ 43
Links...........................................................See Configuration
M
Main Boot Flash ................................................................... 26
Mechanical Specification ................................................ 76
Memory.................................................................................... 26
Microprocessor Subsystem............................................ 25
MTBF.......................................................................................... 73
N
Non Volatile Memory Write Protection ..................... 17
NVRAM...................................................................................... 28
O
Operating Environment.................................................... 75
P
PCI Express............................................................................. 34
Photograph ...............................................................................9
PMC.....................................................................................35, 47
Connectors................................................................................. 66
Installation.................................................................................. 19
Power
Requirements.....................................................................21, 71
Up ................................................................................................... 23
Problems ................................................................................. 13
Product Codes ...............................................................15, 76
Product Identification ....................................................... 15
Profile ........................................................................................ 76
PSU Monitor ........................................................................... 39
R
Registers.................................................................................. 46
Alarm Status...............................................................................50
BIT Address/Data Read Back .............................................59
Board Configuration 1...........................................................47
Board ID .......................................................................................46
Board ID String..........................................................................51
Board Revision ..........................................................................47
Control 1 ......................................................................................51
Control 2 ......................................................................................52
Control 3 ......................................................................................53
Drive Links Low.........................................................................54
GPIO
Active Low/High............................................................................57
Both Edges ......................................................................................58
Direction ...........................................................................................56
In ........................................................................................................55
Interrupt Enable ............................................................................56
Interrupt Status .............................................................................58
Level/Edge .......................................................................................57
Out.......................................................................................................55
IRQ Enable...................................................................................54
Link Settings...............................................................................51
VPX Geographical Address..................................................49
Related Documents ........................................................... 12
Reliability ................................................................................. 73
Reset Sequence and Timing .......................................... 23
Revision State ....................................................................... 15
RTC ............................................................................................. 36
RTM ............................................................................................ 77
Ruggedization Levels ........................................................ 73
S
Safety Notices..........................................................................9
SATA....................................................................................29, 43
Serial I/O ...........................................................................29, 52
Shock......................................................................................... 75
Size ............................................................................................. 76
Software Support ................................................................ 77
Specifications........................................................................ 71
Electrical.......................................................................................71
Environmental...........................................................................75
Static RAM............................................................................... 28
Storage Environment ........................................................ 75
System Controller.........................................................48, 63
T
Technical Support Contact Details ............................. 13
Temperature Sensor.......................................................... 38
U
W
Unpacking .............................................................................. 14
USB............................................................................................. 34
USB Flash Disk ...................................................................... 26
Warnings....................................................................................9
Web Sites ................................................................................ 12
Weight ...................................................................................... 76
Write Protection................................................................... 44
V
Vibration .................................................................................. 75
VPX Connectors ................................................................... 62
Index 81
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SBC320 3U VPX SBC Hardware Reference Manual

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