STMP3410

Transcription

STMP3410

Integrated Mixed-Signal Solutions
PRODUCT DATA SHEET
STMP3410
D-Major™ Audio Decoder with USB Interface and Voice Record
Second Generation Audio Decoder
Version 2.0 April 2002
Host Processor˜
(Optional)
90
94
FM Tuner
98
102
106
Battery
LED/LCD Screen
SDRAM
USB
Microphone
Voice Record
Flash Memory
Headphones
Buttons/Switches
CD Pickup
Hard Drive
OFFICIAL PRODUCT DOCUMENTATION 4/17/02
5-3410-D1-2.0-0402
Copyright © 2002 SigmaTel, Inc. All rights reserved.
All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc.
SigmaTel, the SigmaTel logo, and combinations thereof are registered trademarks and D-Major and C-Major are trademarks of SigmaTel,
Inc. Other product names used in this publication are for identification purposes only and may be trademarks or registered trademarks of
their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has
made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties,
express or implied, as to the accuracy or completeness of the contents of this publication and is providing this publication "AS IS". SigmaTel,
Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make
changes to its products at any time without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential, or incidential damages.
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TABLE OF CONTENTS
1. TABLE OF CONTENTS ..................................................................................................................... 2
1.1. List of Figures ....................................................................................................................................8
1.2. List of Tables ......................................................................................................................................8
2. PRODUCT OVERVIEW ................................................................................................................... 13
2.1. Features ...........................................................................................................................................13
2.2. Description .......................................................................................................................................13
2.3. Additional Documentation ................................................................................................................14
2.4. STMP3410 Block Diagram ...............................................................................................................14
3. CHARACTERISTICS/SPECIFICATIONS ........................................................................................ 15
3.1. Absolute Maximum Ratings .............................................................................................................15
3.2. Recommended Operating Conditions ..............................................................................................15
4. MEMORY MAP ................................................................................................................................ 16
4.1. PXRAM Configuration Register .......................................................................................................16
4.2. PYRAM Configuration Register .......................................................................................................16
4.3. On-Chip Memory Configuration Register .........................................................................................19
5. DSP CORE ....................................................................................................................................... 20
5.1. Revision Register .............................................................................................................................20
5.2. Reset Control Register .....................................................................................................................21
5.3. DCLK Count Lower Register ............................................................................................................22
5.4. DCLK Count Upper Register ............................................................................................................22
5.5. Cycle Steal Count Register ..............................................................................................................22
5.6. Operating Mode Register .................................................................................................................23
5.7. Clock Control Register .....................................................................................................................24
5.8. Misc/Spare Register .........................................................................................................................26
5.9. Scratch Register ..............................................................................................................................26
5.10. Interrupt Priority Register ...............................................................................................................27
5.11. Interrupt Collector ..........................................................................................................................28
5.11.1. Interrupt Sources ..............................................................................................................29
5.11.2. Interrupt Vectors ...............................................................................................................30
5.11.3. Interrupt Collector Registers ............................................................................................30
5.11.3.1. ICOLL Enable 0 Registers ..............................................................................30
5.11.3.2. ICOLL Enable 1 Registers ..............................................................................31
5.11.3.3. ICOLL Status 0 Registers ...............................................................................31
5.11.3.4. ICOLL Status 1 Registers ...............................................................................31
5.11.3.5. ICOLL Priority 0 Registers ..............................................................................31
5.11.3.10. ICOLL Steering 0 Registers ..........................................................................33
5.11.4. Interrupt Collector Debug Registers .................................................................................35
5.11.4.1. ICOLL Debug Force 0 Registers ....................................................................35
5.11.4.2. ICOLL Debug Force 1 Registers ....................................................................35
5.11.4.3. ICOLL Force Enable 0 Registers ....................................................................35
5.11.4.4. ICOLL Force Enable 1 Registers ....................................................................35
5.11.4.5. ICOLL Observation Registers (HW_ICLOBSV0R/1R) ....................................36
5.11.4.5.1. Interrupt Collector Observe 0 Register ..........................................36
5.11.4.5.2. Interrupt Collector Observe 1 Register ..........................................36
5.12. General Debug Register ................................................................................................................36
6. USB INTERFACE ............................................................................................................................ 37
6.1. USB Interface Registers ..................................................................................................................37
6.1.1. USB Endpoint 0 Address Pointer Registers .......................................................................37
ADDITIONAL SUPPORT
Additional product and company information can be obtained by going to the SigmaTel website at: www.sigmatel.com
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6.1.2. USB Utility Register ............................................................................................................37
6.1.3. USB Endpoint Control Status Register ..............................................................................38
6.1.4. USB Configuration Base Address Pointer Register ...........................................................38
6.1.5. USB Control Status Register ..............................................................................................39
6.1.6. USB End Point Data Transfer Types .................................................................................40
6.1.6.1. USB EP0 ...........................................................................................................40
6.1.6.2. USB Control Transfer Type ..............................................................................40
6.1.6.3. USB Bulk Transfer Type ...................................................................................40
6.1.6.4. USB Isochronous Transfer Type ......................................................................40
6.1.6.5. USB Interrupt Transfer Type .............................................................................41
6.1.7. USB Configuration Tables ..................................................................................................41
6.1.7.1. USBDescriptorTable .........................................................................................41
6.1.7.2. USBPowerOnTable ..........................................................................................42
6.1.7.3. Pre-Defined Descriptor Values .........................................................................43
6.2. USB Port Setup Sequences .............................................................................................................44
6.2.0.1. USB Intitialization ..............................................................................................44
6.2.0.2. USB Shutdown .................................................................................................44
6.2.0.3. EP7 Interrupt Service ........................................................................................44
6.3. Multiple Configurations ....................................................................................................................44
7. PARALLEL EXTERNAL MEMORY CONTROLLER (EMC) ........................................................... 45
7.1. EMC Overview .................................................................................................................................45
7.1.1. EMC External Pins .............................................................................................................46
7.2. General Use of the External Memory Interface ................................................................................46
7.2.1. Common Flash Registers ...................................................................................................47
7.2.1.1. Flash Control Register ......................................................................................47
7.2.1.2. Flash Control 2 Register ...................................................................................48
7.2.1.3. Flash Start Address Low Register ....................................................................48
7.2.1.4. Flash Start Address High Register ...................................................................48
7.3. External Memory Interface with SmartMedia/NAND Flash Devices ................................................48
7.3.1. SmartMedia/NAND Pins .....................................................................................................49
7.3.2. SmartMedia Registers ........................................................................................................50
7.3.2.1. SmartMedia Control Register ...........................................................................50
7.3.2.2. SmartMedia Timer 1 Register ...........................................................................51
7.3.2.3. SmartMedia Timer 2 Register ...........................................................................51
7.4. External Memory Interface in CompactFlash Mode .........................................................................51
7.4.1. CompactFlash Modes ........................................................................................................51
7.4.2. CompactFlash Registers ....................................................................................................52
7.4.2.1. CompactFlash Control Register ........................................................................52
7.4.2.2. CompactFlash Timer1 Register ........................................................................53
7.4.2.3. CompactFlash Timer2 Register ........................................................................53
7.4.3. Using the CompactFlash Modes ........................................................................................53
8. I2C INTERFACE ............................................................................................................................... 54
8.1. I2C-Specific Implementation ...........................................................................................................54
8.1.1. I2C Interface External Pins .................................................................................................54
8.1.2. I2C Interface Registers .......................................................................................................54
8.1.2.1. I2C Interface Control/Status Register ...............................................................55
8.1.2.2. I2C Data Registers ............................................................................................56
8.1.2.3. I2C Clock Divider Register ................................................................................57
8.1.3. I2C Interrupt Sources .........................................................................................................57
8.2. I2C Bus Protocol ..............................................................................................................................57
8.2.1. Slave Mode Protocol ..........................................................................................................58
8.2.2. Master Mode Protocol ........................................................................................................60
8.2.2.1. Clock Gen .........................................................................................................60
8.2.2.2. Master Mode Operation ....................................................................................60
9. SPI INTERFACE .............................................................................................................................. 63
9.1. SPI Pins ...........................................................................................................................................63
9.2. SPI Registers ...................................................................................................................................63
9.2.1. SPI Control Register ..........................................................................................................63
9.2.2. SPI Data Register ..............................................................................................................64
9.3. Transferring Data over SPI ..............................................................................................................64
9.3.1. Master Mode ......................................................................................................................64
9.3.1.1. Clock Generation ..............................................................................................64
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9.3.1.2. Slave Selects in Master Mode ..........................................................................65
9.3.2. Slave Mode ........................................................................................................................65
10. ON-CHIP TIMERS .......................................................................................................................... 66
10.1. Using the Timer Modules ...............................................................................................................66
10.1.1. General Programming Guidelines ....................................................................................66
10.1.2. Software-Visible Programmable I/O (PIO) Register .........................................................66
10.1.2.1. Timer Control Register ....................................................................................66
10.1.2.2. Timer Count Register ......................................................................................67
10.1.3. Timer Modes ....................................................................................................................67
10.1.3.1. Internal Clock Decrement, No Output Clock ...................................................67
10.1.3.2. Internal Clock Decrement, Output Pulse ........................................................68
10.1.3.3. Internal Clock, Output Toggle .........................................................................68
10.1.3.4. External Pulse Width Measurement ...............................................................68
10.1.3.5. External Period Measurement ........................................................................68
10.1.3.6. External Clock Increment ................................................................................69
10.1.3.7. External Clock Decrement ..............................................................................69
10.1.4. AC Timing Considerations ...............................................................................................69
11. SDRAM INTERFACE ..................................................................................................................... 70
11.1. SDRAM Interface Registers ...........................................................................................................70
11.1.1. SDRAM Address Pointer 1 Register ................................................................................70
11.1.2. SDRAM Address Pointer 2 Register ................................................................................71
11.1.3. SDRAM System Address Pointer Register ......................................................................71
11.1.4. SDRAM Size Register ......................................................................................................71
11.1.5. SDRAM Timer 1 Register .................................................................................................71
11.1.6. SDRAM Timer 2 Register .................................................................................................72
11.1.7. System Memory Modulo Base Address Register .............................................................72
11.1.8. System Memory Modulo Register ....................................................................................72
11.1.9. SDRAM Memory Modulo Base Address 1 Register .........................................................73
11.1.10. SDRAM Memory Modulo Base Address 2 Register .......................................................73
11.1.11. SDRAM Memory Modulo 1 Register ..............................................................................73
11.1.12. SDRAM Memory Modulo 2 Register ..............................................................................73
11.1.13. SDRAM Transfer Count Register ..................................................................................74
11.1.14. SDRAM Mode Register .................................................................................................74
11.1.15. SDRAM Type Register ..................................................................................................74
11.1.16. SDRAM Control Status Register ....................................................................................75
12. SWIZZLE ........................................................................................................................................ 77
12.1. SWIZZLE Registers .......................................................................................................................77
12.1.1. SWIZZLE Control and Status Register 1 .........................................................................77
12.1.2. SWIZZLE Control and Status Register 2 .........................................................................78
12.1.3. SWIZZLE Transfer Size ...................................................................................................79
12.1.4. SWIZZLE Source Address Register .................................................................................79
12.1.5. SWIZZLE DATA1 Register ...............................................................................................79
12.1.6. SWIZZLE DATA2 Register ...............................................................................................79
12.1.7. SWIZZLE Destination Address Register ..........................................................................79
12.1.8. SWIZZLE Big Endian Register .........................................................................................80
12.1.9. SWIZZLE Bit Reversed Register ......................................................................................80
12.1.10. SWIZZLE Pass Least Significant Byte Register .............................................................80
12.1.11. SWIZZLE Pass Intermediate Significant Byte Register ..................................................80
12.1.12. SWIZZLE Pass Most Significant Byte Register ..............................................................80
12.1.13. SWIZZLE Pass Least Significant Word Register ...........................................................81
12.1.14. SWIZZLE Pass Intermediate Significant Word Register ................................................81
12.1.15. SWIZZLE Pass Most Significant Word Register ............................................................81
12.1.16. SWIZZLE Barrel Shift Register ......................................................................................81
12.2. SWIZZLE Data Manipulation Examples .........................................................................................82
13. REAL-TIME CLOCK/WATCHDOG RESET ................................................................................... 83
13.1. Real-Time Clock Registers ............................................................................................................83
13.1.1. RTC Upper Data Word .....................................................................................................84
13.1.2. RTC Lower Data Word .....................................................................................................84
13.2. Watchdog Reset Timer Registers ..................................................................................................84
13.2.1. Watchdog Count Register ................................................................................................84
13.2.2. Watchdog Reset Enable Register ....................................................................................84
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14. CDSYNC INTERFACE ................................................................................................................... 85
14.1. CDSYNC Interface Registers .........................................................................................................85
14.1.1. CDSYNC Control Status Register ....................................................................................85
14.1.2. CDSYNC Data Register ...................................................................................................86
14.1.3. CDSYNC Word Count Register .......................................................................................86
14.1.4. CDSYNC Current Position Register .................................................................................86
14.1.5. CDSYNC Modulo Register ...............................................................................................86
14.1.6. CDSYNC Base Address Register ....................................................................................87
14.2. Reed Solomon Error Corrector Registers ......................................................................................87
14.2.1. Reed Solomon Control Status Registers .........................................................................87
14.2.2. Reed Solomon Error Offset Register ...............................................................................88
14.2.3. Reed Solomon Word Count Register ...............................................................................88
14.2.4. Reed Solomon Current Position Register ........................................................................88
14.2.5. Reed Solomon Modulo Register ......................................................................................89
14.2.6. Reed Solomon Base Address Register ............................................................................89
14.2.7. Reed Solomon Parity Base Address Register .................................................................89
14.2.8. Reed Solomon Span Register ..........................................................................................89
15. CD-DSP INTERFACE .................................................................................................................... 90
15.1. Features .........................................................................................................................................90
15.2. Hardware functionality ...................................................................................................................90
15.2.1. Functional Description ......................................................................................................90
15.2.1.1. Overview .........................................................................................................90
15.2.1.2. Memory Map ...................................................................................................92
15.2.1.3. Implementation Details ...................................................................................92
15.2.1.4. Interrupts .........................................................................................................94
15.2.1.5. Chip level I/O mapping ...................................................................................95
15.3. Software Functionality ....................................................................................................................95
15.3.1. Programming Rules, Guidelines, and Examples ..............................................................95
15.3.1.1. General Programming Notes ..........................................................................95
15.3.2. CD-DSP Interface (CDI) Registers ...................................................................................96
15.3.2.1. CD-DSP Interface Control Unit Control Status Register .................................96
15.3.2.2. CDI Control Port Timer Register .....................................................................96
15.3.2.3. CDI Time Base Register .................................................................................97
15.3.2.4. CDI Data Register ...........................................................................................97
15.3.2.5. CDI Pin Configuration Register .......................................................................97
15.3.2.6. CD-DSP Interface Serial Input Control Status Register ..................................98
15.3.2.7. Serial Input Time Base Registers ...................................................................98
15.3.2.8. Serial Input Timer Registers ...........................................................................99
15.3.2.9. Serial Input Data Registers .............................................................................99
16. I2S SERIAL AUDIO INTERFACE ................................................................................................ 100
16.1. I2S External Pins ..........................................................................................................................100
16.2. I2S Receive and Transmit Registers ............................................................................................101
16.2.1. Receivers .......................................................................................................................101
16.2.1.1. Receive Status I2S Control Register .............................................................101
16.2.1.2. Receive Status I2S DataI0 Register ..............................................................102
16.2.1.5. Handling Different Word Lengths ..................................................................103
16.2.2. Transmitters ...................................................................................................................103
16.2.2.1. Transmit Status I2S Control Register ............................................................103
16.2.2.2. Transmit Status I2S DataO0 Register ...........................................................104
16.2.3. Timing ............................................................................................................................105
16.2.4. Setting SAI Mode ...........................................................................................................105
16.2.5. Interrupts ........................................................................................................................105
17. TRACE BUFFER .......................................................................................................................... 106
17.1. Trace Buffer Specification ............................................................................................................106
17.2. Trace Buffer Registers .................................................................................................................107
17.2.1. Trace Buffer Configuration Register ...............................................................................107
17.2.2. Trace Buffer Base Address Register ..............................................................................107
17.2.3. Trace Buffer Modulus Address Register ........................................................................108
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17.2.4. Trace Buffer Current Address Register ..........................................................................108
17.2.5. Trace Buffer Mask Registers ..........................................................................................108
17.2.6. Trace Buffer Trigger Command Status Register ............................................................108
17.2.7. Trace Buffer Trigger Value Register ..............................................................................109
17.3. Trace Buffer State Machine .........................................................................................................110
18. GENERAL PURPOSE INPUT/OUTPUT (GPIO) MODULES ...................................................... 111
18.1. GPIO Interface .............................................................................................................................111
18.2. GPIO Registers ............................................................................................................................112
18.2.1. GPIO Enable Register ....................................................................................................112
18.2.2. GPIO Data Out Register ................................................................................................112
18.2.3. GPIO Data In Register ...................................................................................................112
18.2.4. GPIO Data Out Enable Register ....................................................................................112
18.2.5. GPIO Interrupt Pin Enable Register ...............................................................................113
18.2.6. GPIO Interrupt Enable Register .....................................................................................113
18.2.7. GPIO Interrupt Level Register ........................................................................................113
18.2.8. GPIO Interrupt Polarity Register ....................................................................................114
18.2.9. GPIO Interrupt Status Register ......................................................................................114
18.2.10. GPIO Pin Power Register ............................................................................................114
18.2.11. GPIO Pin Drive Strength Register ................................................................................115
18.2.12. GPIO Register Pin Assignments ..................................................................................115
18.2.12.1. GPIO0 (Bank 0) ..........................................................................................115
18.2.12.2. GPIO1 (Bank 1) ..........................................................................................116
18.2.12.3. GPIO2 (Bank 2) ..........................................................................................117
18.2.12.4. GPIO3 (Bank 3) ..........................................................................................117
19. DAC/ADC/MIXER/HEADPHONE/LRADC ................................................................................... 119
19.1. DAC .............................................................................................................................................119
19.1.1. DAC Registers ...............................................................................................................119
19.1.1.1. DAC Base Address Register ........................................................................119
19.1.1.2. DAC Modulo Register ...................................................................................120
19.1.1.3. DAC Current Position Register .....................................................................120
19.1.1.4. DAC Word Count Register ............................................................................120
19.1.1.5. DAC Sample Rate Register ..........................................................................121
19.1.1.6. DAC Control Status Register ........................................................................122
19.2. ADC .............................................................................................................................................122
19.2.1. ADC Registers ...............................................................................................................123
19.2.1.1. ADC Base Address Register ........................................................................123
19.2.1.2. ADC Modulo Register ...................................................................................123
19.2.1.3. ADC Current Position Register .....................................................................123
19.2.1.4. ADC Word Count Register ............................................................................124
19.2.1.5. ADC Sample Rate Register ..........................................................................124
19.2.1.6. ADC Control Status Register ........................................................................125
19.3. Mixer ............................................................................................................................................126
19.3.1. Mixer Address Registers ................................................................................................126
19.3.2. Mixer Block Diagram ......................................................................................................126
19.3.3. Mixer Programming Model .............................................................................................127
19.3.3.1. Mixer Master Volume Register .....................................................................127
19.3.3.2. Analog Mixer Volume Registers ...................................................................128
19.3.3.2.1. Mixer Microphone-In Volume Register ........................................128
19.3.3.2.2. Mixer Line-In Volume Register ....................................................129
19.3.3.2.3. Mixer Line-In 2 Volume Register .................................................129
19.3.3.2.4. Mixer DAC In Volume Register ...................................................129
19.3.3.2.5. Mixer Record Select Register ......................................................130
19.3.3.3. Mixer ADC Gain Register .............................................................................130
19.3.3.4. Mixer Power Down Control/Status Register .................................................131
19.3.3.5. Codec/Mixer Test Register ...........................................................................131
19.3.3.6. Reference Control Register ..........................................................................133
19.4. Headphone Driver ........................................................................................................................134
19.4.1. Headphone Control Register ..........................................................................................134
19.4.2. Headphone Driver ..........................................................................................................135
19.5. Low Resolution ADC ....................................................................................................................135
19.5.1. Low Resolution ADC Control Register ...........................................................................136
19.5.2. Low Resolution ADC Result Register ............................................................................137
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20. BOOT MODES ............................................................................................................................. 138
20.1. General Information on Boot Modes ............................................................................................138
20.2. Bootloader Code Format ..............................................................................................................139
20.3. Encryption ....................................................................................................................................141
20.4. Bootloader Examples ...................................................................................................................141
20.4.1. Boot Example #1 ............................................................................................................141
20.4.2. Boot Example #2 ............................................................................................................141
20.4.3. Boot Example #3 ............................................................................................................142
20.5. Boot Procedure ............................................................................................................................142
20.5.1. USB boot mode ..............................................................................................................142
20.5.1.1. USB Boot Mode Pin Power ...........................................................................145
20.5.2. NAND Flash Boot Mode .................................................................................................145
20.5.2.1. NAND Flash Boot Mode Pin Power ..............................................................145
20.5.3. I2C Slave Boot Mode ......................................................................................................146
20.5.3.1. I2C Slave Boot Mode Pin Power ...................................................................146
20.5.4. I2C Master Boot Mode ....................................................................................................146
20.5.4.1. I2C Master Boot Mode Pin Power .................................................................146
20.5.5. SPI Slave Boot Mode .....................................................................................................146
20.5.5.1. SPI Slave Boot Mode Pin Power ..................................................................146
20.5.6. TESTERLOADER Boot Mode ........................................................................................146
20.5.7. BURNIN Boot Mode .......................................................................................................146
20.5.8. System Recovery Mode .................................................................................................147
20.6. Memory Maps ..............................................................................................................................147
21. DC-DC CONVERTER .................................................................................................................. 148
21.1. STMP3410 DC-DC Converter Implementation ............................................................................148
21.1.1. Defining Battery Configuration .......................................................................................148
21.1.1.1. DC-DC Converter Configuration ...................................................................149
21.1.1.2. Power Up Sequence .....................................................................................149
21.1.1.3. Power Down Sequence ................................................................................153
21.1.1.4. Powered Down State ....................................................................................153
21.1.1.5. Reset Sequence ...........................................................................................154
21.1.1.6. Summary of Major DC-DC Features .............................................................154
21.1.2. DC-DC Registers ...........................................................................................................155
21.1.2.1. DCDC1 Control Register A ...........................................................................155
21.1.2.2. DCDC1 Control Register B ...........................................................................156
21.1.2.3. DCDC2 Control Register A ...........................................................................156
21.1.2.4. DCDC2 Control Register B ...........................................................................157
21.1.2.5. DC-DC VddIO Control Register ....................................................................158
21.1.2.6. DC-DC VddD Control Register .....................................................................158
21.1.2.7. DC-DC VddA/Battery Brownout Enable Control Register .............................159
21.1.2.8. DC-DC Test Bit Register ...............................................................................159
21.2. System Brownout .........................................................................................................................161
22. PIN DESCRIPTION ..................................................................................................................... 162
22.1. STMP3410 Pin Placement and Definitions ..................................................................................162
22.1.1. Analog Pins ....................................................................................................................167
22.1.2. DCDC Converter Pins ....................................................................................................167
22.1.3. External Memory Interface (CompactFlash) Pins ...........................................................167
22.1.4. External Memory Interface (SmartMedia) Pins ..............................................................168
22.1.5. General Purpose Input/Output Pins ...............................................................................169
22.1.6. I2C Interface Pins ...........................................................................................................170
22.1.7. I2S Interface Pins ...........................................................................................................170
22.1.8. Power Pins .....................................................................................................................170
22.1.9. SDRAM Interface Pins ...................................................................................................171
22.1.10. SPI Interface Pins ........................................................................................................172
22.1.11. System Pins .................................................................................................................172
22.1.12. USB Interface Pins .......................................................................................................172
23. PACKAGE DRAWINGS ............................................................................................................... 173
23.1. 100-Pin TQFP ..............................................................................................................................173
23.2. 144-Pin TQFP ..............................................................................................................................174
23.3. 144-Pin fpBGA .............................................................................................................................175
24. INDEX OF REGISTERS ............................................................................................................... 176
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1.1.
List of Figures
Figure 1. STMP3410 Block Diagram ..............................................................................................................14
Figure 2. STMP3410 Package Photos ...........................................................................................................14
Figure 3. Memory Organization ......................................................................................................................17
Figure 4. DSP Memory Map ...........................................................................................................................18
Figure 5. DSP Architechure ...........................................................................................................................20
Figure 6. Clock Control Register (HW_CCR) .................................................................................................24
Figure 7. Interrupt Collector Diagram .............................................................................................................28
Figure 8. I2C data and clock timing ................................................................................................................57
Figure 9. Slave Mode Flow Chart ...................................................................................................................59
Figure 10. Master Mode Flow Chart ...............................................................................................................61
Figure 11. Master Mode Flow Chart – Read and Write States .......................................................................62
Figure 12. Timing diagram of SPI signals, including the various SCLK phases .............................................65
Figure 13. CDI Serial Transfer Type Examples ..............................................................................................91
Figure 14. CDI Serial Interface Architecture ...................................................................................................92
Figure 15. Control Interface State Machine ...................................................................................................93
Figure 16. Serial Input State Machine ............................................................................................................94
Figure 17. I2S Block Diagram .......................................................................................................................100
Figure 18. Receive and Transmit Data Timing .............................................................................................105
Figure 19. Trace Buffer State Machine State Diagram ................................................................................110
Figure 20. GPIO Setup Flow Chart ..............................................................................................................111
Figure 21. Mixer Flow Diagram ....................................................................................................................126
Figure 22. Mixer Block Diagram ...................................................................................................................127
Figure 22. Mixer Block Diagram ...................................................................................................................127
Figure 23. External Microphone Bias Generation ........................................................................................128
Figure 24. Internal Microphone Bias Generation ..........................................................................................129
Figure 25. Headphone application circuit .....................................................................................................135
Figure 26. Low Resolution ADC Diagram ....................................................................................................135
Figure 27. Initial Boot Sequence ..................................................................................................................143
Figure 28. Boot Procedure ...........................................................................................................................144
Figure 29. USB Boot Mode Memory Map ....................................................................................................147
Figure 30. All Other Boot Modes Memory Map ............................................................................................147
Figure 31. DC-DC Converter Control System ..............................................................................................149
Figure 32. DC-DC Converter Control System (Mode 000) ...........................................................................150
Figure 38. Brownout Event Detect Available Circuitry ..................................................................................161
Figure 39. STMP3410 Package Photos .......................................................................................................162
Figure 40. 100-Pin TQFP Package Drawing ................................................................................................173
Figure 41. 144-Pin TQFP Package Drawing ................................................................................................174
Figure 42. 144-Pin fpBGA Package Drawing ...............................................................................................175
1.2.
List of Tables
Table 1. Absolute Maximum Ratings ..............................................................................................................15
Table 2. Recommended Operating Conditions ..............................................................................................15
Table 3. PXRAM Configuration Register Description .....................................................................................16
Table 4. PYRAM Configuration Register Description .....................................................................................16
Table 5. On-Chip Memory Configuration Register Description ......................................................................19
Table 6. Revision Register Description ..........................................................................................................20
Table 7. Reset Control Register Description ..................................................................................................21
Table 8. DCLK Count Lower Register Description .........................................................................................22
Table 9. DCLK Count Upper Register Description .........................................................................................22
Table 10. Cycle Steal Count Register Description .........................................................................................22
Table 11. Operating Mode Register Description ............................................................................................23
Table 12. Clock Control Register Description ................................................................................................24
Table 13. Misc/Spare Register Description ....................................................................................................26
Table 14. Scratch Register Description ..........................................................................................................26
Table 15. Interrupt Priority Register Description ............................................................................................27
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Table 16. Interrupt Sources ............................................................................................................................29
Table 17. Interrupt Vector Map ......................................................................................................................30
Table 18. ICOLL Enable 0 Register Description ............................................................................................30
Table 19. ICOLL Enable 1 Register Description ............................................................................................31
Table 20. ICOLL Status 0 Register Description .............................................................................................31
Table 21. ICOLL Status 1 Register Description .............................................................................................31
Table 22. ICOLL Priority 0 Register Description ............................................................................................31
Table 27. ICOLL Steering 0 Register Description ..........................................................................................33
Table 30. ICOLL Force Value 0 Register Description ....................................................................................35
Table 31. ICOLL Force Value 1 Register Description ....................................................................................35
Table 32. ICOLL Force Enable 0 Register Description ..................................................................................35
Table 33. ICOLL Force Enable 1 Registers Description ................................................................................35
Table 34. ICOLL Observe 0 Register Description ..........................................................................................36
Table 35. ICOLL Observe 1 Register Description ..........................................................................................36
Table 36. USB Endpoint 0 Address Pointer Registers Description ................................................................37
Table 37. USB Utility Register Description .....................................................................................................37
Table 38. USB Endpoint Control Status Register Description ........................................................................38
Table 39. USB Configuration Base Address Pointer Register Description ....................................................38
Table 40. USB Control Status Register Description .......................................................................................39
Table 41. USB End Point 0 (EP0) ..................................................................................................................40
Table 42. USB Control Transfer Type ............................................................................................................40
Table 43. USB Bulk Transfer Type ................................................................................................................40
Table 44. USB Isochronous Transfer Type ....................................................................................................40
Table 45. USB Interrupt Transfer Type ..........................................................................................................41
Table 46. USBEndPtBuf Format Description .................................................................................................42
Table 47. USBConfigBuf Format Description .................................................................................................42
Table 49. Pre-Defined Device Descriptor Description ....................................................................................43
Table 50. Pre-Defined Device Descriptor .......................................................................................................43
Table 51. USB EP0 Descriptor .......................................................................................................................43
Table 48. USBConfigBuf Format Description .................................................................................................43
Table 52. Mapping of pins to CF+/CompactFlash and SmartMedia Card/Device Pins ................................46
Table 53. Flash Control Register Description .................................................................................................47
Table 54. Flash Control 2 Register Description ..............................................................................................48
Table 55. Flash Start Address Low Register Description ...............................................................................48
Table 56. Flash Start Address High Register Description ..............................................................................48
Table 57. SmartMedia Control Register Description ......................................................................................50
Table 58. SmartMedia Timer 1 Register Description .....................................................................................51
Table 59. SmartMedia Timer 2 Register Description .....................................................................................51
Table 60. SmartMedia Timing Specifications .................................................................................................51
Table 61. CompactFlash Control Register Description ..................................................................................52
Table 62. CompactFlash Timer1 Register Description ...................................................................................53
Table 63. CompactFlash Timer2 Register Description ...................................................................................53
Table 64. I2C Registers Address Map ............................................................................................................54
Table 65. I2C Interface Control/Status RegisterDescription ...........................................................................55
Table 66. I2C Data Register Description ........................................................................................................56
Table 67. I2C Clock Divider Register Description ...........................................................................................57
Table 68. I2C Interrupt Address Map .............................................................................................................57
Table 69. Transfer when Master is writing a single byte of data to the interface as a slave ..........................58
Table 70. Transfer when Master is writing multiple bytes to the interface as a slave ....................................58
Table 71. Transfer when Master is receiving one byte of data from interface as a slave ..............................58
Table 72. Transfer when Master is receiving multiple bytes of data from interface as a slave ......................58
Table 73. Slave and Master mode address definitions ..................................................................................59
Table 74. Transfer when the interface as master is transmitting one byte of data would be .........................60
Table 75. Transfer when the interface as master is reading multiple status bytes of data from slave ...........60
Table 76. Transfer when Master is receiving one byte of data from slave internal sub-address ...................60
Table 77. Transfer when Master is receiving multiple bytes of data from slave internal sub-address ...........60
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Table 78. SPI Control Register Description ....................................................................................................63
Table 79. SPI Data Register Description ........................................................................................................64
Table 80. Timer Control Register Description ................................................................................................66
Table 81. Timer Count Register Description ..................................................................................................67
Table 82. AC Timing for DSP Interface ..........................................................................................................69
Table 83. SDRAM Address Pointer 1 Register Description ...........................................................................70
Table 84. SDRAM Address Pointer 2 Register Description ...........................................................................71
Table 85. System Address Pointer Register1 Description .............................................................................71
Table 86. SDRAM Size Register Description .................................................................................................71
Table 87. SDRAM Timer 1 Register Description ............................................................................................71
Table 88. SDRAM Timer 2 Register Description ............................................................................................72
Table 89. System Memory Modulo Base Address Register Description ........................................................72
Table 90. System Memory Modulo Register Description ...............................................................................72
Table 91. SDRAM Memory Modulo Base Address 1 Register Description ....................................................73
Table 92. SDRAM Memory Modulo Base Address 2 Register Description ....................................................73
Table 93. SDRAM Memory Modulo 1 Register Description ...........................................................................73
Table 94. SDRAM Memory Modulo 2 Register Description ...........................................................................73
Table 95. SDRAM Transfer Count Register Description ................................................................................74
Table 96. SDRAM Mode Register Description ...............................................................................................74
Table 97. SDRAM Mode Register Description ...............................................................................................74
Table 98. SDRAM Control Status Register Description .................................................................................75
Table 99. SWIZZLE Control and Status Register 1 Description .....................................................................77
Table 100. SWIZZLE Control and Status Register 2 Description ...................................................................78
Table 101. SWIZZLE Transfer Size Description ............................................................................................79
Table 102. SWIZZLE Source Address Register Description ..........................................................................79
Table 103. SWIZZLE DATA1 Register Description ........................................................................................79
Table 104. SWIZZLE DATA2 Register Description ........................................................................................79
Table 105. SWIZZLE Destination Address Register Description ...................................................................79
Table 106. SWIZZLE Big Endian Register Description ..................................................................................80
Table 107. SWIZZLE Bit Reversed Register Description ...............................................................................80
Table 108. SWIZZLE Pass Least Significant Byte Register Description ........................................................80
Table 109. SWIZZLE Pass Intermediate Significant Byte Register Description .............................................80
Table 110. SWIZZLE Pass Most Significant Byte Register Description .........................................................80
Table 111. SWIZZLE Pass Least Significant Word Register Description ......................................................81
Table 112. SWIZZLE Pass Intermediate Significant Word Register Description ...........................................81
Table 113. SWIZZLE Pass Most Significant Word Register Description .......................................................81
Table 114. SWIZZLE Barrel Shift Register Description ..................................................................................81
Table 115. Examples of the Data Manipulations Supported by the SWIZZLE Module ..................................82
Table 116. RTC Upper Data Word Description ..............................................................................................84
Table 117. RTC Lower Data Word Description ..............................................................................................84
Table 118. Watchdog Reset Count Register Description ...............................................................................84
Table 119. Watchdog Reset Enable Register Description .............................................................................84
Table 120. Control/Status Register Description .............................................................................................85
Table 121. CDSYNC Data Register Description ............................................................................................86
Table 122. CDSYNC Word Count Register Description .................................................................................86
Table 123. CDSYNC Current Position Register Description ..........................................................................86
Table 124. CDSYNC Modulo Register Description ........................................................................................86
Table 125. CDSYNC Base Address Register Description .............................................................................87
Table 126. Reed Solomon Control Status Registers Description ...................................................................87
Table 127. Reed Solomon Error Offset Register Description .........................................................................88
Table 128. Reed Solomon Word Count Register Description ........................................................................88
Table 129. Reed Solomon Current Position Register Description .................................................................88
Table 130. Reed Solomon Modulo Register Description ...............................................................................89
Table 131. Reed Solomon Base Address Register Description .....................................................................89
Table 132. Reed Solomon Parity Base Address Register Description ...........................................................89
Table 133. Reed Solomon Span Register Description ...................................................................................89
Table 134. CDI Control CSR Clock Polarity ...................................................................................................92
Table 135. Interrupt Conditions ......................................................................................................................94
Table 136. CDI Pin Mapping Examples .........................................................................................................95
Table 137. CD-DSP Interface Control Unit Control Status Register Description ...........................................96
Table 138. CDI Control Port Timer Register Description ...............................................................................96
Table 139. CDI Time Base Register Description ............................................................................................97
Table 140. Control Unit Data Register Description ........................................................................................97
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Table 141. CDI Pin Configuration Register Description .................................................................................97
Table 142. CD-DSP Interface Serial Input Control Status Register Description ............................................98
Table 143. Serial Input Time Base Register Description ................................................................................98
Table 144. Serial Input Timer Register Description ........................................................................................99
Table 145. Serial Input Data Register Description .........................................................................................99
Table 146. Receive Status I2S Control Register Description .......................................................................101
Table 147. Receive Status I2S DataI0 Register Description ........................................................................102
Table 150. Transmit Status I2S Control Register Description ......................................................................103
Table 151. Transmit Status I2S DataI0 Register Description .......................................................................104
Table 154. SAI interrupts and Priorities .......................................................................................................105
Table 155. Trace Buffer Configuration Register Description ........................................................................107
Table 156. Trace Buffer base address register Description .........................................................................107
Table 157. Trace Buffer modulus address register Description ...................................................................108
Table 158. Trace Buffer Current Address Register Description ...................................................................108
Table 159. Trace Buffer Mask Registers Description ...................................................................................108
Table 160. Trace Buffer Trigger Command Status Register Description .....................................................108
Table 161. Trace Buffer Trigger Value Register Description ........................................................................109
Table 162. GPIO Enable Register Description .............................................................................................112
Table 163. GPIO Data Out Register Description ..........................................................................................112
Table 164. GPIO Data In Register Description ............................................................................................112
Table 165. GPIO Data Out Enable Register Description .............................................................................112
Table 166. GPIO Interrupt Pin Enable Register Description ........................................................................113
Table 167. GPIO Interrupt Enable Register Description ..............................................................................113
Table 168. GPIO Interrupt Level Register Description .................................................................................113
Table 169. GPIO Interrupt Polarity Register Description ..............................................................................114
Table 170. GPIO Interrupt Options Table ....................................................................................................114
Table 171. GPIO Interrupt Status Register Description ...............................................................................114
Table 172. GPIO Pin Power Register Description ........................................................................................114
Table 173. GPIO Pin Drive Strength Register Description ...........................................................................115
Table 174. GPIO0 Pin Register (Bank 0) Description ..................................................................................115
Table 178. DAC Base Address Register Description ...................................................................................119
Table 179. DAC Modulo Register Description ..............................................................................................120
Table 180. DAC Current Position Register Description ................................................................................120
Table 181. DAC Word Count Register Description ......................................................................................120
Table 182. DAC Sample Rate Register Description .....................................................................................121
Table 183. Example values for the HW_DACSRR register ..........................................................................121
Table 184. DAC Control Status Register Description ...................................................................................122
Table 185. ADC Base Address Register Description ...................................................................................123
Table 186. ADC Modulo Register Description ..............................................................................................123
Table 187. ADC Current Position Register Description ................................................................................123
Table 188. ADC Word Count Register Description ......................................................................................124
Table 189. ADC Sample Rate Register Description .....................................................................................124
Table 191. ADC Control Status Register Description ...................................................................................125
Table 190. Example values for the HW_ADCSRR register ..........................................................................125
Table 192. Mixer Address Registers ............................................................................................................126
Table 193. Mixer Master Volume Register Description ................................................................................127
Table 194. Master Volume Register values .................................................................................................127
Table 195. Analog Mixer Volume Registers .................................................................................................128
Table 196. Mixer Microphone-In Volume Register Description ....................................................................128
Table 197. Mixer Line-In Volume Register Description ................................................................................129
Table 198. Mixer Line-in 2 Volume Register Description .............................................................................129
Table 199. DAC In Volume Register Description .........................................................................................129
Table 200. Mixer Record Select Register Description ..................................................................................130
Table 201. ADC Select Register ..................................................................................................................130
Table 202. Mixer ADC Gain Register Description ........................................................................................130
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Table 203. ADC Gain Register .....................................................................................................................130
Table 204. Mixer Power Down Control/Stat Register Description ................................................................131
Table 205. Power Down Register ................................................................................................................131
Table 206. Codec/Mixer Test Register Description ......................................................................................131
Table 207. Reference Control Register Description .....................................................................................133
Table 208. Headphone Control Register Description ...................................................................................134
Table 209. Low Resolution ADC Control Register Description ....................................................................136
Table 210. Low Resolution ADC Result Register Description ......................................................................137
Table 211. Boot Control Pins .......................................................................................................................138
Table 212. Boot Modes in Current Silicon Revision .....................................................................................138
Table 213. Command Header + Data ..........................................................................................................139
Table 214. Memory Control Bits ...................................................................................................................140
Table 215. Decode of the Three DC-DC Mode Select Pins .........................................................................148
Table 216. DCDC1 Control Register A Description ......................................................................................155
Table 217. DCDC1 Control Register B Description ......................................................................................156
Table 218. DCDC2 Control Register A Description ......................................................................................156
Table 219. DCDC2 Control Register B Description ......................................................................................157
Table 220. DC-DC VddIO Control Register Description ...............................................................................158
Table 221. DC-DC VddD Control Register Description ................................................................................158
Table 222. DC-DC VddA Control Register Description ................................................................................159
Table 223. DC-DC Test Bit Register Description .........................................................................................159
Table 224. STMP3410 Pin Definitions Table ...............................................................................................162
Table 225. Analog Pins (CODEC Module) ...................................................................................................167
Table 226. DCDC Converter Pins ................................................................................................................167
Table 227. External Memory Interface - CompactFlash Pins (EMC-CF Module) .........................................167
Table 228. External Memory Interface - SmartMedia Pins (EMC-SM Module) ............................................168
Table 229. General Purpose Input/Output Pins ...........................................................................................169
Table 230. I2C Interface Pins .......................................................................................................................170
Table 231. I2S Interface Pins .......................................................................................................................170
Table 232. Power Pins .................................................................................................................................170
Table 233. SDRAM Interface Pins ...............................................................................................................171
Table 234. SPI Interface Pins ......................................................................................................................172
Table 235. System Pins ...............................................................................................................................172
Table 236. USB Interface Pins .....................................................................................................................172
Table 237. Notes on Pin Placement and Definitions ....................................................................................172
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2.
PRODUCT OVERVIEW
2.1.
Features
• Decodes MP3, WMA, AAC and is upgradeable to other digital music formats
• Supports WMA digital rights management and other security schemes
• NAND Flash, SmartMedia, MMC, Secure Digital, CompactFlash, SDRAM, CD and
IDE Support
• Flexible, efficient on-chip DC-DC converter
• Designed for greater than 35 hours of operation on a single AA battery
• Designed to operate from many different battery configurations, including 1xAA,
1xAAA, 2xAA, 2xAAA, LiIon
• USB download interface
• LED/LCD Driver
• GPIO and button I/O controls
• Voice record in ADPCM format
• Volume control on record and playback
• Full analog mixer configuration
• >90 dB THD headphone driver, including anti-pop and short-circuit protection
• High performance 18-bit Σ∆ technology
• Line-in to Line-out SNR >95 dB
• Mac and Windows download drivers
• Interface to a host chip/processor (optional)
• Upgradeable firmware
• DSP maximum speed is 65 MHz
• Energy saving dynamic power management
• Bass and Treble control; configurable multiple band control
• FM radio input and control support
• Three analog line-level inputs: Line_In (stereo), FM_In (stereo), and Mic (mono)
• Offered in 100-pin TQFP, 144-pin TQFP, and 144-pin fpBGA packages
2.2.
Description
SigmaTel's STMP3410 is a second generation single-chip highly-integrated digital music
system solution for devices such as dedicated audio players, PDAs, and cell phones. It
includes an audio decoder with a high performance DSP, ADPCM record capabilities
and a USB interface for downloading music and uploading voice recordings. STMP3410
also provides an interface to a CD pickup, flash memory, LED/LCD, button and switch
inputs, headphones, microphone, and FM radio input and control. The STMP3410’s
programmable architecture supports the MP3, WMA, and other digital audio standards.
WMA digital rights management and other security schemes are also supported. The
end-user can download music and also update the software on the STMP3410 through
a USB interface. For devices like PDAs and cell phones, STMP3410 can act as a slave
chip to a host chip/processor. The STMP3410 has low power consumption to allow long
battery life and an efficient flexible on-chip DC-DC converter that allows many different
battery configurations, including 1xAA, 1xAAA, 2xAA, 2xAAA and LiIon. The DACs
include a headphone driver to directly drive low impedance headphones. The ADCs
include inputs for both Microphone and Analog Audio In to support voice recording and
FM radio integration features. SigmaTel's proprietary Sigma-Delta (Σ∆) technology
achieves a DAC SNR in excess of 95 dB. STMP3410 supports the Secure Digital Music
Initiative (SDMI) and other digital content copy protection schemes.
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2.3.
Additional Documentation
Additional documentation and information is available from SigmaTel, including
SDK, reference designs, sample BOM, etc.
2.4.
STMP3410 Block Diagram
90
94
98
102
10
6
FM Radio
SPI ROM/
MMC Flash
I2C
Peripherals
SmartMedia
CompactFlash
NOR Flash
NAND Flash
Hard Drive
SDRAM
I2S
I2S CD
CD
Synchronization
Synchronization
Memory Bus
Peripheral Bus
STMP3410
Boost
DAC
6
SPI
SPI Interface
Interface
DAC
DAC
DSP
DSP
I2C
I2C Interface
Interface
Headphone Amplifier
Amplifier
Headphone
LED/LCD
Buttons/
Switches
General Purpose
Purpose Input/Output
Input/Output
General
CDROM
FM in
Interrupt
InterruptControl,
Control,Timers,
Timers,Bit
Bit
Manipulation
ManipulationUnit,
Unit,RTC,
RTC,Trace
Trace
Debug
Unit,
Reed-Solomon
Debug Unit, Reed-Solomon
USB
USB
Line in
CD
CD Control
Control
Interface
Interface
Mic in
Microphone
USB Bus
Headphones
ADC
ADC
EMC
EMC
SDRAM
SDRAM
Interface
Interface
On-Chip
On-Chip ROM
ROM
8K
8K xx 24bits
24bits
On-Chip
On-Chip RAM
RAM
96K
96K xx 24bits
24bits
DCDC
DCDC
Converter
Converter
Low
Low
Resolution
Resolution
ADC
ADC
PLL
PLL
XTAL
xtal
Battery
Crystal
Figure 1. STMP3410 Block Diagram
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3.
CHARACTERISTICS/SPECIFICATIONS
3.1.
Absolute Maximum Ratings
PARAMETER
SYMBOL
Ambient operating temperature
Storage temperature
Analog supply voltage
Digital supply voltage
I/O Supply
Input voltage on any pin relative to ground
MIN
MAX
UNITS
-10
-40
-0.3
-0.3
-0.3
-0.3
70
125
1.98
1.98
3.6
Vdd+0.3
°C
°C
V
V
V
V
Table 1. Absolute Maximum Ratings
3.2.
Recommended Operating Conditions
PARAMETER
SYMBOL
Ambient temperature
Digital core supply voltage – VddD1, VddD2, VddD3 (Note 1)
Specification dependent on DSP frequency
Digital I/O supply voltage – VddIO1, VddIO2
Analog supply voltage – VddA1, VddA2, Vddpll, Vddh
Specification dependent on maximum output power
Battery startup input voltage in 1xAA or 1xAAA mode
Full Scale Input Voltage:
Line Inputs
Mic Inputs
With 20 dB boost
Without 20 dB boost
Full Scale Output Voltage:
Headphone/Line Outputs (Vdd = 1.8 V)
Headphone/Line Outputs (Vdd = 1.55 V)
Signal-to-noise ratio of line input (Note 2)
Crosstalk between input channels
Total harmonic distortion (16Ω headphone at 1 Khz)
Analog line input resistance (Note 3)
Microphone input resistance
Analog output resistance
DAC SNR Idle Channel (Note 4)
DAC dynamic range (Note 4)
Line SNR (Note 4)
Line SNR idle channel (Note 4)
MIN
TYP
MAX
UNITS
-10
1.55
-
70
1.98
°C
V
2.9
1.55
2.9
-
3.6
1.80
V
V
0.9
-
-
V
-
0.6
0.1
0.06
0.6
-
Vrms
Vrms
85
90
-
0.57
0.42
90
-75
24
100
93
90
90
0.05
<1
-
Vrms
Vrms
dB
dB
%
kΩ
kΩ
Ω
dB
dB
dB
dB
Table 2. Recommended Operating Conditions
Note:
1. Recommended operating voltages for DCLK:
Speed
48 MHz
55 MHz
60 MHz
65 MHz
Vcore
1.55V
1.60V
1.70V
1.80V
Vbrownout
1.45V
1.50V
1.60V
1.70V (<=55ºC)
2. dB is relative to 0.6 Vrms.
3. Analog line input resistance changes with volume setting.
4. Measured “A weighted” over a 20 Hz to a 20 kHz bandwidth.
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4. MEMORY MAP
The STMP3410 includes 96 kwords of on-chip RAM (96k x 24 bits = 2.25 Mbits) that
is used for program and data storage, and 8 kwords of on-chip ROM (8k x 24 bits =
192kbits) that is used for the code that boots the device (see Section 20 for more
details on boot modes and the contents of the on-chip ROM). The on-chip ROM is
mapped at the address range P:$0000-$1FFF at reset, it can also be configured to
be mapped at address range P:$EFFF-$FFFF, or can be disabled to save power
and to free up this address range for on-chip RAM.
The on-chip RAM is organized into two banks of 48 kwords each, called PXRAM
and PYRAM. PXRAM can be mapped into the DSP P memory space, starting at
P:$0000, or into the DSP X memory space, starting at X:$0000. PYRAM can be
mapped into the DSP P memory space, starting immediately after the end of the
PXRAM memory, or into the DSP Y memory space, starting at Y:$0000. Both
PXRAM and PYRAM memory can be allocated to the DSP P, X or Y memory
spaces in 1k word increments, from a minimum of 0k words to all available memory.
The memory configuration is controlled by the PX & PY Memory Configuration registers documented below. There are no hardware safeguards against improper programming of these registers. It is possible to allocate less than all of the on-chip
RAM, unallocated memory will then be invisible to the DSP.
4.1.
PXRAM Configuration Register
HW_PXCFG
BITS
LABEL
23:14
13:8
RSRVD
PXXSIZE
R
RW
RW
0
011000
7:6
5:0
RSRVD
PXPSIZE
R
RW
0
011000
X:$FFE8
RESET
DEFINITION
Reserved
Number of kwords of PXRAM that is mapped in the DSP X memory
space.
Reserved
Number of kwords of PXRAM that is mapped in the DSP P memory
space.
Table 3. PXRAM Configuration Register Description
4.2.
PYRAM Configuration Register
HW_PYCFG
BITS
LABEL
RW
RESET
23:14
13:8
RSRVD
PYYSIZE
R
RW
0
011000
7:6
5:0
RSRVD
PYPSIZE
R
RW
0
011000
X:$FFE9
DEFINITION
Reserved
Number of kwords of PYRAM that is mapped in the DSP Y memory
space.
Reserved
Number of kwords of PYRAM that is mapped in the DSP P memory
space.
Table 4. PYRAM Configuration Register Description
The PXRAM bank is accessible to DSP P space accesses, DSP X space accesses,
and DMA accesses. The PYRAM bank is accessible to DSP P space accesses,
DSP Y space accesses, and DMA accesses. PXRAM & PYRAM are made up of 6
physical blocks of 8 kwords each for a total of 48 kwords each. Since the allocation
of to DSP P space, X space, & Y space is in 1 kword increments, it is possible for a
single physical memory block in the PXRAM bank to be accessed by the DSP P,
DSP X, and DMA bussess at the same time, similarily for the PYRAM bank. When
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this happens, the memory interface control logic steals one or more clock cycles
from the DSP to allow all of the accesses to complete in separate clock cycles. In
case of conflict, DMA accesses take priority over DSP accesses, and DSP program
accesses take priority over DSP data accesses.
It is possible to elminate cycle steals because of DSP P space and DSP X or Y conflicts by allocating PXRAM & PYRAM in increments of 8 kwords, this means that
each physical memory block is allocated to DSP P, X or Y space. It is not possible
to eliminate cycle steal that happen because a DMA access conflicts with a DSP
access to memory. In order to allow the programmer to monitor that cycle steals are
happening, the contents of the Cycle Steal Count Register (HW_CYCSTLCNT) is
incremented whenever a cycle is stolen for a memory access conflict.
Figure 3 below shows an example of how the PXRAM and PYRAM memory banks
can be allocated. In this example, PXRAM is allocated as 22 kwords P, & 26 kwords
X, and PYRAM is allocated as 18 kwords P, & 30 kwords Y, for a total of 40 kwords
of P, 26 kwords of X, and 30 kwords of Y.
PXMEM
PYMEM
X:$0000
Y:$0000
X:$2000
Y:$2000
X:$4000
Y:$4000
X:$6000
X:$67FF
P:$57FF
Y:$6000
8 kwords
instance
8 kwords
instance
48 kwords
total per
memory
bank
26 kwords
X memory
from PXRAM
30 kwords
Y memory
from PYRAM
8 kwords
instance
8 kwords
instance
8 kwords
instance
P:$4000
Y:$77FF
P:$9FFF
P:$9800
P:$2000
P:$7800
P:$0000
P:$5800
22 kwords
P memory
from PXRAM
18 kwords
P memory
from PYRAM
8 kwords
instance
Figure 3. Memory Organization
When the memory is configured as shown in Figure 3, the DSP’s view of the memory map will be as shown below in Figure 4. The DSP P address space has
40kwords of RAM as shown in the range P:$0000 to P:$9FFF. If the ROM is
enabled then it appears in the DSP P address space at P:$E000 to P:$FFFF. The
DSP X space has 26kwords of RAM at X:$0000 to X:$67FF, likewise the DSP X
space has 30kwords of RAM at Y:$0000 to Y:$77FF. The address ranges P:$A000
to P:$DFFF, X:$6800 to X:$EFFF, and Y:$7800 to Y:$FFFF are not populated with
any memory. The address range P:$E000 to P:$FFFF is unpopulated if the ROM is
not enabled. The address range X:$F000 to X:$FFFF is reserved for on-chip peripherals.
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In the above example memory configuration, it is possible for cycle steals to happen
because of either DSP access conflicts, or because of DMA access conflicts. The
areas in the memory map where DSP access conflicts can occur are shown in gray
in both Figure 3 & Figure 4. If the DSP attempts to access an address in the range
P:$4000 to P:$57FF at the same time as an address in the range X:$6000 to
X:$67FF, a stall cycle will occur. If the DSP attempts to access an address in the
range P:$9800 to P:$9FFF at the same time as an address in the range Y:$6000 to
Y:$77FF, a stall cycle will also occur.
DSP
P space
DSP
X Space
X:$FFFF
P:$FFFF
DSP
Y space
X:$FFFF
Peripherals
8 kwords
from PROM
X:$F000
P:$E000
not
populated
not
populated
not
populated
P:$9FFF
P:$9800
P:$97FF
64 kwords
total
18 kwords
P:$7800
from PYMEM P:$77FF
Y:$77FF
X:$67FF
X:$6000
X:$5FFF
Y:$6000
Y:$5FFF
P:$5800
P:$57FF
P:$4000
P:$3FFF
X:$4000
X:$3FFF
26 kwords
from PXMEM
22 kwords
from PXMEM
Y:$4000
30 kwords Y:$3FFF
from PYMEM
P:$2000
P:$1FFF
X:$2000
X:$1FFF
Y:$2000
Y:$1FFF
P:$0000
X:$0000
Y:$0000
Figure 4. DSP Memory Map
It is possible to reallocate on-chip RAM at any time, however doing so is dangerous
and should be done carefully. In particular, the DSP P space memory that is allocated from the PYMEM memory bank will move within address space if the allocation of PXRAM memory is changed.
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4.3.
On-Chip Memory Configuration Register
HW_RAM_ROM_CFG X:$FFED
BITS
LABEL
RW RESET
DEFINITION
23:22 RSRVD
R
Reserved.
21
PYRAM_CLK_EN RW 1
PYRAM Clock Enable. This bit enables or disables the clock to the PYRAM
embedded test and repair (ETR) engine. This clock should be turned off in almost
all circumstances to save power. It must be turned on for the correct operation of
the PYRAM ETR engine. The reset value of this bit is 1, but the bit will be turned
off by the boot code in the on-chip ROM in almost all circumstances.
0 = Disable clock for the PYRAM ETR engine
1 = Enable clock for the PYRAM ETR engine
20
PXRAM_CLK_EN RW 1
PXRAM Clock Enable. This bit enables or disables the clock to the PXRAM
embedded test and repair (ETR) engine. This clock should be turned off in
almost all circumstances to save power. It must be turned on for the correct
operation of the PXRAM ETR engine. The reset value of this bit is 1, but the
bit will be turned off by the boot code in the on-chip ROM in almost all
circumstances.
0 = Disable clock for the PXRAM ETR engine
1 = Enable clock for the PXRAM ETR engine
19
ROM_IMAGE_
RW 1
PROM Clock Enable. This bit enables or disables the clock to the on-chip
ENABLE
ROM. This clock should be turned off to save power if the ROM is not being
used. It must be turned on for the correct operation of the on-chip ROM.
0 = Disable clock for the on-chip ROM
1 = Enable clock for the on-chip ROM
18
PROMIE
RW 1
PROM Image Enable. After reset, the on-chip ROM is located at the address
range P:$0000..$1FFF. Once the bootloader in the ROM clears the MODEA bit
in the Operating Mode Register (HW_OMR), this address range reverts to onchip RAM. This mode bit enables the contents of the ROM to be viewed at the
address range P:$E000..$FFFF, irrespective of the state of the MODEA bit of
the Operating Mode Register. Since this address range can also be used by onchip RAM, it is necessary to be able to disable the ROM in this address range.
0 = Disable P:$E000..$FFFF image for on-chip ROM
1 = Enable P:$E000..$FFFF image for on-chip ROM
17
RAMTEST1
RW 0
Virage RAM TEST1. This register is used to select the TEST1 mode for the
on-chip RAM. This is a test mode that should not be used in normal operation.
0 = Disable TEST1 mode
1 = Enable TEST1 mode
16
RAMAWT
RW 0
RAM AWT Mode. This register is used to select the asynchronous write
through (AWT) mode for the on-chip RAM. This is a test mode that should not
be used in normal operation.
0 = Disable AWT mode
1 = Enable AWT mode
15:12 RAMRM
RW 0000
RAM Read Margin. This register is used to optimize the read performance of
all of the on-chip RAM. The optimum value of this register will be determined
by SigmaTel, and should not be modified.
11:8 PROMCT
RW 1000
PROM clock tune. This register is used to optimize the placement of the clock
to the on-chip ROM. The optimum value of this register will be determined by
SigmaTel, and should not be modified.
7:4
PYRAMCT
RW 1000
PYRAM Clock Tune. This register is used to optimize the placement of the
clock to the PYRAM block. The optimum value of this register will be
determined by SigmaTel, and should not be modified.
3:0
PXRAMCT
RW 1000
PXRAM Clock Tune. This register is used to optimize the placement of the
clock to the PXRAM block. The optimum value of this register will be
determined by SigmaTel, and should not be modified.
Table 5. On-Chip Memory Configuration Register Description
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5.
DSP CORE
The STMP3410 DSP core is modeled exactly after the Motorola DSP56004. It supports the identical instruction set, registers, addressing modes, etc., as the
DSP56000 family of digital signal processors. Figure 5 shows the DSP architecture.
For general information about the DSP56000 family, refer to the Motorola
DSP56000 Digital Signal Processor Family Manual.
The functionality that defines the STMP3410 DSP, is the memory map, interrupt processing, and peripherals it offers.
DSP Core
Debug Interface
Program
Address
Generator
To/from
P space
Address Generation Unit
R0
R1
N0
N1
M0
M1
R2
N2
M2
R3
N3
M3
R4
R5
N4
N5
M4
M5
R6
N6
M6
R7
N7
M7
ProgramDecoder
Instruction Latch
DATA ALU
X0
Bit Manipulation
Unit
Y1
Address to
Y space
Data to/from
X space
x
Decoder
&
State Machines
Registered Control
Y0
X1
Address to
X space
+
A
B
Interrupt
Controller
Data to/from
Y space
Interrupts
Figure 5. DSP Architechure
5.1.
Revision Register
The Revision Register reports the Device ID and revision to the software. This register is read only. The organization of the Revision Register is shown below.
HW_REVR
BITS LABEL RW
23:8
RMJ
R
7
RMP
R
6:0
RMN
R
RESET
X:$FA02
DEFINITION
$3410
Revision Major ID. This is the device part number in binary coded decimal:
STMP3410$3410
depends on DCDC DCDC mode/package type
configuration
0 – DCDC is configured in one of the modes that are only supported in a
144-pin package, therefore this device must be in a 144-pin package.
1 – DCDC is configured one of the modes that are supported in both
100-pin and 144-pin packages, therefore no inference can be made
about whether the current package is a 144-pin or 100-pin package.
depends on silicon Revision Minor ID. Device revision number
revision
Rev A $00
Rev B $01, etc.
Table 6. Revision Register Description
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5.2.
Reset Control Register
The organization of the Reset Control Register is shown below.
HW_RCR
BITS
LABEL
RW RESET
23
SOVFL
R
0
22
SUNFL
R
0
21
IRQB2NMI RW 0
20
SOVFLEN
RW 0
19:16 SOVFLLVL RW 1111
15
SUNFLEN RW 0
14:11 SUNFLLVL RW 0000
10
NMI
R
1
9
IRQB
R
1
8
IRQA
R
1
7:4
SRST
RW 0000
3:0
STKLVL
R
0000
X:$FA01
DEFINITION
Stack Overflow Status Bit
This bit indicates that the current stack depth is equal to or greater than the value
of the SOVFLLVL Stack Overflow Interrupt Level field. This is set or cleared
independently of the SOVLLEN Stack Overflow Interrupt Enable field. In other
words, once set this bit can only be cleared by fixing the stack underflow event by
adding words to the stack.
Stack Underflow Status Bit
This bit indicates that the current stack depth is equal to or greater than the value
of the SUNFLLVL Stack Under Interrupt Level field. This is set or cleared
independently of the SUNFLEN Stack Underflow Interrupt Enable field. In other
words, once set this bit can only be cleared by fixing the stack underflow event by
adding words to the stack.
Redirect battery+VddD+VddIO Brownout Interrupt to NMI
0 battery+VddD+VddIO brownout interrupt on IRQB only
1 battery+VddD+VddIO brownout interrupt on IRQB & NMI
(see brownout Figure 38 for details)
Stack Overflow Interrupt Enable
0 Stack overflow interrupt disabled
1 Stack overflow interrupt enabled
Stack Overflow Interrupt Level
Stack Underflow Interrupt enable
0 Stack underflow interrupt disabled
1 Stack underflow interrupt enabled
Stack Underflow Interrupt Level
NMI Interrupt
An NMI interrupt will be generated by a stack over-/underflow event. If the IRQB2NMI
control bit above is set, an NMI interrupt will also be generated when a brownout event
is detected. This bit will be cleared by hardware when a DSP hardware stack over- or
underflow is detected. A falling edge on this bit causes an NMI interrupt in the DSP.
0 Stack over-/underflow (or brownout if the IRQB2NMI bit is set) detected
1 No Stack over-/underflow (or brownout if the IRQB2NMI bit is set) detected
IRQB Interrupt
An IRQB interrupt will be generated when a brownout event is detected. This bit will
be cleared by hardware to indicate that a brownout event has been detected.
0 Brownout detected
1 No brownout detected
IRQA Interrupt
An IRQA interrupt will be generated when a headphone short is detected. This bit will
be cleared by hardware to indicate that a headphone short event has been detected.
0 Headphone short detected
1 No headphone short detected
Writing 1101 will cause a full chip hardware reset, writing any other value will have
no effect.
The current position of the DSP hardware stack.
Table 7. Reset Control Register Description
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Note that when the IRQB2NMI bit is set, the ISR that services the NMI will need to
do a few special things. When this bit is set, if both interrupts happen at the same
time, only one NMI will be received. Also, if one interrupt occurs while the other is
being serviced, a new NMI interrupt will not be triggered. The NMI routine will need
to check each possible NMI event and take appropriate action to clear the interrupt
event, and then recheck that all NMI interrupt sources are clear before returning. If
the NMI ISR returns with a NMI interrupt event still pending, that event (and all subsequent NMI interrupts) will be lost. Finally, the NMI ISR needs to be able to deal
with the case where no interrupt event is pending when the ISR checks it, since the
latency of the NMI interrupt is several cycles long, and the stack over-/underflow
could have been cleared by the time that the NMI runs. In fact, this is guaranteed to
happen in the case of the stack underflow interrupt, as the very fact of calling the
NMI will push items onto the stack.
We have implemented some timing measurement registers, to allow accurate code
profiling and cycle counting. There are three registers as follows:
5.3.
DCLK Count Lower Register
HW_DCLKCNTL
BITS
23:0
LABEL
X:$FFEA
RW RESET
HW_DCLKCNTL RW 0
DEFINITION
Counter incremented once per DSP clock cycle.
Table 8. DCLK Count Lower Register Description
5.4.
DCLK Count Upper Register
HW_DCLKCNTU
BITS
23:0
LABEL
X:$FFEB
RW RESET
HW_DCLKCNTU RW 0
DEFINITION
Counter incremented every time that the HW_DCLKCNTL counter overflows.
Table 9. DCLK Count Upper Register Description
5.5.
Cycle Steal Count Register
HW_CYCSTLCNT
BITS
23:0
LABEL
RW RESET
HW_CYCSTLCNT RW 0
X:$FFED
DEFINITION
Counter incremented every time a cycle is stolen from the DSP for DMA or
because of an access conflict in the RAMs
Table 10. Cycle Steal Count Register Description
The HW_DCLKCNTL & HW_DCLKCNTU registers together form a 48 bit cycle
counter that is incremented once per clock cycle. There is no hardware support for
reading and writing these registers synchronously, it is possible to read the lower
register before it wraps around, and then read the upper register after it has been
wrapped around, and get an erroneous value. Various software techniques can be
used to avoid this problem. The HW_DCLKCNTL & HW_DCLKCNTU registers are
incremented every clock cycle, including cycles that the DSP doesn’t see because
they are stolen for DMA accesses or because of an access conflict in the on-chip
RAMs. The HW_CYCSTLCNT register counts these cycles, and if you want to calculate the number of cycles actually seen by the DSP during a period of time, you
must subtract the number of stolen clock cycles by referring to this register.
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5.6.
Operating Mode Register
The organization of the operating mode register is shown below. The operating
mode register determines chip configuration including boot modes, and memory
configuration. The HW_OMR is a core register that is accessible by special DSP
instructions. It therefore has no address.
HW_OMR
BITS LABEL RW RESET
23:8
7
RSRVD R
MDLP RW 0
6
SD
5
4
RSRVD R
0
MC
RW 1
3
YD
RW 0
2
DE
RW 1
1
MB
RW 0
0
MA
RW 0
RW 0
DEFINITION
Reserved. Must be written as 0.
Low Power Mode. Writing a 0 to this bit enables some clock gating in the DSP core
that reduces its power consumption. This register must be written with a 1 for proper
operation of the debug functionality in the DSP.
Stop Delay. This bit is exported from the core as an output. It can be used when
waking up from the STOP low power standby mode. If this bit is set, then when an
IRQA interrupt occurs to wake up the core from the STOP state, the clock control
circuitry should wait a time period (e.g. 65536 clock cycles) before allowing the clocks
back in to the DSP core. This can be used, for example, to restablize a PLL clock
oscillator. If this bit has a zero value, then the clocks will be allowed back into the core
immediately after the occurrence of the IRQA interrupt, thus implementing a “warm
boot” from the STOP low power standby state.
Reserved
Operating Mode C. This bit may be used to configure different boot modes for the IC
which embeds the DSP core. When the hardware reset is active, this bit samples the
state of input pin. Once the boot code executes, it can check the state of this bit in
order to make decisions about what type of boot mode to perform.
Internal Y-Memory Disable. This bit is exported from the core as an output. It may be
used by address decode circuitry external to the core to mask off certain portions of
memory space. This bit has no effect in the STMP3410.
Data ROM Enable. This bit is exported from the core as an output. It may be used by
address decode circuitry external to the core to mask off certain portions of memory
space. This bit has no effect in the STMP3410.
Operating Mode B. This bit may be used to configure different boot modes for the IC
which embeds the DSP core. When the hardware reset is active, this bit samples the
state of the input pin. Once the boot code executes, it can check the state of this bit in
order to make decisions about what type of boot mode to perform.
Operating Mode A. This bit is used to choose between Boot ROM and Program
Memory for instruction fetches and read accesses. When this bit is set, as it is after
hardware reset, the Boot ROM space is activated and any fetches or read accesses to
the P: space will refer to the on-chip ROM. When this bit is a zero, the Program
Memory space is enabled instead of the Boot memory space and any fetch or read
access to P: space will refer to the on-chip RAM. Write accesses to P: space always
access the program RAM regardless of the state of the MA bit. It is not possible to
write to the program ROM.
Table 11. Operating Mode Register Description
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5.7.
Clock Control Register
Crystal
PWDN
DDIV
DCLK
PDIV
24.576 MHz
PLLEN
Real Time
Clock
CKSRC
PLL
Post
Divider
ACKEN
ADIV1
XTLEN
Clock to
DAC
DAC Divider
ADIV0
Clock to
ADC
ADC Divider
Figure 6. Clock Control Register (HW_CCR)
The Clock Control Register configures the system clock sources, including the Analog clock and PLL. It is also used to shut down system power by turning off the DCDC converter. Note that none of the bits in this register have any effect unless the
CLKRST bit (bit [0]) is set.
The digital clock can be set to nearly any value between 192 kHz and 77 MHz using
the PLL and post divider.
HW_CCR
X:$FA00
BITS LABEL RW RESET
DEFINITION
23
RSRVD R
Reserved. Must write as 0.
22:20 ADIV1 RW 000
Analog clock divider for DAC. Changes the clock rate used by the DAC. This is used
to scale down the frequencies used in the DAC when using audio sample rates less
than the maximum.
000 xtal/4 = 6.144 MHz = 128*Fssc = 128*48 kHz
001 xtal/6 = 4.096 MHz = 128*Fssc = 128*32 kHz
010 xtal/8 = 3.072 MHz = 128*Fssc = 128*24 kHz
011 xtal/12 = 2.048 MHz = 128*Fssc = 128*16 kHz
100 xtal/8 = 3.072 MHz = 128*Fssc = 128*24 kHz
101 xtal/12 = 2.048 MHz = 128*Fssc = 128*16 kHz
110 xtal/16 = 1.536 MHz = 128*Fssc = 128*12 kHz
111 xtal/24 = 1.024 MHz = 128*Fssc = 128*8 kHz
19
LOCK R
PLL lock status.
0
PLL not locked
1
PLL locked
18
ACKEN RW 0
Analog clock enable. This bit enables clocks to the analog circuitry portions of the
STMP3410. This bit must be set before using the DAC or ADC. In addition to this
mode bit, the ADC or DAC power down bits in the Mixer Power Down Control Status
Register must not be asserted for the ADC or DAC to operate.
0
Analog clocks disabled
1
Analog clocks enabled
17
PWDN RW 0
STMP3410 power-down.
0
STMP3410 powered up
1
Power down STMP3410
Table 12. Clock Control Register Description
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BITS LABEL RW RESET
DEFINITION
16:12 PDIV
RW 00000 PLL frequency divider. Assuming a 24.576 MHz crystal, the PLL can be programmed
in 1.2288 MHz steps, from a minimum frequency of 40.5504 MHz to a maximum
frequency of 78.6432 MHz. The reset value is 00000, which yields a PLL frequency of
40.5504 MHz. When used in combination with DDIV post-divider, it is possible to
reach frequencies below 40.5504 MHz with smaller granularities.
PLL output freq = (33 + PDIV) * (24.576 MHz/20)
11:9 DDIV
RW 000
Clock post-divider. The post divider can be programmed instantly, without switching
the digital clocks over to the crystal. To achieve the minimum power mode, select the
crystal as the source for the digital clocks (CKSRC=0), turn off the PLL (PLLEN=0),
and set this divider to the maximum divide rate. The digital clock will then be set to
24.576 MHz/128 = 192 kHz.
000 divide by 1
011 divide by 8
110 divide by 64
001 divide by 2
100 divide by 16
111
divide by 128
010 divide by 4
101 divide by 32
8
CKSRC RW 0
Clock source. This bit may only be set from 0 to 1 if the PLL is enabled and locked.
0
Digital clock generated from crystal
1
Digital clock generated from PLL
7:5
ADIV0 RW 000
Analog clock divider for ADC. Changes the clock rate used by the ADC. This is used
to scale down the frequncies used in the ADC when using audio sample rates less
than the maximum.
000 xtal/4 = 6.144 MHz = 128*Fssc = 128*48 kHz
001 xtal/6 = 4.096 MHz = 128*Fssc = 128*32 kHz
010 xtal/8 = 3.072 MHz = 128*Fssc = 128*24 kHz
011 xtal/12 = 2.048 MHz = 128*Fssc = 128*16 kHz
100 xtal/8 = 3.072 MHz = 128*Fssc = 128*24 kHz
101 xtal/12 = 2.048 MHz = 128*Fssc = 128*16 kHz
110 xtal/16 = 1.536 MHz = 128*Fssc = 128*12 kHz
111 xtal/24 = 1.024 MHz = 128*Fssc = 128*8 kHz
4
FLB
RW 0
Force lock bit (Test bit). Forces the lock bit output from the PLL.
0
Do nothing
1
Force lock bit output from PLL
3
XTLEN RW 0
Crystal clock enable. The crystal clock runs digital circuitry for the ADC & DAC. This
clock should be disabled when the ADC and DAC are not in use.
0
Crystal clock disabled
1
Crystal clock enabled
2
PLLEN RW 0
PLL enable
0
PLL disabled
1
PLL enabled
1
LTC
RW 0
Lock timer reset. Resets the PLL lock timer. Must be written as 0, then 1 to start the
PLL lock timer.
0
CKRST RW 0
Clock reset. Must be written as 1 for all writes to this register. If set to 0, the entire
clock logic block stays in its reset state.
Table 12. Clock Control Register Description (Continued)
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5.8.
Misc/Spare Register
The Misc/Spare Register is used for system updates (TBD as they are available). It
is used to detect the analog pswitch pin and the USB port/host connection, and is
used to configure the built-in resistor to initiate the USB process and to configure the
I2S pins onto alternate pins. The organization of the Misc/Spare Register is shown
below.
HW_SPARER
BITS
LABEL
X:$FA16
RW RESET
23:10 RSRVD
9
PSWITCH
R
R
0
8
USB_PLUGIN
R
7:2
SPARE BITS
RW 0
1
USB_SELECT RW 0
0
I2S_SELECT
DEFINITION
This bit indicates the state of the analog pswitch pin. Normally, this pin will be
a 1 when the power switch is pressed.
0
analog pswitch pin is 0
1
analog pswitch pin is 1
This bit detects if the USB port is plugged into a USB host. This bit is only
valid when the USB port is idle, before the USB enumeration process.
0
not plugged in
1
plugged in
These bits can be written or read normally but have no function in this revision
of the chip. In a future revision of the chip, we might use these bits to control
something.
This bit is used to configure the built in resistor in the USB pins that causes
the USB host to initiate the USB enumeration process.
0
Resistor disabled
1
Resistor enabled, will enable USB enumeration
This bit is used to switch the I2S functions onto alternate pins. One setting
allows a subset of the I2S functionality to be supported in a 100-pin package,
the other setting allows the full I2S functionality but is only supported in a 144pin package. (see 16.1. “I2S External Pins” on page 100.)
0
Subset of I2S functionality for 100-pin packages
1
Full I2S functionality for 144-pin packages
RW 0
Table 13. Misc/Spare Register Description
5.9.
Scratch Register
The Scratch Register contains bits that do not currently have a function.
HW_SCRATCH
BITS
23:11
9:0
LABEL
RW
RESET
X:$FA13
DEFINITION
RSRVD
R
0
SCRATCH RW 1011011011
Scratch bits. These bits are designated for bits not currenlty available.
Table 14. Scratch Register Description
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5.10. Interrupt Priority Register
The DSP core in the STMP3410 has seven main interrupt lines, IVL[6:0]. This register is used to enable each line and set its priority. Some peripherals connect directly
to this interrupt bus, but most interrupt sources go through the Interrupt collector,
which multiplexes many interrupt sources onto 4 interrupts on these 7 interrupt
lines.
If an interrupt with a higher priority level occurs while the DSP core is servicing
another interrupt, the higher priority interrupt will preempt the lower priority interrupt.
If the new interrupt is of the same or lower priority level, then it will not preempt the
interrupt that is currently being serviced.
HW_IPR
BITS LABEL RW RESET
23:22 L6P
21:20 L5P
19:18 L4P
17:16 L3P
15:14 L2P
13:12 L1P
11:10 L0P
RW 0
RW 0
RW 0
RW 0
RW 0
RW 0
RW 0
9:6
5
RSVD
IRQBT RW 0
4:3
IRQBP RW 0
2
IRQAT RW 0
1:0
IRQAP RW 0
X:$FFFF
DEFINITION
Interrupt line 6 priority level.
00 – Disabled
01 – Priority Level 0 (lowest priority level)
Interrupt line 5 priority level. SPI
00 – Disabled
Interrupt line 4 priority level. I2C
00 – Disabled
00 – Disabled
00 – Disabled
00 – Disabled
Interrupt line 0 priority level. I2S
00 – Disabled
Reserved. Must be written 0.
IRQB Type
0 – Level
1 – Neg. Edge
IRQB Priority Level
00 – Disable
01 – Enable
IRQA Type
0 – Level
1 – Neg. Edge
IRQA Priority Level
00 – Disable
01 – Enable
10 – Priority Level 1
11 – Priority Level 2 (highest priority level)
10 – Enable
11 – Enable
10 – Enable
11 – Enable
Table 15. Interrupt Priority Register Description
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5.11. Interrupt Collector
The STMP3410 provides seven interrupt lines, IVL[6:0], for individual interrupt
requests. The peripheral interrupt count exceeds the seven interrupt request lines,
so the Interrupt Collector (ICOLL) muxes all sources to the seven lines. Three of the
seven interrupt lines are reserved for certain peripherals, so the ICOLL steers 36
interrupt sources to four of the interrupt request lines: IVL[6,3,2,1]. Within an individual interrupt request line, the ICOLL offers an 8-level priority for each of it is interrupt
sources, although preemption of a lower priority interrupt by a higher priority is not
supported. If preemption is required, the interrupt source that needs to preempt
must be routed to a higher priority interrupt request line.
0
0
7
INT
Sources
HW_ICLPRIOR0R
(Priority Register)
HW_ICLENABLE0R
(Enable Register)
15
HW_ICLPRIOR1R
(Priority Register)
IVL6
IVL0
12
IVL4
IVL5
23
HW_ICLENABLE1R
(Enable Register)
IVL3
11
HW_ICLSTEER1R
(Steering Register)
16
24
.
.
.
30
IVL2
HW_ICLSTEER0R
(Steering Register)
8
0
.
.
.
23
IVL1
HW_ICLPRIOR2R
(Priority Register)
30
HW_ICLPRIOR3R
(Priority Register)
DSP
IRQA
IRQB
NMI
23
24
24
HW_IPR
(Enable and
Priority Control
Register)
HW_ICLSTEER2R
(Steering Register)
30
Figure 7. Interrupt Collector Diagram
Interrupt response time is dependent on the interrupt priority. The minimum interrupt
time is as follows:
•
•
28
2 clock cycles for interrupt to appear at DSP.
2 clock cycles to respond and get vector to execute interrupt service routine.
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5.11.1.
Interrupt Sources
Table 16 shows all the interrupt sources.
INTERRUPT SOURCE
DAC Refill
DAC Underflow
ADC Refill
ADC Overflow
Flash Done
CompactFlash Card IRQ
SmartMedia Timeout
SmartMedia Interface Invalid
Programming
CompactFlash No Card
CompactFlash Status Change
GPIO0
GPIO1
GPIO2
Timer0
Timer1
Timer2
Timer 3
GPIO3
SDRAM
CDI
USB Set Configuration Request
USB Set Interface Request
USB Host Reset
USB Endpoint 0
USB Endpoint 1
USB Endpoint 2
USB Endpoint 3
USB Endpoint 4
USB Endpoint 5
USB Endpoint 6
USB Endpoint 7
CDSync Interrupt
CDSync Exception
RS Interrupt
I2C Rx Ready
I2C Rx Overflow
I2C Tx Empty
I2C Tx Underflow
SPI Complete
I2S Rx Overflow
I2S Tx Underflow
I2S Rx Ready
I2S Tx Empty
SOURCE # IVL REQUEST INTERRUPT
DESCRIPTION
BIT #
VECTOR
0
6,3,2,1
$003C
DAC request to fill DAC FIFO buffer
1
6,3,2,1
$003E
DAC FIFO buffer underflow
2
6,3,2,1
$0042
ADC request to empty ADC FIFO buffer
3
6,3,2,1
$0044
ADC FIFO buffer overflow
4
6,3,2,1
$006E
Flash transaction complete
5
6,3,2,1
$0070
CompactFlash card interrupt
6
6,3,2,1
$0072
SmartMedia card WAIT timeout
7
6,3,2,1
$0074
Bad programming of SmartMedia interface
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
-
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
6,3,2,1
4
4
4
4
5
0
0
0
0
$0076
$0078
$001E
$0020
$0022
$0026
$0028
$002A
$0048
$004A
$004C
$007E
$0050
$0052
$0054
$0056
$0058
$005A
$005C
$005E
$0060
$0062
$0064
$0066
$0068
$006A
$0030
$0032
$0034
$0036
$000E
$0016
$0012
$0014
$0010
CompactFlash card remove/absence
CompactFlash card status change
GPIO module 0 interrupt
Timer module 0 interrupt
SDRAM interrupt
CDI interface interrupt
USB set configuration request
USB set interface request
USB host reset
USB endpoint 0
USB endpoint 1
USB endpoint 2
USB endpoint 3
USB endpoint 4
USB endpoint 5
USB endpoint 6
USB endpoint 7
CD synchronizer/formatter interrupt
CD synchronizer/formatter exception
Reed-Solomon error corrector interrupt
I2C receiver data ready
I2C receiver data overflow
I2C transmitter data empty
I2C transmitter data underflow
SPI transfer complete
I2S receiver data overflow
I2S transmitter data underflow
I2S receiver data ready
I2S transmitter data empty
Table 16. Interrupt Sources
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5.11.2.
Interrupt Vectors
Table 17 below shows the interrupt vectors used for each possible STMP3410 interrupt source.
ADDRESS
P:$003A
P:$003C
P:$003E
P:$0040
P:$0042
P:$0044
P:$0046
P:$0048
P:$004A
P:$004C
P:$004E
P:$0050
P:$0052
P:$0054
P:$0056
P:$0058
P:$005A
P:$005C
P:$005E
P:$0060
P:$0062
P:$0064
P:$0066
P:$0068
P:$006A
P:$006C
P:$006E
P:$0070
P:$0072
P:$0074
P:$0076
P:$0078
5.11.3.
INTERRUPT SOURCE
ADDRESS
INTERRUPT SOURCE
P:$007A
DAC Empty
P:$007C
DAC Underflow
P:$007E
CDI Interrupt
P:$0000
Hardware Reset
ADC Full
P:$0002
Stack Error
ADC Overflow
P:$0004
Trace
P:$0006
SWI
Timer 3
P:$0008
IRQA/Headphone Short Detect
GPIO3
P:$000A
IRQB/Battery Brownout Detect
SDRAM
P:$000C
P:$000E
SPI Complete
USB Configuration Request
P:$0010
I2S Tx Data Empty
USB Set Interface Request
P:$0012
I2S Tx Underflow
USB Host Reset
P:$0014
I2S Rx Data Full
USB Endpoint 0
P:$0016
I2S Rx Overflow
USB Endpoint 1
P:$0018
NMI
USB Endpoint 2
P:$001A
USB Endpoint 3
P:$001C
USB Endpoint 4
P:$001E
GPIO 0
USB Endpoint 5
P:$0020
GPIO 1
USB Endpoint 6
P:$0022
GPIO 2
USB Endpoint 7
P:$0024
CDSync Interrupt
P:$0026
Timer 0
CDSync Exception
P:$0028
Timer 1
RS Interrupt
P:$002A
Timer 2
P:$002C
Flash Done
P:$002E
CompactFlash Card IRQ
P:$0030
I2C Rx Data Ready
SmartMedia Timeout
P:$0032
I2C Rx Overflow
SmartMedia Invalid Programming P:$0034
I2C Tx Data Empty
CompactFlash No Card
P:$0036
I2C Tx Underflow
CompactFlash Status Change
P:$0038
Invalid DSP instruction
Table 17. Interrupt Vector Map
Interrupt Collector Registers
5.11.3.1.
ICOLL Enable 0 Registers
The enable registers provide bits to enable/disable interrupts for each source. Each
enable corresponds to a specific interrupt source listed in Table 16. A 1 enables the
relevant interrupt, a 0 disables the relevant interrupt.
HW_ICLENABLE0R
X:$F300
BITS
LABEL
RW RESET
DEFINITION
23:0 SEN23 : SEB0 RW 0
Table 18. ICOLL Enable 0 Register Description
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5.11.3.2.
ICOLL Enable 1 Registers
The enable registers provide bits to enable/disable interrupts for each source. Each
enable corresponds to a specific interrupt source listed in Table 16. A 1 enables the
relevant interrupt, a 0 disables the relevant interrupt.
HW_ICLENABLE1R
X:$F301
BITS
LABEL
RW RESET
DEFINITION
23:10 RSRVD
Reserved
9:0
SEN33 : SEN24 RW 0
Table 19. ICOLL Enable 1 Register Description
5.11.3.3.
ICOLL Status 0 Registers
The status registers reflect the interrupt state of each source. Each enable corresponds to a specific interrupt source listed in Table 16. A 1 indicates an active interrupt, a 0 indicates an inactive interrupt. This register is read only.
HW_ICLSTATUS0R
X:$F302
BITS
LABEL
RW RESET
DEFINITION
23:0 SST23 : SST0 R
Table 20. ICOLL Status 0 Register Description
5.11.3.4.
ICOLL Status 1 Registers
The status registers reflect the interrupt state of each source. Each enable corresponds to a specific interrupt source listed in Table 16. A 1 indicates an active interrupt, a 0 indicates an inactive interrupt. This register is read only.
HW_ICLSTATUS1R
X:$F303
BITS
LABEL
RW RESET
23:10 RSRVD
R
0
Reserved
9:0
SST33 : SST24 RW 0
DEFINITION
Table 21. ICOLL Status 1 Register Description
5.11.3.5.
ICOLL Priority 0 Registers
The priority registers set the priority for each source. Each enable corresponds to a
specific interrupt source listed in Table 16. Lowest priority is 111 and highest is 000.
HW_ICLPRIOR0R
BITS
23:21
20:18
17:15
14:12
11:9
8:6
5:3
2:0
LABEL
S7P
S6P
S5P
S4P
S3P
S2P
S1P
S0P
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESET
0
0
0
0
0
0
0
0
X:$F304
DEFINITION
Table 22. ICOLL Priority 0 Register Description
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5.11.3.6.
HW_ICLPRIOR1R
BITS
23:21
20:18
17:15
14:12
11:9
8:6
5:3
2:0
LABEL
S15P
S14P
S13P
S12P
S11P
S10P
S9P
S8P
RW
RW
RW
RW
RW
RW
RW
RW
RW
X:$F305
RESET
0
0
0
0
0
0
0
0
DEFINITION
5.11.3.7.
HW_ICLPRIOR2R
BITS
23:21
20:18
17:15
14:12
11:9
8:6
5:3
2:0
LABEL
S23P
S22P
S21P
S20P
S19P
S18P
S17P
S16P
RW
RW
RW
RW
RW
RW
RW
RW
RW
X:$F306
RESET
DEFINITION
0
0
0
0
0
0
0
0
5.11.3.8.
HW_ICLPRIOR3R
BITS
23:21
20:18
17:15
14:12
11:9
8:6
5:3
2:0
32
LABEL
S31P
S30P
S29P
S28P
S27P
S26P
S25P
S24P
RW
RW
RW
RW
RW
RW
RW
RW
RW
X:$F307
RESET
DEFINITION
0
0
0
0
0
0
0
0
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STMP3410
5.11.3.9.
HW_ICLPRIOR4R
BITS
23:6
5:3
2:0
LABEL
RSRVD
S33P
S32P
RW
X:$F311
RESET
DEFINITION
Reserved
RW
RW
0
0
5.11.3.10. ICOLL Steering 0 Registers
The steering registers are used to steer a given source to a given IVL as follows:
SETTING
00
01
10
11
IVL
1
2
3
6
Each steering value corresponds to a specific interrupt source listed in Table 17.
HW_ICLSTEER0R
BITS
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
LABEL
S11S
S10S
S9S
S8S
S7S
S6S
S5S
S4S
S3S
S2S
S1S
S0S
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RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESET
X:$F308
DEFINITION
0
0
0
0
0
0
0
0
0
0
0
0
Table 27. ICOLL Steering 0 Register Description
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SETTING
00
01
10
11
IVL
1
2
3
6
HW_ICLSTEER1R
BITS
23:22
21:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
LABEL
S23S
S22S
S21S
S20S
S19S
S18S
S17S
S16S
S15S
S14S
S13S
S12S
RW
X:$F309
RESET
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFINITION
0
0
0
0
0
0
0
0
0
0
0
0
SETTING
00
01
10
11
IVL
1
2
3
6
HW_ICLSTEER2R
BITS
23:20
19:18
17:16
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
LABEL
RSRVD
S33S
S32S
S31S
S30S
S29S
S28S
S27S
S26S
S25S
S24S
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
X:$F30A
RESET
0
0
0
0
0
0
0
0
0
0
0
DEFINITION
Reserved
34
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5.11.4.
Interrupt Collector Debug Registers
5.11.4.1.
ICOLL Debug Force 0 Registers
The debug force value registers will force an interrupt for a given source. The
enable registers enable the forcing mechanism. Each enable corresponds to a specific interrupt source listed in Table 16.
HW_ICLFORCE0R
BITS
23:0
LABEL
X:$F30B
RW RESET
DEFINITION
S23FV : S0FV RW 0
Table 30. ICOLL Force Value 0 Register Description
5.11.4.2.
ICOLL Debug Force 1 Registers
The debug force value registers will force an interrupt for a given source. The
enable registers enable the forcing mechanism. Each enable corresponds to a specific interrupt source listed in Table 16.
HW_ICLFORCE1R
BITS
LABEL
X:$F30C
RW RESET
23:10 RSRVD
9:0
S33FV : S24FV
DEFINITION
Reserved
Table 31. ICOLL Force Value 1 Register Description
5.11.4.3.
ICOLL Force Enable 0 Registers
To generate a forced interrupt you have to write a 1 into the relevant position in both
the force and force enable registers. Writing a 1 to the force enable register will
block any interrupts from the normal interrupt source for the relevant bit. Each force
bit corresponds to a specific interrupt source listed in Table 16.
HW_ICLFENABLE0R X:$F30D
BITS
23:0
LABEL
RW RESET
DEFINITION
S23FE : S0FE RW 0
Table 32. ICOLL Force Enable 0 Register Description
5.11.4.4.
ICOLL Force Enable 1 Registers
To generate a forced interrupt you have to write a 1 into the relevant position in both
the force and force enable registers. Writing a 1 to the force enable register will
block any interrupts from the normal interrupt source for the relevant bit. Each force
bit corresponds to a specific interrupt source listed in Table 16.
HW_ICLFENABLE1R X:$F30E
BITS
LABEL
23:10 RSRVD
9:0
S33FE : S24FE
RW RESET
DEFINITION
Reserved
RW 0
Table 33. ICOLL Force Enable 1 Registers Description
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5.11.4.5.
ICOLL Observation Registers (HW_ICLOBSV0R/1R)
The observation registers make visible the state of the interrupt request vector that
the icoll is sending out on IVL[6:0] and the winning (prioritized) interrupt vectors for
destinations A, B, C, and D.
A IVL1
B IVL2
C IVL3
D IVL6
Each observation bit corresponds to a specific interrupt source listed in Table 16.
This register is read only and is primarily for debug purposes.
5.11.4.5.1.
Interrupt Collector Observe 0 Register
HW_ICLOBSVZ0R
BITS
23:21
20:14
13:7
6:0
LABEL
RSRVD
IVB
IVA
REQ
X:$F30F
RW RESET
DEFINITION
Reserved
R
R
R
Table 34. ICOLL Observe 0 Register Description
5.11.4.5.2.
Interrupt Collector Observe 1 Register
HW_ICLOBSVZ1R
BITS
23:14
13:7
6:0
LABEL RW RESET
RSRVD
Reserved
IVD
R
IVC
R
X:$F310
DEFINITION
Table 35. ICOLL Observe 1 Register Description
5.12. General Debug Register
The HW_GDBR Register is also mapped into the X Peripheral I/O space. This register is used as a gateway between the DSP and the Debug port. For instance, when
displaying the states of the internal registers and memory of the DSP core, the DSP
moves the data to this register and the data is then shifted out the DBOUT line to the
emulator. The HW_GDBR register operation is controlled automatically by the emulator and the debug circuitry within the core. An added feature of the Debug Unit is
that the emulator cannot access the debug unit unless a write to the HW_GDBR
Register is executed by the DSP (normally in the boot code).
HW_GDBR
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STMP3410
6.
USB INTERFACE
The STMP3410 incorporates a Universal Serial Bus (USB) version 1.1 interface.
The USB interface is used to download digital music data or program code into
external memory and to upload voice recordings from memory to the PC. Program
updates can also be loaded into the flash memory area using the USB interface.
6.1.
USB Interface Registers
The USB interface is a dynamically configurable port. It contains six physical endpoints and thirty two logical endpoints, each of which may be configured to be bulk,
interrupt, or isochronous. Each endpoint location in memory is also configurable by
the system when the USB is enabled. The mode for each of these endpoints is
determined by the configuration data that is provided to the USB interface through
the USB Configuration Base Address Register (HW_USBCBAR). The USB interface also supports Class/Vendor commands which is accessed through the control
endpoint 0. The USB EP0 Address Pointer Register allows the system to define the
memory address of the read/write data.
The STMP3410 USB port supports a single configuration, seven interfaces, and
eight endpoints (EP0-7). The Default Pipe is always attached to EP0 and is used for
USB configuration and control data transfers. EP7 is reserved for special handling
of the GetDescriptor message, so there are six general-use endpoints
6.1.1.
USB Endpoint 0 Address Pointer Registers
The Ap15-0 bits of the HW_USBEP0PTRR specify the base address in X memory
of where the Endpoint 0 buffer will be located by software. The USB interface uses
this address location to write or read Endpoint 0 data. Endpoint 0 can be used for
Class/Vendor commands and data transfers.
HW_USBEP0PTRR
X:$F20B
BITS LABEL RW RESET
23:16 RSRVD
15:0 AP
RW 0
DEFINITION
Reserved
Table 36. USB Endpoint 0 Address Pointer Registers Description
6.1.2.
USB Utility Register
HW_USBUTILR
BITS
LABEL RW RESET
23:18 RSRVD
17:16 INTF
R
R
0
0
15:13 ALT
R
0
12:11 CONFIG R
0
10:0
0
FRAME R
X:$F20A
DEFINITION
Reserved
USB Interface value – After SetInterface command by the host INTF will reflect the
Interface setting , the system will receive an interrupt from the USB interface.
USB Alternate Interface value – After SetInterface command by the host ALT will reflect
the Alternate setting , the system will receive an interrupt from the USB interface.
USB Configuration value – After SetConfiguration command by the host CFG will reflect
the Configuration setting , the system will receive an interrupt from the USB interface.
USB Frame Time Stamp Bits – The FRMx bits contain the frame time stamp for the
current frame as defined by the USB host controller.
Table 37. USB Utility Register Description
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6.1.3.
USB Endpoint Control Status Register
HW_USBEP7R
HW_USBEP6R
HW_USBEP5R
HW_USBEP4R
HW_USBEP3R
HW_USBEP2R
HW_USBEP1R
HW_USBEP0R
BITS
LABEL
X:$F209
X:$F208
X:$F207
X:$F206
X:$F205
X:$F204
X:$F203
X:$F202
RW RESET
23
ENEP
RW 0
22
RW
R
21
20
ENIE
DONE
RW 0
R
0
19
STL
RW 0
0
*18
*SPEN/RSRVD
18:10 RSRVD
R
0
9:0
COUNT
RW 0
DEFINITION
When set by the system, the ENEP bit is used to enable transactions between
the USB interface and the USB host controller. At initialization the system
should set all Endpoint[0-7] ENEP bits. After a successful tx/rx transaction,
the system software monitors which endpoint was completed by the
HW_USBCSR[20:13] for EP[7-0] then sets the appropriate USBEPx ENEP bit
to allow the next transaction.
After a successful transaction, RW will indicate if the transaction was a read
(USB IN tranasction) or write (USB OUT transaction).
When set by the system, the ENIE bit allows Epx to generate an interrupt.
After a successful transaction, DONE will generate an interrupt on one of the
pin USB_INTx. After the system services the interrupt, DONE should be reset
to allow the next transaction.
When set by the system software, the STL bit stalls the endpoint. When cleared,
the STL bit clears the stall. This allows the system to tell the USB Host that
endpoint is experiencing an error condition and requires intervention from the
Host to correct a problem befor communication can be resumed.
Short Packet Enable
Reserved
After a successful transaction, COUNT will indicate the number of bytes of the
transaction. For OUT transfers, if the read value is less than the value specified in
the configuration descriptors (typically 64 bytes for control, bulk, interrupt and
1023 for isochronous) then the transfer has ended with a short packet.
For IN transfers, a special case for FP0, 1, 2 and 3 to handle sending short
packets. The value programmed in this field will be the number of bytes
transferred when $F209 bit 18 is enabled, else the number of transfers will
default to the value specified in the configuration descriptors.
* Bit 18 SPEN (Short Packet Disable) is used with HW_USBEP7R in conjuction with USBEP0R CNT (Count) bits 1, 2
and 3. Bit 18 is reserved with HW_USBEP6 through HW_USBEP0.
Table 38. USB Endpoint Control Status Register Description
6.1.4.
USB Configuration Base Address Pointer Register
The BAR15-0 bits of the HW_USBCBAR specify the base address within X memory
where the USB configuration data will be initialize by software. The USB interface
uses data at this location to respond to the USB Host Controller during enumeration.
HW_USBCBAR
BITS LABEL RW RESET
X:$F201
DEFINITION
23:16 RSRVD R
0
Reserved
15:0 AP
RW 0
Table 39. USB Configuration Base Address Pointer Register Description
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6.1.5.
USB Control Status Register
HW_USBCSR
X:$F200
BITS LABEL RW RESET
DEFINITION
23
RSRVD R
0
Reserved
22:21 DMASEL RW 0
Memory space to use for DMA transfers
00
X space
10
P space
01
Y space
11
Reserved
20:13 EP
R
0
Successful Transfer – This signal is enabled when a successful IN (to the Host) or
OUT (from the Host) transfer is completed. This will generate an interrupt and must
be reset after the interrupt is serviced. These bits are copies of the EP7...EP0 bits
contained in the status registers for the individual end points.
12
SUSP
R
0
USB Suspend – Enabled when the USB System is in suspend mode. The USB host and
device will be in suspend mode when there is 3 milliseconds of idle on the USB cable.
11
AIFC
RW 0
USB Latch Interface/Alternate Value – When the Host transmits a SetInterface, this
bit will be set and the corresponding Interface and Alternate value is place on the
USBUTIL[17:13]. The interface value will be USBUTIL[17:16] and the alternate
value will be USBUTIL[15:13]. This will generate an interrupt and must be reset after
interrupt is serviced.
10
ACFG
RW 0
USB Latch Configuration Value – When Host transmits a SetConfiguration, this bit
will be set and the corresponding Configuration value is placed on the
USBUTIL[12:11]. This will generate an interrupt and must be reset after interrupt is
serviced.
9
RSRVD R
0
Reserved
8
LCFGD RW 0
USB Load Configuration Done – When the UDC receives the adequate amount of
configuration data, LCFGD will inform the system that “power on” configuration is
done and the UDC will not accept any more configuration data.
7
CLKOFF RW 0
USB clock off – When set, clocks to the USB module will be set to zero.
6
USBRS RW 0
USB Host Reset – When the Host transmits a USB reset over the cable, this bit will
be set. An interrupt will be generated informing the system. The system has to clear
this bit after the appropriate DSP action has been taken.
5
RXPWD RW 1
USB Analog Receive Power Down – The RXPWD will turn off the receive path on
the USB cable by controlling the USB analog when set .
4
TXPWD RW 1
USB Analog Transmit Power Down – The TXPWD will turn off the transmit path on
the USB cable by controlling the USB analog when set.
3
RSM
RW 0
USB Resume Bit – When the USB interface has entered the standby state, setting
the RSM bit will cause the interface to wake up and resume operation. The RSM bit
is cleared by the USB interface when operation has resumed.
2
SPD
RW 0
USB Speed Bit – The SPD bit determines the speed of the USB interface. When set,
the USB interface is configured for 12 Mbps (high speed) operation. When clear, the
USB interface is configured for 1.5 Mbps (low speed).
1
GIE
RW 0
USB Global Interrupt Enable Bit – When set, the GIE bit allows all endpoint
interrupts to generate interrupts to the DSP core. When cleared, no interrupts will be
generated to the core, even if a given endpoint’s interrupt is enabled.
0
USBEN RW 0
USB Enable Bit – The USBEN bit enables the USB port. This bit must be set before
any other USB registers are written to.
Table 40. USB Control Status Register Description
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6.1.6.
USB End Point Data Transfer Types
The six general-use endpoints may be configured for any of the four USB transfer
types (Control, Bulk, Isochronous, or Interrupt).
6.1.6.1.
USB EP0
End Point 0 (EP0) is used for the Default Pipe and is available for host/device control communications after the USB configuration phase has completed. It consumes
22-words in X memory and is packed in the following manner:
ADDRESS
Base
Base+$0001
.
Base+$0015
BITS 23-26
Byte 2
Byte 5
.
Reserved
BITS 15-8
Byte 1
Byte 4
.
Reserved
BITS 7-0
Byte 0
Byte 3
.
Byte 63
Table 41. USB End Point 0 (EP0)
6.1.6.2.
USB Control Transfer Type
Control transfer buffers are 64-bytes long and may be located anywhere in on-chip
memory on an 8-word boundary. The buffer consumes 22-words and the bytes are
packed as follows:
ADDRESS
Base
Base+$0001
.
Base+$0015
BITS 23-26
Byte 2
Byte 5
.
Reserved
BITS 15-8
Byte 1
Byte 4
.
Reserved
BITS 7-0
Byte 0
Byte 3
.
Byte 63
Table 42. USB Control Transfer Type
6.1.6.3.
USB Bulk Transfer Type
Bulk In/Out transfers use 64-byte buffers which may be located anywhere in on-chip
packed as follows:
ADDRESS
BITS 23-26
BITS 15-8
BITS 7-0
Base
Base+$0001
.
Base+$0015
Byte 2
Byte 5
.
Reserved
Byte 1
Byte 4
.
Reserved
Byte 0
Byte 3
.
Byte 63
Table 43. USB Bulk Transfer Type
6.1.6.4.
USB Isochronous Transfer Type
Isochronous In/Out transfers use 1023-byte buffers which may be located anywhere
in on-chip memory on an 8-word boundary. The buffer consumes 341-words and the
bytes are packed as follows:
ADDRESS
BITS 23-26
BITS 15-8
BITS 7-0
Base
Base+$0001
.
Base+$0154
Byte 2
Byte 5
.
Byte 1022
Byte 1
Byte 4
.
Byte 1021
Byte 0
Byte 3
.
Byte 1020
Table 44. USB Isochronous Transfer Type
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6.1.6.5.
USB Interrupt Transfer Type
Interrupt transfers use 64-byte buffers which may be located anywhere in on-chip
packed as follows:
ADDRESS
BITS 23-26
BITS 15-8
BITS 7-0
Base
Base+$0001
.
Base+$0015
Byte 2
Byte 5
.
Reserved
Byte 1
Byte 4
.
Reserved
Byte 0
Byte 3
.
Byte 63
Table 45. USB Interrupt Transfer Type
6.1.7.
USB Configuration Tables
The STMP3410 USB requires two configuration tables to be loaded into on-chip
before the port is enabled: the USBDescriptorTable and the USBPowerOnTable.
The USBDescriptorTable is a standard set of USB descriptors, and the USBPowerOnTable is a collection of pointers to the USBDescriptorTable, along with other
pertinent EP configuration information.
6.1.7.1.
USBDescriptorTable
The USBDescriptorTable is only used to inform the host of configuration information
– it is not used directly for USB configuration. The STMP3410 USB supports only a
single configuration, so the USBDescriptorTable must have the following form:
Device Descriptor
.
Configuration Descriptor
.
Interface 0 Descriptor
.
.
EP0 Descriptor
.
.
.
.
.
<Interface n Descriptor>
.
EPx Descriptor
.
.
.
.
.
.
.
<EP Descriptor>
String 1 Descriptor
.
.
.
<String y Descriptor>
Where <> denotes an optional element, n denotes the Interface number, x denotes
the EP number, and y indicates the string number. Standard USB device classes,
such as the Audio and Mass Storage classes have requirements for additional,
class-specific descriptors.
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6.1.7.2.
USBPowerOnTable
The USBPowerOnTable is used by the USB hardware to determine the configuration. The table has the following form
USBConfigBuf0
USBStringBuf0
.
.
.
USBStringBuf7
USBEndPtBuf0
.
.
.
USBEndPtBu6
Before the USB end points are enabled and the USB configuration process is
begun, a pointer to the USBPowerOnTable must be written to the USCBAR register.
This table must be located in XRAM. The USBPowerOnTable is comprised of
USBEndPtBuf, USBConfigBuf, and USBStringBuf sections. Since the STMP3410
supports 4 interfaces with 2 alternates, the max number of logical endpoints is 8.
Each USBEndPtBufx represents a logical endpoint – 8 are provided to cover all
interfaces/alternates.
BITS
39:36
35:34
33:32
31:30
29:28
LABEL
EP_NUM
EP_CONFIG
EP_INTERFACE
EP_ALTSETTING
EP_TYPE
RW
R
RW
RW
RW
R
27
EP_DIR
R
26:17 EP_MAXPKTSIZE R
16
EP_USERBIT
R
15:0 EP_BUFADRPTR R
DEFINITION
Physical Endpoint Number, 0000-0111
Configuration Number to which the EndPoint belongs. Always 00.
Interface Number to which the Epndpoint belongs
Alternate Setting to which the Endpoint belongs.
Type of Endpoint:
00
Control
01
Isochronous
10
Bulk
11
Interrupt
Direction of Endpoint:
0
OUT Endpoint
1
IN Endpoint
This bit is ignored for Control Endpoints.
Maximum packet size for this Endpoint.
Hardware signaling – set to 0.
XRAM address for this Endpoint buffer. Bits [2:0] must encode the Endpoint number
(same as Ep_Num, bits [39:36], above). Therefore, the buffer must be allocated on
an 8-word boundary. The bits are masked off for access to the endpoint buffer.
Table 46. USBEndPtBuf Format Description
BITS
LABEL
31:16 DESCRIPTOR SIZE
15:0
42
RW
DEFINITION
R
This is the size of the Descriptor to be returned when the Host makes a request
for GetDescriptor(Configuration). This is the wTotalLength of the standard
Configuration Descriptor. This is the total length of data returned for the
configuration to which this register is associated. This includes the combined
length of all descriptors (Configuration, Interface, Endpoint, and Class or Vendor
specific) returned for this configuration.
DESCRIPTOR
R
This is the XRAM address pointer to the Configuration Descriptor. When the host
ADDRESS POINTER
requests a Configuration Descriptor, the USB port will start at this address and
read Descriptor Size bytes.
Table 47. USBConfigBuf Format Description
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BITS
LABEL
RW
23:16 STRING LENGTH
15:0
R
DEFINITION
This field is the length of the String in bytes with which this USBStringBuf is
associated. This is the bLength of the String Descriptor for the associated String.
This is the XRAM address pointer to the String Descriptor. When the host
requests the String Descriptor, the USB port will start at this address and read
String Length bytes.
Table 48. USBConfigBuf Format Description
STRING ADDRESS R
POINTER
6.1.7.3.
Pre-Defined Descriptor Values
The STMP3410 is a programmable device but there is a certain set of descriptor
values that will be common for most devices. Static values are shown in bold –
these values may not be changed.
BITS
17
16
15
14
12
10
8
7
6
5
4
2
1
0
Note:
LABEL
VALUE
DEFINITION
BNUMCONFIGURATIONS $01
Only one configuration is allowed
ISERIALNUMBER
$xx
Depends on entire configuration.
IPRODUCT
$xx
Depends on entire configuration
IMANUFACTURER
$xx
BCDDEVICE
$xxxx Specific to a given product
IDPRODUCT
$xxxx Specific to a given product
IDVENDOR
$xxxx Specific to a given OEM (assigned by the USB-IF)
BMAXPACKETSIZE0
$40
EP0 buffer is 64-bytes
BDEVICEPROTOCOL
$00
Protocol is specified in the interface descriptors
BDEVICESUBCLASS
$00
Subclass is specified in the interface descriptors
BDEVICECLASS
$00
Class is specified in the interface descriptors
BCDUSB
$0100 USB Specification 1.0
BDESCRIPTORTYPE
$01
DEVICE descriptor
BLENGTH
$12
18-bytes long
Values in bold have been defined. “xx” values will be defined at a later time by the software team.
Table 49. Pre-Defined Device Descriptor Description
BITS
8
7
6
5
4
2
1
0
Note:
LABEL
VALUE
DEFINITION
MAXPOWER
$xx
Depends on configuration
BMATTRIBUTES
$xx
Depends on configuration
BCONFIGURATION
$xx
BCONFIGURATIONVALUE $00
Configuration 0
BNUMINTERFACES
$xx
Depends on the given configuration
WTOTALLENGTH
$xxxx Depends on entire configuration
BDESCRIPTORTYPE
$02
INTERFACE descriptor
BLENGTH
$09
9-bytes long
Values in bold have been defined. “xx” values will be defined at a later time by the software team.
Table 50. Pre-Defined Device Descriptor
BITS
6
4
3
2
1
0
LABEL
BINTERVAL
WMAXPACKETSIZE
BMATTRIBUTES
BENDPOINTADDRESS
BDESCRIPTORTYPE
BLENGTH
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VALUE
$00
$40
$00
$00
$05
$07
DEFINITION
Not applicable for control endpoint
EP0 buffer is 64-bytes
Control type
EP0, control endpoint
ENDPOINT descriptor
7-bytes long
Table 51. USB EP0 Descriptor
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6.2.
USB Port Setup Sequences
6.2.0.1.
USB Intitialization
Initialization of the USB requires that the USBDescriptorTable and the USBPowerOnTable be loaded into XRAM. For devices that boot from Flash these tables will
reflect normal operation modes. For devices that boot from USB these tables will be:
Copy the USBDescriptorTable to XRAM.
Copy the USBPowerOnTable to XRAM.
Write $000000 to the HW_USBCSR, USBEP0…USBEPx.
Write #USBPowerOnTable to the HW_USBCBAR.
If high speed operation, set the HW_USBCSR[SPD] bit.
Set the HW_USBCSR[USBEN] bit.
6.2.0.2.
USB Shutdown
Call USBDisableEndPoint for all enabled End Points.
Clear all USBEPx[ENEP] bits.
Write $000000 to the HW_USBCSR.7
6.2.0.3.
EP7 Interrupt Service
EP7 is reserved by the system for USB port hardware handling of GetDescriptor
requests. However, interrupts will still be generated and must be serviced as follows:
Set HW_USBEP7[ENEP].
Clear HW_USBEP7[DONE].
6.3.
Multiple Configurations
Since the USB descriptors are RAM-based the device may be initialized with virtually any configuration (within the limits previously described). Since the STMP3410
DSP core controls the setup process for the USB port it may disable the port at anytime, load new Descriptor and Power On buffers, then re-enable the port to force a
reconfiguration.
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7.
PARALLEL EXTERNAL MEMORY CONTROLLER (EMC)
The STMP3410 contains an external memory controller that has two major functional modes: SmartMedia/NAND and CompactFlash. The SmartMedia/NAND flash
interface provides a state machine that provides all of the logic necessary to perform
DMA functions between on-chip RAM and the flash. The CompactFlash interface
supports all three major CompactFlash modes: Memory, I/O and IDE. These modes
can be used to communicate with standard CompactFlash (CF) devices such as CF
Flash and the IBM MicroDrive. The CF Memory mode can be used to communicate
with standard ATA/ATAPI devices like CD-ROM and Hard drives.
This documentation will detail the configuration and operation of the STMP3410’s
external memory interface. It will discuss the standard use of the interface for flash
applications. Additional information about other specific applications (CD-ROM,
DRAM, NOR Flash, etc) will be available in future application notes.
7.1.
EMC Overview
The external memory controller has several major features:
•
DMA data transfers allow minimal CPU overhead
•
32-bit SmartMedia addressing supports future devices up to 4Gbyte
•
Multiple device support with four SmartMedia and two CF chip selects
• Configurable timing can be set to support various devices
The external memory controller can be described as two fairly independent devices
in one: a SmartMedia/NAND flash interface and a CompactFlash/NOR flash/IDE
interface. Both interfaces share the same device pins, some registers and the DMA
engine.
Both interfaces uses memory mapped registers to setup and control the transactions. Data is always sent through the DMA – there are no data registers that correspond to the interface data bus. Transactions are always started with a kick bit. The
interface sets up the control lines and transfers data to/from the internal RAM. Once
the transaction is complete the interface signals the DSP with either a polled flag or
an interrupt. The kick bit, polling bit and interrupt configurations are all contained in
the registers.
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7.1.1.
STMP
PIN NUMBER
37:30
26
23
22
21
20
19
18
17
16
15
14
13
12
24
7
9
8
42
44
43
45
27
41
40
25
EMC External Pins
SMARTMEDIA
PIN NAME
SM_D7 - SM_D0
SM_WEn
SM_REn
*
SM_ALE
SM_CLE
SM_SEn
SM_CE0n
SM_CE2n
SM_CE3n
*
*
*
*
SM_CE1n
*
*
*
*
*
*
*
SM_WPn
*
*
SM_READY
CF+/COMPACTFLASH
PIN NAME,
MEMORY MODE
CF_D7 - CF_D0
CF_WEn
CF_OEn
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CF_CE0n
CF_CE1n
*
*
CF_WPn
CF_REGn
CF_RESETn
CF_BVD1/IREQ
*
CF_READY
CF_CDn
CF_WAIT
CF+/COMPACTFLASH
PIN NAME,
I/O MODE
CF_D7 - CF_D0
CF_WEn
CF_OEn
CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
CF_CE0n
CF_CE1n
CF_IOWRn
CF_IORDn
CF_WPn
CF_REGn
CF_RESETn
CF_BVD1
*
CF_READY
CF_CDn
CF_WAIT
CF+/COMPACTFLASH
PIN NAME,
TRUE IDE MODE
CF_D7 - CF_D0
CF_WEn
CF_OEn
*
*
*
*
*
*
*
*
CF_A2
CF_A1
CF_A0
CF_CE0n
CF_CE1n
CF_IOWRn
CF_IORDn
CF_WPn
CF_REGn
CF_RESETn
CF_BVD1
*
CF_READY
CF_CDn
CF_WAIT
Table 52. Mapping of pins to CF+/CompactFlash and SmartMedia Card/Device Pins
Note: Pins marked with (*) are not used by the module and are available for use in GPIO mode. See the GPIO module
documentation for more information. I/O mode and IDE modes are not normally used in any application. Their
pin names are not included in the pin list at the end of this document.
7.2.
General Use of the External Memory Interface
The external memory interface has some functions that are shared between both
the SmartMedia and the CompactFlash modes. In particular, common registers control the functions that communicate with the DSP such as the DMA and transaction
start/done functions. Each of the memory interfaces also have their own registers that
set up their specific parameters. This section will focus on the common registers.
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7.2.1.
Common Flash Registers
7.2.1.1.
Flash Control Register
HW_FLCR
BITS LABEL RW RESET
23:22 RSRVD R
0
21
SRST
RW 0
20:17 RSRVD R
0
16:6 NB
RW $001
5:4
MMD
R
0
3
IRQP
RW 0
2
1
0
TCIE
RW
KICK
RW 0
RW 0
RW 0
X:$F000
DEFINITION
Reserved bits. Must be written as 0.
Flash module software reset. This bit is itself reset by a hardware reset only; a
software reset does not clear the bit.
Reserved bits. Must be written as 0.
Number of bytes to transfer.
External interface type:
00 – SmartMedia
10 – Reserved
01 – CompactFlash
11 – Reserved
Reading a one indicates a pending interrupt; writing back a one de-asserts the
interrupt; writing zero has no effect.
Setting this bit enables the transaction-complete interrupt.
Setting this bit initiates an external memory transfer is a read; otherwise it is a write.
Setting this bit initiates an external memory transfer; it automatically clears when the
transfer completes.
Table 53. Flash Control Register Description
The Flash Control Register sets up basic operating parameters. After the transaction has been set up in all of the appropriate registers (transaction type, timing,
address, etc) the software triggers the kick bit. This will initiate the transaction. The
status bit will indicate when the transaction has been completed. The DSP can
either poll the status bit or the register can be configured to send an interrupt on
transaction completion.
The Flash Start Address Low and High Registers determine the addresses of both
the STMP3410’s internal XRAM, YRAM and PRAM and the external device. Multiple cycle transactions (reading/writing multiple bytes sequentially) will pack/unpack
data from the DSP XRAM, YRAM and PRAM’s 24-bit words into the external device’s
8-bit interface. The LSB is packed/unpacked first. Each byte is packed with its MSB at bit
7, 13, or 23 for bytes 1, 2 or 3.
The address bus’s behavior depends on the specific external device type. SmartMedia devices don’t use the address bus. They are externally selected with chip select
lines (CE0-3) and internally with multi-byte accesses over the I/O lines (see more in
the SmartMedia section, below). CompactFlash devices may use the Address pins
in Memory or I/O mode or with a combination of control pins (CE0, CE1, CF_A0, A1,
A2) in IDE Mode. In all cases the mode configuration registers determine how the
target device is addressed.
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7.2.1.2.
Flash Control 2 Register
HW_FLCR2
BITS
23:7
6
5
4
3
LABEL
RSRVD
CKGT
NFLSH
NDMA
LA
RW
RW
RW
RW
RW
RW
RESET
0
0
0
0
0
2
RA
RW 0
1:0
ASEL
RW 00
X:$F004
DEFINITION
Reserved
Turns clocks to Flash module off.
Inverts data from the system to the Flash.
Inverts data from the Flash to the system .
Left aligns 16-bit word data from bits 23:8. The LSbyte will be zeroed. This is only
associated with CompactFlash 16-bit data mode in the CFControl register bit 23. If
neither Left or Right Align is set the CompactFlash 16-bit data mode will ‘pack’ the
word data into the 24-bit memory.
Right align 16-bit word data from bits 15:0. The MSbyte will be zeroed. This is only
associated with CompactFlash 16-bit data mode int the CFControl register bit 23. If
neither Left or Right Align is set the CompactFlash 16-bit data mode will ‘pack’ the
word data into the 24-bit memory.
00
X space
10
P space
01
Y space
11
Reserved
Table 54. Flash Control 2 Register Description
The Flash Control 2 Register sets up addtional operating parameters.
7.2.1.3.
Flash Start Address Low Register
HW_FLSALR
X:$F001
BITS LABEL RW RESET
23:0
XA
DEFINITION
Lower 24 bits of external memory starting address
Table 55. Flash Start Address Low Register Description
7.2.1.4.
Flash Start Address High Register
HW_FLSAHR
BITS LABEL RW
23:8
7:0
DA
XA
R
R
X:$F002
DEFINITION
Starting address for DMA transfer.
Upper 8 bits of external memory starting address
Table 56. Flash Start Address High Register Description
7.3.
External Memory Interface with SmartMedia/NAND Flash Devices
The external memory interface will commonly be used with SmartMedia flash
devices. SmartMedia are small removable cards that contain one or two NAND
Flash devices. Alternatively, the system designer can use non-removable NAND
flash chips. Both devices use the same pins. The SmartMedia electrical interface
uses an 8-bit data/address bus and 8 control lines. Multiple devices share the same
bus, with chip selects used for selection.
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7.3.1.
5-3410-D1-2.0-0402
SmartMedia/NAND Pins
•
SM_D0 - SM_D7: 8-bit I/O interface. This bus is used to send addresses
(multiple bytes required to send a complete address), data and commands to
the SmartMedia device. Data, device ID and status information are received
from the Flash over this bus.
•
SM_WEn: Write Enable. This active low output is used to indicate a write cycle
to the Flash. The STMP3410’s external memory interface will write to the bus
during a WE~ cycle.
•
SM_REn: Read Enable. This active low output indicates a read cycle to the
Flash. The flash device writes to the bus during a RE~ cycle.
•
SM_ALE: Address Latch Enable. This active high output indicates that the data
on the I/O bus is part of an address. The STMP3410 outputs one byte of a Flash
memory address during this cycle.
•
SM_CLE: Command Latch Enable. This active high output indicates that the
data on the I/O bus is a flash command. The STMP3410 outputs a SmartMedia
command during this cycle. See the data sheet for your SmartMedia device for
more information on the valid commands.
•
SM_SEn: Spare Enable Select. This active low output is used to indicate that
the ECC data should be sent with a regular 512 Byte Flash Block. This
command is not typically used since the ECC should always be used. It is
recommended that the SE~ line be tied to ground (asserted) to ensure that the
spare area is always used.
•
SM_CE0n – SM_CE3n: Chip Enable Lines. Active low outputs that select each
SmartMedia or NAND Flash. Connect one to each of the flash devices.
•
SM_WPn: Write Protect. This active low output is used prevent accidental data
corruption during non-write cycles.
•
SM_READY: Ready/ Busy~. This active low input indicates that the flash device
is busy. No new transactions to any devices should occur unless this line is not
asserted. The Ready/Busy~ line uses open-drain drivers and requires an
external pull-up resistor. All SmartMedia/NAND Flash devices busy pins should
be connected to this pin.
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7.3.2.
SmartMedia Registers
7.3.2.1.
SmartMedia Control Register
HW_FLSMCR
BITS LABEL RW RESET
23:17 RSRVD R
16
BPIRQ R
X:$F010
DEFINITION
0
1
Bad programming interrupt pending. Reading a one indicates a pending interrupt;
writing back a one de-asserts the interrupt; writing zero has no effect.
15
TOIRQ RW 0
Timeout interrupt pending. Reading a one indicates a pending interrupt; writing back a
one de-asserts the interrupt; writing zero has no effect.
14
BPIE
RW 0
Bad Programming interrupt enable. Generate BPIRQ if SmartMedia interface is
kicked with bad programming.
13
TOIE
RW 0
SmartMedia Timeout interrupt enable.
12:5 ICMD
R
1
Initial standard SmartMedia command for transaction:
$FF Card Reset
$70 Card Status Register Read
$60 Card Block Erase. Second command byte is always $D0.
$00 Read/Program Data. Start address is in first 256 bytes of 528-byte page.
$01 Read/Program Data. Start address is in second 256 bytes of 528-byte
page.
$50 Read/Program Data. Start address is in redundant area (last 16-bytes of
page).
$90 Car ID Read
4
SIZE
R
1
Target SmartMedia device size:
0
<= 32 MBytes
1
> 32 MBytes
3
WP
RW 0
Write Protect pin output (active-low):
0
assert -WP pin
1
de-assert -WP pin
2
SE
RW 0
-SE pin control. Allows the spare (redundant) area (last 16 bytes of page) to be skipped.
0
assert -SE pin. Redundant area enabled.
1
de-assert -SE pin. Redundant area disabled.
1:0
CS
R
0
External Chip Select:
00
Select Chip 0
01
Select Chip 1
10
Select Chip 2
11
Select Chip 3
Note: The SmartMedia interface’s state machine logic makes a number of checks on the legitimacy of DSP
programming before transitioning the master state machine out of its IDLE state. If these checks fail, the state
machine remains IDLE, the BPIRQ gets set and the transaction is considered done (Kick bit in the HW_FLSMCR
register is de-asserted). Optionally, a bad-programming interrupt can be enabled by setting the BPIE bit.
Table 57. SmartMedia Control Register Description
The SmartMedia Control Register configures the interface and determines the type
of transaction. The SmartMedia portion of the interface was designed to very closely
interface to external Flash device. The interface knows how to set the appropriate
control and data bits at a device command level. Operations like Reset, accesses to
the Status Register and data operations are automatically processed by the interface. The user code just needs to set up some basic timing and device information
and make a high level request.
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7.3.2.2.
SmartMedia Timer 1 Register
HW_FLSMTMR1R
BITS
23:22
21:17
16:11
10:5
4:0
LABEL
RSRVD
TRWH
TWPW
TRPW
TRWSU
RW RESET
RW
RW
RW
RW
0
0
0
0
X:$F011
DEFINITION
Reserved
Read/Write Pulse Hold in terms of dclks
Write Pulse Width in terms of dclks
Read Pulse Width in terms of dclks
Read/Write Strobe Setup in terms of dclks
Table 58. SmartMedia Timer 1 Register Description
7.3.2.3.
SmartMedia Timer 2 Register
HW_FLSMTMR2R
X:$F012
BITS LABEL RW
DEFINITION
23:6 TWTO RW Delay before timing out on RDY pin in terms of dclks
5:0
TWT
RW Delay before examining RDY pin in terms of (dclks x 1024)
Table 59. SmartMedia Timer 2 Register Description
The SmartMedia timing registers default to conservative settings on reset.
TIMING PARAMETER
Trwh
Twpw
Trpw
Trwsu
Twto
Twait
DEFAULT IN DCLK CYCLES
TIME @ 48MHZ (21NS CYCLE)
2
42ns
6
125ns
6
125ns
2
42ns
488 * 1024
10.5ms
16
336ns
Table 60. SmartMedia Timing Specifications
SAMSUNG SPEC
40ns
80ns
80ns
30ns
4ms
200ns
The firmware designer can change the timing to accommodate higher performance
or newer flash devices, and should check that the timing values are acceptable if the
dclk clock frequency is changed.
7.4.
External Memory Interface in CompactFlash Mode
Some applications will require an interface to either a CompactFlash device such as
a standard CF memory card or IBM Microdrive. Other applications will interface to a
standard IDE/ATAPI device like a CD-ROM or hard disk. The system designer may
also want to interface to an external SDRAM, DRAM or NOR Flash for bulk data
storage. All of these are possible with the CompactFlash mode of the external Memory Interface and, occasionally, some external glue logic like a CPLD.
This interface mode differs significantly from the SmartMedia mode in that it doesn’t
have the intelligence to closely control any device family at a high level. All of the
control pins must be configured at the register level. High-level command state
machines are implemented in software rather than the memory interface. This
requires additional system software development. The benefit is significantly
increased flexibility. The CompactFlash mode covers a large number of interfaces.
7.4.1.
CompactFlash Modes
The three CompactFlash (CF) modes are Memory Mode, I/O Mode and IDE Mode. All
of the modes use an 8-bit or 16-bit data bus based on 144 or 100 package configuration. All CF devices have an 8-bit mode that allows byte addresability. For 100 pin
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package non CompactFlash compliant devices such as CD-ROM and many hard
drives will require external glue logic to support the required 16-bit data bus. All CF
compliant devices can use any of the three CompactFlash modes. In this case the
choice of which mode to use depends on the software requirements. It is recommended that all applications using the CompactFlash interface use the Memory Mode.
7.4.2.
CompactFlash Registers
7.4.2.1.
CompactFlash Control Register
HW_FLCFCR
BITS
23
22
21:20
19
LABEL
MODE16
DASP
VS
CRE
RW
RW
R
R
RW
18:17 CS
16
XDDI
15:14 CFAI
RW
R
RW
RESET
0
unknown
unknown
EMC5600_
CARDRSTEN_OUT
00
unknown
10
13
INCS
RW
0
12
ISCS
RW
0
11
IFCS
RW
0
10
9
INCE
ISCE
RW
RW
0
0
8
IFCE
RW
0
7
RI
R
unknown
6
XWT
R
unknown
5
CRST
RW
4
XATTR
RW
EMC5600_
CARDRST_OUT
0
3:2
SM
RW
2’b00
1
0
CDP
WP
RW
R
EMC5600_PUP
unknown
X:$F008
DESCRIPTION
CompactFlash data bus is 16-bits
DASP pin of the CompactFlash card, if connected.
VS2, VS1 voltage sense inputs (if connected)
Output enable for RESET/-RESET pin
Active-high versions of outgoing -CE2,-CE1/-CS1,CS0 chip selects
Incoming -PDIAGN/-STSCHG pin, sampled into dclk domain
Multi-byte transfer card address increment/toggle
00 - next A10-A0 same as previous
01 - next A10-A0 equal to previous plus one
10 - next A10-A0 equal to previous plus two (CIS)
11 - next A10-A0 equal to previous, but A0 toggles
Reading a one indicates a pending interrupt; writing back a one deasserts the interrupt; writing zero has no effect
Setting this bit enables the card absence/removal interrupt
Setting this bit asserts an interrupt based on the -PDIAGN/-STSCHG
pin of the CompactFlash card going low in any PC Card Mode
Setting this bit passes on a card-based interrupt from the RDY/BSY/-IREQ/INTRQ pin of the CompactFlash card. The interrupt
occurs if the input pin transitions (either direction) in any PC Card
socket mode (Memory, I/O, True IDE)
RDY/-BSY/-IREQ/INTRQ pin of the CompactFlash card, sampled
into dclk domain
-WAIT active-low card pin of the CompactFlash card, sampled into
dclk domain
0 - wait/card is busy
1 - card/data is available
Output value to RESET/-RESET pin of the CompactFlash card.
Active-high in Memory or I/O Mode; Active-low in True IDE Mode.
0 - Access to Attribute Memory or I/O space
1 - Access to Common Memory
Card access mode
00 - PC Card Memory Mode
01 - PC Card I/O Mode
10 - True IDE Mode
11 - reserved
Card Detect pin (-CD1) pullup enable/disable
Write Protect (WP) pin of CompactFlash card, sampled into dclk
domain
Table 61. CompactFlash Control Register Description
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7.4.2.2.
CompactFlash Timer1 Register
HW_FLCFTMR1R
RW
RESET
23:19 TRWH
BITS
LABEL
RW
0
18:12 TWPW
11:5
TRPW
4:0
TRWSU
RW
RW
RW
0
0
0
X:$F009
DESCRIPTION
Hold time for -CE, An, -REG pins of the CompactFlash card, relative to -WE, -RE,
-IOWR or -IORD de-asserting, in dclk cycles
-WE, -IOWR pins of the CompactFlash card pulse width, in dclk cycles
-OE, -IORD pins of the CompactFlash card pulse width, in dclk cycles
Read or write pin of the CompactFlash card setup time, in dclk cycles
Table 62. CompactFlash Timer1 Register Description
7.4.2.3.
CompactFlash Timer2 Register
HW_FLCFTMR2R
X:$F00A
BITS LABEL RW RESET
23:19 TRAQ
RW
0
18:14 THW
RW
1
13:4
3:0
RW
RW
1
0
TWTO
TWW
DESCRIPTION
Delay between -OE/-IORD de-assertion and STMP3410 re-acquiring the data bus,
in dclk cycles
Hold time between -WAIT de-asserting and read or write strobe (-OE, -WE, etc) deasserting, dclk cycles
Timeout waiting for card-imposed wait (-WAIT low) period, in dclk cycles
Wait-for-wait time, in dclk cycles. Time for -WAIT to assert, from -OE/ -WE/-IOWR/IORD assertion edge.
Table 63. CompactFlash Timer2 Register Description
7.4.3.
Using the CompactFlash Modes
SigmaTel will update this datasheet and release application notes to cover specific
applications of the CompactFlash mode.
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8.
I2C INTERFACE
The I2C is a standard 2 wire serial interface used to connect the STMP3410 with
peripherals or host controllers. This interface provides a standard speed (up to
100kbps) and high speed (up to 400kbps) I2C connection to multiple devices with
the STMP3410 acting in either I2C master or I2C slave mode. Typical applications
for the I2C bus include: EEPROM, LED/LCD, FM Tuner, Real Time Clock, etc.
The STMP3410’s I2C port supports multi-master configurations where peripheral
devices can send messages without being queried.
8.1.
I2C-Specific Implementation
8.1.1.
•
The STMP3410 can be configured as either a master or slave device. In master
mode it generates the clock (I2C_SCL) and initiates transactions on the data
line (I2C_SDA).
•
The I2C block can be configured to pack data into 8, 16 or 24 bit words. Data on
the I2C bus is always byte oriented.
•
The STMP3410’s I2C has a programmable device address.
I2C Interface External Pins
I2C_SDA – I2C Serial Data. This pin carries all address and data bits.
I2C_SCL – I2C Serial Clock. This pin carries the clock used to time the address &
data.
Pull-up resistors are required on both of the I2C lines as all of the I2C drivers are
open drain (pull-down only). Typically, external 2k-Ohm resistors are used to pull the
signals up to VddIO.
Note: See Table 230 for I2C pin placement.
8.1.2.
I2C Interface Registers
The address map for the registers which are visible to the processor is as shown
below.
ADDRESS
X:$FFE7
X:$FFE6
X:$FFE5
REGISTER
I2C
Control/Status Register (HW_I2CCSR)
I2C Data Registers (HW_I2CDATR)
I2C Clock Divider Register (HW_I2CDIVR)
Table 64. I2C Registers Address Map
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8.1.2.1.
I2C Interface Control/Status Register
HW_I2CCSR
BITS
LABEL
23:21 RSRVD
20
TUFLCL
19
ROFLCL
18
SUBA
17
LWORD
16:15 BCNT
14
13
ACKF
TUFL
12
ROFL
11
TREQ
10:9
WL
X:$FFE7
RW RESET
DEFINITION
R
0
Reserved
RW 0
Transmitter Underflow Clear bit – Setting this bit clears both the TDE and TUFL
bits. When an underflow condition occurs the correct procedure is to write data to
the HW_I2CDATR register and then send a high pulse on the TUFLCL to clear the
TUFL bit.
RW 0
Receive Overflow Clear Flag – Setting this bit clears both the RDR and ROFL bits.
The correct procedure is to read the HW_I2CDATR register followed by a high
pulse on the ROFLCL bit.
R
0
Sub Address – This bit is set when the Master is transmitting two bytes of sub
address following the slave address byte.
RW 0
Last Word – This bit is set in master mode when the processor has written its last
word to the I2CI2C transmit register or upon receiving the second last word. Wlo
and wl1 decide how many bits the last block of data received by the master will be.
Last_word is cleared when the stop is generated. If a receive overflow condition
occurs in the master, at least two bytes must be received before a stop is
generated ie if wl0 = wl1 = 0 then the last word bit must not be set on this receive.
R
00
Byte Count – These bits hold the number of bytes received by the device in either
master or slave mode.
BCNT Bytes received
01
1 byte
10
2 bytes
00
3 bytes
RW 0
Acknowledge Failure – When this bit is set, no acknowledge has been returned.
R
0
Transmitter Underflow – Underflow occurs when TDE = 1 and another transfer is
triggered copying the contents of the data register into the shift register.
R
0
Receiver Overflow – Overflow occurs when RDR = 1 and the shift register
performs another parallel load of the data register. The shift register is 8 bits wide
for the master receiver, 24 bits wide for the slave receiver. Cleared by a read of the
HW_I2CDATR register followed by a high pulse on the ROFLCL bit.
RW 0
Transmit Request – This bit is used to request a transfer with the I2C in master
mode. It is pulsed high to request the transfer and the mode bit must already be
driven for either standard or fast mode. Upon receiving the pulse the I2C master
section will generate a start condition and transmit the slave address.
RW 00
This bit is also used to request a repeated start to the master device. A pulse must
be sent, when the processor has written its last word to the I2C transmit register or
upon receiving the last word, to generate a repeated start at the end of the
subsequent receive or transmit. To request a repeated start immediately after the
slave address and two bytes of sub address have been transmitted it is necessary
to send a pulse first to start the transfer of the slave address and then another
pulse a maximum of ns later to request the repeated start.
Word Length – Defines the word length being used by the interface for either I2C
master or slave modes.
WL Word Length
00
8 bit
10
16 bit
01
24 bit
These bits are also used with the last_word bit so that the device can decide whether
the last block of data the master receives is 8, 16 or 24 bits, ie wl0, wl1 are set before
the transfer and then the last_word bit is set on the receive of the second last block of
of data. These bits should not be changed while a transfer is in progress.
Table 65. I2C Interface Control/Status RegisterDescription
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BITS
LABEL
8
RWN
7
6
5
4
3
2
1
0
RW RESET
DEFINITION
R
0
Read/Not Write – If equal to zero the Master is writing to the Slave, when equal to
one the Master is reading from the slave.
TDE
R
0
Transmitter Data Empty – This bit is set when the contents of the transmitter data
register are loaded into the shift register. When this bit is set, the processor can
write to the Transmit Data register. If transmit interrupts are enabled, when this bit
becomes set, an interrupt will be asserted to the processor.
RDR
R
0
Receiver Data Ready – This bit is set when the shift register performs a broadside
load to the Receive Data Register. It’s cleared by hardware when the processor
reads the Receive Data Register. If receive interrupts are enabled, when this bit
becomes set, an interrupt will be asserted to the processor.
MODE
RW 0
Operating Mode Bit – When set, the I2C is in Fast mode (400Kbits/sec) and when
cleared, the I2C is in Standard mode (100 Kbits/sec). There is noise suppression
for both modes. If the device is to be master, the mode must be set or cleared
before TREQ (bit 11) becomes active.
TIE
RW 0
Transmitter Interrupt Enable – When set, the transmit interrupts are enabled to the
processor.
ARBLOST RW 0
Arbitration lost – After every transfer using the master I2C device this bit should be
checked to ensure arbitration has not been lost to another master. This bit is
cleared by a write to the control/status register.
BUSY
R
0
I2C Bus Busy – When this bit is set the I2C bus is busy. It is set after a START
condition is detected and remains set until a STOP condition is detected. If there is
arbitration on the I2C_SDA line and our device loses, then the busy bit will remain
set until our device detects a stop condition from the winning device.
RIE
RW 0
RIE Receiver Interrupt – Enable When set, the receive interrupts (Receiver Data
Ready and Receiver Overflow) are enabled. Both interrupts are processed by
reading data from the I2C data register (HW_I2CDATR). If these interrupts are not
processed they will continuously reoccur.
I2C_EN
RW 0
Peripheral Enable – When set, the I2C receive and transmit channel are enabled.
Table 65. I2C Interface Control/Status RegisterDescription (Continued)
8.1.2.2.
I2C Data Registers
There are two 24-bit Data Registers located at the same address, Receive and
Transmit Data Registers. The Receive Data Register contents are read over the
data bus if the processor performs a read of the address X:$FFE6. The Transmit
Data Register is written to the external data bus if the processor writes to this same
address. The Transmit Data Register should be filled before setting the TREQ bit to
initiate a transfer.
HW_I2CDAT
BITS LABEL RW
23:0
DATA
X:$FFE6
RESET
RW 0
DEFINITION
Address/DATA register
Table 66. I2C Data Register Description
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I2C Clock Divider Register
8.1.2.3.
The 8-bit Clock Divider Register is used to divide the system clock (dclk) so that the
I2C serial clock (I2C_SCL) can be generated. The value in [8:1] is used to divide the
system clock to generate the I2C clock, this clock is futher divided by 4 if the MODE
bit (bit 5) in the I2C Interface Control/Status register is clear. If the system clock is
set to 50 MHz, then the reset value for this register will divide this clock by 132 to
give an I2C clock of ~380 kHz for I2C fast mode, if the MODE bit is set, this will be
further divided by 4 to give an I2C clock of ~95 kHz for I2C normal mode. The formula for calculating the SCL Clock is: (div+3)x(system clock period) for fast mode
and ((div x 4) +22) x (system clock period) for slow mode.
HW_I2CDIV
BITS
23:9
8:1
0
LABEL
RSRVD
CDVB
RSRVD
X:$FFE7
RW RESET
DEFINITION
R
0
Reserved
RW 01000010 Clock divider value bits
R
0
Clock divider value bit that must be 0
Table 67. I2C Clock Divider Register Description
8.1.3.
I2C Interrupt Sources
The I2C port can be used in either interrupt driven or polled modes. If interrupts are
enabled, a level-sensitive interrupt will be signaled to the processor upon one of the
following events.
ADDRESS
P:$0030
P:$0032
P:$0034
P:$0036
BIT
6
12
7
13
LABEL
RDR
ROFL
TDE
TUFL
INTERRUPT SOURCE
I2C Receiver Data Ready
I2C Receiver Overflow
I2C Transmitter Data Empty
I2C Transmitter Underflow
Table 68. I2C Interrupt Address Map
The interrupt lines are tied directly to the status bits of the Control/Status Register.
Clearing these bits through software will remove the interrupt request. The Receiver
Data Ready and Transmitter Data Empty requests are automatically removed via
hardware when the Receive Data Register is read or the Transmit Data Register is
written respectively. The overflow and underflow error signals need to be cleared
through software by writing directly to the status bits of the Control/Status Register.
8.2.
I2C Bus Protocol
With reference to the clocking scheme shown in the figure below, the I2C interface
operates in the following manner:
Standard Mode
SCL
SDA
8 bits
8 bits
SLAVE Address & r/w
DATA
Acknowledge
signal
START
Condition
Acknowledge
signal
STOP
Condition
Figure 8. I2C data and clock timing
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A START condition is defined as a HIGH to LOW transition on the data line while the
I2C_SCL line is held HIGH. After this has been transmitted by the Master, the bus is
considered busy. The next byte of data transmitted after the start condition contains
the address of the slave in the first 7 bits and the eighth bit tells whether the Master
is receiving data from the slave or transmitting data to the slave. When an address
is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the
Master. In slave mode, the I2C write address is 86h, its read address is 87h.
Data transfer with acknowledge is obligatory. The transmitter must release the
I2C_SDA line during the acknowledge pulse. The receiver must then pull the data
line LOW so that it remains stable low during the HIGH period of the acknowledge
clock pulse. A receiver which has been addressed is obliged to generate an
acknowledge after each byte of data has been received.
8.2.1.
Slave Mode Protocol
The flow chart for the finite state machine is show in Figure 9. At device start-up all
the registers are reset so that the state is known from that time onward. Once the
I2C is enabled the slave will wait to detect a start condition on the I2C_SCL and
I2C_SDA lines. Once this is detected the slave will read in 8 bits and check against
its own device address which is $0086 to see if a master device is trying to start a
transfer with our device. If it is our address an acknowledge is sent, otherwise our
slave will not acknowledge and will return to state IDLE.
Next the RW is checked. If it is a write operation then the two sub address bytes
must be received and acknowledged and then the data is received with a check of
receive overflow before data is overwritten into the DSP_rx register.
If the master is requesting a read operation then the slave must start sending data
on the I2C_SDA bus immediately after acknowledging the Slave address and RW
bit. After each byte the acknowledge from the master must be checked. When the
master has received the last byte it will not send an acknowledge and the slave will
return to state IDLE. As long as the slave continues transmitting it must first check
whether the DSP_tx register has been fully transmitted and if so request more data.
The underflow condition is also checked.
Tables 69 - 72 show the first 2 bytes of data as a sub-address for purposes of illustration. The sub-address is used to address the memory space inside the device.
Table 69 defines each sub-address shown.
ST
SAD+W SAK SUB SAK SUB SAK DATA SAK SP
Table 69. Transfer when Master is writing a single byte of data to the interface as a slave
ST SAD+W SAK SUB SAK SUB SAK DATA SAK DATA SAK SP
Table 70. Transfer when Master is writing multiple bytes to the interface as a slave
ST SAD+W SAK SUB SAK SUB SR SAD+R SAK DATA NMAK SP
Table 71. Transfer when Master is receiving one byte of data from interface as a slave
ST SAD+W SAK SUB SAK SUB SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP
Table 72. Transfer when Master is receiving multiple bytes of data from interface as a slave
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Receive sub
address 0
Wait for start
Receive slave
address
No
Setup tx data
Our address
Send Ack
Yes
Yes
Ack address
Yes
Rofll
rdrx
No
Read
No
No
Receive
8 bits
Yes
Transmit
8 bits
No
24 bits or
start stop
Yes
No
ACK
Setup tx data
No
Yes
tdefx
No
TX reg
empty
Yes
tdefx
interrupt req
Yes
Yes
Rdr
interrupt req
TUFL
No
Figure 9. Slave Mode Flow Chart
BIT
ST
SR
SAD
SAK
SUB
DATA
SP
MAK
NMAK
DESCRIPTION
START condition
Repeated START condition
Slave address
Slave acknowledge
Sub address
Data
STOP condition
Master Acknowledge
No Master Acknowledge
Table 73. Slave and Master mode address definitions
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Data is now transmitted in byte format. Each data transfer has to contain 8 bits. The
number of bytes transferred per transfer is unlimited. Data is transferred with the
Most Significant Bit (MSB) first. If a receiver can’t receive another complete byte of
data until it has performed some other function, it can hold the clock line, I2C_SCL
LOW to force the transmitter into a wait state. Data transfer only continues when the
receiver is ready for another byte and releases the clock line.
If a slave receiver doesn’t acknowledge the slave address (e.g. it is unable to
receive because it is performing some real time function) the data line must be left
HIGH by the slave. The Master can then abort the transfer.
A LOW to HIGH transition on the I2C_SDA line while the I2C_SCL line is HIGH is
defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP condition.
8.2.2.
Master Mode Protocol
In Master Mode the STMP3410’s I2C interface generates the clock and initiates all
transfers.
8.2.2.1.
Clock Gen
2
The I C clock is generated from the system clock as described above in the register
description.
If another device pulls the clock low before the STMP3410 has counted the high
period, then the STMP3410 device immediately pulls the clock low as well and
starts counting its the low period. Once the low period has been counted the
STMP3410 releases the clock line high but must then check to see if another device
stills holds the line low in which case it enters a high wait-state.
In this way the I2C_SCL clock is generated with its low period determined by the
device with the longest clock low period and its high period determined by the one
with the shortest clock high period.
8.2.2.2.
Master Mode Operation
The finite state machine for master mode operation is shown on the next two Figure
10 and Figure 11. Figure 10 shows the start condition and transmission of the slave
address and two sub address bytes. Figure 11 shows the read and write states.
Tables 74 - 77 show examples of Master Mode I2C transactions. Table 69 defines
each sub-address shown.
ST SAD+W SAK SUB SAK SUB SAK DATA SAK SP
Table 74. Transfer when the interface as master is transmitting one byte of data would be
ST SAD+R SAK DATA MAK DATA MAK DATA NMAK SP
Table 75. Transfer when the interface as master is reading multiple status bytes of data from slave
ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA NMAK SP
Table 76. Transfer when Master is receiving one byte of data from slave internal sub-address
ST SAD+W SAK SUB SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP
Table 77. Transfer when Master is receiving multiple bytes of data from slave internal sub-address
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Wait for dspt
i2c_sda_en=1
stop condition
i2c_sda_en=0
start condition
Setup stop
Suba byte 0
Yes
suba 0 just
transmitted
No
Setup address
Setup TX
TX addr/suba
Underflow
8 bits tx
No
No
Yes
Yes
stop_clk <= 1
Chk ack
ACK
No
Yes
rep_start
rep_start
/last_word
No
Chk read or
write
WRITE
STATES
last_word
Write
No
slave addr
just
transmitted
Yes
Read
or Write
Read
READ
STATES
Figure 10. Master Mode Flow Chart
Start condition and transmission of slave address and two sub address bytes
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READ
STATES
Read
WRITE
STATES
Receive 8 bits
Enable tx data
No
8 bits tx
trans_en <= 1
Check
last_word
rec_count
Transmit 8 bits
8 bits
Decide on ack
Yes
Check ack
last_word
No
Yes
Ack received
NMACK
NMACK
End ack
Check tx reg
ROFL
One byte left
No
STOP
STATE
Yes
ROFL
No
No
SETUP TX
STATE
Yes
No
rdrx
last_word
tdef <= 1
STOP
STATE
Figure 11. Master Mode Flow Chart – Read and Write States
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9.
SPI INTERFACE
The SPI is a standard 4-pin Serial Peripheral Interface for inter-IC control and communication. It interfaces on one side to the SPI bus and on the other has a standard
register data and interrupt interface. The SPI system can be configured as a master
or a slave device.
During an SPI transfer, data is shifted out and shifted in (transmitted and received)
simultaneously. The I2C_SCLK line synchronizes the shifting and sampling of the
information. It is an output when the SPI is configured as a master and an input
when the SPI is configured as a slave. Selection of an individual slave SPI device is
performed on the slave select line and slave devices that are not selected do not
interfere with the SPI buses.
9.1.
SPI Pins
SPI_MISO – Master In/Slave Out. Serial input in master mode and output in slave
mode.
SPI_MOSI – Master Out/Slave In. Serial output in master mode and input in slave
mode.
SPI_SCK – Serial Clock. Bit clock output in master mode and input in slave mode.
SPI_SSn – Slave Select. Selects SPI CS0 in master mode, chip select input in slave
mode.
In master mode the SPI_SSn pin is controlled via software through the GPIO module. In slave mode the pin is in SPI mode and connects directly to the SPI module.
Note: See Table 234 for SPI pin placements.
9.2.
SPI Registers
9.2.1.
SPI Control Register
HW_SPCSR
BITS LABEL RW
RESET
X:$FFF9
DEFINITION
23:16 RSRVD R
0
Reserved
15:8 DIV
RW 00001010 Divide factor bits – These bits are used to control the frequency of the SPI serial
clock with relation to the device clock. The number must be an even number.
These bits must be set before the SPE or MSTR bits i.e. before the SPI is
configured into master mode.
Note: When the divfact is at a high level and after a transfer finishes it is
changed to a lower level then the new divide factor will not take effect until
the counter has finished counting down from the previous higher divide
factor.
7
MODF
0
Mode fault flag – Mode fault occurs if the SPI system is configured as a master and
the SPI_SSn input line goes to active low. This happens if a second SPI device
becomes a master and selects this device as if it were a slave. Reading the
HW_SPCSR with MODF set automatically clears the MODF flag.
Note: This condition should never exist with the STMP3410 since the SPI_SSn
line is not used as an input in master mode.
6
WCOL
0
Write Collision Error Flag – The WCOL Flag is set if the HW_SPDR is written
before the end of transfer is signaled. WCOL is cleared by reading the
HW_SPCSR with WCOL set, followed by an access of the HW_SPDR.
Table 78. SPI Control Register Description
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BITS LABEL RW
RESET
5
SPIF
0
4
CPHA
0
3
CPOL
0
2
SPIE
0
1
MSTR
0
0
SPE
0
DEFINITION
SPI Transfer Complete Flag – The SPIF Flag is set to a one at the end of an SPI
transfer. SPIF is cleared by an access of the HW_SPDR or by a write to the
HW_SPDR register. The definition of an end of transfer depends on who is the
master and who is the slave.
Clock Phase Select –
Note: There must be a delay of 1/2 the clock period of SCLK, after a toggle of
CPHA or CPOL, before there is a write to the HW_SPDR. This is to
prevent glitches on the SCLK.
Clock Polarity Select –
0 = Active high clocks selected; SCLK idles low.
1 = Active low clocks selected; SCLK idles high.
Note: The SPI_SSn line must be deasserted and reasserted for a change in the
CPOL bit.
SPI interrupts enabled – When the SPIE bit is set SPI Interrupts are enabled and
triggered when the SPIF bit is set.
Master/Slave Select – When the MSTR bit is set the SPI is configured as a master
and when 0 a slave.
SPI System Enable – When SPE is set the SPI system is enabled and, when
cleared, disabled.
Table 78. SPI Control Register Description (Continued)
9.2.2.
SPI Data Register
The SPI interface runs in PIO mode only. Its 8-bit data register is mapped to the X
data address space. Writes to the lower byte of this register are shifted out
SPI_MOSI in Master Mode and SPI_MISO in slave mode. This register is read on
the transaction completion to retrieve the incoming data from SPI_MISO in master
mode and SPI_MOSI in slave mode.
HW_SPDR
BITS
23:8
7:0
LABEL
RW
X:$FFFA
RESET
DEFINITION
RSRVD
R
0
Reserved
SPIDATA RW 00000000
Table 79. SPI Data Register Description
9.3.
Transferring Data over SPI
9.3.1.
Master Mode
In master mode the SPI block must generate the SPI_SCK and send appropriate
data/commands to the slave device(s).
9.3.1.1.
Clock Generation
The clock is the main chip digital clock divided by the divide factor (see above). Out
of reset the SPI_SCK is 24.576/10 ~= 2.5 MHz.
The CPOL (clock polarity) and CPHA (clock phase) bits of the HW_SPCSR are
used to select any of the four combinations of serial clock. These bits must be the
same for both the master and slave SPI devices. The clock polarity bit, selects
either an active high or active low clock but does not affect transfer format. The
clock phase bit selects the transfer format. See Figure 12.
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SPI_SSn
SPI_SCK
CPOL=0, CPHA=0
SPI_SCK
CPOL=0, CPHA=1
SPI_SCK
CPOL=1, CPHA=0
SPI_SCK
CPOL=1, CPHA=1
SPI_MISO
SPI_MOSI
MSB
6
5
4
3
2
1
LSB
Internal Strobe for Data Capture
Figure 12. Timing diagram of SPI signals, including the various SCLK phases
9.3.1.2.
Slave Selects in Master Mode
Multiple peripheral slave devices can be accessed by the STMP3410, using GPIO
pins as chip selects. The chip select pins must be configured as a GPIO outputs by
the STMP3410’s DSP. The system code should contain a setup routine that sets
each chip select to non-asserted (high). Before any peripheral is accessed its chip
select must be asserted (low). The chip select should be de-asserted again before
another peripheral is accessed. The SPI_SSn pin should not be in a low state while
the SPI is used or a mode fault will occur.
9.3.2.
Slave Mode
In slave mode the master device (another chip) generates the clock and slave select
for the STMP3410. The STMP3410 will only receive and transmit data on the
SPI_MISO and SPI_MOSI lines when the SPI_SSn input is asserted low. In this
mode the SPI_SSn line is controlled by the SPI peripheral block.
To initialize the SPI into slave mode, the SPI interrupts are enabled (SPIE=1) and
the Master Mode is left off (MSTR=0). The clock polarity is set and finally the system
is enabled (SPE=1). The master device should start sending a slave select, clock
pulses data. After each byte of data is transferred the SPI will interrupt the processor to receive the incoming data and send a new transmit byte.
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10. ON-CHIP TIMERS
Four timers are implemented, TIO0-TIO3. Two are connected to off-chip pins (TIO0,
TIO1) and the others are used for on-chip functions only. The timers are independently configured through PIO mode registers mapped to the X memory space at
base address X:$F100, X:$F140, X:$F180, and X:$F1C0.
10.1. Using the Timer Modules
10.1.1.
General Programming Guidelines
If you are re-starting a timer from scratch, all relevant fields of the Timer Count and
Timer Control registers should be re-programmed.
The Timer Interrupt Service Routine resets the TimerStatus bit in the Control Register below. The timer will wait until it has expired to assert the interrupt. Otherwise,
the Timer Interrupt Service Routine would run continuously.
Throughout the time when an interrupt occurs, the internal, software-invisible running counter within the module, continues to run (otherwise the timer events will not
occur at periodic intervals). Thus, if an interrupt is not serviced in a timely fashion, it
can become lost - ie, it merges with another interrupt event before the handler can
get to it.
In the default timer clock mode, the timer counts time in terms of DSP clocks. Since
the DSP clock frequency can change based on system activity, this means that the
delays in the timer will adjust accordingly. To allow the timers to operate independently of the DSP clock speed, use one of the crystal clock modes controlled by the
TimerMode field of the Timer Control register. Note, that when using one of the
crystal clock modes, the DSP clock must still be running at a minimum of twice the
clock source rate for correct operation. This means that the DSP clock must be running at a speed of at least crystal clock divided by 2 (or 12.288 when using a
24.576 MHz crystal) when in crystal clock/4 mode. Similarily DSP clock must run at a
speed of at least crystal clock/8 (3.072MHz) when in crystal clock/16 mode, and must
run at a speed of at least crystal clock/32 (768kHz) when in crystal clock/32 mode.
10.1.2.
Software-Visible Programmable I/O (PIO) Register
All register reserved fields should be written with zeroes.
10.1.2.1.
Timer Control Register
This is the module’s control and status register. Note that the timer can be enabled
(TimerEnable bit) and configured in the same PIO write to this register
HW_TMR0CR
HW_TMR1CR
HW_TMR2CR
HW_TMR3CR
BITS
23
LABEL
CLKGT
22:10 RSRVD
RW RESET
RW 0
R
0
X:$F100
X:$F140
X:$F180
X:$F1C0
DEFINITION
Clock gate. Used to disable the clocks to the DAC module to conserve power
when the DAC is not in use. Must be set to 0 before writing to any other DAC
registers.
0Clocks not gated
1Clocks are gated
Reserved
Table 80. Timer Control Register Description
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BITS
LABEL
RW RESET
9:8
TimerMode
RW 00
7
6
5:3
TimerStatus
RSRVD
TimerControl
R
0
R
0
RW 000
2
1
Invert
RW 0
TimerIntEnable RW 0
0
TimerEnable
DEFINITION
Timer clock mode:
00 - Clock source = DSP clock/2
01 - Clock source = crystal clock/4 (requires a DSP clock of at least
crystal clock /2)
crystal clock /8)
crystal clock /32)
Timer status notification
Reserved
Timer Control (mode)
000 - internal clock, downcount, no output
001 - internal clock, downcount, output pulse
010 - internal clock, downcount, output toggle
011 - (reserved)
100 - internal clock, external pulse width measurement
101 - internal clock, external period measurement
110 - external clock, upcount
111 - external clock, downcount
Edge/level inversion selection
Timer interrupt enable
Note: The Interrupt must also be enabled in the Interrupt Collector.
Timer enable
RW 0
Table 80. Timer Control Register Description (Continued)
10.1.2.2.
Timer Count Register
This register is used both to program initial count values and to monitor ongoing
counts, depending on the timer mode.
HW_TMR0CNTR
HW_TMR1CNTR
HW_TMR2CNTR
HW_TMR3CNTR
BITS LABEL RW RESET
23:0
COUNT RW
X:$F101
X:$F141
X:$F181
X:$F1C1
DEFINITION
Count value expressed as the number of periods specified by the TimerMode field of
the HW_TMR0CR/HW_TMR1CR/HW_TMR2CR/HW_TMR3CR registers.
Table 81. Timer Count Register Description
10.1.3.
Timer Modes
10.1.3.1.
Internal Clock Decrement, No Output Clock
(TimerControl = 000)
With the timer enabled (TimerEnable = 1), the running counter is loaded with the
value contained in the Count register. The running counter is decremented every two
system clock cycles (dclk/2). During the dclk cycle following the cycle when the running counter decrements to zero, the TimerStatus bit is set and the module asserts an
interrupt (tio_interrupt output) if the TimerIntEnable field is one. Upon reaching zero,
the running counter is automatically reloaded with the value from the Count register
and the process is repeated until the timer is disabled (TimerEnable = 0).
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10.1.3.2.
Internal Clock Decrement, Output Pulse
This mode is a superset of the Internal Clock, No Output mode (TimerControl =
000). In addition to its functionality, this mode causes the TIO pin to be pulsed by the
timer. The duration of the pulse is two dclk cycles. The pulse begins in the dclk cycle
after the running counter has reached zero. The Invert bit determines the polarity of
the output pulse. If Invert is zero, the TIO pulses high for two cycles; if Invert is one,
TIO pulses low for two cycles.
10.1.3.3.
Internal Clock, Output Toggle
This mode is a superset of the Internal Clock, No Output mode (TimerControl =
000). In addition to its functionality, this mode causes the TIO pin to be toggled by
the timer. At reset (resetn zero) or when the timer is disabled (TimerEnable zero),
the state of the TIO output is identical to the Invert programming field. A toggle of
the TIO output occurs off the dclk rising edge after the running counter has reached
zero.
10.1.3.4.
External Pulse Width Measurement
In this mode the timer samples an external event/clock on the TIO pin. The internal
sampling clock runs at half the internal clock frequency, or dclk/2. This mode measures the duration of high or low pulses on TIO, in terms of dclk/2 periods. If the
Invert bit in the TimerControl register is zero, a TIO-high pulse is measured. If the
Invert bit is set, TIO’s low phase is measured. When the timer is enabled, the running counter is held at zero until a leading timing edge is detected on TIO. Thus if
the timer is enabled in the during TIO’s active phase, no counting begins (this eliminates start-up run counts). At the count-terminating edge of TIO, the running count
value is transfered to the Count PIO register, the TimerStatus bit is set, the running
count register internal to the timer is cleared and an interrupt is optionally asserted
(if the interrupt enable is set). The running count register re-starts on the next leading edge of TIO.
Note that this and the following modes should only be used on the externally accessible timers, TIO0 and TIO1.
10.1.3.5.
External Period Measurement
In this mode the timer samples an external event/clock on the TIO pin. The internal
sampling clock runs at half the internal clock frequency, or dclk/2. This mode measures the period TIO, in dclk/2 periods. The user programs an initial count value in
the Count PIO register. When the timer is enabled, this count value is transferred to
the timer’s running count register. The running count register runs continuously, as
long as the timer is enabled, overflowing to zero without event. At each significant
edge of TIO (rising edge if the Invert bit is zero; falling edge otherwise), the running
count is written to the count register, the TimerStatus bit in the Control register is set
and the timer will optionally interrupt (if the TimerIntEnable bit is set). The user program can read successive values in the Count register to get a running count of
TIO’s clock period, in dclk/2 clock cycles. A user program will probably discard the first
count value, since the timer is enabled at an arbitrary point in the TIO clock cycle.
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10.1.3.6.
External Clock Increment
In this mode, the timer counts external clock cycles. When the timer is enabled (TimerEnable = 1), the one’s complement of the value in the Count register is transfered
to the running count register. The running counter is incremented by transitions on
the incoming clock (tio_in). If the Invert bit is zero, the running count register increments on 0-to-1 transitions of tio_in; otherwise it increments on 1-to-0 transitions. At
each update of the running count register, the software-visible Count register is also
updated. The running counter counts continuously through its overflow condition (all
ones to all zeroes). At the transition after the running counter has transitioned to
zero, the TimerStatus bit is set; and if interrupts are enabled, the tio_interrupt output
is asserted.
10.1.3.7.
External Clock Decrement
In this mode, the timer counts external clock cycles. When the timer is enabled (TimerEnable = 1), the value in the Count register is transfered to the running count register. The running counter is decremented by transitions on the incoming clock
(tio_in). If the Invert bit is zero, the running count register decrements on 0-to-1 transitions of tio_in; otherwise it decrements on 1-to-0 transitions. On the transition after
the running count register has reached zero, the TimerStatus bit is set, the
tio_interrupt is asserted (if the TimerIntEnable bit is set) and the running count register is re-loaded with the value from the Count register.
10.1.4.
AC Timing Considerations
When a timer module counts off an external clock, its running counter increments
every other dclk cycle. Design reuse methodology forces an external clock (TIO)
sampling scheme whereby the external clock is sampled into the dclk domain and
its edges are then detected. This combination of Nyquist and dclk/2 counting means
that the external clock must run at most one fourth as fast as the system clock, or
dclk/4 frequency. In practice, the external clock frequency needs to be even lower
than this because of the timer interrupt service or polling overhead. For instance if
the timer is placed in a mode to measure the pulse width of an external clock or
event, the period of such events must be long enough to give the interrupt handler
enough time to read the timer’s Count register and record the sampled count.
PARAMETER
SYMBOL
MIN
MAX
UNIT
tdcyc
tresh
tresh
5 (note 1)
300
1.2
1000
-
ns
ps
ns
dclk Clock Period
Reset De-Assertion Hold Time (note 2)
Reset De-Assertion Setup Time
Table 82. AC Timing for DSP Interface
Note:
1. Maximum frequency imposed by edge counter sizes
2. Assertion of reset is asynchronous to dclk
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11. SDRAM INTERFACE
11.1. SDRAM Interface Registers
The SDRAM interface is a DSP configurable interface to external SDRAM. The
interface will connect to any combination of SDRAMs. The addressing scheme by
the interface will allow connections to 64 Mbit, 128 Mbit, or 256 Mbit SDRAMs. The
data connection will allow transfers of 8-bit or 16-bit according to the external connection. The rate of data transfers and all SDRAM activities is programmable from a
divide by one to fifteen of the system clock. The SDRAM timing specifications are
also programmable based on this rate. Read or write accesses to SDRAM data can
be done through linear or modulo addressing.
Internally the SDRAM interface will tranfer data to/from the system X/Y/P memory
(aka system memory) and is accesable in a linear or modulo address mode. Data
transfers can be programmable to any combination of data packing and unpacking
to/from system memory dependent on 8-bit or 16-bit external SDRAM connection.
The most feature intensive connection is the 8-bit SDRAM connection.
In 8-bit transfers of SDRAM data to/from system memory (24-bit bus), the interface
is programmable to pack the data into 3-byte words, 2-byte words, or 1-byte words
during reads from SDRAM and is programmable to unpack with the same capability
as during writes to SDRAM. Transfering 2-byte words into system memory can be
programmed to be left aligned or right aligned to the 24-bit memory. When left
aligned the least significant byte is zeroed and when right aligned the most significant byte can be zeroed or sign extended. Transfering 1-byte words into a 24-bit
system memory will result in the data residing in the most significant byte and other
two bytes will be zeroed. The interface can be programmed to pick the byte to start
transfering data to/from system memory. Writes to SDRAM can be configured to
read from the system memory in a Big Endian or Little Endian (default) pattern.
11.1.1.
SDRAM Address Pointer 1 Register
SDRAM low address is the programmed address of the SDRAM. The interface will
accordingly place the corresponding values during the RAS and CAS cycles. The
64 Mb SDRAM with 16-bit connection will use bits 21-0. The 64 Mb SDRAM with 8bit connection will use bits 22-0. The 128/256 Mb SDRAM with 16-bit connection will
use bits 23-0. The special case of 128/256 Mb SDRAM with 8-bit connection will use
bits 23-0 and bit 0 of HW_SDRAM_ADDR2. At the end of a transfer, an incremented
address will be placed in this register.
HW_SDRAM_ADDR1 X:$F901
BITS LABEL RW RESET
23:0
A1
DEFINITION
RW 0
Table 83. SDRAM Address Pointer 1 Register Description
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11.1.2.
SDRAM Address Pointer 2 Register
SDRAM high address contains the continuation of the SDRAM. Bit 0 of the
HW_SDRAM_ADDR2 is the continuation of the SDRAM address for
128 Mb/256 Mb with 8-bit connection. At the end of a transfer, the next address will
be placed in this register.
HW_SDRAM_ADDR2 X:$F902
BITS LABEL RW RESET
23:1
0
DEFINITION
RSRVD R
0
A1
RW 0
Table 84. SDRAM Address Pointer 2 Register Description
11.1.3.
SDRAM System Address Pointer Register
SDRAM system address contains the system memory address. This is used with the
corresponding dma_asel (HW_SDRAM_CSR[11:10]) to choose reading/writing from
X/Y/P memories. At the end of a transfer, the next address will be placed in this register.
HW_SDRAM_SYSADDR X:$F903
BITS LABEL RW RESET
DEFINITION
23:16 RSRVD R
0
15:0 A1
RW 0
Table 85. System Address Pointer Register1 Description
11.1.4.
SDRAM Size Register
SDRAM size register contains the number of transfers to/from system memory
from/to the SDRAM. In the case of 8-bit SDRAM connection, it is the number of
bytes to be transfered. In the case of 16-bit SDRAM connection, it is the number of
two byte words to be transfered.
HW_SDRAM_SIZE
X:$F904
BITS LABEL RW RESET
23:18 RSRVD R
0
17:0 SIZE
RW 0
DEFINITION
Table 86. SDRAM Size Register Description
11.1.5.
SDRAM Timer 1 Register
SDRAM timer register programs the delays as specified in the SDRAM specifications in relation to the number of cycles of sdram clocks. SDRAM clock is a divided
version of system clock. HW_SDRAM_TIMER1 programs the number of sdram
clock cycles for the initialization delay for SDRAM, delay from a precharge command to the next command (tRP), and delay from refresh command to the next
command (tRFC).
HW_SDRAM_TIMER1 X:$F905
BITS
23:20
19:16
15:0
LABEL
TRFC
TRP
INIT
RW
RW
RW
RW
RESET
6/$6
2/$2
15000/$
3A98
DEFINITION
Refresh to next command. Value should be greater or equal to 70ns/(sdram period).
Precharge to next command. Value should be greater or equal to 20ns/(sdram period).
Initialization of SDRAM from when sdram enable is activated in HW_SDRAM_CSR[0].
Value should be greater or equal to 200us/(sdram period).
Table 87. SDRAM Timer 1 Register Description
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11.1.6.
SDRAM Timer 2 Register
SDRAM timer register programs the delays as specified in the SDRAM specifications in relation to the number of cycles of sdram clocks. HW_SDRAM_TIMER2 programs the number of cycles in between the row and bank activate (ACTIVE)
command to the next command (tRCD), the number of cycles in between each
refresh commands (tREF/4096), and the number of cycles in between exiting low
power mode SELF REFRESH to the next ACTIVE command (tXSR).
HW_SDRAM_TIMER2 X:$F906
BITS LABEL RW
RESET
DEFINITION
23:20 RSRVD R
0
19:16 TRCD RW 2/$2
15:4
TREF
3:0
TXSR
Reserved
ACTIVE to next command. Value should be greater or equal to 20ns/(system
period).
RW 375/$117 Refresh interval. Within SDRAM spec the refresh interval for 4096 rows is 64ms
thus a refresh must be done every 15us (64ms/4096). Thus this value should be
greater or equal to 15us/(system period).
RW 6/$6
Exiting self refresh mode to next command. Value should be greater or equal to
80ns/(system period).
Table 88. SDRAM Timer 2 Register Description
11.1.7.
System Memory Modulo Base Address Register
HW_SDRAM_BAR programs the base address for system modulo access. The
companion register is the DSP modulo register HW_SDRAM_MR. Once the system
access matches the address created by adding the HW_SDRAM_BAR and
HW_SDRAM_MR it returns to the HW_SDRAM_BAR address for the next access.
HW_SDRAM_BAR
X:$F907
BITS LABEL RW RESET
DEFINITION
23:16 RSRVD
15:0 BAR
RW 0
Table 89. System Memory Modulo Base Address Register Description
11.1.8.
System Memory Modulo Register
HW_SDRAM_MR programs the modulo offset for system modulo access. The companion register is the DSP modulo base adress register HW_SDRAM_BAR. The offset value
is added to the HW_SDRAM_BAR to the determine the limits of the modulo buffer.
HW_SDRAM_MR
X:$F908
BITS LABEL RW RESET
DEFINITION
23:16 RSRVD
Reserved
15:0 MOD
RW $00FFFF Modulo offset 1-FFFE. If 0000 or FFFF is programmed system access will be linear.
Table 90. System Memory Modulo Register Description
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11.1.9.
SDRAM Memory Modulo Base Address 1 Register
HW_SDRAM_DBAR1 holds the lower base address for modulo access in SDRAM
memory. The companion register is offset registers HW_SDRAM_DMR1 and
HW_SDRAM_DMR2. Once SDRAM address reaches the offset specified in
HW_SDRAM_DMR1 and HW_SDRAM_DMR2 the address will return to the base
address specified in HW_SDRAM_DBAR1 and HW_SDRAM_DBAR2.
HW_SDRAM_DBAR1 X:$F909
BITS LABEL RW RESET
23:0
DBAR
DEFINITION
RW 0
Table 91. SDRAM Memory Modulo Base Address 1 Register Description
11.1.10. SDRAM Memory Modulo Base Address 2 Register
HW_SDRAM_DBAR2 holds the upper base address for modulo access in SDRAM
memory. The companion register is offset registers HW_SDRAM_DMR1 and
HW_SDRAM_DMR2. Once SDRAM address reaches the offset specified in
HW_SDRAM_DMR1 and HW_SDRAM_DMR2 the address will return to the base
address specified in HW_SDRAM_DBAR1 and HW_SDRAM_DBAR2
HW_SDRAM_DBAR2 X:$F90A
BITS LABEL RW RESET
23:1 RSRVD
0
DBAR24 RW 0
DEFINITION
Table 92. SDRAM Memory Modulo Base Address 2 Register Description
11.1.11. SDRAM Memory Modulo 1 Register
HW_SDRAM_DMR1 holds the lower offset for modulo access in SDRAM memory.
The companion register is the base address registers (HW_SDRAM_DBAR1 and
HW_SDRAM_DBAR2). Once SDRAM address access reaches the offset specified
by this register and HW_SDRAM_DMR2 the SDRAM address will return to the
value set in the base address register.
HW_SDRAM_DMR1 X:$F90B
BITS LABEL RW RESET
23:0 DMR
RW
DEFINITION
Table 93. SDRAM Memory Modulo 1 Register Description
11.1.12. SDRAM Memory Modulo 2 Register
HW_SDRAM_DMR2 holds the upper offset for modulo access in SDRAM memory.
The companion register is the base address registers (HW_SDRAM_DBAR1 and
HW_SDRAM_DBAR2). Once SDRAM address access reaches the offset specified
by this register and HW_SDRAM_DMR1 the SDRAM address will return to the
value set in the base address register.
HW_SDRAM_DMR2 X:$F90C
BITS LABEL RW RESET
DEFINITION
23:1 RSRVD
0
DMR
RW 0
Table 94. SDRAM Memory Modulo 2 Register Description
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11.1.13. SDRAM Transfer Count Register
HW_SDRAM_CNT holds the value of the number of transfers to and from the
SDRAM at the end of the transfer. (READ ONLY)
HW_SDRAM_CNT
X:$F90D
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 CNT
R
0
Number of transfers completed.
DEFINITION
Table 95. SDRAM Transfer Count Register Description
11.1.14. SDRAM Mode Register
HW_SDRAM_MODE holds the value of the Mode register to be programmed into the
SDRAM during initialization. This register is to accomedate future SDRAM capabilities
but is defaulted to a sequential full page burst mode with a CAS latency of two.
HW_SDRAM_MODE X:$F90E
BITS LABEL RW RESET
DEFINITION
23:13 RSRVD R
0
Reserved
12:0 NADDR R
$0027 Holds the value to be place into the Mode Register of the SDRAM.
Defaults to sequential full page burst mode with a CAS latency of 2
Table 96. SDRAM Mode Register Description
11.1.15. SDRAM Type Register
HW_SDRAM_TYPE configures the interface to handle the SDRAM types. The different SDRAM configuration differ from each other by the amount of address bits
used during column and row commands. This interface will be able to access
64 Mb, 128 Mb, and 256 Mb SDRAM with 8 or 16 data bus.
HW_SDRAM_TYPE
X:$F90F
BITS LABEL RW RESET
DEFINITION
23:3 RSRVD R
0
Reserved
2
TYPE2 RW 0
Row Address range 12:0 when TYPE2 = 1, Row Address range 11:0 when TYPE2 =
0. TYPE2 = 1 is used for 256 Mb SDRAM
1:0
TYPE
RW 01
Column Address range 7:0 when TYPE1:0 = 00 , Column Address range 8:0 when
TYPE1:0 = 01 , Column Address range 9:0 when TYPE1:0 = 10
256 Mbit 16-bit data connection : TYPE =01 128 Mbit 8-bit data connection: TYPE =10
256 Mbit 8-bit data connection : TYPE= 10 64 Mbit 16-bit data connection: TYPE =00
128 Mbit 16-bit data connection: TYPE =01 64 Mbit 8-bit data connection: TYPE =01
Table 97. SDRAM Mode Register Description
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11.1.16. SDRAM Control Status Register
HW_SDRAM_CSR
BITS
LABEL
RW RESET
23
22
SIGN
SDRAM
RW 0
RW 0
21
MULTI
RW 0
20:17 DIV
16
UKICK
RW 0001
RW 0
15:13 ASIZE
RW 0
X:$F900
DEFINITION
Sign Extend bit for SDRAM right align reads.
External bus muxing control. SDRAM address, control, and data buses are shared
with the EMC5600. Setting this signal allows the SDRAM to have control. Default is
EMC control.
Multiple external SDRAM mode. This gives up control of the CSB signal after
initializtion so that it can be controlled by the GPIO’s when there is multiple SDRAMs.
Clock divide. Allows clock to SDRAM to be divisible from 1 to 15 of system clock.
Unkick- Writing a one will cleanly stop the current transfer. A transfer halted by
Unkick will not interrupt the DSP. After the current transfer stops succefully Unkick
will clear.
Align and Connection size - Controls how bytes or 2-byte words are read or written
into system memory. During write to the system memory the byte data can packed
onto the 24-bit bus as 3 bytes or 2 bytes or 1 byte. Packing 3 bytes will default
starting at the least significant byte. Packing 2 bytes can have two options : left
aligned or right aligned. Left aligned will result in the least significant byte assigned
equal to zero. The default starting byte is the middle byte (byte 1). Right aligned will
result in the most significant bytes assigned a sign extension of bit[15] of the data if
the sign extend bit the HW_SDRAM_CSR is set else the most significant bytes will
be zeroed. The default starting byte is the least significant byte (byte 0). Packing 1
byte will place the data at the most significant byte of the bus and the lower two
bytes will be zeroed. During read from the system memory, data written to the
SDRAM will be taken in the same placement as previously described and the zeroed
and sign extended data will not be transfered to the SDRAM.
For 2-byte words (or 16-bit connection to SDRAM data bus) there is the two options
of left aligned or right aligned. For left aligned write to system memory the data will
occupy the two most significant bytes of the bus while the least significant byte will
be zeroed. For right aligned write to system memory the data will occupy the two
least significant bytes of the bus while the most significant byte will have the option
of sign extending bit[15] or zeroing. For reads from system memory the word data
transfered to the 16-bit SDRAM data bus will have the same alignment mentioned
above. The zeroed and sign extended data will not be transfered to the SDRAM. Bit
ASIZE2 will be used to differentiate between 8-bit or 16-bit data connection to
SDRAM.
12
BIGE
RW 0
ASIZE[2:0] = 000 8-bit connection, pack 3 bytes onto system bus (DEFAULT).
ASIZE[2:0] = 001 8-bit connection, pack 2 bytes onto system bus with left alignment.
ASIZE[2:0] = 010 8-bit connection, pack 2 bytes onto system bus with right
alignment.
ASIZE[2:0] = 011 8-bit connection, pack 1 byte onto system bus.
ASIZE[2:0] =100 16-bit connection, pack 2 bytes onto system with left alignment.
ASIZE[2:0] = 101 16-bit connection, pack 2 bytes onto system with right alignment.
Note: ASIZE[2] will differentiate between 8-bit or 16-bit connection.
Big Endian - Controls data is read from system memory and written to SDRAM
memory. In big endian mode the most significant byte is transfered first, followed
byte the next most significant bytes. Little Endian is the DEFAULT and the least
significant byte is transferred first, followed byte the next least significant byte. Only
is valid for 2 or 3 byte transfers.
Table 98. SDRAM Control Status Register Description
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BITS
LABEL
RW RESET
11:10 MEM
RW 00
9:8
SBYTE
RW 00
7
6
RES
PWDN
RW 0
RW 0
5
ISTAT
RW 0
4
LM
RW 0
3
KICK
RW 0
2
RNW
RW 0
1
0
IE
RW 0
SDRAMEN RW 0
DEFINITION
Memory select - Chooses X/Y/P memory to write or read data.
MEM = 00 X memory
MEM = 01 Y memory
MEM = 10 P memory
Start Byte - Start read or write transfer on bytes 0 or 1 or 2. These control bits are
closely tied to the Align and Connection Size (ASIZE) control bits.
If ASIZE = 0 start byte can be 0,1,2
If ASIZE = 1 start byte can be 1,2
If ASIZE = 2 start byte can be 0,1
If ASIZE = 3 start byte can 2
Reserved
Powerdown - Will set the SDRAM into self refresh mode then shut off clocks to the
SDRAM and this interface.
Interrupt Status - Reading a one indicates pending interrupt, writing back a one will
clear interrupt and writing a zero has no effect.
Load Mode - loads value of LOAD MODE register into Mode register of SDRAM.
After the SDRAMMODE value is loaded into SDRAM LM will clear.
Kick writing one will start transfer. After successful completion kick will clear and
interrupt the DSP.
Read not write - writing one will read data from SDRAM to system memory, writing
zero will write data to SDRAM from system memory
Interrupt Enable
SDRAM Enable Bit – The SDRAM bit enables the SDRAM port. This bit must be set
after the DIV bits are set and any other SDRAM registers are written to. This allows
the divided clocks to the SDRAM to stabilize.
Table 98. SDRAM Control Status Register Description (Continued)
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12. SWIZZLE
12.1. SWIZZLE Registers
The SWIZZLE block is a DSP configurable module that is used to manipulate programmed data or data within memory. One or two immediate words can be programmed into the module for manipulation. The resulting data can be read in the
SWIZZLE registers. SWIZZLE features include Endianess, bit reversing, returning
only specific bytes or words with the data sign extended or zeroed, and barrel shifting left or right.
The SWIZZLE block also can be used to manipulate data within X/Y/P memory.
Data can be changed in place or changed then move to a different memory location.
12.1.1.
SWIZZLE Control and Status Register 1
SWIZZLE CSR1 controls the basic function of the module and the DSP programmable manipulation.
HW_SWIZZLECS1R X:$F380
BITS
LABEL
RW RESET
23:11 RSRVD
R
0
10
NEWADD RW 0
9
CLK_OFF RW 0
8
MEM
RW 0
7:4
SHIFT
RW 0000
3
SIGN
RW 0
2
LNR
RW 0
1
LA
RW 0
0
EN
RW 0
DEFINITION
Reserved
Place data into new memory location. If this bit is cleared, the value in the
HW_SWIZZLEDESTADDRR register is ignored.
0 = Manipulate data in memory without moving it
1 = Manipulate data in memory and put it in a new location
Turn clocks off. Clocks must be turned on before any other registers can be
accessed.
0 = SWIZZLE clocks turned on
1 = SWIZZLE clocks turned off
Manipulate data in memory. The SWIZZLE block can be used to manipulate data
written into the HW_SWIZZLEDATA0 & HW_SWIZZLEDATA2R registers, or can be
used to manipulate blocks of data in on-chip memory. If this bit is clear, then the
data in the HW_SWIZZLESOURCER, HW_SWIZZLEDESTADDRR, &
HW_SWIZZLESIZER registers are ignored.
0 = Manipulate data in registers
1 = Manipulate data in memory
Barrel Shift from 0 to 15. Due to a silicon bug, only values in the range 0000 to
0111 operate correctly. To achieve a larger barrel shift, use the LNW bit to switch
the direction of the barrel shift and adjust the SHIFT value to compensate.
Sign extend data of pass_lsB,isB,msB modes
0 = Data is not sign-extended
1 = Data is sign-extended
Left barrel shift. Used in conjuction with the SHIFT field of this register.
0 = Barrel shift to the right
1 = Barrel shift to the left
Left Align data of pass_LSB, ISB, MSB modes. Default is the data is right aligned
with the 24-bit memory bus.
SWIZZLE enable
Table 99. SWIZZLE Control and Status Register 1 Description
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12.1.2.
SWIZZLE Control and Status Register 2
SWIZZLE CSR2 is the rest of the controls to manipulate of data in memory.
HW_SWIZZLECS2R X:$F381
BITS
LABEL
RW RESET
23:16 RSRVD
15
UNKICK
R
0
RW 0
14:13 SBYTE
RW 00
12
BS_EN
RW 0
11
P16I
RW 0
10
P16L
RW 0
9
PMSB
RW 0
8
PISB
RW 0
7
PLSB
RW 0
6
BITREV
RW 0
5
BIGE
RW 0
4:3
DESASEL RW 00
2:1
SASEL
RW 00
0
KICK
RW 0
DEFINITION
Reserved
Will halt memory swizzling. Will return to zero after successful halt. Address of the
next SWIZZLE will be located in HW_SWIZZLESOURCER and
HW_SWIZZLEDESTADDRR
Start byte - words can be shifted by byte when data has a different destination.
Default is no shifting thus the SBYTE = 00
Barrel shift enable. In memory swizzling mode this used in conjuction CSR1 SHIFT
bits.
Pass Intermediate Significant word enable. In memory SWIZZLE mode this will
take the input word and only return the most significant and middle byte. Used in
conjuction with SIGN bit of CSR1.
Pass Least Significant word enable. In memory SWIZZLE mode this will take the
input word and only return the middle and least significant byte. Used in conjuction
with SIGN bit of CSR1.
Pass Most Significant byte enable. In memory SWIZZLE mode this will take the
input word and only return the most significant byte. The end location will have this
byte in the least significant byte position of the 24-bit word. Used in conjuction with
the SIGN bit of the CSR1.
Pass Intermediate byte enable. In memory SWIZZLE mode this will take the input
word and only return the middle byte. The end location will have this byte in the
least significant byte position of the 24-bit word. Used in conjuction with the SIGN
bit of the CSR1.
Pass Least Significant byte enable. In memory SWIZZLE mode this will take the
input word and only return the least significant byte. The end location will have this
byte in the least significant byte position of the 24-bit word. Used in conjuction with
the SIGN bit of the CSR1.
Bit Reversed enable. In memory SWIZZLE mode this will take the input word and
24-bit reverse data to the resulting location.
Big Endian enable. In memory SWIZZLE mode this will take the input word and
change to Big Endian word.
Destination Memory select - Chooses X/Y/P memory to write or read data.
00
X space
01
Y space
10
P space
11
Reserved
Source Memory select - Chooses X/Y/P memory to write or read data.
00
X space
01
Y space
10
P space
11
Reserved
Kick bit. Writing one will start transfer. After successful completion kick will clear.
Table 100. SWIZZLE Control and Status Register 2 Description
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12.1.3.
SWIZZLE Transfer Size
Number of words to be swizzled.
HW_SWIZZLESIZER X:$F382
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 SIZE
RW $0000
DEFINITION
Reserved
Number of words of memory to be manipulated by the SWIZZLE module.
Table 101. SWIZZLE Transfer Size Description
12.1.4.
SWIZZLE Source Address Register
Source address for memory manipulation mode. Used in conjuction with CSR1
Memory mode enable.
HW_SWIZZLESOURCER X:$F383
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 ADD
RW $0000
DEFINITION
Reserved
Source address of the data in memory to be manipulated by the SWIZZLE module.
Table 102. SWIZZLE Source Address Register Description
12.1.5.
SWIZZLE DATA1 Register
DSP programmed data to be swizzled and placed on output SWIZZLE registers
HW_SWIZZLEDATA1R X:$F384
BITS LABEL RW RESET
23:0
DAT
DEFINITION
RW $000000
Table 103. SWIZZLE DATA1 Register Description
12.1.6.
SWIZZLE DATA2 Register
DSP programmed data to be swizzled and placed on output SWIZZLE registers.
This is used only for resulting data for the HW_SWIZZLEPASSMSWR register.
HW_SWIZZLEDATA2R X:$F385
BITS LABEL RW RESET
23:0
DAT
DEFINITION
RW $000000
Table 104. SWIZZLE DATA2 Register Description
12.1.7.
SWIZZLE Destination Address Register
SWIZZLE destination address in memory mode.
HW_SWIZZLEDESTADDRR X:$F386
BITS LABEL RW RESET
23:16 RSVD
15:0 ADR
R
0
RW $0000
DEFINITION
Reserved
Destination address for memory based SWIZZLE operations.
Table 105. SWIZZLE Destination Address Register Description
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12.1.8.
SWIZZLE Big Endian Register
Results of data programed into the HW_SWIZZLEDATA1R register. Used in conjuction with the memmode of the HW_SWIZZLECS1R.
HW_SWIZZLEBIGENDIANR X:$F387
BITS LABEL RW RESET
23:0
DAT
DEFINITION
R
Table 106. SWIZZLE Big Endian Register Description
12.1.9.
SWIZZLE Bit Reversed Register
HW_SWIZZLEBITREVR X:$F388
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 107. SWIZZLE Bit Reversed Register Description
12.1.10. SWIZZLE Pass Least Significant Byte Register
HW_SWIZZLEPASSLSBR X:$F389
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 108. SWIZZLE Pass Least Significant Byte Register Description
12.1.11. SWIZZLE Pass Intermediate Significant Byte Register
HW_SWIZZLEPASSISBR X:$F38A
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 109. SWIZZLE Pass Intermediate Significant Byte Register Description
12.1.12. SWIZZLE Pass Most Significant Byte Register
HW_SWIZZLEPASSMSBR X:$F38B
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 110. SWIZZLE Pass Most Significant Byte Register Description
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12.1.13. SWIZZLE Pass Least Significant Word Register
HW_SWIZZLEPASSLSWR X:$F38C
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 111. SWIZZLE Pass Least Significant Word Register Description
12.1.14. SWIZZLE Pass Intermediate Significant Word Register
HW_SWIZZLEPASSISWR X:$F38D
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 112. SWIZZLE Pass Intermediate Significant Word Register Description
12.1.15. SWIZZLE Pass Most Significant Word Register
Results of data programed into the HW_SWIZZLEDATA1R register. Used in conjuction with the memmode of the HW_SWIZZLECS1R and the HW_SWIZZLEDATA2R
register.
HW_SWIZZLEPASSMSWR X:$F38E
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 113. SWIZZLE Pass Most Significant Word Register Description
12.1.16. SWIZZLE Barrel Shift Register
Results of data programed into the HW_SWIZZLEDATA1R register. Used in conjuction with SHIFT field of the HW_SWIZZLECS1R register.
HW_SWIZZLEBARRELR X:$F38F
BITS LABEL RW RESET
23:0
DAT
R
DEFINITION
$000000
Table 114. SWIZZLE Barrel Shift Register Description
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12.2. SWIZZLE Data Manipulation Examples
Example 1
Setting these register values
HW_SWIZZLEDATA1R
HW_SWIZZLEDATA2R
HW_SWIZZLECS1R
Yields these register values
HW_SWIZZLEBIGENDIANR
HW_SWIZZLEBITREVR
HW_SWIZZLEPASSLSBR
HW_SWIZZLEPASSISBR
HW_SWIZZLEPASSMSBR
HW_SWIZZLEPASSLSWR
HW_SWIZZLEPASSISWR
HW_SWIZZLEPASSMSWR
HW_SWIZZLEBARRELR
C
2
0
D
3
0
Example 2
A
0
0
B
1
0
E
4
0
F
5
1
A
0
0
E
F
0
0
0
0
0
0
A
F
C
D
A
7
B
3
D
0
0
0
E
0
0
0
C
0
0
0
A
0
C
D
E
0
A
B
C
0
4
5
A
B
C
D
E
No sign extension
No barrel shift
B
5
F
D
B
F
D
B
F
E
F
F
F
F
F
F
0
F
B
1
0
C
2
0
D
3
0
E
4
4
D
5
9
F
C
B
A
B
7
B
3
D
5
F
F
F
E
F
F
F
F
C
D
F
F
F
A
B
F
C
D
E
F
F
A
B
C
D
0
4
5
A
B
A
B
C
D
E
Sign extension on
Barrel shift to the right by 4 bits
Table 115. Examples of the Data Manipulations Supported by the SWIZZLE Module
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13. REAL-TIME CLOCK/WATCHDOG RESET
13.1. Real-Time Clock Registers
The real-time clock is a DSP-accessable, continuously running 42-bit millisecond
count. A 42-millisecond has enough resolution to count up to 139 years with millisecond accuracy. The RTC will continue to count time as long as a voltage is
applied to the BATT pin, irrespective of whether the rest of the STMP3410 is powered up. Reset has no effect on the RTC registers. This hardware assumes a
24.576 MHz crystal is being used. If a different speed crystal is used, then the times
measured by this block should be scaled up or down according to the crystal speed.
The register-set is composed of two 24-bit registers which must be read in a specific
order to prevent mismatches between the upper and lower words. The upper data
word (18-bits valid right justified) must be accessed before the lower data-word (24bits). Before either of these registers can be accessed, the CKRST bit of the
HW_CCR Clock control register must be set to 1. The CKRST bit can be set at any
time, but in order to not corrupt the time value stored in the RTC, the CKRST bit
must be cleared at a safe time, within 0.5ms of when the HW_RTCLOW register
updates. Note that the CKRST bit is also cleared by a system shutdown (either
intentional because the PWDN bit of the HW_CCR register is set, or unintentional
because of battery failure). Finally, the CKRST bit is cleared by a system reset (generated by writing 1101 to the SRST field of the HW_RCR register). The following
code segment shows how to clear the CKRST bit safely.
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Disable all interrupts
bset
#9,sr
; Disable all interrupts
bset
#8,sr
move
#$0,x0
movep
x0,x:HW_IPR
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Turn off the PLL & as many clocks as possible
move
#$000001,x0
; Don’t turn off CKRST yet
move
x0,x:HW_CCR
; dclk = xtal_clk = 24.576MHz
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Read the RTC once
move
#$0,b
; Make sure that b2, & b0 are zero
move
X:HW_RTCUP,b
; Must read HW_RTCUP first
move
X:HW_RTCLOW,b
; Must read HW_RTCLOW last
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Wait for the RTC to change
wait_rtc
do
#3,_rtc_loop
; Delay loop for 12 cycles
rep
#4
;
nop
;
_rtc_loop
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Read the RTC again
move
#$0,a
; Make sure that a2, & a0 are zero
move
X:HW_RTCUP,a
; Must read HW_RTCUP first
move
X:HW_RTCLOW,a
; Must read HW_RTCLOW last
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; Compare the RTC values
sub b,a
jeq wait_rtc
; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; ;; It is finally safe to turn off CKRST
move
#$000000,x0
;
move
x0,x:HW_CCR
; dclk = xtal_clk = 24.576MHz
rts
nop
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13.1.1.
RTC Upper Data Word
Contains the upper data word (18 bits) of the RTC millisecond count.
HW_RTCUP
X:$F501
BITS LABEL RW RESET
DEFINITION
23:18 RSRVD R
0
Reserved
17:0 RTC
RW 0
Bits 41:25 of the RTC millisecond counter. This field initializes to a random value, and
continues to count millisecond as long as the battery power is applied, regardless of
whether the STMP3410 is powered up or down.
Table 116. RTC Upper Data Word Description
13.1.2.
RTC Lower Data Word
Contains the lower data word (24 bits) of the RTC millisecond count
HW_RTCLOW
X:$F500
BITS LABEL RW RESET
DEFINITION
23:0 RTC
RW 0
Bits [23:0] of the RTC millisecond counter. This field initializes to a random value, and
continues to count millisecond as long as the battery power is applied, regardless of
whether the STMP3410 is powered up or down.
Table 117. RTC Lower Data Word Description
13.2. Watchdog Reset Timer Registers
The watchdog reset timer is a DSP configurable device. Programmed by software to
generate a RESET after HW_WATCHDOGCNTR milliseconds, the module will generate this reset if software does not re-write this register before this time elapses.
This module assumes a 24.576 MHz crystal. If a different speed crystal is used, the
time delay before a watchdog reset is generated will scale up or down with the crystal speed.
The WATCHDOG TIMER is initially disabled and set to count 256-milliseconds
before generating a watchdog reset.
13.2.1.
Watchdog Count Register
This register contains the 8-bit delay (expressed in milliseconds) after which the
watchdog timer will reset the device when the watchdog timer is enabled.
HW_WATCHDOGCNTR X:$F502
BITS
LABEL RW RESET
DEFINITION
23:12 RSRVD
R
0
Reserved
11:0 WDT_CNT RW $FFF
The number of milliseconds before a watchdog reset is initiated. This counter only
decrements when the watchdog timer is enabled. Due to a silicon bug, only bits
[7:0] of this field can be written by the DSP, other bits are set to 0’s by DSP write.
Table 118. Watchdog Reset Count Register Description
13.2.2.
Watchdog Reset Enable Register
This register contains the enable bit for the watchdog module.
HW_WATCHDOGENR X:$F503
BITS LABEL RW RESET
23:1 RSRVD R
0
Reserved
0
WDT_EN RW 0
Enable for the watchdog timer
DEFINITION
Table 119. Watchdog Reset Enable Register Description
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14. CDSYNC INTERFACE
14.1. CDSYNC Interface Registers
The CDSYNC module is a DSP accessible module which processes CD audio and
CDROM data coming from the I2S-block. Data is parsed for a SYNC frame, descrambled, checked for CRC errors, and written to memory through DMA-transfer.
The CDSYNC is configurable through 6-registers which must be properly set before
any I2S data is received.
14.1.1.
CDSYNC Control Status Register
Provides control over many of the functions of the CDSYNC.
HW_CDSYNCCSR
BITS
23
22
LABEL
RESET
INWRDLEN
RW RESET
RW 1
RW 0
21:20 OUTWRDLEN RW 00
19
INPUTMSB
RW 0
18
MODE1
RW 0
17:13 RSRVD
12
DMAOF
R
0
RW 0
11
SYNC
RW 0
10
LOS
RW 0
9
EDC
RW 0
8
DMADONE
RW 0
7
6
5
4
3
SYNCIRQEN
LOSIRQEN
EDCIRQEN
DMAIRQEN
SYNCEN
RW
RW
RW
RW
RW
0
0
0
0
0
X:$F600
DEFINITION
Software Reset. Software reset and low power mode enable
Input Word Length. Specifies the number of IDR bits that are valid:
016-bits
124-bits
NOTE: no calculations are performed in 24-bit mode
Output Word Length. Specifies the number of bits packed into each DMA data
word. Unused bits are zero.
Input MSB.
0use IDR bits 15:0
1use IDR bits 23:8
NOTE: ignored in 24-bit input mode(CTL[22] = 1)
Force Mode 1. When active(1) the CDSYNC will assume that all CDROM
sectors are mode 01 and will perform calculations on them.
When inactive(0), the CDSYNC extracts the type field from the sector- data and
only does de-scrambling and CRC checking if mode = 01
Reserved bits
DMA Overflow. Indicates that a DMA overflow exists. exception will be
generated if enabled. Must write a ‘1’ to clear this flag.
Detect Interrupt. Indicates that a CDROM sync pattern has been detected and
that the header has been written to memory. An interrupt will be triggered if
enabled. Must write a ‘1’ to clear this flag.
Loss of Interrupt. indicates that an unexpected SYNC pattern has been
detected or that an expected sync pattern has not been detected. An interrupt
will be generated if enabled. Must write a ‘1’ to clear.
EDC Interrupt. CRC miscompare interrupt status bit: indicates that the
calculated CRC does not match the ECDC field of the CDROM sector. An
interrupt will be generated if enabled. Must write a ‘1’ to clear this flag.
DMA Done Interrupt. indicates that the requested DMA-block transfer is complete
(WCR = 0). An interrupt will be generated if enabled. Must write a ‘1’ to clear this flag
Detector Interrupt Enable: enables DSP interrupts.
Loss of Sync Interrupt Enable: enables DSP interrupts
EDC Interrupt Enable. CRC miscompares trigger DSP interrupts
DMA Intterrupt Enable. DMA-block transfers complete trigger DSP interrupt
Detect Enable. Enable the SYNC-detector sub-function of the CDSYNC module.
If enabled, the CDSYNC will perform calculations and DMA based on the
CDROM sectors. If disabled, CDSYNC will DMA directly to memory unaltered.
Table 120. Control/Status Register Description
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BITS
LABEL
RW RESET
2
DSCRAM
RW 0
1
0
CRC
EN
RW 0
RW 0
DEFINITION
Descrambler Enable. Enable the de-scramber seub-funtion of the CDSYNC.
This function de-scrambles a CDROM sector(bytes 12-2353)
CRC Enbable. Checking versus the EDC data on the CDROM
CDSYNC Enable. No DMA actions will occur with this bit disabled(0).
Table 120. Control/Status Register Description (Continued)
14.1.2.
CDSYNC Data Register
The input shift register for the CDSYNC module. Writing this register causes the
CDSYNC to process 16 or 24-bits of data(depending on configuration). This register
is normally configured to be written by the I2S-interface so no DSP intervention is
required
HW_CDSYNCDR
X:$F601
BITS LABEL RW RESET
23:0
DATA
DEFINITION
RW 0
Reserved
Table 121. CDSYNC Data Register Description
14.1.3.
CDSYNC Word Count Register
Holds the number of DMA words to be written to memory. Writing this register with a
non-zero vale will start the DMA-engine.
HW_CDSYNCWCR
X:$F602
BITS LABEL RW RESET
DEFINITION
23:13 RSRVD
12:0 COUNT
Table 122. CDSYNC Word Count Register Description
14.1.4.
CDSYNC Current Position Register
This register holds the current address offset within the DMA buffer, This register
can be written with non-zero values to change the starting offset.
HW_CDSYNCCPR
X:$F603
BITS LABEL RW RESET
DEFINITION
23:12 RSRVD
11:0 POS
Table 123. CDSYNC Current Position Register Description
14.1.5.
CDSYNC Modulo Register
This register holds the modulo offset. This field can be used to set an address offset
limit for addressing circular buffers. When the Current Postions reaches the modulo
offset, the current position is reset to zero.
HW_CDSYNCMODR X:$F604
BITS LABEL RW RESET
DEFINITION
23:13 RSRVD
12:0 MOD
Table 124. CDSYNC Modulo Register Description
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14.1.6.
CDSYNC Base Address Register
This register is used for setting the base-address of the DMA output buffer. This can
be set to point to anywhere in the 16-bit memory space.
HW_CDSYNCBAR
X:$F605
BITS LABEL RW RESET
DEFINITION
23:16 RSRVD
15:0 BASE
Table 125. CDSYNC Base Address Register Description
14.2. Reed Solomon Error Corrector Registers
The Reed-Solomon DSP-accessible module which processes the P and Q parity
codewords of a CDROM-sector. Its prupose is to off-load the process of error-detection and correction from the DSP. Once configured and enabled, the block is capable of processing all P and/or Q codewords within a CDROM sector.
The RS is configurable through 8-control registers which must be configured before
a CDROM sector may be processed.
14.2.1.
Reed Solomon Control Status Registers
This register provides control over much of the functionality of the RS -block.
HW_RSCSR
BITS
LABEL
23
RESET
22:20 RSRVD
19:16 DMAWAIT
15
14
13
12
11
10
9
8
7
6
5
RW RESET
X:$F700
DEFINITION
Software reset and low power mode enable
Reserved
Dma Wait States: number of cycles the RS-module should wait between
consecutive DMA cycle requests.
ODDERROR
R
0
Odd Error Status bit: indicates that and uncorrectable error was detected in the
odd-byte codeword. This bit is only set when CorInt (bit 9) is set.
ODDCORCT
R
0
Odd Correctable Status bit: indicates that a correctable error was detected in
the odd-byte codeword. This bit is only set when CorInt (bit 9) is set.
EVENERROR R
0
Even Error Status bit: indicates that and uncorrectable error was detected in
the even-byte codeword. This bit is only set when CorInt (bit 9) is set.
EVENCORCT R
0
Even Correctable Status bit: indicates that a correctable error was detected in
the even-byte codeword. This bit is only set when CorInt (bit 9) is set.
RSRVD
RW 0
Reserved
ERROR
RW 0
Uncorrectable Error Interrupt Status bit: indicates that an uncorrectable error
was detected in the most recent codeword. If the interrupt is enabled,
processing stops untill this bit is cleared.Must write a ‘1’ to clear this flag.
CORRECT
RW 0
Correctable Error Interrupt Status bit: indicates that an correctable error was
detected in the most recent codeword. If the interrupt is enabled, processing
stops untill this bit is cleared.Must write a ‘1’ to clear this flag.
DONE
RW 0
Done Interrupt Status bit: indicates that all codewords have been processed.
An interrupt is generated if enabled. Must write a ‘1’ to clear this flag.
RSRVD
RW 0
Reserved
ERRIRQEN
RW 0
Uncorrectable Error Interrupt Enable: uncorrectable errors trigger DSP
interrupts.
CORCTIRQEN RW 0
Correctable Error Interrupt Enable: correctable errors trigger DSP interrupts.
Table 126. Reed Solomon Control Status Registers Description
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RW 0
RW 0000
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BITS
LABEL
RW RESET
4
DONEIRQEN
RW 0
3
2
1
0
ODDEN
EVENEN
AUTOCORCT
KICK
RW
RW
RW
RW
Table 126.
14.2.2.
DEFINITION
Done Interrupt Enable: completion of processing of a CDROM sector triggers
DSP interrupts.
0
Enable calculation of odd byte codewords
0
Enable calculation of even byte codewords
0
Enables automatic correction of correctable Reed-solomon errors
0
Starts processing codewords of a CDROM sector. This bit automatically resets
when procesing is complete.
Reed Solomon Control Status Registers Description (Continued)
Reed Solomon Error Offset Register
This register provides an indication of the failing address in the event of a correctable-error.
HW_RSOFFSETR
X:$F701
BITS LABEL RW RESET
23:12 ODD
RW $000
11:0
RW $000
EVEN
DEFINITION
Odd Error Address: the 12-LSB’s of the odd error location. This field is valid only when
the CorInt-control bit is set.
Odd Error Address: the 12-LSB’s of the odd error location. This field is valid only when
the CorInt-control bit is set.
Table 127. Reed Solomon Error Offset Register Description
14.2.3.
Reed Solomon Word Count Register
This register is used to specify the number of codewords to be processed and the
number of bytes-per-codeword. These fields are continuously updated as the module processes data.
HW_RSWRDCNTR
BITS
LABEL
RW RESET
23:12 BLOCKCNT RW $000
11:0
WORDCNT
X:$F702
RW $000
DEFINITION
The number of Reed-Solomon codewords to be processed. The count is
decremented for each new block processed.
The number of words(bytes) per Reed-Colomon codeword. This count is
decremented for each byte during codeword processing
Table 128. Reed Solomon Word Count Register Description
14.2.4.
Reed Solomon Current Position Register
This register holds the current address offset within the DMA buffer, This register
can be written with non-zero values to change the starting offset.
HW_RSCPR
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 POS
RW
X:$F703
DEFINITION
Reserved
Table 129. Reed Solomon Current Position Register Description
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14.2.5.
Reed Solomon Modulo Register
This register holds the modulo offset. Can be used to set an offset limit for the nonparity portion of the codewords. If the current position exceeds BAS+MOD then it is
re-calculated as CPR = CPR - MOD.
HW_RSMODR
X:$F704
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 MOD
RW
DEFINITION
Reserved
Table 130. Reed Solomon Modulo Register Description
14.2.6.
Reed Solomon Base Address Register
This register is used for setting the base-address of the of the non-parity portion of
the codewords.
HW_RSBAR
X:$F705
BITS LABEL RW RESET
23:16 RSRVD R
15:0 ADDR
0
RW
DEFINITION
Reserved
Table 131. Reed Solomon Base Address Register Description
14.2.7.
Reed Solomon Parity Base Address Register
This register contains the base-address of the parity portion of the codewords.
HW_RSPBAR
X:$F706
BITS LABEL RW RESET
23:16 RSRVD R
0
15:0 ADDR RW
DEFINITION
Reserved
Table 132. Reed Solomon Parity Base Address Register Description
14.2.8.
Reed Solomon Span Register
This register is used to configure the type off addressing used to de-scramble the
CDROM sector so that Reed-Solomon calculations may be performed on it.
HW_RSSPANR
BITS
LABEL
RW
RESET
X:$F707
DEFINITION
23:16 BLOCKSPAN RW 00000000 Block Address Increment: the value that is added to the BAS to get the
starting address for each consecutive codeword
15:8 PARITYSPAN RW 00000000 Parity Address Increment: the value added to the each parity location to find
the next location within a codeword.
7:0
WORDSPAN RW 00000000 Word Address Increment: the value that is added to each byte location to find
the next byte within a codeword. If the calculated result exceeds BAS +
MOD, then MOD is subtracted
Table 133. Reed Solomon Span Register Description
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15. CD-DSP INTERFACE
15.1. Features
•
Provides serial interface for controlling various CD-DSP chips
•
Provides serial interfaces for reading raw Q-W subcode data and formatted Q data
•
Provides serial interface for reading CD-DSP status
•
Fully programmable clock and sync generation supports many DSPs
•
Programmable bit width supports 1 to 24 bits per transfer
•
Serial input and output interfaces can operate synchronously or asynchronously
•
Simple interrupt driven software interface saves DSP MIPs
•
Flexible pin allocation helps minimize conflicts with other modules
•
Low power, gated-clock mode provided
15.2. Hardware functionality
15.2.1.
Functional Description
15.2.1.1.
Overview
The CDI module provides an interface to various CD mechanism control DSPs. The
module provides a serial output for sending commands and two serial inputs that
can be used for reading command responses, such as raw Q-W subcode data,
and/or formatted Q subcode data. These three serial interfaces are fully independent but can be made to operate synchronously. They are also fully programmable
to allow a glueless interface to many CD-DSPs.
The CD-DSPs currently in production have between one and four serial interfaces
used for control and subcode data transmission. Each of these interfaces is composed of a serial data line, a bit clock, and a frame synchronization signal. The
clocks and frame synchronization are shared between multiple interfaces on some
devices and independent on others. The CDI module supports having up to three
simultaneous serial transactions. The fourth serial interface can be supported with
the CDI by time multiplexing one of the serial interfaces. It is assumed that STMP
would not need to write a command, read a command response, read Q-W subcode
data, and read Q subcode data all at the same time.
Figure 14 shows the block diagram of the CDI module. The two serial input units are
identical and receive the same frame sync signals: si_frame, si_synca, and
si_syncb. Each input unit can be programmed to use one of the three input syncs or
the sync generated by the control interface, ctl_lat. This use of the ctl_lat signal
allows either of the serial input units to receive command responses from the external DSP. There is one dedicated serial input data signal for each input unit and
another that is shared by both, ctl_sense. The shared data signal allows either input
unit to receive data from two external serial interfaces without glue logic. All three
serial interfaces master their respective bit clocks. The control clocks, ctl_clk and
ctl_sclk, can be mastered by any interface unit. This is useful because some DSPs
use separate clocks for input and output commands while others share the clocks
between serial interfaces.
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Figure 13 shows examples of the types of serial transfers that the CDI is designed
to accommodate.
Control transfer – 8 bits, RZ clock
TA
ctl_clk
ctl_so
ctl_lat
TB
TC
TD
Serial input transfer – 7 bits, NRZ clock
TE
si_clk
si_di
sync
TF
TG
Figure 13. CDI Serial Transfer Type Examples
A typical control transaction consists 24 or fewer bits being shifted out, followed by
the assertion of the latch signal, ctl_lat. The interface can also be programmed to
not issue a latch when the transfer is complete. This allows multiple control transfers
to be combined, forming a single DSP command that can be greater than 24 bits
long. The CDI module must be setup for each partial transfer. A typical serial input
transfer occurs after the detection of an edge on the selected sync signal (si_frame,
si_synca, or si_syncb). The ctl_lat signal can also be selected as the sync signal so
that a serial input can read the response to a DSP command. Similar to the control
interface, the serial input interfaces can ignore the sync signal allowing greater than
24 bit input transfers. The serial inputs also have the ability to disable sync detection
if the serial data-in signal is not at the correct level. This is useful for ignoring data
that the external CD-DSP indicates had failed a CRC check.
To support the largest number of CD-DSPs the serial interfaces have several programmable features. The polarity of all sync, latch, and clock signals are programmable. Also, the capture and shift edges of the clocks are programmable
independent of the clock polarity. The data being sent or received can be transferred
MSB or LSB first and can be packed into the data registers MSB or LSB justified.
The number of bits transferred can range from 1 to 24 and the clock speed can
range from dsp_clk/1 to dsp_clk/1024. All of the other timing parameters shown in
Figure 13 are programmable as well, in increments of bit clocks.
To support the various CD-DSPs using as few external I/Os as possible, the CDI
module provides multiple pin mappings. The logic for remapping the pins is external
to the CDI module but the module provides the control. The pin mapping for CDI
I/Os is described in section 1.3.
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15.2.1.2.
Memory Map
The program interface for each of the three serial interface units is very similar. The
control/status register (CSR) is used to configure the interface, enable interrupts,
and start the transfer. The Time Base register is used to set the speed of the interface and the Timer register is used to configure other timing parameters.
Finally, the Data register holds the transmit or receive data. The CDI module also
contains a Pin Configuration register. This register can be used to change the pin
mapping of the CDI signals.
15.2.1.3.
Implementation Details
The CDI module consists of three serial interfaces and a small amount of external
glue logic. The two serial inputs are exactly the same while the one serial output
shares a similar design. Figure 14 shows the architecture of each interface.
dsp_xdb
Serial In
24 Bit Shift Register
Serial Out
Shift
(control only)
DSP Clock
Counters and
State Machine
Clock Divide
By 2 to 1022
ctl_lat
Bit clock
(si0 & si1 only)
si_synca
si_syncb
si_frame
M
U
X
Figure 14. CDI Serial Interface Architecture
Both the control interface and serial inputs use a clock divider to generate the external bit clock. This divider produces a 50% duty cycle clock by counting half of the
divide value for each clock phase. Since the LSB of the divide value is ignored, the
divide amount is always even. The actual bit clock rate will depend on the DSP
clock speed but the divide range provided should allow the necessary bit clocks to
be generated for DSP clocks of 100 MHz or less. The bit clock forms the basis of
timing for each interface. All other timing parameters are defined by a quantity of bit
clocks.
The external bit clock can be defined to be return to zero or return to one as shown
in Figure 15. The control CSR also contains a clock polarity bit that determines the
shift and capture edges of the bit clock as shown in Table 134:
CRZ=0, POL=0
CRZ=0, POL=1 CRZ=1, POL=0 CRZ=1, POL=1
Rising
Falling
Falling
Rising
CAPTURE EDGE Falling
Rising
Rising
Falling
SHIFT EDGE
Table 134. CDI Control CSR Clock Polarity
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The state machine used to implement the control transaction shown in Figure 15 is
shown below.
Reset
Latch delay
time elapsed
IDLE
LATCH
DELAY
Kick
XFER WAIT
1 Bit
Clock
Latch signal
disabled
Latch active
time elapsed
XFER DATA
LATCH
ACTIVE
Latch wait
time elapsed
LATCH
WAIT
All bits
transferred
Figure 15. Control Interface State Machine
As Figure 15 shows, once the control interface is started it sequences through all
states needed to complete the transaction. The transaction can only be stopped by
issuing a soft reset. Writing a one to the Kick bit of the CSR starts a transaction. The
state machine sequences to XFER WAIT and then waits on the first shift edge of the
bit clock to occur. This delay insures that the serial output data only transitions on
the shift edge of the bit clock. Once the first clock is detected the state machine transitions to XFER DATA. In this state it transfers one bit onto the serial output for each
bit clock shift edge. When the number of bits programmed into the CSR is
exhausted, the state machine transitions to LATCH WAIT if latch generation is
enabled. In this state the output sits idle for the number of bit clocks defined in the
TIMER register. This delay corresponds to time TB in Figure 13. Similarly, the delay
in LATCH ACTIVE and LATCH DELAY corresponds to times TC and TD respectively. The ctl_lat signal is asserted only during the LATCH ACTIVE state. The polarity of the signal is determined by the latch polarity bit in the control CSR.
The data shifted out onto the serial interface can be sent LSB or MSB first. Also, for
transfers of less than 24 bits, the data can be justified into the MSBs or LSBs of the
shift register. To support these capabilities, the shift register can shift in either direction and the ctl_so signal can be derived from any bit of the register. These complexities are designed to make the programming interface simpler and reduce MIPs.
Figure 16 shows the state machine for serial input interfaces:
The serial input state machine does not become active until the CSR Kick bit is set
and optionally a sync edge is detected and a CRC check passes. The sync edge
detection can be setup to watch for either polarity on si_frame, si_synca, si_syncb,
or ctl_lat. The interface can also be programmed to ignore the sync so that multiple
transactions can be put together to form a transfer of more than 24 bits. In that case,
writing the Kick bit to one starts the transaction. The optional CRC check is performed by sampling the state of the serial input when the active sync edge occurs
and verifying that it matches the value specified in the CSR. Once the state machine
is kicked it enters the XFER WAIT state and waits the number of bit clocks defined
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Reset
Finsh Delay
time elapsed
Kick and CRC OK
and Sync Edge
Detected
IDLE
XFER WAIT
DELAY
All bits
transferred
XFER DATA
Start Delay
time elapsed
Figure 16. Serial Input State Machine
in the Timer register before starting the serial transfer. This delay corresponds to TF
in Figure 13. After the start delay the state machine enters XFER DATA where up to
24 bits of data are shifted in. Finally, delay TG from Figure 13 is accomplished using
the DELAY state. This delay is provided so that Mirage can issue a new transaction
as soon as the previous one completes without the violating CD-DSP timing constraints. Note that both TF and TG are forced to zero when sync detection is disabled. This allows transfers of greater than 24 bits to be completed as a continuous
stream without modifying the Timer register.
The bit clock, data direction, and data justification options for the serial inputs are
the same as those for the control interface. Table 134 applies to the inputs as well.
However, since the serial inputs are the receivers of serial data, their shift registers
capture data and shift on the capture edges of the bit clock. The serial inputs are
each capable of driving an additional bit clock pin to make time multiplexing the
interface easier. Only one bit clock is active at a given time. The other bit clock is
held at zero or one depending on the state of the RZ bit defined in the CSR for that
clock. For additional time multiplexing support, the serial data for each input unit can
be selected from two different pins.
15.2.1.4.
Interrupts
The CDI module drives a single interrupt signal, cdi_int, based on three possible
interrupt conditions. If enabled, an interrupt is generated when any of the three
serial interfaces completes a transaction. Each interface has an interrupt enable bit
in its CSR.
INTERRUPT CONDITION
SIGNAL
Control Done
cdi_int
SI0 Done
cdi_int
SI1 Done
cdi_int
DESCRIPTION
Indicates that the control output serial interface
has completed a transaction.
Indicates that the serial input 0 interface has
completed a transaction.
Indicates that the serial input 1 interface has
completed a transaction.
Table 135. Interrupt Conditions
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15.2.1.5.
Chip level I/O mapping
The goal behind the pin muxing used by the CDI module is to support as many CDDSPs as possible while stealing as few pins as possible from other STMP interfaces. The best place to borrow pins seems to be from the EMC/SDRAM interfaces.
The 16 bit wide data bus for this interface can in most cases be operated in 8 bit
mode freeing up 8 pins for use by the CDI. If the CDI needs more pins it can also
use the upper four address bits of the EMC/SDRAM interface. The EMC and
SDRAM can continue to operate but with a reduced address space. When enabled
the CDI takes over all 8 data lines but only takes control of the address lines that it is
configured to use.
The interface requirements for CD-DSPs vary widely. Most have some type of serial
control port and at least one subcode interface. The table below gives some examples of how the CDI can accommodate various devices. More configurations are
possible using the controls in the Pin Configuration register.
CONTROL OUTPUT,
ONE SUBCODE
INTERFACE
Data[15]
Data[14]
Data[13]
Data[12]
Data[11]
Data[10]
Data[9]
Data[8]
Addr[23]
Addr[22]
Addr[21]
Addr[20]
Si0_clk
Si0_di
Si_frame
Si_synca
Ctl_lat
Ctl_clk
Ctl_so
Si_syncb
EMC
EMC
EMC
EMC
TWO SUBCODE
INTERFACES
Si0_clk
Si0_di
Si_frame
Si_synca
Si1_clk
Si1_di
Ctl_sense
Si_syncb
EMC
EMC
EMC
EMC
CONTROL OUTPUT,
CONTROL INPUT
ONE SUBCODE
INTERFACE
Si0_clk
Si0_di
Si_frame
Ctl_sense
Ctl_lat
Ctl_clk
Ctl_so
Si_syncb
Ctl_sclk
EMC
EMC
EMC
CONTROL OUTPUT,
CONTROL INPUT,
TWO SUBCODE
INTERFACES
Si0_clk
Si0_di
Si_frame
Si_synca
Si1_clk
Si1_di
Ctl_sense
Ctl_sclk or si_syncb
Ctl_lat
Ctl_clk
Ctl_so
Ctl_sclk or EMC
Table 136. CDI Pin Mapping Examples
15.3. Software Functionality
15.3.1.
Programming Rules, Guidelines, and Examples
15.3.1.1.
General Programming Notes
The software interface to the CDI module is comprised of the control registers for
three separate serial interfaces and a pin control register. The behavior of the block
in various conditions is described throughout the rest of this document. This section
summaries some of the more obscure points.
5-3410-D1-2.0-0402
•
Long Transfers – A normal transfer on any of the serial interfaces consists of a
serial transfer of 24 or fewer bits. Support is provided for doing long transfers
using multiple transactions. Since the speed of Mirage is much faster than the
interface speeds, multiple transactions can be initiated by Mirage without
violating the CD-DSP timing specifications. For example, a 32 bit control
transfer can be accomplished using a 24 bit and an 8 bit control transfer. In this
case, only the second transfer would enable generation of the latch signal.
•
Serial interface multiplexing – Each serial input interface is designed to be
easily switchable between two serial inputs. A separate clock is provided for
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each input and a separate sync and serial input can be observed by the module.
This capability allows one hardware serial input block to read Q subcode data
and control command response packets, for example.
•
15.3.2.
Multiple Transfers – The state machine of each serial interface is designed to
allow a new serial transaction to be initiated as soon as the previous one
completes. The driver code must ensure that the timer registers are properly
configured to avoid timing problems with the external CD-DSP.
CD-DSP Interface (CDI) Registers
All register reserved fields should be written with zeros.
15.3.2.1.
CD-DSP Interface Control Unit Control Status Register
HW_CDI_CTLCSR
BITS
LABEL
RW
X:$F280
RESET
23
RESET
RW 1
22
21
RSRVD
TFRDONE
RW 0
RW 0
20
19:12
11
10
IRQEN
RSRVD
LATCHPOL
LATCHEN
RW 0
RW
RW 0
RW 0
9
MSBJUSTIFY RW 0
8:4
3
LENGTH
LSBFIRST
RW 00000
RW 0
2
CLKRZ
RW 0
1
CLKPOL
RW 0
0
KICK
RW 0
DEFINITION
Software reset and low power mode enable.
NOTE: When set the clocks are disabled to all three serial interfaces.
Reserved
Transfer Done Interrupt status bit. Indicates that the serial transfer is
complete. Write ‘1’ to clear.
Interrupt Enable. Enables routing of Done interrupt to the cdi_int signal.
Reserved
Latch Polarity. Defines the active state of the ctl_lat signal.
Latch Enable. When set enables the generation of a latch pulse on ctl_lat
after the serial transfer completes.
MSB Justify. When set the valid data is in the MSBs of the 24 bit data register,
otherwise the data is in the LSBs.
Transfer Length. Number of bits to transfer, between 0 and 24.
LSB First. When set the data is shifted out of the data register LSB first,
otherwise it is MSB first.
NOTE: If LSB First and MSB Justify are both active, the LSB of the data is
sent first, not the LSB of the register. The location of this bit in the data
register will depend on the Transfer Length.
Control Clock Return to Zero. When set the inactive state of the clock is ‘0’,
otherwise it is ‘1’.
Control Clock Polarity. In combination with bit 2 Clock RZ, defines the shift and
capture edges of the bit clock. Refer to Table 134.
Kick Pit Positive. When set the serial transaction is started.
Table 137. CD-DSP Interface Control Unit Control Status Register Description
15.3.2.2.
CDI Control Port Timer Register
HW_CDICTRLTMR
X:$F281
BITS
LABEL
23:16 FINALDELAY
15:8
7:0
RW RESET
DEFINITION
RW 0
The number of bit clocks to wait before generating a done interrupt after
deasserting the latch signal. Corresponds to TD in Figure 11.
LATCHWIDTH RW 0
The number of bit clocks to hold the latch signal in its active state.
Corresponds to TC in Figure 11.
LATCHSTART RW 0
The number of bit clocks to wait after completing the serial transfer before
asserting the latch signal. Corresponds to TB in Figure 11.
Table 138. CDI Control Port Timer Register Description
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15.3.2.3.
CDI Time Base Register
HW_CDICTRLTBR
BITS LABEL RW
X:$F282
RESET
23:10 RSRVD RW
9:0
DIVIDE RW 0
DEFINITION
Reserved
Clock Divide Value – The number of times to divide the DSP clock to generate the
bit clock. Must be an even number.
Table 139. CDI Time Base Register Description
15.3.2.4.
CDI Data Register
HW_CDIDATAR
X:$F283
BITS LABEL RW RESET
DEFINITION
23:0 DATA RW $000000 Output Data. Data to be transferred over the serial interface. This register is the shift
register used by the serial interface.
Table 140. Control Unit Data Register Description
15.3.2.5.
CDI Pin Configuration Register
HW_CDIPINCFGR
BITS
LABEL
23:12 RSRVD
11
SCLKOUTEN
10
CTLOUTEN
9:8
CCLK
7
SCLK
6
SENSE
5
SYNCA
4
CTLSO
3:2
SCLK
1
CTL
0
ENABLE
X:$F284
RW RESET
DEFINITION
RW
Reserved bits
RW 0
SCLK Output Enable. Set to enable output driver
RW 0
Control Output Enable. Ctl_clk, ctl_so, and ctl_lat output enable – Set to enable
output drivers
RW 00
Ctl_clk source. 0x – Control unit clock
10 – SI0/SCLK
11 – SI1/SCLK
RW 0
Ctl_sclk source
0–
SI0/SCLK
1–
SI1/SCLK
RW 1/b0
Sense Pin select for ctl_sense
0–
Data[9]
1–
Data[12]
RW 1/b0
SYNCA Pin select for si_synca
0–
Data[12]
1–
Data[9]
RW 0
Control SO Pin select for ctl_so
0–
Data[9]
1–
Addr[21]
RW 00
SCLK Pin select for ctl_sclk
00 – Data[8]
10 – Addr[20]
01 – Reserved
11 – Addr[23]
RW 0
Control Pin select for {ctl_lat, ctl_clk}
0–
Data[11:10]
1–
Addr[23:22]
RW 0
Pin Enable - Enables the CDI module to take control of the EMC/SDRAM pins
Data[15:8] and Addr[23:20]. Depending on the state of other pin configuration
bits, the CDI may not take control of all 12 pins. Refer to Table 136.
Table 141. CDI Pin Configuration Register Description
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15.3.2.6.
CD-DSP Interface Serial Input Control Status Register
HW_CDICSI0CSR
HW_CDICSI1CSR
BITS
23
22
21
LABEL
RESET
RSRVD
DONE
RW
X:$F288
X:$F28C
RESET
DEFINITION
RW 1
RW 0
RW 0
Software reset
Reserved
Transfer Done Interrupt status bit – Indicates that the serial transfer is
complete. Write ‘1’ to clear.
20
IRQEN
RW 0
Interrupt Enable – Enables routing of Done interrupt to the cdi_int signal.
19
RSRVD
RW Unknown Reserved bit
18:17 SYNCSEL
RW 000
Sync signal selector
00 – si_synca
10 – si_frame
01 – si_syncb
11 – ctl_lat
16
DATASEL
RW 0
Data input selector
0–
si01_di
1–
ctl_sense
15
CLKSEL
RW 0
Active clock selector
0–
si01_clk
1–
si01_sclk
14
CRCPOL
RW 0
Polarity of serial input when CRC is good
13
CRCEN
RW 0
When set CRC checking is enabled. The serial input state is compared
against CRC Polarity when the sync edge occurs.
12
SYNCPOL
RW 0
Determines that active edge of the sync signal:
0–
Falling edge
1–
Rising edge
11
SYNCEN
RW 0
When set the serial transfer will not begin until the active sync edge appears.
10
SCLKRZ
RW 0
Return to zero for the sclk output – When set the inactive state of the clock is
‘0’, otherwise it is ‘1’
9
MSBJUSTIFY RW 0
When set the valid data is shifted into the MSBs of the 24 bit data register.
Otherwise the data goes into the LSBs.
8:4
LENGTH
RW 00000
Number of bits to transfer, between 0 and 24.
3
LSBFIRST
RW 0
When set the incoming data is assumed to be LSB first, otherwise it is MSB
first.
2
CLKRZ
RW 0
Return to zero for the bit clock – When set the inactive state of the clock is ‘0’,
otherwise it is ‘1’.
1
CLKPOL
RW 0
Clock polarity for the bit clock – In combination with Clock RZ, defines the shift
and capture edges of the bit clock. Refer to Table 136.
0
KICK
RW 0
When set the serial transaction is started. The transfer may not actually begin
until the sync edge detect and CRC ok conditions are met.
Table 142. CD-DSP Interface Serial Input Control Status Register Description
15.3.2.7.
Serial Input Time Base Registers
HW_CDI_SI0TBASE X:$F28A
HW_CDI_SI1TBASE X:$F28E
BITS LABEL RW
RESET
23:10 RSRVD RW
9:0
DIVIDE RW 0
DEFINITION
Reserved
Clock Divide Value – The number of times to divide the DSP clock to generate the
bit clock. Must be an even number.
Table 143. Serial Input Time Base Register Description
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15.3.2.8.
Serial Input Timer Registers
HW_CDISI0TMRR
HW_CDISI1TMRR
BITS
LABEL
23:16 FINALDELAY
15:8
7:0
RW
X:$F289
X:$F28D
RESET
RW 0
DEFINITION
Final Delay. The number of bit clocks to wait before generating a done
interrupt after completing the serial transfer.
Forced to zero when sync detection is disabled. Corresponds to TG in Figure 13.
Reserved bits
Latch Start. The number of bit clocks to wait after detecting an active sync
edge before starting the serial transfer.
Forced to zero when sync detection is disabled Corresponds to TF in Figure 13.
RSRVD
RW
LATCHSTART RW 0
Table 144. Serial Input Timer Register Description
15.3.2.9.
Serial Input Data Registers
HW_CDISI0DATAR
HW_CDISI1DATAR
BITS
23:0
LABEL
DATA
X:$F28B
X:$F28F
RW RESET
DEFINITION
RW $000000 Data received from the serial interface. This register is
the shift register used by the serial interface.
Table 145. Serial Input Data Register Description
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16. I2S SERIAL AUDIO INTERFACE
The STMP3410 implements a standard 3-channel I2S Serial Audio Interface (SAI).
This allows the STMP3410 to receive data from an external host or A/D or transmit
data to an external D/A. The STMP3410 must be configured as slave device on the
I2S bus. Data can be transferred between the DSP core and the SAI by polling status flags or by servicing interrupts.
16.1. I2S External Pins
Name
I2S_BCLK
I2S_WCLK
2S_DataI0
I2S_DataI1
I2S_DataI2
I2S_DataO0
I2S_DataO1
I2S_DataO2
Description
Input, I2S serial bit clock
Input, I2S left/right word clock
Input, I2S input data 0
Output, I2S output data 0
I2S_SELECT=0
91/127/G3
92/129/H3
95/135/J1
94/133/H2
93/131/H4
90/125/G4
89/123/F3
88/122/F4
Pin #
I2S_SELECT=1
NA/140/K3
NA/142/K1
NA/136/J2
94/133/H2
93/131/H4
90/125/G4
89/123/F3
88/122/F4
Note: The I2S_Select bit of the HW_SPARER Register shown on page 26, controls
the pinout of these pins.
X Peripheral Data Bus (xdb_per)
RCS
TCS
TO xdb_per
FROM xdb_per
23
0
Status
RX2 Data RegisterL
RX2 Data RegisterR
0
Control 23
RX2 Shift Register
Status
Receiver
Controler
SDI2
TO xdb_per
23
0
RX1 Data RegisterL
RX1 Data RegisterR
0
Control 23
RX1 Shift Register
Status
Status
TO xdb_per
23
0
RX0 Data RegisterL
RX0 Data RegisterR
0
Control 23
RX0 Shift Register
SCKR
LRCKR
0
Control 23
TX2 Shift Register
Status
SDI1
SDO2
TO xdb_per
23
0
TX1 Data RegisterR
TX1 Data RegisterL
Transmitter
23
0
Controler Control TX1 Shift Register
Status
SDI0
TX2 Data RegisterR
TX2 Data RegisterL
SDO1
TO xdb_per
23
0
TX0 Data RegisterR
TX0 Data RegisterL
0
Control 23
TX0 Shift Register
SDO0
SCKT
LRCKT
Figure 17. I2S Block Diagram
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16.2. I2S Receive and Transmit Registers
16.2.1.
Receivers
The SAI contains three 2-channel receivers. These receivers shift serial data from
the I2S_DataIx pins using the bit and word clocks. It fills the data register
(SAIRX0,1,2R) until the word clock or RCS word length indicate that the word has
ended. The next word is placed in the other receiver channel.
After both words have been clocked into the data registers the Read Data Ready
(RDR) Flag is set. The DSP should read the data registers and clear the RDR flag
before the next word is ready to move from the shift register to the data register. The
DSP can either poll the RDR flag or receive an interrupt if the RXIE Bit is set.
Both channels of the read data registers are muxed into the same DSP address.
The first read will retrieve the data from the left channel data register. The second
will retrieve the right channel data. Subsequent reads will alternately retrieve the left
and right channel data.
16.2.1.1.
Receive Status I2S Control Register
HW_SAIRCSR
X:$FFF0
BITS LABEL RW RESET
DEFINITION
23:17 RSRVD R
0
Reserved
16
ROFCL RW 0
Receiver Data Overflow Clear – When this bit is set by the DSP both the ROFL and
RDR flags are cleared. This bit is implemented as a one-shot and always reads a zero.
Note: if ROFL is cleared in the last instruction of an Interrupt Service
Routine triggered by this bit, then the Interrupt will be executed twice.
15
RDR
R
0
Receiver Data Ready Flag – Indicates that both left and right data words have been
received. This bit is cleared when both left and right data are read from the receiver
data registers of all enabled receivers, or by writing a one to the ROFCL bit.
14
ROFL R
0
Receiver Data Overflow – Indicates that an overflow condition was detected. This
condition occurs when the RDR Flag is set and a new data word is transferred from the
shift register to the receiver data register. Writing a one to the ROFCL bit clears this bit.
13
RSRVD
Reserved
12
RXIE
RW 0
Receiver Interrupt Enable for DSP – Interrupt enable for DSP.
11
RDWJ RW 1
Receiver Data Word Justification – Determines which portion of the 24-bit portion of
the received 32-bit word will be transferred from the shift register to the data register
when programmed to receive 32 bit words.
0
The first 24 bits received are transferred to the data register.
1
The last 24 bits received are transferred to the data register.
When the receiver is programmed to receive 24 or 16 bit words this bit functions as follows:
0
Means that either the SCKR bit-counter ( when it reaches 16 or 24 ) or a
LRCKR transition , whichever comes first, can transfer data to the data
registers.
1
Means that a LRCKR transition only will terminate the transfer and the last
16 or 24 bits received before the LRCKR transition gets transferred to the
data registers.
10
RREL RW 0
Receiver Relative Timing – Determines the relative timing of the LRCKR signal as
referred to the serial data inputs.
0
The transition of LRCKR occurs together with the first bit data.
1
The transition of LRCKR occurs one SCKR earlier(I2S format).
Table 146. Receive Status I2S Control Register Description
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BITS LABEL RW RESET
DEFINITION
9
RCKP RW 1
Receiver Clock Polarity – Defines the polarity of the receiver clock.
1
Positive Clock Polarity. Means the LRCKR and SDI lines change
synchronously with the positive edge of the clock, and are considered valid
during negative transitions.
0
Negative Clock Polarity. Means the LRCKR and SDI lines change
synchronously with the negative edge of the clock, and are considered valid
during positive transitions
8
RLRS RW 1
Receiver Left Right Selection – Defines the polarity of the LRCKR.
0
If LRCKR = 0 then Left Word, if LRCKR = 1 then Right Word.
1
If LRCKR = 0 then Right Word, if LRCKR = 1 then Left Word.
7
RDIR
RW 0
Receiver Data Shift Direction – Determines the shift direction of the received data.
0
MSB First
1
LSB First.
6:5
RWL
RW 0
Receiver World Length Control – Selects the length of the data word being received
by the SAI.
00 16 Bits
01 24 Bits
10 32 Bits
11 Reserved.
4
RSRVD
Reserved
3
RMME RW 1
Receiver master mode enable
1
Receiver in master mode.
0
Receiver in slave mode.
Enable Master Mode for the receiver. i.e. Enables use of the Transmitter clocks from
the PLL to shift in data. A `1' in this bit configures the receiver into Master Mode.
2
REN2
RW 0
Receiver Enable – Enable bit for Receiver channel 2.
1
REN1
RW 0
Receiver Enable– Enable bit for Receiver channel 1.
0
REN0
RW 0
Receiver Enable – Enable bit for Receiver channel 0.
Table 146. Receive Status I2S Control Register Description (Continued)
16.2.1.2.
Receive Status I2S DataI0 Register
HW_SAIRX0R
BITS
23:0
LABEL
X:$FFF1
RW RESET
RECEIVE0 RW 0
DEFINITION
Data received from I2S_DATAI0
Table 147. Receive Status I2S DataI0 Register Description
16.2.1.3.
HW_SAIRX1R
BITS
23:0
LABEL
X:$FFF2
RW RESET
RECEIVE1 RW 0
DEFINITION
16.2.1.4.
HW_SAIRX2R
BITS
23:0
LABEL
X:$FFF3
RW RESET
RECEIVE2 RW 0
DEFINITION
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16.2.1.5.
Handling Different Word Lengths
It is possible that an external SAI and the STMP3410’s SAI could be programmed to
different size word lengths. The normal case is handled by terminating (performing a
parallel load of the data register) the transfer when a LRCKR transition occurs. However, when the STMP3410’s SAI is programmed to receive 16 bit words and the
external SAI is programmed to transmit 24 bit words (for example) the parallel load
should occur as soon as the 16 bits are serially shifted in. This implies that a bit
counter must be used to terminate the transfer.
Another case would be when the external SAI is programmed to transmit fewer bits
than the STMP3410’s SAI is programmed to receive. For example, if the external
SAI is programmed to transmit 16 bits and the STMP3410’s SAI is programmed to
receive 24 bits the transfer should be terminated by the LRCKR.
16.2.2.
Transmitters
Each I2S channel has a transmitter. The transmitter serially outputs data from the
left/right data registers (SAITX0,1,2R). Each I2S channel can carry two data streams
(i.e. audio channels). The data can be arranged in 16, 24 or 32 bit words. The
STMP3410’s I2S transmitters must operate in slave mode (clocks generated by the
master). The transmit data must loaded into the transmit registers by the DSP
before the master begins clocking. After the master clock copies the second word
into the transmit shift register it sets the Transmit Data Empty (TDE) flag to signal
the DSP for more data. The Transmit Status/Control Register (TCS) configures the
I2S transmitters.
The left and right channel transmit registers also share the same DSP memory. The
first word write will go to the left channel data register. The second will go to the
right. Subsequent rights will alternate between left and right data registers.
16.2.2.1.
Transmit Status I2S Control Register
HW_SAITCSR
X:$FFF5
BITS LABEL RW RESET
DEFINITION
23:17 RSRVD R
0
Reserved
16
TUFCL RW
Transmitter Data Underflow Clear – When this bit is set by the DSP both the TUFL and
TDE flags are cleared. This bit is implemented as a one-shot and always reads a zero.
15
TDE
R
14
TUFL
R
13
12
RSRVD
TXIE
RW
Note: if TUFL is cleared in the last instruction of an Interrupt Service Routine triggered
by this bit, then the Interrupt will be executed twice.
Transmitter Data Empty Flag – Indicates that both left and right data words have been
down loaded to the shift register. This bit is cleared by writing a one to the TUFCL bit
(as explained above).
Transmitter Data Underflow – Indicates that an underflow condition was detected.
This condition occurs if all the transmit data registers are not written to in time (i.e.
TDE is still set when the transmitter loads the shift register with new Left Data,
implying that old data is re-transmitted.) This bit is cleared by writing a one to the
TUFCL bit.
Reserved
Transmitter Interrupt Enable for DSP – Interrupt enable for DSP.
Table 150. Transmit Status I2S Control Register Description
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BITS LABEL RW RESET
DEFINITION
11
TDWE RW
Transmitter Data Word Expansion – Determines the way that the 24-bit data word to
be transmitted is expanded to 32 bits during transmission.
0 - The last bit is transmitted 8 times AFTER transmitting the 24-bit data word
from the transmit data register.
1 - The first bit is transmitted eight times BEFORE transmitting the 24-bit data
word from the transmit data register is transmitted eight times.
10
TREL
RW
Transmitter Relative Timing – Determines the relative timing of the LRCKT signal as
referred to the serial data inputs.
0 - The transition of LRCKT occurs together with the first bit data.
1 - The transition of LRCKT occurs one SCKT earlier (I 2 S format).
9
TCKP RW
Transmitter Clock Polarity – Defines the polarity of the Transmitter clock.
1 - Positive Clock Polarity. Means the LRCKT and SDO lines change
synchronously with the positive edge of the clock, and are considered valid
during negative transitions.
0 - Negative Clock Polarity. Means the LRCKT and SDO lines change
synchronously with the negative edge of the clock, and are considered valid
during positive transitions
8
TLRS
RW
Transmitter Left Right Selection – Defines the polarity of the LRCKT.
0 - If LRCKT = 0 then Left Word, if LRCKT = 1 then Right Word.
1 - If LRCKT = 0 then Right Word, if LRCKT = 1 then Left Word.
7
TDIR
RW
Transmitter Data Shift Direction – Determines the shift direction of the transmitted data.
0 - MSB First
1 - LSB First.
6:5
TWL
RW 00
Transmitter World Length Control – Selects the length of the data word being
transmitted by the SAI.
00 - 16 Bits
01 - 24 Bits
10 - 32 Bits
11 Reserved.
4
RSRVD
Reserved
3
TMME RW 0
Transmitter master mode enable – Reserved, must be set to 0.
2
TEN2
RW 0
Transmitter Enable – Enable bit for Transmitter channel 2.
1
TEN1
RW 0
Transmitter Enable– Enable bit for Transmitter channel 1.
0
TEN0
RW 0
Transmitter Enable – Enable bit for Transmitter channel 0.
Table 150. Transmit Status I2S Control Register Description (Continued)
16.2.2.2.
Transmit Status I2S DataO0 Register
HW_SAITX0R
BITS
23:0
LABEL
TRANSMIT0
X:$FFF6
RW RESET
RW 0
DEFINITION
Data to be sent I2S_DataO0. Most significant bit is sent first. 16 bit transfer data
should be placed at most significant bytes (bits 23:16)
Table 151. Transmit Status I2S DataI0 Register Description
16.2.2.3.
HW_SAITX1R
BITS
23:0
LABEL
TRANSMIT1
RW RESET
RW 0
X:$FFF7
DEFINITION
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16.2.2.4.
HW_SAITX2R
BITS
23:0
LABEL
TRANSMIT2
X:$FFF8
RW RESET
RW 0
DEFINITION
16.2.3.
Timing
Figure 18 shows the SAI timings for both the RDR and TDE flags. Internal flags
allow some leeway in reading and writing the data registers as shown on the diagrams. The incoming and outgoing data is shifted in/out through a buffer shift register. This gives a full LRCKR half-period to service the RDR interrupt and read the
left word received before it is overwritten by the next left word received. The right
word will not be overwritten until the following LRCKR transition. Similarly for transmit there is a half-period of LRCKT from TDE being enabled to service the interrupt
and write the next left/right pair to be transmitted.
LRCKT
Left
Right
Left
Right
TDE
Internal Flag is set when left data is written to
all enabled transmitters. If this internal flag is
set then right data must be written to data
registers before the next falling edge of
LRCKT.
LRCKR
Left
TDE is cleared
when right data
is written to all
enabled
transmitters
Right
Left
Right
RDR
Internal Flag is set when left data is read
from all enabled receivers. If this internal flag
is set then right data must be read from data
registers before the next rising edge of
LRCKR.
RDR is cleared
when right data
is read from all
enabled
transmitters
Figure 18. Receive and Transmit Data Timing
16.2.4.
Setting SAI Mode
To enable the STMP3410 pins into SAI mode, set bit [15] of address X:$EC0F to a 1.
16.2.5.
Interrupts
The SAI interrupt vectors are located at the addresses shown in Table 154:
PRIORITY
Receiver Overflow
Transmitter Underflow
Receiver Data Ready
Transmitter Data Empty
PROGRAM ADDRESS
P:$0016
P:$0012
P:$0014
P:$0010
Table 154. SAI interrupts and Priorities
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17. TRACE BUFFER
The STMP3410 contains a trace buffer module that allows address/data on any of
the on-chip busses to be traced giving visibility into the execution of the DSP. This
eases software debug by allowing real-time triggering and capturing of data. The
trace buffer is designed to trigger on address/data on any bus and then capture
address/data to a memory buffer. It has 8 levels of triggering with the possibility to
capture up to 4k words. The following specification details all the features included
in the trace buffer.
17.1. Trace Buffer Specification
The trace buffer has the following feature set:
1. 4 kword trace buffer depth through on chip SRAM
2. 8 fully programmable levels of triggering
3. Low power consumption when not in use, as it would be for the final application
4. Full visibility of PAB, XAB, YAB, XAB_PER, PDB, XDB, YDB, XDB_PER
5. Programmable control of each trigger level so that reads and writes may be
separately detected.
6. 2 parallel trigger machines with AND, OR, and XOR functionality.
7. When capturing an address bus, the read and write bits are also captured in the
upper two bits. There are no bits available to capture this information when a
data bus is being captured.
With 8 trigger levels, this configuration requires 17 * 8 = 136 register bits. Each level
itself requires 24 bits of data, so 24*8 = 192 bits. The two mask registers require
2*24 = 48 bits. The CSR register contains the various bits, for a total of ? bits. This
gives a total of 371 total control bits.
Each trigger machine (there are currently 2 defined) requires compare logic and
muxing for all 9 trigger modes including an N-bit counter (24 max) used to count the
number of cycles after a given event. The 64 or 128 location memory could be
memory mapped into X or could be indirectly mapped into X peripheral space. Software macros could be used to extract the start and stop pointers from the CSR and
align the data properly in system memory. All unused bits in the trace buffer would
read ‘0’. Only the start and stop trigger pointers for the last level implemented would
be available to the system although it would be possible for data from more than
one level of trigger to remain in the trace buffer (such as successive uses of the End
trigger style).
SPECIAL NOTES ON TRACE BUFFER SECTION (issues below to be expounded
on in future data sheet release):
1) Documentation on the format of data capture into memory will be added in a
future data sheet revision.
2) Warning: Some P fetches, that will end up in the trace, will not be executed.
3) The trace buffer also traces read/writes done by the debugger.
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17.2. Trace Buffer Registers
17.2.1.
Trace Buffer Configuration Register
HW_TB_CSR
BIT
LABEL
X:$F080
RW RESET
23:16 RSRVD
15
TRIG REG
R
R
0
0
14:12 TBCURR
R
000
11
TB_CLK_EN RW
0
10:7
TBSIZE
RW
0000
6:5
TBASEL
RW
00
4:2
TBLVLS
RW
000
1
TBDONE
RW
0
0
TBEN
RW
0
DESCRIPTION
Reserved
0–
Trace buffer not triggered.
1–
Trace buffer is triggered.
Trace Buffer Current Level
000 – Trace buffer is currently at level 0
…
1 – Trace Buffer clock is enabled.
This bit has to be set first to ensure all registers are in the correct state. The
TBEN should be set after desired registers are written to.
Trace Buffer Trace size. This is the number of words that are written to memory
at any particular trace level when that level is set to capture data.
000 – Trace size = 20 = 1
001 – Trace size = 21 = 2
010 – Trace size = 22 = 4
…
111 – Trace size = 27 = 128
Trace Buffer DMA address select
00 – DMA into on-chip XRAM
01 – DMA into on-chip YRAM
10 – DMA into on-chip PRAM
11 – Reserved
Trace buffer levels. This field defines the number of trace buffer levels used in
the current trace operation. The trace buffer is done once the state machine
finishes the trigger level specified in this field.
Trace buffer done
0–
Trace buffer not done
1–
Trace buffer done
Trace buffer enable.
0–
Module disabled, clocks gated
1–
Trace buffer module enabled
Table 155. Trace Buffer Configuration Register Description
17.2.2.
Trace Buffer Base Address Register
HW_TB_BAR
BIT
LABEL
RW RESET
23:16 RSRVD R
15:0 TB_BAR RW
0
$0000
X:$F081
DESCRIPTION
Reserved
Trace Buffer Base address. This is the base address used to point to the DMA
memory buffer used for traces.
Table 156. Trace Buffer base address register Description
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17.2.3.
Trace Buffer Modulus Address Register
HW_TB_MOD
X:$F082
BIT
LABEL RW RESET
DESCRIPTION
23:12 RSRVD R
0
Reserved
11:0 TB_MOD RW 0
Trace Buffer Modulus address. This resister is used to specify the end of the DMA
memory buffer used for traces.
Table 157. Trace Buffer modulus address register Description
17.2.4.
Trace Buffer Current Address Register
HW_TB_CURR
X:$F083
BIT
LABEL
RW RESET
DESCRIPTION
23:12 RSRVD
R
0
Reserved
11:0 TB_CURR RW 0
Trace Buffer Current address. This resister is used to specify the current location
of the write point in the DMA memory buffer used for traces.
Table 158. Trace Buffer Current Address Register Description
17.2.5.
Trace Buffer Mask Registers
HW_TB_MASK0
HW_TB_MASK1
X:$F084
X:$F085
BIT
LABEL
RW
RESET
DESCRIPTION
23:0 TB_MASK0/1 RW Not initialized Trace Buffer Mask0/1. This register is used to filter bits out of the trigger
events. A 1 allows any bit to participate in the compare of that Trigger
level. A 0 will mask the bit off, creating a “don’t care” situation for that bit.
Table 159. Trace Buffer Mask Registers Description
17.2.6.
Trace Buffer Trigger Command Status Register
HW_TB_TCSR0
HW_TB_TCSR1
HW_TB_TCSR2
HW_TB_TCSR3
HW_TB_TCSR4
HW_TB_TCSR5
HW_TB_TCSR6
HW_TB_TCSR7
X:$F090
X:$F091
X:$F092
X:$F093
X:$F094
X:$F095
X:$F096
X:$F097
BIT
LABEL
23:17 RSRVD
16:13 TSRC
RW RESET
DESCRIPTION
R
0
Reserved
R
Not
Trigger source.
initialized
0000 – Trigger on dsp_pab
0101 – Trigger on dsp_xdb
0001 – Trigger on dsp_xab
0110 – Trigger on dsp_ydb
0010 – Trigger on dsp_yab
0111 – Trigger on dsp_xdb_per
0011 – Trigger on dsp_xab_per
1000 – Trigger on count
0100 – Trigger on dsp_pdb
others - Reserved
12:11 TCLASS RW Not
Trigger class.
initialized
00 – Unqualified trigger
10 – Trigger on writes only
01 – Trigger on reads only
11 – Trigger on reads or writes only
Table 160. Trace Buffer Trigger Command Status Register Description
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BIT
10:8
7:6
5:4
3:2
1:0
LABEL
CSRC
RW RESET
DESCRIPTION
RW Not
Capture source.
initialized
000 – Capture on dsp_pab
100 – Capture on dsp_pdb
001 – Capture on dsp_xab
101 – Capture on dsp_xdb
010 – Capture on dsp_yab
110 – Capture on dsp_ydb
011 – Capture on dsp_xab_per
111 – Capture on dsp_xdb_per
CCLASS RW Not
Capture class.
initialized
00 – Unqualified capture
10 – Capture writes only
01 – Capture reads only
11 – Capture reads or writes only
TSTYLE RW Not
Trigger style.
10 – Middle capture (capture around
initialized
00 – No capture
trigger)
01 – Top capture (capture after trigger) 11 – End capture (capture until trigger)
TMODE RW Not
Trigger mode.
initialized
00 – Single level trigger
10 – Two level OR trigger
01 – Two level AND trigger
11 – Two level XOR trigger
TMSEL RW Not
Trigger mask select.
initialized
00 - None
10 – Use Trigger mask1
01 – Use Trigger mask0
11 – All bits.
Table 160. Trace Buffer Trigger Command Status Register Description (Continued)
Note: The “Trigger on count” style can only be used in a single level trigger. Note
also that the TCLASS field must be set to “Unqualified” to use a “Trigger on count”
style trigger.
17.2.7.
Trace Buffer Trigger Value Register
HW_TB_TVAL0
HW_TB_TVAL1
HW_TB_TVAL2
HW_TB_TVAL3
HW_TB_TVAL4
HW_TB_TVAL5
HW_TB_TVAL6
HW_TB_TVAL7
BIT LABEL RW
23:0 TVAL
RW
RESET
X:$F098
X:$F099
X:$F09A
X:$F09B
X:$F09C
X:$F09D
X:$F09E
X:$F09F
DESCRIPTION
Not initialized Trigger value. This is the actual compare value the trace buffer uses to signal a
trigger to the state machine. If this value occurs on the bus currently being
monitored, a trigger will be generated and either data capture will begin or the
next level trigger event detection will be activated.
Table 161. Trace Buffer Trigger Value Register Description
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17.3. Trace Buffer State Machine
Figure 19 shows the state transition table for the Trace Buffer.
Not shown: If enable is
cleared in any state, the
state machine returns to
the Init state.
Init
ot ot
rn rn
ge o g
ig d lin
Tr urre e fil r
c n ffe
c
o do bu
Level 1 is last trigger
Enable set
Level 1
Trigger
ot ot
rn rn
ge o g
ig d lin
Tr urre fil r
c ne ffe
c
o
o d bu
Single level trigger and
buffer fill complete
Level 2
Trigger
ot ot
rn rn
ge o g
ig ed lin
Tr urr e fil r
c n ffe
c
o
o d bu
ot ot
rn rn
ge o g
ig d in
Tr urre e fill r
c n ffe
c
o do bu
ot ot
rn rn
ge o g
ig d lin
Tr urre fil r
c ne ffe
c
o do bu
Multi-level
trigger and
buffer fill
complete
Level 5
Trigger
Multi-level
trigger and
buffer fill
complete
Level 4
Trigger
ot ot
rn rn
ge o g
ig d lin
Tr urre e fil r
c n ffe
c
o do bu
Multi-level
trigger and
buffer fill
complete
Level 3
Trigger
Multi-level
trigger and
buffer fill
complete
Enable
Cleared
Multi-level
trigger and
buffer fill
complete
Level 6
Trigger
Multi-level
trigger and
buffer fill
complete
ot ot Single level trigger and
rn rn
ge o g
ig d lin
Tr urre fil r
e fe
c
n
Multi-level
oc do buf
trigger and
buffer fill
complete
ot ot
rn rn
ge o g
ig d lin
Tr urre fil r
c ne ffe
c
o do bu
Level 7
Trigger
Level 8
Trigger
ot ot
rn rn
ge o g
ig d lin
Tr urre fil r
c ne ffe
c
o do bu
Resting
Figure 19. Trace Buffer State Machine State Diagram
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18. GENERAL PURPOSE INPUT/OUTPUT (GPIO) MODULES
The STMP3410 contains 4 GPIO modules. These modules provide flexible software
control of each pin. Each digital pin can either be controlled by a hardware interface
(I2C, SPI, Flash, etc) or by a GPIO module. Every digital pin on the chip except for
TESTMODE, ONCE_DRN, ONCE_D1, ONCE_D0 and ONCE_CK can be used as
a GPIO pin. The GPIO configuration registers control the pin connection (GPIO or
normal interface) and the pin function (if it is in GPIO mode). The GPIO configuration is independent for all of the pins. For example, the SmartMedia SM_CE3n pin
can be configured as a GPIO pin while the other SmartMedia pins are connected to
the Flash interface. If a pin is switched to be a GPIO, then the internal module connected to that pin will see a logic 0 on that pin, irrespective of the actual status of
that pin.
The GPIO module is the only means of communicating with devices that don’t use
one of the STMP3410’s hardware interfaces. For example, LED/LCD’s that don’t
use I2C, FM tuners and other peripherals will require software that uses pins in
GPIO mode. The pins are also used in GPIO mode for functions such as Key Scan,
Backlights, SmartMedia card insert, etc.
BEGIN
HW_GPxPWR
Selects GPIO pins
as output
HW_GPxDOR
Sets Drive Strength
HW_GPx8MAR
Turn on output drive
on GPIO pins
configured as outputs
Turns ON/OFF Pin Power.
Must be turned on irrespective of whether
the pin is configured as a GPIO or not.
HW_GPxDIR
Selects GPIO pins
as inputs
HW_GPxIPENR
Select GPIO pins
that can generate
an interrupt
HW_GPxILVLR
Set interrupt level/
edge sensitivity
HW_GPxIPOLR
Set interrupt polarity
HW_GPxDOER
HW_GPxIENR
HW_GPxENR
Enable interrupt
Enable/Disable pins
as GPIOs
END
Figure 20. GPIO Setup Flow Chart
18.1. GPIO Interface
There are four GPIO Pin Registers (4 banks) on the STMP3410 used to configure
digital pins on the chip as GPIO or their designated function: GPIO0, GPIO1, GPIO2
and GPIO3 (See Section 18.2.12. on page 115 for details). The following registers
exist within each of these four banks to configure the chips digital pins. Some pins
only exist in the 144-pin package options. The registers that control those pins exist
but perform no useful function.
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18.2. GPIO Registers
18.2.1.
GPIO Enable Register
This register enables all the digital pins, except Testmode, on the chip to be GPIO or
perform assigned functionality, like interfacing to an LED/LCD.
HW_GP0ENR
HW_GP1ENR
HW_GP2ENR
HW_GP3ENR
X:$F400
X:$F410
X:$F420
X:$F430
BIT LABEL RW RESET
DESCRIPTION
23:0 EN
RW 0
Module Enable bits. These pins reset to 0.
0
Pin configured to perform assigned function
1
Pin configured as GPIO
Table 162. GPIO Enable Register Description
18.2.2.
GPIO Data Out Register
This register allows GPIO to send data out on a pin-by-pin basis. Always set this
register before GPIO Data Out Enable because as soon as the enable bit is set, the
current data on the pin is sent out.
HW_GP0DOR
HW_GP1DOR
HW_GP2DOR
HW_GP3DOR
X:$F401
X:$F411
X:$F421
X:$F431
BIT LABEL RW RESET
DESCRIPTION
23:0 DO
RW 0
Output bits if GPIO is set in GPIO Enable and the GPIO Output Enable bit is set.
Table 163. GPIO Data Out Register Description
18.2.3.
GPIO Data In Register
This register allows GPIO to input data on a pin-by-pin basis.
HW_GP0DIR
HW_GP1DIR
HW_GP2DIR
HW_GP3DIR
X:$F402
X:$F412
X:$F422
X:$F432
BIT LABEL RW RESET
DESCRIPTION
23:0
DI
R
0
Input bits if pin is in GPIO Mode and set as an input.
Table 164. GPIO Data In Register Description
18.2.4.
GPIO Data Out Enable Register
This register allows GPIO to enable data output on a pin-by-pin basis.
HW_GP0DOER
HW_GP1DOER
HW_GP2DOER
HW_GP3DOER
X:$F403
X:$F413
X:$F423
X:$F433
BIT LABEL RW RESET
DESCRIPTION
23:0
DOE RW 0
Output enable bits.
0
Input
1
Output
All GPIOs reset to Inputs on H/W or S/W reset.
Table 165. GPIO Data Out Enable Register Description
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18.2.5.
GPIO Interrupt Pin Enable Register
This register allows GPIO to define specific pins to be interrupt pins.
HW_GP0IPENR
HW_GP1IPENR
HW_GP2IPENR
HW_GP3IPENR
X:$F404
X:$F414
X:$F424
X:$F434
BIT LABEL RW RESET
23:0 IPEN
RW
0
DESCRIPTION
Interrupt enable bits.
0
Corresponding pin is not interrupt pin
1
Corresponding pin is an interrupt pin
Table 166. GPIO Interrupt Pin Enable Register Description
18.2.6.
GPIO Interrupt Enable Register
This register allows GPIO to enable specific interrupts to assert DSP interrupt. Note
that this register distinguishes between polling and interrupt driven routines. If a particular pin functions as an interrupt pin (as defined by GPIO Interrupt Pin Enable
register), it’s assertion will be reported in interrupt status register but interrupt signal
to DSP will not be asserted if GPIO Interrupt Enable bit is deserted. Once an interrupt has been received in the interrupt collector and it has been determined that it is
GPIO bank 0, 1, or 2, then this register is used to determine which pin asserted the
interrupt. See Table 170 for Interrupt Options.
HW_GP0IENR
HW_GP1IENR
HW_GP2IENR
HW_GP3IENR
X:$F405
X:$F415
X:$F425
X:$F435
BIT LABEL RW RESET
23:0 EN
RW
0
DESCRIPTION
Interrupt enable bits.
0
Interrupt Disable
1
Interrupt Enable
Table 167. GPIO Interrupt Enable Register Description
18.2.7.
GPIO Interrupt Level Register
This register allows GPIO to define specific pins to be level or edge sensitive if the
are enabled in GPIO Interrupt Enable register. See Table 170 for Interrupt Options.
HW_GP0ILVLR
HW_GP1ILVLR
HW_GP2ILVLR
HW_GP3ILVLR
X:$F406
X:$F416
X:$F426
X:$F436
BIT LABEL RW RESET
23:0 ILVL
RW 0
Interrupt level bits.
0
Edge Sensitive
1
Level Sensitive
DESCRIPTION
Table 168. GPIO Interrupt Level Register Description
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18.2.8.
GPIO Interrupt Polarity Register
This register allows GPIO to define specific pins to Active High/Low or Positive/Negative edge interrupt based on programming of corresponding bit in GPIO Interrupt
Enable and GPIO Interrupt Level register. See Table 170 for Interrupt Options.
HW_GP0IPOLR
HW_GP1IPOLR
HW_GP2IPOLR
HW_GP3IPOLR
X:$F407
X:$F417
X:$F427
X:$F437
BIT LABEL RW RESET
DESCRIPTION
23:0 IPOL
RW 0
Interrupt Polarity bits.
0
Active low level / falling edge
1
Active high level / rising edge
Table 169. GPIO Interrupt Polarity Register Description
HW_GPXIENR
(INT ENABLE)
0
1
1
1
1
HW_GPXILVLR
(INT LEVEL)
X
1
1
0
0
HW_GPXIPOLR
(INT POLARITY)
X
0
1
0
1
DESCRIPTION
Disable Interrupt Pin Functionality
Active Low Interrupt
Active High Interrupt
Falling Edge Interrupt
Rising Edge Interrupt
Table 170. GPIO Interrupt Options Table
18.2.9.
GPIO Interrupt Status Register
This register allows GPIO
grammed as an interrupt
interrupt to DSP.
HW_GP0ISTATR
HW_GP1ISTATR
HW_GP2ISTATR
HW_GP3ISTATR
to monitor and clear interrupts if corresponding bit is propin. Combination of interrupt status and enables assert
X:$F408
X:$F418
X:$F428
X:$F438
BIT LABEL RW RESET
DESCRIPTION
23:0 ISTAT RW 0
Interrupt status bits. Reading 1 indicates a pending interrupt. The bits in interrupt status
register are set irrespective of Interrupt Enable bits. To clear edge interrupt, set the
proper bit to 1. To clear a level interrupt, set the appropriate interrupt pin enable pin to 0.
Table 171. GPIO Interrupt Status Register Description
18.2.10. GPIO Pin Power Register
This register controls whether each pin is powered up irrespective of whether one
pin is configured as a GPIO pin or not. When a pin is powered down its input will
read as 0 irrespective of the voltage on the pin. Similarly, a pin that is powered down
will always be high impedance (i.e. tristated) even if the pin is configured as an output. All pins are powered down after a chip reset.
HW_GP0PWR
X:$F409
HW_GP1PWR
X:$F419
HW_GP2PWR
X:$F429
HW_GP3PWR
X:$F439
BIT LABEL RW RESET
23:0 PWR
RW 0
114
DESCRIPTION
0
Pin is powered down (reset value)
1
Pin is powered up (i.e. active)
Table 172. GPIO Pin Power Register Description
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18.2.11. GPIO Pin Drive Strength Register
This register controls the output drive strengths of groups of pins, when the pins are
configured as outputs. Note that unlike other GPIO registers, each pin does not get
its own control bit. Instead pins are assigned in groups of 8 to an individual control
bit. Each group of pins can be configured as 4mA drivers, or 8mA drivers. The
required setting will depend on the application, but in general it is recommended
that as many pins as possible are configured in 4mA mode. Doing so will increase
the number of simultaneously pins that can be supported without adverse effects on
the rest of the system, and will reduce the momentary peak load on the DCDC converters, and will reduce EMI emissions. A conservative limit on the maximum number of simultaneously switching output pins for the STMP3410 would be 24 4mA
pins, or 12 8mA pins, or an equivalent combination of 4mA and 8mA pins.
It is possible to save some power by gating the clocks in the GPIO modules, this
functionality is controlled by the CLKGATE field of the GPIO Pin Drive Strength register. When the clocks are gated, the DSP will no longer be able to write to any of
the GPIO control registers, except for this one. When the clocks are gated, GPIO
interrupts will continue to be generated, and the DSP will have full read access to all
registers, inlcuding the GPIO Data Input registers. The DSP will need to clear the
CLKGATE bit before it can change the value of pin configured as a GPIO output.
HW_GP08MA
HW_GP18MA
HW_GP28MA
HW_GP38MA
BIT
LABEL
RW RESET
23
CLKGATE RW 0
22:4 RSRVD
2
PDS2
R
RW
1
PDS1
RW
0
PDS0
RW
0
0
X:$F40A
X:$F41A
X:$F42A
X:$F43A
DESCRIPTION
0 Clocks not gated
1 Clocks gated
Reserved
Controls bits [23:16]
0
4 mA driver
1
8 mA driver
0
Controls bits [15:8]
0
4 mA driver
1
8 mA driver
0
Controls bits [7:6]
0
4 mA driver
1
8 mA driver
Table 173. GPIO Pin Drive Strength Register Description
18.2.12. GPIO Register Pin Assignments
18.2.12.1. GPIO0 (Bank 0)
GPIO0
BIT
LABEL
23:20
19
18
17
16
15
14
13
RSRVD
GP0B19
GP0B18
GP0B17
GP0B16
GP0B15
GP0B14
GP0B13
X:$F400–$F40A
PIN NAME (NOTE 1)
DESCRIPTION
Reserved
GP19
GP18
GP17
GP16
GP15
GP14
GP13
Table 174. GPIO0 Pin Register (Bank 0) Description
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BIT
LABEL
12
11
10
9
8
7
6
5
4
3
2
1
0
Note:
GP0B12
GP0B11
GP0B10
GP0B9
GP0B8
GP0B7
GP0B6
GP0B5
GP0B4
GP0B3
GP0B2
GP0B1
GP0B0
PIN NAME (NOTE 1)
DESCRIPTION
GP12
GP11
GP10
GP9
GP8
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
1. Please see Table 229. “General Purpose Input/Output Pins” on page 169.
Table 174. GPIO0 Pin Register (Bank 0) Description (Continued)
18.2.12.2. GPIO1 (Bank 1)
GPIO1
BIT
LABEL
PIN NAME (NOTE 1)
X:$F410–$F41A
DESCRIPTION
23
GP1B23 GP47
22
GP1B22 GP46
21
GP1B21 GP45
20
GP1B20 GP44
19
GP1B19 GP43
18
GP1B18 GP42
17
GP1B17 GP41
16
GP1B16 GP40
15
GP1B15 GP39
14
GP1B14 GP38
13
GP1B13 GP37
12
GP1B12 GP36
11
GP1B11 GP35
10
GP1B10 GP34
9
GP1B9
GP33
8
GP1B8
GP32
7
GP1B7
GP31
6
GP1B6
GP30
5
GP1B5
GP29
4
GP1B4
GP28
3
GP1B3
GP27
2
GP1B2
GP26
1
GP1B1
GP25
0
GP1B0
GP24
Note: 1. Please see Table 229. “General Purpose Input/Output Pins” on page 169.
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18.2.12.3. GPIO2 (Bank 2)
GPIO2
BIT
23
22
21
20
19
18
17
16
15
14
13
12:9
8
7
6
5
4
3
2
1
0
Note:
LABEL
RSRVD
GP2B22
GP2B21
GP2B20
GP2B19
GP2B18
GP2B17
GP2B16
GP2B15
GP2B14
GP2B13
RSRVD
GP2B8
GP2B7
GP2B6
GP2B5
GP2B4
GP2B3
GP2B2
GP2B1
GP2B0
X:$F420 – $F42A
PIN NAME (NOTE 1)
DESCRIPTION
Reserved
GP70
GP69
GP68
GP67
GP66
GP65
GP64
GP63
GP62
GP61
Reserved
GP56
GP55
GP54
GP53
GP52
GP51
GP50
GP49
GP48
1. Please see Table 229. “General Purpose Input/Output Pins” on page 169..
18.2.12.4. GPIO3 (Bank 3)
GPIO3
BIT
LABEL
23:22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
RSRVD
GP3B21
GP3B20
GP3B19
GP3B18
GP3B17
GP3B16
GP3B15
GP3B14
GP3B13
GP3B12
GP3B11
GP3B10
GP3B9
GP3B8
X:$F430 – $F43A
PIN NAME (NOTE 1)
DESCRIPTION
Reserved
GP93
GP92
GP91
GP90
GP89
GP88
GP87
GP86
GP85
GP84
GP83
GP82
GP81
GP80
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BIT
7
6
5
4
3
2
1
0
Note:
LABEL
GP3B7
GP3B6
GP3B5
GP3B4
GP3B3
GP3B2
GP3B1
GP3B0
PIN NAME (NOTE 1)
DESCRIPTION
GP79
GP78
GP77
GP76
GP75
GP74
GP73
GP72
1. Please see Table 229. “General Purpose Input/Output Pins” on page 169..
Table 177. GPIO2 Pin Register (Bank 3) Description (Continued)
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19. DAC/ADC/MIXER/HEADPHONE/LRADC
19.1. DAC
The DAC on the STMP3410 behaves as a DMA device which outputs data from a
modulo buffer in X/Y/P memory specified by software configuration. Software
configuration begins by programming the DAC Base Address Register
(HW_DACBAR), the DAC Modulo Register (HW_DACMR), and the DAC Current
Position Register (HW_DACCPR) to specify the base address and modulo of the
buffer to be used by the DAC as well as the current position in the DAC buffer. Next,
the buffer is filled by software. The sample rate of the DAC may be specified in the
DAC Sample Rate Register (HW_DACSRR). The sample rate of the DAC can be
adjusted with fine resolution using this register. The number of samples available is
specified in the DAC Word Count Register (HW_DACWCR). Finally, transmit is
enabled, and the DAC begins to output data. As each DSP word is processed, the
DAC Word Count Register (HW_DACWCR) is decremented and the DAC Current
Position Register (HW_DACCPR) is incremented. When the word count reaches
zero, an interrupt will occur if interrupts have been enabled in the DAC Control
Status Register (HW_DACCSR). Software is then responsible for writing to
HW_DACWCR register indicating more data is available. If the HW_DACWCR is
not updated before the next sample is needed by the DAC, an exception will occur,
and a DAC underflow interrupt will be generated.
DAC data in stored in X/Y/P memory with the left channel sample in the lowest
address, followed by the corresponding right channel sample in the next memory
location. The DAC data should always consist of an even number of samples to
allow left and right channels, it is not possible to play mono data unless the mono
samples are each repeated twice in memory, once for the left channel and once for
the right channel. The data is stored as 24 bit 2’s compliment values, where the full
scale value depends on the programming of the sample rate converter. The DAC
expects data samples that already have been 2x oversampled by code in the DSP,
i.e. to play 44.1k sample/sec data, there should be 44.2k * 2 = 88.4k samples/sec
per channel in memory.
Before the DAC can be turned on and used, the crystal clock used by the DAC and
mixer must be enabled using the ACKEN bit of the Clock Control Register
(HW_CCR). Also the DAC and Mixer analog circuitry must be powered up using the
PR1 & PR2 bits of the Mixer Powerdown Control/Status Register
(HW_MIXPWRDNR).
19.1.1.
DAC Registers
19.1.1.1.
DAC Base Address Register
The HW_DACBAR is used to specify the base address of the modulo buffer used by
the DAC port. The buffer’s base address must zero the k LSBs, where 2k >=
HW_DACMR.
HW_DACBAR
BIT
LABEL RW RESET
23:16 RSRVD R
15:0 BAR
RW
0
0
X:$F805
DESCRIPTION
Reserved
Base address for the DAC output sample buffer in memory.
Table 178. DAC Base Address Register Description
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19.1.1.2.
DAC Modulo Register
The DAC Modulo Register specifies the modulus of the DAC buffer. The modulus
specified in the same manner as the Mn modulo registers of the Address Generation Unit of the DSP core. For example, writing $000001 to the HW_DACMR indicates a modulo buffer of size $000002.
HW_DACMR
BIT
X:$F804
LABEL RW RESET
23:10 RSRVD R
9:0
MR
RW
0
0
DESCRIPTION
Reserved
Modulo (i.e. size) of the DAC output sample buffer in memory.
Table 179. DAC Modulo Register Description
19.1.1.3.
DAC Current Position Register
The DAC Current Position Register indicates the address offset from the address
specified in the HW_DACBAR DAC Base Address Register where the DAC will read
the next output sample.
HW_DACCPR
BIT
X:$F803
LABEL RW RESET
23:10 RSRVD R
9:0
CPR
RW
0
0
DESCRIPTION
Reserved
Current read position of the DAC output sample buffer in memory.
Table 180. DAC Current Position Register Description
19.1.1.4.
DAC Word Count Register
The DAC Word Count Register specifies the number of words to be output until the
next interrupt is generated. Software should fill the memory buffer with sample data,
then program the HW_DACWCR to indicate the number of words available to the
DAC to be output. For each sample output, the HW_DACWCR is decremented
twice, one each for the left and right samples. When the HW_DACWCR=0, an interrupt is generated. If the HW_DACWCR is not updated before the DAC requires
another sample (i.e., underrun), then and exception occurs (TSEXC in the
HW_DACCSR is set). Writing to the HW_DACWCR also clears any pending DAC
interrupts.
This register counts words in memory, not samples. Since the DAC operates on stereo data, the number of words will be twice the number of samples.
HW_DACWCR
BIT
LABEL RW RESET
23:10 RSRVD R
9:0
WCR
RW
0
0
X:$F802
DESCRIPTION
Reserved
Number of DAC samples remaining until a DAC interrupt will be generated.
Table 181. DAC Word Count Register Description
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19.1.1.5.
DAC Sample Rate Register
The DAC Sample Rate Register is programmed to specify the sample rate of the DAC.
HW_DACSRR
X:$F801
BIT LABEL RW RESET
23
RSRVD R
22:0 SR
RW
0
0
DESCRIPTION
Reserved
Sample Rate to use for DAC playback.
Table 182. DAC Sample Rate Register Description
The value of the HW_DACSRR register is calculated according to the following
formula.
HW_DACSRR = 010000 ( OSR DAC – 1 )
where
8 × Fanalog DAC
OSRDAC = --------------------------------------------128 × FsampleDAC
Where Fanalog is the sample rate of the DAC analog circuitry as specified by the
ADIV1 field of the HW_CCR Clock Control Register., and Fsamples is the sample
rate of the DAC data being played. This formula assumes the presence of a 1->2
interpolation filter running on the DSP to generate the final DAC samples read by
the hardware, the DAC hardware expects samples in memory that are 2 times oversampled compared to the desired sample rate.
The value stored in the HW_DACSRR is interpreted as a 24 bit 2’s compliminent
signed value, and since a negative value doesn’t make sense, the MSB must be set
to 0 for valid operation.
If we use the reset value of Fanalog = 128 x 48 kHz, then Table 183 contains the
required value of the HW_DACSSR register for various common sample rates. If
SAMPLE RATE
HW_DACSRR VALUE
48,000 Hz
44,100 Hz
32,000 Hz
24,000 Hz
22,050 Hz
16,000 Hz
12,000 Hz
11,025 Hz
8,000 Hz
$070000
$07B51E
$0B0000
$0F0000
$106A3B
$170000
$1F0000
$210476
$2F0000
Table 183. Example values for the HW_DACSRR register
the crystal is changed from the normal 24.576 MHz rate, the Fanalog freqency will
change, and the HW_DACSSR register will need to be changed to compensate.
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19.1.1.6.
DAC Control Status Register
HW_DACCSR
BITS
LABEL
RW RESET
23
CLKGT
RW 0
22:7
6:5
RSRVD
R 0
DMASEL RW 00
4
LPBK
RW 0
3
TXEXC
RW 0
2
TXI
RW 0
1
TXIEN
RW 0
0
TXEN
RW 0
X:$F800
DEFINITION
Clock gate. Used to disable the clocks to the DAC module to conserve power when
the DAC is not in use. Must be set to 0 before writing to any other DAC registers.
0Clocks not gated
1Clocks are gated
00 - X space
01 - Y space
10 - P space
11 - Reserved
Loopback – When set, the LPBK bit connects the ADC single bit data from the ADC
analog circuitry directly to the DAC analog circuitry to perform an analog loopback
test without utilizing the DSP core.
Transmit Exception – The TXEXC bit is a status bit indicating a transmit exception
has occurred. A transmit exception occurs when the DAC needs to read a sample
but the HW_DACWCR is zero indicating no samples are available. The TXEXC bit
is cleared by writing a 0 to this location. The TXEXC can also be cleared by writing
to the HW_DACWCR register.
Transmit Interrupt – The TXI bit is a status bit indicating a transmit interrupt has
occurred. The TXI bit is cleared by writing a 0 to this location. The Transmit Interrupt
can also be cleared by writing to the HW_DACWCR register.
Transmit Interrupt Enable – The TXIEN bit enables interrupt generation for this port.
When the HW_DACWCR reaches zero, an interrupt is generated.
Transmit Enable – Setting the TXEN bit causes the DAC Port to begin outputting
samples from the modulo buffer specified by the HW_DACBAR, HW_DACMR, and
HW_DACWCR. When TXEN is cleared, the TXI and TXEXC bits are cleared. No
other DAC registers are cleared.
Table 184. DAC Control Status Register Description
19.2. ADC
The ADC on the STMP3410 behaves as a DMA device which places data in a modulo buffer in X/Y/P memory specified by software configuration. Software configuration begins by programming the ADC Base Address Register (HW_ADCBAR), the
ADC Modulo Register (HW_ADCMR), and the ADC Current Position Register
(HW_ADCCPR) to specify the base address and modulo of the buffer to be used by
the ADC as well as the current position in the ADC buffer. The sample rate of the
ADC may be specified in the ADC Sample Rate Register (HW_ADCSRR). The
number of samples available are specified in the ADC Word Count Register
(HW_ADCWCR). At this point transmit is enabled and the ADC begins input of
data. As each DSP word is input, the HW_ADCWCR is decremented and the ADC
Current Position Register (HW_ADCCPR) is incremented. When the word count
reaches zero, an interrupt will occur if interrupts have been enabled in the ADC
Control Status Register (HW_ADCCSR). Software is then responsible for writing to
HW_ADCWCR register indicating space for more data is available. If the
HW_ADCWCR is not updated before the next sample would be needed by the
ADC, an exception will occur and an ADC overflow interrupt will be generated.
ADC data is stored in X/Y/P memory with the left channel sample in the lowest
address, followed by the corresponding right channel sample in the next memory
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location. The ADC data always consists of an even number of samples to allow left
and right channels, it is not possible to record mono data unless the stereo data is
recorded and one of the channels is thrown away by the DSP software. The data is
stored as 24 bit 2’s compliment values, where the full scale value depends on the
programming of the sample rate converter. The ADC generates data samples that
are 8x oversampled, and that need to be decimated to the base rate by code in the
DSP. For example, to record 44.1k sample/sec data, the ADC will generate 44.1k * 8
= 352.8k samples/sec per channel in memory, which must be filtered and decimated
down to 44.1k samples/sec by code executing on the DSP.
Before the ADC can be turned on and used, the crystal clock used by the ADC must
be enabled using the ACKEN bit of the HW_CCR Clock Control register. Also the
ADC analog circuitry must be powered up using the PR0 bit of the
HW_MIXPWRDNR Mixer Powerdown Control/Status register.
19.2.1.
ADC Registers
19.2.1.1.
ADC Base Address Register
The HW_ADCBAR is used to specify the base address of the modulo buffer used by
the ADC. The buffer’s base address must zero the k LSBs, where 2k >=
HW_ADCMR.
HW_ADCBAR
X:$FB05
BIT LABEL RW RESET
DESCRIPTION
23:16 RSRVD R
0
Reserved
15:0 BAR
RW 0
Base address for the ADC input sample buffer in memory.
Table 185. ADC Base Address Register Description
19.2.1.2.
ADC Modulo Register
The ADC Modulo Register specifies the modulus of the ADC buffer. The modulus
specified in the same manner as the Mn modulo registers of the Address Generation Unit. For example, writing $0001 to the HW_ADCMR indicates a modulo buffer
of size $0002.
HW_ADCMR
X:$FB04
BIT LABEL RW RESET
DESCRIPTION
23:10 RSRVD R
0
Reserved
9:0
MR
RW 0
Modulo (i.e. size) of the ADC input sample buffer in memory.
Table 186. ADC Modulo Register Description
19.2.1.3.
ADC Current Position Register
The ADC Current Position Register indicates the address offset from the address
specified by the ADC Base Address Register (HW_ADCBAR) where the ADC will
write the next output sample to.
HW_ADCCPR
X:$FB03
BIT LABEL RW RESET
DESCRIPTION
23:10 RSRVD R
0
Reserved
9:0
CPR
RW 0
Current write position of the ADC input sample buffer in memory.
Table 187. ADC Current Position Register Description
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19.2.1.4.
ADC Word Count Register
The ADC Word Count Register specifies the number of words to be output until the
next interrupt is generated. Software should fill the memory buffer with sample data,
then program the HW_ADCWCR to indicate the number of words available to the
ADC to be output. For each sample output, the HW_ADCWCR is decremented
twice, once each for the left and right samples. When the HW_ADCWCR=0, an
interrupt is generated. If the HW_ADCWCR is not updated before the ADC requires
another sample (i.e., overrun), then an exception occurs (TXEXC in the
HW_ADCCSR is set).
This register counts words in memory, not samples. Since the ADC operates on
stereo data, the number of words will be twice the number of samples.
HW_ADCWCR
X:$FB02
BIT LABEL RW RESET
DESCRIPTION
23:10 RSRVD R
0
Reserved
9:0
WCR
RW 0
Number of ADC samples remaining until an ADC interrupt will be generated.
Table 188. ADC Word Count Register Description
19.2.1.5.
ADC Sample Rate Register
The ADC Sample Rate Register is programmed to specify the sample rate of the ADC.
HW_ADCSRR
X:$FB01
BIT LABEL RW RESET
DESCRIPTION
23
RSRVD R
0
Reserved
22:0 SR
RW 0
Sample Rate to use for ADC recording.
Table 189. ADC Sample Rate Register Description
The value of the HW_ADCSSR register is calculated according to the following formula..
HW_ADCSRR = 010000 ( OSR ADC – 1 )
where
16 × FanalogADC
OSRADC = --------------------------------------------128 × FsampleADC
Where Fanalog is the sample rate of the ADC analog circuitry as specified by the
ADIV0 field of the Clock Control Register (HW_CCR), and Fsamples is the desired
sample rate of the ADC data being recorded. This formula assumes the presence of
a 8->1 decimation filter running on the DSP to generate the final ADC samples at
the sample rate desired, in other words, the ADC hardware will generate samples in
memory that are 8 times oversampled compared to the desired sample rate.
The value stored in the HW_ADCSSR is interpreted as a 24 bit 2’s compliminent
signed value, and since a negative value doesn’t make sense, the MSB must be set
to 0 for valid operation.
If we use the reset value of Fanalog = 128 x 48 kHz, then the following table contains the required value of the HW_ADCSSR register for various common sample
rates. If the crystal is changed from the normal 24.576 MHz rate, the Fanalog frequency
will change, and the HW_ADCSSR register will probably need to be changed to
compensate.
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SAMPLE RATE
48,000 Hz
44,100 Hz
32,000 Hz
24,000 Hz
22,050 Hz
16,000 Hz
12,000 Hz
11,025 Hz
8,000 Hz
HW_ADCSRR VALUE
$0F0000
$106A3B
$170000
$1F0000
$21D476
$2F0000
$3F0000
$44A8ED
$5F0000
Table 190. Example values for the HW_ADCSRR register
19.2.1.6.
ADC Control Status Register
HW_ADCCSR
BITS
LABEL
RW RESET
23
CLKGT
RW 0
22:7
6:5
RSRVD
R 0
DMASEL RW 00
4
LPBK
RW 0
3
TXEXC
RW 0
2
TXI
RW 0
1
TXIEN
RW 0
0
TXEN
RW 0
X:$FB00
DEFINITION
Clock gate. Used to disable the clocks to the ADC module to conserve power when
the ADC is not in use. This bit must be set to 0 before writing to any other ADC
registers, and while the ADC is operating.
0Clocks enabled
1Clocks gated
00 - X space
01 - Y space
10 - P space
11 - Reserved
Loopback – When set, the LPBK bit connects the DAC single bit data output from the
DAC digital circuitry directly to the ADC digital circuitry to perform a digital loopback
test without utilizing the analog circuitry.
Transmit Exception – The TXEXC bit is a status bit indicating a transmit exception
has occurred. A transmit exception occurs when the ADC needs to write a sample
but the HW_ADCWCR is zero indicating no room is available in the module buffer.
This register can also be cleared by writing to the HW_ADCWCR register. The
TXEXC bit is cleared by writing a 0 to this location.
Transmit Interrupt – The TXI bit is a status bit indicating a transmit interrupt has
occurred. This register can also be cleared by writing to the HW_ADCWCR register.
The TXI bit is cleared by writing a 0 to this location.
Transmit Interrupt Enable – This bit enables interrupt generation for the ADC. When
the HW_ADCWCR register reaches zero, an interrupt is generated.
Transmit Enable – Setting the TXEN bit causes the ADC Port to begin outputting
samples into the modulo buffer specified by the HW_ADCBAR, HW_ADCMR, and
HW_ADCWCR registers. When TXEN is cleared, the TXI and TXEXC bits are
cleared. No other ADC registers are cleared.
Table 191. ADC Control Status Register Description
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19.3. Mixer
19.3.1.
Mixer Address Registers
ADDRESS
DESCRIPTION
X:$FA03
X:$FA04
X:$FA05
X:$FA06
X:$FA07
X:$FA08
X:$FA09
X:$FA0A
X:$FA0B
Codec/mixer test register
Mixer master volume register
Mixer Microphone in volume register
Mixer Line In volume register
Mixer FM In volume register
Mixer DAC In volume register
Mixer Record Select register
Analog ADC gain register
Mixer Power down/control stat register
Table 192. Mixer Address Registers
19.3.2.
Mixer Block Diagram
The analog level of the signals mixed throughout the STMP3410 can be controlled
through registers. The block diagram is shown in Figure 22. The microphone channel is
a mono source, so its signal is available on both the left and right channels.
HW_MIXLINE1INVR
LINEIN
HW_MIXMICINV
HW_MIXMASTERVR
MICIN
+
HW_MIXLINE2INVR
OUTPUT
HW_HPCTRL
FMIN
HW_MIXDACINVR
FROM
DAC
BUFFER
DAC
CLK
EN
HW_DACCSR[0]
HW_DACSRR
CLK
CRYSTAL
HW_CCR[22:20]
HW_CCR[3]
HW_CCR[18]
HW_MIXADCINR
HW_MIXADCGAINR
LINEIN
FMIN
ADC
MICIN
CLK
CLK
CRYSTAL
HW_CCR[7:5]
HW_CCR[18]
HW_ADCSRR
TO ADC
BUFFER
EN
HW_ADCCSR[0]
HW_CCR[3]
Figure 21. Mixer Flow Diagram
Note that when the mixer is powered down (using the PR2 field of the
HW_MIXPWRDNR register), the DAC can still play audio through the headphone
amplifier to the output. This mode has the dual advantage of saving the power
consumption of the analog mixer, as well as eliminating the mixer as a source of
SNR or THD loss.
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LINEIN
INEIN
MICIN
MIC+20dB
bits of
MICIN reg
LINEIN
MICIN
MICIN
Headphone
(HPH)
+
FMIN
FMIN
MICIN
Headphone
(HPH)
Output
Master Volume Stage
(MASTERV)
DACIN
DACIN
MIC+20dB
bits of
MICIN reg
Output
FMIN
DACIN
ADC Max.
(RECSELECT)
Master Volume Stage
(MASTERV)
DACIN
ADC Max.
(RECSELECT)
ADC In
ADCGAIN
ADC In
ADCGAIN
(PR2 = 0)
(PR2 = 1)
Mixer Powered Up
Mixer Powered Down
Figure 22. Mixer Block Diagram
19.3.3.
Mixer Programming Model
The various mixer control registers are summarized below.
19.3.3.1.
Mixer Master Volume Register
The ML field adjusts the level for the left channel master output, while the MR field
adjusts the level for the right channel master output. Each increment of the ML/MR
fields represents 1.5 dB of attenuation of the master volume output on the mixer.
The Mute bit will silence the output regardless of the current settings of the ML/MR
bits. The master volume can only attenuate the mixer output level.
HW_MIXMASTERVR X:$FA04
BITS LABEL RW RESET
23:16 RSRVD R
0
15
MUTE RW 1
14:13
12:8
7:5
4:0
RSRVD
ML
RSRVD
MR
R
RW
R
RW
0
00000
0
00000
DEFINITION
Reserved
Mixer Master mute control
0unmuted
1muted
Reserved
Mixer Master volume control for left channel
Reserved
Mixer Master volume control for right channel
Table 193. Mixer Master Volume Register Description
MUTE
ML/MR
LEVEL
0
0
1
0 0000
1 1111
X XXXX
0 dB
-46.5 dB
-infinity
Table 194. Master Volume Register values
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19.3.3.2.
Analog Mixer Volume Registers
This section refers to the MicIn, Line-In, Line-In 2 (also know as FM-In), and DAC
registers listed below. The GL fields adjust the gain for the left channel of the analog
input, while the GR fields adjust the gain for the right channel of the analog input.
For the MicIn, there is only one channel adjusted by the GN field, although the
results of this volume stage are available on both channels of the mixer. Each increment of the GL/GR/GN fields represents -1.5 dB of adjustment in the gain level. All
analog mixer inputs have a mute bit which will silence this analog input regardless of
the settings of the GL/GR/GN bits. The MicIn additionally has a 20 dB boost bit
which provides a fixed 20 dB boost to the microphone signal when set. Unlike the
master volume, each analog mixer input has the ability to apply gain or attenuation
to the analog signal.
MUTE
0
0
0
1
GL/GR/GN
0 0000
0 1000
1 1111
X XXXX
LEVEL
+12 dB
0 dB
-34.5 dB
-infinity
Table 195. Analog Mixer Volume Registers
19.3.3.2.1.
Mixer Microphone-In Volume Register
HW_MIXMICINVR
BITS
23:16
15
14:7
6
LABEL
RSRVD
MUTE
RSRVD
20DB
RW
R
RW
R
RW
RESET
0
1
0
0
5
4:0
RSRVD R
0
GN
RW 01000
X:$FA05
DEFINITION
Reserved
Mixer Microphone In mute
Reserved
Mixer Microphone In boost
0no boost
120 dB boost
Reserved
Mixer Microphone-In volume
Table 196. Mixer Microphone-In Volume Register Description
The external microphone needs a bias voltage to enable it to operate. This bias
voltage can be generated externally using discrete components as shown in
Figure 23, or if the LINE1R pin is available, it can be used to supply a bias voltage
from on on-chip generator, as shown in Figure 24. To enable the generation of the
microphone bias voltage on the LINE1R pin, the MICBIAS bits in the HW_MIXTBR
need to be set to the required value. Also the bias voltage used comes from the
LRADC, so the LRADC auxilliary channel must be powered up using the AUXPWD
bit in the HW_LRADCCR register.
MIC
0.1µF
Microphone
2.2k
VddIO 2.2k
0.1µF
10µF
Figure 23. External Microphone Bias Generation
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MIC
0.1µF
Microphone
HW_CMTR
MICBIAS
LINE1R
2k
LRADC
AUX
4k
8k
2.8V
HW_LRADCCR
AUXPWD
Figure 24. Internal Microphone Bias Generation
19.3.3.2.2.
Mixer Line-In Volume Register
HW_MIXLINE1INVR
BITS
23:16
15
14:13
12:8
7:5
4:0
LABEL
RSRVD
MUTE
RSRVD
GL
RSRVD
GR
RW
R
RW
R
RW
R
RW
RESET
0
1
0
01000
0
01000
X:$FA06
DEFINITION
Reserved
Mixer Line-In mute
Reserved
Mixer Line-In left channel volume
Reserved
Mixer Line-In right channel volume
Table 197. Mixer Line-In Volume Register Description
19.3.3.2.3.
Mixer Line-In 2 Volume Register
Line-In 2 is also know as FM-In, although nothing about this input restricts it to only
be used with an FM source, it can also be used with other sources. This input channel is only available in 144-pin package versions of the STMP3410.
HW_MIXLINE2INVR
X:$FA07
BITS LABEL RW RESET
23:16
15
14:13
12:8
7:5
4:0
RSRVD
MUTE
RSRVD
GL
RSRVD
GR
R
RW
R
RW
R
RW
0
1
0
01000
0
01000
DEFINITION
Reserved
Mixer Line-in 2 mute
Reserved
Mixer Line-in 2 left channel volume
Reserved
Mixer Line-in 2 right channel volume
Table 198. Mixer Line-in 2 Volume Register Description
19.3.3.2.4.
Mixer DAC In Volume Register
HW_MIXDACINVR
BITS LABEL RW RESET
23:16
15
14:13
12:8
7:5
4:0
RSRVD
MUTE
RSRVD
GL
RSRVD
GR
R
RW
R
RW
R
RW
0
1
0
01000
0
01000
X:$FA08
DEFINITION
Reserved
Mixer DAC mute. This bit is only valid when PR2 in FA0B = 0.
Reserved
Mixer DAC Left channel volume
Reserved
Mixer DAC right channel volume
Table 199. DAC In Volume Register Description
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19.3.3.2.5.
Mixer Record Select Register
HW_MIXRECSELR
X:$FA09
BITS LABEL RW RESET
23:12
11
10:8
7:3
2:0
RSRVD R
0
DEFINITION
Reserved
SL
RW 000
RSRVD R
0
SR
RW 000
Mixer Record Left channel select
Reserved
Mixer Record Right channel select
Table 200. Mixer Record Select Register Description
SR
RIGHT RECORD SELECT
000
001
010
011
100
101
110
111
SL
Mic-in
Reserved
Reserved
Line-in2 (AKA FM-in)
Line-in
StereoMix
Reserved
Reserved
000
001
010
011
100
101
110
111
LEFT RECORD SELECT
Mic-in
Reserved
Reserved
Line-in2 (AKA FM-in)
Line-in
StereoMix
Reserved
Reserved
Table 201. ADC Select Register
19.3.3.3.
Mixer ADC Gain Register
The record gain register provides gain only to the analog signal being input into the
ADC. The GL field adjusts the left channel, while the GR field adjusts the right
channel. Each increment of these fields represents -1.5 dB of gain. The mute bit will
silence the input regardless of the settings of the GL/GR fields.
HW_MIXADCGAINR X:$FA0A
BITS LABEL RW RESET
23:16
15
14:12
11:8
7:4
3:0
RSRVD
MUTE
RSRVD
GL
RSRVD
GR
R
RW
R
RW
R
RW
0
1
0
0000
0
0000
DEFINITION
Reserved
Mixer ADC Gain mute
Reserved
Mixer ADC Gain left channel
Reserved
Mixer ADC Gain right channel
Table 202. Mixer ADC Gain Register Description
MUTE
GL/GR
LEVEL
0
0
1
1111
0000
XXXX
+22.5 dB
0 dB
-infinity
Table 203. ADC Gain Register
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19.3.3.4.
Mixer Power Down Control/Status Register
HW_MIXPWRDNR
X:$FA0B
BITS LABEL RW RESET
23:12 RSRVD R
0
11
PR2
RW 1
10
PR1
RW 1
9
PR0
RW 1
8:0
RSRVD R
DEFINITION
Power down analog mixer
0Analog mixer powered up
1Analog mixer powered down
When the analog mixer is powered down, it is still possible to play audio through the
DAC. The reference voltage generator is still powered up, and if the DAC is still
powered up and playing audio, the audio is routed directly into the master volume
stage, bypassing the analog mixer. Aside from saving power, this mode of operation
has the added advantage of providing better SNR/THD performance.
Power down DAC analog circuitry
0DAC & input mux powered up
1DAC & input mux powered down
Power down ADC & input mux analog circuitry
0ADC & input mux powered up
1ADC & input mux powered down
0
Table 204. Mixer Power Down Control/Stat Register Description
BIT
PR0
PR1
PR2
FUNCTION
PCM in ADC’s and Input Mux Powerdown
PCM out DACs Powerdown
Analog Mixer Powerdown (Vref still on)
(Please see Figure 22)
Table 205. Power Down Register
19.3.3.5.
Codec/Mixer Test Register
The Codec/Mixer test register contains bits that control functionality that was
designed in the STMP3410 as options, and that are not expected to be used. The
programmer shouldn’t change the fields in this register without being directed to do
so by SigmaTel, as undesired operation may result. The organization of the
Codec/Mixer Test register is shown below.
HW_MIXTBR
BITS
LABEL
RW
RESET
23
22
21
20
DZCMA
DZCMI
DZCLI
DZCFM
RW
RW
RW
RW
0
0
0
0
19
18
DZCDA
EZD
RW
RW
0
0
X:$FA03
DEFINITION
Disable zero crossing volume update for master volume stage.
Disable zero crossing volume update for microphone volume stage.
Disable zero crossing volume update for line-in volume stage.
Disable zero crossing volume update for line-in 2 (also known as FM-in)
volume stage.
Disable zero crossing volume update for DAC volume stage.
Enable zero crossing detect in both channels of the mixer.
Table 206. Codec/Mixer Test Register Description
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BITS
LABEL
RW
RESET
16
PWDADC
RW
0
17,15
MICBIAS
RW
00
14
13
ADTHD
XBGC
RW
RW
0
0
12
11
10
9
8
7
6
5
4
3
2
XBCO
VCOS
FX2
PSRN
XBCLR
DCKI
PCPCD
PCPCU
ASD2X
ACKI
USBPDO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
1
0
USBFFB
USBCKN
RW
RW
0
0
DEFINITION
Power down ADC right channel. This powers down one ADC channel
when the ADC is being used to record only a mono channel. When set,
some power will be saved in the analog portion of the ADC. The ADC will
still generate stereo data, however only the samples for the left channel
will be valid.
Microphone resistor select. Provides an option for reducing board
complexity by integrating some bias circuitry for the microphone. This
circuit provides a regulated supply connected via a selectable resistor
value to the line-in right pin. This allows users to connect the microphone
to line-in right and then externally place a capacitor to the microphone
input to impelement the microphone function. This functionality cannot be
used at the same time that the line-in input is needed. See the
microphone volume register for a figure detailing the circuit. Note that the
regulated supply is generated from the aux channel of the low resolution
ADC, so the AUXPWD field of the HW_LRADCCR register must be
cleared as well to turn on the regulated supply circuit.
00 - Mic bias off
10 - 4kohm
01 - 2kohm
11 - 8kohm
Turn off ADC dither.
Causes the xtal oscillator to use the band gap bias current, instead of its
self-generated bias current.
Turns off xtal internal bias current.
Speed up PLL VCO.
Double frequency reference to the PLL.
Disable fast falling edge reset on PSWITCH pin.
Reduce xtal osciallator bias current
Invert DAC clock.
Decrease PLL charge pump current 2X.
Increase PLL charge pump current 2X.
Slow ADC dither.
Invert ADC clock.
Replace differential digital output of transceiver with positive digital
output. This function allows lower power consumption by recognizing the
fact that the positive receive data is identical to the differential data.
Bypass flip-flops in the USB transceiver.
Invert USB clock
Table 206. Codec/Mixer Test Register Description (Continued)
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19.3.3.6.
Reference Control Register
HW_REF_CTRL
BITS
LABEL
RW RESET
23:19 RSRVD
18
LWREF
17:16 BIASC
R
0
RW 0
RW 0
15
RW 0
PWRDWNS
14
ADJADC
13:10 ADCREFV
RW 0
RW 0
9
ADJV
RW 0
8:5
VAGVAL
RW 0
4
ADJDAC
RW 0
3:0
DACVBGVAL RW 0000
X:$FA19
DEFINITION
lower voltage in 13:10, 8:5, 3:0 by 20%
Bias current control.
00 - nominal
10 - -10%
01 - -20%
11 - +20%
These bits control the bias currents sent to all the analog circuits from the band
gap generator.
Powers down selfbias circuit. The reference uses a self bias circuit during
powerup that can be turned off with this bit. However, care must be taken that
the DC-DC converter must be using the bandgap-generated current before the
selfbias is powered down (bit [11] in $fa14).
Adjust adc reference using bits [13:10], default 1.5V derived from the bandgap
ADC reference value.
1111 - 1.600V
1001 - 1.450V
0100 - 1.325V
1110 - 1.575V
1000 - 1.425V
0011 - 1.300V
0111 - 1.400V
1101 - 1.550V
0010 - 1.275V
1100 - 1.525V
0110 - 1.375V
0001 - 1.250V
1011 - 1.500
0101 - 1.350V
0000 - 1.225V
1010 - 1.475V
These bits adjust the value of the reference used by the adc, and can be used
to allow acceptable analog performance at low supply voltages. Voltages
shown can be lowered 20% lower by setting bit 18.
Adjust Vag. Default is a resistor divider from the analog power supply. These
bits adjust the value of the analog reference used throughout the codec. This
value should be programmed to be near half of the analog target supply
voltage.
Vag Value.
1111 - 1.000V
1001 - 0.850V
0100 0.725V
1110 - 0.975V
1000 - 0.825V
0011 0.700V
1101 - 0.950V
0111 - 0.800V
0010 0.675V
1100 - 0.925V
0110 - 0.775V
0001 0.650V
1011 - 0.900V
0101 - 0.750V
0000 0.625V
1010 - 0.875V
Voltages shown can be lowered 20% lower by setting bit 18.
Adjust DAC reference value. Default is the band gap voltage. These bits adjust
the value of the reference used by the d/a converters, and can be used to allow
acceptable analog performance at low supply voltages.
dacvbgval <3:0>
1111 - 1.300V
1001 1.150V
0011 1.000V
1110 - 1.275V
1000 1.125V
0010 0.975V
1101 - 1.250V
0111 1.100V
0001 0.950V
1100 - 1.225V
0110 1.075V
0000 0.925V
1011 - 1.200V
0101 1.050V
1010 - 1.175V
0100 1.025V
Voltages shown can be lowered 20% lower by setting bit 18.
Table 207. Reference Control Register Description
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19.4. Headphone Driver
19.4.1.
Headphone Control Register
The organization of the Headphone Control Register is shown below.
HW_HPCTRL
X:$FA15
BITS
LABEL
23:11 RSRVD
10
HPHPWD
9
8
7
6
5
4
3
2
1
0
RW RESET
DEFINITION
R
0
Reserved. Must always read as 0.
RW 1
0 - Headphone amplifier powered up
1 - Headphome amplifier powered down (reset value)
HPHSHORT1
RW 0
hphshort1
HPHSHORT0
RW 0
hphshort0
short1 short0 result
0
0
short function held in reset
0
1
sw view latched short signal, hw pwd enabled
(recommended mode in application)
1
0
sw view latched short signal, hw pwd disabled
1
1
sw view direct short signal, hw pwd disabled
CLASSAB
RW 0
ClassAB (reset value 0 = ClassA mode). ClassA mode is intended only for
powerup antipop. ClassAB mode should be set before a signal is applied.
ClassAB mode should be used to drive both a low impedence (e.g.
headphone) or high impedance (e.g. line-in to another device) load.
POP2
RW 0
pop2
POP1
RW 0
pop1
POP0
RW 0
pop0
hphpwd classab pop2
pop1 pop0 "ramp result"
expected output pop
[bit 10]
[bit 7]
[bit 6] [bit 5] [bit 4]
0
0
0
0
0
1*84uA PMOS source current
1.3mV
0
0
0
0
1
1.3mV
0
0
0
1
0
1.3mV
0
0
1
1
1
1.3mV
1
x
0
0
0
11.0k pulldown resistor
1.3mV
1
x
0
0
1
depends on timing
1
x
0
1
0
depends on timing
1
x
0
1
1
depends on timing
1
x
1
0
0
depends on timing
1
x
1
0
1
depends on timing
1
x
1
1
0
depends on timing
1
x
1
1
1
depends on timing
TESTI1DWN
RW 0
test i1down
TESTI1UP
RW 0
test i1up
I1up
I1dn
Change to 1st stage current
0
0
nominal
0
1
-50%
1
0
+33.3%
1
1
-16.7%
TESTIALLUP
RW 0
test iall up
TESTIALLDWN RW 0
test iall down
Iallup
Ialldown Change to 1st stage current
0
0
nominal
0
1
-25%
1
0
+100%
1
1
+20%
Table 208. Headphone Control Register Description
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19.4.2.
Headphone Driver
Headphones
16 Ω
16 Ω
16 Ω
16 Ω
.01µF
.01µF
220 µF
220 µF
65
62
HPR
HPL
Figure 25. Headphone application circuit
19.5. Low Resolution ADC
The low resolution ADC (LRADC) block can do analog to digital conversion operations on two simultaneous channels. One channel is the battery channel which
measures the voltage on the BATT pin, and the other channel is auxillary channel
which measures the voltage on the LRADC pin. The battery channel can be used to
monitor the battery voltage to sense the amount of battery life remaining. The auxillary can be used for a variety of different uses, including a resistor based wired
remote control. The LRADC is accurate to 7 bits of resolution, and samples at 1/4 of
the analog DAC clock rate.
BANDGAP 2.8V
VDDIO
HW_LRADC_CTRL[23:22]
HW_LRADC_CTRL[12]
REF
[16]
BATT
[6:0]
IN
2
HW_LRADC_RES[6:0]
ADC OUT
PWD
HW_LRADC_CTRL[14]
[4]
+
(brownout level)
BANDGAP 2.8V
HW_LRADC_RES[7]
(brownout result)
VDDIO
HW_LRADC_CTRL[0]
REF
[6:0]
LRADC
IN
ADC OUT
HW_LRADC_RES[14:8]
PWD
HW_LRADC_CTRL[2]
Figure 26. Low Resolution ADC Diagram
The DAC analog clock must be turned on for the low resolution ADC to work. This
clock is controlled by the ACKEN bit of the Clock Control Register (HW_CCR
X:FA00).
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19.5.1.
Low Resolution ADC Control Register
HW_LRADC_CTRL
BITS
LABEL
23:22 BATREF
21:17 BATBRWN
16
IDIV2
15
14
BATHCONV
BATPWD
13
BATPWBR
12
BATADC
11:10 AUXREF
X:$FA17
RW RESET
DEFINITION
RW 00
Reference Adjust. These bits abjust the reference voltage used in the LRADC
battery channel.
00 - 2.800 V
10 - 2.700 V
01 - 2.900 V
11 - 2.780 V
RW 00000 Brownout tip point. These bits control the trip point for the LRADC battery
channel brownout detector. (see brownout Figure 38 for details)
00000 - 0.744 V
11010 - 1.160 V
01101 - 1.400 V
10000 - 0.787 V
00110 - 1.182 V
11101 - 1.444 V
01000 - 0.830 V
10110 - 1.204 V
00011 - 1.488 V
11000 - 0.873 V
01110 - 1.226 V
10011 - 1.532 V
00100 - 0.916 V
11110 - 1.248 V
01011 - 1.576 V
10100 - 0.959 V
00001 - 1.270 V
11011 - 1.620 V
01100 - 1.002 V
10001 - 1.292 V
00111 - 1.664 V
11100 - 1.045 V
01001 - 1.314 V
10111 - 1.708 V
00010 - 1.088 V
11001 - 1.336 V
01111 - 1.752 V
10010 - 1.116 V
00101 - 1.358 V
11111 - 1.796 V
01010 - 1.138 V
10101 - 1.380 V
Note: In order to enable battery brownout detection, BOEN bit 10 of the
HW_DCDC_VDDA register (shown on page 159) must be set.
RW 0
1Input = vbat/2
0Input = vbat
RW 0
Half converter power for the LRADC battery channel.
RW 1
Power down the LRADC battery channel.
1LRADC battery channel powered down
0LRADC battery channel powered up
RW 1
Power down brownout comparator. Power down the brownout circuit for the
LRADC battery channel.
1LRADC battery channel brownout circuit powered down
0LRADC battery channel brownout circuit powered up
RW 0
ADC reference is VddIO. Useful when input signals must be interpreted relative
to the VddIO (nominally 3.3 V) rail.
RW 00
Reference adjust. These bits adjust the reference voltage used in the LRADC
auxiliary channel.
00 - 2.800 V
10 - 2.700 V
01 - 2.900 V
11 - 2.780 V
R
0
Reserved
RW 0
Brownout Input.
1Brownout input = vbat/2
0Brownout input = vbat
9:5
4
RSRVD
BDIV2
3
2
AUXHCONV
AUXPWD
RW 0
RW 1
1
0
RSRVD
AUXADC
R
0
RW 0
Note: INPUT bit 16 shown above must be set for BRWNINPUT bit to be active.
Half converter power for the LRADC auxilliary channel.
Power down for the LRADC auxiliary channel.
1LRADC aux channel powered down
0LRADC aux channel powered up
Reserved
ADC reference is VddIO. Useful when input signals must be interpreted relative
to the VddIO (nominally 3.3 V) rail.
Table 209. Low Resolution ADC Control Register Description
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19.5.2.
Low Resolution ADC Result Register
HW_LRADC_RES
X:$FA18
BITS
LABEL
23:15 RSRVD
14:8 AUXLRR
7
6:0
RW RESET
DEFINITION
R
0
Reserved
R
N/A
Aux low resolution ADC result. This field gives the voltage measured on the
LRADC input pin
1111111 100.00% of the reference voltage (i.e. 100% * 127/127)
....... ...
BATLRBR R
0
Battery low resolution ADC brownout
BATLRR R
N/A
Battery low resolution ADC result. This field gives the voltage measured on the
BATT input pin
....... ...
Table 210. Low Resolution ADC Result Register Description
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20. BOOT MODES
20.1. General Information on Boot Modes
The STMP3410 on-chip ROM contains program code that is responsible for loading
code from outside the chip into on-chip RAM, and transferring control to that code.
The DSP determines which mode to use for booting by examining the signal level
on some pins. Table 211 shows the pins used for determining the boot mode. Three
pin numbers are listed for each pin, these are in order, the pin number in the 100-pin
TQFP package, the pin number in the 144-pin TQFP package, and the pin number
in the 144-pin fpBGA package.
PIN #
84/118/D1
83/116/D2
95/135/J1
94/133/H2
93/131/H4
92/129/H3
PIN LABEL
GP8
GP11
GP0
GP1
GP2
GP3
BOOT FUNCTION
Specifies boot mode
Reserved for future use
Enables POST operation
Specifies boot mode
Specifies boot mode
Specifies boot mode
Table 211. Boot Control Pins
These pins can and are used for other functions besides configuring the boot mode;
this is achieved by specifying the high or low state on these pins with a high value
resistor (typically 47k ) pulling the pin either up to VddIO or down to VssIO. During
boot mode, these pins are not driven by the STMP3410, and the pull-up/down resistors will specify the value. One boot mode pin is reserved for future use, this pin has
no effect on the boot process, but should be pulled to 1 if possible to maximize
future compatibility. Table 212 shows the different boot modes supported.
GP3
1
1
1
1
1
GP2
0
0
0
0
0
GP1
0
0
0
0
1
GP0
0
1
0
1
0
GP11
X
X
X
X
X
GP8
0
0
1
1
0
1
0
1
1
X
0
1
0
1
0
X
1
1
0
1
1
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
0
0
1
1
0
0
1
BOOT MODE
USB
USB
I2C slave
I2C slave
NAND with Play
recovery
NAND with Play
recovery
NAND with PSWITCH
recovery
NAND with PSWITCH
recovery
I2C master
I2C master
SPI slave
SPI slave
TESTERLOADER
TESTERLOADER
BURNIN
POST
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
N/A
Table 212. Boot Modes in Current Silicon Revision
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POST is the Power On Self Test. This function runs a self-test and repair function on
the on-chip RAMs and swaps in spare bits where necessary/possible to repair any
defects found. Note that STMP3410 parts shipped by SigmaTel are guaranteed to
have no un-repaired defects in the on-chip RAMs, this means that the POST MUST
be run as part of the boot process for correct operation of the chip. The POST process takes about 40msec to complete, and is designed to consume as little power
as possible. The POST process does not stop on errors, and does not give any indication as to success or failure; the application loaded by the boot loader should
assume that the on-chip RAM has been repaired correctly. The POST operation will
overwrite any data stored in on-chip RAM, so any data in on-chip RAM will lost during the STMP3410 boot process.
The USB, I2C master & slave, NAND Flash and SPI slave boot modes are intended
to be used in applications of the STMP3410; in other words, they are user boot
modes. The TESTERLOADER & BURNIN boot modes are for internal SigmaTel use
only. In a future version of the STMP3410 boot ROM, the POST process will be
compulsory, and the GP0 pin will become available to specify future additional boot
modes. Any changes to the above boot mode table will preserve all of the entries for
user boot modes to preserve compatibility for existing designs.
During reset, and while the POST process is running, all digital pins on the
STMP3410 are in tri-state mode. Once an individual boot mode starts, the boot
mode will enable and configure the pins required for that boot mode. It is the
responsibility of the application loaded by the boot ROM to enable & configure all of
the pins it requires, the application should do this without making any assumptions
about how the pins were configured by the boot ROM.
There is one additional implicit boot mode, over and above the boot modes listed in
the above table, that is OnCE (On Chip Emulation) boot mode. This boot mode
occurs when the external debug hardware pulls the ONCE_DRN pin low during the
boot process to trigger the on-chip debugger. When this happens the DSP will execute the first few instructions in the on-chip ROM before stopping and allowing the
external debugger to take control. In this circumstance, the actual boot mode
selected on the boot pins will have no effect. OnCE boot mode will only be used by
developers, however PCB boards designed for the STMP3410 should support the
OnCE boot mode wherever possible, to enable system debug.
20.2. Bootloader Code Format
For the user boot modes, the boot loader expects the code read from the external
storage to be organized in a specific format. This format is able to load blocks of
data into X, Y, P, or L memory. It is also capable of initializing a block of memory to a
specified value. Loading a block of code or data into memory is achieved by first
sending a two-word command header, followed by the data. The command header
is shown in Table 213.
WORD 0
WORD 1
WORD 2-N
BITS 23-20
Mc[3:0]
BITS 19-16
0000
00000000
Data[23:0]
BITS [15:0]
Address[15:0]
Length[15:0]
Table 213. Command Header + Data
For Word 0, the Memory Control bits, Mc[3:0], are used to specify the target memory
space for the code that is being loaded, and whether this is a block memory load, or
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an initialization of a range of addresses to one value. Table 214 specifies the meaning of these bits in more detail.
MC3
MC2 (P)
MC1 (X)
MC0 (Y)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DESCRIPTION
Unused
Load into Y Memory
Load into X Memory
Load into L memory (XY memory)
Load into P memory
Unused
Unused
Unused
Unused
Init Y memory with data value
Init X memory with data value
Init L memory with data value
Init P memory with data value
Unused
Unused
Boot load complete, exit and jump to P:$0.
Must be a complete Command Header
($F00000 $000000).
Table 214. Memory Control Bits
The Address[15:0] field specifies the base address in memory where data is to be
written. The Length[15:0] specifies the length of the block of data in memory to be
loaded or initialized. When loading into P, X or Y memory, Words 2 through N will
contain one word of data for each P, X, or Y memory location to be loaded. When
loading into L memory, Words 2 through N will contain two words of data for each L
memory location to be loaded, words 2, 4, etc, will go into X memory, words 3, 5,
etc, will go into Y memory. When initializing P, X, or Y memory, Word 2 will specify
the value to be used in initializing memory. When initializing L memory, Words 2
through 3 will specify the value to be used in initializing memory.
This data structure allows the initialization of STMP3410 hardware control registers
as part of the boot process, this could be achieved by using the above data structure
to write directly to a memory mapped hardware register. Most frequently, this is
used to write to the HW_PXCFG & HW_PYCFG registers that control the configuration of on-chip RAM.
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20.3. Encryption
The STMP3410 expects the code to be loaded by the boot loader to be encrypted.
This encryption serves two purposes; it makes it harder for an end user to hack the
device, and it includes a check-sum to prevent corrupted code from being used to
boot the device. The boot loader will fall back to USB boot mode if the code being
loaded fails the check-sum test, this allows a player with corrupted code to be recovered by an end user with the use of a recovery program on their PC.
The details of the encryption algorithm are not covered in this document; please
contact SigmaTel for more information if needed. The SigmaTel STMP3410 SDK
(Software Development Kit) includes everything needed to encrypt code that is to be
loaded into the STMP3410.
20.4. Bootloader Examples
This section provides a few examples of data delivered to the DSP and how it will be
copied into memory. Note that these examples show the data before it is encrypted
using the encryption mentioned above.
20.4.1.
Boot Example #1
The following example of data presented to the DSP would result in 8 words being
loaded into Y memory.
$100210
$000008
$000000
$111111
$222222
$333333
$444444
$555555
$666666
$777777
$F00000
$000000
20.4.2.
; load into Y memory starting at Y:$0210
; load 8 words of data into Y memory
; data word #0, written to Y:$0210
; end of boot, execute program
; this word IS required
Boot Example #2
The following example of data presented to the DSP would result in 8 contiguous P
memory locations being initialized to a specified value.
$C00400
$000008
$CCCCCC
$F00000
$000000
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; initialize P memory starting at P:$0400
; initialize 8 locations, i.e. P:$0400..$0407
; initialize with the value $CCCCCC
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20.4.3.
Boot Example #3
The following example of data presented to the DSP would result in 11 contiguous L
memory (XY memory) locations being initialized to specified values.
$300230
$00000B
$000001
$000002
$000004
$000008
$000010
$000020
$000040
$000080
$000100
$000200
$000400
$000800
$001000
$002000
$004000
$008000
$010000
$020000
$040000
$080000
$100000
$200000
$F00000
$000000
; load L memory at address L:$0230
; load 11 L words
; data word #0 upper, loaded to X:$0230
; data word #0 lower, loaded to Y:$0230
; data word #10 upper, loaded to X:$023A
; data word #10 lower, loaded to Y:$023A
20.5. Boot Procedure
The flow chart in Figure 27 shows the initial boot sequence and Figure 28 shows the
subsequent general boot procedure.
20.5.1.
USB boot mode
The USB boot mode enables the USB interface, attempts to enumerate on the USB
bus, and then expects USB Bulk-Out data from the host PC containing the data to
be use for booting. This boot mode is intended to be used at the end of the production line for EOL (end of line) tests, and for personalizing the players. Together with
a recovery application running on a PC, this mode may also be used by an end user
to recover if the code on a player somehow becomes corrupted.
One issue with using the USB Boot Class MODE is that the STMP3410 device ROM
does not have a unique ID and therefore multiple devices built using the STMP3410
may not be connected simultaneously to a single computer. To get around this limitation all software implementations provided by SigmaTel will populate the STMP
Boot component with a Boot Manager program. The Boot Manager is used to
decide whether to load code for a player or for USB. The Boot Manager will check to
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Power Up
p:$0 = jmp p:BootLoader
BootLoader Entry
Enable OnCE
Init Variables
Power up
BootMode GPIO
Pins
Enable, Sense, &
Disable BootMode
GPIO pins
BURNIN Mode?
Y
jmp BURNIN
Y
jmp
TESTERLOADER
N
Run POST
Y
POST Enabled?
N
TESTERLOADER
mode?
N
Execute BootMode
Figure 27. Initial Boot Sequence
see if USB is connected and if so it will load the DCC Image, and if not it will load the
Player Image. The DCC Image will be specific to a given product hence it may have
unique USB IDs and allow multiple devices to co-exist on a computer. In this manner the generic USB Boot Class is completely by-passed. Please refer to the
STMP34xx Boot Manager document for more details.
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Continue Boot
Each BootMode is
responsible for powering
all required pads
BootMode ==
NAND Flash?
N
BootMode ==
USB?
The UsbInit Routine will wait
up to 5 minutes for USB to
be connected.
BootMode = USB
N
USB
Connected?
Y
N
N
Play/PSWITCH
Button
Pressed > 5s ?
Y
Y
BootMode = USB
Generic BootClass
N
Copy ROM to
RAM
Y
N
Set OMR[0] == 0
Run BootMode Init
Routine
jmp p:RunInit
Got
CipherKey?
Y
N
Got CheckSum
Target?
N
Y
Version Okay?
N
N
Get Command
All pads powered for a
given BootMode will
remain powered
Valid
Command?
N
Y
Run BootMode
Exit Routine
y
CheckSum
Okay?
Reboot?
Y
N
jmp p:$0
Execute
Command
Okay?
Figure 28. Boot Procedure
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20.5.1.1.
USB Boot Mode Pin Power
USB Boot Mode pins are analog pins and are powered at system startup up. No
other digital pins are powered for this boot mode.
Note: See Table 236 for USB Interface pin placement.
20.5.2.
NAND Flash Boot Mode
The NAND Flash boot mode will read boot commands from NAND Flash or SmartMedia flash devices. The BootMode Init routine will search up to four NAND/SmartMedia devices and boot from the first device/card that is found with valid boot code.
The NAND Flash boot mode searches for and boots from the STMP Boot component. Please refer to the STMP3XXX SmartMedia Blocks document for more details
on components. The search will start with chip select 0 and move on to 1, 2, and 3.
If an error is encountered then the device on the next chip select is searched. If
desired, the entire code set may reside in the STMP Boot component and the Boot
Manager and other components may be left out of the system.
If all NAND/SmartMedia devices are searched and no valid boot code is found the
boot mode is changed to USB, and the part attempts to boot from the USB bus. This
situation will most commonly be encountered at the end of a production line where
the devices being manufactured will not contain any code. This situation will also be
encountered if the code on the NAND/SmartMedia device becomes corrupted for
some reason, the end user will be able to reload the code onto the device by using a
recovery program on a PC.
Finally, the end user can manually force a boot from USB by holding down the Play
button (NAND Flash boot mode with play recovery), or power button (NAND Flash
boot mode with PSWITCH recovery) for 5 seconds during the boot process. See
Figure 28, Boot Procedures, for details.
20.5.2.1.
NAND Flash Boot Mode Pin Power
The NAND Flash boot mode will power the following pins:
SM_D0
SM_ALE
SM_D1
SM_CLE
SM_D2
SM_SEn
SM_D3
SM_CE0n
SM_D4
SM_CE1n
SM_D5
SM_CE2n
SM_D6
SM_CE3n
SM_D7
SM_WPn
SM_REn
SM_READY
SM_WEn
Note: See Table 228 for SmartMedia pin placement.
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20.5.3.
I2C Slave Boot Mode
The I2C slave boot mode enables the I2C port as a slave device, and waits for data
to be written to the I2C port using the bootloader code format documented above.
20.5.3.1.
I2C Slave Boot Mode Pin Power
The I2C Slave boot mode will power the following pins:
I2C_SCL
I2C_SDA
Note: See Table 230 for I2C Interface pin placement.
20.5.4.
I2C Master Boot Mode
The I2C master boot mode enables the I2C port as a master device, and then
attempts to read data formatted using the bootloader code format documented
above from an external I2C device at I2C address $A0.
20.5.4.1.
I2C Master Boot Mode Pin Power
The I2C Master boot mode will power the following pins:
I2C_SCL
I2C_SDA
20.5.5.
SPI Slave Boot Mode
The SPI slave boot mode enables the SPI port as a slave device, and waits for data
to be written to the SPI port using the bootloader code format documented above.
20.5.5.1.
SPI Slave Boot Mode Pin Power
The SPI Slave boot mode will power the following pins:
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SSn
20.5.6.
TESTERLOADER Boot Mode
This boot mode provides a simple, fast interface to testers for loading test code.
This mode is intended for internal SigmaTel use only, and no further documentation
is provided here.
20.5.7.
BURNIN Boot Mode
This boot mode provides a simple way to exercise large portions of the STMP3410
on-chip hardware. Note that the power consumed by the STMP3410 will be significantly higher than normal when the part is operating in BURNIN mode. This boot
mode is intended for internal SigmaTel use, and no further documentation is provided here.
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20.5.8.
System Recovery Mode
This is not an explicit boot mode but is entered in a special case of the two NAND
modes. If the STMP3410 has power turned on with MODE = NAND with play recovery and USB is connected, and the Play button is held for 5 seconds the player will
automatically go to the USB MODE. This will cause the device to show up as a USB
Boot Class device. If a host driver detects this device it may take action to reformat
the SmartMedia. Please refer to Figure 28.
20.6. Memory Maps
Various memory maps are employed in the different boot modes. Figure 29 shows
the memory map for the USB boot modes and Figure 30 shows the map for all other
modes. Shaded areas are available for loading code.
$9FFF
$9FFF
$4FFF
$4FFF
$4FFF
$4FFF
$2000
$1FFF
USB
Boot
Code
$0000
$01FF
$0000
$0200
$1FFF
$0200
Boot
Params
$01FF
Boot
ROM
$0000
$0000
Boot
Params
$0000
$0000
PRAM
XRAM
YRAM
Figure 29. USB Boot Mode Memory Map
PRAM
XRAM
YRAM
Figure 30. All Other Boot Modes Memory Map
In USB Boot Class p:$0..1 are available for writing the Reboot vector. All other
interrupt vectors must be created by code at run-time.
Although the interrupt vector table is available (p:$0000..p:$007F) it is required that
all vectors must be created by code at run-time.
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21. DC-DC CONVERTER
The STMP3410 has 2 programmable integrated DC-DC converters that can be
used to provide power for the device as well as the entire application. The converters can be configured to operate from standard battery chemistries in the range of
0.9-3.6 volts including alkaline cells, NiMH, LiIon etc. If multiple batteries are used, a
series configuration is strongly preferred to optimize efficiency and battery life. Also,
for applications that do not need integrated power management, the converters can
be disabled and external supplies provided.
Board layout and external inductor/capacitor quality are critical to maximize analog performance and as well as DC-DC converter efficiency. Users should read and understand SigmaTel’s printed circuit board layout application notes for guidance before
beginning PCB layout. Further, users should refer to SigmaTel’s reference designs for
assistance in selecting the inductor and large external decoupling capacitors.
21.1. STMP3410 DC-DC Converter Implementation
21.1.1.
Defining Battery Configuration
The outputs of both DC-DC converters are isolated from the power rails of the chip.
Therefore, the connection between the DC-DC converter outputs and the voltage rails
of the chip must be done on the PCB. However, the specific PCB connections and
battery connections are unique to each battery configuration as described below.
The battery configuration of the player is determined by the three mode pins
DCDC_mod2, DCDC_mod1, DCDC_mod0. These pins each have an internal
100 kΩ pullup resistor to the BATT pin (the battery must always be connected to the
BATT pin for the device to power up), so each mode pin is default high. Low value
resistors should be added on the board to pull the desired mode pin low. Note that
the configuration of these pins cannot be changed dynamically. In 100 pin configurations, only DCDC_mod2 is available on a pin, therefore only modes 111 and 011 can
be used in this configuration. Also, the pins of DCDC Converter #2 are not available
in a 100 pin configuration.
The selection of the three DC-DC mode pins determines whether each of the two
DC-DC converters is operating in buck mode, boost mode, or is powered off. As the
following table shows, each converter operates in boost mode when it’s output voltages > battery voltage, and in buck mode when output voltage < battery voltage.
Table 215 details the decode of the three DC-DC mode select pins:
DCDC_MODE2:0 POWER SOURCE DCDC CONVERTER #1 DCDC CONVERTER #2
111
1 Alkaline or 1 NiMH
2-channel boost
off
(0.9V-1.5V)
(1.8/3.3 V)
110*
reserved
reserved
reserved
101*
1 Alkaline or 1 NiMH
3-channel boost
off
(0.9V-1.5V)
(1.8/1.8/3.3 V)
100*
reserved
reserved
reserved
011
LiIon, (3.0-3.6V)
1- channel buck (1.8 V)
off
010*
External supplies
off
off
001*
2 Alkaline or 2 NiMH 1-channel buck (1.8 V) 1-channel boost (3.3 V)
(1.8V-3.0V)
000*
LiIon
1-channel buck (1.8 V) 1-channel buck (3.3 V)
(3.3V-3.6V)
* Only available in 144-pin package
Table 215. Decode of the Three DC-DC Mode Select Pins
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As Table 215 shows, DC-DC converter #2 is only used to generate the 3.3 V rail
when higher voltage battery configurations are selected. Additionally, DC-DC converter #2 has a lower resistance PMOS FET that can perform well in high current
applications such as rotating media.
21.1.1.1.
DC-DC Converter Configuration
The two integrated DC-DC converters provide several low resistance FETs for use
in power conversion as shown in the following Figure 31:
VddIO
1/2/3*/4*
VddD
1/2/3/4
VddA
1/2/3/4
DCDC_VddD
DCDC_VddA*
DCDC_VddIO
battery
Low
Resolution
ADC
BATT
DC-DC
#1 Control System
DCDC_Batt
DCDC_Gnd
Regulator
DSP_RESET
VddXTAL
DCDC2_Vout*
RTC
DC-DC
#2 Control System
XTAL
OSC
DCDC2_Batt*
Vbg
PSWITCH
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
DCDC2_Gnd*
* only available on 144-pin packages
Figure 31. DC-DC Converter Control System
The configuration of the three DC-DC mode pins described in the previous section
determines how these two groups of FETs are switched to provide the desired output voltage values. The FETs can be switched to either create a buck mode converter (battery >= output voltage) or boost mode converter (battery <= output
voltage). These two different operating modes require different connectivity between
the battery and inductor on the PCB. The various arrangements are shown in Figures 32 to 37.
21.1.1.2.
Power Up Sequence
The DC-DC converters control the power up sequence of the device and hold the
rest of the chip in reset until after the power up sequence is complete. This is necessary to prevent operation of the DSP and system before stable power supply voltages are present.
The Power Up sequence begins when the battery is connected to the BATT pin of
the device. As shown in Figure 31, the BATT pin provides the pullup on the three
DC-DC mode select pins, as well as supplies power to the crystal oscillator and the
real-time clock. This means that the crystal oscillator will be running whenever the
battery is connected to BATT pin. This feature is necessary to allow the real time
clock to operate when the player is in the off state. The crystal oscillator/RTC is the
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NC
battery
VddA
NC
DCDC_VddD
1/2/3/4
DCDC_VddA*
DCDC_VddIO
VddD
1/2/3/4
VddIO
1/2/3*/4*
battery
BATT
Low
Resolution
ADC
DC-DC
#1 Control System
VddD
DCDC_Batt
DCDC_Gnd
Regulator
VddXTAL =
BATT/2
battery
VddXTAL
RTC
DC-DC
#2 Control System
DCDC2_Vout*
VddIO
DCDC2_Batt*
DCDC2_Gnd*
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
XTAL
OSC
VddIO
1/2/3*/4*
Figure 32. DC-DC Converter Control System (Mode 000)
144 Pin only
DCDC1
1 channel buck
DCDC2
1 channel buck
VddD
1/2/3/4
NC
battery
VddA
NC
DCDC_VddD
1/2/3/4
DCDC_VddA*
DCDC_VddIO
battery
BATT
Low
Resolution
ADC
DC-DC
#1 Control System
VddD
DCDC_Batt
DCDC_Gnd
Regulator
VddXTAL =
BATT/2
VddXTAL
DCDC2_Vout*
RTC
DC-DC
#2 Control System
XTAL
OSC
battery
DCDC2_Batt*
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
DCDC2_Gnd*
NC
144 Pin only
DCDC1
1 channel buck
DCDC2
1 channel boost
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Low
Resolution
ADC
BATT
NC
NC
NC
DCDC_VddD
DCDC_VddA*
DCDC_VddIO
driven externally
VddD
VddA
1/2/3/4
1/2/3/4
VddIO
1/2/3*/4*
NC
DCDC_Batt
DC-DC
#1 Control System
DCDC_Gnd
Regulator
VddXTAL =
BATT/2
VddXTAL
NC
DCDC2_Vout*
RTC
NC
DCDC2_Batt*
DC-DC
#2 Control System
XTAL
OSC
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
DCDC2_Gnd*
NC
144 Pin only
DCDC1
Off
DCDC2
Off
linear regulator or
converter**
VddD
1/2/3/4
VddIO
1/2/3*/4*
linear regulator or
converter**
Low
Resolution
ADC
BATT
VddA
1/2/3/4
DCDC_VddIO
DC-DC
#1 Control System
NC
NC
DCDC_VddD
DCDC_VddA*
VddD
DCDC_Batt
DCDC_Gnd
Regulator
VddXTAL =
BATT/2
VddXTAL
NC
DCDC2_Vout*
RTC
DC-DC
#2 Control System
NC
DCDC2_Batt*
XTAL
OSC
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
DCDC2_Gnd*
NC
** VddIO is powered using a linear regulator or converter. This same
power source is connected to the BATT and DCDC_Batt pins. The
primary application for this mode is 100 pin devices that use series
batteries or high voltage batteries such as LiIon.
NC
100 Pin
DCDC1
1 channel buck
or 144 Pin
DCDC2
Off
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VddD
VddA
1/2/3/4 1/2/3/4
VddIO
1/2/3*/4*
battery
BATT
DCDC_VddIO DCDC_VddD DCDC_VddA*
battery
Low
Resolution
ADC
DC-DC
#1 Control System
DCDC_Batt
DCDC_Gnd
Regulator
VddXTAL=BATT
VddXTAL
NC
DCDC2_Vout*
RTC
NC
DCDC2_Batt*
DC-DC
#2 Control System
XTAL
OSC
DCDC_mod0*
DCDC_mod2
DCDC_mod1*
DCDC2_Gnd*
NC
NC
144 Pin only
DCDC1
3 channel boost
DCDC2
Off
VddD
1/2/3/4
VddIO
1/2/3*/4*
VddA
1/2/3/4
DCDC_VddIO DCDC_VddD
battery
BATT
Low
Resolution
ADC
NC
DCDC_VddA*
battery
DC-DC
#1 Control System
DCDC_Batt
DCDC_Gnd
Regulator
VddXTAL=BATT
VddXTAL
NC
DCDC2_Vout*
RTC
DC-DC
#2 Control System
XTAL
OSC
DCDC_mod0*
DCDC_mod1*
DCDC_mod2
DCDC2_Gnd*
NC
NC
NC
152
NC
DCDC2_Batt*
100 Pin
DCDC1
2 channel boost
or 144 Pin
DCDC2
Off
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only power drain on the battery in this state and consumes only a very small amount
of power. During this time, the digital (VddD) and analog (VddA) supplies are held at
ground, while the VddIO rail is shorted to the battery. This is the off state that continues until the PSWITCH pin is asserted high. The voltage value is .9V and it has to
stay high for 100ms.
When the PSWITCH pin is asserted, the DC-DC converters are enabled and the
device attempts to power up. Depending on the DC-DC mode select pins, one or
both of the DC-DC converters begin switching and drive the voltage outputs toward
the target values. When both of the converters control systems sense that the voltage rails have reached their default target values, the DSP reset is de-asserted and
the DSP begins executing code. If the power supplies do not reach the target values
by the time PSWITCH is de-asserted, then the player returns to the off state.
The startup time for the DC-DC converters are dependent on battery voltage, but
should be less than 100 msec.
21.1.1.3.
Power Down Sequence
Power Down is also controlled by the DC-DC converters. When the DC-DC converters detect a power down event, they return the player to the off state described
above that shorts the battery to the VddIO rail and holds the internal VddD and
VddA supplies at ground. A Power Down event is triggered by writing a 1 to the
Clock Control Register PWDN bit (HW_CCR, bit [17]). A Power Down event can
also be triggered by a fast falling edge on the PSWITCH pin. The Power Down via
PSWITCH is an edge sensitive event and requires < 15ns falling edge to cause a
Power Down to be detected. An external capacitor on PSWITCH can be used to
prevent unwanted Power Down events in the final application, but this fast falling
edge Power Down mechanism can also be disabled by writing a 1 to the
Coded/Mixer Test Register PSRN field (HW_CMTR, bit [9]).
21.1.1.4.
Powered Down State
While the STMP3410 is powered down, the VddA & VddD rails are shorted to
ground, and the VddIO rail is shorted to the battery, the crystal oscillator and the
RTC continue to operate by drawing power from the BATT pin. The functions are
implemented differently in each of the DCDC configurations.
For the DCDC boost modes (modes 101, & 111), the DCDC_VddD & DCDC_VddA
pins are shorted to digital ground, which will short the VddA & VddD rails to ground.
For the DCDC buck modes (modes 000, 001 & 011) the DCDC_Batt pin is shorted
to digital ground, which will also short the VddA & VddD rails to ground. For the
DCDC external supply mode (mode 010), the DCDC_Batt pin is also shorted to digital ground, but since this pin is not connected, it will have no effect on the VddA &
VddD rails.
For the DCDC boost modes (modes 101, & 111), the DCDC_VddIO & DCDC_Batt
pins are shorted to each other, which will short the VddIO rail to the battery voltage.
For the DCDC buck modes (modes 000, 001 & 011) the DCDC2_Batt and
DCDC2_Vout pins are shorted to each other, which will also short the VddIO rail to
the battery. For the DCDC external supply mode (mode 010), the DCDC2_Batt and
DCDC2_Vout pins are also shorted to each other, but since these pins are not connected, it will have no effect on the VddIO rail.
For the DCDC boost modes (modes 101, & 111), the crystal oscillator and RTC take
their power from the BATT pin, which is decoupled by a capacitor on the VddXTAL
pin. For the DCDC buck modes (modes 000, 001 & 011) the crystal oscillator and
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RTC take their power from the BATT pin via a regulator which restricts the voltage to
50% of the battery voltage, which is decoupled by a capacitor on the VddXTAL pin.
For the DCDC external supply mode (mode 010), the crystal oscillator and RTC also
take their power from the BATT pin via a regulator which restricts the voltage to 50%
of the battery voltage, which is decoupled by a capacitor on the VddXTAL pin.
21.1.1.5.
Reset Sequence
A reset event can be triggered by writing the binary value 1101 to the Reset Control
Register SRST field (HW_RCR, bits [7:4]). This reset only affects the digital logic,
although the digital logic also includes all of the registers that control the analog portions of the chip. The DCDC converters continue to maintain the power supply rails
during the reset, although the target voltages for the DCDC converters may change
once the digital registers go to their reset values.
21.1.1.6.
Summary of Major DC-DC Features
The unique architecture of the integrated DC-DC converters on the device allows
access for many control features via registers. Some of the most commonly used
features are described below:
1. Digital adjustment of the voltage rails: The target values of the voltage rails can
be adjusted during operation to optimize power consumption and extend battery
life. SigmaTel to provide a suggested clock speed vs. voltage curve to allow for
the optimum settings to be chosen.
Note: An most DC-DC operating modes (except mode 101) the analog supply is
shorted to the digital supply. In these cases analog performance may suffer if
the supply voltage is reduced below 1.7 volts or so. If the supply voltage is
affecting analog performance, alternate settings for the analog reference voltage and bandgap voltage may provide relief. The control for the analog reference voltages resides in the Reference Control Register (HW_REF_CTRL).
2. Power supply brownout detection: Analog comparators in the DC-DC converters provide immediate input to the DSP via an IRQB or NMI interrupt (controlled
by the HW_RCR Reset Control Register) if the supplies drop below the brownout level specified in the HW_DCDC_VDDD/HW_DCDC_VDDIO Control Registers (X:$FA0E, X:$FA20). This feature is generally used to alert the DSP when
the power supplies are reaching dangerously low levels and allow a controlled
system shutdown. These comparators may trip on brief transients below the target brownout voltage, so enough margin between the output voltage target and
the brownout voltage target must be provided to eliminate false triggers. The
magnitude of the difference between the output voltage target and brownout
voltage target will depend on system power requirements and board layout,
should typically be set to between 100 mV and 200 mV.
3. Battery brownout detection. Another comparator is present outside of the DCDC converters to provide battery brownout information to the DSP via the
Reset/Interrupt Control Register (HW_RCR X:$FA01). This feature is intended
to provide indication to the DSP of a low battery voltage that requires a controlled system shutdown due to an event such as the battery falling out during
application operation. The programming of the battery brownout level is via the
Low Resolution ADC Control Register (HW_LRADC_CTRL X:$FA17).
4. DC-DC clock rate. The DC-DC converter clock rate can be lowered by 2x, 4x, or
8x from the default 6.144 MHz value. The clock rate can be lowered to reduce
power consumption in the DC-DC converter if the corresponding increase in
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supply transients can be tolerated in the application. See bit 4, 5 in DC-DC Test
Bit Register (HW_DCDCTBR X:$FA14).
5. Linear Regulator generates analog/digital supply. Another low-power option is
provided by replacing the DC-DC converter #1 with a linear regulator to generate the 1.8 V supply during very low current modes (<5 mA). Enabling this regulator is described in the DCDC1 Control Register (HW_DCDC1_CTRL0). It is
possible to switch back and forth between the linear regulator and switching
DC-DC converter.
21.1.2.
DC-DC Registers
The DC-DC control registers are used to control DC-DC low-level functionality. It is
ill-advised to change these registers from their defaults unless SigmaTel indicates
otherwise.
21.1.2.1.
DCDC1 Control Register A
The organization of the DCDC1 Control Register A is shown below.
HW_DCDC1_CTRL0 X:$FA0C
BITS LABEL RW RESET
DEFINITION
23:22 RSRVD R
0
21:17 NLVL
RW 00011
16:12 PLVU
11:7
PLVD
6:0
R
Negative Digital Loop Clip Level. This value represents the negative value at which
the digital loop filter clips to prevent illegal values. These five bits represent bits 18:14
of the 20-bit loop filter value. Bit 19 of the negative clip value are set to binary 1, while
13:0 are high. Altering the clip value should be done with caution since it may cause
the sigma delta output to be non-monotonic. Default decodes to -458753.
RW 01110
Positive Digital Loop Clip Level in Boost mode. This value represents the positive
value at which the digital loop filter clips to prevent illegal values while operating in
boost converter mode. These five bits represent bits 18:14 of the 20-bit loop filter
value. Bit 19 of the positive clip are set to binary 0, while 13:0 are low. The optimum
value of this register depends on the battery voltage and acts effectively to limit the
battery current when the load exceeds the capabilities of the converter. Default
decodes to 229376.
RW 11100
Positive Digital Loop Clip Level in Buck mode. This value represents the positive
buck converter mode. These five bits represent bits 18:14 of the 20-bit loop filter
decodes to 458752.
RW 0010000 Resistor Value. This value represents the R value of the “resistor” in the digital loop
filter in the common mode control loop in the DC-DC converter. The reset value of
decimal 4096 is chosen in conjunction with the value for bits [21:15], the actual
decoupling capacitor, and the clock rate to provide a stable control system. The
value will rarely be altered, but conditions may arise in the actual application for
which a different value is more optimum. Values range 256 to 32767 (Only bits 14:8
are shown here, others bits are always 0). Values for NLVL, R, PLVU, and PLVD
must satisfy the following restrictions:
NLVL – 4R ≥ – 475137
PLVU + 4R ≤ 475136
PLVD + 4R ≤ 475136
Table 216. DCDC1 Control Register A Description
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21.1.2.2.
DCDC1 Control Register B
The organization of the DCDC1 Control Register B is shown below.
HW_DCDC1_CTRL1 X:$FA0D
BITS LABEL RW RESET
23:16 RSRVD R
15:10 DCYC R
9:7
FFOR
6:0
C
DEFINITION
0
Duty Cycle. 2’s complement number representing duty cycle of charging/discharging
the inductor. A large positive number indicates the energy needed by the system is
close to the limit the battery can provide, while a negative number means the battery
is easily supplying the power needed by the system.
100000 - DC-DC duty cycle at minimum (small charge time/large discharge
time)
......
011111 - DC-DC duty cycle at maximum (large charge time/ small discharge
time)
This value will be limited according to the NLVL and PLVD/PLVU values set for this
DC-DC Converter. This value can be used to estimate the amount of life left in the
battery at the current rate of consumption.
RW 000
Feed Forward to loop filter value. This two’s complement value steps the loop filter
value by the amount DDD once on a 000->DDD transition. Thus, this value must be
rewritten to 000 everytime before use. The feed forward featue is used to help the
control loop react under heavy, but well-known, transient loads.
RW 0100000 Capacitor 1/C Value. This value represents 1/C value of the “capacitor” in the digital
loop filter in the common mode control loop in the DC-DC converter. The reset value
of decimal 32 is chosen in conjunction with the value for the R field in the DCDC1
Control Register A (HW_DCDC1_CTRL0 X:$FA0C), the actual external decoupling
capacitor, and the clock rate to provide a stable control system. This value will rarely
be altered, but conditions may arise in the actual application for which a different
value is more optimum. Values can range between 0 and 127.
Table 217. DCDC1 Control Register B Description
21.1.2.3.
DCDC2 Control Register A
The organization of the DCDC2 Control Register A is shown below.
HW_DCDC2_CTRL0 X:$FA11
BITS LABEL RW RESET
23:22 RSRVD R
0
21:17 NLVL
RW 00011
16:12 PLVU
RW 01110
DEFINITION
Negative Digital Loop Clip Level. This value represents the negative value at which
the digital loop filter clips to prevent illegal values. These five bits represent bits 18:14
of the 20-bit loop filter value. Bit 19 of the negative clip value is set to binary 1, while
bits 13:0 are high. Altering the clip value should be done with caution since it may
cause the sigma delta output to be non-monotonic. Default decodes to -458753.
Positive Digital Loop Clip Level in Boost mode. This value represents the positive
boost converter mode. These five bits represent bits 18:14 of the 20-bit loop filter
decodes to 229376.
Table 218. DCDC2 Control Register A Description
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BITS LABEL RW RESET
11:7
PLVD
6:0
R
DEFINITION
RW 11100
Positive Digital Loop Clip Level in Buck mode. This value represents the positive
buck converter mode. These five bits represent bits 18:14 of the 20-bit loop filter
decodes to 458752.
RW 0010000 Resistor Value. This value represents the R value of the “resistor” in the digital loop
filter in the common mode control loop in the DC-DC converter. The reset value of
decimal 4096 is chosen in conjunction with the value for bits [21:15], the actual
decoupling capacitor, and the clock rate to provide a stable control system. The
value will rarely be altered, but conditions may arise in the actual application for
which a different value is more optimum. Values range 256 to 32767 (Only bits 14:8
are shown here, others bits are always 0). Values for NLVL, R, PLVU, and PLVD
must satisfy the following restrictions:
NLVL – 4R ≥ – 475137
PLVU + 4R ≤ 475136
PLVD + 4R ≤ 475136
Table 218. DCDC2 Control Register A Description (Continued)
21.1.2.4.
DCDC2 Control Register B
The organization of the DCDC2 Control Register B is shown below.
HW_DCDC2_CTRL1 X:$FA12
BITS LABEL RW RESET
23:15 RSRVD R
15:10 DCYC R
9:7
FFOR
6:0
C
DEFINITION
0
Duty Cycle. 2's complement number representing duty cycle of charging/discharging
the inductor. A large positive number indicates the energy needed by the system is
close to the limit the battery can provide, while a negative number means the battery
is easily supplying the power needed by the system.
100000 - DC-DC duty cycle at minimum (small charge time/large discharge
time)
......
011111 - DC-DC duty cycle at maximum (large charge time/ small discharge
time)
This value will be limited according to the NLVL and PLVD values set for this DC-DC
Converter. This value can be used to estimate the amount of life left in the battery at
the current rate of consumption.
RW 000
Feed Forward to loop filter value. This two's complement value steps the loop filter
value by the amount DDD once on a 000->DDD transition. Thus, this value must be
rewritten to 000 every time before use. The feed forward featue is used to help the
control loop react under heavy, but well-known, transient loads.
RW 0100000 Capacitor 1/C Value. This value represents 1/C value of the “capacitor” in the digital
loop filter in the common mode control loop in the DC-DC converter. The reset value
of decimal 32 is chosen in conjunction with the value for bits [6:0] in $FA11, the
actual external decoupling capacitor, and the clock rate to provide a stable control
system. This value will rarely be altered, but conditions may arise in the actual
application for which a different value is more optimum. Values can range between 0
and 127.
Table 219. DCDC2 Control Register B Description
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21.1.2.5.
DC-DC VddIO Control Register
The organization of the DC-DC VddIO Control Register is shown below.
HW_DCDC_VDDIO
X:$FA0E
BITS LABEL RW RESET
DEFINITION
23:12 RSRVD R
0
11
BOS
R
VddIO brownout detect status.
0No brownout detected on VddIO rail
1Brown out detected on VddIO rail
10
BOEN RW 0
VddIO brownout detect enable.
0VddIO brownout detect disabled
1VddIO brownout detect enabled
9
RSRVD R
0
8:5
BLVL
RW 0110
On-chip VddIO brownout detect level.
1100 3.64 V
1000 3.43 V
0100 3.22 V
0000 3.02 V
1001 3.38 V
0101 3.17 V
0001 2.96 V
1101 3.59 V
1110 3.54 V
1010 3.33 V
0110 3.12 V
0010 2.91 V
1111 3.48 V
1011 3.27 V
0111 3.07 V
0011 2.70 V
4
RSRVD R
0
3:0
VLVL
RW 1011
On-chip VddIO voltage level.
The voltage level settings for this field are the same as for the BLVL field above.
Note: BLVL and VLVL represent on-chip voltages. Due to voltage drop from the board to the on-chip supplies, the
board will measure higher than the BLVL and VLVL values.
Table 220. DC-DC VddIO Control Register Description
21.1.2.6.
DC-DC VddD Control Register
The organization of the DC-DC VddD Control Register is shown below.
HW_DCDC_VDDD
BITS LABEL RW RESET
23:12 RSRVD R
11
BOS
R
X:$FA0F
DEFINITION
0
VddD brownout detect status.
0No brownout detected on VddD rail
1Brownout detected on VddD rail
10
BOEN RW 0
VddD brownout detect enable.
0VddD brownout detect disabled
1VddD brownout detect enabled
9:5
BLVL
RW 00011 On-chip VddD brownout detect level.
01101
2.50 V
01000 2.03 V
00110
1.72 V
00000
1.61 V
01100
2.40 V
11110
2.00 V
10101
1.72 V
10110
1.57 V
01111
2.29 V
01011 1.98 V
00001
1.67 V
00011
1.56 V
11101
2.28 V
01010 1.92 V
10100
1.67 V
10001
1.52 V
11100
2.19 V
11001 1.90 V
10111
1.62 V
10000
1.47 V
01110
2.18 V
00101 1.87 V
11011
1.81 V
00010
1.45 V
11111
2.09 V
11000 1.86 V
00111
1.77 V
10011
1.43 V
01001
2.08 V
00100 1.82 V
11010
1.76 V
10010
1.33 V
4:0
VLVL
RW 00111 On-chip VddD voltage level. The voltage level settings for this field are the same as
for the BLVL field above. Both VLVL bit 4 and BLVL bit 9 must be set identical for
proper operation.
Note: BLVL and VLVL represent on-chip voltages. Due to voltage drop from the board to the on-chip supplies, the
board will measure higher than the BLVL and VLVL values.
Table 221. DC-DC VddD Control Register Description
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21.1.2.7.
DC-DC VddA/Battery Brownout Enable Control Register
The organization of the DC-DC VddA Control Register is shown below.
HW_DCDC_VDDA
X:$FA10
BITS LABEL RW RESET
DEFINITION
23:11 RSRVD R
0
10
BOEN RW 0
Battery brownout detect enable.
0Battery brownout detect disabled
1Battery brownout detect enabled
This bit enables the battery brown out feature controlled by the HW_LRADC_CTRL
register.
9:4
RSRVD RW 000110 Reserved.
3:0
VLVL
RW 0111
On-chip VddA voltage level.
1101
2.50 V
1001
2.08 V
0101
1.87 V
0001
1.67 V
1100
2.40 V
1000
2.03 V
0100
1.82 V
0000
1.61 V
1111
2.29 V
1011
1.98 V
0111
1.77 V
0011
1.56 V
1110
2.18 V
1010
1.92 V
0110
1.72 V
0010
1.45 V
The on-chip VddA voltage controlled by this field must be set to <= 300mV above the
on-chip VddD voltage selected through the VLVL field of the HW_DCDC_VDDD
register. The on-chip VddA voltage can only be controlled independently of the onchip VddD in DCDC mode 101 (3-channel boost configuration).
Note: VLVL represents on-chip voltage. Due to voltage drop from the board to the on-chip supplies, the board will
measure higher than the VLVL value.
Table 222. DC-DC VddA Control Register Description
21.1.2.8.
DC-DC Test Bit Register
The organization of the DC-DC Test Bit Control Register is shown below.
HW_DCDCTBR
BITS
23:20
19
18
17
16
15
14
13
12
11
LABEL
RSRVD
D2T7
D2T6
D2T5
D2T4
D2T3
D2T2
D2T1
D2T0
D1T11
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RESET
0
0
0
0
0
0
0
0
0
0
10
D1T10
RW 0
9
D1T9
RW 0
8
D1T8
RW 0
X:$FA14
DEFINITION
DCDC2 test bit 7
DCDC2 test bit 6
DCDC2 test bit 5
DCDC2 test bit 4
DCDC2 test bit 3
DCDC2 test bit 2
DCDC2 test bit 1
DCDC2 test bit 0
DCDC1 test bit 11
0 - No action.
1 - Use band gap bias in analog comparators
DCDC1 test bit 10
0 - No action.
1 - Connect additional capacitance to the common mode sense node
DCDC1 test bit 9
0 - No action.
1 - Drop analog comparator bias current.
This bit can reduce power when the DC-DC converter is running at a reduced clock
rate, i.e. when either DCDC1 test bit 5 or 4 are set.
DCDC1 test bit 8
0 - No action.
1 - Power up VddIO brownout detect circuit. (defaults powered down)
Table 223. DC-DC Test Bit Register Description
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BITS LABEL RW RESET
DEFINITION
7
D1T7
RW 0
DCDC1 test bit 7
0 - No action.
1 - No pass thru mode. Removes the functionality that shorts the battery to the
load in buck mode
6
D1T6
RW 0
DCDC1 test bit 6
0 - No action.
1 - No zero charge time allowed in boost. Removes the functionality that shorts
the battery to the load in boost mode
5
D1T5
RW 0
DCDC1 test bit 5
0 - No action.
1 - Slow DC-DC converter clock 2X
4
D1T4
RW 0
DCDC1 test bit 4
0 - No action.
1 - Slow DC-DC converter clock 4X
3
D1T3
RW 0
DCDC1 test bit 3
0 - No action.
1 - Make VddIO duty cycle adjustment 2->3. Adjusts the duty cycle scaling that
occurs when the inductor drives the VddIO output.
2
D1T2
RW 0
DCDC1 test bit 2
0 - No action.
1 - Turn off VddIO duty cycle adjustment.
This test bit removes the VddIO duty cycle scaling. Note: if both D1T2 and D1T3 bits
are set, then different functionality occurs. In this case DC-DC converter #1 is
powered off and a linear regulator powers the 1.8V supply from the 3.3V supply. The
current capability of the linear regulator is < 5mA, so this functionality should only be
used in low power modes of operation.
1
D1T1
RW 0
DCDC1 test bit 1
0 - No action.
1 - Invert DC-DC converter clock
0
D1T0
RW 0
DCDC1 test bit 0
This bit has two independent functions as defined below:
Function 1: Mode 5 comparator error decision default. (In mode 5, the DC-DC
converter must decide which output is farthest below it’s target value. Due to offsets,
there may be cases in which the converter cannot resolve which output is farthest
below its target.)
0 - Comparator decisions that result in an undefined state default to the VddD output.
1 - Comparator decisions that result in an undefined state default to the VddA output.
Note: that this functionality only is relevant when the system is configured in Mode 101.
Function 2: Mode 5 and 7 Dc-Dc Vddd brownout behavior.
0 - When a VddD brownout is detected, the VddD output is charged regardless of
the voltage on the VddIO output.
1 - The converter charges the output that is farthest below it’s target, regardless of
brownout events.
Note: that this functionality is only relevant when the system is configured in Mode
101 or 111.
Table 223. DC-DC Test Bit Register Description (Continued)
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21.2. System Brownout
The STMP3410 also contains circuitry to sense when the power requirements of the
system are more than the power the DC-DC converters can provide. The entrance
into the state of power required > power available is called a brownout event.
Detection of a brownout event is important to provide a controlled shutdown and
acceptable system behavior in the event of battery falling out, weak battery, short
circuit, etc. Typically, these brownout events are low frequency events (<100kHz)
due to the large capacitors on the battery and the supply rails in the application, and
the software can shutdown the application in a controlled manner. Figure 38 shows
the circuitry available to detect a brownout event:
$FA0F, BLVL
Comparator
resolution time ~1µs
$FA0F
BOS
Voltage Generator
VddD
$FA0F
BOEN
Internal Pole
@ ~1MHz
$FA0E, BLVL
Voltage Generator
VddIO
stack over/
under flow
$FA01
IRQB2NMI
$FA14
D1T8
NMI
$FA0E
BOS
IRQB
$FA0E
BOEN
$FA17, BATBRWN
$FA17
BATPWBR
$FFFF
BIT3
Voltage Generator
Battery
$FA10
BOEN
$FA10, BLVL
Voltage Generator
$FA10
BOS
VddA2
Figure 38. Brownout Event Detect Available Circuitry
As shown in Figure 38, there are three brownout sources that can be used to interupt the DSP via a NMI or IRQB. All brownouts are detected with comparators which
detect when a crucial system voltages (battery, VddD, VddIO) falls below a software
defined target voltage. These brownout detection comparators have a resolution
time of approximately 1us. This finite resolution time combined with the internal lowpass filter pole at 1MHz, limit the frequency range for which a brownout event will be
detected. In the audio frequency range, the brownout events will be detected when
any instantaneous system voltage falls below the target voltage as defined in the
software control of the Voltage Generator blocks. In the 100kHz frequency range,
the comparator resolution time will act to reduce brownout sensitivity, and the
instantaneous system voltage will need to fall below the software control value to
detect a brownout event. As the frequency continues to increase, this effect continues to worsen and by 500kHz, a brownout event cannot be detected. Thus, it is
necessary to decouple the supplies well on the board to filter any high frequency
transients that could cause an undetected brownout event.
5-3410-D1-2.0-0402
161
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
22. PIN DESCRIPTION
Pin 1
14 x 14 mm
Pin 1
100 TQFP
20 x 20 mm
10 x 10 mm Pin A1
144 TQFP
144 fpBGA
For additional package measurements, please see 23. “PACKAGE DRAWINGS” on page 173.
Figure 39. STMP3410 Package Photos
22.1. STMP3410 Pin Placement and Definitions
100TQFP
1
144TQFP
1
144fpBGA
M2
2
2
L2
3
3
K4
4
4
M3
5
5
L3
6
7
6
7
H6
M4
8
8
J5
9
9
L4
10
11
12
10
11
12
G6
H7
M5
NA
13
K5
13
14
L5
NA
15
M6
14
16
K6
NA
17
J6
PIN
GP14
SPI_MOSI
GP13
SPI_MISO
GP12
SPI_SCK
GP16
I2C_SCL
GP17
I2C_SDA
TESTMODE
CF_CE1n
GP44
CF_IORDn
GP52
CF_IOWRn
GP51
VssD2
VddD2
CF_A0
GP32
RAM_A0
CF_A22
GP69
RAM_A22
CF_A1
GP33
RAM_A1
CF_A21
GP68
RAM_A21
CF_A2
GP34
RAM_A2
CF_A20
GP67
RAM_A20
MODULE
GPIO
SPI
GPIO
SPI
GPIO
SPI
GPIO
I2C
GPIO
I2C
SYSTEM
EMC-CF
GPIO
EMC-CF
GPIO
EMC-CF
GPIO
POWER
POWER
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I/O
O
I/O
O
I/O
P
P
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
O
I/O
O
DESCRIPTION
GP0B14
SPI Master Output/Slave Input
GP0B13
SPI Master Input/Slave Output
GP0B12
SPI Serial Clock
GP0B16
I2C Serial Clock
GP0B17
I2C Serial Data
Test Mode Pin
CompactFlash Chip Enable 1
GP1B20
CompactFlash I/O Read Data Strobe
GP2B4
CompactFlash I/O Write Data Strobe
GP2B3
Digital Core Ground 2
Digital Core Power 2
CompactFlash Address 0
GP1B8
SDRAM Address 0
GP2B21
SDRAM Address 22
GP1B9
SDRAM Address 1
GP2B20
SDRAM Address 21
GP1B10
SDRAM Address 2
GP2B19
SDRAM Address 20
Table 224. STMP3410 Pin Definitions Table
(See Table 237 for Notes pertaining to Pin Placement and Definitions)
162
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
15
144TQFP
18
144fpBGA
L6
NA
19
L7
16
20
K7
NA
NA
NA
21
22
23
F7
G7
M7
17
24
J7
NA
25
L8
18
26
K8
NA
27
M8
19
28
J8
NA
29
M9
20
30
L9
NA
31
K9
21
32
L10
22
33
M10
23
34
M11
24
35
K10
25
36
M12
NA
37
L12
PIN
CF_A3
GP35
RAM_A3
CF_A19
GP66
RAM_A19
CF_A4
SM_CE3n
GP36
RAM_A4
VddIO3
VssIO3
CF_A18
GP65
RAM_A18
CF_A5
SM_CE2n
GP37
RAM_A5
CF_A17
GP64
RAM_A17
CF_A6
SM_CE0n
GP38
RAM_A6
CF_A16
GP63
RAM_A16
CF_A7
SM_SEn
GP39
RAM_A7
CF_A15
GP62
RAM_A15
CF_A8
SM_CLE
GP40
RAM_A8
CF_A14
GP61
RAM_A14
CF_A9
SM_ALE
GP41
RAM_A9
CF_A10
GP42
RAM_A10
CF_OEn
SM_REn
GP53
CF_CE0n
SM_CE1n
GP45
CF_WAIT
SM_READY
GP56
CF_A11
GP80
RAM_A11
MODULE
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
POWER
POWER
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
EMC-CF
EMC-SM
GPIO
EMC-CF
EMC-SM
GPIO
EMC-CF
GPIO
SDRAM
TYPE
O
I/O
O
O
I/O
O
O
O
I/O
O
P
P
O
I/O
O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
O
I/O
O
O
O
I/O
O
O
I/O
I
I
I/O
O
I/O
O
DESCRIPTION
GP1B11
SDRAM Address 3
GP2B18
SDRAM Address 19
SmartMedia Chip Enable 3
GP1B12
SDRAM Address 4
Digital I/O Power 3
Digital I/O Ground 3
GP2B17
SDRAM Address 18
GP1B13
SDRAM Address 5
GP2B16
SDRAM Address 17
GP1B14
SDRAM Address 6
GP2B15
SDRAM Address 16
SmartMedia Spare Area Enable
GP1B15
SDRAM Address 7
GP2B14
SDRAM Address 15
SmartMedia Command Latch Enable
GP1B16
SDRAM Address 8
GP2B13
SDRAM Address 14
SmartMedia Address Latch Enable
GP1B17
SDRAM Address 9
GP1B18
SDRAM Address 10
CompactFlash Output Enable Strobe
SmartMedia Read Enable Strobe
GP2B5
GP1B21
CompactFlash Wait
SmartMedia Ready/Busy
GP2B8
GP3B8
SDRAM Address 11
Table 224. STMP3410 Pin Definitions Table (Continued)
5-3410-D1-2.0-0402
163
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
26
144TQFP
38
144fpBGA
L11
NA
39
K11
27
40
K12
NA
41
J9
28
29
30
42
43
44
H8
G8
J10
NA
45
J12
31
46
H9
NA
47
J11
32
48
H12
NA
49
H11
33
50
H10
NA
51
G11
34
52
G10
NA
53
G12
35
54
G9
NA
55
F9
36
56
F11
NA
57
F12
PIN
CF_WEn
SM_WEn
GP54
CF_A12
GP81
RAM_A12
CF_WPn
SM_WPn
GP55
CF_A13
GP82
RAM_A13
VssIO1
VddIO1
CF_D0
SM_D0
GP24
RAM_D0
CF_D15
GP79
RAM_D15
CF_D1
SM_D1
GP25
RAM_D1
CF_D14
GP78
RAM_D14
CF_D2
SM_D2
GP26
RAM_D2
CF_D13
GP77
RAM_D13
CF_D3
SM_D3
GP27
RAM_D3
CF_D12
GP76
RAM_D12
CF_D4
SM_D4
GP28
RAM_D4
CF_D11
GP75
RAM_D11
CF_D5
SM_D5
GP29
RAM_D5
CF_D10
GP74
RAM_D10
CF_D6
SM_D6
GP30
RAM_D6
CF_D9
GP73
RAM_D9
MODULE
EMC-CF
EMC-SM
GPIO
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
EMC-CF
GPIO
SDRAM
POWER
POWER
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
EMC-CF
EMC-SM
GPIO
SDRAM
EMC-CF
GPIO
SDRAM
TYPE
O
O
I/O
O
I/O
O
O
O
I/O
O
I/O
O
P
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
CompactFlash Write Enable Strobe
SmartMedia Write Enable Strobe
GP2B6
GP3B9
SDRAM Address 12
CompactFlash Write Protect
SmartMedia Write Protect
GP2B7
GP3B10
SDRAM Address 13
Digital I/O Power 1
CompactFlash Data 0
SmartMedia I/O 0
GP1B0
SDRAM Data 0
CompactFlash Data 15
GP3B7
SDRAM Data 15
CompactFlash Data 1
SmartMedia I/O 1
GP1B1
SDRAM Data 1
GP3B6
SDRAM Data 14
CompactFlash Data 2
SmartMedia I/O 2
GP1B2
SDRAM Data 2
GP3B5
SDRAM Data 13
CompactFlash Data 3
SmartMedia I/O 3
GP1B3
SDRAM Data 3
GP3B4
SDRAM Data 12
CompactFlash Data 4
SmartMedia I/O 4
GP1B4
SDRAM Data 4
GP3B3
SDRAM Data 11
CompactFlash Data 5
SmartMedia I/O 5
GP1B5
SDRAM Data 5
GP3B2
SDRAM Data 10
CompactFlash Data 6
SmartMedia I/O 6
GP1B6
SDRAM Data 6
CompactFlash Data 9
GP3B1
SDRAM Data 9
164
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
37
144TQFP
58
144fpBGA
F10
38
39
NA
59
60
61
F8
E8
E9
40
62
E12
41
63
E10
42
64
E11
43
65
C11
44
66
D11
45
67
D10
46
47
48
49
50
NA
NA
NA
NA
NA
NA
51
52
53
NA
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
B11
D12
C12
B12
A12
A11
E7
E6
B10
A10
A9
C10
D9
C9
B9
54
55
56
57
58
59
60
61
62
63
NA
64
65
NA
NA
66
67
68
69
70
71
NA
72
73
74
75
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
D8
A7
D7
B8
A8
C8
C7
B7
B6
C6
D6
D5
A6
D4
C5
A5
B4
A4
B3
C4
C3
A3
B5
B2
A2
A1
PIN
CF_D7
SM_D7
GP31
RAM_D7
VssD1
VddD1
CF_D8
GP72
RAM_D8
CF_CDn
GP46
CF_READY
GP47
CF_WPn
GP48
CF_RESETn
GP50
CF_REGn
GP43
CF_BVD1
GP49
ONCE_DSI
DCDC_VddIO
DCDC_VddD
DCDC_Batt
DCDC_Gnd
DCDC_VddA
VddIO4
VssIO4
DCDC2_Gnd
DCDC2_Batt
DCDC2_Vout
ONCE_DSK
ONCE_DSO
ONCE_DRN
GP83
RAM_DQM0
DCDC_mod2
MIC
BATT
LINE1L
LRADC
LINE1R
VssA2
VddA2
HPL
VssHP
DCDC_mod1
VddHP
HPR
LINE2L
LINE2R
Vbg
Vag
ADCL
ADCR
REFn
REFp
DCDC_mod0
VssA1
VddA1
XTALO
XTALI
MODULE
EMC-CF
EMC-SM
GPIO
SDRAM
POWER
POWER
EMC-CF
GPIO
SDRAM
EMC-CF
GPIO
EMC-CF
GPIO
EMC-CF
GPIO
EMC-CF
GPIO
EMC-CF
GPIO
EMC-CF
GPIO
SYSTEM
DCDC
DCDC
DCDC
DCDC
DCDC
POWER
POWER
DCDC
DCDC
DCDC
SYSTEM
SYSTEM
SYSTEM
GPIO
SDRAM
DCDC
CODEC
POWER
CODEC
SYSTEM
CODEC
POWER
POWER
CODEC
POWER
DCDC
POWER
CODEC
CODEC
CODEC
CODEC
CODEC
CODEC
CODEC
CODEC
CODEC
DCDC
POWER
POWER
SYSTEM
SYSTEM
TYPE
I/O
I/O
I/O
I/O
P
P
I/O
I/O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
O
I/O
I
I/O
I
P
P
P
P
P
P
P
P
P
P
O
O
I
I/O
O
P
A
P
A
A
A
P
P
A
P
P
P
A
A
A
A
A
A
A
A
A
P
P
P
A
A
DESCRIPTION
CompactFlash Data 7
SmartMedia I/O 7
GP1B7
SDRAM Data 7
CompactFlash Data 8
GP3B0
SDRAM Data 8
CompactFlash Card Detect
GP1B22
CompactFlash Ready
GP1B23
GP2B0
CompactFlash Reset
GP2B2
CompactFlash Register Select
GP1B19
CompactFlash Bad Voltage Detect
GP2B1
Debug Data In
DCDC VddIO
DCDC VddD
DCDC Battery
DCDC Ground
DCDC VddA
Digital I/O Power 4
DCDC2 Ground
DCDC2 Battery
DCDC2 Vout
Debug Clock
Debug Data Out
Debug Reset
GP3B11
SDRAM DQM0
DCDC mode pin 2
Microphone Input
Battery Input
Line-in 1 Left
Low Resolution ADC Input
Line-in 1 Right
Analog Ground 2
Analog Power 2
Headphone/Line-out Left
Headphone Ground
DCDC mode pin 1
Headphone Power
Headphone/Line-out Right
Line-in 2 Left (AKA: FM-in Left)
Line-in 2 Right (AKA: FM-in Right)
Bandgap Decoupling Capacitor
Analog Ground Decoupling Capacitor
ADC Left Filter Capacitor
ADC Right Filter Capacitor
ADC Negative Reference Capacitor
ADC Positive Reference Capacitor
DCDC mode pin 0
Analog Ground 1
Analog Power 1
Crystal Out
Crystal In
5-3410-D1-2.0-0402
165
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
76
77
78
79
144TQFP
109
110
111
112
144fpBGA
B1
E4
E5
D3
80
81
82
83
NA
113
114
115
116
117
C2
C1
E3
D2
E2
84
85
86
87
88
118
119
120
121
122
D1
E1
F6
F5
F4
89
123
F3
NA
124
F2
90
125
G4
NA
126
F1
91
127
G3
NA
128
G2
92
129
H3
NA
130
G1
93
131
H4
NA
132
J3
94
133
H2
NA
134
H1
95
135
J1
NA
136
J2
96
97
98
137
138
139
G5
H5
J4
NA
140
K3
99
141
K2
NA
142
K1
100
143
L1
NA
144
M1
PIN
VddPLL
VddXTAL
VssPLL
FRESET
PSWITCH
USB_DP
USB_DM
GP11
GP9
GP90
RAM_CLK
GP8
GP10
VddD3
VssD3
GP7
I2S_DataO2
GP6
I2S_DataO1
GP84
RAM_DQM1
GP5
I2S_DataO0
GP89
RAM_CKE
GP4
I2S_BCLK
GP88
RAM_CSn
GP3
I2S_WCLK
GP85
RAM_RASn
GP2
I2S_DataI2
GP86
RAM_CASn
GP1
I2S_DataI1
GP87
RAM_WEn
GP0
I2S_DataI0
GP92
I2S_DataI0
VddIO2
VssIO2
GP19
TIO1
GP93
I2S_BCLK
GP18
TIO0
GP91
I2S_WCLK
GP15
SPI_SSn
CF_A23
GP70
RAM_A23
MODULE
POWER
SYSTEM
POWER
SYSTEM
SYSTEM
USB
USB
GPIO
GPIO
GPIO
SDRAM
GPIO
GPIO
POWER
POWER
GPIO
I2S
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
SDRAM
GPIO
I2S
GPIO
I2S
POWER
POWER
GPIO
TIMER
GPIO
I2S
GPIO
TIMER
GPIO
I2S
GPIO
SPI
EMC-CF
GPIO
SDRAM
TYPE
P
A
P
A
A
A
A
I/O
I/O
I/O
O
I/O
I/O
P
P
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
I/O
O
I/O
I
I/O
O
I/O
I
I/O
O
I/O
I
I/O
O
I/O
I
I/O
I
P
P
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
O
I/O
O
DESCRIPTION
PLL Power
Power for XTAL oscilator (generated on-chip)
PLL Ground
Fast Reset, Fast Falling Edge Resets Part
Power Switch
USB Positive Data Line
USB Negative Data Line
GP0B11
GP0B9
GP3B18
SDRAM Clock
GP0B8
GP0B10
GP0B7
I2S Data Out 2
GP0B6
I2S Data Out 1
GP3B12
SDRAM DQM1
GP0B5
I2S Data Out 0
GP3B17
SDRAM CKE
GP0B4
I2S Bit Clock
GP3B16
SDRAM CSn
GP0B3
I2S Word Clock
GP3B13
SDRAM RASn
GP0B2
I2S Data In 2
GP3B14
SDRAM CASn
GP0B1
I2S Data In 1
GP3B15
SDRAM WEn
GP0B0
I2S Data In 0
GP3B20
I2S Data In 0 (Alternate pin)
Digital I/O Power 2
GP0B19
Timer 1 Pin
GP3B21
I2S Bit Clock (Alternate pin)
GP0B18
Timer 0 Pin
GP3B19
I2S Word Clock (Alternate pin)
GP0B15 (Do not use as GPIO if using SPI)
SPI Slave Select
GP2B22
SDRAM Address 23
166
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
22.1.1.
100TQFP
55
57
59
62
65
NA
NA
66
67
68
69
70
71
Analog Pins
144TQFP
84
86
88
91
95
96
97
98
99
100
101
102
103
144fpBGA
A7
B8
C8
B6
A6
D4
C5
A5
B4
A4
B3
C4
C3
PIN
MIC
LINE1L
LINE1R
HPL
HPR
LINE2L
LINE2R
Vbg
Vag
ADCL
ADCR
REFn
REFp
TYPE
A
A
A
A
A
A
A
A
A
A
A
A
A
DESCRIPTION
Microphone Input
Line-in 1 Left
Line-in 1 Right
Headphone/Line-out Left
Headphone/Line-out Right
Line-in 2 Left (AKA: FM-in Left)
Line-in 2 Right (AKA: FM-in Right)
Bandgap Decoupling Capacitor
Analog Ground Decoupling Capacitor
ADC Left Filter Capacitor
ADC Right Filter Capacitor
ADC Negative Reference Capacitor
ADC Positive Reference Capacitor
Table 225. Analog Pins (CODEC Module)
22.1.2.
100TQFP
47
48
49
50
NA
NA
NA
NA
54
NA
NA
DCDC Converter Pins
144TQFP
69
70
71
72
73
76
77
78
83
93
104
144fpBGA
D12
C12
B12
A12
A11
B10
A10
A9
D8
D6
A3
PIN
DCDC_VddIO
DCDC_VddD
DCDC_Batt
DCDC_Gnd
DCDC_VddA
DCDC2_Gnd
DCDC2_Batt
DCDC2_Vout
DCDC_mod2
DCDC_mod1
DCDC_mod0
TYPE
P
P
P
P
P
P
P
P
P
P
P
DESCRIPTION
DCDC VddIO
DCDC VddD
DCDC Battery
DCDC Ground
DCDC VddA
DCDC2 Ground
DCDC2 Battery
DCDC2 Vout
DCDC mode pin 2
DCDC mode pin 1
DCDC mode pin 0
Table 226. DCDC Converter Pins
22.1.3.
100TQFP
7
8
9
12
NA
13
NA
14
NA
15
NA
16
NA
17
NA
18
NA
19
NA
20
NA
21
22
144TQFP
7
8
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
33
External Memory Interface (CompactFlash) Pins
144fpBGA
M4
J5
L4
M5
K5
L5
M6
K6
J6
L6
L7
K7
M7
J7
L8
K8
M8
J8
M9
L9
K9
L10
M10
PIN
CF_CE1n
CF_IORDn
CF_IOWRn
CF_A0
CF_A22
CF_A1
CF_A21
CF_A2
CF_A20
CF_A3
CF_A19
CF_A4
CF_A18
CF_A5
CF_A17
CF_A6
CF_A16
CF_A7
CF_A15
CF_A8
CF_A14
CF_A9
CF_A10
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
CompactFlash I/O Read Data Strobe
CompactFlash I/O Write Data Strobe
Table 227. External Memory Interface - CompactFlash Pins (EMC-CF Module)
5-3410-D1-2.0-0402
167
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
23
24
25
NA
26
NA
27
NA
30
NA
31
NA
32
NA
33
NA
34
NA
35
NA
36
NA
37
NA
40
41
42
43
44
45
NA
144TQFP
34
35
36
37
38
39
40
41
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
144
144fpBGA
M11
K10
M12
L12
L11
K11
K12
J9
J10
J12
H9
J11
H12
H11
H10
G11
G10
G12
G9
F9
F11
F12
F10
E9
E12
E10
E11
C11
D11
D10
M1
PIN
CF_OEn
CF_CE0n
CF_WAIT
CF_A11
CF_WEn
CF_A12
CF_WPn
CF_A13
CF_D0
CF_D15
CF_D1
CF_D14
CF_D2
CF_D13
CF_D3
CF_D12
CF_D4
CF_D11
CF_D5
CF_D10
CF_D6
CF_D9
CF_D7
CF_D8
CF_CDn
CF_READY
CF_WPn
CF_RESETn
CF_REGn
CF_BVD1
CF_A23
TYPE
O
O
I
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
O
I
O
DESCRIPTION
CompactFlash Output Enable Strobe
CompactFlash Wait
CompactFlash Write Enable Strobe
CompactFlash Data 0
CompactFlash Data 1
CompactFlash Data 2
CompactFlash Data 3
CompactFlash Data 4
CompactFlash Data 5
CompactFlash Data 6
CompactFlash Data 9
CompactFlash Data 7
CompactFlash Data 8
CompactFlash Card Detect
CompactFlash Ready
CompactFlash Reset
CompactFlash Register Select
CompactFlash Bad Voltage Detect
Table 227. External Memory Interface - CompactFlash Pins (EMC-CF Module) (Continued)
22.1.4.
100TQFP
16
17
18
19
20
21
23
24
25
26
27
30
31
32
33
34
35
36
37
144TQFP
20
24
26
28
30
32
34
35
36
38
40
44
46
48
50
52
54
56
58
External Memory Interface (SmartMedia) Pins
144fpBGA
K7
J7
K8
J8
L9
L10
M11
K10
M12
L11
K12
J10
H9
H12
H10
G10
G9
F11
F10
PIN
SM_CE3n
SM_CE2n
SM_CE0n
SM_SEn
SM_CLE
SM_ALE
SM_REn
SM_CE1n
SM_READY
SM_WEn
SM_WPn
SM_D0
SM_D1
SM_D2
SM_D3
SM_D4
SM_D5
SM_D6
SM_D7
TYPE
O
O
O
O
O
O
O
O
I
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
SmartMedia Spare Area Enable
SmartMedia Command Latch Enable
SmartMedia Address Latch Enable
SmartMedia Read Enable Strobe
SmartMedia Ready/Busy
SmartMedia Write Enable Strobe
SmartMedia Write Protect
SmartMedia I/O 0
SmartMedia I/O 1
SmartMedia I/O 2
SmartMedia I/O 3
SmartMedia I/O 4
SmartMedia I/O 5
SmartMedia I/O 6
SmartMedia I/O 7
Table 228. External Memory Interface - SmartMedia Pins (EMC-SM Module)
168
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
22.1.5.
100TQFP
1
2
3
4
5
7
8
9
12
NA
13
NA
14
NA
15
NA
16
NA
17
NA
18
NA
19
NA
20
NA
21
22
23
24
25
NA
26
NA
27
NA
30
NA
31
NA
32
NA
33
NA
34
NA
35
NA
36
NA
37
NA
40
41
42
43
44
45
NA
82
83
NA
General Purpose Input/Output Pins
144TQFP
1
2
3
4
5
7
8
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
62
63
64
65
66
67
82
115
116
117
144fpBGA
M2
L2
K4
M3
L3
M4
J5
L4
M5
K5
L5
M6
K6
J6
L6
L7
K7
M7
J7
L8
K8
M8
J8
M9
L9
K9
L10
M10
M11
K10
M12
L12
L11
K11
K12
J9
J10
J12
H9
J11
H12
H11
H10
G11
G10
G12
G9
F9
F11
F12
F10
E9
E12
E10
E11
C11
D11
D10
B9
E3
D2
E2
PIN
GP14
GP13
GP12
GP16
GP17
GP44
GP52
GP51
GP32
GP69
GP33
GP68
GP34
GP67
GP35
GP66
GP36
GP65
GP37
GP64
GP38
GP63
GP39
GP62
GP40
GP61
GP41
GP42
GP53
GP45
GP56
GP80
GP54
GP81
GP55
GP82
GP24
GP79
GP25
GP78
GP26
GP77
GP27
GP76
GP28
GP75
GP29
GP74
GP30
GP73
GP31
GP72
GP46
GP47
GP48
GP50
GP43
GP49
GP83
GP11
GP9
GP90
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
GP0B14
GP0B13
GP0B12
GP0B16
GP0B17
GP1B20
GP2B4
GP2B3
GP1B8
GP2B21
GP1B9
GP2B20
GP1B10
GP2B19
GP1B11
GP2B18
GP1B12
GP2B17
GP1B13
GP2B16
GP1B14
GP2B15
GP1B15
GP2B14
GP1B16
GP2B13
GP1B17
GP1B18
GP2B5
GP1B21
GP2B8
GP3B8
GP2B6
GP3B9
GP2B7
GP3B10
GP1B0
GP3B7
GP1B1
GP3B6
GP1B2
GP3B5
GP1B3
GP3B4
GP1B4
GP3B3
GP1B5
GP3B2
GP1B6
GP3B1
GP1B7
GP3B0
GP1B22
GP1B23
GP2B0
GP2B2
GP1B19
GP2B1
GP3B11
GP0B11
GP0B9
GP3B18
Table 229. General Purpose Input/Output Pins
5-3410-D1-2.0-0402
169
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
84
85
88
89
NA
90
NA
91
NA
92
NA
93
NA
94
NA
95
NA
98
NA
99
NA
100
NA
144TQFP
118
119
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
139
140
141
142
143
144
144fpBGA
D1
E1
F4
F3
F2
G4
F1
G3
G2
H3
G1
H4
J3
H2
H1
J1
J2
J4
K3
K2
K1
L1
M1
PIN
GP8
GP10
GP7
GP6
GP84
GP5
GP89
GP4
GP88
GP3
GP85
GP2
GP86
GP1
GP87
GP0
GP92
GP19
GP93
GP18
GP91
GP15
GP70
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
GP0B8
GP0B10
GP0B7
GP0B6
GP3B12
GP0B5
GP3B17
GP0B4
GP3B16
GP0B3
GP3B13
GP0B2
GP3B14
GP0B1
GP3B15
GP0B0
GP3B20
GP0B19
GP3B21
GP0B18
GP3B19
GP0B15 (Do not use as GPIO if using SPI)
GP2B22
Table 229. General Purpose Input/Output Pins (Continued)
I2C Interface Pins
22.1.6.
100TQFP
4
5
144TQFP
4
5
144fpBGA
M3
L3
PIN
I2C_SCL
I2C_SDA
TYPE
I/O
I/O
DESCRIPTION
I2C Serial Clock
I2C Serial Data
Table 230. I2C Interface Pins
I2S Interface Pins
22.1.7.
100TQFP
88
89
90
91
92
93
94
95
NA
NA
NA
144TQFP
122
123
125
127
129
131
133
135
136
140
142
144fpBGA
F4
F3
G4
G3
H3
H4
H2
J1
J2
K3
K1
PIN
I2S_DataO2
I2S_DataO1
I2S_DataO0
I2S_BCLK
I2S_WCLK
I2S_DataI2
I2S_DataI1
I2S_DataI0
I2S_DataI0
I2S_BCLK
I2S_WCLK
TYPE
O
O
O
I
I
I
I
I
I
I
I
DESCRIPTION
I2S Data Out 2
I2S Data Out 1
I2S Data Out 0
I2S Bit Clock
I2S Word Clock
I2S Data In 2
I2S Data In 1
I2S Data In 0
I2S Data In 0 (Alternate pin)
I2S Bit Clock (Alternate pin)
I2S Word Clock (Alternate pin)
Table 231. I2S Interface Pins
22.1.8.
100TQFP
10
11
NA
NA
28
29
38
Power Pins
144TQFP
10
11
21
22
42
43
59
144fpBGA
G6
H7
F7
G7
H8
G8
F8
PIN
VssD2
VddD2
VddIO3
VssIO3
VssIO1
VddIO1
VssD1
TYPE
P
P
P
P
P
P
P
DESCRIPTION
Digital I/O Power 3
Digital I/O Power 1
Table 232. Power Pins
170
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
39
NA
NA
56
60
61
63
64
72
73
76
78
86
87
96
97
144TQFP
60
74
75
85
89
90
92
94
105
106
109
111
120
121
137
138
144fpBGA
E8
E7
E6
D7
C7
B7
C6
D5
B5
B2
B1
E5
F6
F5
G5
H5
PIN
VddD1
VddIO4
VssIO4
BATT
VssA2
VddA2
VssHP
VddHP
VssA1
VddA1
VddPLL
VssPLL
VddD3
VssD3
VddIO2
VssIO2
TYPE
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
DESCRIPTION
Digital I/O Power 4
Battery Input
Analog Ground 2
Analog Power 2
Headphone Ground
Headphone Power
Analog Ground 1
Analog Power 1
PLL Power
PLL Ground
Digital I/O Power 2
Table 232. Power Pins (Continued)
22.1.9.
100TQFP
12
NA
13
NA
14
NA
15
NA
16
NA
17
NA
18
NA
19
NA
20
NA
21
22
NA
NA
NA
30
NA
31
NA
32
NA
33
NA
34
NA
35
NA
36
NA
37
NA
NA
NA
SDRAM Interface Pins
144TQFP
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
33
37
39
41
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
61
82
117
144fpBGA
M5
K5
L5
M6
K6
J6
L6
L7
K7
M7
J7
L8
K8
M8
J8
M9
L9
K9
L10
M10
L12
K11
J9
J10
J12
H9
J11
H12
H11
H10
G11
G10
G12
G9
F9
F11
F12
F10
E9
B9
E2
PIN
RAM_A0
RAM_A22
RAM_A1
RAM_A21
RAM_A2
RAM_A20
RAM_A3
RAM_A19
RAM_A4
RAM_A18
RAM_A5
RAM_A17
RAM_A6
RAM_A16
RAM_A7
RAM_A15
RAM_A8
RAM_A14
RAM_A9
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_D0
RAM_D15
RAM_D1
RAM_D14
RAM_D2
RAM_D13
RAM_D3
RAM_D12
RAM_D4
RAM_D11
RAM_D5
RAM_D10
RAM_D6
RAM_D9
RAM_D7
RAM_D8
RAM_DQM0
RAM_CLK
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
DESCRIPTION
SDRAM Address 0
SDRAM Address 22
SDRAM Address 1
SDRAM Address 21
SDRAM Address 2
SDRAM Address 20
SDRAM Address 3
SDRAM Address 19
SDRAM Address 4
SDRAM Address 18
SDRAM Address 5
SDRAM Address 17
SDRAM Address 6
SDRAM Address 16
SDRAM Address 7
SDRAM Address 15
SDRAM Address 8
SDRAM Address 14
SDRAM Address 9
SDRAM Address 10
SDRAM Address 11
SDRAM Address 12
SDRAM Address 13
SDRAM Data 0
SDRAM Data 15
SDRAM Data 1
SDRAM Data 14
SDRAM Data 2
SDRAM Data 13
SDRAM Data 3
SDRAM Data 12
SDRAM Data 4
SDRAM Data 11
SDRAM Data 5
SDRAM Data 10
SDRAM Data 6
SDRAM Data 9
SDRAM Data 7
SDRAM Data 8
SDRAM DQM0
SDRAM Clock
Table 233. SDRAM Interface Pins
5-3410-D1-2.0-0402
171
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
100TQFP
NA
NA
NA
NA
NA
NA
NA
144TQFP
124
126
128
130
132
134
144
144fpBGA
F2
F1
G2
G1
J3
H1
M1
PIN
RAM_DQM1
RAM_CKE
RAM_CSn
RAM_RASn
RAM_CASn
RAM_WEn
RAM_A23
TYPE
O
O
O
O
O
O
O
DESCRIPTION
SDRAM DQM1
SDRAM CKE
SDRAM CSn
SDRAM RASn
SDRAM CASn
SDRAM WEn
SDRAM Address 23
Table 233. SDRAM Interface Pins (Continued)
22.1.10. SPI Interface Pins
100TQFP
1
2
3
100
144TQFP
1
2
3
143
144fpBGA
M2
L2
K4
L1
PIN
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SSn
TYPE
I/O
I/O
I/O
I
DESCRIPTION
SPI Master Output/Slave Input
SPI Master Input/Slave Output
SPI Serial Clock
SPI Slave Select
Table 234. SPI Interface Pins
22.1.11. System Pins
100TQFP
6
46
51
52
53
58
74
75
77
79
144TQFP
6
68
79
80
81
87
107
108
110
112
144fpBGA
H6
B11
C10
D9
C9
A8
A2
A1
E4
D3
PIN
TESTMODE
ONCE_DSI
ONCE_DSK
ONCE_DSO
ONCE_DRN
LRADC
XTALO
XTALI
VddXTAL
FRESET
PSWITCH
TYPE
I
I
O
O
I
A
A
A
A
A
A
DESCRIPTION
Test Mode Pin
Debug Data In
Debug Clock
Debug Data Out
Debug Reset
Low Resolution ADC Input
Crystal Out
Crystal In
Power for XTAL oscilator (generated on-chip)
Fast Reset, Fast Falling Edge Resets Part
Power Switch
Table 235. System Pins
22.1.12. USB Interface Pins
100TQFP
80
81
98
99
144TQFP
113
114
139
141
144fpBGA
C2
C1
J4
K2
PIN
USB_DP
USB_DM
TIO1
TIO0
TYPE
A
A
I/O
I/O
DESCRIPTION
USB Positive Data Line
USB Negative Data Line
Timer 1 Pin
Timer 0 Pin
Table 236. USB Interface Pins
TYPE
MODULE
DESCRIPTION
CODEC
Analog pins
DCDC
DCDC Converter pins
EMC-CF
External memory interface pins (CompactFlash)
EMC-SM
External memory interface pins (SmartMedia)
GPIO
General Purpose Input/Output pins
I2C
I2C interface pins
I2S
I2S interface pins
POWER
Power pins
SDRAM
SDRAM interface pins
SPI
SPI interface pins
SYSTEM
System pins
TIMER
Timer pins
USB
USB interface pins
Almost all digital pins are powered down (i.e. high impedance) at reset, until reprogrammed by the DSP. The only exceptions are:
TESTMODE, DSI, DSK, DSO, DRN; these pins are always active.
A
I
I/O
O
P
DESCRIPTION
Analog pin
Input pin
Input/output pin
Output pin
Power pin
Table 237. Notes on Pin Placement and Definitions
172
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23. PACKAGE DRAWINGS
23.1. 100-Pin TQFP
D
D
1
BODY + 2.00 mm FOOTPRINT
LEADS
100L-1.4 THK.
L/F
DIMS.
.127 .152
TOL.
A
1.60
MAX.
A1
.05 MIN./.15 MAX.
A2
1.40
±.05
16.00
D
±.20
14.00
D1
±.05
E
16.00
±.20
14.00
E1
±.05
+.15/-.10
.60
L
e
.50
BASIC
b
±.05
.22
O
0°-7D
MAX.
.08
ddd
ccc
MAX.
.08
N
1
A
E
B
E
1
D
12° TYP.
A2
A
e
A1
12° TYP.
ANOTHER VARIATION
OF PIN 1 VISUAL AID
N
.20 RAD. TYP.
NOTES: 1) ALL DIMENSIONS IN MM.
1
2) DIMENSIONS SHOWN ARE NOMINAL WITH TOL.
AS INDICATED.
3) L/F: EFTEC 64T COPPER OR EQUIVALENT, 0.127 MM
(.005") OR 0.15 MM (.006") THICK.
4) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE,
AT 0.25 ABOVE THE SEATING PLANE.
.20 RAD. TYP.
6°P4°
A
STANDOFF
A
1
.25
.17 MAX.
O
L
b
ddd M C A-B S D S
SEATING
PLANE
C
LEAD COPLANARITY
100 Pin 14x14 TQFP
ccc C
Figure 40. 100-Pin TQFP Package Drawing
Supply of this Implementation of AAC technology does not convey a license nor imply any right to use this Implementation in
any finished end-user or ready-to-use final product. An independent license for such use is required.
MPEG Layer 3 audio coding technology from Fraunhofer IIS and THOMSON multimedia.
5-3410-D1-2.0-0402
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23.2. 144-Pin TQFP
N
DIMS.
A
A1
A2
D
D1
E
E1
L
e
b
ddd
ccc
O
1
B
A
1
D
1
BODY + 2.00 mm FOOTPRINT
144L
TOLS. LEADS
MAX.
1.60
.05 MIN/.15 MAX
±.05
1.40
22.00
±.20
20.00
±.10
±.20
22.00
±.10
20.00
+.15/-.10
.60
.50
BASIC
.22
±.05
.08
.08
MAX.
0°-5D
12° TYP.
A1
A2
A
e
NOTES: 1) ALL DIMENSIONS IN MM.
12° TYP.
2) DIMENSIONS SHOWN ARE NOMINAL WITH
TOLERANCES AS INDICATED.
3) L/F: EFTEC 64T COPPER OR EQUIVALENT,
0.127 MM (.005") THICK.
0.20 RAD. MAX.
4) FOOT LENGTH "L" IS MEASURED AT GAGE
PLANE AT 0.25 MM ABOVE THE SEATING PLANE
0.20 RAD. NOM.
6° P4D
A
A1
STANDOFF
0.25
SEATING
PLANE
C
C
0.17 MAX.
O
b
ddd M C A-B S D S
20x20 mm TQFP
LEAD COPLANARITY
ccc
C
L
Figure 41. 144-Pin TQFP Package Drawing
174
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23.3. 144-Pin fpBGA
DEATIL B
0.10
-A-
D
12
11
10
9
8
6
7
5
4
3
2
DIMENSIONAL REFERENCES
1
-B-
E
MIN.
NOR.
MAX.
A
1.25
1.35
1.45
A1
0.25
0.30
0.35
A2
0.65
0.70
0.75
10.00
10.20
A
B
C
D
E
F
G
H
J
K
L
M
(e)
E2
REF.
(E1)
D
D1
(e)
D2
(D1)
8.80 BSC.
D2
9.80
10.00
10.20
E
9.80
10.00
10.20
E1
BOTTOM VIEW
TOP VIEW
9.80
8.80 BSC
E2
9.80
10.00
10.20
b
0.35
0.40
0.45
0.35
c
f
DETAIL A
NX b
0.15 s
f
0.075 s
A s
B s
C
4
e
SIDE VIEW
C
aaa
0.15
bbb
0.20
0.25
ccc
e
0.725
f
0.50
0.80
0.875
0.60
0.70
M
12
N
144
NOTES:
DETAIL B
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. ’e’ REPRESENTS THE BASIC SOLDER BALL GRID PITCH.
ccc
c
bbb C
-CA
A2
DETAIL A
C
AND SYMBOL ’N’ IS THE MAXIMUM ALLOWABLE NUMBER OF
BALLS AFTER DEPOPULATING.
4. ’b’ IS MEASURABLE AT THE MAXIMUM SOLDER BALL DIAMETER
PARALLEL TO PRIMARY DAIUM -C- .
6
SEATING PLANE
5. DIMENSION ’aaa’ IS MEASURED PARALLEL TO PRIMARY DATUM -C- .
6. PRIMARY DATUM -C- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
A1
aaa C
3. ’M’ REPRESENTS THE BASIC SOLDER BALL MATRIX SIZE.
7. PACKAGE SURFACE SHALL BE MATTE FINISH CHARMILLES 24 TO 27.
5
8. PACKAGE CENTERING TO SUBSTRATE SHALL BE 0.0760 MM MAXIMUM
FOR BOTH X AND Y DIRECTION RESPECTIVELY.
9. PACKAGE WARP SHALL BE 0.050MM MAXIMUM.
144 fpBGA (10 x 10 mm)
10. SUBSTRATE MATERIAL BASE IS BT RESIN.
11. THE OVERALLPACKAGE THICKNESS "A" ALREADY CONSIDERS COLLAPSE BALLS
Figure 42. 144-Pin fpBGA Package Drawing
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24. INDEX OF REGISTERS
HW_ADCBAR
HW_ADCCPR
HW_ADCCSR
HW_ADCMR
HW_ADCSRR
HW_ADCWCR
HW_CCR
HW_CDI_CTLCSR
HW_CDI_SI0TBASE
HW_CDI_SI1TBASE
HW_CDICSI0CSR
HW_CDICSI1CSR
HW_CDICTRLTBR
HW_CDICTRLTMR
HW_CDIDATAR
HW_CDIPINCFGR
HW_CDISI0DATAR
HW_CDISI0TMRR
HW_CDISI1DATAR
HW_CDISI1TMRR
HW_CDSYNCBAR
HW_CDSYNCCPR
HW_CDSYNCCSR
HW_CDSYNCDR
HW_CDSYNCMODR
HW_CDSYNCWCR
HW_CYCSTLCNT
HW_DACBAR
HW_DACCPR
HW_DACCSR
HW_DACMR
HW_DACSRR
HW_DACWCR
HW_DCDC_VDDA
HW_DCDC_VDDD
HW_DCDC_VDDIO
HW_DCDC1_CTRL0
HW_DCDC1_CTRL1
HW_DCDC2_CTRL0
HW_DCDC2_CTRL1
HW_DCDCTBR
HW_DCLKCNTL
HW_DCLKCNTU
HW_FLCFCR
HW_FLCFTMR1R
HW_FLCFTMR2R
HW_FLCR
HW_FLCR2
HW_FLSAHR
HW_FLSALR
HW_FLSMCR
HW_FLSMTMR1R
HW_FLSMTMR2R
HW_GDBR
HW_GP08MA
HW_GP0DIR
HW_GP0DOER
HW_GP0DOR
HW_GP0ENR
HW_GP0IENR
HW_GP0ILVLR
176
X:$FB05 .........................................................................................123
X:$FB03 .........................................................................................123
X:$FB00 .........................................................................................125
X:$FB04 .........................................................................................123
X:$FB01 .........................................................................................124
X:$FB02 .........................................................................................124
X:$FA00 ...........................................................................................24
X:$F280 ............................................................................................96
X:$F28A ...........................................................................................98
X:$F28E ...........................................................................................98
X:$F288 ............................................................................................98
X:$F28C ...........................................................................................98
X:$F282 ............................................................................................97
X:$F281 ............................................................................................96
X:$F283 ............................................................................................97
X:$F284 ............................................................................................97
X:$F28B ...........................................................................................99
X:$F289 ............................................................................................99
X:$F28F ............................................................................................99
X:$F28D ...........................................................................................99
X:$F605 ............................................................................................87
X:$F603 ............................................................................................86
X:$F600 ............................................................................................85
X:$F601 ............................................................................................86
X:$F604 ............................................................................................86
X:$F602 ............................................................................................86
X:$FFED ...........................................................................................22
X:$F805 ..........................................................................................119
X:$F803 ..........................................................................................120
X:$F800 ..........................................................................................122
X:$F804 ..........................................................................................120
X:$F801 ..........................................................................................121
X:$F802 ..........................................................................................120
X:$FA10 .........................................................................................159
X:$FA0F .........................................................................................158
X:$FA0E .........................................................................................158
X:$FA0C .........................................................................................155
X:$FA0D .........................................................................................156
X:$FA11 .........................................................................................156
X:$FA12 .........................................................................................157
X:$FA14 .........................................................................................159
X:$FFEA ...........................................................................................22
X:$FFEB ...........................................................................................22
X:$F008 ............................................................................................52
X:$F009 ............................................................................................53
X:$F00A ...........................................................................................53
X:$F000 ............................................................................................47
X:$F004 ............................................................................................48
X:$F002 ............................................................................................48
X:$F001 ............................................................................................48
X:$F010 ............................................................................................50
X:$F011 ............................................................................................51
X:$F012 ............................................................................................51
..........................................................................................................36
X:$F40A .........................................................................................115
X:$F402 ..........................................................................................112
X:$F403 ..........................................................................................112
X:$F401 ..........................................................................................112
X:$F400 ..........................................................................................112
X:$F405 ..........................................................................................113
X:$F406 ..........................................................................................113
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
HW_GP0IPENR
HW_GP0IPOLR
HW_GP0ISTATR
HW_GP0PWR
HW_GP18MA
HW_GP1DIR
HW_GP1DOER
HW_GP1DOR
HW_GP1ENR
HW_GP1IENR
HW_GP1ILVLR
HW_GP1IPENR
HW_GP1IPOLR
HW_GP1ISTATR
HW_GP1PWR
HW_GP28MA
HW_GP2DIR
HW_GP2DOER
HW_GP2DOR
HW_GP2ENR
HW_GP2IENR
HW_GP2ILVLR
HW_GP2IPENR
HW_GP2IPOLR
HW_GP2ISTATR
HW_GP2PWR
HW_GP38MA
HW_GP3DIR
HW_GP3DOER
HW_GP3DOR
HW_GP3ENR
HW_GP3IENR
HW_GP3ILVLR
HW_GP3IPENR
HW_GP3IPOLR
HW_GP3ISTATR
HW_GP3PWR
HW_HPCTRL
HW_I2CCSR
HW_I2CDAT
HW_I2CDIV
HW_ICLENABLE0R
HW_ICLENABLE1R
HW_ICLFENABLE0R
HW_ICLFENABLE1R
HW_ICLFORCE0R
HW_ICLFORCE1R
HW_ICLOBSVZ0R
HW_ICLOBSVZ1R
HW_ICLPRIOR0R
HW_ICLPRIOR1R
HW_ICLPRIOR2R
HW_ICLPRIOR3R
HW_ICLPRIOR4R
HW_ICLSTATUS0R
HW_ICLSTATUS1R
HW_ICLSTEER0R
HW_ICLSTEER1R
HW_ICLSTEER2R
HW_IPR
HW_LRADC_CTRL
HW_LRADC_RES
5-3410-D1-2.0-0402
X:$F404 ..........................................................................................113
X:$F407 ..........................................................................................114
X:$F408 ..........................................................................................114
X:$F409 ..........................................................................................114
X:$F41A .........................................................................................115
X:$F412 ..........................................................................................112
X:$F413 ..........................................................................................112
X:$F411 ..........................................................................................112
X:$F410 ..........................................................................................112
X:$F415 ..........................................................................................113
X:$F416 ..........................................................................................113
X:$F414 ..........................................................................................113
X:$F417 ..........................................................................................114
X:$F418 ..........................................................................................114
X:$F419 ..........................................................................................114
X:$F42A .........................................................................................115
X:$F422 ..........................................................................................112
X:$F423 ..........................................................................................112
X:$F421 ..........................................................................................112
X:$F420 ..........................................................................................112
X:$F425 ..........................................................................................113
X:$F426 ..........................................................................................113
X:$F424 ..........................................................................................113
X:$F427 ..........................................................................................114
X:$F428 ..........................................................................................114
X:$F429 ..........................................................................................114
X:$F43A .........................................................................................115
X:$F432 ..........................................................................................112
X:$F433 ..........................................................................................112
X:$F431 ..........................................................................................112
X:$F430 ..........................................................................................112
X:$F435 ..........................................................................................113
X:$F436 ..........................................................................................113
X:$F434 ..........................................................................................113
X:$F437 ..........................................................................................114
X:$F438 ..........................................................................................114
X:$F439 ..........................................................................................114
X:$FA15 .........................................................................................134
X:$FFE7 ...........................................................................................55
X:$FFE6 ...........................................................................................56
X:$FFE7 ...........................................................................................57
X:$F300 ............................................................................................30
X:$F301 ............................................................................................31
X:$F30D ...........................................................................................35
X:$F30E ...........................................................................................35
X:$F30B ...........................................................................................35
X:$F30C ...........................................................................................35
X:$F30F ............................................................................................36
X:$F310 ............................................................................................36
X:$F304 ............................................................................................31
X:$F305 ............................................................................................32
X:$F306 ............................................................................................32
X:$F307 ............................................................................................32
X:$F311 ............................................................................................33
X:$F302 ............................................................................................31
X:$F303 ............................................................................................31
X:$F308 ............................................................................................33
X:$F309 ............................................................................................34
X:$F30A ...........................................................................................34
X:$FFFF ...........................................................................................27
X:$FA17 .........................................................................................136
X:$FA18 .........................................................................................137
177
OFFIC IA L
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D OCU MENTATION
4/17 /02
STMP3410
HW_MIXADCGAINR
HW_MIXDACINVR
HW_MIXLINE1INVR
HW_MIXLINE2INVR
HW_MIXMASTERVR
HW_MIXMICINVR
HW_MIXPWRDNR
HW_MIXRECSELR
HW_MIXTBR
HW_OMR
HW_PXCFG
HW_PYCFG
HW_RAM_ROM_CFG
HW_RCR
HW_REF_CTRL
HW_REVR
HW_RSBAR
HW_RSCPR
HW_RSCSR
HW_RSMODR
HW_RSOFFSETR
HW_RSPBAR
HW_RSSPANR
HW_RSWRDCNTR
HW_RTCLOW
HW_RTCUP
HW_SAIRCSR
HW_SAIRX0R
HW_SAIRX1R
HW_SAIRX2R
HW_SAITCSR
HW_SAITX0R
HW_SAITX1R
HW_SAITX2R
HW_SCRATCH
HW_SDRAM_ADDR1
HW_SDRAM_ADDR2
HW_SDRAM_BAR
HW_SDRAM_CNT
HW_SDRAM_CSR
HW_SDRAM_DBAR1
HW_SDRAM_DBAR2
HW_SDRAM_DMR1
HW_SDRAM_DMR2
HW_SDRAM_MODE
HW_SDRAM_MR
HW_SDRAM_SIZE
HW_SDRAM_SYSADDR
HW_SDRAM_TIMER1
HW_SDRAM_TIMER2
HW_SDRAM_TYPE
HW_SPARER
HW_SPCSR
HW_SPDR
HW_SWIZZLEBARRELR
HW_SWIZZLEBIGENDIANR
HW_SWIZZLEBITREVR
HW_SWIZZLECS1R
HW_SWIZZLECS2R
HW_SWIZZLEDATA1R
HW_SWIZZLEDATA2R
HW_SWIZZLEDESTADDRR
HW_SWIZZLEPASSISBR
178
X:$FA0A .........................................................................................130
X:$FA08 .........................................................................................129
X:$FA06 .........................................................................................129
X:$FA07 .........................................................................................129
X:$FA04 .........................................................................................127
X:$FA05 .........................................................................................128
X:$FA0B .........................................................................................131
X:$FA09 .........................................................................................130
X:$FA03 .........................................................................................131
..........................................................................................................23
X:$FFE8 ...........................................................................................16
X:$FFE9 ...........................................................................................16
X:$FFED ...........................................................................................19
X:$FA01 ...........................................................................................21
X:$FA19 .........................................................................................133
X:$FA02 ...........................................................................................20
X:$F705 ............................................................................................89
X:$F703 ............................................................................................88
X:$F700 ............................................................................................87
X:$F704 ............................................................................................89
X:$F701 ............................................................................................88
X:$F706 ............................................................................................89
X:$F707 ............................................................................................89
X:$F702 ............................................................................................88
X:$F500 ............................................................................................84
X:$F501 ............................................................................................84
X:$FFF0 .........................................................................................101
X:$FFF1 .........................................................................................102
X:$FFF2 .........................................................................................102
X:$FFF3 .........................................................................................102
X:$FFF5 .........................................................................................103
X:$FFF6 .........................................................................................104
X:$FFF7 .........................................................................................104
X:$FFF8 .........................................................................................105
X:$FA13 ...........................................................................................26
X:$F901 ............................................................................................70
X:$F902 ............................................................................................71
X:$F907 ............................................................................................72
X:$F90D ...........................................................................................74
X:$F900 ............................................................................................75
X:$F909 ............................................................................................73
X:$F90A ...........................................................................................73
X:$F90B ...........................................................................................73
X:$F90C ...........................................................................................73
X:$F90E ...........................................................................................74
X:$F908 ............................................................................................72
X:$F904 ............................................................................................71
X:$F903 ............................................................................................71
X:$F905 ............................................................................................71
X:$F906 ............................................................................................72
X:$F90F ............................................................................................74
X:$FA16 ...........................................................................................26
X:$FFF9 ...........................................................................................63
X:$FFFA ...........................................................................................64
X:$F38F ............................................................................................81
X:$F387 ............................................................................................80
X:$F388 ............................................................................................80
X:$F380 ............................................................................................77
X:$F381 ............................................................................................78
X:$F384 ............................................................................................79
X:$F385 ............................................................................................79
X:$F386 ............................................................................................79
X:$F38A ...........................................................................................80
5-3410-D1-2.0-0402
OFFIC IA L
PRODUC T
D OCU MENTATION
4/17 /02
STMP3410
HW_SWIZZLEPASSISWR
HW_SWIZZLEPASSLSBR
HW_SWIZZLEPASSLSWR
HW_SWIZZLEPASSMSBR
HW_SWIZZLEPASSMSWR
HW_SWIZZLESIZER
HW_SWIZZLESOURCER
HW_TB_BAR
HW_TB_CSR
HW_TB_CURR
HW_TB_MASK0
HW_TB_MASK1
HW_TB_MOD
HW_TB_TCSR0
HW_TB_TCSR1
HW_TB_TCSR2
HW_TB_TCSR3
HW_TB_TCSR4
HW_TB_TCSR5
HW_TB_TCSR6
HW_TB_TCSR7
HW_TB_TVAL0
HW_TB_TVAL1
HW_TB_TVAL2
HW_TB_TVAL3
HW_TB_TVAL4
HW_TB_TVAL5
HW_TB_TVAL6
HW_TB_TVAL7
HW_TMR0CNTR
HW_TMR0CR
HW_TMR1CNTR
HW_TMR1CR
HW_TMR2CNTR
HW_TMR2CR
HW_TMR3CNTR
HW_TMR3CR
HW_USBCBAR
HW_USBCSR
HW_USBEP0PTRR
HW_USBEP0R
HW_USBEP1R
HW_USBEP2R
HW_USBEP3R
HW_USBEP4R
HW_USBEP5R
HW_USBEP6R
HW_USBEP7R
HW_USBUTILR
HW_WATCHDOGCNTR
HW_WATCHDOGENR
5-3410-D1-2.0-0402
X:$F38D ...........................................................................................81
X:$F389 ............................................................................................80
X:$F38C ...........................................................................................81
X:$F38B ...........................................................................................80
X:$F38E ...........................................................................................81
X:$F382 ............................................................................................79
X:$F383 ............................................................................................79
X:$F081 ..........................................................................................107
X:$F080 ..........................................................................................107
X:$F083 ..........................................................................................108
X:$F084 ..........................................................................................108
X:$F085 ..........................................................................................108
X:$F082 ..........................................................................................108
X:$F090 ..........................................................................................108
X:$F091 ..........................................................................................108
X:$F092 ..........................................................................................108
X:$F093 ..........................................................................................108
X:$F094 ..........................................................................................108
X:$F095 ..........................................................................................108
X:$F096 ..........................................................................................108
X:$F097 ..........................................................................................108
X:$F098 ..........................................................................................109
X:$F099 ..........................................................................................109
X:$F09A .........................................................................................109
X:$F09B .........................................................................................109
X:$F09C .........................................................................................109
X:$F09D .........................................................................................109
X:$F09E .........................................................................................109
X:$F09F ..........................................................................................109
X:$F101 ............................................................................................67
X:$F100 ............................................................................................66
X:$F141 ............................................................................................67
X:$F140 ............................................................................................66
X:$F181 ............................................................................................67
X:$F180 ............................................................................................66
X:$F1C1 ...........................................................................................67
X:$F1C0 ...........................................................................................66
X:$F201 ............................................................................................38
X:$F200 ............................................................................................39
X:$F20B ...........................................................................................37
X:$F202 ............................................................................................38
X:$F203 ............................................................................................38
X:$F204 ............................................................................................38
X:$F205 ............................................................................................38
X:$F206 ............................................................................................38
X:$F207 ............................................................................................38
X:$F208 ............................................................................................38
X:$F209 ............................................................................................38
X:$F20A ...........................................................................................37
X:$F502 ............................................................................................84
X:$F503 ............................................................................................84
179

STMP3410

Transcription

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