Challenges of Modeling VLSI Interconnects in the DSM Era

Transcription

Challenges of Modeling VLSI
Interconnects in the DSM Era
Narain Arora
[email protected]
Narain Arora
Simplex Solutions, Inc
1
Outline
• Interconnect – an overview
• Technology scaling
• Methods of modeling interconnect R, L and C
• Field Solver Approach
• Examples for C-extraction
• Examples for R-extraction
• Full-chip approach
• Silicon Validation
• Model order reduction
• Conclusion
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1
An Overview
•
•
•
Interconnections are used to connect devices on a chip. In
fact interconnections defines all the operations to be
performed by a chip.
B
Interconnection is a medium through
A
which signal propagates from point A
C
to reach other points, such as B and C.
For signal frequencies of interest (few GHz) the only mode
of propagation is TEM, and is well approximated
L
R
C
L
R
G
Section 1
G
C
Section N
• An interconnect is characterized by three elements
Resistance R, Capacitance C, Inductance L
known as interconnect parasitic elements.
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VLSI Interconnections - 1
• The three electrical parameters R, C, L of an interconnection
are always present, but not all of them are equally important,
depends upon
–
Length of the line, longer the line, the more important all three types of
parasitic elements will be.
–
S i g n a l r i s e t i m e t r, d r i v e r i m p e d a n c e Z s , a n d l i n e i m p e d a n c e Z 0.
Rs
Zo
V out
1
0
V out
1.0
V out
Rs >Zo
Rs <Zo
td
1.0
td
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tr
t
td tr
t
ts
4
2
Technology Trends
§ During the last two decades MOS transistors have been
systematically scaled down in dimensions in order to
achieve
§ Higher performance
§ Increased circuit density
Delay (ps)
§ So has the interconnects
45
40
35
Speed / Performance - Gate vs interconnect
Ca
Interconnect Delay
Al + SiO2
30
25
20
Gate Delay
15
10
5
0
3 micron
0.65 0.5
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0.35
Interconnect
Interconnect
dominates
dominates
gate
gate delay
delay
0.25 0.18
0.18
0.3 micron
Clt
Substrate
Substrate
Model LPE
Total Capacitance
Ca
Lateral Clt
Overlap
Ca
Cfr Fringe
Substrate
Ct=Ca+Cf+Clt
Interconnect Delay
Cu + low-k
0.13 0.10 µ
Understanding interconnect
is critical for chip design
Source: SIA Roadmap 1997
5
Interconnect Scaling - 1
•
Scaling device dimensions aggressively to below 0.25 µ m
though resulted in many advantages it also resulted in
significant degradation in interconnect related circuit
parameters
1.
Propagation delays (Timing)-- wire R, C and L
2.
Cross-talk effects (Signal Integrity) -- False switching due to Cc , L
3.
Clock skew (Signal Integrity) - wire R, C and L
4.
Electromigration effect (Reliability) - wire R, C
5.
IR Voltage Drop (Reliability) - wire R, C
6.
Power Consumption (Reliability)- wire C
Which in fact are chip design issues.
Clearly, knowledge of an accurate R, C and L of
interconnects at the chip level is very important.
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3
State of the art VLSI chip interconnections are
Global Line
1. Multilevel
§
Higher packing densities
due to shorter device dimension
Larger chip area
Higher clock frequency
§
§
2. Multilayer
§
via
M2
M1
Local Line
silicon
Reduce electromigration
ρ=3.7x 10-6 Ω.cm
effect
Al +
0.5% Cu
3. Multidielectric
§
§
§
M4
ILD
ρ=2.2x 10-6 Ω.cm
ARC
(Alloy of Ti)
Cladding layer
( TaN)
lines are getting closer and narrower
number of levels are increasing
Low K
ε3
( ε=2-3.2 )
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ε1
Cu
SiN3
M3
ε2
M2
M1
7
Embedded Low-k Dielectrics
Why embedded low-k (e~ 2 - 3.2) dielectric only between metal lines ?
SiO2
(ε
ε ~4.2 )
•
MET
Low K
MET
V
I
A
SiO2
(ε
ε ~4.2 )
V
I
A
MET
Low K
MET
•
•
•
Mechanical strength
CMP compatibility
Ease of integration and cost
Thermal conductivity
Passivation layer
SiO2
(ε
ε ~4.2)
Conformal dielectric
These dielectrics could be planar or Conformal
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4
A typical 0.13µm process
•
T0,T1,T2,T3,T4,T5 -- Dielectrics Thickness corresponding to dielectric values of E0,E1, E2 etc
•
M1,M2,M3 are metal Thickness, while W and S1 are width and spacing
M3
T4
E4
E3
T5, E5
S1
T3
S1
M2
E6
w
E2
T2
E1
T1
M1
E0
T0
ground
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M1=0.26
M2=0.35
M3=0.35
T0=0.95
T1=0.15
T2=0.05
T3=0.37
T4=0.05
T5=0.02
E0=3.9
E1=5
E2=4.2
E3=4.2
E4=5
E5=7.9
W=0.2
S1=0.22
9
Metal Fills
§ To avoid dishing and erosion of the inter-level dielectrics, CMP
requires metal lines to be at a certain minimum distance from
each other (metal density). This leads to the so called metal fills
(dummy metal) - floating metal lines
Metal fill
Signal Lines
§ Dummy metals are of different shape and size.
§ Impact of metal fills is to increase line capacitance by 3-10%
depending upon shape, size and proximity of the fills to the line.
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5
Copper Process
• Cu wire dimensions are not as drawn – variations from
drawn are much more significant than aluminum
Dishing and Erosion effects
•
•
•
•
Wire erosion
Wire width variation
Resistance variation
Wire shape
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Drawn
Manufactured
Function of wire
width, spacing,
thickness and wire
density
11
Trapezoidal Wire Shape not New
• Scanning Electron Microscope Picture from Cosmic
Testchip 0.18um Aluminum and 0.13um Copper
– Accuracy has been validated with Raphael and in Silicon by
taking average width (TSMC 0.13um)
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6
Optimized Manhattan Routing
Preferred direction
with optimization
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Benefits From X Architecture
20+% less interconnect
30+% less vias
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10% performance gain AND
20% power reduction AND
30% cost savings
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7
Chip Level R, C Extraction - 1
• Computation of R, C and L for a densely packed
multiconductor system such as that of a VLSI circuit is
complex and difficult task.
• The software tool that computes the R,C, L of a chip
interconnections is called Parasitic Extractor, also known
as circuit level extractor, LPE, etc.
• Numerical methods, the so called Field Solvers:
– provides accurate em field solutions for complex geometry.
– allows the modeling of non-linear, inhomogeneous and
anisotropic materials. .
– too compute intensive and cannot be applied at the chip level R,
L and C extraction. In fact they are not practical for circuits
containing larger than few tens of transistors.
• Empirical models are not accurate enough, particularly
for estimating 2-D and 3-D coupling capacitances.
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Methods of modeling R, L, C
• Numerical or Field solver approach uses Maxwell’s
Electromagnetic field equations
Ampere’s theorem
curlH = J +
div D = ρ
∂D
∂t
Faraday’s law
curlE = −
∂B
∂t
div B = 0
Constitutive equations
B = µ H, D = ε E, J = σ E
To be solved with initial and boundary conditions
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8
Numerical computation of EM field
Physical equations
choice of working variables
field quantities, potentials, ...
Partial differential equations
choice of numerical technique
FEM, FDM, BEM, ...
Algebraic equations
iterative, direct,
multigrid, ...
choice of matrix solver
Solutions
post-processor
discretization of domain by
elements of simple shape
MESH
approximation of unknown
functionby simple functions
(polynomials)
BASIS
interpolation, integration, visualization ...
Filed distribution, circuit parameters
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Comparison of different methods
Method
Advantages
Analytic
Integral
(BEM, Method
of moments, Green
Function)
FD
FE
MC
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Very fast
Fast solutions for Q and E. No
need to specify outer
boundary.
Moderately fast solution with
good economy of memory.
Mesh is rectangular and
normally equally spaced. E
are cheap to compute from
potentials.
Disadvantages
Examples
Only deals with simple shapes
A full matrix is produced for the
solution phase requiring more
computer memory than FE
method with same mesh size.
Difficult for inhomogeneous material
Difficult to represent complex
geometries unless fine mesh is
Specified. Outer boundary must
be specified.
Mesh can be designed to fit
matrix permits fast solution
Complex geometries. Sparse
with economy of core. Handle
Inhomogenous and nonlinear sys.
Outer boundaries must be
specified. Good for any geometry.
Fast potential solution
No Mesh – stochastic Approach
Field evaluation is very slow.
Performance on mesh quality
Raphael (Avant!)
Fastcap (MIT)
UA3D (U. Arizona)
Raphael (Avant!)
GEMI3D (Celestry)
Maxwell (Ansoft)
Metal (OEA Int)
SAP (U. Vienna)
QuickCap (RLCorp)
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9
Example (via structure)
net 1
FEM
net 2
net 1
FDM
net 2
net 1
QCAP
net 2
unknowns
26,322
111,456
time (s)
26
258
net 2
160
C (fF)
2.100
1.000
2.093
0.979
error (%)
0.50
1.34
0.16
-0.84
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net 1
2.090
0.987
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Example (3 by 3 cross)
FEM
straight
Extraction net
Unknowns 277,086
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FDM
45º
straight
232,596
147,825
QCAP
straight
45º
time (s)
325
258
332
60
180
C (fF)
3.697
3.779
3.726
3.690
3.686
errors (%)
0.19
2.52
0.99
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10
Interconnect Resistance (R) - 1
• Resistance of a rectangular conductor is given by:
• To obtain resistance R of a wire,
simply multiply ρs , by the ratio
of length-to-width of the wire.
• Remember, resistance is a function of conductor
geometry and conductivity only.
• Due to the interconnects being multilayer, Ρ σσ
sheet resistance of a wire now becomes
function of width of the line. The lower the
width, the higher the resistance.
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W
21
Slotting Experimental Results
Simplex Field Solver Results
Resistance
w/ no slots
Results
with slots
(Ω)
(Ω)
Difference
No Slots vs
Slots
(%)
0.1569
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0.1569
0
0.1781
13.51
0.2340
49.14
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Resistance (R) - Skin effect
• As signal frequency increases, penetration depth (skin depth,
δ] of the em field into the conductor decreases
1
πfµσ
• thereby increasing conductor R.
Skin Depth (microns)
δ=
4
3.5
3
2.5
2
1.5
1
0.5
0
Al
Cu
0
2
4
6
8
10
Frequency (GHz)
At 1 GHz , δ for Al is 2.8µm,
Contains Bessel functions and
its derivatives.
maximum impact on clocks and grids
Modeling wire R with Skin depth is not straight forward.
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Interconnect Capacitance (C) - 1
• Fundamental expression for the computation of
interconnect capacitance is the parallel plate formula
C=ε .Wl /H
(1)
where ε is dielectric constant of the surrounding medium
between the plates, W is the width and H is the spacing
between the plates (one of the plates could be a ground
plane). (1) is applicable under the assumptions that
- T negligible and W >> H.
• This 1D parallel plate formula (1) has been
successfully used in the past for calculating
T
interconnect capacitances before dimensions H
became small that fringing capacitance is no
longer negligible.
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l
W
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12
Interconnect Capacitance (C) - 2
W
1
C12
C11
S
2
C13
3
C23
C22
C33
F
/
m
• Due to finite T and W of the line, with
dimensions comparable to ILD, fringe
capacitance is significant. It is customary l
T
to define 3 different components
(1) overlap, (2) lateral, and (3) fringe.
H
Though these capacitances are treated
separately, such distinctions are artificial.150
• 2D model assumes long lengths
100
• Physically speaking capacitance
is a 3D electromagnetic problem.
50
• Total capacitance of conductor 2
00
C2t = C 12 + C 23 + C 22
(
]p
C2t
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Cpp
C2 2
C1 2
2
3
4
Space and width (µm)
5
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Interconnect Inductance -1
Inductance calculation of a wire is complicated:
• inductance, by definition, is for a loop of a wire (wider
the current loop, higher the inductance).
• inductance of a wire in an IC requires knowledge of
return path(s) - the Vss or Vdd closes loop for each piece of
interconnection.
• Often return path is not easily identified, particularly at
layout stage as it is not necessarily through the silicon
substrate. If return path is known, L calculation using
Maxwell’s equation is straight forward
J
jω µ
+
σ
4π
∫
v
J (r ' )
dr' = V
r − r'
• Knowing I, L is calculated using Φ / I
• Silicon substrate is treated as having finite thickness and
resistivity.
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13
Inductive effects
§ With increasing clock frequency, decreasing rise time
(BW ~ 0.35 /Τ
Τ r ) and decreasing resistance due to wide
and thick wires (top levels) and use of copper,
Z = R + jω
ωL
inductive effects have become increasingly
significant, particularly on clocks/busses:
– Ringing and overshoot - problematic for clocks since
glitches can be observed as transitions leading to faulty
switching
– Reflections of signals due to impedance mismatch
di
– Switching noise due to L d t voltage drops - problematic for
power distribution network.
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Interconnect Inductance - 2
• On chip it is not clear which conductor forms the loop.
Concept of partial inductance is introduced which allows
algebra to take care of determining the loops (A.E. Ruehli.
IBM J. Res. Dev. 16, pp 470-481, 1972)
• Each partial inductance assumes current return at infinity.
• The “infinity return” parts cancel out when we do the
subtraction.
• This is equivalent to calculating the flux linkage.
• Based on PI approach, one can easily calculate self and
mutual inductance of two parallel lines of length l, width w,
thickness t, separated by distance d
L
M
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µ 0 l
2 π 
µ 0l 
ln
2 π 
=
self
=
. ln 

 2l
 d

2l
 + l
w + t 
2

 d 
 − 1 +  l 



+ 0 . 2235

(w + t) 




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14
Comparison of L, C
•
•
For 3x3 lines on silicon substrate
(w = 5 µm,
s = 5 µm, t = 1.0 µm , l = 1000µm
•
Inductance matrix
0.401 0.07 3 0.023
0.073 0.401 0.073
0.023 0.073
0.401
•
•
Capacitance matrix
32.4
-6.7
-0.93
-6.7
34.15 -0.93
-0.93
-6.7
32.4
nH
Unlike capacitve coupling, inductive
coupling is much stronger (has long
range effects). As such localized
windowing is not easy. Challenge is
how far to go ?
a
fF
c
b
T
S
W
H
Silicon substrate
Inductance results in many high frequency poles and zeros, making
reduced order Model Approximation difficult.
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Comparison of L, C - 2
• Capacitance per unit length is constant for wire length
approximately > 10 µm.
• Inductance of a wire is not scalable with length.
• Wire capacitance is important for any length, while
Length (cm)
wire inductance is
10.00
1. Inductance is not important
t
significant only
because of high attenuation. l > 2 LC
1&2
for certain range of
1.00
Inductance
is important
2 L
wire length.
l<
R C
0.10
2. Inductance is not important
• Inductance is reduced
because of the large transition
time of the input signal.
by design using metal
0.01
plane or intedigitated shield.
0.01
0.10
1.00
10.00
r
Transition Time (ns)
[After Ismail et al. DAC 1998 p. 560]
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15
Chip Level Extraction -1
• Different modeling approaches of computing R,L, C at
the chip level has resulted in different types of tools.
- Preset formulas
- Rule based - Boolean operation
- Pattern matching - use look-up table, quasi 2-D
- Context based, looks at each conductor with its
3D surrounding or “halo” region. Analytical models that
are parameterized as a function of line width and spacing
are used to calculate line capacitance.
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Preset Formulas
•
Only known for simple geometries, with uniform dielectric constant,
and for fixed range of W,T and H. Well known are Sakurai formulas
(IEEE Trans. ED-30, pp 183, 1983) and Chern et al. [IEEE EDL -13, p 32, 1992].
• These formulas are based on
assumption that the conductors
a
c
b
are infinitely long, surrounded by
T
S
uniform dielectrics and have 2D
W
Cc
H
Silicon substrate
accuracy

T 
 2H 
Cc = εr 1.064 A10.695 + A10.804A12. 4148 + 0.831A20. 055

S


 2H + 0.5S 

– Capacitance calculation very quick
 T + 2H 
 W 
A1 = 
 & A2 = 

Disadvantage
 T +2 H + 0.5S 
W +0.8S 
• Advantage:
•
– In general not applicable for UDSM
– Even where applicable accuracy is limited.
– Cross-coupling difficult to get
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Pattern Matching - Quasi 2D
a
Boundary effects
ignored
Matched in design
2D+2D (Quasi 3D) vs. 3D Accuracy
70
1.2
60
1
50
Error
0.8
40
0.6
30
0.4
20
3D
0.2
10
Quasi 3D
0
0
2
1.5
1
0.5
0
Wire width ÷ thickness
2D+2D or Quasi 3D
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Capacitance
Pre- extracted
Prepattern
% Error
•
33
Chip Level R, C Extraction
• Procedure for chip level RC extraction: [Ref.
Arora et al., IEEE
CAD-15, p58 (1996)
Air
Nitride
Physical (Process)
Interconnect
Parameters
Oxide
Metal 2
Metal1
Silicon (Ground Plane)
3D
Field Solver
Layout
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Capacitance
Data
Optimization
3D Capacitance Models
Layout
Extractor
XTC
Capacitance
Extractor
ICE
SPICE
Circuit
Netlist
3D Analytical
Model
Parameters
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Interconnect Characterization
• Two ways of characterizing interconnects are :
1. Use the Field Solvers that are based on Maxwell’s
equations (soft validation).
#
– The average difference from 3D field solver
is a good measure. However, a better measures
standard deviation of the difference from a 3D
field solver
– Inherent assumption is that process parameters - 10%
that are input to the solver are correct (from silicon
on prospective).
0
Accuracy
+10%
2. Test chips fabricated on Silicon Wafers for a given technology,
measuring the capacitance of those structures (Silicon validation).
Though expensive and time consuming, it is the only way to do
correct model validation.
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Active Approach
• The total capacitance ,
C, of the interconnect I
is determined by measRef
A
uring the difference
I
in the dc drain
currents, Iavg, of the
two “pseudo inverters” [Chen et al. Proc. IEDM, December 1996]
Ref and A such that
C = Vdd . f / (IA - Iref) = Vdd . f / Iavg
where
f
Vdd = DC supply voltage to the inverters
= frequency of the pulses applied to the gates
• Assumption: Two pseudo inverters are matched.
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18
Advantages of Active Approach
•
Active test structures represent actual layout seen on the chip
and as such
are directly correlated with the silicon.
•
Validation of the capacitance models is more meaningful with
these structures.
•
Lower limit of the capacitance measurement is dictated by the
leakage current of the sensor circuit and matching of device
capacitances (overlap and junction) in the two switches.
•
Unlike in LCR method, here capacitance is a derived quantity,
derived from the current measurements .
•
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Results of 0.18u process - Foundry A
Test
Struc.
Measured
Cap. (fF)
ICE
(fF)
Error
ICE vs Measured
Total
A3
6.81
A4
8.25
B1
6.68
B2
9.44
B3
106.97
COUPLING
M2-M2
3.74
M5-M5
3.56
M5-M6
0.10
M2-M3
0.41
M2-M2
5.43
7.33
8.48
6.94
10.13
108.63
7.61 % [3 M5crossing]
2.74 %
3.8 %
7.31 % [M2 Bend]
1.56 % [M1-M2 plate]
3.72
3.89
0.26
0.56
5.86
0.45 %
0.84 %
160%
37%
7.9%
(3 parallel lines)
[3 parallel lines)
[3x3 crossing]
[3x3 crossing]
(3bends)
• Measured capacitances are within 8% of the ICE
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19
Statistical variation
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DSM Design
• As VLSI moving to SoC Design chip complexity is
Increasing:
§ 10-20M transistors design a common place
• 30-100M parasitics
• Parasitic database in GB range
• Typical parasitic extraction takes 24-48 hours (single CPU)
§ Increased # of designs requiring detailed signal
integrity
• Cross-coupling delay effects
• Noise problems that could cause functional failures
• Clock skew and jitter
• Power supply noise, ground bounce and substrate injection
• Inductive effects from package, power/ground rails
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20
Model Order Reduction
• To use huge parasitic data base for downstream tools for
Timing Analysis, Signal Integrity etc., data needs to be
reduced
R
R
R
R
R
R’
C
C
C
C’
C’
• Reduced model should have the following characteristics:
– Accuracy
• Preserves dc and ac characteristic
– Stability
– Passivity
– RLC synthesizability
• Spice-in / Spice-out
– Scalability
• Handling of networks with large number of ports
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Reduction Accuracy
(PRIMA) ICCAD 1997
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21
Conclusion
• Accurate characterization and
modeling of VLSI interconnects is
important because it affects chip
design through, timing, signal integrity
and reliability of the chip.
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• Because of low resistivity ( 3.7x 10-6 Ω .cm) and silicon
compatibility Al is used for interconnections and is de
facto industry standard.
• As we move towards UDSM technologies with feature
size at or below 0.18 µ m, Al being replaced by Cu
because of its 40-45% lower resistance compared to Al.
After Edelstein et al. IBM J
R&D 39, 384 1995
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22
Distributed RC
• Due to the distributed nature of R, C and L, the RCL
segments are described by partial differential equations,
rather than the ordinary differential equations that
characterize lumped circuit elements. For the case of RC
R, C
Distributed
• Combining above equations
• Solution of this equation is
• there is no closed form time-domain solution for this
function due to infinite order series.
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Distributed RC
• For circuit modeling we replace these distributed
elements into series of lumped elements. This way we
convert infinte order system into finite order system.
R
R
Lumped
C
2R
C
R
R
R
C
C
• Lumping of the elements depends upon signal
frequencies of interest.
Vout
Distributed
1.0
Response of distributed vs lumped
Lumped
0.5
time
0.5RC
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1.0RC
1.5RC
2.0RC
2.5RC
46
23
Capacitance of Crossing Lines
•
An example of multilevel interconnections for a
RISC chip is shown in the following figure
• 90% of the interconnections in a chip are parallel
crossing lines with 3D effect.
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Comparison: Active Vs. Passive
Example - 0.35 µ m technology
• Passive - comb structure, line to ground capacitance,
per finger = 3.48 fF
• Active - single line, capacitance to ground = 5.14 fF
ERROR = 47%
• Passive - interleaved comb structure, line coupling
capacitance = 4.81 fF
• Active - coupling capacitance between two lines = 3.41 fF
ERROR = 41%
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Statistical Modeling
• Statistical models are developed for all 3 types of
capacitance - area, lateral and fringe.
2
2
2
 ∂C
 ∂C 
 ∂C
2
 σ 2+
 σT 2 + 
 σp
 ∂H H
 ∂T 
 ∂p 
Var ( C) ≅ 
The 3σ-
capacitance is therefore
C3σ
=
Cnom ± (3 Var(C ) )
• These models are function of total percentage variation in
ILD and DW variations.
• Any percentage ILD and DW variation could be specified.
• Statistical variation of both coupling and total capacitance
of a net could be obtained.
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Process variations
• Due to manufacturing tolerances, interconnect related
process variations
•
•
•
•
Interlevel dielectric thickness (H)
Metal width (W) and thickness (T)
Dielectric uniformity
Line sheet resistivity
• Parameters change from die-to-die, wafer-to-wafer, lot-tolot resulting in R, and C which could be 20% of the typical
value.
• Geometry specific variations
• In circuit design one normally should use worst case
value (maximum W and thinnest H) for delay and
dynamic power calculations, while for race calculations
minimum W and maximum H be used.
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25
2nd Generation
• Projection based methods
– Arnoldi-based algorithm
Ø trade-off accuracy for stability/passivity
•
•
•
•
Silveira: Arnoldi based method DAC 1995
Silveira: Coordinate-Transformed Arnoldi ICCAD 1996
Elfaded: Passive Arnoldi DAC 1997
Odabasioglu: Passive Reduced-order Interconnect
Macromodeling Algorithm (PRIMA) ICCAD 1997
– Congruency Transformation
• Kerns:Pole Analysis via Congruency Transformation (PACT)
DAC 1996
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Future
• Model-order reduction capturing manufacturing
variation
– Liu, Pileggi, Strojwas: “Model Order-Reduction of
RC(L) Interconnect including Variational Analysis” DAC
1999
• Extension of PACT and PRIMA
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26
Case of electrostatic field
(C-extraction)
Γe
ε
Ω
Physical
equations
curl E = 0
div D = 0
D=εE
P.D.E.
div ε grad v = 0
Algebraic
equation
Mv=S
ε0
σ
Γe
Γd
Working variable: E = grad v
v: electric scalar potential
(Dirichlet)
(Neumann)
Γe : v = const
Γd : ∂v/ ∂n = 0
Discretization
Matrix inversion
Solutions
v
Postprocessor
Interpolation, integration
E, D, We, Q, C
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Context-based Approach
• Context-based extractors look at each conductor with its 3D
surroundings and store the polygons in a geographical data
structures. [Ref. Arora et al., IEEE CAD-15, p58 (1996)
• Nine capacitance between M1 and M1, which shows
distributed nature of the interconnect.
M4
9 areas M1
4
profiles
A1
B1
A3
C
D
C
A 2 B2
A4
CL
M1
M3
•
M3
M1
C
B D
A
Methodology is independent of design style and scales with technology.
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27
Accuracy Comparison - 1
• There are many claims to accuracy for a parasitic
extractor. Based on interconnect characteristics
following points MUST be considered while evaluating
an extractor:
– Extractor should provide not just the lump R,L, C , but its
distributed nature between two nodes.
– It must provide coupling C, and L between different nets.
– Extractor should be independent of design style, i.e. should not
be tuned for different chip designs.
– It should scale with technology. That is it should work as good
for 0.25u technology with few metal levels as with 0.13u
technology with higher number of metal levels.
– should be capable of generating min and max capacitance due
to process changes (statistical variation), without much
overhead on performance.
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Passive test chips
• To date the most commonly used test structures that are
fabricated on a Silicon Wafer, for characterizing
interconnects, are the so called, passive structures, of
the following type
ILD
• parallel plate over a parallel plate
• parallel plate over fingers
• fingers over a parallel plate
• interdigited fingers
• interdigited fingers over a plate
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Model Order Reduction -1st
Generation
• Required characteristic of model reduction algorithm
– Numerical stable
– Efficient
• O(n)
• Asymptotic Waveform Evaluation (AWE) is a technique
for generating “reduced order” transfer function models for
RLC circuits
• The model order reduction is performed via “Moment
∞
Matching”.
H(s) = ∫ h(t ).e− st dt = m0 + m1 s + m2 s2 + m3 s3 + ...
0
• The Elmore delay is a first order AWE approximation.
• For a second order model we match 4 moments (2 p’s
and 2 K’s) which is what Ist generation MOR algorithims
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2nd Generation
• Approximation based algorithms
– S-parameter based method
• Liao/Dai ICCAD 1995
– TIme Constant Equilibration Reduction (TICER)
• Sheehan ICCAD 1999
• Moment Matching
– Pade approximation based methods
• Freund: Pade Via Lanczos (PVL) Tr. CAD 1994
– Matrix Pade Via a Lanczos-type process (MPVL) Tr. CAD 1995
– SyPVL, SyMPVL
– Nodal Equation based
• Sheehan: Efficient Nodal Order Reduction (ENOR) DAC 1999
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Impact of Coupling on delay
• Driver of line 2 sees effective capacitance of C 2 which
may vary between C 22 and C 22+2C12+2C23. Thus delay of
2 depends on switching of 1 and 3.
1
C2
 C 22
 C 22 ++
 C
+
22 +
== 
C 22 ++

 C 22 ++
 ...
Narain Arora
C12
2
C22

C23
3
1,3 switching same direction
2C 12 ++ 2 C 23 

2C 23
1,3 switching opp. direction
C 12
3 same dir., 1 not switching
C 12 ++ C 23




3 opp. dir, 1 same dir.
1,3 not switching
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30

Challenges of Modeling VLSI Interconnects in the DSM Era

Transcription

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