interactive
Transcription
interactive
VISHAY INTERTECHNO L O G Y , INC . INTERACTIVE data book infrared data communication vishay semiconductors vse-db2802-0610 Notes: 1.To navigate: a) Click on the Vishay logo on any datasheet to go to the Contents page for that section. Click on the Vishay logo on any Contents page to go to the main Table of Contents page. b) Click on the products within the Table of Contents to go directly to the datasheet. c) Use the scroll or page up/page down functions. d) Use the Adobe ® Acrobat ® page function in the browser bar. 2.To search the text of the catalog use the Adobe ® Acrobat ® search function. One of the World’s Largest Manufacturers of Discrete Semiconductors and Passive Components V I S H AY I N T E R T E C H N O L O G Y, I N C . DATA B O O K Infrared data communication vishay semiconductors Tr a n s c e i v e r s Encoders/Decoders w w w. v i s h a y. c o m SEMICONDUCTORS RECTIFIERS RF TRANSISTORS Bipolar Transistors (AF and RF) Dual Gate MOSFETs MOSMICs® Schottky (single, dual) Standard, Fast, and Ultra-Fast Recovery (single, dual) Bridge Superectifier® Sinterglass Avalanche Diodes SMALL-SIGNAL DIODES P rod u ct L istings Schottky and Switching (single, dual) Tuner/Capacitance (single, dual) Bandswitching PIN OPTOELECTRONICS IR Emitters and Detectors, and IR Receiver Modules Optocouplers and Solid-State Relays Optical Sensors LEDs and 7-Segment Displays Infrared Data Transceiver Modules Custom Products ZENER AND SUPPRESSOR DIODES ICs Zener (single, dual) TVS (TransZorb®, Automotive, ESD, Arrays) MOSFETs Power MOSFETs JFETs Power ICs Analog Switches DC/DC Converters RF Transceivers ICs for Optoelectronics Passive Components RESISTIVE PRODUCTS CAPACITORS Foil Resistors Film Resistors Metal Film Resistors Thin Film Resistors Thick Film Resistors Metal Oxide Film Resistors Carbon Film Resistors Wirewound Resistors Power Metal Strip® Resistors Chip Fuses Variable Resistors Cermet Variable Resistors Wirewound Variable Resistors Conductive Plastic Variable Resistors Networks/Arrays Non-linear Resistors NTC Thermistors PTC Thermistors Varistors Tantalum Capacitors Molded Chip Tantalum Capacitors Coated Chip Tantalum Capacitors Solid Through-Hole Tantalum Capacitors Wet Tantalum Capacitors Ceramic Capacitors Multilayer Chip Capacitors Disc Capacitors Film Capacitors Power Capacitors Heavy-Current Capacitors Aluminum Capacitors Silicon RF Capacitors MAGNETICS Inductors Transformers STRAIN GAGE TRANSDUCERS and stress analysis systems PhotoStress® Strain Gages Load Cells Force Transducers Instruments Weighing Systems IR Transceivers Databook Vishay Semiconductor GmbH P.O.B. 3535, D-74025 Heilbronn Germany Telephone: + 49 (0)7131 67 2831 Fax number: + 49 (0)7131 67 2423 www.vishay.com NOTICE Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. OZONE DEPLETING SUBSTANCES POLICY STATEMENT It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. Table of Contents Vishay Semiconductors Alphanumeric Index .............................................................................................................................................. 4 Selection Guide ...................................................................................................................................................... 5 General Information Infrared Data Communication According to IrDA® Standard, Part 1: Physical Layer............................................ Infrared Data Communication According to IrDA® Standard, Part 2: Protocol...................................................... Symbols and Terminology ..................................................................................................................................... Data Sheet Structure ............................................................................................................................................. Taping, Labeling, Storage, Packing and Marking.................................................................................................. Environmental Health and Safety Policy ............................................................................................................... Surface Mount Assembly Instructions ................................................................................................................... Window Size in Housings ...................................................................................................................................... Sources for Accessories and Testing .................................................................................................................... Ambient Light and Electromagnetic Interference .................................................................................................. Eye Safety of Diode Emitters ................................................................................................................................ Remote Control with IrDA® Transceivers .............................................................................................................. Interface Circuits ................................................................................................................................................... Reference Layouts and Circuit Diagrams.............................................................................................................. Quality and Reliability ............................................................................................................................................ 8 21 31 41 42 52 53 58 60 66 68 69 80 87 96 SIR TFBS4650 ............................................................................................................................................................. TFBS4652 ............................................................................................................................................................. TFBS4710 ............................................................................................................................................................. TFBS4711 ............................................................................................................................................................. TFDU4100 ............................................................................................................................................................. TFDU4101 ............................................................................................................................................................. TFDU4202 ............................................................................................................................................................. TFDU4203 ............................................................................................................................................................. TFDU4300 ............................................................................................................................................................. 120 131 142 151 160 171 185 194 204 MIR TFBS5700 ............................................................................................................................................................. TFBS5711 ............................................................................................................................................................. TFDU5307 ............................................................................................................................................................. 218 230 242 FIR TFBS6711 ............................................................................................................................................................. TFBS6712 ............................................................................................................................................................. TFDU6102 ............................................................................................................................................................. TFDU6103 ............................................................................................................................................................. TFDU6300 ............................................................................................................................................................. TFDU6301 ............................................................................................................................................................. TFBS6614 ............................................................................................................................................................. 258 270 282 295 308 321 334 FIR with RC Receiver TFDU7100 ............................................................................................................................................................. 346 VFIR TFDU8108 ............................................................................................................................................................. 360 Emitter/Detector Pair TFDU2201 ............................................................................................................................................................. 384 Endec TOIM4232 ............................................................................................................................................................. 392 www.vishay.com 3 Alphanumeric Index Vishay Semiconductors TFBS4650.............................................................................................................................................................. 120 TFBS4652.............................................................................................................................................................. 131 TFBS4710.............................................................................................................................................................. 142 TFBS4711.............................................................................................................................................................. 151 TFBS5700.............................................................................................................................................................. 218 TFBS5711.............................................................................................................................................................. 230 TFBS6614.............................................................................................................................................................. 334 TFBS6711.............................................................................................................................................................. 258 TFBS6712.............................................................................................................................................................. 270 TFDU2201 ............................................................................................................................................................. 384 TFDU4100 ............................................................................................................................................................. 160 TFDU4101 ............................................................................................................................................................. 171 TFDU4202 ............................................................................................................................................................. 185 TFDU4203 ............................................................................................................................................................. 194 TFDU4300 ............................................................................................................................................................. 204 TFDU5307 ............................................................................................................................................................. 242 TFDU6102 ............................................................................................................................................................. 282 TFDU6103 ............................................................................................................................................................. 295 TFDU6300 ............................................................................................................................................................. 308 TFDU6301 ............................................................................................................................................................. 321 TFDU7100 ............................................................................................................................................................. 346 TFDU8108.............................................................................................................................................................. 360 TOIM4232.............................................................................................................................................................. 392 www.vishay.com 4 Selection Guide Vishay Semiconductors Type Size Operating Link Distance (H x L x W) Voltage VCC (m) (mm x mm x mm) (V) Idle Supply Current (mA) Shutdown Current (μA) Pins Pad Pitch (mm) I/O Voltage TXD (V) Echo Data Rate: SIR 9.6 kbit/s to 115.2 kbit/s TFBS4650 1.6 x 6.8 x 2.8 0 to t 0.3 2.4 to 3.6 0.08 0.01 7 0.95 VCC on TFBS4652 1.6 x 6.8 x 2.8 0 to t 0.3 2.4 to 3.6 0.08 0.01 7 0.95 t 1.5 on TFBS4710 2.7 x 8.0 x 3.3 0 to t 1.0 2.4 to 5.5 0.07 0.01 6 1.55 VCC off TFBS4711 1.9 x 6.0 x 3.1 0 to t 0.5 2.7 to 5.5 0.08 0.01 6 0.95 VCC off TFDU4100 4.0 x 9.7 x 4.7 0 to t 1.0 2.7 to 5.5 1 no SD 8 1 VCC x TFDU4101 4.0 x 9.7 x 4.7 0 to t 1.0 2.7 to 5.5 1 0.01 8 1 VCC on TFDU4202 2.8 x 7.3 x 4.7 0 to t 0.7 2.4 to 5.5 0.06 no SD 8 0.8 VCC off TFDU4203 2.8 x 7.3 x 4.7 0 to t 0.7 2.4 to 5.5 0.06 0.02 8 0.8 VCC off TFDU4300 2.5 x 8.3 x 3.1 0 to t 0.7 2.4 to 5.5 0.08 0.01 8 0.95 t 1.5 off Data Rate: SIR 9.6 kbit/s to MIR 1.152 Mbit/s TFBS5700 1.6 x 6.8 x 2.8 0 to t 0.5 2.7 to 3.6 0.55 0.01 6 0.95 1.8 on TFBS5711 1.9 x 6.0 x 3.1 0 to t 0.5 2.7 to 5.5 0.55 0.1 6 0.95 VCC off TFDU5307 2.5 x 8.3 x 3.1 0 to t 0.7 2.7 to 5.5 0.55 0.01 8 0.95 t 1.5 on Data Rate: SIR 9.6 kbit/s to FIR 4 Mbit/s TFBS6614 2.7 x 8.0 x 3.0 0 to t 0.7 2.7 to 5.5 1.6 0.01 8 0.95 t 1.5 on TFBS6711 1.9 x 6.0 x 3.1 0 to t 0.5 2.4 to 3.6 1.7 0.01 6 0.95 VCC on TFBS6712 1.9 x 6.0 x 3.1 0 to t 0.5 2.4 to 3.6 1.7 0.01 6 0.95 1.8 on TFDU6102 4.0 x 9.7 x 4.7 0 to t 1.0 2.7 to 5.5 1.6 < 1.0 8 1 VCC on TFDU6103 4.0 x 9.7 x 4.7 0 to t 1.0 2.7 to 5.5 1.6 < 1.0 8 1 1.8 on TFDU6300 2.5 x 8.3 x 3.1 0 to t 0.7 2.4 to 3.6 1.7 0.01 8 0.95 VCC on TFDU6301 2.5 x 8.3 x 3.1 0 to t 0.7 2.4 to 3.6 1.7 0.01 8 0.95 1.8 on Data Rate: SIR 9.6 kbit/s to FIR 4 Mbit/s and 36 kHz to 38 kHz Carrier Remote Control Receiver TFDU7100 4.0 x 9.7 x 4.7 2.7 to 5.5 5 2 mA (RC active) 8 1 VCC on 0 to t 0.7 2.7 to 5.5 3 0.01 8 1 t 1.8 on n.a. 2.4 to 5.5 n.a. n.a. 8 0.8 n.a. yes n.a. 2.7 to 3.6 2 1 16 VCC n.a. 0 to t 0.5 Data Rate: SIR 9.6 kbit/s to VFIR 16 Mbit/s TFDU8108 4.0 x 9.7 x 4.7 Emitter/Decoder pair any data rate TFDU2201 2.8 x 7.3 x 4.7 SIR Encoder/Decoder TOIM4232 2.7 x 10.3 x 10.4 Document Number 81368 Rev. 1.0, 04-Jul-06 www.vishay.com 5 Vishay Semiconductors www.vishay.com 6 Contents Infrared Data Communication According to IrDA® Standard, Part 1: Physical Layer .............. 8 Infrared Data Communication According to IrDA® Standard, Part 2: Protocol ........................21 General Information Symbols and Terminology........ 31 Data Sheet Structure ............... 41 Taping, Labeling, Storage, Packing and Marking ............... 42 Environmental Health and Safety Information.................... 52 Surface Mount Assembly Instructions .............................. 53 Window Size in Housings ........ 58 Sources for Accessories and Testing ..................................... 60 Ambient Light and Electromagnetic Interference.............................. 66 Eye Safety of Diode Emitters.................................... 68 Remote Control with IrDA® Transceivers ............................ 69 Interface Circuits...................... 80 Reference Layouts and Circuit Diagrams ................................. 87 Quality and Reliabilty ............... 96 IRDC, Part 1: Physical Layer Vishay Semiconductors Infrared Data Communication According to IrDA® Standard Part 1: Physical Layer What is IrDA? IrDA is the abbreviation for the Infrared Data Association, a non-profit organization for setting standards in IR serial computer connections. The following is an original excerpt from the IrDA Web site (http://www.irda.org). Executive Summary IrDA was established in 1993 to set and support hardware and software standards which create infrared communications links. The Association's charter is to create an interoperable, low-cost, low-power, halfduplex, serial data interconnection standard that supports a walk-up, point-to-point user model that is adaptable to a wide range of applications and devices. IrDA standards support a broad range of computing, communications, and consumer devices. International in scope, IrDA is a non-profit corporation headquartered in Walnut Creek, California, and led by a Board of Directors which represents voting membership worldwide. As a leading high technology standards association, IrDA is committed to developing and promoting infrared standards for the hardware, software, systems, components, peripherals, communications, and consumer markets. Industry Overview Infrared (IR) communications is based on technology which is similar to the remote control devices such as TV and entertainment remote controls used in most homes today. IR offers a convenient, inexpensive and reliable way to connect computer and peripheral devices without the use of cables. IrDA connectivity is being incorporated into most notebook PCs to bring the most cost-effective and easy to use support available for wireless technologies. There are few US, European or other international regulatory constraints. Manufacturers can ship IrDA-enabled products globally without any constraints, and IrDA functional devices can be used by international travellers wherever they are, and interference problems are minimal. Standards for IR communications have been developed by IrDA. In September 1993, IrDA determined the basis for the IrDA SIR Data Link Standards. In June 1994, IrDA published the IrDA standards which www.vishay.com 8 includes Serial Infrared (SIR) Link specification, Link Access Protocol (IrLAP) specification, and Link Management Protocol (IrLMP) specification. IrDA released extensions to SIR standard including 4 Mbit/s in October 1995. The IrDA Standard Specification has been expanded to include high speed extensions of 1.152 Mbit/s and 4.0 Mbit/s. This extension will require an add-in card to retrofit existing PCs with high speed IR, and a synchronous communications controller or equivalent. In 1995, several market leaders announced or released products with IR features based on IrDA standards. These products include components, adapters, printers, PCs, PDAs, notebook computers, LAN access, and software applications. In November 1995, the Microsoft Corporation announced it had added support for IrDA connectivity to the Microsoft Windows 95 operating system, enabling low-cost wireless connectivity between Windows 95 based PCs and peripheral devices. IrDA's interoperable infrared serial data link features low power consumption with data speeds up to 4 Mbit/s, allowing a cordless 'walk-up-to' data transfer in a simple, yet compelling way. Applications are in both consumer and commercial markets with a universal data connection relevant in the use of docking and input units, printers, telephones, desktop/ laptop PCs, network nodes, ATMs, and handheld mobile peers (PDA meets PDA). Yesterday’s systems with IR capabilities such as Newton, Omnibook, Wizard and Zoomer are not easily compatible with each other or other complementary devices. IrDA is the response in which many segments of the industry have committed themselves to realizing the opportunity of a general standard providing data links which are noninterfering and interoperable. The IrDA - Standard The current IrDA physical layer standard is version 1.4 and includes all changes and add-ons up to VFIR with 16 Mbit/s. Version 1.4 replaced version 1.3 which is obsolete as are all former versions from 1.0 to 1.2. Referring to these versions currently can describe only historical steps of the IrDA - development. Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors How IrDA Transmission Works The transmission in an IrDA-compatible mode (sometimes called SIR for serial IR) uses, in the simplest case, the RS232 port, a built-in standard of all compatible PCs. With a simple interface, shortening the bit length to a maximum of 3/16 of its original length for power-saving requirements, an infrared emitting diode is driven to transmit an optical signal to the receiver. This type of transmission covers the data range up to 115.2 kbit/s which is the maximum data rate supported by standard UARTs (see figure 1). The minimum demand for transmission speed for IrDA is only 9600 bit/s. All transmissions must be started at this frequency to enable compatibility. Higher speeds are a matter of negotiation of the ports after establishing the links. Higher speeds require special interfaces which operate at 1.152 Mbit/s and use a similar pulse-shortening process as in the RS232-related mode, but with a pulse reduction to 1/4 of the original pulse length. The fastest data rate supported by IrDA is 4.0 Mbit/s (often called FIR), operating with 125-ns pulses in a 4-PPM (PPM = Pulse-Position Modulation) mode. The typical interfaces for the various modes are shown in figure 2. In the following chapter "IrDA Standard - Physical Layer", the definitions of the IrDA standard are given. Optical output power and receiver sensitivity are set to a level where a point-and-shoot activity (r15q) is sufficient for point-to-point communication, but prevents the pollution of the ambient by straying needless power. Transmission over a distance of at least 1 m is ensured. The detector front end receives the transmitted signal, re-shapes the signal and feeds it to the port. The system works in a half-duplex mode that allows only one transmission direction to be active at any given time. For frequencies up to 115.2 kbit/s, the minimum output intensity is defined with 40 mW/sr. For higher speeds, a higher output intensity of 100 W/sr minimum is used. The sensitivity thresholds are 40 mW/m2 and 100 mW/m2 for SIR and FIR respectively. The wavelength chosen for the standard is between 850 nm and 900 nm. An additional IrDA standard was generated in 1997 (voted Feb. 1998) for Control applications, the socalled IrControl standard. This standard is using the IEC1603-1 sub carrier frequency allocation with a carrier at 1500 kHz. The transmission capacity is 72 kbit/s. This system has still some compatibility problems with the SIR/FIR Document number: 82513 Rev. 1.4, 20-Sep-06 IrDA Standard. One of the disadvantages is that the detector circuitry is different from the other, baseband system. Therefore, integrating both into one application is expensive. Using IrControl and SIR/FIR in one application would imply that two IR hardware channels must be built-in. The Very Fast IR (VFIR, min. 16 Mbit/s transfer rate over more than 1 m) established in 1999. What do I need to enable IrDA Transmission? The simplest way of optical interfacing in the SIR mode is shown in figure 1. For pulse shaping and recovery, the Vishay Semiconductors device TOIM4232 is recommended. The front end including transmitter and receiver should be realized for example by the integrated transceiver module TFDU4100 or other devices of the 4000 series. The TFDU4100 can also be directly connected to Super I/Os. A transimpedance amplifier is used in the receiver for input amplification. Its output signal is fed to the comparator input, whose reference level is adjusted to efficiently suppress noise and interferences from the ambient. Additionally, the digital pulse-shaping circuit must be inserted for shortening the pulse to be emitted to 1.6 Ps (i.e., 3/16 of the bit length at 115 kbit/s) and pulse recovery of the detected signal to comply with the IrDA standard. Only the active low bits (0) are transmitted. For the high-speed mode, the TFDU6102 or other devices from the 6000 series are recommended to be operated with e.g NSC’s or SMC’s IrDA-compatible Super I/O circuits. Circuit proposals for the various modes can be found in our application section. A block diagram is shown in Figure 2. www.vishay.com 9 IRDC, Part 1: Physical Layer Vishay Semiconductors IR output Pulse shaping UART16550/ RS232 TOIM4232 Pulse recovery Transmitter 4000 series transceiver Receiver IR input 17255 Figure 1. Block diagram of one end of the overall SIR link Up to 115.2 kbit/s I/O Output driver and IRED 1.152 Mbit/s 0.576 Mbit/s IR transceiver module 4.0 Mbit/s Detector and receiver IR output Active output interface Active input interface IR output 17256 Figure 2. Block diagram of one end of the link for signaling rates up to 4.0 Mbit/s The IrDA standard documentation can be found on the IrDA web site http://www.irda.org. The documents which are public and can be downloaded are shown on the next page. The physical layer is responsible for the definition of hardware transceivers for the data transmission. The physical layer is therefore discussed in the following chapters which define the properties of the front end devices manufactured by Vishay Semiconductors. www.vishay.com 10 Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors Standards available for public access and download on www.irda.org Standards, specifications and guidelines are available under the addresses http://www.irda.org/standards/standards.asp http://www.irda.org/standards/guidelines.asp http://www.irda.org/standards/specifications.asp The following documents describe the IrDA Standards: IrDA SIR Data Specification (http://www.irda.org/standards/pubs/IrData.zip) containing IrDA Serial Infrared Physical Layer Link Specification IrPHY 1.4 (http://www.irda.org/standards/pubs/IrPHY_1p4.pdf) IrDA Serial Infrared Link Access Protocol (IrLAP) IrDA Serial Infrared Link Management Protocol (IrLMP) IrDA Tiny TP IrDA Point and Shoot Profile Test Specification Document number: 82513 Rev. 1.4, 20-Sep-06 Other available documents IrDA Financial Messaging (IrFMTM) Point and Pay Specification IrDA Financial Messaging (IrFMTM)Test Specification IrDA IrLAPFast Connect Application Note IrDA Adapter Application Profile and Test Specification IrDA Control Specification IrDA Infrared Communications Protocol (IrCOMM 1.0) IrDA Infrared Tiny Transport Protocol (IrTinyTP 1.1) IrDA Infrared LAN Access Extensions for Link Management Protocol (IrLAN 1.0) IrDA Object Exchange Protocol (OBEXTM) Ver.1.3 IrDA Object Exchange Protocol (OBEXTM) Test Specification Ver.1.0.1 IrDA Minimal IrDA Protocol Implementation (IrLite) IrDA Plug & Play Extensions to IrLMP 1.0 IrDA Infrared Mobile Communications (IrMC) IrDA Infrared Transfer Picture Specifications (IrTranP) IrDA Dongle Interface specifications IrDA Infared for Wrist Watches specification (IrWW) Serial Port Profile, IrModem Profile and Test Specs Serial Interface for Transceivers IrDA Point and Shoot IrDA Point and Shoot Application Profile IrDA Point and Shoot Test Specification www.vishay.com 11 IRDC, Part 1: Physical Layer Vishay Semiconductors IrDA-Standard - Physical Layer Specification In SIR mode, the data is represented by optical pulses between 1.6 μs and 3/16 of the bit length of the RS232 data pulse in SIR mode. Pulse-length reduction is also applied in the higher frequency modes. The limits of the standards are shown in tables 1 and 3. The optical radiant intensity and detector sensitivity are adjusted to guarantee a point-to-point transmission in a cone of r15qover a distance of at least 1 m. The radiant intensity and the sensitivity of the front end can be increased to ensure a transmission over 3 m (see figure 3). Data from the optical interface standard are documented in tables 2 to 4. Media Interface Specification Overall Links There are two different sets of transmitter/ receiver specifications. The first, referred to as Standard, is for a link which operates from 0 to at least 1 meter. The second, referred to as the Low Power Option, has a shorter operating range, and is only defined up to 115.2 kbit/s. There are three possible links (see Table 1 below): Low Power Option to Low Power Option, Standard to Low Power Option; Standard to Standard. The distance is measured between the optical reference surfaces.The Bit Error Ratio (BER) shall be no greater than 10-8. The link shall operate and meet the BER specification over its range. Signaling Rate and Pulse Duration: An IrDA serial infrared interface must operate at 9.6 kbit/s. Additional allowable rates listed below are optional. Signaling rate and pulse duration specifications are shown in table 2. For all signaling rates up to and including 115.2 kbit/s the minimum pulse duration is the same (the specification allows both a 3/16 of bit duration pulse and a minimum pulse duration for the 115.2 kbit/s signal (1.63 μs minus the 0.22 μs tolerance). The maximum pulse duration is 3/16 of the bit duration, plus the greater of the tolerance of 2.5 % of the bit duration, or 0.60 μs. For 0.576 Mbit/s and 1.152 Mbit/s, the maximum and minimum pulse durations are the nominal 25 % of the bit duration plus 5 % (tolerance) and minus 8 % (tolerance) of the bit duration. For 4.0 Mbit/s, the maximum and minimum single pulse durations are the nominal 25 % of the symbol duration plus and minus a tolerance of 2 % of the symbol duration. For 4.0 Mbit/s, the maximum and minimum double pulse durations are 50 % of the symbol plus and minus a tolerance of 2 % of the symbol duration. Double pulses may occur whenever two adjacent chips require a pulse. The link must meet the BER specification over the link length range and meet the optical pulse constraints. Low Power Low Power Link Distance Lower Limit, meters Minimum Link Distance Upper Limit, meters Standard Low Power Standard Standard 0 0 0 0.2 0.3 1.0 Table 1: Link Distance Specifications www.vishay.com 12 Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors UART Start Frame Data Bits Stop Bit 0 Bit 0 1 1 0 1 0 UART 0 1 1 Frame IR Frame Start Data Bit s Stop Bit 0 Bit 1 1 0 0 0 1 1 0 1 IR Frame Bit T ime Pulse Width = 3/16 Bit Time 17257 Signaling Rate Modulation Rate Tolerance % of Rate Pulse Duration Minimum Pulse Duration Nominal Pulse Duration Maximal 2.4 kbit/s RZI*) r 0.87 1.41 μs 78.13 μs 88.55 μs 9.6 kbit/s RZI*) r 0.87 1.41 μs 19.53 μs 22.13 μs 19.2 kbit/s RZI*) r0.87 1.41 μs 9.77 μs 11.07 μs 38.4 kbit/s RZI*) r0.87 1.41 μs 4.88 μs 5.96 μs 57.6 kbit/s RZI*) r0.87 1.41 Ps 3.26 μs 4.34 μs 115.2 kbit/s RZI*) r0.87 1.41 μs 1.63 μs 2.23 μs 0.576 Mbit/s RZI *) r0.1 295.2 ns 434.0 ns 520.8 ns 1.152 Mbit/s RZI*) r0.1 147.6 ns 217.0 ns 260.4 ns 4.0 Mbit/s Single pulse Double pulse 4 PPM 4 PPM r0.01 r0.01 115.0 ns 240.0 ns 125.0 ns 250.0 ns 135.0 ns 260.0 ns HHH (1.13) r0.01 38.3 ns 41.7 ns 45.0 ns 16 Mbit/s Table 2: Signaling rate and pulse-duration specification *) RZI = Return to Zero Inverted Document number: 82513 Rev. 1.4, 20-Sep-06 www.vishay.com 13 IRDC, Part 1: Physical Layer Vishay Semiconductors 1.6 μ s or 3 /16 NRZ ≤ 115.2 kbit/s RZ I - IR 0.576 Mbit/s 1.15 2 Mbit/s 17258 1/ 4 Bit cell 4.0 Mbit/s One complete Symbol chip 1 chip 2 chip 3 chip 4 Ct = 125 ns Dt = 500 ns 17259 www.vishay.com 14 Data Bit Pair (DBD) 4PPM Data Symbol (DD) 00 01 10 11 1000 0100 0010 0001 Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors HHH (1,13) Modulation Code for the 16-Mbit/s VFIR Standard The HHH (1, 13) modulation code has the following salient features: • Code Rate: 2/3 , • Maximal Duty Cycle: 1/3 (~ 33 %) , • Average Duty Cycle: ~ 26 % , • Minimal Duty Cycle: 1/12 (~ 8.3 %) , • Run-Length Constraints: (d, k) = (1, 13) , • Longest Run of '10' s: yyy'000'101'010'101'000'yyy , • Chip Rate at Data Rate 16 Mbit/s: 24 Mchips/s , • System Clock at Data Rate 16 Mbit/s: N × 12 MHz (where N t 4). Document number: 82513 Rev. 1.4, 20-Sep-06 The HHH(1,13) code is a Run Length Limited (RLL) code that provides both power efficiency and bandwidth efficiency at the high data rate. The signaling rate of the code is 24 Mchips/s allowing a rise and fall time of 19 ns. LED on time is further improved by having a 26 % average duty cycle for random data. The lower duty cycle is achieved by scrambling the incoming data stream. The run length constraints (d, k) = (1, 13) ensure an inactive chip after each active chip, i.e. only single-chip-width pulses occur. This feature allows a source or a receiver to exhibit a long tail property. To take full advantage of the d = 1 feature of HHH(1, 13) in strong signal conditions, clock and data recovery circuitry should be designed to ignore the level of the chip following an active chip and assume these chips are inactive. The 13 in HHH(1, 13) denominates that the maximum number of chips without a signal is 13. That limits the lower cutoff frequency of the system and optimizes threshold trigger stability in receiver designs. The modulation code is enhanced with simple framesynchronized scrambler/descrambler mechanisms as defined and described in the IrDA IrPhy 1.4 standard. While such a scheme does not eliminate worst-case duty cycle signal patterns in all specific cases, the probabilities of their occurrence are reduced significantly on average. This leads to a better "eye" opening and reduced jitter in the recovered signal stream for typical payload data. www.vishay.com 15 IRDC, Part 1: Physical Layer Vishay Semiconductors Active Output Interface The active output interface (IRLED) emits an infrared signal. Key parameters for this interface, defined by IrDA physical layer specification are shown in table 3. A complete specification is available from IrDA. Data Rates Type Minimum Peak wavelength, Op, Pm Specification All Both 0.85 0.90 Maximum intensity in angular range, mW/sr All Std - 500*) Low Power - 500*) Std 40 - Low Power 3.6 - Std 100 - Low Power 9 - All Both r 15 r 30 All Both See table 2 See table 2 - 600 - 40 115.2 kbit/s and below Minimum intensity in angular range, mW/sr Above 115.2 kbit/s Half angle, degrees Signaling rate (also called clock accuracy) Rise time tr ,10 % to 90 %, fall time tf , 90 % to 10 %, ns 115.2 kbit/s and below Both 115.2 kbit/s to 4.0 Mbit/s 16 Mbit/s Pulse duration Optical overshoot, % Maximum - 19 See table 2 All Both See table 2 All Both - 25 115.2 kbit/s and below Both - r 6.5 Edge Jitter, relative to reference clock, % of nominal duration 0.576 and 1.152 Mbit/s Both - r 2.9 Edge Jitter % of nominal chip duration 4.0 Mbit/s Both - r 4.0 16.0 Mbit/s Std - r 4.0 Edge Jitter, % of nominal pulse duration Table 3: Active output specification *)For a given transmitter implementation, the IEC 60825-1 AEL Class 1 limit may be less than this. See section 2.4 above and Appendix A. Tolerance Field of Angular Emission The optical radiant intensity is limited to a maximum of 500 mW/sr and an angle of r 30q to enable the independent operation of more than one system in a room. In figure 3, the tolerance field of an infrared transmitter's emission is shown. A typical far field characteristic of a transmitter is also shown in this figure. Radiant intensity (mW/sr) 550 500 450 400 350 IrDA tolerance field 300 250 200 Typical characteristic 150 100 (V)FIR 50 0 - 90 17260 SIR - 75 - 60 - 45 - 30 - 15 0 15 30 45 60 75 90 Angle of emission (°) Figure 3. Tolerance field of angular emission www.vishay.com 16 Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors Active Input Interface When a infrared optical signal impinges on the active input interface (PIN photodiode), the signal is detected, conditioned by the receiver circuitry, and transmitted to the IR receive decoder. Specification Data Rates Type Minimum Maximum All Both - 500 115.2 kbit/s and below Low Power 9.0 - Std 4.0 - Low Power 22.5 - Std 10.0 - All Both 15 - 4.0 kbit/s and below Std - 10 Low Power - 0.5 Both - 0.10 Maximum irradiance in angular range, mW/m2 Minimum irradiance in angular range, mW/m2 Above 115.2 kbit/s Half angle, degrees Receiver latency allowance, ms 16.0 Mbit/s Table 4: Active input specification Active Input Specification The following five specifications form a set which can be measured concurrently: Maximum irradiance in angular range, mW/m2 Minimum irradiance in angular range, mW/m2 Half-angle, degrees Bit Error Ratio, (BER) Receiver Latency Allowance, ms These measurements require an optical power source and means to measure angles and BERs. Since the optical power source must provide the specified characteristics of the Active Output, calibration and control of this source can use the same equipment as that required to measure the intensity and timing characteristics. BER measurements require some method to determine errors in the received and decoded signal. The latency test requires exercise of the node's transmitter to condition the receiver. Definitions of the reference point etc., are the same as for the Active Output Interface optical power measurements except that the test head is now an optical power source with the in-band characteristics (peak wavelength, rise and fall times, pulse duration, signaling rate and jitter) of the Active Output Interface. The optical power source must also be able to provide the maximum power levels listed in the Active Output Specifications. It is expected that the minimum levels can be attained by appropriately spacing the optical source from the reference point. Document number: 82513 Rev. 1.4, 20-Sep-06 Figure 4 illustrates the region over which the Optical High State is defined. The receiver is operated throughout this region and BER measurements are made to verify the maximum and minimum requirements. The ambient conditions of A.1 (page 20) apply during BER tests; BER measurements can be done with worst case signal patterns. Unless otherwise known, the test signal pattern should include maximum length sequences of "1"s (no light) to test noise and ambient, and maximum length sequences of "0"s (light) to test for latency and other overload conditions. Latency is tested at the Minimum Irradiance in angular Range conditions. The receiver is conditioned by the exercise of its associated transmitter. For rates up to and including 1.152 Mbit/s, the conditioning signal should include maximum length sequences of "0"s (light) permitted for this equipment. For 4.0 Mbit/s 4 PPM operation, various data strings should be used; the latency may be pattern dependent. The receiver is operated with the minimum irradiance levels and BER measurements are made after the specified latency period for this equipment to verify irradiance, half angle, BER and latency requirements. The minimum allowable intensity value is indicated by "minimum" in figure 5, since the actual specified value is dependent upon the data rate, SIR or FIR. www.vishay.com 17 IRDC, Part 1: Physical Layer Vishay Semiconductors Low Power Standard and Full Range Operation The message that a Low Power device must be a special design is often propagated, but is incorrect. Full standard devices can be operated easily with reduced IRED drive current to fulfill the low power specification. However, devices specially designed for Low Power applications with low profile package are not able to cover the full standard because of limited efficiency and little drive current capability. Irradiance (or Incidence) (W/m 2 ) (Vertical axis is not drawn to scale) 5 kW/m 2 Undefined Region Optical Undefined Region High State minimum - 30 17261 - 15 0 15 30 Angle (Degrees) Figure 4. Optical High State Acceptable Range www.vishay.com 18 Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 1: Physical Layer Vishay Semiconductors Transmission Distance From figure 5, the transmission distance as a function of the sensitivity (necessary irradiance on the detector) can be read. For example: Sensitivity given as a minimum irradiance on the detector of 40 mW/m2, combined with an intensity of 40 mW/sr, results in a transmission distance of 1 m. A combination of a detector with a minimum irradiance of 10 mW/m2 and an emitter with 250 mW/sr can transmit over almost five meters. Vishay Semiconductor transceivers work well with standard remote control receivers and can therefore be operated as remote control transmitters. The physical layer properties of the devices are defined under ambient conditions listed in an appendix which has been reprinted in the following chapters. 107 Ie = 500 mW/sr Ie = 240 mW/sr 106 Ie = 100 mW/sr Ie = 40 mW/sr 105 Irradiance (mW/m 2) IrDA FIR Standard specified sensitivity IrDA SIR Standard specified sensitivity 104 Remote Control, guaranteed sensitivity Remote Control, typical sensitivity 103 102 101 100 10-1 10-2 0.01 0.1 1 Distance (m) 10 100 17262 Figure 5. IrDA and Remote Control maximum transmission distance. For Remote Control receivers operating with IrDA transmitters a sensitivity of 0.7 mW/m2 can be assumed. Document number: 82513 Rev. 1.4, 20-Sep-06 www.vishay.com 19 IRDC, Part 1: Physical Layer Vishay Semiconductors Appendix A. Test Methods Note - A.1 is Normative unless otherwise noted. The rest of Appendix A and all of Appendix B are Informative, not Normative {i.e. it does not contain requirements, but is for information only}. Examples of measurement test circuits and calibration are provided in IrDA Serial Infrared Physical Layer Measurement Guidelines. A.1. Background Light and Electromagnetic Field There are four ambient interference conditions in which the receiver is to operate correctly. The conditions are to be applied separately: • Electromagnetic field: 3 V/m maximum (Refer to IEC 61000-4-3. test level 2 for details) (For devices that intend to connect with or operate in the vicinity of a mobile phone or pager, a field of 30 V/m with frequency ranges from 800 MHz to 690 MHz and 1.4 GHz to 2.0 GHz including 80 % amplitude modulation with a 1 kHz sine wave is recommended. Refer to IEC 61000-4-3 test level 4 for details. The 30 V/m condition is a recommendation; 3 V/m is the normative condition.) • Sunlight: 10 kilolux maximum at the optical port This is simulated with an IR source having a peak wavelength within the range 850 nm to 900 nm and a spectral width less than 50 nm biased to provide 490 μW/cm2 (with no modulation) at the optical port. The light source faces the optical port. This simulates sunlight within the IrDA spectral range. The effect of longer wavelength radiation is covered by the incandescent condition. www.vishay.com 20 • Incandescent Lighting: 1000 lux maximum. This is produced with general service, tungsten filament, gas-filled, inside-frosted lamps in the 60 Watt to 150 Watt range to generate 1000 lux over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The source is expected to have a filament temperature in the 2700 to 3050 degrees Kelvin range and a spectral peak in the 850 nm to 1050 nm range. • Fluorescent Lighting: 1000 lux maximum This is simulated with an IR source having a peak wavelength within the range 850 nm to 900 nm and a spectral width of less than 50 nm biased and modulated to provide an optical square wave signal (0 μW/cm2 minimum and 0.3 μW/cm2 peak amplitude with 10 % to 90 % rise and fall times less than or equal to 100 ns) over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The frequency of the optical signal is swept over the frequency range from 20 kHz to 200 kHz. Due to the variety of fluorescent lamps and the range of IR emissions, this condition is not expected to cover all circumstances. It will provide a common basis for IrDA operation. Document number: 82513 Rev. 1.4, 20-Sep-06 IRDC, Part 2: Protocol Vishay Semiconductors Infrared Data Communication According the IrDA® Standard Part 2: Protocol IrDA Protocol Stack The IrDA protocol stack provides hardware and software architecture guidelines for designing an IrDA compliant system. Figure 1 shows the different layers in the stack. As a minimum, compliance to IrPHYS, IrLAP, and IrLMP is required. Optional sections of the protocol include the Higher Speed Extensions (1.15 and 4 Mbit/s), IrCOMM, TinyTP & PnP. 17265 Figure 1. IrDA Protocol Stack IrDA Link Access Protocol (IrLAP) IrLAP, is derived from an existing asynchronous data communications standard (an adaptation of HDLC). It provides guidelines for link access in which the software searches for other machines to connect to (sniffing), recognizes other machines (discovery), resolves addressing conflicts, initiates connection and information exchange, and manages disconnection. During data transfer, IrLAP is responsible for providing reliable error detection, retransmission, and flow control. While the discovery and address conflict resolution procedures are somewhat unique to IrLAP, the link initialization/ shutdown, connection startup, disconnection and information transfer procedures all resemble similar operations in HDLC protocols and are adapted to the IrDA serial infrared environment. A link operates essentially as follows: A device (primary) will want to connect to another device (either by automatic detection via the discovery and sniffing capability of IrLAP, or via direct user request). A data link involves at least one primary Document Number: 82504 Rev.1.4, 20-Sep-06 (commanding) station and one or more secondary (responding) stations, whose roles IrLAP has the responsibility of managing. The primary station has responsibility for the data link. All transmissions over a data link go to or from the primary station and can be point-to-point or point-to-multi-point. There is always one and only one primary station while all other stations must be secondary stations. After obeying the media access rules the primary will send connection request information at 9600 bit/s to the other device, this data will include information such as its address and its other capabilities such as data rate, etc. The responding device will assume the secondary role and, after obeying the media access rules, return information that contains its address and capabilities. The primary and secondary will then change the data rate and other link parameters to the common set defined by the capabilities described in the information transfer. The primary will then send data to the secondary confirming the link data rate and capabilities. The two devices are now connected and the data is transferred between primary and secondary under the complete control of the primary. Rules are defined which ensure that the secondary and primary are both able to efficiently transfer data. Any station that is capable can contend to play the primary station role. The role of primary is determined dynamically when the link connection is established and continues until the connection is closed (the exception is that there is a method provided for a primary and secondary on a point to point link to exchange roles without closing the connection). Sniff- Open Address Discovery Address Conflict Resolution Connect Information Transfer Disconnect Reset 17266 Figure 2. IrLAP Operation Procedures www.vishay.com 21 IRDC, Part 2: Protocol Vishay Semiconductors IrDA Infrared Link Management Protocol (IrLMP) Once a connection is established, IrLMP manages the available functions and applications between the communicating devices. IrLMP determines the capabilities of the connected devices (discovery) and manages negotiation of link parameters and correct data transfer (link control). The link management framework also provides a means for a device to establish coexisting access to an IR connection between multiple devices (multiplexing). Discovery occurs when two devices first encounter each other. Each service and each protocol on a device will have registered with the link management. The information registered includes both standard and protocol specific information. An application can query the capabilities of devices within range. Once an application on one device has determined which service or protocol it wishes to use, it requests the link control to use the protocol. The link management framework allows multiplexing of application or transport protocols on the same link connection at the same time. Multifunctional devices may have requirements for the IR link to support concurrent activities. While the IrDA Link Access Protocol, IrLAP, provides a single connection between a given pair of IrDA compliant devices, it provides no means for multiple application components to share coexisting access to that connection. A useful feature set of capabilities would have the mobile user wishing his handheld/PDA or note-book computer to synchronize systems, check/send/ receive electronic mail, reconcile scheduling & address book (PIM) data, and also initiate deferred printing when it makes contact with the owner's desktop personal computer (PC) and network gateway. Each activity may be controlled by distinct application components within each device (mobile unit and PC) and each component has a separate requirement to locate its peer component and establish the relevant connection. www.vishay.com 22 IrDA Link Management Protocol, IrLMP, is a mandatory component of IrDA compliant devices and addresses both the previous needs mentioned. • Connection multiplexing services provided by IrLMP Multiplexer (LM-MUX). • Location of peer application components supported by IrLMP Information Access Service(LMIAS) IrLMP Multiplexer (LM-MUX) provides multiplexed channels on top of an IrLAP connection. Each of these so called Link Service Access Point or LSAPconnections (distinguished from IrLAP connections) carries a logical separated information stream. The multiplexer operates in two modes. In multiplexed mode, the multiplexer will accept data from any of its clients (transport entities or directly bound applications). In exclusive mode a single LSAP-connection claims access to the IR medium. IrLMP Information Access Service (LM-IAS) is a direct client of LM-MUX and operates in a sclient servers manner. Application components that wish to make themselves accessible to peer components in other devices "describe" themselves by creating an object whose attributes carry the essential parameters required to establish a connection between the two peers. An application component seeking a peer application component inspects the objects within the remote LM-IAS information base. Assuming a suitable object exists, the connection parameters and the mechanism are retrieved, which is accessible at the top of the LM-IAS. MUX is used to enumerate the devices available. The resulting list of devices may be sorted/prioritized on the basis of the information hints supplied in discovery responses. IrDA Physical Layer (IrPHY) The Physical Layer provides guidelines for the physical connection of equipment using IR and defines the specifications which infrared transceivers must be able to meet. The specifications of the Physical Layer were already described in a previous chapter. Document Number: 82504 Rev.1.4, 20-Sep-06 IRDC, Part 2: Protocol Vishay Semiconductors IrDA Flow Control Mechanism (Tiny TP) Whilst IrLAP provides a flow-control mechanism between peer IrLAP entities, the introduction of multiplexed channels above IrLAP by IrLMP LM-MUX introduces a problem. Reliance on IrLAP to provide flow-control for a multiplexed channel can result in dead-locks if the consumption of data from one multiplexed channel is dependent on data flowing in an adjacent multiplexed channel. Conversely, if inbound data on a multiplexed channel cannot be consumed and the underlying IrLAP connection cannot be flow controlled off due to the possibility of deadlock, inbound data (freshly arrived or buffered) must be discarded in the event of buffer exhaustion. Sadly this reduces the reliable delivery service provided by IrLAP to a best effort delivery service provided by IrLMP LM-MUX (when multiple multiplexed channels are in operation).There are at least two possible solutions for restoring a reliable delivery service above IrLMP LM-MUX. • Provide a per application stream flow-control mechanism above LM-MUX between peer application entities. This ensures that there is always sufficient buffer space available to accommodate in-bound application data. • Provide a per application stream retransmission mechanism above LM-MUX that recovers from the loss of data that arises if inbound buffering become exhausted. The Tiny TP protocol provides: • Independently flow controlled transport connections • Segmentation and re-assembly IrDA Serial & Parallel Port Emulation (IrCOMM) IrCOMM defines the emulation of Serial and Parallel ports over the IrLMP/IrLAP protocol stack. The motivation for IrCOMM comes from the many printing and communication applications which use standard communication APIs to talk to other devices via serial and parallel ports. By making IrDA protocols accessible via these APIs, many existing applications including printing can run over an IrDA infrared link without change. This intent to support so-called legacy applications is the basis for IrCOMM. New applications are encouraged to take better advantage of IrDA protocols by using their capabilities directly. Emulating COMM ports raises a number of questions, Document Number: 82504 Rev.1.4, 20-Sep-06 starting with what kinds of ports will be emulated. IrCOMM emulates RS-232 (EIA/TIA-232-E) serial ports, and Centronics parallel ports like those found on most personal computers. The four service types used to emulate these ports are the core of this specification. Before discussing service types, however, there are some basic differences between wired and IrDA communications to consider. Wired communications methods can send streams of information in both directions at once, because there are multiple wires (some to send data on, some to receive data from). With infrared, there is the equivalent of only one wire (the IR path through the air). This has the following implications: • IrDA protocols send packets one way at a time.If a device tried to send data and listen for data at the same time, it would "hear" itself and not the device it wants to communicate with. The way IrDA devices achieve two way communications is to take turns, also known as "turning the link around". This happens at least every 500 ms, and can be made more frequent as necessary. This latency makes it impossible to perfectly emulate the wired COMM environment - very timing sensitive operations will be disrupted.Fortunately, many communication tasks are not so sensitive, and can therefore use IrCOMM. • All of the information carried on multiple wires must be carried on the single IR "wire". This is accomplished by subdividing the packets into data and control parts. In this way a logical data channel and control channel are created, and the various wires can be emulated. On a different level, IrCOMM is intended for legacy applications, applications that know about serial or parallel ports but know nothing about IrDA protocols. IrDA protocols, however, have very different procedures and APIs from wired COMMs. Suppose, for example, a word processing application wants to print via IR using IrDA protocols, an application must first "discover" the printer (locate a printer in IR-space), then check the printercs IAS to find information needed to connect. Since the word processing application (a legacy application) knows nothing about this, IrCOMM maps these operations into normal COMM operations so that it is completely transparent. For the purposes of IrCOMM a complete communication path involves two applications running on different devices (the communication endpoints) with a communication segment between them. The www.vishay.com 23 IRDC, Part 2: Protocol Vishay Semiconductors communication segment may consist solely of IR or IR connections to a network. The figure below shows the complete communication path. Application Application Communication Segment Device A Device B 17267 IrCOMM is intended to cover applications that make use of the serial and parallel ports of the devices in which they reside. In the simple case, the communication segment is an IR link from one device to another (direct connect). In the case where the communication segment is a network, IR is used for the path between the device and a networking connection device like a modem. Modems communicate through the network using wire, radio or IR. IrCOMM is only concerned with the connection between devices in the direct connect case or between the device and a modem in the network case. There are other configurations that IrCOMM can support such as modules that communicate via IR on one side and provide a wired interface on the other side. These devices are not really modems but offer a similar service and thus, are not explicitly discussed. Basically two device types exist that IrCOMM must accommodate. Type 1 devices are the communication end points such as computers and printers. Type 2 devices are those that are part of the communication segment such as modems. Though IrCOMM does not make a distinction between these two device types in the protocol, accommodating both types of devices impacts the IrCOMM protocol. The figures below illustrate how the two IrCOMM device types fit into communication paths. Device A with IrDA (Type 1) 17268 Device A with IrDA (Type 1) IR IR Device B with IrDA (Type 2) Device B with IrDA (Type 1) Wire Device C non IrDA The information transferred between two IrCOMM entities has been defined to support both type 1 and type 2 devices. Some information is only needed by type 2 devices while other information is intended to be used by both. In the protocol no distinction is made www.vishay.com 24 between type 1 and type 2 therefore, it is up to the IrCOMM implementor to determine if the information passed in the IrCOMM protocol is of use to the implementation. Since the devices do not know the type of the other device in the communication path, they must pass all the information specified by the protocol of which they have knowledge. IrCOMM emulates serial and parallel ports. However, printing and communications applications use communication ports in a variety of ways. To address this need, IrCOMM provides four service types or classes: 3-Wire raw, 3-Wire, 9-Wire, and Centronics. The service types fall into 2 camps, which are called raw and cooked; the differences hinge on whether a control channel is supplied and the type of flow control used. 3-Wire raw provides a data channel only, and uses IrLAP flow control. The "cooked" service types (3Wire, 9-Wire, and Centronics) support a control channel, and employ Tiny TP flow control. 3-Wire raw - This service type can be used for serial or parallel emulation when a single exclusive connection is acceptable, and only the data circuits need to be emulated (no non-data circuits in a corresponding wired setting carry any information). The name of this service comes from the notion of emulating the minimum three RS-232 circuits required for full duplex communications. The circuits are shown below. CCITT Signal Description Comment 102 Signal Common This circuit is not needed for IR but is one of the circuits that drove the definition of the name. 103 Transmitted Data (TD) This connection carries data transmitted by the DTE 104 Received Data (RD) This connection carries data received by the DTE Here are the main attributes of the 3-Wire Raw service class: • Only one non-IAS IrLMP connection can be open if 3-Wire raw is used - all other connections must be closed before it can be established, and others must wait until the raw connection is closed before they can connect.This is because 3-Wire raw uses the flow control features of IrLAP, which can result in a deadlock condition if more than one non-IAS connection is open. • Minimal Implementation. All the IrCOMM data is sent directly via IrLMP in IrLMP packets. All data that follows the IrLMP Mux bytes in an IrLMP packet is IrCOMM data, (i.e., it is the information that would travel over the data line(s) of a wired interface). No control channel is available to comDocument Number: 82504 Rev.1.4, 20-Sep-06 IRDC, Part 2: Protocol Vishay Semiconductors municate information about the state of other leads (e.g., RTS/CTS), software flow control settings, and the like. A service which employs 3-Wire raw must be able to do without that information. The link is merely a raw channel for the movement of data. • This service can be used to emulate both serial and parallel ports. This may seem counter–intuitive (who has ever heard of a 3-Wire parallel port?), but if you remove the non-data circuits (which 3-Wire raw does not emulate), serial and parallel are equivalent, i.e., just streams of data. IrLPT is an IrDA service in use on commercially available printing devices. It is equivalent to 3-Wire raw in functionality, but is slightly different in how it uses the IAS. 3-Wire - Like 3-Wire raw, the name of this service comes from the minimum three RS-232 circuits required for full duplex communications. Like 3-Wire raw, it is intended for both serial and parallel ports. However, there are the following important differences to be noted: • 3-Wire service class makes use of Tiny TP flow control, so that it may coexist with other connections that employ higher level (not IrLAP) flow control (including other cooked IrCOMM connections). It is not limited like 3-Wire raw to a single IrLMP connection. • 3-Wire service class supports a control channel for sending information like data format. The control channel mechanism is described in the chapter titled Frame Formats and the Control Channel. • Because of the need for flow control and the use of the control channel, the 3-Wire service type uses a more elaborate frame format. 9-Wire - The name of this service class comes from the notion of emulating the 9 circuits of an RS-232 interface which are part of a standard IBM compatible PC. Unlike the previous services it is true to its name; 9-Wire emulates serial ports only. Three of the circuits are the same as described in the 3-Wire service classes. The other six are listed below. CCITT Signal Description 105 Request to Send (RTS) 106 Clear to Send (CTS) 107 Data Set Ready (DSR) 108 Data terminal Ready (DTR) 109 Data Channel received line signal detector (RLSD), aka Carrier Detect (CD) 125 Calling indicator, aka ring Indicator (RI) Document Number: 82504 Rev.1.4, 20-Sep-06 Some attributes of this service are listed below. • Like 3-Wire, it uses the Tiny TP flow control mechanism. It also uses the same control channel mechanism for sending information like data format. • The control channel is used to send the states of the other RS-232 leads as they change. Centronics - This service is intended to emulate the function of a standard Centronics interface. This service is for parallel ports only. Some attributes of this service are listed below. • It uses the Tiny TP flow control mechanism. • It uses the same control channel mechanism used in 3-Wire to send the status/changes of the additional circuits. IrDA Object Exchange Protocol (IrOBEX) One of the most basic and desirable uses of the IrDA infrared communication protocols is simply to send an arbitrary "thing", or data object, from one device to another, and to make it easy for both application developers and users to do so. We refer to this as object exchange (uncapitalized), and it is the subject of the protocol IrOBEX (for IrDA Object Exchange, OBEX for short). OBEX is a compact, efficient, binary protocol that enables a wide range of devices to exchange data in a simple and spontaneous manner. OBEX is being defined by members of the Infrared Data Association to interconnect the full range of devices that support IrDA protocols. It is not, however, limited to use in an IrDA environment. OBEX performs a function similar to HTTP, a major protocol underlying the World Wide Web. However, OBEX works for the many very useful devices that cannot afford the substantial resources required for an HTTP server, and it also targets devices with different usage models from the Web. OBEX is enough like HTTP to serve as a compact final hop to a device "not quite" on the Web. A major use of OBEX is a "Squirt" or "Slurp" application, allowing rapid and ubiquitous communications among portable devices or in dynamic environments. For instance, a laptop user squirts a file to another laptop or PDA; an industrial computer slurps status and diagnostic information from a piece of factory floor machinery; a digital camera squirts its pictures into a film development kiosk, or if lost can be queried (slurped) for the electronic business card of its owner. However, OBEX is not limited to quick connect-transfer-disconnect scenarios - it also allows sessions in which transfers take place over a period of time, maintaining the connection even when it is idle. www.vishay.com 25 IRDC, Part 2: Protocol Vishay Semiconductors PCs, pagers, PDAs, phones, auto-tellers, information kiosks, calculators, data collection devices, watches, home electronics, industrial machinery, medical instruments, automobiles, pizza ovens, and office equipment are all candidates for using OBEX. To support this wide variety of platforms, OBEX is designed to transfer flexibly defined "objects"; for example, files, diagnostic information, electronic business cards, bank account balances, electrocardiogram strips, or itemized receipts at the grocery store. "Object" has no lofty technical meaning here; it is intended to convey flexibility in what information can be transferred. OBEX can also be used for Command and Control functions – directives to TVs, VCRs, overhead projectors, computers and machinery. OBEX consists of two major parts: a model for representing objects (and information that describes the objects), and a session protocol to provide a structure for the "conversation" between devices. OBEX is designed to fulfill the following major goals: IrDA Infrared Transfer Picture (IrTran-P) IrTran-P (Infrared Transfer Picture) is an image communication scheme for a digital camera based on the Infrared Communication Standard specification created by IrDA. The IrTran-P specification should generally be used together with the IrDA standard specifications. IrTran-P is placed on the upper layer of IrSIR, IrLAP, IrLMP, TinyTP and IrCOMM which is already established as IrDA standard specifications. SCEP (Simple Command Execute Protocol) and a bFTP (Binary File Transfer Protocol) are necessary for exchanging an image between devices and mutually exchanging properties of the devices. An image format (file) called UPF (Uni Picture Format) is exchanged on such an entity (UPF is the image format out of the category of IrDA, and can be found in the appendix of the IrTranP specification). IrTran-P is a generic name given to all of these components. UPF (Uni Picture Format) bFTB (binary File Transfer Protocol) The wide world of applications (Command Definition) Default OBEX applications SCEP (Simple Command Execute Protocol) (connection management, segmentation & reassemple) IrCOMM (RS232Cemulation) OBEX protocol Various Transports (TinyTP, Connectionless) IAS Services IrLMP-IAS Tiny TP (Information Acces Service) (flow control for a multiplexed channel) IrMP-MUX (Link Management Protocol) IrLMP LM-MUX IrLAP (Link Acces Protocol) IrLAP 17269 Figure 3. OBEX in the IrDA architecture • Application friendly - provide the key tools for rapid development of applications • Compact - minimum strain on resources of small devices • Cross platform • Flexible data handling, including data typing and support for standardized types - this will allow simpler devices for the user through more intelligent handling of data inside. • Maps easily into Internet data transfer protocols • Extensible - provides growth path to future needs like security, compression, and other extended features without burdening more constrained implementations. • Debuggable www.vishay.com 26 17270 IrDA SIR 1.0 (115.2kbit/s) / SIR 1.1 (4.0Mbit/s) SCEP establishes a session on IrCOMM and provides a transparent session which notifies an upper layer of a command. The procedure of SCEP is developed by a lower layer making use of an advantage that an IrDA protocol is "error free", as a high speed session layer matching the IrDA protocol. As is apparent from its name, bFTP provides a service for transferring a binary file. The bFTP assumes a virtual file system together with a communication protocol. The bFTP has an aspect which enables it to be easily implemented, because it assumes such a simple file system that will allow "a binary file to be stored with its name". Moreover, bFTP is characterized by a query function which allows it to query functions and properties of a device and the image format available in the theme of this section, i.e., the image transfer. This query function simplifies the user interface of a digital camera, Document Number: 82504 Rev.1.4, 20-Sep-06 IRDC, Part 2: Protocol Vishay Semiconductors and allows the most suitable data of an image to be transferred between the digital cameras or printers facing each other. In addition, this function makes it possible for the user to transfer, communicate or print suitable image data regardless of the difference in platform or model just by "selecting a photograph to be sent and pushing a transmission button". As mentioned earlier, UPF is the standard of an image format not included in the category of the IrDA standard. The IrDA standards were originally provided for defining and standardizing a protocol in connection with infrared communications. Therefore, it is out of the scope to define the contents of an image transfer. However, in order to ensure mutual connectivity as an application of a digital camera, it is required to decide an image format so that image data sent via infrared communication is reliably reproduced. Therefore, in advocating IrTran-P as a standard to IrDA, the specific contents of an image format of IrTran-P are defined and described in an appendix. UPF is an image file format based on the JPEG base line. JFIF, which is a JPEG file, makes an image of various color forms available and employs a high level of compression scheme. For this reason, JFIF may be regarded as the industry standard of an image file format today. Since JPEG is a format enabling a variety of color forms, a compromise is required to some extent in order to realize the standard at a low cost, for example adopting only a part of the format as the standard. In UPF, among the formats included in the base line of JPEG, the format which allows the devices at least to reliably display and mutually transfer an image is defined as an indispensable one, and others are regarded as an option. For more details, please refer to the sections of UPF in the later part of this document. It is characteristic of a digital camera that all the data accompanying a photograph taken by a digital camera, such as a photo-taking date/time and the orientation (direction) of an image and other additional data, cannot be covered by the data within the JPEG format. In view of such a background, UPF is designed so that data is separated and stored on its own header arranged in the file without changing the image data scheme of JPEG Base Line at all. In addition, the header has expendability and allows a vendor-unique function to be added thereto. This makes it possible to separate the data necessary for a digital video camera from the data necessary for display and expansion of an image. This is advantageous in that the existing JPEG techniques can be used where they stand and do not have to be changed. In a compact device like a digital camera, when using existing Document Number: 82504 Rev.1.4, 20-Sep-06 hardware or software, e.g. in the case where an algorithm of JPEG compression/expansion or the like is performed by hardware or is fixedly used as firm ware, it is undesirable to change JPEG itself. As a further advanced step, UPF is designed so that additional data on an ambiguous point within the data of JPEG scheme is arranged in the header part. The additional data includes factors such as white level, black level and color-difference signal, necessary for reproducing an image with correct brightness and color. Although the format of a digital camera is being examined by various organizations, a conclusive decision has not yet been made. In most cases, an arrangement such as a new addition of a tag to JPEG or the like has been proposed. However, it will take a long time to reach a conclusion satisfactory to all the companies concerned. The approach of making the best use of an existing standard, wherein the data necessary for a digital camera is separated and added so as to assure expendability, is more realistic than the approach of waiting for a new standard to be defined and finalized. Though UPF is defined as an appendix, it is indispensable in order that the IrTran-P standard is able to support an image format of a UPF scheme. In IrTranP, a sender starts an operation which transfers picture data from a digital camera. • Operation by User With the use of "selection of a specific picture" and a "transmission button" the user puts the digital camera of the sender into a transmission state. It is assumed that the device of a receiver is always in a receiving state or put info a picture data receiving state by a "reception button". • Establishment of Session by SCEP The digital camera of the sender carries out a discovery procedure using IrDA protocols and performs a connection for the physical to IrCOMM layers of IrDA protocols in accordance with IrDA protocols. When an IrDA transmission path is established, SCEP makes a "session establishment request" from the sender to the receiver of a digital camera, printer or PC. If the receiver is implemented with SCEP, it must make a response of either "session established" or "session establishment rejected". • Query Operation by bFTP (Query function) When a session by SCEP is established, the digital camera of the sender issues a Query request in order to recognize the picture processing functions of the receiver. The information mutually www.vishay.com 27 IRDC, Part 2: Protocol Vishay Semiconductors exchanged by the Query request includes the transmittable / receivable picture size, the picture compression format and the basic picture size of the device. Since this information is exchanged before transfer of picture data, the picture data can be transferred in "the most reasonable format" between devices of different platforms. In IrTran-P, a "mandatory format" is defined among the picture data formats of both sides, whereby a picture can be reliably exchanged between devices of different grades or manufacturers. Furthermore, the power supply condition of the device, the receivable data capacity etc. should be queried. This makes it possible to deal with the applications of a portable system. • Transfer of Picture Data by bFTP Transfer of picture data is started once the most appropriate picture format for both the sender and the receiver has been determined by Query. SCEP performs the data transfer at a high transmission rate by making use of IrDA protocols. After the file transfer is completed, next picture data may be subsequently transmitted, or a session may be disconnected by SCEP. (Accordingly, even a simple model can transmit more than one picture in succession.) • Completion of Session by SCEP When the picture transfer has been completed, the digital camera of the sender disconnects a session by SCEP. Thereafter, a disconnection request is issued for IrCOMM and lower layers of IrDA protocols and the picture transfer operation has been completed. IR Mobile Communication Standard (IrMC) The IrDA IrMC specification defines the rules for utilization of IR in wireless communications equipment, e.g., in mobile handsets, PDAs, PCs, notebook computers and pagers. The IrMC specification enables IrMC Object exchange between a variety of applications. For instance, the IrMC specification enables easy exchange of: • business cards between Phone Book Applications • text messages between Messaging Applications • calendar and todo items between Calendar Applications • short notes between Note applications www.vishay.com 28 The IrMC Call Control specification enables call control of mobile handsets. The IrMC Audio Specification enables real time audio transmission respectively. These two specifications are for communication between a handset and PC or a handset and car cradle. Data Transmission The IrMC framework uses the existing IrDA specifications as much as possible. IrDA connection-oriented services are used as is, and the connectionless service (Ultra) is further defined to be applicable to IrMC devices. Physical Layer Considerations Because the power consumption requirements of the IrMC devices are very critical, a low power option for these devices has been specified already in the IrPHY version 1.2. This specification defines a lighter physical layer and allows up to ten times savings in the LED drive current. It should be noted that this specification, which only expects the Specifications for IR Mobile Communications (IrMC) Version 1.1 IrMC devices to be capable of 20 cm link distance from IrMC device to IrMC device and 30 cm from IrMC device to a standard IrDA device, is optional and the original IrDA-SIR values may be used in all IrMC device implementations. Despite the shorter communication range of some IrMC devices, all devices must clearly be compatible with the IrDA-SIR in the short range. Devices supporting IrCOMM communications with personal computers should realize that the RF interference shielding of PCs may be imperfect. For Mobile Communication applications standard transceivers, fulfilling the IrDA‚ physical layer specification can be applied. However, especially in mobile phone application the demand for a high EMI immunity must be considered. Vishay Semiconductors supplies devices suited for these applications. Document Number: 82504 Rev.1.4, 20-Sep-06 IRDC, Part 2: Protocol Vishay Semiconductors IR Financial Messaging (IrFM) IrSimpleTM - Simple Connect Standard The IrFM profiles have been developed to enable a digital payment system which will cut transaction costs for the merchant and the financial institutions, cut charge-back fees to merchants through the electronic warehousing of transaction receipts, and provide a simpler method of financial transaction tracking to individuals for personal and business use. In simple words: IR enabled devices as mobile phones or PDAs will include the credit card information and the transaction will be done over the air by Infrared beaming. IrFM provides a quick and seamless way for users of infrared enabled portable devices, such as PDAs and mobile phones, to pay for services and merchandise by beaming their "soft" credit cards, debit cards, checks, cash, or other financial instruments to a point of sale device (POS), ATM, vending machine or other compatible payment terminal. The IrFM Profiles define the minimum technical requirements needed to implement the use cases described. Potential devices implementing these Profiles include pagers, PDAs and mobile phones communicating with POS terminals, vending machines, ATMs and other existing POS devices enabled with infrared adapters, or new devices with IrDA capability built in. IrFM is compatible with the Ir Physical Layer standard and any physical layer compliant hardware transceiver will support IrFM. Early adopters of this new financial messaging scenario will include the many millions of users of IrDA enabled PDA's and mobile phones; paying for meals at restaurants and fast food outlets, buying gas at the pump, making purchases at all types of stores, going to the movies, using public transportation systems and a host of other applications made possible by the electronic wallet concept. The manual card swipe/card reader interaction between the consumer's physical card and the point of sale terminal is replaced by the consumer’s handheld device and an IR-enabled point of sale terminal. After the transaction has been "beamed", the backend processing of the transaction is treated as if the process had occurred by card swipe. No backend processing changes are required. IrSimple (Acronym: IrSC), is one of the latest additions to the upper layer protocols, it does not replace but enhances most of the other application based protocols by providing a more efficient mechanism to transfer specific object data formats such as graphic files that are typically associated with small portable devices maintaining the lowest usage of memory. Frequent scenarios are the transmission of pictures between mobile phones as well as from mobiles to TV sets. This protocol also relies on the binding Access and Management protocols. Because it must maintain a degree of integrity with other application’s protocol that would also allow it to handle standard bidirectional transmission of small data files, it makes use of a sequence manager protocol IrSMC for the segmentation and reassembly of frames (flow control), primarily between the application protocols and the link management protocol IrLMP. Unlike with other robust and complex data transfer protocols, IrSC is specifically aimed at visual (graphical data transfers). It is not mandatory for the receiving station to maintain a bidirectional link because successful transmission of data is visually ackknowledged. The Infrared Data Association (IrDA) announced the availability of the IrSimple Protocol and Profile Specifications under the brand name SimpleShotTM. Simple Shot enables mobile devices like Camera Phones to wireless transmit digital images to similarly enabled Televisions, Monitors, Projectors and Photo Kiosks. SimpleShot frees the billions of digital images trapped in Camera Phones and PDAs, allowing them to be viewed on large screens or quickly printed. The IrDA Special Interesting Group (SIG) developed and perfected SimpleShot for fast, wireless communication between mobile devices and digital home appliances. Document Number: 82504 Rev.1.4, 20-Sep-06 www.vishay.com 29 IRDC, Part 2: Protocol Vishay Semiconductors Appendix List of Terms and Abbreviations: IrDA Infrared Data Association IrLAP IrDA Link Access Protocol IrLMP IrDALink Management Protocol IrPHY IrDA Physical Layer IrTRAN-P IrDA Transfer Picture IrCOMM IrDA "Serial & Parallel Port Emulation over Ir" IrOBEX IrDA Object Exchange Protocol Tiny TP a Flow control mechanism for use with IrLMP LM-MUX IrLMP Multiplexer LM-IAS IrLMP Information Access Service SCEP Simple Command Execute Protocol BFTP binary File Transfer Protocol UPF Uni Picture Format SIR Serial Infrared FIR Fast Infrared IrMC IrDA Mobile Communication IrFM IrDA Financial Messaging IrSC IrSimple(TM), SimpleShot(TM) www.vishay.com 30 Document Number: 82504 Rev.1.4, 20-Sep-06 Symbols and Terminology Vishay Semiconductors Symbols and Terminology A anode Anode terminal A ampere SI unit of electrical current A radiant sensitive area That area which is radiant sensitive for a specified range a distance E.g. a distance between the emitter (source) and the detector B base Base terminal BER Bit Error Rate bit/s data rate or signaling rate 1000 bit/s = 1 kbit/s, 106 bit/s = 1 Mbit/s C capacitance Unit: F (farad) = C/V C coulomb C=As C cathode, cathode terminal C collector, collector terminal °C degree Celsius Celsius temperature, symbol t, and is defined by the quantity equation t = T - T0. The unit of Celsius temperature is the degree Celsius, symbol °C. The numerical value of a Celsius temperature t expressed in degrees Celsius is given by t / °C = T / K – 273.15 It follows from the definition of t that the degree Celsius is equal in magnitude to the kelvin, which in turn implies that the numerical value of a given temperature difference or temperature interval whose value is expressed in the unit degree Celsius (°C) is equal to the numerical value of the same difference or interval when its value is expressed in the unit kelvin (K) cd candela SI unit of luminous intensity. The candela is the luminous intensity, in a given direction, of a source that emits monochromatic radiation of frequency 540 x 1012 hertz and that has a radiant intensity in that direction of 1/683 watt per steradian. (16th General Conference of Weights and Measures, 1979) 1 cd = 1 lm sr-1 CD diode capacitance Total capacitance effective between the diode terminals due to case, junction and parasitic capacitances Document Number: 82512 Rev. 1.4, 06-Oct-06 Cj junction capacitance Capacitance due to a pn junction of a diode, decreases with increasing reverse voltage d apparent (or virtual) source size (of an emitter) The measured diameter of an optical source used to calculate the eye safety laser class of the source. See IEC60825-1 and EN ISO 11146-1 E emitter Emitter terminal (phototransistor) EA illumination at standard illuminant A According to DIN 5033 and IEC 306-1, illumination emitted from a tungsten filament lamp with a color temperature Tf = 2855.6 K, which is equivalent to standard illuminant A Unit: lx (Lux) or klx EA amb ambient illumination at standard illuminant A echo - off Unprecise term to describe the behavior of the output of IrDA® transceivers during transmission. "echo – off" means that by blocking the receiver the output Rxd is quiet during transmission echo - on Unprecise term to describe the behavior of the output of IrDA® transceivers during transmission. "echo – on" means that the receiver output Rxd is active but often undefined during transmission. For correct data reception after transmission the receiver channel must be cleared during the latency period Ee, E irradiance (at a point of a surface) Quotient of the radiant flux d)e incident on an element of the surface containing the point, by the area dA of that element. Equivalent definition. Integral, taken over the hemisphere visible from the given point, of the expression Le cosT d:, where Le is the radiance at the given point in the various directions of the incident elementary beams of solid angle d:, and T is the angle between any of these beams and the normal to the surface at the given point Ee d) = --------e- = dA ³ L e cos T d : 2 S sr Unit: W m-2 Ev, E illuminance (at a point of a surface) Quotient of the luminous flux d)v incident on www.vishay.com 31 Symbols and Terminology Vishay Semiconductors an element of the surface containing the point, by the area dA of that element. Equivalent defnition. Integral, taken over the hemisphere visible from the given point, of the expression Lv cosT d:, where Lv is the luminance at the given point in the various directions of the incident elementary beams of solid angle d:, and T is the angle between any of these beams and the normal to the surface at the given point d )v L v cos T d : E v = --------- = dA ³ 2 S sr F f fc, fcd fs FIR Ia IB IBM IC Ica ICEO ICM idle Unit: lx = lm m-2 farad Unit: F = C/V frequency Unit: s-1, Hz (Hertz) cut-off frequency – detector devices The frequency at which, for constant signal modulation depth of the input radiant power, the demodulated signal power has decreased to ½ of its low frequency value. Example: The incident radiation generates a photocurrent or a photo voltage 0.707 times the value of radiation at f = 1 kHz (3 dB signal drop, other references may occur as e.g. 6 dB or 10 dB) switching frequency Fast Infrared, as SIR, data rate 4 Mbit/s light current General: Current which flows through a device due to irradiation/illumination base current base peak current collector current collector light current Collector current under irradiation Collector current which flows at a specified illumination/irradiation collector dark current, with open base Collector-emitter dark current For radiant sensitive devices with open base and without illumination/radiation (E = 0) repetitive peak collector current Mode of operation where the device (e.g. a transceiver) is fully operational and expecting to receive a signal for operation e.g in case of a transceiver waiting to receive an optical input www.vishay.com 32 or to send an optical output as response to an applied electrical signal Ie, I radiant intensity (of a source, in a given direction) Quotient of the radiant flux d)e leaving the source and propagated in the element of solid angle d: containing the given direction, by the element of solid angle Ie = d)e/d: Unit: W sr-1 Note: The radiant intensity Ie of emitters is typically measured with an angle < 0.01 sr on mechanical axis or off-axis in the maximum of the irradiation pattern IF continuous forward current The current flowing through a diode in the forward direction IFAV average (mean) forward current IFM peak forward current IFSM surge forward current short-circuit current Ik That value of the current which flows when a photovoltaic cell or a photodiode is short circuited (RL << Ri ) at its terminals Io dc output current Iph photocurrent That part of the output current of a photoelectric detector, which is caused by incident radiation IR reverse current, leakage current Current which flows through a reverse biased semiconductor pn-junction IR Abbreviation for infrared Ira reverse current under irradiation Reverse light current which flows due to a specified irradiation/illumination in a photoelectric device Ira = Iro + Iph IrDA® Infrared Data Association No profit organization generating infrared data communication standards IRED infrared emitting diode Solid state device embodying a p-n junction, emitting infrared radiation when excited by an electric current. See also LED: Solid state device embodying a p-n junction, emitting optical radiation when excited by an electric current. Iro reverse dark current, dark current Reverse current flowing through a photoelectric device in the absence of irradiation Document Number: 82512 Rev. 1.4, 06-Oct-06 Symbols and Terminology Vishay Semiconductors IrPHY version 1.0 SIR IrDA®‚ data communication specification covering data rates from 2.4 kbit/s to 115.2 kbit/s and a guaranteed operating range more than one meter in a cone of ± 15° IrPHY version 1.1 MIR and FIR were implemented in the IrDA® standard with the version 1.1, replacing version 1.0 IrPHY version 1.2 Added the SIR Low Power Standard to the IrDA® standard, replacing version 1.1. The SIR Low Power Standard describes a current saving implementation with reduced range (min. 20 cm to other Low Power Devices and min. 30 cm to full range devices). IrPHY version 1.3 extended the Low Power Option to the higher bit rates of MIR and FIR replacing version 1.2. IrPHY version 1.4 VFIR was added, replacing version 1.3 ISB quiescent current ISD supply current in dark ambient ISH supply current in bright ambient Iv, I luminous intensity (of a source, in a given direction) Quotient of the luminous flux d)v leaving the source and propagated in the element of solid angle d: containing the given direction, by the element of solid angle Ie = d)v/d: Unit: cd sr-1 Note: The luminous intensity Iv of emitters is typically measured with an angle < 0.01 sr on mechanical axis or off-axis in the maximum of the irradiation pattern K luminous efficacy of radiation Quotient of the luminous flux )v by the corresponding radiant flux )e: K = )v / )e Unit: lm W-1 Note: When applied to monochromatic radiations, the maximum value of K(O) is denoted by the symbol Km Km = 683 lm W-1 for Qm = 540 1012 Hz (Om | 555 nm) for photopic vision. K'm = 1700 lm W-1 for O'm | 507 nm for scotopic vision. For other wavelengths: K(O) = Km V(O) and K'(O) = K'm V'(O) K kelvin SI unit of thermodynamic temperature, is the fraction 1/273.15 of the thermodynamic temDocument Number: 82512 Rev. 1.4, 06-Oct-06 perature of the triple point of water (13th CGPM (1967), Resolution 4). The unit kelvin and its symbol K should be used to express an interval or a difference of temperature. Note: In addition to the thermodynamic temperature (symbol T), expressed in kelvins, use is also made of Celsius temperature (symbol t ) defined by the equation t = T-T0, where T0 = 273.15 K by definition. To express Celsius temperature, the unit "degree Celsius", which is equal to the unit "kelvin" is used; in this case, "degree Celsius" is a special name used in place of "kelvin". An interval or difference of Celsius temperature can, however, be expressed in kelvins as well as in degrees Celsius Latency receiver latency allowance (in ms or μs) is the maximum time after a node ceases transmitting before the node’s receiving recovers its specified sensitivity LED and IRED Light Emitting Diode LED: Solid state device embodying a p-n junction, emitting optical radiation when excited by an electric current. The term LED is correct only for visible radiation, because light is defined as visible radiation (see “Radiation and Light”). For infrared emitting diodes the term IRED is the correct term. Nevertheless it is common but not correct to use "LED" also for IREDs Le; L radiance (in a given direction, at a given point of a real or imaginary surface) Quantity defined by the formula Le lm lx m d) v = -------------------------------- , dA cos T d : where d)e is the radiant flux transmitted by an elementary beam passing through the given point and propagating in the solid angle d: containing the given direction; dA is the area of a section of that beam containing the given point; T is the angle between the normal to that section and the direction of the beam Unit: W m-2 sr-1 lumen Unit for luminous flux lux Unit for illuminance meter SI unit of length www.vishay.com 33 Symbols and Terminology Vishay Semiconductors Me; M radiant exitance (at a point of a surface) Quotient of the radiant flux d)e leaving an element of the surface containing the point, by the area dA of that element. Equivalent definition. Integral, taken over the hemisphere visible from the given point, of the expression Le cosT d:, where Le is the radiance at the given point in the various directions of the emitted elementary beams of solid angle d:, and T is the angle between any of these beams and the normal to the surface at the given point. d) M e = ----------e- = dA ³ 2Ssr L e cos T d : Unit: W m-2 MIR Medium speed IR, as SIR, with the data rate 576 kbit/s to 1152 kbit/s Mode Electrical input or output port of a transceiver device to set the receiver bandwidth N.A. Numerical Aperture N.A. = sin D/2 Term used for the characteristic of sensitivity or intensity angles of fiber optics and objectives NEP Noise Equivalent Power Ptot total power dissipation Pv power dissipation, general Radiation and Light visible radiation Any optical radiation capable of causing a visual sensation directly. Note: There are no precise limits for the spectral range of visible radiation since they depend upon the amount of radiant power reaching the retina and the responsivity of the observer. The lower limit is generally taken between 360 nm and 400 nm and the upper limit between 760 nm and 830 nm Radiation and Light optical radiation Electromagnetic radiation at wavelengths between the region of transition to X-rays ( O = 1 nm) and the region of transition to radio waves ( O = 1 mm) Radiation and Light IR infrared radiation Optical radiation for which the wavelengths are longer than those for visible radiation. Note: For infrared radiation, the range between 780 nm and 1 mm is commonly sub-divided into: IR-A 780 nm to 1400 nm IR-B 1.4 μm to 3 μm IR-C 3 μm to 1 mm www.vishay.com 34 RD RF Ri Ris RL RS Rsh dark resistance feedback resistor internal resistance isolation resistance load resistance serial resistance shunt resistance The shunt resistance of a detector diode is the dynamic resistance of the diode at zero bias. Typically it is measured at a voltage of 10 mV forward or reverse, or peak-to-peak RthJA thermal resistance, junction to ambient RthJC thermal resistance, junction to case RXD electrical data output port of a transceiver device s second SI unit of time 1 h = 60 min = 3600 s S absolute sensitivity Ratio of the output value Y of a radiant-sensitive device to the input value X of a physical quantity: S = Y/X Units: E.g. A/lx, A/W, A/(W/m2) s(Op) spectral sensitivity at a wavelength Op s(O) absolute spectral sensitivity at a wavelength O The ratio of the output quantity y to the radiant input quantity x in the range of wavelengths O to O +'O: s(O) = dy(O)/dx(O). E.g., the radiant power )e(O) at a specified wavelength O falls on the radiationsensitive area of a detector and generates a photocurrent Iph. s(O) is the ratio between the generated photocurrent Iph and the radiant power )e(O) which falls on the detector: s(O) = Iph / )e(O) Unit: A/W s(O)rel spectral sensitivity, relative Ratio of the spectral sensitivity s(O) at any considered wavelength to the spectral sensitivity s(O0) at a certain wavelength O0 taken as a reference: s(O)rel = s(O)/s(O0) s(O0) spectral sensitivity at a reference wavelength O0 SC Electrical input port of a transceiver device to set the receiver sensitivity SD Electrical input port of a transceiver device to shut down the transceiver shutdown Mode of operation where a device is switched to a sleep mode (shut down) by an external signal or after a quiescent period keeping some Document Number: 82512 Rev. 1.4, 06-Oct-06 Symbols and Terminology Vishay Semiconductors functions alive to be prepared for a fast transition to operating mode. Might be in some cases identical with "Standby" SIR Serial Infrared, Term used by IrDA® to describe infrared data transmission up to and including 115.2 kbit/s. SIR IrDA® data communication covers 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard introduced with the physical layer version IrPhy version 1.0 split power supply Term for using separated power supplies for different functions in transceivers. Receiver circuits need well-controlled supply voltages. IRED drivers don’t need a controlled supply voltage but need much higher currents. Therefore it safes cost not to control the IRED current supply and have a separated supply. For that some modified design rules have to be taken into account for designing the ASIC. This is used in nearly all Vishay transceivers and is described in US-Patent No. 6,157,476 sr steradian (sr) SI unit of solid angle : Solid angle that, having its vertex at the centre of a sphere, cuts off an area of the surface of the sphere equal to that of a square with sides of length equal to the radius of the sphere. (ISO, 31/1-2.1, 1978) Example: The unity solid angle, in terms of geometry, is the angle subtended at the center of a sphere by an area on its surface numerically equal to the square of the radius (see figures below) Other than the figures might suggest, the shape of the area doesn't matter at all. Any shape on the surface of the sphere that holds the same area will define a solid angle of the same size. The unit of the solid angle is the steradian (sr). Mathematically, the solid angle is dimensionless, but for practical reasons, the steradian is assigned Standby Mode of operation where a device is prepared to be quickly switched into an idle or operating mode by an external signal T period of time (duration) T temperature 0 K = – 273.15 °C Unit: K (kelvin) t temperature °C (degree Celsius) Document Number: 82512 Rev. 1.4, 06-Oct-06 t Tamb Tamb TC TC Tcase td tf Tj toff ton tp Instead of t sometimes T is used not to mix up temperature T with time t time ambient temperature If self-heating is significant: temperature of the surrounding air below the device, under conditions of thermal equilibrium. If self-heating is insignificant: air temperature in the surroundings of the device ambient temperature range As an absolute maximum rating: The maximum permissible ambient temperature range temperature coefficient The ratio of the relative change of an electrical quantity to the change in temperature ('T) which causes it under otherwise constant operating conditions colour temperature (BE) The temperature of a Planckian radiator whose radiation has the same chromaticity as that of a given stimulus Unit: K Note: The reciprocal colour temperature is also used, unit K-1 (BE) case temperature The temperature measured at a specified point on the case of a semiconductor device. Unless otherwise stated, this temperature is given as the temperature of the mounting base for devices with metal can delay time fall time The time interval between the upper specified value and the lower specified value on the trailing edge of the pulse. Note: It is common to use a 90 % value of the signal for the upper specified value and a 10 % value for the lower specified value junction temperature The spatial mean value of the temperature during operation. In the case of phototransistors, it is mainly the temperature of the collector junction because its inherent temperature is the maximum turn-off time turn-on time pulse duration The time interval between the specified value on the leading edge of the pulse and the specified value an the trailing edge of the output pulse www.vishay.com 35 Symbols and Terminology Vishay Semiconductors Note: In most cases the specified value is 50 % of the signal tpi input pulse duration tpo output pulse duration rise time tr The time interval between the lower specified value and the upper specified value on the trailing edge of the pulse. Note: It is common to use a 90 % value of the signal for the upper specified value and a 10 % value for the lower specified value ts Storage time ts storage time Tsd soldering temperature Maximum allowable temperature for soldering with a specified distance from the case and its duration Tstg storage temperature range The temperature range at which the device may be stored or transported without any applied voltage TXD Electrical data input port of a transceiver device V volt V(O) standard luminous efficiency function for photopic vision (relative human eye sensitivity) V(O), V'(O) spectral luminous efficiency (of a monochromatic radiation of wavelength O); V(O) for photopic vision; V'(O) for scotopic vision) Ratio of the radiant flux at wavelength Om to that at wavelength O such that both radiations produce equally intense luminous sensations under specified photometric conditions and Om is chosen so that the maximum value of this ratio is equal to 1. VCC supply voltage (positive) VCEsat collector-emitter saturation voltage The saturation voltage is the dc voltage between collector and emitter for specified (saturation) conditions, i.e., IC and EV (Ee or IB), whereas the operating point is within the saturation region Vdd supply voltage (positive) VF forward voltage The voltage across the diode terminals which results from the flow of current in the forward direction VFIR As SIR, data rate 16 Mbit/s Vlogic reference voltage for digital data communication ports VO output voltage www.vishay.com 36 'VO output voltage change (differential output voltage) VOC open circuit voltage The voltage measured between the photovoltaic cell or photodiode terminals at a specified irradiance/illuminance (high impedance voltmeter!) VOH output voltage high VOL output voltage low Vph photovoltage The voltage generated between the photovoltaic cell or photodiode terminals due to irradiation/ illumination VR reverse voltage (of a junction) Applied voltage such that the current flows in the reverse direction VR reverse (breakdown) voltage The voltage drop which results from the flow of a defined reverse current VS supply voltage VSS (most negative) supply voltage (in most cases: Ground) ± M1/2 angle of half transmission distance K quantum efficiency T1/2; ± M = D/2 half – intensity angle In a radiation diagram, the angle within which the radiant (or luminous) intensity is greater than or equal to half of the maximum intensity. Note: IEC60747-5-1 is using T1/2. In Vishay data sheets mostly ± M = D/2 is used T1/2; ± M = D/2 half – sensitivity angle In a sensitivity diagram, the angle within which the sensitivity is greater than or equal to half of the maximum sensitivity. Note: IEC60747-5-1 is using T1/2. In Vishay data sheets mostly ± M = D/2 is used : solid angle, see sr, steradian for IEC60050(845)-definition The space enclosed by rays, which emerge from a single point and lead to all the points of a closed curve. If it is assumed that the apex of the cone formed in this way is the center of a sphere with radius r and that the cone intersects with the surface of the sphere, then the size of the surface area (A) of the sphere subtending the cone is a measure of the solid angle : : = A/r2 The full sphere is equivalent to 4S sr. A cone with an angle of D/2 forms a solid angle Document Number: 82512 Rev. 1.4, 06-Oct-06 Symbols and Terminology Vishay Semiconductors of : = 2S(1-cos D/2) = 4Ssin2D/4 Unit: sr (steradian) Om wavelength of the maximum of the spectral luminous efficiency function V(O) 'O range of spectral bandwidth (50 %) The range of wavelengths where the spectral sensitivity or spectral emission remains within 50 % of the maximum value )e;); P radiant flux; radiant power Power emitted, transmitted or received in the form of radiation. Unit: W W = Watt )v; ) luminous flux Quantity derived from radiant flux )e by evaluating the radiation according to its action upon the CIE standard photometric observer. For photopic vision )v = Km f d) eO V( O d O ³0 -------------dO O Oc wavelength, general centroid wavelength Centroid wavelength Oc of a spectral distribution, which is calculated as "centre of gravity wavelength" according to O2 O2 Oc = ³ O Sx ( O d O e ³ Sx ( O d O O1 OD Op O1 dominant wavelength wavelength of peak sensitivity or peak emission , d )e O where -------------- is the spectral distribution of dO the radiant flux and V(O) is the spectral luminous efficiency. Unit : lm lm: lumen Km = 683 lm/W: Note: For the values of Km (photopic vision) and K'm (scotopic vision), see IEC60050 (845-01-56). Document Number: 82512 Rev. 1.4, 06-Oct-06 www.vishay.com 37 Symbols and Terminology Vishay Semiconductors Ω = 4 π sr α = 65.5° Ω = 1.0sr α = 2 arc cos ( 1– / 2 π) α = 20.5° Ω = 0.01sr Ω = 0.1sr α = 6.5° 94 8584 Definitions Databook Nomenclature The nomenclature and usage of symbols, abbreviations and terms inside the Vishay Semiconductors IRDC Databook is based on ISO and IEC standards. The special optoelectronic terms and definitions are referring to the IEC Multilingual Dictionary (Electricity, Electronics and Telecommunications), Fourth edition (2001-01), IEC50 (Now: IEC60050). The references are taken from the current editions of IEC60050 (845), IEC60747-5-1 and IEC60747-5-2. Measurement conditions are based on IEC and other international standards and especially guided by IEC60747-5-3. Editorial notes: Due to typographical limitations variables cannot be printed in an italics format, which is usually mandatory. Our databook in general is using American spelling (AE). International standards are www.vishay.com 38 written in British English (BE). Definitions are copied without changes from the original text. Therefore these may contain British spelling. Radiant and Luminous Quantities and Their Units These two kinds of quantities have the same basic symbols, identified respectively, where necessary, by the subscript e (energy) or v (visual), e.g.)e, )v. See note. Note: Photopic and scotopic quantities. - Luminous (photometric) quantities are of two kinds, those used for photopic vision and those used for scotopic vision. The wording of the definitions in the two cases being almost identical, a single definition is generally sufficient with the appropriate adjective, photopic or scotopic added where necessary. The symbols for scotopic quantities are prime ()'v, I'v, etc), but the units are the same in both cases. Document Number: 82512 Rev. 1.4, 06-Oct-06 Symbols and Terminology Vishay Semiconductors The radiometric terms are used to describe the quantities of optical radiation. The relevant radiometric units are: In general, optical radiation is measured in radiometric units. Luminous (photometric) units are used when optical radiation is weighted by the sensitivity of the human eye, correctly spoken, by the CIE standard photometric observer (Ideal observer having a relative spectral responsivity curve that conforms to the V(O) function for photopic vision or to the V'(O) function for scotopic vision, and that complies with the summation law implied in the definition of luminous flux). Note: With a given spectral distribution of a radiometric quantity the equivalent photometric quantity can be evaluated. However, from photometric units without knowing the radiometric spectral distribution in general one cannot recover the radiometric quantities. Radiometric Terms, Quantities and Units Photometric Term Equivalent Radiometric Term Radiometric Term Symbol Unit Reference Radiant power, Radiant flux )e W IEC50 (845-01-24) Radiant intensity Ie W/sr IEC50 (845-01-30) Irradiance Ee W/m2 IEC50 (845-01-37) Radiant Exitance Me W/m2 IEC50 (845-01-47) Radiance Le W/(srm2) IEC50 (845-01-34) Table 1: Radiometric Quantities and Units Photometric Terms, Quantities and Units The photometric terms are used to describe the quantities of optical radiation in the wavelength range of visible radiation (generally assumed as the range Symbol Unit Reference )v: IEC50 (845-01-25) Luminous power or Luminous flux Radiant power or Radiant flux )e )v lm Luminous intensity Radiant intensity Ie Iv lm/sr = cd Iv: IEC50 (845-01-31) cd: IEC50 (845-01-50) Illuminance Irradiance Ee Ev lm/m2 = lx (Lux) Ev: IEC50 (845-01-38) lx: IEC50 (845-01-52) Luminous exitance Radiant exitance Me Mv lm/m2 IEC50 (845-01-48) Luminance Radiance Le Lv cd/m2 IEC50 (845-01-35) lm: IEC50 (845-01-51) Table 2: Photometric Quantities and Units Photometric units are derived from the radiometric units by weighting them with a wavelength dependent standardized human eye sensitivity V(O) - function, the so-called CIE-standard photometric observer. There are different functions for photopic vision (V(O) ) and scotopic vision (V'(O) ). In the following is shown, how the luminous flux is derived from the radiant power and its spectral distribution. The equivalent other photometric terms can be derived from the radiometric terms in the same way. 9 m2 4 m2 1 m2 1m 2m 3m Relation between distance r, irradiance (illuminance) Ee (Ev) and intensity Ie (Iv) The relation between intensity of a source and the resulting irradiance in the distance r is given by the basic square root rule law. An emitted intensity Ie generates in a distance r the irradiance Ee = Ie/r2. This relationship is not valid under near field conditions and should be used not below a distance d smaller than 5 times the emitter source diameter. Document Number: 82512 Rev. 1.4, 06-Oct-06 18145 www.vishay.com 39 Symbols and Terminology Vishay Semiconductors Using a single radiation point source, one gets the following relation between the parameter Ee, )e, r: d )e W E e = ----------- ------dA m 2 use ) , : = ---A- and get Ie = d ------2 d: r I W d) d: E e = ----------e- = I e -------- = ----e ------2 2 dA dA r m Examples 1. Calculate the irradiance with given intensity and distance r: Transceivers with specified intensity of Ie = 100 mW/sr will generate in a distance of 1 m an irradiance of Ee = 100/12 = 100 mW/m2. In a distance of 10 m the irradiance would be Ee = 100/102 = 1 mW/m2. 2. Calculate the range of a system with given intensity and irradiance threshold. When the receiver is specified with a sensitivity threshold irradiance Ee = 20 mW/m2, the transmitter with an intensity Ie = 120 mW/sr the resulting range can be calculated as r = www.vishay.com 40 Ie = -----Ee 120 ---------- = 20 6 = 2.45 m Document Number: 82512 Rev. 1.4, 06-Oct-06 Data Sheet Structure Vishay Semiconductors Data Sheet Structure Data sheet information is generally presented in the following sequence: • Description • Features • Applications • Absolute maximum ratings • Optical and electrical characteristics • Typical characteristics (diagrams) • Dimensions (mechanical data) Additional information on device performance is provided if necessary. The thermal resistance junction ambient (RthJA) quoted is that which would be measured without artificial cooling, i.e., under worst-case conditions. Temperature coefficients, on the other hand, are listed together with the associated parameters under "Optical and Electrical Characteristics". Description Typical Characteristics (Diagrams) The following information is provided: Type number, semiconductor materials used, sequence of zones, technology used, device type and, if necessary, construction. Also, short-form information on the typical applications and special features is given. Besides the static (dc) and dynamic (ac) characteristics, a family of curves is given for specified operating conditions. Here, the typical independence of individual characteristics is shown. Absolute Maximum Ratings These define maximum permissible operational and environmental conditions. If any one of these conditions is exceeded, this could result in the destruction of the device. Unless otherwise specified, an ambient temperature of 25 r3 °C is assumed for all absolute maximum ratings. Most absolute ratings are static characteristics; if they are measured by a pulse method, the associated measurement conditions are stated. Maximum ratings are absolute (i.e., interdependent). Any equipment incorporating semiconductor devices must be designed so that even under the most unfavorable operating conditions, the specified maximum ratings of the devices used are never exceeded. These ratings could be exceeded because of changes in supply voltage, the properties of other components used in this equipment, control settings, load conditions, drive level, environmental conditions and the properties of the devices themselves (i.e., ageing). Some thermal data is given under the heading "Absolute Maximum Ratings" (e.g., junction temperature, storage temperature range, total power dissipation). This is because it imposes a limit on the application range of the device. Document Number: 82635 Rev. 1.1, 29-Sep-05 Optical and Electrical Characteristics The most important operational optical and electrical characteristics (minimum, typical and maximum values) are grouped under this heading, together with associated test conditions supplemented with curves. Dimensions (Mechanical Data) In this section, important dimensions and connection sequences are given, supplemented by a circuit diagram. Case outline drawings carry DIN-, JEDEC or commercial designations. Information on angle of sensitivity or intensity and weight completes the list of mechanical data. Note: If the dimensional information does not include any tolerances, then the following applies: Lead length and mounting hole dimensions are minimum values. Radiant sensitive or emitting area respectively are typical, all other dimensions are maximum. Any device accessories must be ordered separately and the order number must be quoted. Additional Information Preliminary specifications This heading indicates that some information given here may be subject to changes. Not for new developments This heading indicates that the device concerned should not be used in equipment under development. The device is, however, available for present production. www.vishay.com 41 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors Taping, Labeling, Storage, Packing and Marking Vishay Semiconductor Standard Bar-Code Labels Standard bar code labels for finished goods The standard bar code labels are product labels and used for identification of goods. The finished goods are packed in final packing area. The standard packing units are labeled with standard bar code (3-of-9 bar code (code 39) conforming MIL-STD-1189) before transported as finished goods to warehouses. The labels are on each packing unit with Vishay Semiconductor GmbH specific data. The content of the label is show in the following table and figure 1. In future a change from 1D to 2D barcodes can be expected. That one will look as shown in figure 2. For transceivers the following logos are used inside the bar code label which are shown in figure 3. The following lead (Pb)-free categories (see figure 1 to figure 3) are meant to describe the lead (Pb)-free 2nd level interconnect terminal finish/material of components and/or the solder used in board assembly. e1 SnAgCu (shall not be included in category 2) e2 Sn alloys with no Bi or Zn excluding SnAgCu e3 Sn e4 Precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) e5 SnZn, SnZnx (no Bi) e6 contains Bi e7 low temperature solder (d 150 °C) containing Indium (no Bi) e0, e8, e9 symbol are unassigned Lead (Pb)-free category e3 – Sn Origin Machine (CPU) number QA acceptance seal Device type QA signature and date Plant location code Lead (Pb)-free logo Device selection code Date code Lot number Quantity RoHS compliance logo Working week day and shift 19873 Remark: Multi - Date Codes would be marked in the QA field of this label on top of the lead Figure 1. Barcode label, detailed description Terminations lead (Pb)-free designed 19874 ESD Totally lead (Pb)-free designed Lead (Pb)-free categories 19877 Figure 2. 2D barcode label (according the Barcode Standard for 2D Label PDF 417) for a lead (Pb)-free device, equivalent to that shown in figure 11. www.vishay.com 42 Figure 3. Logos inside the label Document Number: 82601 Rev. 1.7, 20-Sep-06 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors Moisture Proof Packing The reel with the taped components is packed in a moisture proof aluminum bag to protect the devices from absorbing moisture during transportation and storage. This bag finally is packed in a cardboard box. On the reel as well as on the bag and the box are labels, which are described in the following (see figure 4). This is an example and little variations may be between different plants. Pb-free information is part of the bar code label, but when it is missing a "lead (Pb)-free"-label (figure 8) may be attached. In addition the "Moisture-Sensitive Identification Label (MSID)" is applied (figure 9). Moisture Level Sticker BarCode ESD Sticker Label Aluminum bag Box 19880 0 Figure 7. Product (top) and taping label Reel 18298 Figure 4. Moisture proof packing Inside the aluminum bag with the reel are a desiccant bag and a humidity indicator (figure 5). 19881 Figure 8. Lead (Pb)-free logo 19878 Figure 5. Desiccant bag (example, left) and humidity indicator card 19882 On the reel are the barcode product label and taping label (figure 7) and a yellow ESD sticker (figure 6). Figure 9. Moisture-Sensitive Identification Label (MSID) 19879 Figure 6. ESD sticker Document Number: 82601 Rev. 1.7, 20-Sep-06 www.vishay.com 43 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors On the bag the same stickers as on the reel will be shown. In addition the moisture-sensitivity caution label as shown in figure 10 describes the storage and drying procedures. CAUTION This bag contains MOISTURE-SENSITIVE DEVICES LEVEL 4 1. Shelf life in sealed bag: 12 months at < 40 °C and < 90 % relative humidity (RH) 2. After this bag is opened, devices that will be subjected to soldering reflow or equivalent processing (peak package body temp. 260 °C) must be 2a. Mounted within 72 hours at factory condition of < 30 °C/60 % RH or 2b. Stored at < 5 % RH 3. Devices require baking befor mounting if: Humidity Indicator Card is > 10 % when read at 23 °C ± 5 °C or 2a. or 2b. are not met. 4. If baking is required, devices may be baked for: 192 hours at 40 °C + 5 °C/- 0 °C and < 5 % RH (dry air/nitrogen) or 96 hours at 60 °C ± 5 °C and < 5 % RH for all device containers or 24 hours at 125 °C ± 5 °C not suitable for reels or tubes Bag Seal Date: (If blank, see barcode label) Note: Level and body temperature defined by EIA JEDEC Standard JSTD-020 Figure 10. EIA JEDEC Standard JSTD-020 Level 4 label is included on all dry bags In the following two reels of different size are shown with the labeling (figure 11 and figure 12). Figure 12. 330-mm reel with labels. No labels on the rear. Lead (Pb)-free information is on the barcode label. Final Packing The sealed reel is packed into a cardboard box, which is 334 x 335 x 40 mm3 in size. A secondary cardboard box is used for shipping purposes, with the following sizes, slightly different for different production locations, see the following tables. Table 2. Secondary boxes Malaysia, location code 68 Size, Length x Width x Height mm x mm x mm Quantity of boxes 360 x 360 x 45 1 360 x 360 x 120 2 360 x 360 x 200 5 360 x 360 x 340 8 675 x 355 x 375 16 620 x 530 x 480 26 625 x 525 x 640 30 1000 x 600 x 580 60 Philippines, location code 19 Size, Length x Width x Height mm x mm x mm Quantity of boxes 360 x 360 x 130 2 380 x 380 x 260 5 370 x 360 x 620 11 730 x 380 x 570 20 On the boxes the same labels as on the bag will be used. 19889 Figure 11. 180-mm reel with labels. No labels on the rear. Lead (Pb)-free marking is not on the barcode; here an additional lead (Pb)-free sticker is applied. www.vishay.com 44 Document Number: 82601 Rev. 1.7, 20-Sep-06 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors Recommended Method of Storage Dry box storage is recommended as soon as the dry bag has been opened to prevent moisture absorption. The following conditions should be observed, if dry boxes are not available: • Storage temperature 10 qC to 30 qC • Storage humidity d60 % RH max. After more than 72 hours under these conditions moisture content will be too high for reflow soldering. In case of moisture absorption, the devices will recover to the former condition by drying under the conditions given in the label on the aluminium bag as shown in figure 5. Such an EIA JEDEC Standard JSTD-020 Level 4 label is included on all dry bags (see figure 10). ESD Precaution Proper storage and handling procedures should be followed to prevent ESD damage to the devices especially when these are removed from the Antistatic Shielding Bag. “Electro–Static Sensitive Devices”warning labels (figure 6) are affixed on the packaging. Order Information, Related Packing Units, Tape and Reel Size and Labeling In this document the packing and labeling information for IR transceivers is compiled. Part Description Quantity / Reel Orientation in tape for mounting pcs TFBS4650-TR1 Side view 1000 TFBS4650-TR3 Side view 2500 TFBS4652-TR1 Side view 1000 TFBS4652-TR3 Side view 2500 TFBS5700-TR3 Side view 2500 TFBS4711-TR1 Side view 1000 TFBS4711-TR3 Side view 2500 TFBS5711-TR1 Side view 1000 TFBS5711-TR3 Side view 2500 TFBS6711-TR1 Side view 1000 TFBS6711-TR3 Side view 2500 TFBS6712-TR1 Side view 1000 TFBS6712-TR3 Side view 2500 TFDU4300-TR1 Side view 750 TFDU4300-TR3 Side view 2500 TFDU4300-TT1 Top view 750 TFDU4300-TT3 Top view 2500 TFDU5307-TR1 Side view 750 TFDU5307-TR3 Side view 2500 TFDU5307-TT1 Top view 750 TFDU5307-TT3 Top view 2500 TFDU6300-TR3 Side view 2500 TFDU6300-TT3 Top view 2500 TFDU6301-TR3 Side view 2500 TFDU6301-TT3 Top view 2500 TFBS4710-TR1 Side view 1000 TFBS6614-TR3 Side view 2500 TFDU2201-TR1 Side view 750 TFDU2201-TR3 Side view 2250 TFDU4202-TR1 Side view 750 TFDU4202-TR3 Side view 2250 TFDU4203-TR1 Side view 750 TFDU4203-TR3 Side view 2250 TFDU4100-TR3 Side view 1000 TFDU4100-TT3 Top view 1000 TFDU6102-TR3 Side view 1000 TFDU6102-TT3 Top view 1000 TFDU8108-TR3 Side view 1000 TFDU8108-TT3 Top view 1000 TOIM4232 Top view 500 Table1. Transceiver tape drawing and reel size reference according to type order text Document Number: 82601 Rev. 1.7, 20-Sep-06 Tape Figure-No 14 14 14 14 14 15 15 15 15 15 15 15 15 16 16 17 17 16 16 17 17 16 17 16 17 18 18 19 19 19 19 19 19 20 21 20 21 20 21 22 Reel Reel No in Reel Table 1 2 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 2 2 2 2 2 2 1 2 1 2 1 2 3 3 3 3 3 3 2 www.vishay.com 45 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors Shape of Reel and Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Tape Width A max. N W1 min. W2 max. W3 min. Reel mm mm mm mm. mm mm W3 max. mm #1 16 180 60 16.4 22.4 15.9 19.4 #2 16 330 50 16.4 22.4 15.9 19.4 #3 24 330 60 24.4 30.4 23.9 27.4 (According EN 60286-3: 1998) Leader and Trailer Trailer no devices Leader devices no devices End Start min. 200 min. 400 Trailer Leader 96 11818 Figure 13. Leader and trailer Cover Tape Peel Strength According to IEC 286 Peel Strength: 0.1 N to 1.3 N (300 r10 %) mm/min 165q 180qpeel angle www.vishay.com 46 Document Number: 82601 Rev. 1.7, 20-Sep-06 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors Tape Dimensions 19867 Drawing-No.: 9.700-5296.01-4 Issue: 1; 08.12.04 Figure 14. Tape for 1.6 - mm package side view oriented 19868 Drawing-No.: 9.700-5294.01-4 Issue: 1; 08.12.04 Figure 15. Tape for 1.9 - mm package side view oriented Document Number: 82601 Rev. 1.7, 20-Sep-06 www.vishay.com 47 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 16. Tape for 2.5 - mm package side view oriented 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 17. Tape for 2.5 - mm package top view oriented www.vishay.com 48 Document Number: 82601 Rev. 1.7, 20-Sep-06 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors 19869 Drawing-No.: 9.700-5299.01-4 Issue: 1; 18.08.05 Figure 18. Tape for 2.74 - mm package side view oriented 19870 Drawing-No.: 9.700-5227.01-4 Issue: 3; 03.09.99 Figure 19. Tape for 2.75 - mm package side view oriented Document Number: 82601 Rev. 1.7, 20-Sep-06 www.vishay.com 49 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors 19871 Drawing-No.: 9.700-5297.01-4 Issue: 1; 08.04.05 Figure 20. Tape for 4.0 - mm package side view oriented 19872 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 21. Tape for 4.0 - mm package top view oriented www.vishay.com 50 Document Number: 82601 Rev. 1.7, 20-Sep-06 Taping, Labeling, Storage, Packing and Marking Vishay Semiconductors 19876 Drawing-No.: 9.700-5284.01-4 Issue: 1; 24.07.03 Figure 22. Tape for SO - 16 package top view oriented Marking of Transceiver Modules Date code 6 1 0 0 V Y W W X X Package 2: no specific Selection Vishay Year Type 4: 115 kbit/s, SIR Work week Manufacturing 5: 1 Mbit/s, MIR location 0: Standard, SMD 6: 4 Mbit/s, FIR 3: DIL, Through Hole 7: RC - Receiver added Note: V and XX are optional and 8: 16 Mbit/s, VFIR can be omitted when the space for marking is limited 1: 4 mm (leadframe) 2: 2.75 mm (leadframe) Example: 3: 2.5 mm (leadframe) The marking 4650V61268 6: PCB-based identifies a 7: PCB-based, 6 pin 17273-1 TFBS4650, produced by Vishay in week 12 of year 2006 at the location 68 (Krubong, Malaysia) Document Number: 82601 Rev. 1.7, 20-Sep-06 www.vishay.com 51 Environmental Health and Safety Policy Vishay Semiconductors www.vishay.com 52 Document number: 81375 Rev. 1.0, 18-Aug-06 Surface Mount Assembly Instruction Vishay Semiconductors Soldering Process When assembling IrDC transceivers on a printed circuit board (PCB), it is useful to have an understanding of the properties of the materials used during manufacturing. While IrDC transceivers use semiconductor dice and other constituents processed in the semiconductor industry, there are considerable differences between transceivers and other semiconductor devices. One of the most important differences is the molding material that is used for its manufacture. Packaging material used for transceivers must be transparent to infrared radiation in order to emit and receive optical signals. However, visible light might disturb the proper performance of the transceiver ASIC. A special dye is mixed into the encapsulant to block visible light. This results in the transceiver appearing black. The need for good optical performance requires the use of pure resin. No other ingredients can be added. The encapsulant used for standard integrated circuits (IC), however, is a mixture of resin (typically 30 %) and other ingredients (e.g. nearly 70% silica sand). This mixture results in more uniform mechanical properties of semiconductor die, leadframe and encapsulant. Figure 1 and figure 2 show the difference between filled and unfilled epoxy resin. The following table 1 shows the main differences between the two types of mold compound 18052 1 Figure 1. IC molding compound (30 % resin) 18053_1 Figure 2. Clear molding compound (100 % resin) Table 1 Characteristics Optical Properties IC Mold Compound IrDC Mold Compound Light Blocking Transparent High Low (brittle) Hardness Coefficient of thermal expansion Glass transition temperature Low (matched to leadframe & die) High High (160 °C) Low (120 °C to 140 °C) Thermal conductivity High Low Moisture ingress Low High A standard molded integrated circuit will have its constituents nicely matched to each other in terms of thermal expansion. The typical IC package Document Number: 82602 Rev. 1.3, 20-Sep-06 is rather free of mechanical stress compared to an IrDC transceiver, which experience more mechanical stresses during manufacturing. www.vishay.com 53 Surface Mount Assembly Instruction Vishay Semiconductors Moisture Sensitivity The high rate of moisture ingress is another property of the optical clear molding compound. The saturation value for room temperature of moisture intake is roughly a factor of ten larger than for filled molding compound. Due to this high rate of moisture ingress transceivers are more prone to the "popcorn effect". Any possible void (delamination, bubble) inside the package will be filled very quickly with moisture. Even the whole package can soak up a considerable amount of moisture. Whenever the package is heated up above the boiling point of water, a very high vapor pressure builds up inside the voids. This pressure can cause the package to crack or creates severe delamination. The amount of moisture absorbed by the package is determined by the exposure time to humid air. The exposure time allowed for a particular package is defined by a moisture sensitivity level (MSL) according to JEDEC standards J-STD-020 and JESD22-A113. Vishay transceivers are designed to withstand three subsequent passes through a reflow soldering oven using our recommended reflow temperature-time profile when the package has been exposed not longer than 72 hours to environmental conditions of d 30 °C/60 % RH. This correlates to MSL 4. The parts will be delivered in a moisture barrier bag containing desiccant and a humidity indicator card. As long as the parts are stored in the sealed bag, the performance will not degrade. As soon as the bag is opened, the material should be consumed within 72 hours or must be stored in a dry place (chamber which is purged with a dry gas like air or nitrogen) or baked according to the sticker on the reel. Reflow Soldering Vishay Semiconductor transceivers are surface mount devices and are designed to be assembled to printed circuit boards (PCB) using reflow soldering. State of the art for reflow soldering is the use of a so-called convection reflow oven. Recommendations for reflow conditions can only be given in general terms since each PCB should be considered individually depending on the size and distribution of components. Because IrDA transceivwww.vishay.com 54 ers are more sensitive to thermal stress than most other components, it is recommended that these be used to determine the optimum soldering conditions. If the subsequent recommendations are followed excellent results can be achieved despite the limitations of the materials used. Reflow Solder Profile There are two distinct tasks for the temperature-time profile of the solder process: • Prepare the components for the stress at the soldering temperature. • Solder the components to the PCB. The main idea behind this pre-soldering preparation (neglecting the solder paste activation and the like) is to have a very small temperature difference between all components. This allows for a low peak temperature and damage free soldering. There are two different profile types used in industry nowadays. The most often used type in the past and still today is the ramp-soak-spike profile (RSS). The convection oven allows for a ramp-to-spike profile (RTS), and the application of this type is increasing. A solder profile consists roughly of three distinct phases. • Pre-heating or Soak Phase: For standard components, this is the phase where all parts should come roughly to the same temperature. This is achieved either by keeping the PCB for a certain time at a specific temperature (RSS) or ramp-up the temperature at a certain speed (RTS) to have all parts at all times of the profile at the same temperature. • Soldering: During this phase, the actual soldering takes place. We recommend not to exceed 260 °C peak temperature and the device should not be exposed to higher temperatures than 255 °C for more than 30 s (TFDUxxxx) or 20 s (TFBSxxxx) depending on the type of transceiver • Cool Down: The PCB should be cooled down rather quickly to have a fine grain solder joint. As outlined previously a transceiver package has built-in mechanical stress, which should be reduced before submitting the part to the actual solder temperature. This stress is relieved during the soak phase. Document Number: 82602 Rev. 1.3, 20-Sep-06 Surface Mount Assembly Instruction Vishay Semiconductors Depending on the encapsulant material used for packaging, the best soak temperature is in the range of 140 °C to 160 °C and the time interval is 120 s to 180 s. As a rule of thumb, the temperature should be slightly above the glass transition temperature and the dwell time must be long enough to allow for stress relief. This is most conveniently realized with an RSS profile. For RTS profiles, the low thermal conductivity compared to standard components should be considered. To get the transceiver into thermal equilibrium with the PCB and allow for internal stress relief the thermal ramp-up rate normally must be lower than for standard components. Vishay Semiconductor recommended RSS Profile Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is quite highly depending on the experience of the operator. Nevertheless, we added a chapter, describing manual soldering and desoldering. Before soldering or desoldering be sure that the devices (or boards) are correctly dried corresponding to given MSL-condition. See the equivalent standard JEDEC J-STD033A, "Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices". Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4 if not otherwise specified in the data sheet. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 275 T ≥ 255 °C for 10 s....30 s 250 225 Tpeak = 260 °C T ≥ 217 °C for 70 s max Temperature/°C 200 175 150 30 s max. 125 90 s...120 s 100 70 s max. 2 °C...4 °C/s 75 2 °C...3 °C/s 50 Pick & Place 25 0 0 50 100 150 200 250 300 350 Time/s 19693 Vishay Semiconductor recommended RTS Profile 280 Tpeak = 260 °C max. 260 240 220 Temperature/°C < 4 °C/s 160 1.3 °C/s 140 120 Due to the non-symmetric package - very common for opto-electronic parts - the pick-up position can not be expected in any case at the center of the package. The best pick-up location is indicated in the data sheet drawings as "mounting center". It coincides with the center of the hole in the pocket of the carrier tape. 200 180 For reliable pick and place operation an adequate flat area on the topside of the module is important. Vishay Semiconductors always design transceivers to have a flat surface on the topside for pick and place. Time above 217 °C t ≤ 70 s <2 °C/s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 60 40 20 0 0 50 100 19694 Document Number: 82602 Rev. 1.3, 20-Sep-06 150 200 250 300 Time/s www.vishay.com 55 Surface Mount Assembly Instruction Vishay Semiconductors Manual Soldering Although IrDC transceivers are surface mount components and therefore designed for reflow soldering, it is possible to solder these manually using soldering irons. Be sure that the devices are correctly dried corresponding to the MSL4 conditions. Based on long-standing experience of some of Vishay Semiconductors customers the following rules should be observed: • Use standard Pb-Sn or Sn solder • Use a high power (at least 25 W) temperature controlled soldering iron • Soldering iron temperature 345 °C ± 5 °C • Soldering time 1 second maximum per lead • Avoid any mechanical stress to the leads during soldering or cool down 18272 18270 Step 1: Start with one pad only and get some solder on it. 18271 Step 2: Place the transceiver at its appropriate position www.vishay.com 56 Step 3: Solder the lead to lead pad prepared in step 1 18273 Step 4: Solder quickly and skillfully the remaining leads Document Number: 82602 Rev. 1.3, 20-Sep-06 Surface Mount Assembly Instruction Vishay Semiconductors Desoldering Hot air method If it is necessary to remove a transceiver from a PCB for replacement or investigation without damage the same constraints apply as for soldering. Excessive heat or mechanical strain (e.g. usage of pliers) could result in cracks or damaged wire bonds. Bake the whole board according to MSL4 before removing the part to avoid moisture effects. Vishay recommends two procedures which have been found to give the most consistent results: • Nozzle temperature 400 °C ± 10 °C • Lead temperature (nozzle 5 cm from the device) 270 °C ± 10 °C • Hold device with long tweezers • Apply air at an angle of 45° to the lead moving the nozzle to heat all of the leads or apply the heat from the back side when no components are mounted on the back under the transceiver • When the solder melts (< 4 s) push gently or lift device to lift off the leads It is important that as little mechanical force as possible is applied to the leads when the package is hot and softened by the heat. Any excessive force can tear off the leads causing internal damage to the wire bonds. Soldering iron method • Use a high thermal capacity soldering iron (> 25 W) at 360 °C ± 10 °C • Use a solder iron with a very broad tip • Hold device with long nose tweezers • Heat leads • Do not apply force until the solder melts • Push the unit away without force 18274 Use a broad tip for desoldering with a solder iron 18276 When the solder is completely molten (< 2 s) push the transceiver gently off the solder pads on the PCB 18275 Apply heat uniformly to the whole set of leads Document Number: 82602 Rev. 1.3, 20-Sep-06 www.vishay.com 57 Window Size in Housings Vishay Semiconductors Window Size in Housings In Figure 1 and 2, the minimum window size in relation to the distance between the window and the transceiver is described. Generally speaking, a 10 % transmission loss should be accounted for in the design calculations so that output power and input sensitivity requirements are met for the system design. The external filter should be placed squarely against the transceiver otherwise reflection may cause emitter power loss or a decrease in receiver sensitivity in the system. Optically transparent window materials are available from different sources, e.g. Bayer, GE, Rohm & Haas (see “Source for Accessories”). The optical window must be a minimum size of d1 x d2 rectangular or elliptical so as not to reduce the IrDA performance. The following expressions apply to figures 1 to 4. d1 = w + 2x = w + 0.54a d2 = h + 2x = h + 0.54a where x = a tan 15q Dimensions of d1, d2, and a are given in mm. The dimensions for w and h for the different packages are as follows: Device Package Type w (mm) h (mm) Baby Face (TFDUx1xx) family 9.7 4.0 2.5 mm family (as TFDUx3xx) 8.5 2.5 1.9 mm family (as TFBSx7xx) 6.2 2.0 1.6 mm family (as TFBSx6xx) 7.0 1.7 Micro Face (as TFDUx2xx) 5.7 2.7 Window 15 ° x a h d2 x 15 ° 18062-1 Figure 2. View from the side, example Baby Face package 15 ° w 15 ° Window a d1 x x 18063-1 Figure 3. View from above, example Micro Face package Window 15 ° w 15 ° 15 ° x Window a h d2 x d1 x a x 18061-1 15 ° 18064-1 Figure 1. View from above, example Baby Face package www.vishay.com 58 Figure 4. View from the side, example Micro Face package Document Number: 82506 Rev. 1.4, 09-Sep-05 Window Size in Housings Vishay Semiconductors Some recommendations to enhance robustness of your design: • Do not make the window larger than needed, otherwise you will unnecessarily increase the influence of ambient (sun) light. • The larger the distance a, the better the shielding against the ambient light. • The outer window surface may be recessed against the surrounding case material to protect the window from scratches, abrasion, dust, etc. Recessed window avoiding scratches Recessed transceiver is recommended to shield against ambient (sun)light ±15° Avoid vignettation but limit the reception angle 15809 Figure 5. ? ? 15 810 Figure 6. Avoid an unintentional lens effect of your window Document Number: 82506 Rev. 1.4, 09-Sep-05 www.vishay.com 59 Sources for Accessories and Testing Vishay Semiconductors Sources for Accessories IrDA Related References Infrared Data Association IrDA P. O. Box 3883 2855 Mitchell Drive, Suite 107 Walnut Creek, CA 94598 Phone: +1 925 943-6546 Fax: +1 925 943-5600 Email: [email protected] http://www.irda.org Software Microsoft Corporation IrDA is supported by Windows 95®‚ Windows 98®, Windows NT®, Win CE®Windows 2000®, Windows XP®and Palm PC®platforms. IrDA device drivers are either already included in the software package or can be downloaded from the Microsoft website. One Microsoft Way, 5/2153 Redmond, WA 98052–6399, USA http://www.microsoft.com www.vishay.com 60 ACTiSYS ACTiSYS Corp has been a leading supplier of Infrared wireless IrDA and ASK–IR protocol software and adapters for 115.2 kbit/s and 4 Mbit/s since 1990. ACTiSYS also provides test software and hardware for IRDA compatibility testing. ACTiSYS 48511 Warm Springs Blvd., Suite #206 Fremont, CA 94539 USA Phone: +1 510-490-8024 http://www.actisys.com Laplink Software Laplink Software Inc. 10210 NE Points Drive, Suite 400 Kirkland, WA 98033, USA Phone: +1 425 952-6000 Fax: +1 425 952-6002 http://www.travsoft.com/ Document Number: 82600 Rev. 1.5, 20-Sep-06 Sources for Accessories and Testing Vishay Semiconductors Plastics Korea In our products we use polycarbonate (PC) and polymethylmethacrylate (PMMA) for optical window and as filter material. Therefore we recommend these materials and list some sources. www.bayer.co.kr Polycarbonate (PC) PC is available under many different trade names and supplied by many manufacturers and distributors. A comprehensive list can be found at http://www.matweb.com/reference/polycarbonate mfr.asp Some product names of PC material Product Calibre Durolon Enduran Jupilon Lexan Lupoy Makrolon Wonderlite Manufacturer DOW Policarbonatos do Brasil GE Mitsubishi GE LG Chemical Bayer Chi Mei Some manufacturers are listed below. Contact them for local distributors. Bayer "Makrolon®" http://www.plastics.bayer.com USA Bayer MaterialScience LLC Pittsburgh, Pennsylvania 100 Bayer Road Pittsburgh, PA 15205-9741 www.BayerMaterialScienceNAFTA.com Phone: 800-662-2927 Phone: +1 (412) 777-2000 Fax: +1 (412) 777-3899 The Dow Chemical Company www.dow.com (see Calibre polycarbonate resins) General Electric Plastics "Lexan®" EUROPE GE Plastics B.V. Plasticslann 1 Bergen op Zoom 4612PX Netherlands Phone: +31 164-292911 http://www.geplastics.com Germany GE Plastics GmbH Eisenstrasse 5 65428 Rüsselsheim Postfach 1362-65402 Phone: +49 6142 6010 USA GE Plastics Technology Centre 1 Plastics Avenue Pittsfield / MA 01201 Phone: +1 413 448-5800 Fax: +1 413 448-7493 GERMANY Bayer MaterialScience AG RSC EMEA Leverkusen, Deutschland www.bayerplastics.com Document Number: 82600 Rev. 1.5, 20-Sep-06 www.vishay.com 61 Sources for Accessories and Testing Vishay Semiconductors PMMA (Polymethylmethacrylate) PMMA is available under many different trade names and supplied by many manufacturers and distributors. Some product names of PMMA material Product Acrylite Acryrex Acrystex Altuglas Degalan Diakon Oroglas/Altuglas Plexiglas Manufacturer Cyro Chi Mei Chi Mei Atoglas Degussa-Röhm Lucite Arkema (Atoglas) Degussa-Röhm Some manufacturers are listed below. Contact them for local distributors. Altuglas Based on the history of Rohm & Haas, formerly known as Atoglas and Arkema www.plexiglas.com www.altuglas.com www.altumax.com USA Altuglas International www.plexiglas.com/altuglas/plex2.cfm Altuglas International c/o Arkema 2000 Market Street Philadelphia PA 19103 Phone: +1 215 419-7000 Fax: +1 215 419-7591 Chi Mei Corporation No. 59-1, San Chia, Jen Te, Tainan County, Taiwan 71702 Phone: +886-6-2663000.2665000 Ext. 1372 Fax: +886-6-2665555~7 [email protected] Lucite www.lucite.com www.vishay.com 62 Cyro Industries Cyro is the North American arm of the Röhm/Degussa group Technical Service Orange, Conn. 06477 Phone: +1 203 799-4066 www.cyro.com For Europe see www.degussa.com Polycast Technology Corporation 70 Carlisle PI Ste 1 Stamford, CT 06902-7630 Phone: +1 203 327 6010 Distributors (USA) Calsak Corporation 200 W. Artesia Blvd. Compton, CA 90220 Phone: (800) 743-2595 +1 310 637-2000 Fax: +1 310 637-3696 E-mail: [email protected] www.calsakpolymers.com Plastic Sales Incorporated 849 W. 18th St. Costa Mesa, Calif. 92627 Phone: +1 714 645-6860 Regal Plastics Southern Region 2356 Merrell Road Dallas, TX 75229 Phone: +1 972 484-0741 or (800) 441-1553 Fax: +1 972 484-0746 Specialty Manufacturing Inc. 6790 Nancy Ridge Dr. San Diego, CA 92121-2230 Phone: +1 858 450-1591 Phone: 800 491-1652 Fax: +1 858 450-0400 Document Number: 82600 Rev. 1.5, 20-Sep-06 Sources for Accessories and Testing Vishay Semiconductors Interface Circuits National Semiconductor Corporation National Semiconductor Corporation, a Fortune 500 company headquartered in Santa Clara, California, develops and manufactures semiconductor products for high growth markets in the electronics equipment industry. Their Super I/O ICs provide IrDA encoding/ decoding function as well as single chip solutions for floppy disk control, keyboard control, dual UARTs, parallel port and IDE interface. World Headquarters National Semiconductor Corporation 2900 Semiconductor Dr. P. O. Box 58090 Santa Clara, California USA 95052–8090 Phone: +1 408 721–5000 http://www.national.com Standard Microsystems Corporation (SMSC) Standard Microsystems Corporation (SMSC) is a worldwide supplier of MOS/VLSI integrated circuits (ICs) for the personal computer industry. SMSC has a leading position in input/output (I/O) circuits for PCs with over 80 million units shipped and, additionally, supplies ICs for local area networks and embedded control systems. Standard Microsystems Corporation 80 Arkay Drive P.O. Box 18047 Hauppauge, New York 11788–8847 Toll Free: 800–443–SEMI (7364) – USA and Canada Only Phone: +1 631 435–6000 Email: [email protected] http://www.smsc.com SigmaTel, Inc. European Headquarters National Semiconductor Corporation Livry-Gargan-Str. 10 82256 Fürstenfeldbruck Germany +49 (0) 81 41 35-0 [email protected] Deutsch: +49 (0) 69 9508 6208 English: +44 (0) 870 240 21 71 Francais: +33 (0) 141 91 87 90 Document Number: 82600 Rev. 1.5, 20-Sep-06 SigmaTel Worldwide Headquarters Sigma Tel, Inc. 1601 S. Mo Pac Expressway, Suite 100 Austin, TX 78746 Phone: +1 512-381-3700 Fax: +1 512-744-1700 [email protected] http://www.sigmatel.com SigmaTel Asia, Limited Unit 3613-14, 36/F, Tower 6 The Gateway, Harbour City 9 Canton Road Tsimshatsui, Kowloon Hong Kong Phone: +852-2175 5225 Fax: +852-2175 5050 [email protected] www.vishay.com 63 Sources for Accessories and Testing Vishay Semiconductors Microprocessors AMD AMD is a global supplier of integrated circuits (ICs) for the personal and network computer and communications markets. The company produces processors for Microsoft® Windows® compatible PCs, flash memories, products for communications and networking applications. AMD's Elan family of 32-bit micro controllers provides support for IrDA along with other features for mobile computing applications. AMD One AMD Place P. O. Box 3453 Sunnyvale, CA 94088–3453, USA Phone: +1 408 749–4000 www.amd.com Hitachi Semiconductor America The 32-bit SuperH RISC engine series is the high end of Hitachi’s micro controller and microprocessor product lines. This advanced product family provides a solid roadmap for meeting embedded controller and microprocessor requirements with the most efficient solutions for emerging applications. www.hitachi.com Hitachi Semiconductor America 2000 Sierra Point Parkway Brisbane, CA 94005, USA Phone: +1 800 285–1601 Motorola Motorola manufactures a wide variety of microprocessors suitable for embedded and hosted applications that contain built–in support for IrDA. Many of their microprocessors can be connected to industry typical IrDA transceivers directly, without any interface support electronics. In support of the processors, Motorola provides IrDA software implementing the full IrDA stack. Motorola 6501 William Cannon Drive West Austin, Texas 78735, USA http://www.mot.com Philips Semiconductors Philips Semiconductors provides the TwoChipPICTM and TwoChipPIC PlusTM, dual 32-bit enhanced MIPS RISC chipsets which provide integrated solutions for Personal Digital Assistants (PDAs), Personal Intelligent Communicators (PICs), and Handheld PCs (H/PCs) for Windows®‚CETM. www.philips.com www.vishay.com 64 Document Number: 82600 Rev. 1.5, 20-Sep-06 Sources for Accessories and Testing Vishay Semiconductors Test Houses - Interoperability Testing IrDA Test Labs (from IrDA-website www.irda.org) The function of these Test Labs is to provide an independent assessment of the interoperability of an IrDA product. In addition, Test Labs may also provide services and consulting to resolve design problems when they occur. It is up to each Test Lab to set their fees for the services provided. The primary responsibility of Test Labs is: • To provide testing services to assure IrDA interoperability and compliance. • To perform the Interop tests and if authorized perform full compliance tests necessary to verify reference products. • To present the Qualified Product certificate to products that pass the tests as defined by IrDA. • Report successful products to the IrDA office for registration. In providing the IrDA Interop testing services, Test Lab ensures that: • The tests, procedures and processes conducted are the most up to date as defined by IrDA and that they are an advocate for the enduser in conducting the tests. • IrDA policies and procedures are complied with. • Tools and equipment are available for conducting the tests. • Other services may also be provided related to IrDA such as consulting and troublesshooting. This is the independent decision of the individual Test Lab. Independent Test Lab Locations that can assist in the validation of product qualification are: ICT Korea, Co., Ltd. 5F Bogwang Bldg., 249-14 Yangjae-2Dong, Seocho-Gu, Seoul, Korea Web: www.ictk.co.kr Contact: Mr. Kwanhoon Lee, Researcher & Overseas Management at [email protected] Testing Type: IrFM Waseda University Test Lab Tokyo, 160-0074, Japan Tel: 81-3-5286-3114 Contact: Mitsuji Matsumoto at [email protected] Testing Type: IrReady Document Number: 82600 Rev. 1.5, 20-Sep-06 ACTiSYS Corp. 48511 Warm Springs Blvd., Suite 206, Fremont, CA 94539, USA Tel: (510)490-8024 Fax: (510)623-7268 www.actisys.com Contact: Dr. Keming Yeh at [email protected] Testing Type: IrReady ACTiSYS (Asia) Corp. 3rd Floor, #12, Prosperity 2nd Rd., Science Park, Hsin-Chu City, Taiwan Tel: +886-3-578-5161 Fax: +886-3-578-5164 Contact: Lawrence Yang at [email protected] Testing Type: IrReady Couleur Communication Ecriture CCE, France Immeuble Grenat, 3 av. Doyen Louis Weil, 38000 Grenoble, France Tel: +33 4 76 48 86 30 Fax: +33 4 76 96 41 79 Web: www.affixcce.com Contact: Mr. Serge Veyres, Director at [email protected] Testing Type: IrReady OPEN INTERFACE, INC. 2-15-12 Shinyokohama Kouhoku-ku, Yokohama-city, Kanagawa, 222-0033 Japan Tel: +81-45-476-3900 Fax: +81-45-476-3689 Web: www.oii.co.jp Contact: Mr.Tatsuo Iwasaki, Director of Technical Dept. 1 at [email protected] Ms.Kayoko Yamanashi, Groupe Manager of IrDA Groupe Testing Solution Center at [email protected] Testing Type: IrReady, IrFM www.vishay.com 65 Ambient Light and Electromagnetic Interference Vishay Semiconductors Ambient Light and Electromagnetic Interference IrDA specifies normative tests, with specific ambient conditions, under which IrDA applications must be able to operate within the IrDA specifications. These normative conditions are part of the physical layer specification IrPHY 1.4, Appendix A. In the following these four essential requirements are quoted from the original standard: Background Light and Electromagnetic Field There are four ambient interference conditions in which the receiver is to operate correctly. The conditions are to be applied separately. 1. Electromagnetic field: 3 V/m maximum Refer to IEC 61000-4-3 test level 2 for details. (For devices that intend to connect with or operate in the vicinity of a mobile phone or pager, a field of 30 V/m with frequency ranges from 800 MHz to 960 MHz and 1.4 GHz to 2.0 GHz including 80% amplitude modulation with a 1 kHz sine wave is recommended. Refer to IEC 61000-4-3 test level 4 for details. The 30 V/m condition is a recommendation; 3 V/m is the normative condition.) 2. Sunlight: 10 kilolux maximum at the optical port This is simulated with an IR source having a peak wavelength within the range 850 nm to 900 nm and a spectral width less than 50 nm biased to provide 490 μW/cm2 (with no modulation) at the optical port. The light source faces the optical port. This simulates sunlight within the IrDA spectral range. The effect of longer wavelength radiation is covered by the incandescent condition. 3. Incandescent Lighting: 1000 lux maximum This is produced with general service, tungsten-filament, gas-filled, inside-frosted lamps in the 60 Watt to 150 Watt range to generate 1000 lux over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The source is expected to have a filament temperature in the 2700 to 3050 degrees Kelvin range and a spectral peak in the 850 nm to 1050 nm range. 4. Fluorescent Lighting : 1000 lux maximum This is simulated with an IR source having a peak wavelength within the range 850 nm to 900 nm and a spectral width www.vishay.com 66 of less than 50 nm biased and modulated to provide an optical square wave signal (0 μW/cm2 minimum and 0.3 μW/cm2 peak amplitude with 10 % to 90 % rise and fall times less than or equal to 100 ns) over the horizontal surface on which the equipment under test rests. The light sources are above the test area. The frequency of the optical signal is swept over the frequency range from 20 kHz to 200 kHz. Due to the variety of fluorescent lamps and the range of IR emissions, this condition is not expected to cover all circumstances. It will provide a common floor for IrDA operation. Electromagnetic Interference (EMI) Standards The IrDA EMI specification is similar to the conditions specified by the standard conditions used for European "CE" certification. The standards to be taken into account are specified as IEC standards or equivalent EN standards IEC/EN 61000-4-3: "Electromagnetic compatibility (EMC) - Part 4: Testing and measurement techniques - Section 3: Radiated, radio-frequency, electromagnetic field immunity test". IrDA doesn’t specify the immunity to conducted disturbances. However, this is also necessary for CE certification for the final product. See for that: IEC/EN 61000-4-6: "Electromagnetic compatibility (EMC) - Part 4: Testing and measurement techniques - Section 6: Immunity to conducted disturbances, induced by radio-frequency fields". For mobile phone applications the conditions are listed in ETSI EN 301 489-1 Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements ETSI EN 301 489-7 ElectroMagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS) Document Number: 82511 Rev. 1.4, 20-Sep-06 Ambient Light and Electromagnetic Interference Vishay Semiconductors Testing The Vishay Semiconductors transceivers for IrDA applications are tested according the standards in the frequency range of 15 kHz (the standard starts at 150 kHz) to 80 MHz and for mobile phone frequencies in the extended range of 700 MHz to 2100 MHz covering the 800 MHz, 900 MHz, 1800 MHz, and 1900 MHz mobile phone applications. The test capabilities also include frequencies up to 3000 MHz to cover the 2400 MHz band. In the frequency range of 700 MHz to 3000 MHz a GTEM 250 Cell with a field strength test capability of up to 500 Vrms/m is used. This RF signal is AM modulated by 217 Hz, 80 % modulation depth, GSM equivalent burst duration of 550 μs. Another tool available for testing is DPI (direct power injection). In the lower frequencies (15 kHz to 80 MHz) strip line boxes are used with a maximum applied field of about 80 Vrms/m. The RF signal is AM modulated by 1 kHz, 80 % modulation depth. In both ranges the transceivers are tested for the specified Bit Error Ratio (BER). The IrDA specified field strengths are sufficient for normal applications. However, when transceivers are operated close to an antenna, much higher field strengths may occur. An electromagnetic compatibility (EMC) of 30 V/m is not sufficient when the transceiver is built into a mobile phone close to an antenna. Experience shows that a minimum of 100 V/m is necessary in the case when pick-up in the wired circuit is avoided. Board – Layout and EMI In most of the GSM Applications - EMI is not caused by the transceivers. At these frequencies very strong (and resonant) coupling to the wiring from and to the transceiver can occur. Therefore all connecting lines should be sandwiched between grounded layers and these lines should be handled like strip lines and terminated. Transceiver inputs/ outputs detect the RF signal when the signal voltage is above the threshold. In 3 V applications, using DPI test method, it was verified that applied GSM signals with RF voltages of more than 1.5 V trigger the input. Therefore it has to be pointed out, that a suitable circuit layout and correct termination of lines is the major issue when discussing the EMI behavior of transceivers. The design goal for the transceiver itself (when used in mobile phones) is to withstand field strength of 300 V/m when terminated lines are used and no RF signals above the threshold are applied. Document Number: 82511 Rev. 1.4, 20-Sep-06 The internal shielding mechanism in the transceivers is efficient and additional metal EMI shields are not necessary. Additional metal shielding has no or even worse effect on the EMI behavior. Interference with Optical Light (Radiation) Sources Unmodulated sources of optical radiation are e.g. sunlight and incandescent lamps. The spectra of both are different, therefore the eye sensitivity related visible impression of a source (measured e.g. in lux or lumen per Watt) is quite different, also in the case when the optically generated detector current (A) in a Si-detector might be the same. The Silicon detector absorption characteristic defining the detector sensitivity is very different from the human eye. The invisible infrared part of the radiation of incandescant light is much larger compared to sunlight and more efficiently detected. Therefore the incandescent lamp is a more disturbing source for a Silicon receiver than sunlight, same illuminance assumed. Such unmodulated sources generate a background current in the photo detector, which generates noise, and offsets and displacements of the operating conditions. Vishay typically specifies and test designs for higher values than given by the standard. Vishay is testing with vertical incidence on the optical axis, a condition much worse than the IrDA given condition with irradiating the optical test setup from the ceiling. Fluorescent Lighting Fluorescent Lamps and especially Compact Fluorescent Lamps operated with electronic ballasts generate a quite strong infrared radiation modulated with a wide electrical spectrum. The IrDA specified value of 3 mW/m2 reflects the worst-case irradiance in about a meter distance of a fluorescent lamp. In this case also Vishay is testing with vertical incidence on the optical axis, a condition much worse than the IrDA given condition with irradiating the optical test setup from the ceiling. The majority of the Vishay Semiconductors transceivers are specified with a no-output level of 4 mW/m2, an additional safety margin vs. the IrDA specified value. www.vishay.com 67 Eye Safety of Diode Emitters Vishay Semiconductors Eye Safety of Diode Emitters Since 1993, the International Electrotechnical Committee (IEC) and the European Committee for Electrotechnical Standardization (CENELEC, officially recognized as the European Standards Organization in its field by the Commission in Directive 83/189/EEC) have included Diode Emitters1) such as IREDs2) and LEDs3) in the laser safety standard. LEDs and lasers are technologically similar. However, the different radiance of LEDs compared to lasers was not taken into account. This resulted in LEDs being incorrectly assessed concerning eye safety. In the 1997 edition of the standard EN 60825-1 (and the IEC equivalent IEC 60825-1) the basic assessment errors were corrected. The standard was further revised in January 2001. Amendment 2 was added (IEC60825-1 Amd. 2 Ed. 1.0) and is available at www.iec.ch. Based on the parallel voting process, this standard is also effective as a CENELEC document, EN60825-1 Amendment 2. Amendment 2 allows for a large increase in exposure limits, especially for the extended sources such as conventional LEDs and IREDs. The standard describes the Maximum Possible Exposure (MPE) and the Accessible Emission Levels (AEL) for the human eye and skin. The safe emission level is dependent on exposure time, wavelength, virtual source size and other parameters. For extended sources like LEDs, the apparent or virtual source size is the most important parameter in assessing risk and shall be specified in the component manufacturer's data sheet. Given the revised exposure limits, under normal operating conditions the MPE and AEL values are difficult to exceed when using conventional LEDs. Also, recognizing the low risk emissions of these sources, Amendment 2 eliminated the single fault condition for standard LEDs. Worldwide, no eye damage by LEDs has ever been reported. Diode Emitters efficiency is still increasing. Especially at the shorter wavelengths, a risk due to blue light effects, called blue light hazard, may occur and shall be considered. By definition, Laser Class 1 devices are safe under all reasonably foreseeable conditions. All of Vishay's IrDA transceivers and LEDs are rated as Class 1 devices when operated within specifications. The datasheet of each transceiver notes this Class 1 rating. The following example justifies the Class 1 rating. Given an LED transmitter emitting at 880 nm with a source size of 2 mm, the Class 1 limit for continuous operation is approximately 570 mW/sr. For an IrDA application using an FIR transceiver with a 25 % duty cycle, this limit would allow the LED to emit pulse intensities up to 2280 mW/sr. When operated within specifications, this high intensity will never occur. First, the IrDA® Physical Layer limits emitter intensities to 500 mW/sr. Second, IrDA transceivers limit the pulse duration. Finally, if drive conditions are set outside the specification, the thermal saturation of the emitter will limit the output intensity. Vishay's LEDs and IrDA transceivers are eye-safe. For more information regarding LEDs see the ICNIRP (International Commission on Non-Ionizing Radiation Protection) statement "ICNIRP Statement on LightEmitting diodes (LEDs) and Laser Diodes: Implications for Hazard Assessment"4). In the United States the safety standard IEC60825-1, Amd. 2 is harmonized by the Food and Drug Administration's (FDA) Center for Devices and Radiological Health (CDRH): "Laser Products - Conformance with IEC60825-1, Am. 2 and IEC60601-2-22; Final Guidance for Industry and FDA (Laser Notice No. 50)5)", issued July 26, 2001. Recent studies in the United States support these revisions; finding that eye damage can not be caused by even the brightest of currently available LEDs. 1) Diode Emitters: Semiconductor devices with diode characteristic emitting radiation such as LDs(laser diodes), IREDs or LEDs IRED: Infrared Emitting Diode. It is common but not correct to use the term LED also for Infrared Emitting Diodes LED: Light Emitting Diode, this term is used also for IR emitting diodes 4) Copyright© 2000 Health Physics Society. Copies are available from the Internet at: http://www.icnirp.org/documents/led.pdf 5) Copies are available from the Internet at: http://www.fda.gov/cdrh/comp/guidance/1346.html 2) 3) www.vishay.com 68 Document Number 82502 Rev. 1.3, 20-Sep-06 Remote Control with IrDA® Transceivers Vishay Semiconductors Utilizing a Vishay IrDA Transceiver for Remote Control Table of Contents Remote Control with IrDA Transceivers ......................................................................................... 70 Hardware - Interface Schematics ..................................................................................................... 70 Transmit Distance............................................................................................................................... 71 Test Results......................................................................................................................................... 75 Expected Performance ....................................................................................................................... 76 Remote Control Data Formats ........................................................................................................... 77 Application Examples......................................................................................................................... 78 Document Number 82606 Rev. 1.6, 20-Sep-06 www.vishay.com 69 Remote Control with IrDA® Transceivers Vishay Semiconductors Remote Control with IrDA Transceivers An infrared remote control unit is used to control many common consumer electronic products such as TV’s, DVD players, VCR’s and CD players. When a button is pressed on the remote control unit, a signal is sent from the unit, and received for example by the TV. The remote control unit contains an infrared emitting diode (LED) that transmits the signal and the TV contains an infrared receiver that receives the signal. This signal “commands” the TV to perform a function like Power-On/Off, Sound-Up/Down, and Channel-Up/ Down. The signal contains the TV’s address and the command code. Each function will have a different command code. The signal is encoded and transmitted using a modulated carrier wave in the frequency range of 30 kHz to 56 kHz. There are many different coding systems used for remote control. The most common codes are the RC5®, RC6®, and RMM® codes from Philips and the NEC code. Different products may use different coding systems. For example, your old TV remote control unit may not work with your new TV because they use different coding systems. For products using the same coding system, each product will have a different address to avoid performing a command meant for another product. Figure 1 in the Remote Control Data Formats section provides an example of a remote control signal using the Philips RC5 code when the channel “3” is pressed. For more information about remote control codes, please refer to this section and the document “Data Format for IR Remote Control”. Design engineers of handheld devices such as mobile phones and PDAs are faced with the challenge of combining multiple functions in a single device. Among the new features being integrated into handheld devices is TV remote control. Most of these devices feature a Vishay IrDA transceiver used for short-distance wireless communication. The transceiver’s emitter can be used to transmit remote control signals. This eliminates the need to designin an additional discrete LED emitter. At no additional cost or board space, this is an excellent solution. The remote control signal can be generated by software or by the combination of hardware (Baud Rate Generator or Timer) and software. Remote control applications generally include many of the available coding systems. For handheld devices, it is best if the application supports a “teach” function where the handheld device learns the codes from the remote control unit. The detector of the IrDA transceiver receives the emitted signals to be stored in the handheld application. www.vishay.com 70 ”Teaching” 18802 Figure 1. By integrating the remote control application with voice recognition, PDA and mobile phone manufacturers can offer their customers a very attractive capability: while in the process of answering a call, the user can simply say “Mute” to mute the TV. Convert the spoken word into an infrared remote control signal. Hardware - Interface Schematics The same hardware interface can be used for Vishay’s IrDA transceivers whether used for IrDA communication or remote control. No additional components are required for remote control. The following is a general interface block diagram for IrDA and remote control (RC) using Vishay’s new generation transceivers (figure 2). There are two output signals (IRTXD and SD/Mode) from the controller and one input signal to it. To use the same output line IRTXD of a controller for both IrDA and RC, the IrDA TXD port should be a multifunction port, which supports also GPIO (General Purpose Output) and UART (asynchronous serial data Transmit, in case using its Baud Rate Generator), and its functions can be alternated by software. To use the same input line IRRXD of a controller for both IrDA and RC “Teaching/Learning” function, the IrDA RXD port should be a multifunction port, which supports also GPIO (General Purpose Input), and its functions can be alternated by software. If the IrDA port does not support UART or GPIO one has to find another port and an extra multiplexer to do the RC. Document Number 82606 Rev. 1.6, 20-Sep-06 Remote Control with IrDA® Transceivers Vishay Semiconductors The circuit diagram in figure 2 shows additionally to the connections for the logic the little external circuit to be added for filtering the supply voltage (low-pass R1, C) and a resistor R2 for limiting the LED drive current. The resistor R2 is only necessary when the transceiver has no internal current control or the current should be reduced to a level lower than the internally controlled current. Also when operated with a supply voltage Vcc > 4 V the resistor R2 may be necessary when the application is operated close to the maximum temperature limits. "Transceiver" stands here for e.g. TFDU4300 (SIR, 115.2 kbit/s) or TFBS6614 (FIR, 4 Mbit/s). For these the pin numbers are valid. VCC = 3.3 V R2 = 2.7 (optional) Vcc Transceiver LEDA (1) LEDC (2) IRTXD/UART/GPIO TXD (3) IRRXD/GPIO RXD (4) GPIO[X] SD (5) Vcc (6) R1 = 22 GND C = 200 nF Transmit Distance Factors Influencing Transmit Distance This section provides a detailed description of factors influencing transmit distance: • Wavelength of emitter and detector • Optical intensity of the emitter • Receiver Sensitivity • Frequency of the emitter and detector. Operating Range The primary factors in the theoretical distance calculation are radiant intensity of the emitter (Ie in mW/sr) and sensitivity of the receiver (given as minimum or threshold irradiance Eemin in mW/m²). Calculating transmission distance in the simplest case assumes a square-law relationship between distance d and irradiance Eemin on the receiver. Shown below is the calculation using a receiver sensitivity of Eemin = 0.4 m W/m2 and an intensity of Ie = 40 mW/sr. The distance d is resulting as Vlogic (7) GND (8) d = 18803 Figure 2. General Interfacing Block Diagram for IrDA and RC Pin Function Description: IRRXD/GPIO: IrDA and RC data input RTXD2/UART/GPIO: IrDA and RC data output GPIO[x]: the available General Purpose pin, used for SD and Bandwidth Select In case when only an external RC port is available that can be used to independently switch the LED (or more precise IRED as indicated). Figure 3. General Interfacing Block Diagram for IrDA® and RC using an n-channel FET when only a separate RC port is available. In the chapter "Application Examples" samples with the interfacing circuit diagrams of the three most common used microcontrollers are shown, which have the IrDA port built-in and the port supports both UART and GPIO. Document Number 82606 Rev. 1.6, 20-Sep-06 Intensity --------------------------- = Sensitivity Ie -------------- = E emin 40 -------- = 10 m 0.4 Transmission distance increases as the intensity increases and as the receiver becomes more sensitive. Wavelength Standard infrared remote control uses a wavelength of 900 nm to 950 nm and a subcarrier frequency of 33 kHz to 40 kHz (IEC61603-1). Some manufacturers use a subcarrier frequency range from 30 kHz to 56 kHz. After the use of these wavelengths became standard, the still more efficient and much faster 850 nm to 900 nm emitters became available. These emitters are used in IrDA applications. Vishay further limits the peak wavelength used in its IrDA transceivers to 880 nm to 900 nm with a typical value of 886 nm. The main difference between an LED used exclusively for remote control and an IrDA LED is the emitted wavelength. The wavelength of Vishay’s IrDA LED is t 880 nm while the wavelength of a typical remote control LED is 940 nm. For longer transmit distances, the spectral distribution of an emitting LED should match the remote control receiver spectral sensitivity. Vishay’s IrDA transceivers are effective for remote control because the remote control receiver is sensitive to the wavelength emitted by the transceiver. Figure 4 shows that Vishay’s IrDA (886 nm) LED emits a wavelength long enough to be received by the remote control receivwww.vishay.com 71 Remote Control with IrDA® Transceivers Vishay Semiconductors meaning there is an 11 % range loss when using an 886-nm emitter instead of a 950-nm emitter. Normalized Spectral Emission or Sensitivity ers. Though the peak wavelength of the emitter and receiver are not matched, enough radiation is received to function well. Figure 5 shows spectral sensitivity curve of the leading remote control receivers. Because the peak wavelengths of the IrDA emitter and receiver are not matched, transmit distance is a function of a reduction factor, Rf, derived from the relative responsivity of the receiver Rf = Eemin/Ee (with Eemin = threshold irradiance at the maximum at 950 nm and Ee = threshold irradiance at the given wavelength). This reduction factor, Rf, is obtained from the curves by reading the normalized sensitivity value (Y-axis) where the receiver sensitivity curve intersects the IrDA emitter’s peak wavelength of 886 nm.The wavelength of 886 nm is the specified typical peak wavelength of Vishay’s IrDA-transceivers. In the following equations the parameter IrDA represents the wavelength range from 880 nm to 900 nm, CIR refers to the consumer IR wavelength of 930 nm to 950 nm. 1.1 1 0.9 0.8 "886 nm - peak emitter" "950 nm - peak emitter" RC-Receiver 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 750 800 850 900 950 Wavelenght (nm) 1000 1050 1100 17225 Figure 4. Spectral sensitivity and emitter „Overlap“ Ie E emin = ----2 d d = Ie -------------E emin 1 E emin IrDA = E emin CIR u ----Rf Ie E emin CIR = --------------------2 d CIR E emin IrDA 1 Rf I e = E emin CIR u ----- = ----------------------2 I d IrDA = Rf e u ------------------------------- = d IrDA = Rf u d CIR E emin CIR d IrDA Rf u d CIR E.g. in Figure 6, R f = 0.79 , www.vishay.com 72 Rf = 0.79 = 0.89 Document Number 82606 Rev. 1.6, 20-Sep-06 Remote Control with IrDA® Transceivers Relative Spectral Sensitivity S (λ) rel Vishay Semiconductors 1.2 1.0 0.8 0.6 0.4 0.2 0 750 850 950 1050 Wavelength λ (nm) 17229 1150 80 60 40 20 0 600 700 Relative Spectral Sensitivity S (λ) rel 17232 800 900 1000 1100 1200 Wavelength λ (nm) 1.2 1.0 0.8 250 0.6 200 0.4 0.2 0 750 17230 850 950 1050 Wavelength λ (nm) 1150 Intensity (mW/sr) Relative Sensitivity S (% ) 100 Optical Intensity As already described, remote control transmit distance is a function of emitter intensity. Transmit distance increases as the intensity of the emitter diode increases. Vishay lab results indicate that to transmit over a distance of 10 meters, the minimum intensity of the 880-nm emitter should be 70 mW/sr. Most lowpower IrDA transceivers have a LED intensity of less than 9 mW/sr, woefully inadequate to be used for remote control function. The intensity of the emitter depends on its peak current and efficiency. The peak current can be controlled by using a serial, current-limiting resistor. By reducing the value of the resistor, the LED peak current will increase which increases the intensity. Each IrDA transceiver, however, has a limit or maximum intensity. For example, the TFDU6102, the world’s leading FIR transceiver, has a peak current of typically 550 mA and typical intensity of 170 mW/sr (max. 350 mW/sr). Similarly, the TFDU4300 peak current and resulting intensity are typically 300 mA and 65 mW/sr. While the TFDU6102 does not require a current limiting resistor, figure 6 shows the dependence of intensity on the value of the serial resistor for randomly selected transceivers. The serial resistor may be used to reduce the internal power dissipation or to reduce the current consumption with resulting lower intensity. Note that these curves are for a few transceivers only. Single devices may deviate from average or normal behavior due to device parameter tolerances. 150 100 Figure 5. Collection of different spectral sensitivity curves of different types from different manufacturers 50 0 18807 0 1 2 3 4 5 6 7 8 Rled (Ohm) Figure 6. Current-limiting resistor vs. on-axis intensitity for TFDU6102 (five randomly selected transceivers). Applied operating voltage V2 = 3.3 V Document Number 82606 Rev. 1.6, 20-Sep-06 www.vishay.com 73 Remote Control with IrDA® Transceivers Vishay Semiconductors Carrier Frequency The sensitivity of an infrared remote control receiver is dependent on the carrier frequency as shown in Figure 7. The 3-dB bandwidth f is about 1/10 of its central frequency f0. A carrier based modulation scheme is used for remote control to efficiently filter the signal from disturbed ambient. Therefore remote control receivers can be much more sensitive (x 100 to x 200) than baseband transmission systems as e.g. IrDA equivalent receivers. The carrier frequency of the handheld device’s controller should be the same as the central frequency of the target device. A difference will result in a loss in sensitivity and subsequent transmit distance. For example, the transmit distance of a system which uses a 36-kHz controller with a Vishay TSOP1238 receiver (center frequency of 38 kHz) will be reduced by approximately 10 %. The selectivity is not that high to allow multi-channel operation. With strong signals as e.g. in a distance of 1 m a TSOP1238 will receive also 30 kHz and 56 kHz carriers. Battery Charge A weakly charged battery causes a drop in the strength of the emitted signal, particularly the beginning of the signal. In the following two diagrams (see figure 8 and 9) the effect of charging state of the battery is shown. This drop at the beginning of the signal may reduce the efficiency of the gain control of the receiver, requiring longer response times or repeating of the signal. Note that this is not RC-5 code. This code provides a long header to allow the receiver to adjust gain but with a weak battery the header is dropped. E e min / E e – Rel. Responsivity 1.0 0.8 18808 0.6 Figure 8. Signal from the IR transmitter with empty batteries. The measured intensity is decreasing during the burst. 0.4 0.2 f = f0 ± 5 % Δ f ( 3 dB ) = f0/10 0.0 0.7 94 8143 0.8 0.9 1.0 1.1 1.2 1.3 f/f0 – Relative Frequency Figure 7. Frequency dependence of responsivity 18809 Figure 9. Signal from the IR transmitter with new Alkaline batteries. The measured intensity is constant. www.vishay.com 74 Document Number 82606 Rev. 1.6, 20-Sep-06 Remote Control with IrDA® Transceivers Vishay Semiconductors Test Results Tests have verified that Vishay’s IrDA transceivers can easily and effectively be used as remote control emitters. These tests were performed using Vishay’s standard remote control test procedures and equipment. Vishay, the leading supplier of remote control receivers, as well other leading supplier’s receivers were tested. The measurements are performed on a Test Results Remote Control IrDA Transceivers Emitter Part Number long corridor, where reflections from walls, floor and ceiling improve the transmit distance. Therefore the range data does not follow the square law rule for free air transmission mentioned above. The measured ranges are not resulting from a statistical relevant number of devices. When comparing with table 2, remember that the test conditions may be different. SIR MIR FIR Vishay Vishay Vishay Vishay Vishay TSAL6400 TFDU4100 TFDU4300 TFDU5307 TFDU6614 IRED Peak Current (mA) 100 100 300 420 550 Intensity (mW/sr) 41 48 145 235 110 Peak Wavelength (nm) 940 886 886 886 886 RC Receivers Transmit Distance (m) Vishay TSOP1238 19 11 20 25 17 Panasonic PNA4612 11 8 13 17 11 Vishay TSOP4838 25 22 39 > 42 34 The signal was generated using a Philips remote control transmitter, Figure 10 and Figure 11 and Philips RC5® code with a modified carrier frequency of 38 kHz with a pulse width of 9 μs. +3V 200 μF DUT Button Array Philips Remote Control DUT 17226 17227 Figure 10. Philips remote control used in test Figure 11. Circuit diagram for driver the DUT Since carrier frequency has no influence on the optical matching of transmitter to receiver, the collected data can be transferred to any other carrier frequency system. This remote control transmitter generated a digital signal. The signal is fed to an IRED driver transistor. When testing IrDA transceivers with internal current controllers, the signal from the remote control was directly fed to the TXD input of the transceiver. For transceivers without internal current controllers, a serial resistor was used to generate constant current signal during the pulse. The transmitter supply voltage was set to 3 V. With the different receivers listed in the tables a Philips decoder SAA3049 was used, see the circuit diagram in Figure 12. Document Number 82606 Rev. 1.6, 20-Sep-06 +5V 100 Ω Data 10 μF Adress Toggle Remote Control Receiver 17228 SAA3049 5 V 4 MHz Figure 12. Receive circuit diagram www.vishay.com 75 Remote Control with IrDA® Transceivers Vishay Semiconductors Expected Performance Remote Control and IrDA® applications are both using Infrared as transmission medium. The remote control applications are using historically the wavelength band from 930 nm to 960 nm while IrDA covers the band from 850 nm to 900 nm. In the early days the 950-nm band was also under consideration for the IrDA organization. However, expecting future higher speed, IrDA decided to go with the shorter wavelength range. Standard IrDA receivers are able to receive RC signals, while RC receivers may not necessarily be able to receive IrDA signals. The typical RC receivers have cut-off filters which are in the center of the IrDA band. In general one can state, that the sensitivity of remote control receivers is questionable in the lower part of the IrDA band while above 880 nm the sensitivity of remote control receivers is quite good and can be used. This opens up the option to use IrDA transmitters also with remote control without spending an additional long wavelength chip. The experience confirms, that for the wavelength range from 880 nm to 900 nm for the majority of stateof-the-art remote control receivers a sensitivity threshold of 0.7 mW/m2 can be assumed. In the following table 1 the range is listed which can be expected under IrDA intensity conditions with the boundary condition that the wavelength is above 880 nm. In table 2 the expected range with some VISHAY transceivers is listed. Table 1: Expected Minimum RC Range under Standardized IrDA Conditions (Wavelength > 880 nm) Wavelength > 880 nm Min Intensity Sensitivity = 0.7 mW/m2 (VISHAY TSOP1238 receiver) IrDA Ie RC Range [mW/sr] [m] VFIR/FIR/MIR Standard 100 12.0 at IrDA nominal conditions VFIR/FIR/MIR extended LowPower 70 cm 50 8.5 > SIR 70 cm IrDA range with standard VFIR/FIR/MIR extended LowPower 50 cm 25 6.0 > SIR 50 cm IrDA range with standard VFIR/FIR/MIR LowPower 9 3.6 at IrDA nominal conditions SIR Standard 40 7.6 at IrDA nominal conditions SIR extended LowPower 70 cm 20 5.3 SIR 70 cm IrDA range with standard SIR extended LowPower 50 cm 10 3.8 SIR 50 cm IrDA range with standard SIR LowPower 3.6 2.3 at IrDA nominal conditions Bold: IrDA Physical Layer IrPHY 1.4 Table 2: Expected RC Range with Selected VISHAY IrDA Transceivers Transceiver RC Range [m] Remark TFDU4100 14.1 at 5.0 V, Rs = 14 Ohm, about 210 mA TFDU6102 20.0 at 550 mA TFDU8108 20.0 at 550 mA TFBS4710 12.5 at 300 mA internally controlled TFBS6614 18.2 at 3.3 V, R = 0 Ohm TFDU5307 18.1 at 3.3 V, internally controlled TFDU4300 10.5 at 300 mA internally controlled TFBS4711 9.3 at 300 mA internally controlled TFBS6711 12.8 at 440 mA internally controlled TFBS5700 9.3 at 3.3 V, R = 4.7 Ohm, about 300 mA TFBS4650/4652 9.3 at 300 mA internally controlled, device specified operation TFBS4650/4652 3.8 at 50 mA externally limited, LowPower operation TFDU4202 14.6 at 320 mA resistor limited TFDU4203 14.6 at 320 mA resistor limited Receiver: VISHAY TSOP1238, Sensitivity = 0.7 mW/m2 at 885 nm www.vishay.com 76 Document Number 82606 Rev. 1.6, 20-Sep-06 Remote Control with IrDA® Transceivers Vishay Semiconductors Remote Control Data Formats There are many different coding systems used for remote control. The most common codes are the RC5® and RC6® codes from Philips and the NEC code. For more information see the application note Data Formats for IR Remote Control. Figure 13 is an example of a remote control signal using the Philips RC5 code when channel “3” is pressed. It was recorded using an oscilloscope connected to IR PIN detector. Figure 13. RC5 optical signals of Key ‘3’ Channel 3: The RC5 code of key ‘3’ (RC5 0 3) Channel A: Zoom-in of the start bits (11) and toggle bit. Channel B: Zoom-in of the start bit. Figure 14 shows the data format of the RC5 code. The data word is repeated as long as a key is pressed. 114 ms Data 24.9 ms Bit length 1.78 ms Example of a data word 2 start bit 1 toggle bit 5 address bit 6 data bit 27.8 μs Burst (half bit) 868 μs (32 cycles of 36 kHz) 17052 Figure 14. Philips RC5 IR remote control protocol The RC5 - code has an instruction set of 2048 different instructions and is divided into 32 addresses (5 bits) of each 64 instructions or commands (6 bits). Each remote controlled device has its own address, making it possible to change the volume of the TV without changing the volume of the CD player. The transmitted code is a data word that consists of 14 bits and is defined as: Document Number 82606 Rev. 1.6, 20-Sep-06 • 2 start bits (ss) for the automatic gain control in the infrared receiver. ss = 10 (Add 64 to command)1) ss = 11 (Use command as it is) • 1 toggle bit (change every time when a new button is pressed on the IR transmitter) • 5 address bits for the system address • 6 instruction bits for the command or key pressed The RC5 code uses the Bi-Phase modulation technique, meaning that a single bit is split up into two half bits: 0 -> 10 1 -> 01 The duration time of each bit is equal to 1.778 ms containing 32 pulses with a repetition rate of 36 kHz, the carrier frequency of this code. The total time of a full RC5 code is 24.889 ms. The space between two transmitted codes is 50 bit times or 88.889 ms. The carrier frequency is used to enable a narrow band reception to improve the noise rejection. The carrier frequency of the RC5 code is 36 kHz. The complete signal is repeated every 114 ms as long as the command button is still pressed. The toggle bit is changing its polarity each time the button is pressed. For example, pressing and holding the volume key will hold the toggle bit constant and the volume will continuously increase bar by bar, the signal will not change but will be repeated. By discretely pressing the volume button, the toggle bit will change its value each time. The final result is the same. In this case, the toggle bit has no influence. However, when selecting channel “1” and pressing and holding the “1”- key, the receiver will detect the unchanged toggle bit and will recognize only the “1” ignoring identical signals regardless of how long the button is pressed. Even if the transmission path is interrupted, it will not detect “11” or “111”. To change to channel “11”, the number “1” must be pressed twice. With each press, the polarity of the toggle bit changes and the receiver recognizes the command. Additional Components Required for Remote Control No additional components are required when using Vishay transceivers. Vishay’s transceivers have an emitter driver built-in and use the same digital input pin, TXD, for IrDA and RC. No MOSFET is required. 1)The command set can be increased by 64 commands by using a modified start bit “10” instead of “11” using the second start bit as a 7th command bit. www.vishay.com 77 Remote Control with IrDA® Transceivers Vishay Semiconductors Application Examples Motorola MC68SZ328 Processor (DragonBall) The Motorola MC68SZ328 Processor (DragonBall) is a high-performance low-power 32-bit microcontroller with an integrated IrDA block for direct support of the IrDA physical layer protocol (SIR, 9.6 kbit/s to 115.2 kbit/s). The application circuit is shown in figure 15. This processor uses the pin TXD / PE5 for IrDA or RC data output and RXD / PE4 as IrDA or RC data input. The pin RTS* / PE6 serves originally as RTS or GPIO. Here this pin is used as a general-purpose output. It is connected to SD for controlling the transceiver operating mode by asserting this pin low or high to enable or shutdown it. It is controlled by RTS bit of UMISC register. TXD/PE5, RXD/PE4 and RTS/PE6 pins are dedicated to the UART/Infrared Communication Port. For RC data output or recording, set the SEL4-6 of the PESEL register to 1. Control of these pins is given to the Port E for use as general-purpose input/output pins. Intel SA-1110 Processor, StrongArm The Intel SA-1110 Processor or StrongArm is a high performance, low-power microcontroller with an IrDA interface which supports SIR (9.6 kbit/s to 115.2 kbit/s) and FIR (4 Mbit/s). It does not support MIR (1 Mbit/s). The Vishay low profile (2.7 mm) transceiver TFBS6614 is an option to operate with this processor in the FIR range while the low profile (2.5 mm) transceiver TFDU4300 supports SIR in this application. Both can be used for IrDA and remote control operations. Other transceivers depending on the demand of the application (device profile, and range) may be applicable, too. The pin numbering of the transceiver may be different from that shown in figure 15. The SA1110 pin functions (see figure 16) are RXD2 as IrDA data input, and TXD2 as IrDA data output. GPx is an available general-purpose pin used for SD and Bandwidth selection. TXD2 and RXD2 pins are dedicated to the infrared communication port. If serial transmission is not required and this port is disabled, control of these pins is given to the peripheral pin control (PPC) unit for use as general-purpose input/output pins, uninterruptible. Refer to section 11.13 entitled "Peripheral Pin Controller" on page 11167 of the Intel StrongArm SA-1110 Microprocessor Developers Manual. To use these pins for remote control, the user must also program the PPC pin direction register. The direction of TXD2 should be output and RXD2 should be input. 19896 Figure 15. Motorola MC68SZ328 Processor, DragonBall, interfaced for IrDA/RC applications The pin numbers are related to the VISHAY transceiver TFDU4300. Depending on the demand also TFBS4650, TFBS4652, or other SIR transceivers can be used, the pin numbering may be different in that case. 19897 Figure 16. Intel SA-1110 Processor, StrongArm, in IrDA/RC applications www.vishay.com 78 Document Number 82606 Rev. 1.6, 20-Sep-06 Remote Control with IrDA® Transceivers Vishay Semiconductors Intel PXA255 Processor or XScale The Intel PXA255 Processor or XScale is a high-performance low-power microcontroller and has an IrDA interface which supports both SIR (9.6 kbit/s to 115.2 kbit/s) and FIR (4 Mbit/s), see figure 17. 19898 Figure 17. Intel PXA255 Processor, Xscale, in IrDA/RC applications The Vishay low profile (2.7 mm) transceiver TFBS6614 is an option to operate with this processor in the FIR range while the low profile transceiver (2.5 mm) TFDU4300 supports SIR in this application. Both can be used for IrDA and remote control operations. The circuit diagram is shown in figure 17. The transmitter input TXD (pin-3) of the transceiver is connected to the processor's pin IRTXD/GPIO[47], the receiver output RXD (pin-4) is connected to IRRXD/GPIO[46] and the shutdown SD (pin-5) to one of any available GPIO pins. The I/Os IRRXD/GPIO[47] and IRTXD2/GPIO[46] are multifunctional pins. To change their function between IrDA and RC the bit-pair AF47 and AF46 of the GPIO Alternate Function Select Registers (GAFR1) is to be programmed. For example, setting the bit-pair of GAFR1_L AF47 alters its function between SIR, FIR, STD_UART and GPIO for remote control as shown in the following table. bits <31,30> Name Description 00 GP47 General Purpose IO port (for CIR) 01 TXD STD_UART transmit data 10 ICP_TXD FIR transmit data Document Number 82606 Rev. 1.6, 20-Sep-06 Programming Example for RC operation (direct access the GPIO ports): Refer to section 4.1.3 GPIO Register Definitions, on page 4-6 of "Intel® PXA255 Processor Developer's Manual", March 2003 1. Set the direction of port GPIO[47] to Output, by setting 1 to bit-15 (PD47) of register GPDR1 (GPIO Pin Direction). Set the direction of port GPIO[46] to input, by setting 0 to bit-14 (PD46) of register GPDR1 (GPIO Pin Direction). 2. Set the IRTXD/GPIO[47] port to GPIO, by writing 00 to bit-pair <31,30> (AF47) of register GAFR1_L. Set the IRRXD/GPIO[46] port to GPIO, by writing 00 to bit-pair <29,28> (AF46) of register GAFR1_L. 3. Send the same signals through the output port, by writing one to either bit-15 (PS47) of register GPSR1 (to set) or bit-15 (PC47) of GPCR1 (to clear). 4. Read and record the inputs from port IRRXD/GPIO[46] for RC simulation. The pin state can be read by reading the bit-14 (pl46) of register GPLR1. www.vishay.com 79 Interface Circuits Vishay Semiconductors Interface Circuits Interfacing SIR transceivers to an RS232 port A quite common method of adding the IrDA capability to a desktop computer is the usage of a so-called dongle connected to the COM - port (RS232 - port). This connectivity is currently available at any desktop or laptop computer but in future will be replaced by the USB port. For interfacing the SIR frontend transceivers (4000 series) as for other SIR transceivers an Encoder/ Decoder device (TOIM4232) is necessary to provide the NRZ to RZI conversion. This device also provides the clock generator and can be programmed by a set of (8 bit-) commands. Drivers for the RS232 connector with TOIM4232 are provided by Microsoft (R) with the Operating Systems. The block diagram of a dongle connection to RS232 is shown in figure 1. RS232 9 pin connector Level converter SIR transceiver TOIM4232 Pin4, DTR RESET Pin7, RTS BR/D VCC_SD TD_IR TxD Pin3, TxD TD_UART RD_IR RxD Pin2, RxD RD_UART X1 18046-1 VCC X2 3.6842 MHz Figure 1. TOIM4232-RS232 Interface (external infrared adapter) Interfacing SIR Transceivers with Enhanced UART16550A that are provided with internal IR encoder/decoder. There’s a large selections of enhanced UART’s and μP’s for customized industrial applications as well as portable handheld equipment, that have an embedded IR encoder/decoder supporting speeds from 9.6 kbit/s up to 115.2 kbit/s. A short list of the UART’s in this criteria; PC87334VLJ/PC87334VJG from National Semiconductors as well as FDC37C6651RI/ FDC37C666IR from Standard Microsystems, or W83877TF and W83977TF from Winbond, the SC16C550 and SC16C650 from Philips. Also microprocessors for www.vishay.com 80 universal applications such as the Toshiba’s TMP91CW12F, TMP3912U and the IT8172G from ITE Tech. Inc. just to mention a few. For this new generation of enhanced UART’s and Micros, the SIR transceivers can be directly interconnected. Please consult the application notes and interfacing guidelines by the manufacturer to optimize the efficiency and performance of your design. Interfacing MIR and FIR Transceivers. Advanced UART Interfaces provides this Port. Our MIR transceivers support speeds from 9.6 kbit/s to 1.152 Mbit/s while the FIR transceivers are supporting speeds from 9.6 kbit/s to 4 Mbit/s. Only TFDU5307 out of the 5000 series is compatible to the NSC and SMSC controller circuits described in the following. All available devices of the 6000 series are compatible to the described interface circuits. NSCPC87108 The configuration shown in figure 2 is recommended to interface MIR and FIR transceivers to the National Semiconductor PC87108VHG "Advanced UART and Infrared Controller". • C1 and C2 should be placed as close as possible to the Infrared Transceiver. • The area which is grounded should be large enough to cover as much space as possible between the circuit paths leading to the Infrared Transceiver. This will enhance EMI shielding to the internal optoelectronics. NSCPC87338VLJ The configuration shown in figure 3 is recommended to interface MIR and FIR transceivers to the National Semiconductor's PC87338VLJ. • C1 and C2 should be placed as close as possible to the Infrared Transceiver. • The area which is grounded should be large enough to cover as much space as possible between the circuit paths leading to the Infrared Transceiver. This will enhance EMI shielding to the internal optoelectronics. A catalog overview by National can be found in at http://www.national.com/catalog/PersonalComputing.html and documentation of the PC87109 controller in http://www.national.com/pf/PC/PC87109.html. Document Number: 82503 Rev. 1.7, 20-Sep-06 Interface Circuits Vishay Semiconductors Interfacing MIR and FIR transceivers with SMSC Infrared Controllers tor’s IrDA compatible transceivers with regard to these circuits are available from SMSC (see appendix for addresses). For more product information, see: http://www.smsc.com/main/datasheet.html and http://www.smsc.com/main/catalog/pcio.html. Many application hints can be found in the document "SMSC IrCC (Infrared Communications Controller) Hardware Design Guide" at http://www.smsc.com/main/appnotes/an76.html Standard Microsystems Corporation SMC has developed a variety of new Advance and Ultra I/Os. Typical representatives of the new controllers are the FDC37C669FR and the FDC37C93XFR. Application notes describing how to use the Vishay Semiconduc- Application Examples 16506 C3 VCC R2 2 : R1 50 : 6.8 PF VCC IRRX1 38 NSC87108 2 IRED Cathode 4 IRSLO IRTX Rxd Txd 37 TFDU6102 6 39 Vcc2, IRED Anode 8 Vcc1 SD GND Mode 1 3 5 7 GND GND C1 C2 470 nF 6.8 PF Figure 2. Application Example using NSC87108 Comp.# Recommended Values Vishay Part # R1 50 : CRCW–1206–50R00–F–RT1 R2 2: CRCW–1206–2R00–F–RT1 C1 470 nF VJ1206Y474–JXXMT C2, C3 6.8 PF 293D685X9016B2T 16507 VCC R2 2: R1 50 : VCC IRRX1 67 PC87338VLJ IRSLO 2 4 68 IRED Cathode 65 8 TXD RXD TFDU6102 6 IRTX Vcc2,IRED Anode Vcc1 SD GND Mode 1 3 5 7 GND GND C1 C2 470 nF 6.8 PF Figure 3. Application Example for TFDU6102 with NSC87338VLJ I/O Document Number: 82503 Rev. 1.7, 20-Sep-06 www.vishay.com 81 Interface Circuits Vishay Semiconductors Comp.# Recommended Values Vishay Part # R1 50 : CRCW–1206–50R00–F–RT1 R2 2: CRCW–1206–2R00–F–RT1 C1 470 nF VJ1206Y474–JXXMT C2 6.8 μF 293D685X9016B2T Recommended Application Circuits V CC R3 MAX3232CSE 1 C+ + C3 3 4 VCC TOIMx232 16 1 U1 C1- V+ C2+ V- 2 C5 + 6 C7 + 2 3 C6 + C4 4 + 5 C2- GND 15 5 6 11 10 12 9 T1IN T2IN R1OUT R2OUT T1OUT T2OUT R1IN R2IN 14 7 13 8 7 8 Reset Vcc U2 BR/Data RD IR RD 232 TD IR TD 232 S2 V CC SD S1 X1 NC X2 RD LED GND TD LED C10 16 2 + 15 R4 R6 TFDU4100 C11 4 14 6 13 8 IRED Cathode RXD VCC1 IRED Anode U4 GND TXD NC SC 1 3 5 7 12 11 10 9 J1 1 6 2 7 3 8 4 9 5 RXD RTS (BR/D) TXD R1 DTR (Reset) VCC Y1 Application circuit using TFDU4100 with integrated level shifter MAX3232E. When used directly with 3 Vlogic , this one can be omitted Z2 CON9 ext. input max 3.3 V DC J2 1 2 C1 R2 + C2 C8 CON2 C9 16527 Figure 4. Application circuit using TFDU4300 with an integrated level shifter MAX3232E. When used directly with 3 V logic, this one can be omitted For the component list see the TOIM4232 data sheet. USB to IrDA Interface HOST SYSTEM 4230 VFIR BLOCK Host Power Supplies Power STIR4230 Host Controller Control Signals 24.00 MHz crystal TFDU8108 SPI Transceiver The USB connection replaces in computers the well known old peripheral connections as RS232 and LPT and will be the most common connector in future. Therefore it is important to also support the IrDA wireless connectivity at the USB port. In the drawing in figure 5 the circuit block diagram using a SigmaTel solution is shown. This design operates up to the VFIR speed of 16 Mbit/s using the VISHAY transceiver TFDU8108. The USB to IrDA® interface shown here covers the frequency range up to 16 Mbit/s. On the following page the Sigmatel reference design is shown for the Sigmatel STIR4230 interface circuit used with the VISHAY transceiver TFDU8108. 19817 Figure 5. Block diagram of the USB to IrDA interface www.vishay.com 82 Document Number: 82503 Rev. 1.7, 20-Sep-06 Connect RESET_B to the pin on the Host Controller that will control the reset of the 4230 Connect INT to the pin on the Host Controller that will monitor the interrupt line Connect SPI_SSn to the SPI_SSn pin on the Host Controller Connect SPI_MOSI to the SPI_MOSI pin on the Host Controller Connect SPI_MISO to the SPI_MISO pin on the Host Controller Connect SPI_SCK to the SPI_SCK pin on the Host Controller Connect VDDIO to the 3.3V supply generated by the Host System Connect V_IR to the Host System's battery (must be above 2.7V) or 3.3V supply. RESET_B INT SPI_SSn SPI_MOSI SPI_MISO SPI_SCK 3.3V_Supply BATT 1.8V_Supply VDD VDDIO V_IR R1 47K GND 16 15 VDD VSS1 INT C1 22pF 16-Pin 4x4mm QFN STIR4230N GND C2 22pF IR_RX IR_SCLK VDDIO VSS2 D1 LED R4 220 Ohm VDDIO 5 6 7 8 Optional Activity LED 24.000MHz Y1 SPI_SSn XTAL must be close to the STIR4230. GND C3 0.1uF VDD 14 13 U1 12 SPI_MOSI GND GND C4 0.1uF VDDIO V_IR + GND C5 10uF GND C6 0.1uF C7 0.1uF Date: Size B Page Title 1 2 3 4 5 GND IRED Anode TOP VIEW 8 7 6 5 4 3 2 1 TFDU8108 Friday, December 10, 2004 Sheet 2 of 3 This design is the property of SigmaTel, Inc. It is offered on an "as is" basis, and carries no implied warranty. STIR4230 - Battery IR Rev B 3815 Capital of Texas Hwy. Suite 300 Austin, TX 78704 tel: (512)381-3700 www.sigmatel.com GND GND C8 4.7uF SigmaTel, Inc. U2 TFDU8108 IRED Cathode Txd Rxd SCLK + STIR4230 16L-4X4mm QFN Reference design Filter to reduce noise on the system's power supplies - may be required in some systems R2 10 Ohm Place C7 as close as possible to pins 6 and 7 of U2 R3 4.7 Ohm VDDIO R2, C5 and C6 are used to reduce the amount of noise on the system's power supplies. The actual values for R2 and C5 depend on several factors and will be specific to each application. IMPORTANT DESIGN NOTES STIR4230 16-Pin 4x4mm QFN 6 VCC Connect VDD to the 1.8V supply generated by the Host System XTAL_OUT 2 XTAL_IN 1 11 SPI_MISO 10 SPI_SCK 9 LED_OUT IR_TX 4 RESET_B 3 7 Vlogic Rev. 1.7, 20-Sep-06 GND Document Number: 82503 8 VDD Interface Circuits Vishay Semiconductors 19818 Figure 6. STIR4230 16-Pin 4 x 4 mm QFN Reference design www.vishay.com 83 Interface Circuits Vishay Semiconductors Remarks to the circuit shown in figure 6, STIR4230 16-Pin 4 x 4 mm QFN Reference design. 1) VDD is the core supply for the 4230. Connect to the host system´s 1.8 V supply. 2) VDDIO is the I/O supply for the 4230 and must be connected to the I/O supply used by the host processor and IR transceiver to ensure proper logic levels. VDDIO can be either 3.3 V or 1.8 V. 3) The integrity of the SPI_MOSI, SPI_MISO, and SPI_SCK signals are critical to the proper operation of the 4230. Use proper high speed layout techniques for these signals. Use signal paths that are as short and clean as possible. Introducing a delay of even a few nanoseconds can be enough to prevent full speed operation of the SPI bus and must be avoided. 4) While transmitting, the IR transceiver will consume large amounts of power and cause large current spikes on the supply and ground planes. Peak currents of over 500 mA are common for devices that transmit 1 m. Attention must be paid to power and ground layout as well as supply bypassing to prevent issues related to excessive ground bounce or power supply ripple. In some circumstances R2, C5 and C6 can be used to help isolate the transmit diode from the rest of the system. The optimum values for R2 and C5 depend on several factors and will be unique to each design. 5) The supply used for the transmit diode (V_IR) must be above 2.7 V. The transmit diode does not require a regulated supply, and for systems with battery voltages that are between 2.7 V and 5.5 V, can be powered from the battery. If the supply voltage is above 4 V, a series resistor may be needed to limit the amount of power dissipated inside the IR transceiver. 6) Place bypassing caps as close as possible to the IC´s power and ground pins. For U1, place C3 close to pins 15 and 16 and C4 close to pins 7 and 8. For U2, place C7 as close as possible to pins 6 and 7. 7) Place Y1 close to the STIR430. 8) The DAP (die attachpad) is not needed either electrically or thermally and attaching it to the PC board is not required. However, attaching the DAP provides additional mechanical support and may improve self allignment. www.vishay.com 84 Document Number: 82503 Rev. 1.7, 20-Sep-06 Interface Circuits Vishay Semiconductors List of some I/O Controllers and Interfaces Supporting IR (Remark: This list is not complete, there are other suppliers such as IBM, ITC, VLSI, or Phoenix) SC14428 Baseband Processor NSC ADSP-BF531, 532 & 533 Embedded Processor ANALOG DEVICES ADSP-BF537 & 536 Embedded Processor ANALOG DEVICES ADSP-BF561 Embedded Processor ANALOG DEVICES Elan SC400 Microprocessor AMD Elan SC520 Microprocessor AMD Alchemy AU1000 & 1100 Microprocessor AMD Geode SC Family Microprocessor AMD Geode GX533 & GX500 Microprocessor AMD Vr4100 Processor Family NEC WV8307 VolP Chipset Agere Systems BCM2121 GPRS/GSM Baseband Processor BROADCOM BCM2132 EDGE/GPRS/GSM Single-Chip Multimedia BROADCOM BCM2140 WCDMA (UTMS) FDD Baseband Coprocessor BROADCOM ML2011 GSM Single-Chip Baseband Processor BROADCOM BCM2702 Mobile Multimedia Processor BROADCOM AT76C713 Microcontroller ATMEL EP9312 Embedded ARM Processor (Industrial Applications) Cirrus Logic EP7309 Embedded ARM Processor (Portable Devices) Cirrus Logic EP7311 Embedded ARM Processor (Industrial, Mediacal) Cirrus Logic EP9302 Embedded ARM Processor (Industrial & Consumer) Cirrus Logic EP7312 Embedded ARM Processor (Portables & Handheld) Cirrus Logic EP9315 Embedded ARM Processor (Industrial & Consumer) Cirrus Logic EP9301 Embedded ARM Processor (Industrial & Consumer) Cirrus Logic EP9307 Embedded ARM Processor (Portables & Handheld) Cirrus Logic Document Number: 82503 Rev. 1.7, 20-Sep-06 CY8C21123, 223 & 323 Mixed-Signal Array PSoC Family product CYPRESS MPC875, 880, 875, 870 Power QUICC Processors Motorola-Freescale i.MX31 & iMX21 Multimedia Applications Processors Motorola-Freescale MCF54xX ColdFire V4e Core Processor Family Motorola-Freescale MC9S12E123/64/32 16-bit Microcontrollers Motorola-Freescale H8 & H8S H8SX Microprocessor Family HITACHI-Renesas M32R Microprocessor Family HITACHI-Renesas HMCS400 Microprocessor Family HITACHI-Renesas M16C Microprocessor Family HITACHI-Renesas H8/300H Microprocessor Family HITACHI-Renesas R8C Microprocessor Family HITACHI-Renesas ComCentrix L1501 I/O Controller LSI MAX3130, MAX3131 IrDA Encoder/Decoder MAXIM-DALLAS DS80C400 Network Microcontroller MAXIM-DALLAS DS89C420 8051 Microcontroller MAXIM-DALLAS MCP2120 EnDec IrDA MICROCHIP MCP2122 EnDec IrDA MICROCHIP MCP2140 EnDec IrDA MICROCHIP MCP2150 EnDec IrDA MICROCHIP MCP2155 EnDec IrDA MICROCHIP Vr41xx Microprocessor Family NEC MSM9405 EnDec IrDA OKI S3C4530A Microcontroller SAMSUNG SC16Cxxx UART Product family PHILIPS SC68Cxxx UART Product family PHILIPS PCD509x2/zuu/v Baseband Controller family PHILIPS uPSD Microcontroller 8032 Product family STMicroelectronics www.vishay.com 85 Interface Circuits Vishay Semiconductors STn88xx Multimedia Processor Product family STMicroelectronics USB2230 & USB2229 USB-IrDA Controller 4 Mbit/s SMSC MPC47N207 Super I/O UART SMSC SIO1036 & SIO 1000 I/O UART SMSC LPC47M10x & 47B272 Super I/O Controller (consumer appl.) SMSC LPC47M112 Enhanced Super I/O UART SMSC LPC47M172 & 182 Advance I/O Controller SMSC LPC47S45x Advance I/O Controller X-Bus SMSC LPC47S42x Enhanced Super I/O Server Appl. SMSC SCH5017 Super I/O SMSC SCH3116, 3114 & 3112 Super I/O SMSC SIO10N268 Advance Notebook I/O (ISA/LPC) SMSC FDC37N3869 Super I/O Controller (Portable Applications) SMSC FDC37M81x Enhanced Super I/O SMSC FDC37M707 Super I/O SMSC FDC37B72x & 78x Super I/O SMSC FDC37C665GT & 66GT Super I/O SMSC KBC1100 & KBC1100L Embedded Controller (Mobile) SMSC TMP91Cxxx Microcontroller Product family TOSHIBA TLCS-900/L1& H1 Microcontroller Product family TOSHIBA TMP86FS64FG Microcontroller Product family TOSHIBA VT1211 Super I/O VIA OXmPCI954 UART Bridge OXFORD Semicon. OX16PCI952 UART Dual Channel OXFORD Semicon. OXCB950 UART High Performance OXFORD Semicon. OX16C954 UART High Performance OXFORD Semicon. XC95108 Programmable CPLD Xilinx ST16C580 UART EXAR ST16C650A & 654 UART EXAR XR17C152, 154 & 158, UART PCI Bus EXAR XR17D152, 154 & 158 UART PCI Bus EXAR XR17L152, 154 & V258 UART PCI Bus EXAR XR16C285xx UART Family EXAR UCC5340 IrDA Receiver ???? Texas Instruments UCC5341 IrDA Receiver ???? Texas Instruments MSP430 IrDA SIR EnDec Texas Instruments TL16PIR552 Dual UART Texas Instruments TIR1000 IrDA SIR EnDec Texas Instruments TUSB3410 USB-RS232 Texas Instruments TMS320VC5470 & 5471 Fixed-Point DSP Texas Instruments OMAP5912 Multimedia Processor Texas Instruments OMAP5910 Dual-Core Processor Texas Instruments C5472 Programmable DSP Texas Instruments eCOG1K Mikrocontroller CYAN Technlg. W83L517D LPC I/O WINBOND W83637HF LPC I/O WINBOND W8369UF LPC I/O WINBOND W83627HF LPC I/O WINBOND L1501 Embedded UART LSI Logic. STIR4200 IrDA-USB1 Bridege FIR SIGMATEL STIR4210, 4220 & 4116 IrDA-USB2 Bridege VFIR SIGMATEL STIR4230 & 4231 VFIR Embedded Controller SIGMATEL IT8661F Super I/O ITE Tech. IT8702F Super I/O ITE Tech. IT8705F Super I/O ITE Tech. IT8700F Super I/O ITE Tech. IT8711F Super I/O ITE Tech. Note: The list of controllers is based on our research in the public literature. We don’t claim that this list covers all available controllers. We cannot guarantee the functionality of these controllers with transceivers. This must be verified for any special case. www.vishay.com 86 Document Number: 82503 Rev. 1.7, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors Reference Layouts and Circuit Diagrams For testing and comparing test results a common base is necessary. The layout of a test board can have a quite big influence on parameters, especially on rise and fall time and also on jitter. testing all transceivers with the common Vishay pin order and with a 1 mm lead pitch.1 The test boards and the Gerber plots of the test boards are available on request. In most cases the used power supplies are far away from the device under test and the wiring is done with long inductive cables. In such a case the power supply is not able to supply high peak currents. The only way to overcome this condition is to implement many capacitors close to the device under test. For comparison test data, especially as mentioned before for rise and fall times, the circuit ambient must be well defined. The circuit and the layout may have a quite big influence on the resulting data. Therefore a comparison should only be done under equal or very similar conditions. The boards for testing can be used for different types. Therefore redundant pads for circuit components may be in some cases not used or may have different purposes for different transceivers. For connecting to the test equipment, controllers, and power supplies twisted pair cables are used, which provide low capacitive load and defined impedance. The different usage of pin 7 of the transceiver in figure 2 leads to a layout where only for the case of Vlog at pin 7 the components C5, C6, and R4 may be used. In other cases a jumper replaces R4, and C5 and C6 are omitted. It is very important to note, that the circuit for testing is different from the application circuit, where e.g. in a telephone application the battery is very close to the transceiver and the wiring is also low impedance. In general we recommend using in application circuits the combination R1/C4 (shown in figure 1 and figure 2) and not more than that. In this chapter a common reference layout and the circuit diagram is described which is used for JP1 1 IRED Anode R2 Vlogic Vlogic V cc1 GND V cc R1 C1 C4 Ground SD SD TXD TXD RXD RXD I R T ra ns c e ive r V cc2 2 4 + C1 R1 6 8 10 9 5 R2 C2 GND GND 7 3 19706 R3 VCC GND 2 RXD 4 GND 6 C3 GND + C4 GND C5 Vlog. Mode or NC SD + 8 IRED Cathode IRED Anode RXD TXD Transceiver VCC1 SD GND Vlog. Mode or NC 1 3 5 7 C6 R4 opt. TXD 19707 Figure 1. Generally recommended application circuit for all Vishay IR transceivers. R1/C4 are recommended, R2 necessary only for not internally current controlled transceivers, C1 is optional, when inductive wiring is used. Figure 2. Test circuit for IR transceivers. The component positions are provided on the reference test board and can be populated depending on the demand and the test conditions Circuit description The test board is using only one power supply voltage VCC (at pin 1 of connector JP1, figure 2) for the transmitter and receiver. Another supply voltage is available for different logic voltages Vlog at JP1, pin 3 connected to pin 7 of the transceiver. The analog supply voltage VCC1 at pin 6 of the transceiver is connected to VCC via a low pass filter given by R1 and C3/C4. Also C1/C2 contribute to smoothing and stabilizing the voltage at pin 6, VCC1. The IRED anode is connected to the power supply via R2/R3 (two parallel resistors for increased power dissipation). These re1 sistors define the IRED current for the case a switch is built into the transceiver. In case of a built-in current controller, these two resistors can be replaced by a jumper. For supply voltages above 4 V it might by advisable to use these for lowering the power dissipation inside the transceiver, especially in case the maximum operating temperature will be used. In that case care should be taken, that the voltage at the IRED pin doesn’t drop below the minimum specified supply voltage. Note: This is an example for the 8 pin devices with 1-mm pitch. For other devices with different pitch and less pins equivalent boards are also available. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 87 Reference Layouts and Circuit Diagrams Vishay Semiconductors In figure 3 the test board layout is shown with top and 9-pin Sub-D connector or a twisted pair cable (see bottom layer, the component placement and the dif- table 3). ferent option for external connection, either via a Table 1. Component list for testing SIR - devices at VCC = 3.3 V TFDU4300 max. distance Component TFDU4300 Low Power mode TFDU4100 Test board C8P_5102 acc. figure 2 Application acc. figure 1 C8P_5102 acc. figure 2 Application acc. figure 1 U8-P_5002 acc. figure 2 R1 47 : 47 : 47 : 47 : 47 : 47 : R2 0: 56 : 56 : 10 : 4.7 : R3 open open R2/R3 0: 56 : 10 : R4 0: 0: 5: C1 10 μF 10 μF 10 μF C2 470 nF 470 nF 470 nF C3 6.8 μF 6.8 μF C4 470 nF C5 - - - C6 - - - 100 nF Application acc. figure 1 470 nF 100 nF 6.8 μF 4.7 μF 470 nF 100 nF - Remark: For component values in application circuits for volume production and other SIR transeivers see the relevant data sheets. Table 2. Component list for testing FIR/VFIR - devices at VCC = 3.3 V Component TFBS6614 TFDU6102 TFDU8108 Test board C8P_5102 acc. figure 2 Application acc. figure 1 C8P_5102 acc. figure 2 Application acc. figure 1 U8-P_5002 acc. figure 2 Application acc. figure 1 R1 10 : to 47 : 10 : 10 : to 47 : 10 : 4.7 : 4.7 : R2 0: 0: 0: 0: 0: 0: R3 - - - - - R2/R3 0: 0: 0: R4 0: 0: 0: C1 10 μF 10 μF 10 μF C2 470 nF 470 nF 470 nF C3 6.8 μF 6.8 μF C4 470 nF 100 nF 470 nF 6.8 μF 100 nF 220 nF 220 nF C5 C6 470 nF 470 nF 470 nF Table 3. Signal and pin assignment for test board Connector D_Sub 9 pos. male Function Cable pinning and color (when using twisted pair cables) Pin Signal Pin / Color 1 SD 9 / Blue 2 RX 7 / Green www.vishay.com 88 3 TX 5 / Yellow 4 Vlogic, SC, Mode or NC 3 / Orange 5 VCC 1 / Red 6 GND 2, 4, 6, 8, 10 / White 7 VCC (opt.) 8 VCC (opt.) 9 GND Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors 19711 19708 Figure 3. Board dimensions. Figure 6. Board layout BOTTOM-Side. See from Top-Side. 19709 19712 Figure 4. Component placement. Figure 7. Upper layer with Connector pinning. 19710 19713 Figure 5. Board layout TOP-Side. Figure 8. Upper layer with cable pinning. Figure 3 to figure 8. Test board layout for 8 pin transceiver – modules with 1-mm pitch. “U8P_5002” is the internal ID number, another test board with 0.95 mm pitch is available with the ID “C8P_5102”. For 6-pin and 7-pin transceivers equivalent test boards are available on request. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 89 Reference Layouts and Circuit Diagrams Vishay Semiconductors Remarks to the Test Board Layout and Pin - Function The circuit layouts are designed to operate with transceivers with the general Vishay pin order as SIR (9600 bit/s to 115.2 kbit/s) to VFIR(16 Mbit/s) shown in the following table. data rates. Our test boards can be used with pin #1 pin #2 pin #3 pin #4 pin #5 pin #6 pin #7 pin #8 IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Digital Supply Voltage Ground IREDA IREDC TXD RXD SD VCC Vlogic GND IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Mode Input Ground IREDA IREDC TXD RXD SD VCC Mode GND IR Emitter Annode IR Emitter Cathode Transmitter Input Receiver Output Serial Clock Analog Supply Voltage Mode Input Ground IREDA IREDC TXD RXD SD VCC Mode GND Function 7-pin device TFBS4650 IR Emitter Anode IR Emitter Cathode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Ground Symbol IREDA IREDC TXD RXD SD VCC GND Function 7-pin device TFBS4652 IR Emitter Anode Receiver Output Transmitter Input Shutdown Digital Supply Voltage Analog Supply Voltage Ground Symbol IREDA RXD TXD SD Vlogic VCC GND Function 6-pin device as e.g. TFBS4711 TFBS6711 TFBS6712 IR Emitter Anode Transmitter Input Receiver Output Shutdown Analog Supply Voltage Ground Symbol IREDA TXD RXD SD VCC GND Function 8-pin device as e.g. TFBS6614 Symbol Function 8-pin device as e.g. TFBS6102 Symbol Function 8-pin device as e.g. TFBS8108 Symbol The recommended board layouts are Vishay references for testing the transceivers. Identical boards are used for all speeds from SIR to VFIR. The layout has an influence on the rise/fall times of the signals, especially of the optical output pulse due to the quite high drive current through the LED. The circuit is also identical for all transceivers apart from the different use of pin 5 (SD or not connected as e.g. in case of TFDU4100, which has no SD function), pin 7 (Mode, Vlogic, or NC), and the device dependent current limiting resistors R2 for controlling the current through the IR emitter. As already described, the given layout is nearly identical for all Vishay transceivers because the pin order is identical for all devices. For different lead pitch different boards are available. www.vishay.com 90 Transceiver I/Os (8-pin as example) Optical Domain, Input and Output The IrDA® physical layer standard specifies only the optical interlink, not the electrical input or output signals. The optical domain is strictly specified and tested with the IrDA-given conditions. However, the constriction to the IrDA standard limits the application of the transceivers outside the IrDA protocol. Due to the pulse duration limits of minimum and maximum optical pulse width IrDA receivers are designed to suppress low frequency and DC radiation as sunlight, incandescent or fluorescent lamps. Therefore these receivers cannot be used as DC-radiation sensors. The emitter pulse duration is limited to overcome the overload risk during start-up conditions of computers and for eye safety issues, too. Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors Pin #1 - IR Emitter Anode There are in general different LED (or IRED) drive options in the different devices. Most of the new designs have a built-in current control for the LED drive current to set the intensity correctly for the application adapted to the IrDA standards (e.g. TFDU6102, TFBS6614, TFDU4300, TFBS4650). In that case the IREDA-pin is directly connected to the supply voltage. Only in special cases a series resistor is applicable: Adding an external resistor in series to the LED can have two reasons. The first is to reduce the dissipated power inside the receiver when supply voltages above 4 V are used (and specified) and the full temperature range should be covered keeping the internal current control active. The second is to reduce the internally set current e.g. for low power application or just saving power when the full range is not needed. In that case the controller function is changed just to a switch. Other transceivers are using only an internal switch. In that case the external resistor R2 from pin #1 to the power supply is responsible for the current limitation. With the internally defined current through the LED the intensity is to a great extent independent of the applied voltage while in case of using the switch the intensity is strongly voltage dependent and the resistor R2 is to be selected depending on the applied voltage. Also when the internal regulation is overruled by an external resistor this will behave like a switched but not controlled IRED. In figure 9 the typical resulting currents dependent on the applied voltages are shown when the current limitation is done by a series resistor Rs. In figure 10 the influence of the series resistance on the resulting current is shown. 400 350 IRED current (mA) 300 250 200 150 100 Rs = 3.3 Ohm 50 0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 19714 Voltage VIRED = VCC (V) Figure 9. Resulting current depending on the operating voltage LED drive current, limiting series resistor Rs = 3.3 : Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 91 Reference Layouts and Circuit Diagrams Vishay Semiconductors 450 Resulting IRED current (mA) 400 350 300 250 200 150 100 VCC1 = VCC2 = 3.3 V 50 0 1 10 100 Series Resistor Rs (Ω) 19722 Figure 10. Resulting current depending on the series resistor for limiting the LED drive current, VCC1 = VCC2 = 3.3 V The on-resistances RDSon of the driver transistors do not vary very much. Therefore this example is quite representative for all transceiver types with built-in switches. One should keep in mind that the parameters may slightly change over the temperature range. In figure 11 and figure 12 the behavior of transmitters with built-in current control is shown. There only a little voltage dependency can be observed for the drive current and the intensity, respectively. To increase the intensity a serial LED can be used when the quite high operating voltage is available. The abs. max ratings must be taken into account. 350 100 Intensity le (mW/sr) Peak current lf (mA) 300 250 200 150 100 50 60 40 20 0 0 2 3 4 2 5 IRED Anode Voltage (V) 19723 Figure 11. TFBS4711, peak emitter current as a function of the applied voltage Pin #2 – IR Emitter Cathode In most cases the IR Emitter Cathode pin is not to be connected. The IR Emitter cathode is internally connected to the LED driver. When the IR Emitter should be driven from an additional source as a Remote Control controller (Figure 13) an n-channel FET can be added to operate the Emitter like via an “or”-gate. An additional external diode can be operated in parallel when the intensity should be improved. That is efwww.vishay.com 92 80 3 4 5 IRED Anode Voltage (V) 19725 Figure 12. TFBS4711, intensity as a function of supply voltage ficient, when the transceiver is internally operated by a switch (Figure 14). In all cases the abs. max ratings must be taken into account. Connecting this pin to a large copper PCB-area would improve the heat dissipation especially in lead frame based designs (TFDUxxxx-types). Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors V cc1 R1 C1 GND IRED Anode V cc2 Vlogic Vlogic V cc C4 Ground SD SD TXD TXD RXD RXD R2 IRED Anode Vlogic V cc R1 V cc1 C1 GND C4 Ground SD SD TXD TXD RXD RXD IR Transceiver R2 I R T ra ns c e ive r V cc2 Vlogic Si1012R/X TXD_RC IRED Cathode IRED Cathode R2’ 19727 19726 Figure 13. Figure 14. Pin #3 – TXD Transmitter Input Inputs in general All inputs (as all other pins) are ESD protected. For the protection level see the data sheets or the Qualpacks for the special transceivers. Nevertheless, care should be taken that the voltage at the inputs does not exceed the specified values. Voltages above the threshold will trigger the input. This is valid also for applied RF – signals. Some EMI is just generated by too high applied RF voltages to the inputs (e.g. of more than 1.5 V with 3 V logic levels). When the transceivers are operated close to RF-antenna it should be avoided to couple RF to the input or output lines. As a counter measure terminating inputs (and also output lines) is recommended. Most devices have a built-in dynamic load circuit at the inputs (TXD, SD, Mode, SC), which keeps the input in the Low state. Changing the state will cause a current of some μA. The typical behavior and current flow is shown in figure 15. In figure 15 a simulation is shown with rising TXI input voltage over time. IVIC is the resulting input current and IDDadd is the additional operating current. Other inputs (e.g. SD) show the same behavior. V(TXI)_1:1 V 7 6 5 4 3 2 1 0 -1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0e-3 s 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0e-3 s 1.0 1.2 1.4 1.6 1.8 IVIC 1.5e-5 1.0 0.5 0.0 -0.5 -1.0 -1.5 0.0 IDDadd e-4 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 VDD = 3.0 V 0.0 0.2 0.4 0.6 0.8 19731 2.0e-3 s Figure 15. Input current characteristic Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 93 Reference Layouts and Circuit Diagrams Vishay Semiconductors To demonstrate the current vs. input voltage characteristics a triangular voltage function V(TXI) is applied to the TXD input pin. With increasing voltage the input current IVIC is increasing until the voltage crosses the switching point of the input. Above that the input load is switched off. However, there is still an additional operating current in the vicinity of the logic threshold level. That current vanishes, when the input voltage comes closer to the operating voltage (3 V in this case). Pin #3 – TXD Input Setting the transceiver input active will cause to output an electrical drive current through the LED and emitting a specified optical intensity. The pulse duration of IrDA-standard related transmission is limited to a maximum of about 20 μs2. To protect the emitter against wrong timing and also to comply with eye safety regulations the pulse duration in VISHAY emitters is limited to a value between 20 μs to 100 μs. This indicates that an NRZ-code (NRZ: no return to zero) cannot be transmitted with these devices spe- cialized for the IrDA standard. For communicating with RS232 via IrDA transceivers a code converter (ENDEC as the device TOIM4232) from NRZ to RZI (return to zero inverted) is necessary. Remote Control codes are supported. The IrDA standardized wavelength is shorter than the remote control wavelength. However, the RC receivers are able to receive IrDA signals, at least when the emitted wavelength is in the IrDA band above 870 nm as used by VISHAY. Pin #4 – RXD Receiver Output Outputs Vishay transceivers use tri-state outputs. When the device is set to the shut down mode, the output is floating with a very little load (in the order of 500 k: to 1 M:) to the digital supply voltage Vlogic, if available, or Vcc. The only device, which is using an open collector output, is TFDU4100 with an internal pull-up of 20 k: to Vcc. protected. With that feature programming errors will not kill outputs. All Vishay FIR transmitter outputs are short circuit As already noted for the TXD-input also the receive channel detects only pulses, but no DC-radiation. In general carrier based remote control signals (as RC5®, RC6® or NEC® - codes) can be received and used especially for a teach mode for learning RC codes. Pin #5 – SD Shutdown Shutdown With a few exemptions as TFDU4100 and TFDU4202 all Vishay Semiconductors IrDA-compliant transceivers feature a shutdown input. When set active the devices go into a shutdown mode with the RXD output floating with a weak pull-up. To shut down TFDU4100 and TFDU4202 see the special data sheets. and VFIR devices it is recommended to reset the transceivers by setting the SD active to force the device directly into a programmed mode before starting a communication. Often the start-up conditions in circuits are not defined very well. Therefore it is advisable to force the transceiver into a desired condition than to rely on a default state. In case of programmable transceivers as the MIR, FIR Pin #6 – VCC Analog Supply Voltage In nearly all Vishay Semiconductors transceivers the supply voltages for the LED and the transceiver can be applied separately. This has the advantage that only the transceiver with a small operating current has to be connected to the regulated power supply whereas the much higher LED drive current is supplied by the unregulated source, resulting in less cost for the Pin #7 – Mode The mode pin is used in FIR devices as e.g. TFDU6102 to change the mode from SIR to FIR statically. This pin can also be used to monitor the opera2 power supply. The supply voltage should be filtered with a low pass as shown in the circuit diagram. A combination of a Tantalum capacitor and a ceramic capacitor is recommended. Especially when EMI immunity is an issue, care should be taken for the RFquality of the ceramic capacitor. tion mode (SIR or FIR) of the device, which is set dynamically by using SD and TXD lines. If not used, leave this pin open. Maximum capacitive load: 50 pF. Note: Any IrDA receiver must be able to handle 1.6 μs input signals www.vishay.com 94 Document Number: 82610 Rev. 2.0, 20-Sep-06 Reference Layouts and Circuit Diagrams Vishay Semiconductors Pin #7 – Vlogic Digital Supply Voltage Some of the Vishay Semiconductors transceivers have the opportunity to apply an external reference for the logic input and output levels. If a Vlogic – voltage is specified, this can be either connected to Vcc or can be separately supplied by a reference voltage to adapt input thresholds and output levels to the logic levels for optimum noise suppression especially when using low I/O voltages. The input threshold is about half of the applied Vlogic and the output swing is defined by Vlogic. If not different from Vcc this pin can be directly connected to Vcc. Pin #8 – GND Ground This is the reference for all applied voltages. Especially when working with FIR and VFIR frequencies the standard rules for ground wiring in RF circuits should be observed. For testing basic parameters the described reference layout should be used. Switching times, delays, noise immunity and even sensitivity can suffer from bad grounding. Longer signal lines in particular should not be used without termination. See e.g. “The Art of Electronics” Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN 0521370957. Encoder and Decoder Circuits The VISHAY transceivers are designed to operate according to the IrDA standard, this means with dedicated pulse duration for transmitter and receiver. Many controllers (PC, mobile phone and microprocessor families) support the IrDA standard. SIR with RS232 is supported by the VISHAY – ENDEC TOIM4232. For a circuit diagram see this data sheet. See also the supplier list in the application note “Sources for Accessories”. Optical Windows Optical windows should be designed not to truncate the beam shape of transceivers. On the other hand the window design also can be used to minimize interference with background light and other disturbances. For type related window design and general information regarding windows materials and suppliers see the application note “Window Size in Housings”. Supplier references are in the note “Sources for Accessories”. Document Number: 82610 Rev. 2.0, 20-Sep-06 www.vishay.com 95 Quality and Reliability Vishay Semiconductors Quality Information Corporate Quality Policy Our goal is to exceed the quality expectations of our customers. This commitment starts with top management and extends through the entire organization. It is achieved through innovation, technical excellence and continuous improvement. 18348 Figure 1. Vishay quality policy www.vishay.com 96 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors VISHAY INTERTECHNOLOGY; INC. ENVIRONMENTAL, HEALTH AND SAFETY POLICY VISHAY INTERTECHNOLOGY, INC. is committed to conducting its worldwide operations in a socially responsible and ethical manner to protect the environment, and ensure the safety and health of our employees to conduct their daily activities in an environmentally responsible manner. Protection of the Environment: Conduct our business operation in a manner that protects the environmental quality of the communities in which our facilities are located. Reduce risks involved with storage and use of hazardous materials. The company is also committed to continual improvement of its environmental performance. Compliance with Environmental, Health and Safety Laws and Regulations: Comply with all relevant environmental, health and safety laws and regulations in every location. Maintain a system that provides timely updates of regulatory change. Cooperate fully with governmental agencies in meeting applicable requirements. Energy, Resource Conservation and Pollution Control: Strive to minimize energy and material consumption in the design of products and processes, and in the operation of our facilities. Promote the recycling of materials, including hazardous wastes, whenever possible. Minimize the generation of hazardous and non-hazardous wastes at our facilities to prevent or eliminate pollution. Manage and dispose of wastes safely and responsibly. Document Number: 82501 Rev. 1.3, 20-Sep-06 www.vishay.com 97 Quality and Reliability Vishay Semiconductors WWoor rl dl dCCl al assssEExxcceel llel ennccee 2008 In te g ra te d M a n a g e m e n t S y s te m s E C - D ir e c tiv e E L V , R o H S , W E E E fu lfille d IS O /T S 1 6 9 4 9 - A u to m o tiv e S ta n d a r d IS O 9 0 0 1 :2 0 0 0 P r o c e s s O r ie n te d B u s in e s s 2000 IS O 1 4 0 0 1 Q S 9 0 0 0 / V D A 6 .1 E F Q M A p p ro a c h 1995 M e a s u r e m e n t C u s t o m e r S a t is f a c t io n C o r p o r a te C u s to m e r S e r v ic e P o lic y IS O 9 0 0 0 A d v a n c e d Q u a lity T o o ls S u p p lie r P a r tn e r s h ip C o s t o f Q u a l i ty 1990 E m p o w e re d Im p ro v e m e n t T e a m s 19593 Figure 2. Vishay Quality road map Quality System Quality Program Vishay Corporate Quality At the heart of the quality process is the Vishay worldwide quality program. This program, which has been in place since the early 90's, is specifically designed to meet rapidly increasing customer quality demands now and in the future. Vishay Corporate Quality implements the Quality Policy and translates its requirements for use throughout the worldwide organization. Vishay Quality has defined a roadmap with specific targets along the way. The major target is to achieve world-class excellence throughout Vishay worldwide by 2008. The Vishay Corporate Quality defines and implements the Vishay quality policy at a corporate level. It acts to harmonize the quality systems of the constituent divisions and to implement Total Quality Management throughout the company worldwide. www.vishay.com 98 Vishay Zero Defect Program • Exceeding quality expectations of our customers • Commitment from top management through entire organization • Newest and most effective procedures and tools - design, manufacturing and testing - management procedures (eg. SPC, TQM) • Continuous decreasing numbers for AOQ and Failure Rate • Detailed failure analysis using 8D methodology • Continuous improvement of quality performance of parts and technology Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors Quality Goals and Methods Inputs from: from: rIntetability un aco QM Rev. 1.3, 20-Sep-06 re ultu C-C Document Number: 82501 Di r ec t i v es f r o m : tegy Stra K ey f u n c t i o n s : Forecast Mar k et i n g Order R& D, En g i n eer i n g Products Tr an s ac t i o n o f Or d er s Data Base New Products >3years VM, Cu s tom er Ac c. Cycle Time Sales/ASP Turns Inventorries Promisses Turns Response Time Returns A OQ Raw Material AOQ, Returns C o m p l a i nt s Q-Costs GGOOAALLSS Qu al i t y Cu s t o m er Qu al i t y En v i r o n m en t Su p p o r t ed b y : Con trolli ng Standards Laws K ey Parameter V M , RTM Product Sampl es Proj ect M gmt Y i el d Pr o d u c t i o n ManProject age men t Other Agreements Pu r c h as i n g Sale s Customer Qualitiy Dev el o p m en t o f New Pr o d u c t s F G MaS R rco,H m,L,ACC OG . ,IT Customer Requests Process Outputs K ey Pr oc es s es : Pl an n i ng Division The goals are straightforward: Customer satisfaction through continuous improvement towards zero defects in every area of our operation. We are committed to meet our customers' requirements in terms of quality and service. In order to achieve this, we build excellence into our product from concept to delivery and beyond. • Design-in Quality Quality must be designed into products. Vishay uses optimized design rules based on statistical information. This is refined using electrical, thermal and mechanical simulation together with techniques such as FMEA, QFD and DOE. • Built-in Quality Quality is built into all Vishay products by using qualified materials, suppliers and processes. Fundamental to this is the use of SPC techniques by both Vishay and its suppliers. The use of these techniques, as well as tracking critical processes, reduces variability, optimizing the process with respect to the specification. The target is defect prevention and continuous improvement. • Qualification All new products are qualified before release by submitting them to a series of mechanical, electrical and environmental tests. The same procedure is used for new or changed processes or packages. • Monitoring A selection of the same or similar tests used for qualification is also used to monitor the short- and longterm reliability of the product. • SPC (Statistical Process Control) SPC is an essential part of all Vishay process control. It has been established for many years and is used as a tool for the continuous improvement of processes by measuring, controlling and reducing variability. • Vishay Quality System All Vishay's facilities worldwide are approved to ISO 9000. In addition, depending on their activities, some Vishay companies are approved to recognized international and industry standards such as VDA 6.1 and QS 9000. Each subsidiary goal is to fulfill the particular requirements of customers. The Opto Divisions of Vishay Semiconductor GmbH are certified according to ISO 9001:2000, QS 9000 and ISO/TS 16949. Co n t i n u o u s Im p r o v ement (PDCA - Cy c le) le) 19594 The procedures used are based upon these standards and laid down in an approved and controlled Quality Manual. Total Quality Management Total Quality Management is a management system combining the resources of all employees, customers and suppliers in order to achieve total customer satisfaction. The fundamental elements of this system are: • Management commitment • European Foundation for Quality Management (EFQM assessment methodology) • Empowered Improvement Teams (EITs) • Supplier development and partnership • Quality tools • Training • Quality System All Vishay employees from the senior management downwards are trained in understanding and using of TQM. Every employee plays its own part in the continuous improvement process which is fundamental to TQM and our corporate commitment to exceed customers' expectations in all areas including design, technology, manufacturing, human resources, marketing, and finance. Everyone is involved in fulfilling this goal. The management believes that this can only be achieved by employee empowerment. The Vishay corporate core values • Leadership by example • Employee empowerment • Continuous improvement • Total customer satisfaction • Business excellence are the very essence of the Vishay Quality Movement process. www.vishay.com 99 Quality and Reliability Vishay Semiconductors • Training Vishay maintains that it can only realize its aims if the employees are well trained. It therefore invests heavily in courses to provide all employees with the knowledge they need to facilitate continuous improvement. A training profile has been established for all employees with emphasis being placed on Total Quality Leadership. Our long-term aim is to continuously improve our training so as to keep ahead of projected changes in business and technology. • EFQM Assessment Methodology From 1995, Vishay has started to introduce the EFQM (European Foundation for Quality Management) methodology for structuring its Total Quality Management approach. This methodology, similar to the Malcolm Baldrige process, consists in selfassessing the various Vishay divisions and facilities according to nine business criteria: • Leadership • People • Policy & Strategy • Partnership & Resources • Processes • People Results • Customer Results • Society Results • Key Performance Results (See figure 3) RESUL TS People related People related Results Results Politicy and Politicy and Strateg y Strategy Processes Processes Leadership Leadership People People Partnerships and Partnerships and Resources Resources Customer related Customer related Results Results Society related Society related Results Results I NNOV A TI ON & L EA RNI NG Key Performance Key Performance Results Results ENA BL ERS The assessments are conducted on a yearly basis by trained and empowered, internal Vishay assessors. This permits the identification of keypriority improvement projects and the measurement of the progress accomplished. The EFQM methodology helps Vishay to achieve world-class business excellence. • Empowered Improvement Teams (EITs) At Vishay we believe that every person in the company has a contribution to make in meeting our target of customer satisfaction. Management therefore empowers employees to higher and higher levels of motivation, thus achieving higher levels of effectiveness and productivity. Empowered improvement teams, which are both functional and cross functional, combine the varied talents from across the breadth of the company. By taking part in training, these teams are continually searching for ways to improve their jobs, achieving satisfaction for themselves, the company and most important of all the customer. 19595 Figure 3. EFQM criteria for self-assessment www.vishay.com 100 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors TQM Tools As part of its search for excellence, Vishay employs many different techniques and tools. The most important of them are: • Auditing As well as third party auditing employed for approval by ISO 9000 and customers, Vishay carries out its own internal and external auditing. There is a common auditing procedure for suppliers and sub-contractors between the Vishay entities. This procedure is also used for inter-company auditing between the facilities within Vishay. It is based on the "Continuous Improvement" concept with heavy emphasis on the use of SPC and other statistical tools for the control and reduction of variability. Internal audits are carried out on a routine basis. They include audits of satellite facilities (i.e., sales offices, warehousing etc.). Audits are also used widely to determine attitudes and expectations both within and outside the company. more efficient and promoting common understanding among team members of the methods and principles used. • Gauge Repeatability and Reproducibility (GR&R) This technique is used to determine equipment’s suitability for purpose. It is used to make certain that all equipment is capable of functioning to the required accuracy and repeatability. All new equipment is approved before use by this technique. • Quality Function Deployment (QFD) QFD is a method for translating customer requirements into recognizable requirements for Vishay’s marketing, design, research, manufacturing and sales (including after-sales). QFD is a process, which brings together the life cycle of a product from its conception, through design, manufacture, distribution and use until it has served its expected life. Quality Service Vishay believes that quality of service is equally as important as the technical ability of its products to meet their required performance and reliability. • Our objectives therefore include: • On-time delivery • Short response time to customers’ requests • Rapid and informed technical support • Fast handling of complaints • A partnership with our customers 18351 • Failure Mode and Effect Analysis (FMEA) FMEA is a technique for analyzing the possible methods of failure and their effect upon the performance/ reliability of the product/process. Process FMEAs are performed for all processes. In addition, product FMEAs are performed on all critical or customer products. • Design of Experiments (DOE) There is a series of tools that may be used for the statistical design of experiments. It consists of a formalized procedure for optimizing and analyzing experiments in a controlled manner. Taguchi and factorial experiment design are included in this. They provide a major advantage in determining the most important input parameters, making the experiment Document Number: 82501 Rev. 1.3, 20-Sep-06 18352 • Customer Complaints Complaints fall mainly into two categories: • Logistical • Technical www.vishay.com 101 Quality and Reliability Vishay Semiconductors Vishay has a procedure detailing the handling of complaints. Initially complaints are forwarded to the appropriate sales office where in-depth information describing the problem, using the Vishay Product Analysis Request and Return Form (PARRF), is of considerable help in giving a fast and accurate response. If it is necessary to send back the product for logistical reasons, the Sales Office issues a Returned Material Authorization (RMA) number. On receipt of the goods in good condition, credit is automatically issued. If there is a technical reason for complaint, sample together with the PARRF is sent to the Sales Office for forwarding to the Failure Analysis Department of the supplying facility. The device’s receipt will be acknowledged and a report issued on completion of the analysis. The cycle time this analysis has set targets and is constantly monitored in order to improve the response time. Failure analysis normally consists of electrical testing, functional testing, mechanical analysis (including X-ray), decapsulation, visual analysis and electrical probing. Other specialized techniques (i.e. LCD, thermal imaging, SEM, acoustic microscopy) may be used if necessary. If the analysis uncovers a quality problem, Corrective Action Report (CAR) in 8D format will be issued. Any subsequent returns are handled with the RMA procedure. 18353 Customer notifies Vishay Sales Office of a complaint and Sales obtains the necessary information about return using attached form (Product Analysis Request and Return Form) Customer has a complaint regarding Commercial Aspects e.g. Incorrect products, stock rotation, wrong delivery times or quantities Customer has a complaint regarding Technical Aspects e.g. Product out of specification, labeling error, and packaging issues Customer sends samples to designated factory location (communicated by Sales) Customer receives an analysis report from Vishay with reference number End of return procedure No Entitled to return/replacement products Yes Sales assign RMA number and Customer returns product 18354 Complaint and Return Procedure www.vishay.com 102 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors Product A nalysis Request and Return Form Address Data Customer: Address: Sales Ref.No: Sales Office: Incoming Date: Customer Ref.-No: Cust. Contact Person: E-Mail: Phone: Fax: Sales Contact Person: E-Mail: Phone: Fax: Product A nalysis Request Device: Date Code: Qty. for Analysis: Failure Rate: Plant Code: Type of Complaint (pls. specify) Electr. Mechan. Others Failure description Point of Failure: Qualification Reliability Others Incoming Assembly Field Failure Stress Conditions before Failure: (Temp / %HR / Voltage / Others) Application: (please specify) Remarks / Other Data: (please specify) Return Request Device: Date Code: Inv. No.: Commercial Return Technical Return RMA-No. : ( mandatory ) CAR-No. of 8D - Report: QM Vishay Issue: 02.10.2000 19596 Product Analysis Request and Return Form (PARRF) Document Number: 82501 Rev. 1.3, 20-Sep-06 www.vishay.com 103 Quality and Reliability Vishay Semiconductors Company Address CAR Number: Page: 1 VISHAY Company Name 8D Report Company Phone Number Report Date: Complete following for all applicable items: Date Opened: Originator Vishay Location: Vishay Part No.: Plant code: Customer: Date Code: Lot Serial No.: Customer Location: Device Type: Lot size: Customer Ref. Code: Value: Sample Qty: Customer Part No.: Tolerance: Failure rate: Customer P.O. No.: RMA Number: Analysis Code: Company Specific Information Package Type: 8D APPROACH – Disciplines 1, 2, and 4 below must be completed for ALL requests. DISCIPLINE 1: ESTABLISH TEAMS DISCIPLINE 2: DESCRIBE PROBLEM DISCIPLINE 3: CONTAINMENT ACTIONS DISCIPLINE 4: ROOT CAUSE/RESULTS If VALID, ALL Disciplines must be completed. DISCIPLINE 5: CORRECTIVE ACTIONS DISCIPLINE 6: IMPLEMENT CORRECTIVE ACTIONS DISCIPLINE 7: PREVENT RECURRENCE DISCIPLINE 8: CONGRATULATE TEAM Revised by: Approved by: Rev.: Date: Date: Date Closed: Form # CQA004 Rev B 04/26/02 MANUFACTURER OF ONE OF THE WORLD’S BROADEST LINE OF DISCRETE SEMICONDUCTORS AND PASSIVE COMPONENTS Confidential Information 19598 Vishay 8D form www.vishay.com 104 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors • Change Notification All product and process changes are controlled and released via ECN (Engineering Change Notification). This requires the approval of the relevant departments. In the case of a major change, the change is forwarded to customers via Sales/ Marketing before implementation. Where specific agreements are in place, the change will not be implemented unless approved by the customer. • Ship-to-Stock/Ship-to-Line (STS/STL) Many customers now require devices to be shipped direct to stock or to the production line by omitting any goods inwards inspection. Vishay welcomes such agreements as part of its customer partnership program, which promises an open approach in every aspect of its business. A product will only be supplied as STS or STL if there is a valid agreement in place between the two companies. Such an agreement details the quality level targets agreed upon between the companies and the methods to be used in case of problems. Quality and Reliability Assurance Program Though both quality and reliability are designed into all Vishay products, three basic programs must assure them: • Average Outgoing Quality (AOQ) – 100 % testing is followed by sample testing to measure the defect level of the shipped product. This defect level (AOQ) is measured in ppm (parts per million). • Reliability qualification program – to assure that the design, process or change is reliable. • Reliability monitoring program – to measure and assure that there is no decrease in the reliability of the product. AOQ Program Before leaving the factory, all products are sampled after 100% testing to ensure that they meet a minimum quality level and to measure the level of defects. The results are accumulated and expressed in ppm (parts per million). They are the measure of the average number of potentially failed parts in deliveries over a period of time. The sample size used is determined by AQL or LTPD tables depending upon the product. No rejects are allowed in the sample. The AOQ value is calculated monthly using the method defined in standard JEDEC 16: 6 AOQ = p LAR 10 ppm where: number of devices rejected p = -------------------------------------------------------------------------------total number of devices tested LAR = lot acceptance rate: number of lots rejected LAR = 1 – --------------------------------------------------------------------total number of lots tested 18357 Document Number: 82501 Rev. 1.3, 20-Sep-06 The AOQ values are recorded separately with regard to electrical and mechanical (visual) rejects by product type and package. The actual qualification procedure depends on which of these (or combinations of these) are to be qualified. Normally there are three categories of qualification in order of degree of qualification and testing required: • New technology or process (this includes a new design on a new process) www.vishay.com 105 Quality and Reliability Vishay Semiconductors • New product or re-designed product using a qualified process New package including piece-part or material change New manufacturing location • Minor change of process, assembly or package Accelerated testing is normally used in order to produce results fast. The stress level employed depends upon the failure mode investigated. The stress test is set so that the level used gives the maximum acceleration without introducing any new or untypical failure mode. The tests used consist of a set of the following: • High temperature life test (static) • High temperature life test (dynamic) • HTRB (High Temperature Reverse Bias) • Humidity 85/85 (with or without bias) • HAST (Highly Accelerated Stress Test) • Temperature cycling • High-temperature storage • Low-temperature storage • Marking permanency • Lead integrity • Solderability • Resistance to solder heat • Mechanical shock (not plastic packages) • Vibration (not plastic packages) • ESD characterization SMD devices only are subjected to preconditioning to simulate board assembly techniques using the methods defined in standard JSTD 020A before being subjected to stresses. Normally, the endpoint tests are related to the data sheet or to specified parameters. Additionally, they may include: • Destructive physical analysis • X-ray • Delamination testing using scanning acoustic microscope • Thermal imaging • Thermal and electrical resistance analysis Qualificationprocedure procedure Qualification Waferprocess process Wafer Package Package DeviceType Type Device qualification qualification qualification qualification qualification qualification Monitoring Monitoring Processchange change Process qualification qualification 18358 18358 www.vishay.com 106 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors TFDU TFDU 6102 6102 // TFDU TFDU 6108 6108 Low Low Profile Profile Transceiver Transceiver Module Module 18359 18359 Example of the QualPack Document Number: 82501 Rev. 1.3, 20-Sep-06 www.vishay.com 107 Quality and Reliability Vishay Semiconductors Reliability Monitoring & Wear Out Reliability Principles The monitoring program consists of short-term monitoring to provide fast feedback on a regular basis in case of a reduction in reliability and to measure the Early-life Failure Rate (EFR). At the same time, Longterm monitoring is used to determinate the Long-term steady-state Failure Rate (LFR). The tests used are a subset from those used for qualification and consist of: • Life tests • Humidity tests • Temperature-cycling tests • Solderability tests • Resistance-to-solder-heat test The actual tests used depend on the product tested. Depending on the assembly volume a yearly monitoring and wear out test plan is created. Wear Out data are very important in Opto electronic device. Out of that data degradation curves can be made. These curves show the long time behavior of the different devices. Some typical curves are attached in this report. Reliability is the probability of survival as a function of time and stress, and is usually expressed in terms of FITs (failures in 109 device hours). It is expressed as: failure failure rate rateλλ Early-life Early-life failures failures (EFR) (EFR) Operating Operatinglife lifefailures failures (LFR) (LFR) F(t) + R(t) = 1 or R(t) = 1 – F(t) where: R(t) = probability of survival F(t) = probability of failure F(t) = 1-e-Ot where O = instantaneous failure rate t = time thus, R(t) = e-Ot The lifetime distribution or hazard rate curve is shown on figure 4. This curve is also known as the 'bath-tub curve' because of its shape. There are three basic sections: • Early-life failures (infant mortality) • Operating-life failures (random failures) • Wear-out failures Wear-out Wear-out failures failures 18374 18374 Figure 4. Bathtub curve 18353 The failure rate (l) during the constant (random) failure period is determined from life-test data. The failure rate is calculated from the formula: r r O = ------------------------------------------- = ---6 Fi ti + N t C where www.vishay.com 108 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors O = failure rate (hours-1) r = number of observed failures fi = failure number = time to defect ti N = good sample size t = entire operating time C = number of Components X hours The result is expressed in either a) % per 1000 component hours by multiplying by 105 or in b) FITs by multiplying by 109 (1 FIT = 10-9 hours -1) Example 1: Determination of failure rate O 500 devices were operated over a period of 2000 hours (t) with: 1 failure (f1) after 1000 hours (t1) and 1 failure (f2) after 1500 hours (t2). The failure rate of the given example can be calculated as follows: 2 O = ---------------------------------------------------------------------------------------------------------- 1 1000h + 1 1500h + 498 2000h O = 2 10 –6 hours -1 That means that this sample has an average failure rate of 0.2 %/1000 hours or 2000 FIT Observed failure rates as measured above are for the specific lot of devices tested. If the predicted failure rate for the total population is required, statistical confidence factors have to be applied. The confidence factors can be obtained from "chi square" (F2) charts. Normally, these charts show the value of (F2/2) rather than F2. The failure rate is calculated by dividing the F2/2 factor by the number of component hours. 2 F e 2 O pop = -----------------C Document Number: 82501 Rev. 1.3, 20-Sep-06 The values for F2/2 are given in table 1 Number of Failures Confidence Level 60 % 90 % 0 0.92 2.31 1 2.02 3.89 2 3.08 5.30 3 4.17 6.70 4 5.24 8.00 5 6.25 9.25 6 7.27 10.55 Table 1: F2/2 chart Example 2: The failure rate of the population Using example 1 with a failure rate of 2000 FIT and 2 failures: F2/2 at 60% confidence is 3.08 O pop 3.08 = ----------------------------- = 3085 FIT 5 9.985 10 This means that the failure rate of the population will not exceed 3085 FIT with a probability of 60% • Accelerated Stress Testing In order to be able to assure long operating life with a reasonable confidence, Vishay carries out accelerated testing on all its products. The normal accelerating factor is the temperature of operation. Most failure mechanisms of semiconductors are dependent upon temperature. This temperature dependence is best described by the Arrhenius equation. O T2 = O T1 u e EA 1 -------- u § ------ – 1-· © T1 -----k T2¹ where k = Boltzmann's constant 8.63 x 10-5 eV/K EA = Activation energy (eV) T1 = Operation temperature (K) = Stress temperature (K) T2 OT1 = Operation failure rate OT2 = Stress-test failure rate Using this equation, it is possible from the stress test results to predict what would happen in use at the normal temperature of operation. • Activation Energy Provided the stress testing does not introduce a failure mode, which would not occur in practice, this method gives an acceptable method for predicting reliability using short test periods compared to the life of the device. It is necessary to know the activation www.vishay.com 109 Quality and Reliability Vishay Semiconductors energy of the failure mode occurring during the accelerated testing. This can be determined by experiment. In practice, it is unusual to find a failure or if there is, it is a random failure mode. For this reason an average activation energy is normally used for this calculation. Though activation energies can vary between 0.3 and 2.2 eV, under the conditions of use, activation energies of between 0.6 and 0.9 eV are used depending upon the technology. Acceleration factor Failure mechanism Activation Energy Mechanical wire shorts 0.3 – 0.4 Diffusion and bulk defects 0.3 – 0.4 Oxide defects 0.3 – 0.4 Top-to-bottom metal short 0.5 Electro migration 0.4 – 1.2 0.8 eV Electrolytic corrosion 0.8 – 1.0 0.7 eV Gold-aluminum intermetallics 0.8 – 2.0 0.6 eV Gold-aluminum bond degradation 1.0 – 2.2 Ionic contamination 1.02 Alloy pitting 1.77 1000 100 Activation Energies for common failure mechanisms The activation energies for some of the major semiconductor failure mechanisms are given in the table below. These are estimates taken from published literature. 0.5 eV 10 Table 2: Activation energies for common failure mechanism 100 1 55 75 95 120 115 150 135 155 Temperature (°C) 18361 Figure 5. Acceleration factor for different activation energies normalized to T = 55 °C Failure rates are quoted at an operating temperature of 55 °C and 60 % confidence using an activation energy (EA) of 0.8 eV for optoelectronic devices. Example 3: Conversion to 55 °C In Example 2, the life test was out at 150 °C so to transform to an operating temperature of 55 °C. T1 = 273 + 55 = 328K T1 = 273 + 150 = 423K Acceleration factor = O O 423K T2 --------------- = ---------------------- = 258 O O 328K T1 O 18362 www.vishay.com 110 328K O 423K 3080 = ---------------------- = ------------258 258 = 12 FIT (at 55 °C with a confidence of 60 %) This figure can be re-calculated for any operating/junction temperature using this method. Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors • EFR (Early Life Failure Rate) This is defined as the proportion of failures, which will occur during the warranty period of the system for which they were designed. In order to standardize this period, Vishay uses 1000 operation hours as the reference period. This is the figure also used by the automotive industry; it equates to one year in the life of an automobile. In order to estimate this figure, Vishay normally operates a sample of devices for 48 or 168 hours under the accelerated conditions detailed above. The Arrhenius law is then used as before to calculate the failure rate at 55 °C with a confidence level of 60 %. This figure is multiplied by 1000 to give the failures in 1000 hours and by 106 to give a failure in ppm. All EFR figures are quoted in ppm (parts per million). • Climatic Tests Models Temperature cycling failure rate The inverse power law is used to model fatigue failures of materials that are subjected to thermal cycling. For the purpose of accelerated testing, this model relationship is called Coffin-Manson relationship, and can be expressed as follows: 'T stress M A F = § ----------------------· © 'T use ¹ where: AF = Acceleration factor 'Tuse = temp. range under normal operation 'Tstress = temp. range under stress operation M = constant characteristic of the failure mechanism. Failure mechanism Coffin–Manson exponent M Al wire bond failure 3.5 Intermetallic bond fracture 4.0 Au wire bond heel crack 5.1 Chip-out bond failure 7.1 Table 3: Coffin - Manson exponent M For instance: 'T use = 15 °C/ 60 °C = 45 °C 'T stress = – 25 °C/ 60 °C = 125 °C Document Number: 82501 Rev. 1.3, 20-Sep-06 125 °C 3 A F = § ------------------· | 21 © 45 °C ¹ Relative Humidity failure rate Moisture effect modeling is based upon the HowardPecht-Peck model using the acceleration factor of the equation shown below: E 1 1 ------A- § ------------ – ------------------· k © T use T stress¹ RH stress C A F = § -----------------------· e © RH use ¹ where: RHstress = relative humidity during test RHuse = relative humidity during operation Tstress = temperature during test Tuse = temperature during operation EA = activation energy k = Boltzmann constant C = material constant For instance: RHstress = 85 % RHuse = 92 % Tuse = 313 K Tstress = 358 K AF 0, 8 1 1 ------------------------------ § ---------- – ----------· – 5 © 313 358¹ 3 8,617 x 10 85 % RH = § ------------------------· e © 92 % RH¹ A F | 33 This example shows how to transform test conditions into environmental or into another test conditions. This equation is applicable for devices subjected to temperature humidity bias (THB) testing. Using these acceleration factors the useful lifetime can be calculated. Applying the acceleration factor once more, useful lifetime for the moisture effect model for parts subjected to THB can be estimated by the following equation: A F test hours Useful life Years = ------------------------------------hours per year www.vishay.com 111 Quality and Reliability Vishay Semiconductors with: Test hours = 1000 hours per year = 8760 AF | 118 (40 °C / 60 % RH) 118 1000 Useful life Years = --------------------------- | 13.5 years 8760 This means that operation in 40 °C / 60 % RH environment is good for around 13 years, calculated out of the 85 °C/ 85 % RH 1000h humidity stress test. 18370 Wafer Level Reliability Testing Due to the increasing demand for complex devices with reduced geometry, Vishay is committed to enhancing and improving process and product quality through the use of Wafer Level Testing (WLT). Through the use of custom-designed and standard test devices and structures, the on-going design as well as the process quality and reliability are monitored both at the wafer and package level. When implemented in the manufacturing process, they provide a rapid means of monitoring metal integrity and parameter stability. The main tests are: • Electro-migration Commonly known as SWEAT (Standard Wafer- Level Electro-migration Test), this test is used as a metallization process quality monitor. • Mobile ion instability Special sensitive transistors are used together with built-in heaters to measure the effect of the movement of mobile ions at the interface region. www.vishay.com 112 Handling for Quality • Electrostatic Discharge (ESD) Precautions Electrostatic discharge is defined as the high voltage, which is generated when two dissimilar materials move in contact with one another. This may be by rubbing (i.e. walking on a carpet) or by hot air or gas passing over an insulated object. Sometimes, ESD is easily detectable as when a person is discharged to ground (shock). Electronic devices may be irreversibly damaged when subjected to this discharge. They can also be damaged if they are charged to a high voltage and then discharged to ground. Damage due to ESD may occur at any point in the process of manufacture and use of the device. ESD is a particular problem if the humidity is low (< 40 %) which is very common in non-humidified but air-conditioned buildings. ESD is not just generated by the human body but can also occur with un-grounded machinery. ESD may cause a device to fail immediately or damage a device so that it will fail later. Whether this happens or not, usually depends on the energy available in the ESD pulse. All ESD-sensitive Vishay products are protected by means of • Protection structures on chip • ESD protection measures during handling and shipping Vishay has laid down procedures, which detail the methods to be used for protection against ESD. These measures meet or exceed those of EN61340-5-1 or MIL-STD-1686, the standards for ESD-protective and preventative measures. These include the use of: • Grounded wrist straps • Grounded benches • Conductive floors • Protective clothing • Controlled humidity It also lays down the methods for routinely checking these and other items such as the grounding of machines. A semiconductor device is only completely protected when enclosed in a «Faraday Cage». This is a completely closed conductive container (i.e., sealed conductive bag or box). Most packaging material (i.e. tubes) used for semiconductors is now manufactured from antistatic material or anti-static-coated material. This does not mean Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors with a maximum temperature of 245 °C maximum 2 x with the total restricted to 3 soldering operations Note: certain components may have limitations due to their construction. • Dry pack When being stored, certain types of device packages can absorb moisture, which is released during the soldering operations, thus causing damage to the device. The so-called «popcorn» effect is such an example. To prevent this, Surface Mount Devices (SMD) are evaluated during qualification, using a test consisting of moisture followed by soldering simulation (pre-conditioning) and then subjected to various stress tests. In table Number 3 - Moisture Sensitivity Levels – the six different levels, the floor life conditions as well as the soak requirements belonging to these levels are described. Any device, which is found to deteriorate under these conditions, is packaged in «dry pack». The dry-packed devices are packed generally according to EIA-583 «Packaging Material Standards for Moisture Sensitive Items», IPC-SM-786 «Recommended Procedures for Handling of Moisture Sensitive Plastic IC Packages». The following are general recommendations: • Shelf life in the packaging at < 40 °C and 90 % RH is 12 months. • After opening, the devices should be handled according to the specifications mentioned on the dry-pack label. • If the exposure or storage time is exceeded, the devices should be baked: • Low-temperature baking - 192 hours at 40 °C and 5 % RH • High-temperature backing - 24 hours at 125 °C. that the devices are completely protected from ESD, only that the packing will not generate ESD. Devices are completely protected only when surrounded on all sides by a conductive package. It should also be remembered that devices can equally as easily be damaged by discharge from a high voltage to ground as vice-versa. Testing for ESD resistance is part of the qualification procedure. The methods used are detailed in MILSTD-883 Method 3015.7 (Human Body Model) and EOS/ESD-S5.1-1993 (Machine Model) specification. • Latch-up The latch-up effect is a state in which a low impedance path results and persists following an input, output or the latch-up effect is a state in which a low impedance path supply over voltage that triggers a parasitic Thyristor. Due to this effect an over current occurs in the IC, which can destroy the IC. At least the supply voltage of the IC must be cut off to get back the IC in a defined state. Normally, the latch-up test is carried out just at CMOS ICs. This CMOS latch-up test is according to the JEDEC 17 standard. For Bipolar ICs, there is no standard available so far. • Soldering All products are tested to ascertain their ability to withstand the industry standard soldering conditions after storage. In general, these conditions are as follows. • Hand soldering: 260 °C, 2 mm from the device body for 10 s. • Wave soldering: Double-wave soldering according to CECC 00802 maximum 2 x total restricted to 3 soldering operations • Reflow soldering: convection soldering according to CECC 00802 with a maximum temperature of 260 °C, maximum 2 x with the total restricted to 3 soldering operations, IR soldering to CECC 00802 Floor Life Level Conditions Time Time (hours) Soak Requirements Conditions 1 d30 °C / 90 % RH Unlimited 85 °C / 85 % RH 2 d30 °C / 60 % RH 1 year 2a d30 °C / 60 % RH 4 Weeks 168 168 696hrs 85 °C / 60 % RH 30 °C / 60 % RH X Y Z 3 d30 °C / 60 % RH 168 h. 24 168 192 30 °C / 60 % RH 4 d30 °C / 60 % RH 72 h. 24 72 96 30 °C / 60 % RH 5 d30 °C / 60 % RH 24 / 48 h. 24 24 / 48 48 / 72 30 °C / 60 % RH 6 d30 °C / 60 % RH 6 h. 0 6 6 30 °C / 60 % RH Table 4: Moisture Sensitivity Levels Document Number: 82501 Rev. 1.3, 20-Sep-06 www.vishay.com 113 Quality and Reliability Vishay Semiconductors X Y Z = Default value of semiconductor manufacturer’s exposure time (MET) between bake and bag plus the maximum time allowed out of the bag at the distributor’s facility. The actual times may be used rather than the default times, but they must be used if they exceed the default times. = Floor life of package after it is removed from dry pack bag (level 8 after completion of bake). = Total soak time for evaluation (X + Y). Note: There are two possible floor lives and soak times in Level 5. The correct floor life will be determined by the manufacturer and will be noted on the dry pack bag label per JEP 113.«Symbol and Labels for Moisture Sensitive Devices». www.vishay.com 114 Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors Reliability & Statistics Glossary Definitions Accelerated Life Test: A life test under conditions those are more severe than usual operating conditions. It is helpful, but not necessary, that a relationship between test severity and the probability distribution of life be ascertainable. Acceleration Factor: Notation: f(t) = the time transformation from more severe test conditions to the usual conditions. The acceleration factor is f(t)/t. The differential acceleration factor is df(t)/dt. Acceptance number: The largest numbers of defects that can occur in an acceptance sampling plan and still have the lot accepted. Acceptance Sampling Plan: An accept/reject test the purpose of which is to accept or reject a lot of items or material based on random samples from the lot. Assessment: A critical appraisal including qualitative judgements about an item, such as importance of analysis results, design criticality, and failure effect. Attribute (Inspection By): A term used to designate a method of measurement whereby units are examined by noting the presence (or absence) of some characteristic or attribute in each of the units in the group under consideration and by counting how many units do (or do not) possess it. Inspection by attributes can be two kinds: either the unit of product is classified simply as defective or no defective or the number of defects in the unit of product is counted with respect to a given requirement or set of requirements. Attribute Testing: Testing to evaluate whether or not an item possesses a specified attribute. Auger Electron Spectrometer: An instrument, which identifies elements on the surface of a sample. It excites the area of interest with an electron beam and observes the resultant emitted Auger electrons. These electrons have the specific characteristics of the near surface elements. It is usually used to identify very thin films, often surface contaminants. Availability (Operational Readiness): The probability that at any point in time the system is either operating satisfactorily or ready to be placed in operation on demand when used under stated conditions. Average Outgoing Quality (AOQ): The average quality of outgoing product after 100 % inspection of rejected lot, with replacement by good units of all defective units found in in- spection. Document Number: 82501 Rev. 1.3, 20-Sep-06 Bathtub Curve: A plot of failure rate of an item (whether repairable or not) vs. time. The failure rate initially decreases, then stays reasonably constant, then begins to rise rather rapidly. It has the shape of bathtub. Not all items have this behaviour. Bias: (1) The difference between the s-expected value of an estimator and the value of the true parameter; (2) Applied voltage. Burn-in: The initial operation of an item to stabilize its characteristics and to minimize infant mortality in the field. Confidence Interval: The interval within which it is asserted that the parameters of a probability distribution lies. Confidence Level: Equals 1 - D where D = the risk (%). Corrective Action: A documented design, process, procedure, or materials change to correct the true cause of a failure. Part replacement with a like item does not constitute appropriate corrective action. Rather, the action should make it impossible for that failure to happen again. Cumulative Distribution Function (CDF): The probability that the random variable takes on any value less than or equal to a value x, e.g. F(x) = CDF (x) = Pr (x d X). Defect: A deviation of an item from some ideal state. The ideal state usually is given in a formal specification. Degradation: A gradual deterioration in performance as a function of time. Derating: The intentional reduction of stress / strength ratio in the application of an item, usually for the purpose of reducing the occurrence of stressrelated failures. Duty Cycle: A specified operating time of an item, followed by a specified time of no operation. Early Failure Period: That period of life, after final assembly, in which failures occur at an initially high rate because of the presence of defective parts and workmanship. This definition applies to the first part of the bathtub curve for failure rate (infant mortality). EDX Spectrometer: Generally used with a scanning electron microscope (SEM) to provide elemental analysis of X-rays generated on the region being hit by the primary electron beam. Effectiveness: The capability of the system or device to perform its function. EOS – Electrical Overstress: The electrical stressing of electronic components beyond specifications. May be caused by ESD. www.vishay.com 115 Quality and Reliability Vishay Semiconductors ESD – Electrostatic Discharge: The transfer of electrostatic charge between bodies at different electrostatic potentials caused by direct contact or induced by an electrostatic field. Many electronic components are sensitive to ESD and will be degraded or fail. Expected Value: A statistical term. If x is a random variable and F (x) it its CDF, the E (x) = xdF (x), where the integration is over all x. For continuous variables with a pfd, this reduces to E (x) = ³ x pfd (x) dx. For discrete random variables with a pfd, this reduces to E (x) = 6xnp (xn) where the sum is over all n. Exponential Distribution: A 1-parameter distribution (O > 0, t d 0) with: pfd (t) = lexp (-Ot); Cdf (t) 0 1 – exp (-Ot); Sf (t) = exp (-Ot) ; failure rate = O; mean time-to-failure = 1/O. This is the constant failure-rate-distribution. Failure: The termination of the ability of an item to perform its required function. Failure Analysis: The identification of the failure mode, the failure mechanism, and the cause (i.e., defective soldering, design weakness, contamination, assembly techniques, etc.). Often includes physical dissection. Failure, Catastrophic: A sudden change in the operating characteristics of an item resulting in a complete loss of useful performance of the item. Failure, Degradation: A failure that occurs as a result of a gradual or partial change in the operating characteristics of an item. Failure, Initial: The first failure to occur in use. Failure, Latent: A malfunction that occurs as a result of a previous exposure to a condition that did not result in an immediately detectable failure. Example: Latent ESD failure. Failure Mechanism: The mechanical, chemical, or other process that results in a failure. Failure Mode: The effect by which a failure is observed. Generally, describes the way the failure occurs and tells "how" with respect to operation. Failure Rate: (A) The conditional probability density that the item will fail just after time t, given the item has not failed up to time t; (B) The number of failures of an item per unit measure of life (cycles, time, miles, events, etc.) as applicable for the item. Failure, Wearout: Any failure for which time of occurrence is governed by rapidly increasing failure rate. FIT: Failure Unit; (also, Failures In Time) Failures per 109 hours. Functional Failure: A failure whereby a device does not perform its intended function when the inputs or controls are correct. www.vishay.com 116 Gaussian Distribution: A 2-parameter distribution with: 1 § x – u· 2 --- -----------V ¹ 2© 1 pfd (x) = ------------- e V 2S Cdf (x) = guaf (x). SF (x) = gaufc (x). "Mean value of x" u, "standard deviation of x" = V Hazard Rate: Instantaneous failure rate. Hypothesis, Null: A hypothesis stating that there is no difference between some characteristics of the parent populations of several different samples, i.e., that the samples came from similar populations. Infant Mortality: Premature catastrophic failures occurring at a much greater rate than during the period of useful life prior to the onset of substantial wear out. Inspection: The examination and testing of supplies and services (including when appropriate, raw materials, components, and intermediate assemblies) to determine whether they conform to specified requirements. Inspection by Attributes: Inspection whereby either the unit of product or characteristics thereof is classified simply as defective or no defective or the number of defects in the unit of product is counted with respect to a given requirement. Life Test: A test, usually of several items, made for the purpose of estimating some characteristic(s) of the probability distribution of life. Lot: A group of units from a particular device type submitted each time for inspection and / or testing is called the lot. Lot Reject Rate (LRR): The lot reject rate is the percentage of lots rejected form the lots evaluated. Lot Tolerance Percent Defective (LTPD): The percent defective, which is to be, accepted a minimum or arbitrary fraction of the time, or that percent defective whose probability of rejection is designated by b. Mean: (A) The arithmetic mean, the expected value; (B) As specifically modified and defined, e.g., harmonic mean (reciprocals), geometric mean (a product), logarithmic mean (logs). Mean Life: R(t)dt; where R(t) = the s-reliability of the item; t = the interval over which the mean life is desired, usually the useful life (longevity). Mean-Life-Between-Failures: The concept is the same as mean life except that it is for repaired items and is the mean up-time of the item. The formula is the same as for mean life except that R(t) is inter- Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality and Reliability Vishay Semiconductors preted as the distribution of up-times. Mean-TimeBetween-Failures (MTBF): For a particular interval, the total functioning life of a population of an item divided by the total number of failures within the population during the measurement interval. The definition holds for time, cycles, miles, events, or other measure of life units. Mean-Time-To-Failure (MTTF): See "Mean Life". Mean-Time-To-Repair (MTTR): The total corrective maintenance time divided by the total number of corrective maintenance actions during a given period of time. MTTR: = G(t)dt; where G(t) = Cdf of repair time; T – maximum allowed repair time, i.e., item is treated as no repairable at this echelon and is discarded or sent to a higher echelon for repair. Operating Characteristic (OC) Curve: A curve showing the relation between the probability of acceptance and either lot quality or process quality, whichever is applicable. Part Per Million (PPM): PPM is arrived at by multiplying the percentage defective by 10,000. Example: 0.1 % = 1,000 PPM. Population: The totality of the set of items, units, measurements, etc., real or conceptual that is under consideration. Probability Distribution: A mathematical function with specific properties, which describes the probability that a random variable will take on a value or set of values. If the random variable is continuous and well behaved enough, there will be a pfd. If the random variable is discrete, there will be a pmf. Qualification: The entire process by which products are obtained from manufacturers or distributors, examined and tested, and then identified on a Qualified Product List. Quality: A property, which refers to, the tendency of an item to be made to specific specifications and / or the customer’s express needs. See current publications by Juran, Deming, Crosby, et al. Quality Assurance: A system of activities that provides assurance that the overall quality control job is, in fact, being done effectively. The system involves a continuing evaluation of the adequacy and effectiveness of the overall quality control program with a view to having corrective measures initiated where necessary. For a specific product or service, this involves verifications, audits, and the evaluation of the quality factors that affect the specification, production inspection, and use of the product or service. Document Number: 82501 Rev. 1.3, 20-Sep-06 Quality Characteristics: Those properties of an item or process, which can be measured, reviewed, or observed and which are identified in the drawings, specifications, or contractual requirements. Reliability becomes a quality characteristic when so defined. Quality Control (QC): The overall system of activities that provides a quality of product or service, which meets the needs of users; also, the use of such a system. Random Samples: As commonly used in acceptance sampling theory, the process of selecting sample units in such a manner that all units under consideration have the same probability of being selected. Reliability: The probability that a device will function without failure over a specified time period or amount of usage at stated conditions. Reliability Growth: Reliability growth is the effort, the resource commitment, to improve design, purchasing, production, and inspection procedures to improve the reliability of a design. Risk: D : The probability of rejecting the null hypothesis falsely. Scanning Electron Microscope (SEM): An instrument, which provides a visual image of the surface features of an item. It scans an electron beam over the surface of a sample while held in a vacuum and collects any of several resultant particles or energies. The SEM provides depth of field and resolution significantly exceeding light microscopy and may be used at magnifications exceeding 50,000 times. Screening Test: A test or combination of tests intended to remove unsatisfactory items or those likely to exhibit early failures. Significance: Results that show deviations between hypothesis and the observations used as a test of the hypothesis, greater than can be explained by random variation or chance alone, are called statistically significant. Significance Level: The probability that, if the hypothesis under test were true, a sample test statistic would be as bad as or worse than the observed test statistic. SPC: Statistical Process Control. Storage Life (Shelf Life): The length of time an item can be stored under specified conditions and still meet specified requirements. Stress: A general and ambiguous term used as an extension of its meaning in mechanics as that which could cause failure. It does not distinguish between www.vishay.com 117 Quality and Reliability Vishay Semiconductors those things which cause permanent damage (deterioration) and those things, which do not (in the absence of failure). Variance: The average of the squares of the deviations of individual measurements from their average. It is a measure of dispersion of a random variable or of data. Wearout: The process of attribution which results in an increase of hazard rate with increasing age (cycles, time, miles, events, etc.) as applicable for the item. Abbreviations AQL CAR DIP ECAP EMC EMI EOS ESD FAR FIT FMEA FTA h (t) LTPD MOS MRB MTBF MTTF MTTR PPM PRST QA QC QPL RPM SCA SEM TW Z (t) O www.vishay.com 118 Acceptable Quality Level Corrective Action Report / Request Dual In-Line Package Electronic Circuit Analysis Program Electro Magnetic Compatibility Electro Magnetic Interference Electrical Overstress Electrostatic Discharge Failure Analysis Report / Request (Failure In Time) Failure Unit; Failures / 109 hours Failure Mode and Effects Analysis Fault Tree Analysis Hazard Rate Lot Tolerance Percent Defective Metal Oxide Semiconductor Material Review Board Mean-Time-Between-Failures Mean-Time-To-Failure Mean-Time-To-Repair Parts Per Million Probability Ratio Sequential Test Quality Assurance Quality Control Qualified Products List Reliability Planning and Management Sneak Circuit Analysis Scanning Electron Microscope Wearout Time Hazard Rate Failure Rate (Lambda) Document Number: 82501 Rev. 1.3, 20-Sep-06 Contents TFBS4650..............................120 TFBS4652..............................131 TFBS4710..............................142 TFBS4711..............................151 SIR TFDU4100 ............................. 160 TFDU4101 ............................. 171 TFDU4202 ............................. 185 (9.6 kbit/s to 115 kbit/s) TFDU4203 ............................. 194 TFDU4300 ............................. 204 www.vishay.com 3 TFBS4650 Vishay Semiconductors Infrared Transceiver 9.6 kbit/s to 115.2 kbit/s (SIR) Description The TFBS4650 is one of the smallest IrDA® compliant transceivers available. It supports data rates up to 115 kbit/s. The transceiver consists of a PIN photodiode, infrared emitter, and control IC in a single package. 20206 Features • Compliant with the IrDA physical layer IrPHY 1.4 (low power specification, 9.6 kbit/s to 115.2 kbit/s) e4 • Link distance: 30 cm/20 cm full 15° cone with standard or low power IrDA, respectively. Emission intensity can be set by an external resistor to increase the range for extended low power spec to > 50 cm • Typical transmission distance to standard device: 50 cm • Small package L 6.8 mm x W 2.8 mm x H 1.6 mm • Low current consumption 75 μA idle at 3.6 V • Shutdown current 10 nA typical at 25 °C • Operates from 2.4 V to 3.6 V within specification over full temperature range from - 25 °C to + 85 °C • Split power supply, emitter can be driven by a separate power supply not loading the regulated. U.S. Pat. No. 6,157,476 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • Mobile phone • PDAs Parts Table Part Description Qty / Reel TFBS4650-TR1 Oriented in carrier tape for side view surface mounting 1000 pcs TFBS4650-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs www.vishay.com 120 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4650 Vishay Semiconductors Functional Block Diagram VCC Tri-State Driver PD Amplifier RXD Comparator IREDA SD Mode Control IRED Driver TXD IRED IREDC ASIC GND 19283 Pin Description Pin Number Function Description 1 IREDA IRED Anode, connected via a current limiting resistor to VCC2. A separate unregulated power supply can be used. I/O Active 2 IREDC IRED Cathode, do not connect for standard operation 3 TXD Transmitter Data Input. Setting this input above the threshold turns on the transmitter. This input switches the IRED with the maximum transmit pulse width of about 50 μs. I HIGH 4 RXD Receiver Output. Normally high, goes low for a defined pulse duration with the rising edge of the optical input signal. Output is a CMOS tri-state driver, which swings between ground and Vcc. Receiver echoes transmitter output. O LOW 5 SD Shut Down. Logic Low at this input enables the receiver, enables the transmitter, and un-tri-states the receiver output. It must be driven high for shutting down the transceiver. I HIGH 6 VCC Power Supply, 2.4 V to 3.6 V. This pin provides power for the receiver and transmitter drive section. Connect VCC1 via an optional filter. 7 GND Ground Pinout TFBS4650, bottom view weight 0.05 g 19284 Document Number 84672 Rev. 1.1, 03-Jul-06 www.vishay.com 121 TFBS4650 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 Typ. 6.0 V Supply voltage range, transmitter 0 V < VCC1 < 3.6 V VCC2 - 0.5 6.0 V Voltage at RXD All states Vin - 0.5 VCC + 0.5 V Input voltage range, transmitter TXD Independent of VCC1 or VCC2 Vin - 0.5 6.0 V Input currents For all pins, except IRED anode pin - 40 40 mA Output sinking current Power dissipation PD Junction temperature Storage temperature range Soldering temperature ***) see section Recommended Solder Profile Repetitive pulse output current < 90 μs, ton < 20 % Average output current (transmitter) 125 °C - 25 + 85 °C Tstg - 40 + 100 °C °C IIRED (RP) 500 mA IIRED (DC) 100 mA Virtual source size Method: (1-1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie *) mA mW Tamb TJ Ambient temperature range (operating) 20 250 0.8 mm *) mW/sr (500)**) Due to the internal limitation measures the device is a "class1" device. **) IrDA specifies the max. intensity with 500 mW/sr ***) Sn/Pb-free soldering. The product passed VISHAY’s standard convection reflow profile soldering test. Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhY 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhY 1.1, followed by IrPhY 1.2, adding the SIR Low Power Standard. IrPhY 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhY 1.4. A new version of the standard in any case obsoletes the former version. www.vishay.com 122 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4650 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage range Symbol Min VCC 2.4 Typ. Max Unit 3.6 V 130 μA Dynamic supply current Idle, dark ambient SD = Low (< 0.8 V), Eeamb = 0 klx, ICC 90 ICC 75 2 Ee < 4 mW/m2 - 25 °C dT d+ 85 °C Idle, dark ambient SD = Low (< 0.8 V), Eeamb = 0 klx, μA Ee < 4 mW/m2 T = + 25 °C 3 mA ISD 0.1 μA ISD 1.0 μA °C Peak supply current during transmission SD = Low, TXD = High Iccpk Shutdown supply current dark ambient SD = High (> VCC - 0.5 V), T = 25 °C, Ee = 0 klx Shutdown supply current, dark ambient SD = High (> VCC - 0.5 V), - 25 °C dT d+ 85 °C Operating temperature range TA - 25 + 85 Input voltage low (TXD, SD) VIL - 0.5 0.5 V VIH VCC - 0.5 6.0 V Input voltage high VCC = 2.4 V to 3.6 V Input voltage threshold SD VCC = 2.4 V to 3.6 V 1.8 V Output voltage low VCC = 2.4 V to 3.6 V CLOAD = 15 pF VOL - 0.5 VCC x 0.15 V Output voltage high VCC = 2.4 V to 3.6 V CLOAD = 15 pF VOH VCC x 0.8 VCC + 0.5 V RXD to VCC pull-up impedance SD = VCC VCC = 2.4 V to 5 V RRXD Input capacitance (TXD, SD) Document Number 84672 Rev. 1.1, 03-Jul-06 0.9 CI 1.35 500 k: 6 pF www.vishay.com 123 TFBS4650 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Sensitivity: Minimum irradiance Ee in angular range *)**) 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm Ee Maximum irradiance Ee in angular range ***) O = 850 nm to 900 nm Ee 5 (500) No receiver output input irradiance According to IrDA IrPHY 1.4, Appendix A1, fluorescent light specification Ee 4 (0.4) Typ. Max Unit 40 (4.0) 81 (8.1) mW/m2 (μW/cm2) kW/m2 (mW/cm2) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 20 100 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 20 100 ns RXD pulse width of output signal, 50%****) Input pulse width 1.63 μs tPW 1.7 2.9 μs Receiver start up time Power on delay Latency tL 2.0 100 150 μs 50 200 μs *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps **) IrDA sensitivity definition: Minimum Irradiance E In Angular Range, power per unit area. The receiver must meet the BER specification e while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance E In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maxe imum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. ****) RXD output is edge triggered by the rising edge of the optical input signal. The output pulse duration is independent of the input pulse duration. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). www.vishay.com 124 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4650 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Max Unit IRED operating current, current controlled The IRED current is internally controlled but also can be reduced by an external resistor R1 ID 200 400 mA 1 μA 4 150 mW/sr Output leakage IRED current Tamb = 85°C Output radiant intensity *) D = 0°, 15°, TXD = High, SD = Low, VCC1 = 3.0 V, VCC2 = 3.0 V, R1 = 30 :(resulting in about 50 mA drive current) Ie Output radiant intensity *) D = 0°, 15°, TXD = High, SD = Low, VCC1 = 3.0 V, VCC2 = 3.0 V, R1 = 0 :, If = 300 mA Ie Output radiant intensity *) VCC1 = 5.0 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie Saturation voltage of IRED driver VCC = 3.0 V, If = 50 mA IIRED Optical rise time, Optical fall time Optical output pulse duration 25 mW/sr 0.04 VCEsat Peak - emission wavelength Optical output pulse duration Typ. mW/sr 0.4 Op 880 tropt, tfopt 20 V 886 900 nm 100 ns Input pulse width t < 30 μs Input pulse width t t 30 μs topt topt 30 t 50 300 μs μs Input pulse width t = 1.63 μs topt 1.45 1.61 2.2 μs 20 % Optical overshoot *) The radiant intensity can be adjusted by the external current limiting resistor to adapt the intensity to the desired value. The given value is for minimum current consumption. This transceiver can be adapted to > 50 cm operation by increasing the current to > 200 mA, e.g. operating the transceiver without current control resistor (i.e. R1 = 0 :and using the internal current control. Table 1. Truth table Inputs Outputs SD TXD Optical input Irradiance mW/m2 RXD Transmitter high x x Tri-state floating with a weak pull-up to the supply voltage 0 Ie low high x low (echo on) low high > 50μs x high 0 low low <4 high 0 low low > Min. irradiance Ee < Max. irradiance Ee low (active) 0 low low > Max. irradiance Ee x 0 Document Number 84672 Rev. 1.1, 03-Jul-06 www.vishay.com 125 TFBS4650 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS4650 needs only one additional external component when the IRED drive current should be minimized for minimum current consumption according the low power IrDA standard. When combined operation in IrDA and Remote Control is intended no current limiting resistor is recommended. However, depending on the entire system design and board layout, additional components may be required (see figure 1). When long wires are used for bench tests, the capacitors are mandatory for testing rise/fall time correctly. VCC2 recommended to position C2 as close as possible to the transceiver power supply pins. When connecting the described circuit to the power supply, low impedance wiring should be used. In case of extended wiring the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current is rise time. In that case another 10 μF cap at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Wienfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. IRED Anode R1 IRED Cathode VCC1 GND Table 2. Recommended Application Circuit Components VCC R2 C1 C2 Ground SD SD Component Recommended Value Txd Txd C1, C2 Rxd Rxd 0.1 μF, Ceramic Vishay part# VJ 1206 Y 104 J XXMT R1 See table 3 R2 47 :, 0.125 W (VCC1 = 3 V) 19286 Table 3. Recommended resistor R1 [:] Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage Vcc2 and eliminates the inductance of the power supply line. This one should be a small ceramic version or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is necessary for controlling the IRED drive current when the internally controlled current is too high for the application. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. As already stated above R2, C1 and C2 are optional and depend on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly www.vishay.com 126 VCC2 [V] Minimized current consumption, IrDA Low power compliant 2.7 24 3.0 30 3.3 36 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4650 Vishay Semiconductors Recommended Solder Profiles Solder Profile for Sn/Pb soldering 260 Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 2. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS4650 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 3 is VISHAY's recommended profiles for use with the TFBS4650 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Document Number 84672 Rev. 1.1, 03-Jul-06 Figure 3. Solder Profile, RSS Recommendation www.vishay.com 127 TFBS4650 Vishay Semiconductors Package Dimensions 19322 Figure 4. TFBS4650 mechanical dimensions, tolerance ± 0.2 mm, if not otherwise mentioned 19729 Figure 5. TFBS4650 soldering footprint, tolerance ± 0.2 mm, if not otherwise mentioned www.vishay.com 128 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4650 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 Document Number 84672 Rev. 1.1, 03-Jul-06 W3 max. www.vishay.com 129 TFBS4650 Vishay Semiconductors Tape Dimensions in mm www.vishay.com 130 Document Number 84672 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Infrared Transceiver 9.6 kbit/s to 115.2 kbit/s (SIR) Description The TFBS4652 is one of the smallest IrDA compliant transceivers available. It supports data rates up to 115 kbit/s. The transceiver consists of a PIN photodiode, infrared emitter, and control IC in a single package. Features 20206 • Compliant with the IrDA® physical layer IrPHY 1.4 (low power specification, 9.6 kbit/s to 115.2 kbit/s) e4 • Link distance: 30 cm/20 cm full 15° cone with standard or low power IrDA, respectively. Emission intensity can be set by an external resistor to increase the range to > 50 cm • Typical transmission distance to standard device: 50 cm • Small package L 6.8 mm x W 2.8 mm x H 1.6 mm • Low current consumption 75 μA idle at 3.6 V • Operates from 2.4 V to 3.6 V within specification over full temperature range from - 25 °C to + 85 °C • Split power supply, emitter can be driven by a separate power supply not loading the regulated. U.S. Pat. No. 6,157,476 • Adjustable to logic I/O voltage swing from 1.5 V to 5.5 V • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • Mobile phone • PDAs Parts Table Part Description Qty / Reel TFBS4652-TR1 Oriented in carrier tape for side view surface mounting 1000 pcs TFBS4652-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs Document Number 84671 Rev. 1.1, 03-Jul-06 www.vishay.com 131 TFBS4652 Vishay Semiconductors Functional Block Diagram VCC Vlog Tri-State Driver PD Amplifier RXD Comparator IREDA SD Mode Control IRED Driver IRED TXD ASIC GND 19288 Pin Description Pin Number Function Description I/O Active 1 IREDA IRED Anode, connected via a current limiting resistor to Vcc2. A separate unregulated power supply can be used. 2 RXD Receiver Output. Normally high, goes low for a defined pulse duration with the rising edge of the optical input signal. Output is a CMOS tri-state driver, which swings between ground and Vlogic. Receiver echoes transmitter output. O LOW 3 TXD Transmitter Data Input. Setting this input above the threshold turns on the transmitter. This input switches the IRED with the maximum transmit pulse width of about 50 μs. I HIGH 4 SD Shut Down. Logic Low at this input enables the receiver, enables the transmitter, and un-tri-states the receiver output. It must be driven high for shutting down the transceiver. I HIGH I 5 Vlogic Reference for the logic swing of the output and the input logic levels. 6 VCC Power Supply, 2.4 V to 3.6 V. This pin provides power for the receiver and transmitter drive section. Connect Vcc1 via an optional filter. 7 GND Ground Pinout Definitions: TFBS4652, bottom view weight 0.05 g In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhY 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhY 1.1, followed by IrPhY 1.2, adding the SIR Low Power Standard. IrPhY 1.3 extended the 19284 Low Power Option to MIR and FIR and VFIR was added with IrPhY 1.4. A new version of the standard in any case obsoletes the former version. www.vishay.com 132 Document Number 84671 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 Typ. 6.0 V Supply voltage range, transmitter 0 V < VCC1 < 3.6 V VCC2 - 0.5 6.0 V Supply voltage range, digital supply 0 V < VCC1 < 3.6 V Vlogic - 0.5 6.0 V Voltage at RXD All states Vin - 0.5 Vlogic + 0.5 V Input voltage range, transmitter TXD Independent of Vdd or Vlogic Vin - 0.5 6.0 V Input currents For all pins, except IRED anode pin - 40 40 mA Output sinking current Power dissipation PD Junction temperature TJ Ambient temperature range (operating) Storage temperature Soldering temperature ***) see section Recommended Solder Profile Repetitive pulse output current < 90 μs, ton < 20 % Average output current (transmitter) mA mW 125 °C Tamb - 25 + 85 °C Tstg - 40 + 100 °C °C IIRED (RP) 500 mA IIRED (DC) 100 mA Virtual source size Method: (1-1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie *) 20 250 0.8 mm mW/sr *) (500)**) Due to the internal limitation measures the device is a "class1" device. **) IrDA ***) specifies the max. intensity with 500 mW/s.r Sn/Pb-free soldering. The product passed VISHAY’s standard convection reflow profile soldering test. Document Number 84671 Rev. 1.1, 03-Jul-06 www.vishay.com 133 TFBS4652 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage range Symbol Min VCC 2.4 Typ. Max Unit 3.6 V 130 μA Dynamic Supply current Idle, dark ambient SD = Low (< 0.8 V), Eeamb = 0 klx, ICC 90 ICC 75 Iccpk 2 Ee < 4 mW/m2 - 25 °C dT d+ 85 °C Idle, dark ambient SD = Low (< 0.8 V), Eeamb = 0 klx, μA Ee < 4 mW/m2 T = + 25 °C Peak supply current during transmission SD = Low, TXD = High Idle, dark ambient at Vlogic - pin SD = Low (< 0.8 V), Eeamb = 0 klx, 3 mA Ilogic 1 μA Ee < 4 mW/m2 Shutdown supply current Dark ambient SD = High (> Vlogic - 0.5 V), T = 25 °C, Ee = 0 klx ISD 0.1 μA Shutdown supply current, dark ambient SD = High (> Vlogic - 0.5 V), T = 70 °C, Ee = 0 klx ISD 2.0 μA Shutdown supply current, dark ambient SD = High (> Vlogic - 0.5 V), T = 85 °C, Ee = 0 klx ISD 3.0 μA + 85 °C Output voltage low IOL = 0.2 mA, VCC = 2.4 V Cload = 15 pF VOL Output voltage high IOL = 0.2 mA, VCC = 2.4 V Cload = 15 pF VOH RXD to Vcc pull-up impedance SD = VCC, VCC = 2.4 V to 5 V RRXD Operating temperature range TA Input voltage low (TXD, SD) Input voltage high (TXD, SD) VCC = 2.4 V to 3.6 V Input voltage threshold SD V CC = 2.4 V to 3.6 V Input capacitance (TXD, SD) www.vishay.com 134 - 25 0.3 Vlogic - 0.5 V Vlogic 500 V k: VIL - 0.5 0.5 V VIH Vlogic - 0.5 Vlogic + 0.5 V 0.9 CI 0.5 x Vlogic 0.66 x Vlogic 6 V pF Document Number 84671 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Sensitivity: Minimum irradiance Ee in angular range *)**) 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm Ee Maximum irradiance Ee in angular range ***) O = 850 nm to 900 nm Ee 5 (500) No output receiver input irradiance According to IrDA IrPHY 1.4, Appendix A1, fluorescent light specification Ee 4 (0.4) Typ. Max Unit 40 (4.0) 81 (8.1) mW/m2 (μW/cm2) kW/m2 (mW/cm2) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 20 100 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 20 100 ns RXD pulse width of output signal, 50 %****) Input pulse width 1.63 μs tPW 1.7 2.9 μs Receiver start up time Power on delay tL 30 Latency 100 150 μs 50 100 μs *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps. **) IrDA sensitivity definition: Minimum Irradiance E In Angular Range, power per unit area. The receiver must meet the BER specificae tion while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance E In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the e maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. ****) RXD output is edge triggered by the rising edge of the optical input signal. The output pulse duration is independent of the input pulse duration. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). Document Number 84671 Rev. 1.1, 03-Jul-06 www.vishay.com 135 TFBS4652 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Max Unit IRED operating current, current controlled The IRED current is internally controlled but also can be reduced by an external resistor R1 ID 200 400 mA 1 μA 4 150 mW/sr Output leakage IRED current Tamb = 85°C Output radiant intensity*) D = 0°, 15°, TXD = High, SD = Low, VCC1 = 3.0 V, VCC2 = 3.0 V, R1 = 30 :(resulting in about 50 mA drive current) Ie Output radiant intensity*) D = 0°, 15°, TXD = High, SD = Low, VCC1 = 3.0 V, VCC2 = 3.0 V, R1 = 0 :, If = 300 mA Ie Output radiant intensity*) VCC1 = 5.0 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie Saturation voltage of IRED driver VCC = 3.0 V, If = 50 mA IIRED Optical rise time, Optical fall time Optical output pulse duration 25 mW/sr 0.04 VCEsat Peak - emission wavelength Optical output pulse duration Typ. mW/sr 0.4 Op 880 tropt, tfopt 20 V 886 900 nm 100 ns Input pulse width t < 30 μs Input pulse width t t 30 μs topt topt 30 t 50 300 μs μs Input pulse width t = 1.63 μs t opt 1.45 1.61 2.2 μs 20 % Optical overshoot *) The radiant intensity can be adjusted by the external current limiting resistor to adapt the intensity to the desired value. The given value is for minimum current consumption. This transceiver can be adapted to > 50 cm operation by increasing the current to > 200 mA, e.g. operating the transceiver without current control resistor (i.e. R1 = 0 :) and using the internal current control. Table 1. Truth table Inputs TXD Optical input Irradiance mW/m2 RXD Transmitter high x x Tri-state floating with a weak pull-up to the supply voltage 0 Ie low high x low (echo on) low high > 100μs x high 0 low low <2 high 0 low low > Min. irradianceEe < Max. irradiance Ee low (active) 0 low low > Max. irradiance Ee x 0 www.vishay.com 136 Outputs SD Document Number 84671 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS4652 needs only one additional external component when the IRED drive current should be minimized for minimum current consumption according the low power IrDA standard. When combined operation in IrDA and Remote Control is intended no current limiting resistor is recommended. When long wires are used for bench tests, the capacitors are mandatory for testing rise/fall time correctly. VCC2 IRED Anode R1 Vlogic VCC1 Vlogic VCC R2 C1 GND C2 Ground SD SD TXD TXD RXD RXD 19289 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage VCC2 and eliminates the inductance of the power supply line. This one should be a small ceramic version or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is necessary for controlling the IRED drive current when the internally controlled current is too high for the application. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. As already stated above R2, C1 and C2 are optional and depend on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to Document Number 84671 Rev. 1.1, 03-Jul-06 the transceiver power supply pins. When connecting the described circuit to the power supply, low impedance wiring should be used. In case of extended wiring the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current is rise time. In that case another 10 μF cap at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Wienfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 2. Recommended Application Circuit Components Component Recommended Value C1, C2 0.1 μF, Ceramic, Vishay part# VJ 1206 Y 104 J XXMT R1 See table 3 R2 47 :, 0.125 W (VCC1 = 3 V) Table 3. Recommended resistor R1 [:] VCC2 [V] Minimized current consumption, IrDA Low power compliant 2.7 24 3.0 30 3.3 36 www.vishay.com 137 TFBS4652 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 2. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS4652 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 3 is VISHAY's recommended profiles for use with the TFBS4652 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 3. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 138 Document Number 84671 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Package Dimensions in mm 19322 Figure 4. TFBS4652 mechanical dimensions, tolerance ± 0.2 mm, if not otherwise mentioned 19729 Figure 5. TFBS4652 soldering footprint, tolerance ± 0.2 mm, if not otherwise mentioned Document Number 84671 Rev. 1.1, 03-Jul-06 www.vishay.com 139 TFBS4652 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 140 W3 max. Document Number 84671 Rev. 1.1, 03-Jul-06 TFBS4652 Vishay Semiconductors Tape Dimensions in mm 19286 Document Number 84671 Rev. 1.1, 03-Jul-06 www.vishay.com 141 TFBS4710 Vishay Semiconductors Serial Infrared Transceiver SIR, 115.2 kbit/s, 2.7 V to 5.5 V Operation Description The TFBS4710 is a low profile, full range Infrared Data Transceiver module. It supports IrDA data rates up to 115.2 kbit/s (SIR). The transceiver module consists of a photo PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total front-end solution in a single package. The device has a link distance of 1 meter. The RXD pulse width is independent of the duration of TXD pulse and always stays at a fixed width thus making the device optimum for all standard SIR Encoder/ Decoder and interfaces. The Shut Down (SD) feature cuts current consumption to typically 10 nA. 18071 Features • Compliant with the latest IrDA physical layer specification (9.6 kbit/s to 115.2 kbit/s) e4 • Small package: H 2.74 mm x D 3.33 mm x L 8.96 mm • Typical Link distance 1 m • Drop in replacement for IRM5000D/ IRMT5000 • Battery & Power Management Features: > Idle Current - 75 μA Typical > Shutdown Current - 10 nA Typical > Operates from 2.4 V - 5.0 V within specification over full temperature range from - 25 °C to + 85 °C • Remote Control - transmit distance up to 8 meters • Tri-State Receiver Output, floating in shutdown with a weak pull-up • Fixed RXD output pulse width (2 μs typical) • Meets IrFM Fast Connection requirements • Split power supply, an independant, unregulated supply for IRED Anode and a well regulated supply for VCC • Directly Interfaces with Various Super I/O and Controller Devices and Encoder/ Decoder such as TOIM4232 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance to RoHS 2002/95/EC and WEEE 202/96EC Applications • • • • • • • Ideal for Battery Operated Devices PDAs Mobile Phones Electronic Wallet (IrFM) Notebook Computers Digital Still and Video Cameras Printers, Fax Machines, Photocopiers, Screen Projectors • • • • • • • • Data Loggers External Infrared Adapters (Dongles) Diagnostics Systems Medical and Industrial Data Collection Devices Kiosks, POS, Point and Pay Devices GPS Access Control Field Programming Devices Parts Table Part Description Qty / Reel TFBS4710-TR1 Oriented in carrier tape for side view surface mounting 1000 pcs TFBS4710-TT1 Oriented in carrier tape for top view surface mounting 1000 pcs www.vishay.com 142 Document Number 82612 Rev. 1.5, 03-Jul-06 TFBS4710 Vishay Semiconductors Functional Block Diagram VCC1 Push-Pull Driver Amplifier Comparator RXD VCC2 Logic & SD TXD Controlled Driver Control RED C GND 18282 Pinout Definitions: TFBS4710 weight 100 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low 1 2 3 4 5 6 Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any case obsoletes the former ver- 18511 sion. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). Pin Description Pin Number Function Description 1 IRED Anode IRED Anode is connected to a power supply. The LED current can be decreased by adding a resistor in series between the power supply and IRED Anode. A separate unregulated power supply can be used at this pin. I/O Active 2 TXD This Input is used to turn on IRED transmitter when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs I HIGH 3 RXD Received Data Output, normally stays high but goes low for a fixed duration during received pulses. It is capable of driving a standard CMOS or TTL load. O LOW 4 SD Shutdown. Setting this pin active for more than 1.5 ms switches the device into shutdown mode I HIGH 5 VCC Regulated Supply Voltage 6 GND Ground Document Number 82612 Rev. 1.5, 03-Jul-06 www.vishay.com 143 TFBS4710 Vishay Semiconductors Absolute Maximum Ratings Reference Point Ground, Pin 6 unless otherwise noted. Parameter Test Conditions Supply voltage range, all states Input current For all Pins except IRED Anode Pin Symbol Min VCC - 0.3 Typ. ICC Output Sink Current, RXD Average output current, pin 1 20 % duty cycle Repetitive pulsed output current < 90 μs, ton < 20 % IRED anode voltage, pin 1 Voltage at all inputs and outputs Vin > VCC is allowed Power dissipation See derating curve Storage temperature range Soldering temperature Unit V 10.0 mA 25.0 mA IIRED (DC) 60 mA IIRED (RP) 300 mA V VIREDA - 0.5 + 6.0 VIN - 0.5 + 6.0 V 200 mW Junction temperature Ambient temperature range (operating) Max + 6.0 125 °C Tamb - 30 + 85 °C Tstg - 40 + 100 °C 260 °C Max Unit See Recommended Solder Profile Electrical Characteristics Transceiver Tamb = 25 °C, VCC = VIREDA = 2.4 V to 5.5 V unless otherwise noted. Parameter Test Conditions Supply voltage range, all states Idle supply current at V CC1 (receive mode, no signal) Symbol Min VCC 2.4 Typ. 5.5 V 130 μA SD = Low, Ee = 1 klx*), Tamb = - 25 °C to + 85 °C, VCC1 = VCC2 = 2.7 V to 5.5 V ICC1 90 SD = Low, Ee = 1 klx*), Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V ICC1 75 Receive current VCC = 2.7 V ICC 280 Shutdown current SD = High, T = 25 °C, Ee = 0 klx ISD 2 μA SD = High, T = 85 °C ISD 3 μA Operating temperature range μA μA TA - 25 + 85 °C Output voltage low, RXD IOL = 1 mA VOL - 0.5 0.15 x VCC V Output voltage high, RXD IOH = - 500 μA VOH 0.8 x VCC VCC + 0.5 V IOH = - 250 μA VOH 0.9 x VCC VCC + 0.5 V RRXD 400 600 k: RXD to VCC impedance Input voltage low: TXD, SD Input voltage high: TXD, SD CMOS level (0.5 x VCC typ, threshold level) Input leakage current (TXD, SD) Vin = 0.9 x VCC Controlled pull down current SD, TXD = "0" or "1", 0 < Vin < 0.15 VCC SD, TXD = "0" or "1" Vin > 0.7 VCC Input capacitance www.vishay.com 144 500 VIL - 0.5 0.5 V VIH VCC - 0.5 6.0 V IICH -2 IIRTx IIRTx CIN -1 0 +2 μA + 150 μA 1 μA 5 pF Document Number 82612 Rev. 1.5, 03-Jul-06 TFBS4710 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted Symbol Min Typ. Max Unit Minimum detection threshold irradiance, SIR mode Parameter 9.6 kbit/s to 115.2 kbit/s O = 850 nm - 900 nm, D = 0°, 15° Test Conditions Ee 10 (1.0) 25 (2.5) 40 (4) mW/m2 Maximum detection threshold irradiance O = 850 nm - 900 nm Ee Maximum no detection threshold irradiance (μW/cm2) 5 (500) Ee kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr(RXD) 10 100 Fall time of output signal 90 % to 10 %, CL = 15 pF tf(RXD) 10 100 ns RXD pulse width Input pulse width > 1.2 μs tPW 1.65 3.0 μs Leading edge jitter Input Irradiance = 100 mW/m2, d 115.2 kbit/s 250 ns Standby /Shutdown delay After shutdown active 150 μs Receiver startup time Power-on delay 150 μs Latency 2.0 tL ns Transmitter Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted. Parameter Test Conditions IRED operating current Symbol Min Typ. Max Unit ID 250 300 350 mA Vf 1.4 1.8 1.9 V IIRED -1 1 μA 40 350 mW/sr 0.04 mW/sr IRED forward voltage Ir = 300 mA IRED leakage current TXD = 0 V, 0 < VCC < 5.5 V Output radiant intensity D = 0°, 15°, TXD = High, SD = Low Ie VCC = 5.0 V, D = 0°, 15°, TXD = High or SD = High (Receiver is inactive as long as SD = High) Ie D Output radiant intensity, angle of half intensity 70 ± 24 ° Peak-emission wavelength Op Spectral bandwidth 'O Optical rise time tropt 10 100 Optical fall time tfopt 10 100 ns Input pulse width 1.63 μs, 115.2 kbit/s topt 1.46 1.8 μs Input pulse width tTXD < 20 μs topt tTXD t + 0.15 μs Input pulse width tTXD t 20 μs topt 50 μs 25 % Optical output pulse duration Optical overshoot Document Number 82612 Rev. 1.5, 03-Jul-06 880 900 45 1.63 nm nm ns www.vishay.com 145 TFBS4710 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 1. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS4710 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 2 is VISHAY's recommended profiles for use with the TFBS4710 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 2. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 146 Document Number 82612 Rev. 1.5, 03-Jul-06 TFBS4710 Vishay Semiconductors Recommended Circuit Diagram Table 1. High Operating Temperature > 70 °C V CC IR Controller Vdd Rled TFBS4710 IREDA (1) IRTX IRRX IRMODE R1= 47: TXD (2) RXD (3) SD (4) Vcc (5) GND (6) GND C4 C2 C3 C1 4.7 μF 0.1μF 4.7 μF 0.1 μF 18281 Figure 3. Recommended Application Circuit The TFBS4710 integrates a sensitive receiver and a built-in power driver. This combination needs a careful circuit layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output (RXD) should be directly (DC) coupled to the I/O circuit. The combination of resistor R1 and capacitors C1, C2, C3 and C4 filter out any power supply noise to provide a smooth supply voltage. The placement of these components is critical. It is strongly recommended to position C3 and C4 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 and C3 while a ceramic capacitor should be used for C2 and C4. A current limiting resistor is not needed for normal operation. It is strongly recommended to use the Rled values mentioned in Table 1 below for high temperature operation. For Low Power Mode, IRED Anode voltage of less than 5 V is recommended. Under extreme EMI conditions as placing a RF transmitter antenna on top of the transceiver, it is recommended to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. Basic RF design rules for circuit design should be followed. Especially longer signal lines should not be used without proper termination. For reference see "The Art of Electronics" by Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Document Number 82612 Rev. 1.5, 03-Jul-06 Rled (:) Rled (:) VLED (V) Standard Power Mode (Intensity > 40 mW/sr, 0° - 15°) Low Power Mode (Intensity > 3.6 mW/sr, 0° - 15°) 2.7 3 50 3.3 6 > 50 5.0 18 > 60 I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Table 2. Recommended Application Circuit Components Component Recommended Value C1, C3 4.7 μF, 16 V Vishay Part Number 293D 475X9 016B C2, C4 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 47 :, 0.125 W CRCW-1206-47R0-F-RT1 Rled See Table 1 www.vishay.com 147 TFBS4710 Vishay Semiconductors Table 3. Truth table Inputs SD TXD Outputs Optical input Irradiance Remark RXD Transmitt er Operation Shutdown mW/m2 high > 1 ms x x weakly pulled (500 :) to VCC1 0 low high x high inactive Ie Transmitting high > μs low x high inactive 0 Protection is active <4 high inactive 0 low > Min. Detection Threshold Irradiance < Max. Detection Threshold Irradiance low (active) 0 low > Max. Detection Threshold Irradiance undefined 0 Ignoring low signals below the IrDA defined threshold for noise immunity Response to an IrDA compliant optical input signal Overload conditions can cause unexpected outputs Package Dimensions 18086 Drawing-No.: 6.550-5256.01-4 Issue: 1; 24.06.03 Figure 4. Package drawing TFBS4710 www.vishay.com 148 Document Number 82612 Rev. 1.5, 03-Jul-06 TFBS4710 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 Document Number 82612 Rev. 1.5, 03-Jul-06 W3 max. www.vishay.com 149 TFBS4710 Vishay Semiconductors Tape Dimensions 19611 Drawing-No.: 9.700-5299.01-4 Issue: 1; 18.08.05 Figure 5. Tape drawing for TFBS4710 for side view mounting www.vishay.com 150 Document Number 82612 Rev. 1.5, 03-Jul-06 TFBS4711 Vishay Semiconductors Serial Infrared Transceiver SIR, 115.2 kbit/s, 2.7 V to 5.5 V Operation Description The TFBS4711 is a low profile, Infrared Data Transceiver module. It supports IrDA data rates up to 115.2 kbit/s (SIR). The transceiver module consists of a PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total frontend solution in a single package. The device is designed for the low power IrDA standard with an extended range on-axis up to 1 m. The RXD pulse width is independent of the duration of TXD pulse and always stays at a fixed width thus making the device optimum for all standard SIR Encoder/ Decoder and interfaces. The Shut Down (SD) feature cuts current consumption to typically 10 nA. 20208 Features • Compliant with the latest IrDA physical layer low power specification ( 9.6 kbit/s to 115.2 kbit/s) • Small package: e4 H 1.9 mm x D 3.1 mm x L 6.0 mm • Industries smallest footprint - 6.0 mm length - 1.9 mm height • Typical Link distance on-axis up to 1 m • Battery & power management features: > Idle Current - 75 μA Typical > Shutdown current - 10 nA typical > Operates from 2.4 V - 5.5 V within specification over full temperature range from - 25 °C to + 85 °C • Remote Control - transmit distance up to 8 meters • Tri-State receiver output, floating in shutdown with a weak pull-up • Constant RXD output pulse width (2 μs typical) • Meets IrFM Fast Connection requirements • Split power supply, an independent, unregulated supply for IRED Anode and a well regulated supply for VCC • Directly interfaces with various Super I/O and Controller Devices and Encoder/ Decoder such as TOIM4232 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • • • • • • • Ideal for battery operated devices PDAs Mobile phones Electronic wallet (IrFM) Notebook computers Digital still and video cameras Printers, fax machines, photocopiers, screen projectors • • • • • • • • Data loggers External infrared adapters (Dongles) Diagnostics systems Medical and industrial data collection devices Kiosks, POS, Point and Pay devices GPS Access control Field programming devices Parts Table Part Description Qty / Reel TFBS4711-TR1 Oriented in carrier tape for side view surface mounting 1000 pcs TFBS4711-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs Document Number 82633 Rev. 1.8, 26-Sep-06 www.vishay.com 151 TFBS4711 Vishay Semiconductors Functional Block Diagram V CC Amp Comp RXD Driver IRED A Power SD Driver Control TXD 18280 GND Pinout Definitions: TFBS4711 weight 50 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy PIN 1 1.2, adding the SIR Low Power Standard. 19428 Pin Description Pin Number Function Description 1 IRED Anode IRED Anode is directly connected to a power supply. The LED current can be decreased by adding a resistor in series between the power supply and IRED Anode. A separate unregulated power supply can be used at this pin. I/O Active 2 TXD This Input is used to turn on IRED transmitter when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 Ps I HIGH 3 RXD Received Data Output, normally stays high but goes low for a fixed duration during received pulses. It is capable of driving a standard CMOS or TTL load. O LOW 4 5 6 SD VCC Shutdown. Setting this pin active switches the device into shutdown mode Supply Voltage Ground I HIGH GND Absolute Maximum Ratings Reference Point Ground, Pin 6 unless otherwise noted. Parameter Test Conditions Supply voltage range, all states Input current For all Pins except IRED Anode Pin Symbol Min VCC - 0.5 ICC Output sink current, RXD Average output current, pin 1 20 % duty cycle Repetitive pulsed output current < 90 μs, ton < 20 % IRED anode voltage, pin 1 Voltage at all inputs and outputs Vin > VCC is allowed Ambient temperature range (operating) Storage temperature range Soldering temperature www.vishay.com 152 See Recommended Solder Profile Typ. Max Unit + 6.0 V 10.0 mA 25.0 mA IIRED (DC) 80 mA IIRED (RP) 400 mA V VIREDA - 0.5 + 6.0 VIN - 0.5 + 6.0 V Tamb - 30 + 85 °C Tstg - 40 + 100 °C 260 °C Document Number 82633 Rev. 1.8, 26-Sep-06 TFBS4711 Vishay Semiconductors Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy Test Conditions d 1.3 1.5 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie Max Unit mm mW/sr *) (500)**) Electrical Characteristics Transceiver Tamb = 25 °C, VCC = VIREDA = 2.4 V to 5.5 V unless otherwise noted. Parameter Test Conditions Supply voltage range, all states Idle supply current at V CC1 (receive mode, no signal) Symbol Min VCC 2.4 Typ. SD = Low, Ee = 1 klx , Tamb = - 25 °C to + 85 °C, VCC = 2.7 V to 5.5 V ICC1 SD = Low, Ee = 1 klx*), Tamb = 25 °C, VCC = 2.7 V to 5.5 V ICC1 Receive current VCC = 2.7 V ICC 80 Shutdown current SD = High, T = 25 °C, Ee = 0 klx ISD < 0.1 SD = High, T = 85 °C ISD *) Operating temperature range Max Unit 5.5 V 130 μA 75 μA μA 2 μA 3 μA TA - 25 + 85 °C Output voltage low, RXD IOL = 1 mA VOL - 0.5 0.15 x VCC V Output voltage high, RXD IOH = - 500 μA VOH 0.8 x VCC VCC + 0.5 V IOH = - 250 μA VOH 0.9 x VCC VCC + 0.5 V RRXD 400 600 k: RXD to VCC impedance Input voltage low: TXD, SD 500 VIL - 0.5 0.5 V VIH VCC - 0.5 6.0 V Input leakage current (TXD, SD) Vin = 0.9 x VCC IICH -2 Controlled pull down current SD, TXD = "0" or "1", 0 < Vin < 0.15 VCC IIRTx SD, TXD = "0" or "1" Vin > 0.7 VCC IIRTx Input voltage high: TXD, SD Input capacitance Document Number 82633 Rev. 1.8, 26-Sep-06 CMOS level (0.5 x VCC typ, threshold level) CIN -1 0 +2 μA + 150 μA 1 μA 5 pF www.vishay.com 153 TFBS4711 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted Parameter Test Conditions Symbol Minimum irradiance Ee in angular range **) 9.6 kbit/s to 115.2 kbit/s O = 850 nm - 900 nm, D = 0 °, 15 ° Ee Maximum irradiance Ee in angular range***) O = 850 nm - 900 nm Ee Maximum no detection irradiance Ee Min Typ. Max Unit 35 (3.5) 80 (8) mW/m2 5 (500) (μW/cm2) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr(RXD) 10 100 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf(RXD) 10 100 ns RXD pulse width Input pulse width > 1.2 μs tPW 1.7 Leading edge jitter Standby /Shutdown delay, receiver startup time 3.0 μs Input Irradiance = 100 mW/m2, d 115.2 kbit/s 250 ns After shutdown active or power-on 150 μs 150 μs Latency 2.0 tL **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance E In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the e maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER). For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). Transmitter Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted. Symbol Min Typ. Max IRED operating current Parameter Tamb = - 25 °C to + 85 °C Test Conditions ID 200 300 400 Transceiver operating peak supply current During pulsed IRED operation @ ID = 300 mA ICC 0.57 Unit mA mA IRED leakage current TXD = 0 V, 0 < VCC < 5.5 V IIRED -1 1 μA Output radiant intensity D = 0 °, TXD = High, SD = Low, R = 0 :, VLED = 2.4 V Ie 45 60 300 mW/sr D = 0 °, 15 °, TXD = High, SD = Low, R = 0 :, VLED = 2.4 V Ie 25 35 300 mW/sr VCC = 5.0 V, D = 0 °, 15 °, TXD = High or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr D Output radiant intensity, angle of ± 22 ° Peak-emission wavelength Op Spectral bandwidth 'O Optical rise time tropt 10 100 Optical fall time tfopt 10 100 ns topt 1.41 2.23 μs Input pulse width tTXD < 20 μs topt tTXD Input pulse width tTXD t 20 μs topt Optical output pulse duration Optical overshoot www.vishay.com 154 Input pulse width 1.63 μs, 115.2 kbit/s 880 900 45 1.63 nm nm ns tTXD + μs 300 μs 25 % Document Number 82633 Rev. 1.8, 26-Sep-06 TFBS4711 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 1. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS4711 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 2 is VISHAY's recommended profiles for use with the TFBS4711 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 2. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Document Number 82633 Rev. 1.8, 26-Sep-06 www.vishay.com 155 TFBS4711 Vishay Semiconductors Recommended Circuit Diagram V CC IR Controller Vdd TFBS4711 Rled IREDA (1) TXD IRTX IRRX IRMODE R1= 47: (2) RXD (3) SD (4) Vcc (5) GND (6) GND C4 C2 C3 C1 4.7 PF 0.1PF 4.7 PF 0.1 PF 18510 Figure 3. Recommended Application Circuit Operated at a clean low impedance power supply the TFBS4711 needs no additional external components when the internal current control is used. For reducing the IRED drive current for low power applications with reduced range an additional resistor can be used to connect the IRED to the separate power supply. Depending on the entire system design and board layout, additional components may be required. (see figure 3). Worst-case conditions are test set-ups with long cables to power supplies. In such a case capacitors are necessary to compensate the effect of the cable inductance. In case of small applications as e.g. mobile phones where the power supply is close to the transceiver big capacitors are normally not necessary. The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a small ceramic version or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is optional for reducing the IRED drive current. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage when noisy supply voltage is used or pick-up via the wiring is expected. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCCX and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. In any case, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not to follow the fast current rise time. In that case another 10 μF capacitor at VCC2 will be helpful. The recommended components in table 1 are for test set-ups Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957 I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Table 1. Recommended Application Circuit Components Component Recommended Value C1, C3 4.7 μF, 16 V 293D 475X9 016B C2, C4 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 47 :, 0.125 W CRCW-1206-47R0-F-RT1 www.vishay.com 156 Vishay Part Number Document Number 82633 Rev. 1.8, 26-Sep-06 TFBS4711 Vishay Semiconductors Table 2. Truth table SD TXD Optical input Irradiance RXD Transmitter Operation mW/m2 Inputs Inputs Inputs Outputs Outputs Remark high x x weakly pulled (500 :) to VCC1 0 Shutdown low high x high inactive Ie Transmitting low high > 300 μs x high inactive 0 Protection is active low low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low low > Min. Detection Threshold Irradiance < Max. Detection Threshold Irradiance low (active) 0 Response to an IrDA compliant optical input signal low low > Max. Detection Threshold Irradiance undefined 0 Overload conditions can cause unexpected outputs Package Dimensions in mm 19612 Figure 4. Package drawing of TFBS4711, tolerance of height is + 0.1mm, - 0.2 mm, other tolerances ± 0.2 mm Document Number 82633 Rev. 1.8, 26-Sep-06 www.vishay.com 157 TFBS4711 Vishay Semiconductors 19728 Figure 5. Recommended Solder Footprint Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 158 W3 max. Document Number 82633 Rev. 1.8, 26-Sep-06 TFBS4711 Vishay Semiconductors Tape Dimensions in mm 19613 Document Number 82633 Rev. 1.8, 26-Sep-06 www.vishay.com 159 TFDU4100 Vishay Semiconductors Not for new design* Serial Infrared Transceiver SIR, 115.2 kbit/s, 2.7 V to 5.5 V Operation Description The TFDU4100 is an infrared transceiver module compliant with the IrDA standard for serial infrared (SIR) data communication, supporting IrDA speeds up to 115.2 kbit/s. The transceiver module consists of a PIN photodiode, an infrared emitter (IRED), and a low-power analog control IC to provide a total frontend solution in a single package. This SIR transceiver is using the small BabyFace package. The transceivers are capable of directly interfacing with a wide variety of I/O chips which perform the pulse-width modulation/demodulation function, including Vishay Semiconductors’ TOIM4232. At a minimum, a cur- 20110 rent-limiting resistor in series with the infrared emitter and a VCC bypass capacitor are the only external components required to implement a complete solution. Features • Compliant to the IrDA physical layer specification (Up to 115.2 kbit/s), HP-SIR® and TV Remote Control e3 • 2.7 V to 5.5 V wide operating voltage range • Low Power Consumption (1.3 mA Supply Current) • Surface mount package - universal (L 9.7 mm × W 4.7 mm × H 4.0 mm) • Open collector receiver output, with 20 k: internal pull-up. • BabyFace (Universal) package capable of surface mount solderability to side and to view orientation • Directly interfaces with various Super I/O and controller devices and Vishay Semiconductors’s TOIM4232 I/O • Built-in EMI protection - no external shielding necessary • Few external components required • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US - Patent No. 6,157,476 • Compliant with IrDA background light specification • EMI Immunity in GSM Bands > 300 V/m verified • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Printers, fax machines, photocopiers, screen projectors • Telecommunication products (cellular phones, pagers) • Internet TV boxes, video conferencing systems • Medical and industrial data collection devices • • • • External infrared adapters (dongles) Data loggers GPS Kiosks, POS, Point and Pay devices including IrFM - applications Parts Table Part Description Qty / Reel TFDU4100-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU4100-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs * TFDU4100 will be replaced by TFDU4101, January 2007 www.vishay.com 160 Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4100 Vishay Semiconductors Functional Block Diagram VCC1 VCC2 Driver RXD Comparator Amplifier IRED Anode AGC Logic SC R1 IRED Cathode TXD Open Collector Driver 14876 GND Pin Description Pin Number Function Description 1 IRED Anode IRED anode, should be externally connected to VCC2 through a current control resistor 2 IRED Cathode IRED cathode, internally connected to driver transistor I/O Active 3 TXD Transmit Data Input I HIGH 4 RXD Received Data Output, open collector. No external pull-up or pull-down resistor is required (20 k: resistor internal to device). Output data is invalid during transmission. O LOW 5 NC No internal connection 6 VCC1 Supply Voltage 7 SC Sensitivity control I HIGH 8 GND Ground Pinout Definitions: TFDU4100 weight 200 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared "U" Option BabyFace (Universal) standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s IRED Detector FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the 1 17087 2 3 4 5 6 7 8 Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. Document Number 82514 Rev. 1.6, 03-Jul-06 www.vishay.com 161 TFDU4100 Vishay Semiconductors Absolute Maximum Ratings Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Supply voltage range Input current Symbol Min Max Unit 0 V d VCC2 d 6 V Test Conditions VCC1 - 0.5 Typ. +6 V 0 V d VCC1 d 6 V VCC2 - 0.5 +6 V 10 mA for all pins, except IRED anode pin Output sink current Power dissipation see derating curve Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature mA mW 125 °C - 25 + 85 °C Tstg - 25 + 85 °C IIRED(DC) t < 90 μs, ton < 20 % 25 200 Tamb see recommended solder profile Average IRED current Repetitive pulsed IRED current PD IIRED(RP) 260 °C 100 mA 500 mA VIREDA - 0.5 +6 V Transmitter data input voltage VTXD - 0.5 VCC1 + 0.5 V Receiver data output voltage V RXD - 0.5 VCC1 + 0.5 V Max Unit IRED anode voltage Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy d 2.5 2.8 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie *) Test Conditions mm mW/sr (500)*) **) The device is a "class 1" device. **) IrDA specifies the max. intensity with 500 mW/sr. Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supported data rates base band Supply voltage receive mode transmit mode, R2 = 47 : (see recommended application circuit) Supply current pin VCC1 (receive mode) Symbol Min Max Unit 2.4 Typ. 115.2 kbit/s VCC1 2.7 5.5 V VCC2 2.0 5.5 V VCC1 = 5.5 V ICC1(Rx) 1.3 2.5 mA VCC1 = 2.7 V ICC1(Rx) 1.0 1.5 mA Supply current pin VCC1 (avg) IIRED = 210 mA (at IRED anode (transmit mode), 20 % duty cycle pin), VCC1 = 5.5 V ICC1(Tx) 5.0 5.5 mA IIRED = 210 mA (at IRED anode pin), VCC1 = 2.7 V ICC1(Tx) 3.5 4.5 mA VCC1 = OFF, TXD = LOW, VCC2 = 6 V, T = - 25 to + 85 °C IL(IREDA) 0.005 0.5 μA 50 μs Leakage current of IR emitter, IRED anode pin Transceiver power on settling time www.vishay.com 162 TPON Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4100 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Minimum detection threshold irradiance Test Conditions Symbol Min Typ. Max Unit BER < 10- 8 (IrDA specification) D = ± 15°, SC = LOW, SIR Ee 20 35 mW/m2 D = ± 15°, SC = HIGH, SIR Ee 6 10 15 mW/m2 Maximum detection threshold irradiance D = ± 90°, VCC1 = 5.0 V Ee 3.3 5 D = ± 90°, VCC1 = 3.0 V Ee 8 15 Logic LOW receiver input irradiance Note: No detection below this input irradiance Ee 4 Output voltage - RXD Active, C = 15 pF, R = 2.2 k: VOL non-active, C = 15 pF, R = 2.2 k: VOH kW/m2 kW/m2 mW/m2 0.5 0.8 V VCC1 - 0.5 Output current - RXD VOL < 0.8 V Rise time - RXD active to inactive C = 15 pF, R = 2.2 k: to VCC1 tr(RXD) 20 200 ns active to inactive C = 15 pF, internal load only tr(RXD) 20 1400 ns inactive to active C = 15 pF, R = 2.2 k: to VCC1 tf(RXD) 20 200 ns inactive to active C = 15 pF, internal load only tf(RXD) 20 200 ns tPW 1.63 4.3 μs 2 μs 500 μs Fall time - RXD Pulse width - RXD output Jitter, leading edge of output signal over a period of 10 bit, 115.2 kbit/s Latency IOL V 4 4 ti 100 tL mA Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current Test Conditions IRED operating current can be adjusted by variation of R1. Current limiting resistor is in series to IRED: R1 = 14 :, VCC2 = 5.0 V Symbol Min Id Typ. Max Unit 0.2 0.28 A Logic LOW transmitter input voltage VIL(TXD) 0 0.8 V Logic HIGH transmitter input voltage VIH(TXD) 2.4 VCC1 + 0.5 V In agreement with IEC825 eye safety limit, if current limiting resistor is in series to IRED: R1 = 14 :, VCC2 = 5.0 V, D = ±15 ° Ie 45 200 mW/sr TXD logic LOW level Ie 0.04 mW/sr 900 nm Output radiant intensity Angle of half intensity D Peak wavelength of emission Op Document Number 82514 Rev. 1.6, 03-Jul-06 140 ± 24 880 ° www.vishay.com 163 TFDU4100 Vishay Semiconductors Parameter Test Conditions Symbol Min Half-width of emission spectrum Typ. Max Optical rise time, fall time tropt, tfopt nm 200 600 Optical overshoot Rising edge peak-to-peak jitter of optical output pulse Unit 45 Over a period of 10 bits, independent of information content tj ns 25 % 0.2 μs Recommended Circuit Diagram power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. 500 Vcc = 5.25 V, max. efficiency, center, min. VF, min. VCEsat 450 400 350 Intensity (mW/sr) The only required components for designing an IrDA® compatible application using Vishay Semiconductors SIR transceivers are a current limiting resistor to the IRED. However, depending on the entire system design and board layout, additional components may be required (see figure 1). It is recommended that the capacitors C1 and C2 are positioned as near as possible to the transceiver power supply pins. A tantalum capacitor should be used for C1, while a ceramic capacitor should be used for C2 to suppress RF noise. Also, when connecting the described circuit to the power supply, low impedance wiring should be used. 300 250 200 Vcc = 4.75 V, min. efficiency, ±15q off axis, max. VF, max. VCEsat 150 100 50 0 VCC2 6 R1 VCC1 14377 IRED Cathode R2 RXD 8 10 12 14 Current Control Resistor ( : ) 16 IRED Anode RXD Figure 2. Ie vs. R1 TXD TFDx4x00 C1 GND C2 VCC1/SD SC GND NC 18092 Note: outlined components are optional depending on the quality of the power supply Figure 1. Recommended Application Circuit R1 is used for controlling the current through the IR emitter. For increasing the output power of the IRED, the value of the resistor should be reduced. Similarly, to reduce the output power of the IRED, the value of the resistor should be increased. For typical values of R1 (see figures 2 and 3), e.g. for IrDA compliant operation (VCC2 = 5 V ± 5 %), a current control resistor of 14 : is recommended. The upper drive current limitation is dependent on the duty cycle and is given by the absolute maximum ratings on the data sheet and the eye safety limitations given by IEC825.1. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCC1 and injected noise. An unstable www.vishay.com 164 Intensity (mW/sr) SC TXD 14378 760 720 VCC = 3.3 V, max. intensity on 680 axis, min. VF , min VCEsat 640 600 560 520 480 440 400 360 320 280 240 VCC = 2.7 V, min. intensity 200 ± 15q off axis, max. VF , 160 max. VCEsat 120 80 40 0 0 1 2 3 4 5 6 7 8 Current Control Resistor ( : ) Figure 3. Ie vs. R1 Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4100 Vishay Semiconductors Table 1. Recommended Application Circuit Components Component Recommended Value Vishay Part Number C1 4.7 μF, Tantalum 293D 475X9 016B 2T C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 14 :, 0.25 W (recommended using two 7 :M, 0.125 W resistor in series, (VCC2 = 5 V) CRCW-1206-7R00-F-RT1 R2 47 :, 0.125 W CRCW-1206-47R0-F-RT1 The sensitivity control (SC) pin allows the minimum detection irradiance threshold of the transceiver to be lowered when set to a logic HIGH. Lowering the irradiance threshold increases the sensitivity to infrared signals and increases transmission range up to 3 meters. However, setting the Pin SC to logic HIGH also makes the transceiver more susceptible to transmission errors due to an increased sensitivity to fluorescent light disturbances. It is recommended to set the Pin SC to logic LOW or left open if the increased range is not required or if the system will be operating in bright ambient light. cally 5 nA). The settling time after switching VCC1/SD on again is approximately 50 Ps. Vishay Semiconductors’ TOIM4232 interface circuit is designed for this shutdown feature. The VCC_SD, S0 or S1 outputs on the TOIM4232 can be used to power the transceiver with the necessary supply current. If the microcontroller or the microprocessor is unable to drive the supply current required by the transceiver, a low-cost SOT23 pnp transistor can be used to switch voltage on and off from the regulated power supply (see figure 5). The additional component cost is minimal and saves the system designer additional power supply costs. Shutdown The internal switch for the IRED in Vishay Semiconductors SIR transceivers is designed to be operated like an open collector driver. Thus, the VCC2 source can be an unregulated power supply while only a well regulated power source with a supply current of 1.3 mA connected to VCC1/SD is needed to provide power to the remainder of the transceiver circuitry in receive mode. The term VCC1/SD is used here for the power supply pin to indicate that VCC1 can be switched off independently to shut down the transceiver. It is allowed to keep the power supply connected to the IRED Anode. In transmit mode, the current at VCC1 is slightly higher (approximately 4 mA average at 3 V supply current) and the voltage is not required to be kept as stable as in receive mode. A voltage drop of VCC1 is acceptable down to about 2.0 V when buffering the voltage directly from the Pin VCC1 to GND see figure 1). This configuration minimizes the influence of high current surges from the IRED on the internal analog control circuitry of the transceiver and the application circuit. Also board space and cost savings can be achieved by eliminating the additional linear regulator normally needed for the IRED’s high current requirements. The transceiver can be very efficiently shutdown by keeping the IRED connected to the power supply VCC2 but switching off VCC1/SD. The power source to VCC1/SD can be provided directly from a microcontroller (see figure 4). In shutdown, current loss is realized only as leakage current through the current limiting resistor to the IRED (typiDocument Number 82514 Rev. 1.6, 03-Jul-06 IIRED Power Supply + – Regulated Power Supply 50 mA R1 IRED Anode Microcontroller or Microprocessor 20 mA IS VCC1/SD TFDU4100 (Note: Typical Values Listed) Receive Mode at 5 V: IIRED = 210 mA, IS = 1.3 mA at 2.7 V: IIRED = 210 mA, IS = 1.0 mA Transmit Mode at 5 V: IIRED = 210 mA, IS = 5 mA (Avg.) at 2.7 V: IIRED = 210 mA, IS = 3.5 mA (Avg.) 14878 Figure 4. IIRED Power Supply + – Regulated Power Supply 50 mA R1 IRED Anode Microcontroller or Microprocessor 20 mA IS VCC1/SD TFDU4100 (Note: Typical Values Listed) Receive Mode at 5 V: IIRED = 210 mA, IS = 1.3 mA at 2.7 V: IIRED = 210 mA, IS = 1.0 mA Transmit Mode at 5 V: IIRED = 210 mA, IS = 5 mA (Avg.) at 2.7 V: IIRED = 210 mA, IS = 3.5 mA (Avg.) 14879 Figure 5. www.vishay.com 165 TFDU4100 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 275 2...4 °C/s T ≥ 255 °C for 10 s....30 s 250 225 Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 0 50 19535 100 150 200 250 300 350 Time/s Figure 6. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFDU4100 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 7 and 8 are VISHAY's recommended profiles for use with the TFDU4100 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. Temperature/°C 260 240 220 200 180 160 140 120 100 80 60 40 20 0 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 2 °C...3 °C/s 50 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 7. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 8. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Current Derating Diagram 600 Peak Operating Current (mA) Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 500 400 300 200 Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25 %. 100 0 - 40 - 20 14880 0 20 40 60 80 100 120 140 Temperature (5 °C) Figure 9. Current Derating Diagram www.vishay.com 166 Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4100 Vishay Semiconductors Package Dimensions 7x1=7 0.6 2.5 1 8 1 18470 Figure 10. Package drawing and solder footprint TFDU4100, dimensions in mm, tolerance ± 0.2 mm if not otherwise mentioned Document Number 82514 Rev. 1.6, 03-Jul-06 www.vishay.com 167 TFDU4100 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 www.vishay.com 168 W3 max. Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4100 Vishay Semiconductors Tape Dimensions 19824 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 11. Tape drawing, TFDU4100 for top view mounting, tolerance ± 0.1 mm Document Number 82514 Rev. 1.6, 03-Jul-06 www.vishay.com 169 TFDU4100 Vishay Semiconductors 19875 Drawing-No.: 9.700-5297.01-4 Issue: 1; 08.04.05 Figure 12. Tape drawing, TFDU4100 for side view mounting, tolerance ± 0.1 mm www.vishay.com 170 Document Number 82514 Rev. 1.6, 03-Jul-06 TFDU4101 Vishay Semiconductors Infrared Transceiver Module (SIR, 115.2 kbit/s) for IrDA® Applications Description The TFDU4101 transceiver is an infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 115.2 kbit/s (SIR), and carrier based remote control modes. Integrated within the transceiver module are a photo PIN diode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This device covers the full IrDA range of more than 1 m using the internal intensity control. With one external current control resistor the current can be adjusted for shorter ranges saving operating current operating in IrDA low power mode. This Vishay SIR transceiver is using the lead frame technology. The receiver output pulse duration is independent of 20110 the optical input pulse duration and recovers always a fixed pulse duration optimum for compatibility to standard Endecs and interfaces. TFDU4101 has a tristate output and is floating in shutdown mode with a weak pull-up. Features • Operates from 2.4 V to 3.6 V within specification over full temperature range from - 30 °C to + 85 °C e3 • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US - Patent No. 6,157,476 • Low power consumption (< 0.12 mA supply current in receive mode, no signal) • Power shutdown mode (< 4 μA shutdown current in full temperature range, up to 85 °C, < 10 nA at 25 °C) • Surface mount 4-mm package L 9.7 mm × W 4.7 mm × H 4.0 mm • High efficiency emitter • Low profile (universal) package capable of surface mount soldering to side and top view orientation • Directly Interfaces with various Super I/O and controller devices as e. g. TOIM4232 • Tri-state-Receiver Output, floating in shut down with a weak pull-up • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Printers, fax machines, photocopiers, screen projectors • Internet TV boxes, video conferencing systems • Medical data collection • Diagnostic systems • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • • • • • • Internet TV Boxes, video conferencing systems External infrared adapters (dongles) Data loggers GPS Kiosks, POS, Point and Pay devices Industrial applications Parts Table Part Description Qty / Reel TFDU4101-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU4101-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 171 TFDU4101 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 Logic & SD Controlled Driver Control TXD IRED C GND 18468 Pin Description Pin Number 1 Function Description I/O Active VCC2 IRED anode to be externally connected to VCC2. An external resistor is only IRED Anode necessary for controlling the IRED current when a current reduction below 300 mA is intended to operate in IrDA low power mode. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC1 - supply. 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 50 μs (max 300 μs). I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. During transmission the RXD output is active (echo-on). No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. O LOW I HIGH 5 SD Shutdown 6 VCC1 Supply Voltage 7 NC No internal connection 8 GND Ground I Pinout TFDU4101 weight 200 mg "U" Option BabyFace (Universal) IRED 1 2 3 4 5 6 Detector 7 8 17087 www.vishay.com 172 Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6.0 V Test Conditions VCC1 - 0.5 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6.0 V VCC2 - 0.5 6.0 V Voltage at RXD - 0.5 V < VCC1 < 6.0 V VRXD - 0.5 VCC1 + 0.5 V Vin - 0.5 6.0 V 10 mA Voltage at all inputs and outputs Vin > VCC1 is allowed Input currents Typ. For all Pins, Except IRED Anode Pin Output sinking current Power dissipation See Derating Curve Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature < 90 μs, ton < 20 % 25 mA 250 mW 125 °C Tamb - 30 + 85 °C Tstg - 30 + 85 °C 260 °C IIRED (DC) 80 mA IIRED (RP) 400 mA Max Unit See “Recommended Solder Profile” Average output current, pin 1 Repetitive pulse output current, pin 1 to pin 2 PD Eye safety information Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Virtual source size Parameter Method: EN ISO 11146 d 2.6 Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 operating below the absolute maximum ratings Ie *) Due **) Test Conditions Typ. mm *) (500)**) mW/sr to the internal limitation measures the device is a "class1" device under all conditions IrDA specifies the max. intensity with 500 mW/sr Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy: 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with the physical layer standard IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any case obsoletes the former version. Note: We apologize to use sometimes in our documentation the abbreviation LED and the word Light Emitting Diode instead of Infrared Emitting Diode (IRED) for IR-emitters. That is by definition wrong; we are here following just a bad trend. Typical values are for design aid only, not guaranteed nor subject to production testing and may vary with time. Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 173 TFDU4101 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions/Pins Supply voltage Symbol Min VCC1 2.4 Typ. Max Unit 5.5 V 130 μA Dynamic supply current SD = Low, Ee = 1 klx*), Tamb = - 25 °C to + 85 °C VCC1 = VCC2 = 2.4 V to 5.5 V ICC1 90 Dynamic supply current SD = Low, Ee = 1 klx*), Tamb = 25 °C VCC1 = VCC2 = 2.4 V to 5.5 V ICC1 75 Average dynamic supply current, transmitting IIRED = 300 mA, 25 % Duty Cycle ICC 0.65 mA Shutdown supply current SD = High, T = 25 °C, Ee = 0 klx No signal, no resistive load ISD 0.1 μA SD = High, T = 70 °C No signal, no resistive load ISD 3 μA SD = High, T = 85 °C No signal, no resistive load ISD 4 μA TA - 30 + 85 °C Output voltage Low, RXD Cload = 15 pF VOL - 0.5 0.15 x VCC1 V Output voltage High, RXD IOH = - 500 μA, CLoad = 15 pF VOH 0.8 x VCC1 VCC1 + 0.5 V IOH = - 250 μA, CLoad = 15 pF VOH 0.9 x VCC1 VCC1 + 0.5 V RRXD 400 600 k: Operating temperature range RXD to VCC1 impedance Input voltage low (TXD, SD) Input voltage High (TXD, SD) 1.5 V d Vlogic d 2.5 V**) 500 μA VIL - 0.5 0.5 V VIH 0.8 x VCC1 6 V VIH VCC1 - 0.5 6 V Input leakage current (TXD, SD) Vin = 0.9 x VCC1 IICH -2 +2 μA Controlled pull down current 0 < Vin < 0.15 VCC1 Vin > 0.7 VCC1 IIrTX + 150 1 μA μA 5 pF Vlogic > 2.5 V** Input capacitance (TXD, SD) *) ) SD, TXD = "0" or "1" -1 CI 0 Standard Illuminant A **) The typical threshold level is 0.5 x VCC1. It is recommended to use the specified min/max values to avoid increased operating current. www.vishay.com 174 Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Minimum irradiance Ee in angular range**) SIR mode 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm; D = 0°, 15° Minimum irradiance Ee in angular range O = 850 nm to 900 nm Symbol Min Typ. Max Unit Ee 4 (0.4) 20 (2) 35*) (3.5) mW/m2 (μW/cm2) Ee 5 (500) kW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 20 100 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 20 100 ns RXD pulse width input pulse length > 1.2 μs t PW 1.65 3.0 μs Leading edge jitter Input Irradiance = 100 mW/m2, d 115.2 kbit/s 250 ns Standby /Shutdown delay, receiver startup time After shutdown active or power-on 500 μs 150 μs Latency *) tL 2.2 100 IrDA specification is 40 mW/m2. Specification takes a window loss of 10 % into account. **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical power delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 175 TFDU4101 Vishay Semiconductors Optoelectronic Characteristics, continued Transmitter Tamb = 25 °C, VCC1 =VCC2 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions No external resistor for current Symbol Min Typ. Max Unit ID 250 300 350 mA 1.8 1.9 V 1 μA limitation*) Forward voltage of built-in IRED If = 300 mA Output leakage IRED current Vf 1.4 IIRED -1 48 Output radiant intensity D = 0°, 15° TXD = High, SD = Low Ie Output radiant intensity VCC1 = 5.0 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie Peak - emission wavelength**) Op Spectral bandwidth 'O Optical rise time, Optical fall time ± 24 880 mW/sr deg 900 45 nm nm tropt, tfopt 10 300 ns tTXD - 0.15 tTXD + 0.15 μs 300 μs 25 % Optical output pulse duration input pulse width 1.6 μs < tTXD < 20 μs topt Optical output pulse duration input pulse width tTXD t 20 μs topt Optical overshoot mW/sr 0.04 D Output radiant intensity, angle of half intensity 65 20 *) Using an external current limiting resistor is allowed and recommended to reduce IRED intensity and operating current when current reduction is intended to operate at the IrDA low power conditions. E.g. for VCC2 = 3.3 V a current limiting resistor of Rs = 56 : will allow a power minimized operation at IrDA low power conditions. **) Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e. g. Philips RC5/RC6® or RECS 80. www.vishay.com 176 Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors Recommended Circuit Diagram Operated with a clean low impedance power supply the TFDU4101 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 1). That is especially the case when separate power supplies are used for bench tests. When using compact wiring and regulated supplies as e. g. in phone applications in most cases no external components are necessary. VIRED R1 *) VCC R2 C1 GND VCC2 , IRED A VCC1 C2 Ground SD SD TXD TXD RXD RXD IRED C 20037 Figure 1. Recommended test circuit. *) R1 is optional when reduced intensity is used. The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor, which may be used to reduce the operating current to levels below the specified controlled values for saving battery power. VISHAY's transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The shutdown input must be grounded for normal operation, also when the shutdown function is not used. The inputs (TXD, SD) and the output RXD should be directly connected (DC - coupled) to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCC1 and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. When extended wiring is used (bench tests!) the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. The transceiver itself withstands EMI at GSM frequencies above 500 V/m. When interference is observed, the wiring to the inputs picks it up. It is verified by DPI measurements that as long as the interfering RF - voltage is below the logic threshold levels of the inputs and equivalent levels at the outputs no interferences are expected. One should keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Tests and Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 depends on current to be adjusted, e. g. with VCC2 = 3.3 V 56 : is an option for minimum low power operation R2 Document Number 81288 Rev. 1.0, 26-Sep-06 Vishay Part Number 47 :, 0.125 W CRCW-1206-47R0-F-RT1 www.vishay.com 177 TFDU4101 Vishay Semiconductors Figure 2 shows an example of a typical application with a separate supply voltage VS and using the transceiver with the IRED Anode connected to the unregulated battery Vbatt. This method reduces the peak load of the regulated power supply and saves therefore costs. Alternatively all supplies can also be tied to only one voltage source. R1 and C1 are not used in this case and are depending on the circuit design in most cases not necessary. In figure 2 an option is shown to operate the transmitter at two different power levels to switch for long range to low power mode for e.g. saving power for IrDA application but use the full range specification for Remote Control. The additional components are marked in the figure. For operating at RS232 ports TOIM4232 is recommended as ENDEC. I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Current Derating Diagram Figure 3 shows the maximum operating temperature when the device is operated without external current limiting resistor. Vbatt | 3 V Hi/Low C1 R1 Vs = 2.8 V Vdd IRED Anode (1) IRED Cathode (2) TXD (3) RXD (4) SD (5) Vcc1 (6) IRTX IRRX IR MODE R2 C2 GND (8) 20038 Ambient Temperature (°C) 90 85 80 75 70 65 60 55 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % 18097 Figure 3. Current Derating Diagram Figure 2. Typical application circuit. Grey: Optional for Hi/Low switching. Table 2. Truth table Inputs Remark TXD Optical input Irradiance mW/m2 RXD Transmitter high > 1 ms x x weakly pulled (500 k:) to VCC1 0 Shutdown low high < 50 μs x low active Ie Transmitting high > 50 μs x high inactive 0 Protection is active low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low > Min. irradiance Ee < Max. irradiance Ee low (active) 0 Response to an IrDA compliant optical input signal low > Max. irradiance Ee undefined 0 Overload conditions can cause unexpected outputs www.vishay.com 178 Outputs SD Operation Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 100 19535 150 200 250 300 350 Figure 4. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 5. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU4101 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 and 6 are VISHAY's recommended profiles for use with the TFDU4101 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 6. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 179 TFDU4101 Vishay Semiconductors Package Dimensions in mm 7x1=7 0.6 2.5 1 8 1 18470 Figure 7. Package drawing TFDU6103, dimensions in mm, tolerance ± 0.2 mm if not otherwise mentioned www.vishay.com 180 Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors 20035 Figure 8. Recommended footprint for side view applications and solderpaste mask 20036 Figure 9. Recommended footprint for top view applications and solderpaste mask Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 181 TFDU4101 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 www.vishay.com 182 W3 max. Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4101 Vishay Semiconductors Tape Dimensions 19824 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 10. Tape drawing, TFDU6103 for top view mounting, tolerance ± 0.1 mm Document Number 81288 Rev. 1.0, 26-Sep-06 www.vishay.com 183 TFDU4101 Vishay Semiconductors Tape Dimensions 19875 Drawing-No.: 9.700-5297.01-4 Issue: 1; 04.08.05 Figure 11. Tape drawing, TFDU6103 for side view mounting, tolerance ± 0.1 mm www.vishay.com 184 Document Number 81288 Rev. 1.0, 26-Sep-06 TFDU4202 Vishay Semiconductors Integrated Low Profile Transceiver Module for Telecom Applications - IrDA Standard Description The miniaturized TFDU4202 is an ideal transceiver for applications in telecommunications like mobile phones and pagers. The device is mechanically designed for lowest profile with a height of only 2.8 mm. The infrared transceiver is compatible to the latest IrDA® IrPHY specification up to a data rate of 115 kbit/s. At lower operating voltages up to 3.3 V the transceiver can be operated without external current limiting resistor to achieve a range > 1 m. The added feature is a split power supply for IRED driver and ASIC. 18170 Features • Package dimension: L 7.1 mm x W 4.7 mm x H 2.8 mm • Compatible to latest IrDA IrPHY standard e3 • CIR Remote Control operation: Typical transmission range 8 m using standard RC-receivers. Receives RC-commands with typical specified sensitivity. • SMD Side View • Lowest power consumption 65 μA, receive mode, 0.01 μA Shutdown • Built-in current limitation • Output intensity adjustable by external resistor • Wide supply voltage range (2.4 V to 5.5 V) • Split power supply • Operational down to 2.0 V • Fewest external components • Eye safety: Double safety Measures: Limited optical output pulse duration Limited optical output intensity IEC60825-1, 2001: Class 1 • Push-pull output (RXD) • High EMI immunity • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • • • • Mobile Phones Pagers Personal Digital Assistants (PDA) Handheld Battery Operated Equipment Parts Table Part Description Qty / Reel TFDU4202-TR1 Orientated in carrier tape for side view in mounting 750 pcs TFDU4202-TR3 Orientated in carrier tape for side view in mounting 2250 pcs Document Number 82541 Rev. 2.0, 06-Oct-06 www.vishay.com 185 TFDU4202 Vishay Semiconductors Functional Block Diagram Tri-State-Driver RXD Comparator Amplifier Control Logic Vccp TXD Control Controlled Driver 18190 VCC GND Pin Description Pin Number Function Description 1 2 3 4 5 6 7 8 IRED GND IRED GND RXD VCCP GND GND TXD VCC IRED cathode, ground IRED cathode, ground Output, received data, push-pull output IRED supply voltage Ground Ground Input, transmit data Power supply voltage I/O Active O low I I high high Pinout TFDU4202 weight 100 mg 18228 Absolute Maximum Ratings Reference Point Pin 8, unless otherwise noted. Parameter Test Conditions Supply voltage range Input current Output sink current Power dissipation Junction temperature Ambient temperature range (operating) Storage temperature range Soldering temperature 2.4 V dVCC d 6 V all pins Min VCC Vccp - 0.5 - 0.5 Max Unit 6 6 10 25 200 125 85 V V mA mA mW °C °C Ptot TJ Tamb - 25 Tstg - 40 100 260 °C °C IIRED(DC) 125 mA IIRED(RP) 500 mA see the chapter “Soldering conditions” for lead-bearing and Pb-free processing Average IRED current Repetitive pulsed IRED current Symbol < 90μs, ton < 20 % Typ. Transmitter data input voltage VTXD - 0.5 6 V Receiver data output voltage V RXD - 0.5 6 V www.vishay.com 186 Document Number 82541 Rev. 2.0, 06-Oct-06 TFDU4202 Vishay Semiconductors Eye safety information Parameter Virtual source size Test Conditions Method: (1 - 1/e) encircled energy Symbol Min Typ. d Max 2 Unit mm Compatible to Class 1 operation of IEC 60825 or EN60825 with worst case IrDA SIR pulse pattern, 115.2 kbit/s Electrical Characteristics Transceiver Tested for the following parameters (VCC = 2.4 V to 5.5 V, - 25 °C to + 85 °C, unless otherwise stated). Parameter Supported data rates Test Conditions Symbol base band Min Typ. 9.6 VCC Max Unit 115.2 kbit/s Supply voltage range operational down to 2.0 V 5.5 V Supply current VCC = 2.4 V to 5.5 V, Ee = 0, receive mode, full temperature range IS 65 100 μA VCC = 2.4 V to 5.5 V, 10 klx sunlight, receive mode, full temperature range, no signal IS 70 100 μA VCC = 2.7 V, Vccp = 2.7 V, 115.2 kbit/s transmission, receive mode, nose to nose operation IS 1 Supply current at V ccp shutdown mode, entire temperature range 20 °C ISshdown 0.02 IRED peak current transmitting Ie = 40 mW/sr, no external resistor, Vccp = 2.7 V, SIR standard Transceiver ‘power on‘ settling time time from switching on VCC to established specified operation 2.4 IStr mA 1 μA 360 mA 1 ms Optoelectronic Characteristics Receiver Tested for the following parameters (VCC = 2.4 V to 5.5 V, - 25 °C to + 85 °C, unless otherwise stated). Parameter Test Conditions Symbol Minimum detection threshold irradiance (logic high receiver input irradiance) | D | d ± 15 °, VCC = 2.4 V to 5.5 V 2.0 V, 25 °C tested Ee, min Maximum detection threshold irradiance | D | d ± 90 °, VCC = 5 V Ee, max | D | d ± 90 °, VCC = 3 V Logic low receiver input irradiance Min Ee, min Ee, max Typ. Max Unit 25 (2.5) 50 (5) mW/m2 50 100 3300 (330) 5000 (500) 8000 (800) 15000 (1500) Ee, max,low W/m2 W/m2 (mW/cm2) 4 (0.4) VOL 0 non active, C = 15 pF VOH VCC - 0.5 VOL < 0.5 V Rise time at load C = 15 pF, R = 2.2 k: Document Number 82541 Rev. 2.0, 06-Oct-06 tr mW/m2 (μW/cm2) μW/m2 active, C = 15 pF Output current RXD mW/m2 (mW/cm2) Ee, max,low Output voltage RXD (μW/cm2) 20 0.5 V 4 mA 70 ns V www.vishay.com 187 TFDU4202 Vishay Semiconductors Symbol Min Fall time at load Parameter C = 15 pF, R = 2.2 k: Test Conditions tf 20 Typ. 70 ns RXD signal electrical output pulse width 2.4 kbit/s, input pulse width 1.41 μs to 3/16 of bit duration tp 1.41 20 μs 115.2 kbit/s, input pulse width 1.41 μs to 3/16 of bit duration tp 1.41 4.5 μs Output delay time (RXD), leading edge optical input to electrical output output level = tdl 2 μs Jitter, leading edge of output signal over a period of 10 bit, 115.2 kbit/s tj 400 ns tdt 6.5 μs 0.1 1 ms 100 200 μs 1 Max Unit 0.5 x VCC at 40 mW/m2 Output delay time (RXD), trailing output level = edge optical input to electrical 0.5 x VCC at 40 mW/m2 output Power on time, SD recovery time Latency tL Transmitter Symbol Min Max Unit Logic low transmitter input voltage Parameter Test Conditions VIL(TXD) - 0.5 0.15 x VCC V Logic high transmitter input voltage VIH(TXD) 0.8 x VCC 6 V Ie 45 Op 850 Output radiant intensity IF1 = 320 mA, | D | d ± 15 °, current controlled by external resistor, voltage range 2.7 V to 5.5 V Peak emission wavelength Spectral emission bandwidth Typ. mW/sr 900 Optical rise/fall time 115.2 kHz square wave signal (duty cycle 1 : 1) Optical output pulse duration input pulse duration 1.6 μs 1.5 1.6 input pulse duration > 25 μs, safety protection Output radiant intensity logic low level Overshoot, optical Rising edge peak to peak jitter nm 60 over a period of 10 bits, independent of information content tj nm 200 ns 1.7 μs 25 μs 0.04 μW/sr 25 % 0.2 μs Truth table Inputs TXD Optical input Irradiance mW/m2 RXD low x x low 0 high high x high Ie Transmitter high t 25 μs x high 0 low <4 high 0 low > Min. detection threshold irradiance < Max. detection threshold irradiance x 0 low > Max. detection threshold irradiance undefined 0 www.vishay.com 188 Outputs VCC Document Number 82541 Rev. 2.0, 06-Oct-06 TFDU4202 Vishay Semiconductors Application Hints The TFDU4202 does not need any external component when operated with a "clean" power supply. In a more noisy ambient it is recommended to add a capacitor C1 and a resistor R1 for noise suppression. A combination of a tantalum with a ceramics capacitor will be efficient to attenuate both, RF and LF. The power supply Vccp must be able to source up to 550 mA current with a fast rise time. If that cannot be guaranteed an additional capacitor near pin 4 (Vccp) should be included. The value is depending on the power supply quality. A good choice is between 4.7 μF and 10 μF. Latency The receiver is in specified conditions after the defined latency. In a UART related application after that time after the last transmitted signal (IrDA specifies 500 μs maximum for low power applications and 10 ms maximum for standard) the receiver buffer of the UART must be cleared. Therefore the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state. For more application circuits, see IrDC Design Guide and TOIM4232 data sheet. Recommended Circuit Diagram R1 C1 VCC 8 VCC GND 5, 6 GND RXD 3 RXD TXD 7 TXD 4 VCCP Vccp R2 1, 2 IRED Cathode 18187 Table Recommended Application Circuit Components Component Recommended Value Vishay Part Number C1 4.7 μF, 16 V 293D 475X9 016B 2T R1 5 : ( 2 : to 47 :) This is a recommendation for a combination to start with to exclude power supply effects. Optimum, from a costs point of view, to work without both. Temperature Derating Diagram The temperature derating diagram shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 : is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. Ambient Temperature (˚C) 90 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 1. Temperature Derating Diagram Document Number 82541 Rev. 2.0, 06-Oct-06 www.vishay.com 189 TFDU4202 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 19535 100 150 200 250 300 350 Figure 2. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 3. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU4202 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 3 and 4 are VISHAY's recommended profiles for use with the TFDU4202 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 4. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. www.vishay.com 190 Document Number 82541 Rev. 2.0, 06-Oct-06 TFDU4202 Vishay Semiconductors Package Dimensions 19821 Drawing-No.: 6.550-5185.01-4 Issue: 5; 02.09.05 Figure 5. Package drawing, TFDU4202 Document Number 82541 Rev. 2.0, 06-Oct-06 www.vishay.com 191 TFDU4202 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 mm mm mm mm mm mm mm Tape Width A max. N W1 min. W2 max. W3 min. W3 max. 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 192 Document Number 82541 Rev. 2.0, 06-Oct-06 TFDU4202 Vishay Semiconductors Tape Dimensions 19820 Drawing-No.: 9.700-5227.01-4 Issue: 3; 03.09.99 Figure 6. Tape drawing, TFDU4202 for side view mounting Document Number 82541 Rev. 2.0, 06-Oct-06 www.vishay.com 193 TFDU4203 Vishay Semiconductors Integrated Low Profile Transceiver Module for Telecom Applications - IrDA Standard Description The miniaturized TFDU4203 is an ideal transceiver for applications in telecommunications like mobile phones and pagers. The device is mechanically designed for lowest profile with a height of only 2.8 mm. The infrared transceiver is compatible to the IrDA® IrPHY specification up to a data rate of 115 kbit/s. The transceiver can be operated without external current limiting resistor to achieve full SIR compliance (range > 1 m in full ± 15° cone). 18170 Features • Package dimension: L 7.1 mm x W 4.7 mm x H 2.8 mm • Compatible to the latest IrDA IrPHY e3 standard • CIR Remote Control operation: Typical transmission range 8 m using standard RC-receivers. Receives RC-commands with typical specified sensitivity. • SMD side view • Lowest power consumption 65 μA, Receive Mode, 0.01 μA shutdown current • Built-in current limitation • Output intensity adjustable beyond IrDA Low Power • Supply voltage range 2.4 V to 5.5 V Operational down to 2.0 V • Fewest external components • Eye safety: Double safety Measures: Limited optical output pulse duration, limited optical output intensity IEC60825-1, 2001: Class 1 • Tri - state output (RXD) • High EMI immunity • SD pin • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • • • • Mobile phones Pagers Personal digital assistants (PDA) Hand-held battery operated equipment Parts Table Part Description Qty / Reel TFDU4203-TR1 Orientated in carrier tape for side view in mounting 750 pcs TFDU4203-TR3 Orientated in carrier tape for side view in mounting 2250 pcs www.vishay.com 194 Document Number 82542 Rev. 1.6, 04-Oct-06 TFDU4203 Vishay Semiconductors Functional Block Diagram Vcc Tri-State-Driver RXD Comparator Amplifier Control & Logic TXD Control SD Controlled Driver 19019 GND Pin Description Pin Number Function Description 1 2 IRED GND IRED GND IRED Cathode, Ground IRED Cathode, Ground 3 4 5 6 7 8 RXD VCC GND GND TXD SD Output, received data, tri-state, floating in shutdown mode Supply voltage Ground Ground Input, transmit data Shutdown I/O Active O Low I I High High Pinout TFDU4203 weight 100 mg 18228 Absolute Maximum Ratings Reference Point Pin 8, unless otherwise noted. Parameter Supply voltage range Input current Output sink current Power dissipation Junction temperature Ambient temperature range (operating) Test Conditions Average IRED current Repetitive pulsed IRED current Transmitter data input voltage Receiver data output voltage Document Number 82542 Rev. 1.6, 04-Oct-06 Min VCC - 0.5 Ptot TJ Tamb - 25 Tstg - 40 all pins Storage temperature range Soldering temperature Symbol see the chapter “Soldering conditions” for lead-bearing and Pb-free processing < 90 μs, ton < 20 % IIRED(DC) IIRED(RP) VTXD V RXD - 0.5 - 0.5 Typ. Max Unit +6 10 25 200 125 85 V mA mA mW °C °C 100 °C 260 °C 125 500 6 6 mA mA V V www.vishay.com 195 TFDU4203 Vishay Semiconductors Eye safety information Parameter Virtual source size (TFDU4203 only) Test Conditions Method: (1 - 1/e) encircled energy Symbol Min d Typ. Max 2 Unit mm Compatible to Class 1 operation of IEC 60825 or EN60825 with worst case IrDA SIR pulse pattern, 115.2 kbit/s Electrical Characteristics Transceiver Parameter Supported data rates Test Conditions Symbol base band Min Typ. 9.6 Unit kbit/s Supply voltage range operational down to 2.0 V 5.5 V Supply current VCC = 2.4 V to 5.5 V, Ee = 0, receive mode, full temperature range IS 65 100 μA VCC = 2.4 V to 5.5 V, 10 klx sunlight, receive mode or transmit mode, full temperature range, no signal IS 70 100 μA VCC = 2.7 V 115.2 kbit/s transmission, receive mode, nose to nose operation IS 1 shutdown mode, entire temperature range ISshdown 0.02 VCC = 5.5 V, 20 °C ISshdown 10 nA IStr 360 mA 1 ms Supply current, at VCCP IRED peak current transmitting Ie = 40 mW/sr, no external resistor VCCP = 2.7 V, equivalent to SIR standard Transceiver ‘power on‘ settling time time from switching on VCC to established specified operation www.vishay.com 196 VCC Max 115.2 2.4 mA 1 μA Document Number 82542 Rev. 1.6, 04-Oct-06 TFDU4203 Vishay Semiconductors Optoelectronic Characteristics Receiver Tested for the following parameters (VCC = 2.4 V to 5.5 V, - 25 °C to + 85 °C, unless otherwise stated). Parameter Test Conditions Symbol Minimum detection threshold irradiance (logic high receiver input irradiance) | D | d ± 15 °, VCC = 2.0 V to 5.5 V 2.0 V, 25 °C tested Ee, min Maximum detection threshold irradiance | D | d ± 90 °, VCC = 5 V Ee, max | D | d ± 90 °, VCC = 3 V Logic low receiver input irradiance Output voltage RXD Output current RXD Min Ee, min Ee, max Typ. Max Unit 25 (2.5) 50 (5) mW/m2 50 100 3300 (330) 5000 (500) 8000 (800) 15000 (1500) Ee, max,low (μW/cm2) mW/m2 W/cm2 (μW/cm2) W/cm2 (μW/cm2) 4 (0.4) active, C = 15 pF VOL 0 non active, C = 15 pF VOH VCC - 0.5 mW/m2 (μW/cm2) 0.5 V 4 mA ns V VOL < 0.5 V Rise time at load C = 15 pF, R = 2.2 k: tr 20 70 Fall time at load C = 15 pF, R = 2.2 k: tf 20 70 ns Rxd signal electrical output pulse width 2.4 kbit/s, input pulse width 1.41 μs to 3/16 of bit duration tp 1.41 20 μs 115.2 kbit/s, input pulse width 1.41 μs to 3/16 of bit duration tp 1.41 4.5 μs Output delay time (RXD), leading edge optical input to electrical output output level = tdl 2 μs Jitter, leading edge of output signal over a period of 10 bit, 115.2 kbit/s tj 400 ns tdt 6.5 μs 0.1 1 ms 100 200 μs Output delay time (RXD), trailing output level = edge optical input to electrical 0.5 x VCC at 40 mW/m2 output Power on time, SD recovery time Latency Document Number 82542 Rev. 1.6, 04-Oct-06 1 0.5 x VCC at 40 mW/m2 tL www.vishay.com 197 TFDU4203 Vishay Semiconductors Transmitter Parameter Test Conditions Logic low shutdown input Symbol Min Max Unit VIL(TXD) - 0.5 Typ. 0.15 x VCC V VIH(TXD) 0.8 x VCC 6 V VIL(TXD) 0.5 0.81 x VCC V VIH(TXD) 0.8 x VCC 6 V Ie 45 Op 880 voltage*) Logic high shutdown input voltage*) Logic low transmitter input voltage*) Logic high transmitter input voltage*) Optical output radiant intensity | D | d ± 15 °, IF1 = 320 mA, mW/sr Internally current controlled**), voltage range 2.7 V to 5.5 V*) Peak emission wavelength Spectral emission bandwidth 900 Optical rise/fall time 115.2 kHz square wave signal (duty cycle 1 : 1) Optical output pulse duration input pulse duration 1.6 μs Output radiant intensity logic low level *) nm 200 1.5 1.6 Overshoot, optical Rising edge peak to peak jitter nm 40 tj over a period of 10 bits, independent of information content ns 1.7 μs 0.04 μW/sr 25 % 0.2 μs Recommended logic levels for minimum shutdown current. The CMOS decision level is 0.5 x VCC. **) Add external resistor for VCC > 4 V to prevent thermal overload, see Fig. 3. Truth table Inputs Outputs SD TXD Optical input Irradiance mW/m2 RXD Transmitter high low low low low low x high high t 25 μs low low low x x x <4 > Min. Detection Threshold Irradiance > Max. Detection Threshold Irradiance floating high high high x x 0 Ie 0 0 0 0 Application Hints Latency The TFDU4203 does not need any external components when operated with a "clean" power supply. In a more noisy ambient it is recommended to add a capacitor C1 (4.7 μF Tantalum) and a resistor R1 (d 3 :) for noise suppression. In addition the capacitor is needed to prevent a pulse distortion when the power supply is not able to generate the peak currents or inductive wiring is used. A combination of a tantalum with a ceramics capacitor will be efficient to attenuate both, RF and LF if RF noise is present. The value is dependent on the power supply quality. A good choice is between 4.7 μF and 10 μF. The receiver is in specified conditions after the defined latency. In a UART related application after that time after the last transmitted signal (IrDA specifies 500 μs maximum for low power applications and 10 ms maximum for standard) the receiver buffer of the UART must be cleared. Therefore the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state. For more application circuits, see IrDC Design Guide and TOIM4232 data sheet. Shut down To shut down the TFDU4203 into a standby mode the SD pin has to be set active. www.vishay.com 198 Document Number 82542 Rev. 1.6, 04-Oct-06 TFDU4203 Vishay Semiconductors Recommended Circuit Diagram SD 8 SD GND 5, 6 GND RXD 3 RXD TXD 7 TXD 4 VCC R1 Vcc C1 1, 2 IRED Cathode R2 18199 Recommended Application Circuit Components Component Recommended Value Vishay Part Number C1 R1 4.7 μF, 16 V 5 : max 293D 475X9 016B 2T This is a recommendation for a combination to start with to exclude power supply effects. Optimum, from a costs point of view, to work without both. Temperature Derating Diagram Ambient Temperature (˚C) 90 85 80 75 70 65 60 55 50 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % 18097 Figure 1. Temperature Derating Diagram The temperature derating diagram shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 : is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. Document Number 82542 Rev. 1.6, 04-Oct-06 www.vishay.com 199 TFDU4203 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 19535 100 150 200 250 300 350 Figure 2. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 3. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU4203 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 3 and 4 are VISHAY's recommended profiles for use with the TFDU4203 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 50 100 150 200 250 300 Time/s Figure 4. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. www.vishay.com 200 Document Number 82542 Rev. 1.6, 04-Oct-06 TFDU4203 Vishay Semiconductors Package Dimensions 19821 Drawing-No.: 6.550-5185.01-4 Issue: 5; 02.09.05 Figure 5. Package drawing, TFDU4203 Document Number 82542 Rev. 1.6, 04-Oct-06 www.vishay.com 201 TFDU4203 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 mm mm mm mm mm mm mm Tape Width A max. N W1 min. W2 max. W3 min. W3 max. 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 202 Document Number 82542 Rev. 1.6, 04-Oct-06 TFDU4203 Vishay Semiconductors Tape Dimensions 19820 Drawing-No.: 9.700-5227.01-4 Issue: 3; 03.09.99 Figure 6. Tape drawing, TFDU4203 for side view mounting Document Number 82542 Rev. 1.6, 04-Oct-06 www.vishay.com 203 TFDU4300 Vishay Semiconductors Infrared Transceiver Module (SIR, 115.2 kbit/s) for IrDA® Applications Description The TFDU4300 is a low profile (2.5 mm) infrared transceiver module with independent logic reference voltage (Vlogic) for low voltage IO interfacing. It is compliant to the latest IrDA® physical layer standard for fast infrared data communication, supporting IrDA speeds up to 115.2 kbit/s (SIR) and carrier based remote control. The transceiver module consists of a PIN photodiode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This device covers an extended IrDA low power range of close to 1 m. With an external current control resistor the current can be adjusted for shorter ranges. This Vishay SIR transceiver is built in a new smaller package using the experiences of the lead frame BabyFace technology. 20101 The RXD output pulse width is independent of the optical input pulse width and stays always at a fixed pulse width thus making the device optimum for standard Endecs. TFDU4300 has a tri-state output and is floating in shut-down mode with a weak pull-up. Features • Compliant to the latest IrDA physical layer specification (9.6 kbit/s to 115.2 kbit/s) and TV Remote Control, bi-directional operation included. e3 • Operates from 2.4 V to 5.5 V within specification over full temperature range from 30 °C to + 85 °C • Logic voltage 1.5 V to 5.5 V is independent of IRED driver and analog supply voltage • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476 • Extended IrDA Low Power range to about 70 cm • Typical Remote Control range 12 m • Low power consumption (< 0.12 mA supply current) • Power shutdown mode (< 5 μA shutdown current in full temperature range, up to 85 °C) • Surface mount package, low profile (2.5 mm) - (L 8.5 mm × H 2.5 mm × W 2.9 mm) • High efficiency emitter • Low profile (universal) package capable of surface mount soldering to side and top view orientation • Directly interfaces with various Super I/O and controller devices as e.g. TOIM4232 • Tri-state-receiver output, floating in shut down with a weak pull-up • Compliant with IrDA background light specification • EMI immunity in GSM bands > 300 V/m verified • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Ideal for battery operated applications • Telecommunication products (cellular phones, pagers) • Digital still and video cameras • Printers, fax machines, photocopiers, screen • projectors • Medical and industrial data collection • Diagnostic systems www.vishay.com 204 • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Internet TV boxes, video conferencing systems • External infrared adapters (Dongles) • Data loggers • GPS • Kiosks, POS, Point and Pay devices including IrFM - applications Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors Parts Table Part Description TFDU4300-TR1 Qty / Reel Oriented in carrier tape for side view surface mounting 750 pcs TFDU4300-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs TFDU4300-TT1 Oriented in carrier tape for top view surface mounting 750 pcs TFDU4300-TT3 Oriented in carrier tape for top view surface mounting 2500 pcs Functional Block Diagram VCC1 Push-Pull Driver Amplifier Comparator RXD VCC2 SD TXD Logic & Controlled Driver Control RED C GND 18282 Pin Description Pin Number Function Description 1 VCC2 IRED Anode Connect IRED anode directly to the power supply (VCC2). IRED current can be decreased by adding a resistor in series between the power supply and IRED anode. A separate unregulated power supply can be used at this pin. I/O Active 2 IRED Cathode IRED Cathode, internally connected to the driver transistor 3 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 300 Ps. The input threshold voltage adapts to and follows the logic voltage swing defined by the applied Vlogic voltage. I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. During transmission the RXD output is inactive. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. The voltage swing is defined by the applied Vlogic voltage O LOW 5 SD Shutdown. The input threshold voltage adapts to and follows the logic voltage swing defined by the applied Vlogic voltage. I HIGH 6 VCC1 Supply Voltage 7 Vlogic Vlogic defines the logic voltage level of the I/O ports to adap the logic voltage swing to the IR controller. The RXD output range is from 0 V to Vlogic, for optimum noise suppression the inputs- logic decision level is 0.5 x Vlogic 8 GND Ground Document Number 82614 Rev. 1.5, 03-Jul-06 I www.vishay.com 205 TFDU4300 Vishay Semiconductors Pinout Definitions: TFDU4300 weight 75 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA® operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former 18101 5 6 1 2 3 4 8 7 IRED A IRED C TXD RXD SD Vcc Vlog GND version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA ® standard is the actual version IrPhy 1.4 (in Oct. 2002). Absolute Maximum Ratings Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6 V - 0.5 V < Vlogic < 6 V Test Conditions VCC1 - 0.5 + 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6 V - 0.5 V < Vlogic < 6 V VCC2 - 0.5 + 6.0 V Supply voltage range, Vlogic - 0.5 V < VCC1 < 6 V - 0.3 V < VCC2 < 6 V Vlogic - 0.5 + 6.0 V RXD output voltage - 0.5 V < VCC1 < 6 V - 0.3 V < Vlogic < 6 V VRXD - 0.5 Vlogic + 0.5 V VIN - 0.5 + 6.0 V 10 mA Voltage at all inputs Note: Vin t VCC1 is allowed Input current for all pins, except IRED anode pin Output sinking current Power dissipation see derating curve Junction temperature Storage temperature range Repetitive pulsed output current, pin 1 to pin 2 www.vishay.com 206 t < 90 μs, ton < 20 % mA mW 125 °C - 30 + 85 °C Tstg - 40 + 100 °C 260 °C IIRED(DC) 125 mA IIRED(RP) 600 mA see recommended solder profile Average output current, pin 1 25 250 Tamb TJ Ambient temperature range (operating) Soldering temperature PD Typ. Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy d 1.3 1.8 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie *) Test Conditions Max Unit *) mW/sr mm (500)**) Due to the internal limitation measures the device is a "class 1" device under all conditions. **) IrDA specifies the max. intensity with 500 mW/sr. Note: We apologize to use sometimes in our documentation the abbreviation LED and the word Light Emitting Diode instead of Infrared Emitting Diode (IRED) for IR-emitters. That is by definition wrong; we are here following just a bad trend. Typical values are for design aid only, not guaranteed nor subject to production testing and may vary with time. Electrical Characteristics Transceiver Tested at Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Supply voltage Parameter Remark: For 2.4 V < V CC1 < 2.6 V at Tamb < - 25 °C a minor reduction of the receiver sensitivity may occur Test Conditions VCC1 2.4 Typ. Max Unit 5.5 V Idle supply current at V CC1 (receive mode, no signal) SD = Low, Ee = 1 klx*), Tamb = - 25 °C to + 85 °C, VCC1 = VCC2 = 2.7 V to 5.5 V ICC1 90 130 μA SD = Low, Ee = 1 klx*), Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V ICC1 75 Idle supply current at V logic (receive mode, no signal) SD = Low, Ee = 1 klx*), Vlog, pin 7, no signal, no load at RXD Ilog 1 μA Average dynamic supply current, transmitting IIRED = 300 mA, 20 % Duty Cycle ICC1 0.65 mA Standby supply current SD = High, T = 25 °C, Ee = 0 klx SD = High, T = 70 °C SD = High, T = 85 °C no signal, no load - 30 - 0.5 0.1 2 3 1 + 85 0.15 x Vlogic μA μA μA μA °C V V μA Standby supply current, Vlogic Operating temperature range Output voltage low, RXD CLoad = 15 pF ISD ISD ISD I log TA VOL Output voltage high, RXD IOH = - 500 μA VOH 0.8 x Vlogic Vlogic + 0.5 IOH = - 250 μA, CLoad = 15 pF VOH 0.9 x Vlogic Vlogic + 0.5 V RRXD 400 600 k: VIL VIH - 0.5 Vlogic - 0.5 0.5 6 V V RXD to VCC1 impedance Input voltage low (TXD, SD) Input voltage high (TXD, SD) CMOS level**), Vlogic t2.5 V CMOS level**), Vlogic <2.5 V Input leakage current (TXD, SD) VIN = 0.9 x Vlogic Controlled pull down current SD, TXD = "0" to "1", VIN < 0.15 Vlogic Input voltage high (TXD, SD) SD, TXD = "0" to "1", VIN > 0.7 Vlogic Input capacitance (TXD, SD) *) 500 VIH 0.8 x Vlogic 6 V IICH IIRTx -2 +2 + 150 μA μA IIRTx -1 1 μA 5 pF CIN 0 Standard illuminant A **) To provide an improved immunity with increasing Vlogic the typical threshold level is increasing with Vlogic and set to 0.5 x Vlogic. It is recommended to use the specified min/max values to avoid increased operating current. Document Number 82614 Rev. 1.5, 03-Jul-06 www.vishay.com 207 TFDU4300 Vishay Semiconductors Optoelectronic Characteristics Receiver Tested at Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Typ. Max Unit 9.6 kbit/s to 115.2 kbit/s O = 850 nm - 900 nm; D = 0 °, 15 ° Ee 40 (4) 80 (8) mW/m2 (μW/cm2) O = 850 nm - 900 nm Ee 5 (500) O = 850 nm - 900 nm tr, tf < 40 ns, tpo = 1.6 μs at f = 115 kHz, no output signal allowed Ee Rise time of output signal 10 % to 90 %, CL = 15 pF tr(RXD) 20 100 Fall time of output signal 90 % to 10 %, CL = 15 pF tf(RXD) 20 100 ns tPW 1.65 3.0 μs Minimum irradiance Ee in angular range **) Maximum Irradiance Ee In Angular Range ***) Maximum no detection irradiance Test Conditions RXD pulse width of output signal input pulse length > 1.2 μs Symbol Min kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) 2.0 ns Stochastic jitter, leading edge input irradiance = 100 mW/m2, d 115.2 kbit/s 250 ns Standby /Shutdown delay, receiver startup time after shutdown active or power-on 150 μs 150 μs Latency *) tL 100 Equivalent to IrDA Background Light and Electromagnetic Field Test: Fluorescent Lighting Immunity. **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angular range at the maximum Link Length. ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible ralated link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER). For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). Transmitter Tested at Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions IRED operating current Forward voltage of built-in IRED Output leakage IRED current Output radiant intensity No external resistor for current limitation*) If = 300 mA TXD = 0 V, 0 < VCC1 < 5.5 V D = 0 °, 15 ° TXD = High, SD = Low VCC1 = 5.0 V, D = 0 °, 15 ° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Symbol ID Vf IIRED Ie D Peak - emission wavelength**) Op Max Unit 300 1.8 350 1.9 1 mA V μA mW/sr 0.04 mW/sr 900 nm Optical rise time, fall time 65 ± 24 880 'O Spectral bandwidth Optical overshoot Typ. Ie Output radiant intensity, angle of Optical output pulse duration Min 250 1.4 -1 30 45 tropt, tfopt input pulse width 1.6 < tTXD < 20 μs topt input pulse width tTXD t 20 μs topt ° nm 100 tTXD-0.15 20 ns tTXD + μs 300 μs 25 % *) Using an external current limiting resistor is allowed and recommended to reduce IRED intensity and operating current when current reduction is intended to operate at the IrDA low power conditions. E.g. for VCC2 = 3.3 V a current limiting resistor of RS = 56 : will allow a power minimized operation at IrDA low power conditions. **) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Phillips RC5/RC6® or RECS 80. www.vishay.com 208 Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors Recommended Circuit Diagram Operated with a clean low impedance power supply the TFDU4300 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 1). VIRED R1 *) VCC2, IRED A VCC R2 VCC1 C1 GND C2 Ground Vlogic Vlogic SD SD TXD TXD RXD RXD IRED C 19295 Figure 1. Recommended Application Circuit *) R1 is optional when reduced intensity is used The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor, which may be used to reduce the operating current to levels below the specified controlled values for saving battery power. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The shutdown input must be grounded for normal operation, also when the shutdown function is not used. The inputs (TXD, SD) and the output RXD should be directly connected (DC - coupled) to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCC1 and injected noise. An unstable power supply with dropping voltage during transmision may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver pins. When extended wiring is used as in bench tests the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. The transceiver itself withstands EMI at a GSM frequencies above 500 V/m. When interference is observed, the wiring to the inputs picks it up. It is verified by DPI measurements that as long as the interfering RF - voltage is below the logic threshold levels of the inputs and equivalent levels at the outputs no interferences are expected. One should keep in mind that basic RF - design rules for circuits design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. “The Art of Electronics” Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Compo nent Recommended Value Vishay Part Number C1 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 depends on current to be adjusted R2 47 :, 0.125 W Document Number 82614 Rev. 1.5, 03-Jul-06 CRCW-1206-47R0-F-RT1 www.vishay.com 209 TFDU4300 Vishay Semiconductors 19296 Figure 2. Typical application circuit Current Derating Diagram Figure 3 shows the maximum operating temperature when the device is operated without external current limiting resisor. I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. For operating at RS232 ports the ENDEC TOIM4232 is recommended. 90 Ambient Temperature (˚C) Figure 2 shows an example of a typical application for to work with low voltage logic (connected to VDD), a seperate supply voltage VS and using the transceiver with the IRED Anode connected to the unregulated battery Vbatt. This method reduces the peak load of the regulated power supply and saves therefore costs. Alternatively all supplies can also be tied to only one voltage source. R1 and C1 are not used in this case and are depending on the circuit design in most cases not necessary. 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 3. Current Derating Diagram Table 2. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitter Operation high > 1 ms x x weakly pulled (500 k:) to VCC1 0 Shutdown low high x high inactive Ie Transmitting low high > 50 μs x high inactive 0 Protection is active low low <4 high inactive 0 Ignoring low signals below the IrDA® defined threshold for noise immunity low low > Min. irradiance Ee < Max. irradiance Ee low (active) 0 Response to an IrDA® compliant optical input signal low low > Max. Irradiance Ee undefined 0 Overload conditions can cause unexpected outputs www.vishay.com 210 Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 100 19535 150 200 250 300 350 Figure 4. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 5. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU4300 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 and 6 are VISHAY's recommended profiles for use with the TFDU4300 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 50 100 150 200 250 300 Time/s Figure 6. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Document Number 82614 Rev. 1.5, 03-Jul-06 www.vishay.com 211 TFDU4300 Vishay Semiconductors Package Dimensions in mm 19700 www.vishay.com 212 Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 Document Number 82614 Rev. 1.5, 03-Jul-06 W3 max. www.vishay.com 213 TFDU4300 Vishay Semiconductors Tape Dimensions in mm 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 7. Tape drawing, TFDU4300 for top view mounting www.vishay.com 214 Document Number 82614 Rev. 1.5, 03-Jul-06 TFDU4300 Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 8. Tape drawing, TFDU4300 for side view mounting Document Number 82614 Rev. 1.5, 03-Jul-06 www.vishay.com 215 Vishay Semiconductors www.vishay.com 216 Contents TFBS5700..............................218 TFBS5711..............................230 TFDU5307 ............................. 242 MIR (9.6 kbit/s to 1.15 Mbit/s) www.vishay.com 217 TFBS5700 Vishay Semiconductors Fast Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA® and Remote Control Applications Description The TFBS5700 is a low profile infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 1.152 Mbit/s (MIR) and carrier based remote control modes up to 2 MHz. The transceiver module consists of a PIN photodiode, an infrared emitter (IRED), and a low-power control IC to provide a total font-end solution in a single package. 20207 Features • IrDA IrPHY 1.4 compliant 9.6 kbit/s to 1.152 Mbit/s range > 50 cm, exceeding the low e4 power standard • Wide operating voltage range 2.4 V to 3.6 V • I/O compatible to 1.8 V logic voltage • Low power consumption Supply current in receive mode, Idle: 550 μA • Small package L 6.8 mm x W 2.8 mm x H 1.6 mm • Remote control transmitter operation - Typical range 12 m • Emitter wavelength: 886 nm - suited for Remote Control • High immunity to fluorescence light • High EMI immunity > 200 V/m (700 MHz to 2100 MHz) • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Mobile phone • Smart phone • PDAs • POS Terminals/Vending • Battery Operated IrDA applications Parts Table Part TFBS5700-TR3 www.vishay.com 218 Description Qty/Reel Oriented in carrier tape for side view surface mounting 2500 pcs Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors Functional Block Diagram VCC Tri-state Driver PD Amplifier Comparator RXD IRED SD Mode Control IREDA IRED Driver TXD ASIC GND 19291 Pin Description Pin Number Function Description 1 IRED A IRED anode, VCC2 I/O Active 2 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs. When used in conjunction with the SD pin, this pin is also used to control receiver output pulse duration. The input threshold voltage adapts to and follows the internal logic voltage reference of 1.8 V I HIGH 3 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. The voltage swing is defined by the internal Vlogic voltage of 1.8 V O LOW 4 SD Shutdown. Also used for setting the output pulse duration. Setting this pin active for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used to set the receiver output to long pulse duration (2 μs) or to short pulse duration (0.4 μs) mode. The input threshold voltage adapts to and follows the internal logic voltage reference of 1.8 V I HIGH 5 VCC Power Supply. Receives power supply 2.4 V to 3.6 V. This pin provides power for the receiver and transmitter drive section. 6 GND Ground Pinout Definitions: TFBS5700, bottom view weight 33 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhY 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhY 1.1, followed by IrPhY 1.2, adding the SIR Low Power Standard. IrPhY 1.3 extended the 19290 Low Power Option to MIR and FIR and VFIR was added with IrPhY 1.4. A new version of the standard in any case obsoletes the former version. Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 219 TFBS5700 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6.5 V Voltage at all I/O pins - 0.5 Typ. 5.5 V Power dissipation See derating curve PD 350 mW Junction temperature Note: Internal protection above 125° ASIC temperature TJ 125 °C Ambient temperature range (operating) Storage temperature range Soldering temperature Tamb - 30 + 85 °C Tstg - 40 + 100 °C 260 °C IIRED (DC) 125 mA IIRED (RP) 500 See section “Recommended Solder Profile” Average output current Repetitive pulse output current < 90 μs, ton < 20 % Virtual source size Method: (1-1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie 0.8 mA mm *) mW/sr (500)**) ESD protection ESD protection on all pins Method: Human body model Latch up *) d 1 kV d |± 100| mA Due to the internal limitation measures the device is a "class1" device **) IrDA specifies the max. intensity with 500 mW/sr www.vishay.com 220 Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC 2.4 Typ. Max Unit 3.6 V Dynamic Supply current Idle, dark ambient SD = Low (< 0.8 V), Ee = 0 klx ICC 550 Receiving SD = Low, 1 Mbit/s, ICC 0.75 Shutdown supply current SD = High (> VCC1 - 1.3 V), T = 25 °C, Ee = 0 klx T = 25 °C ISD SD = High, (> VCC1 - 1.3 V), T = 85 °C ISD Output voltage low IOL = 0.5 mA, Cload = 15 pF VOL Output voltage high IOH = - 250 μA, Cload = 15 pF VOH Output voltage high IOH = 0 μA, Cload = 15 pF VOH RXD to internal Vlogic impedance SD = active, pull-up in shutdown RRXD 400 Input voltage low (TXD, SD) VIL - 0.5 Input voltage high (TXD, SD) VIH 1.3 IS-SD, IIN-SD - 1.1 tSDPW 0.2 900 μA mA Ee = 100 mW/m2 Dark ambient Shutdown supply current at maximum operating temperature Operating temperature range Input leakage current (TXD, SD) *) SD mode programming pulse width Input capacitance (TXD, SD) *) 0.01 TA Vin = 0.9 x VCC1 CI - 25 1.0 μA 5.0 PA + 85 °C 0.4 V 1.44 V 1.98 V 800 k: 0.5 V 1.8 2.2 V 4 10 μA 300 μs 5 pF 500 Decision level 0.9 V Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 221 TFBS5700 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Minimum irradiance Ee in angular range **) SIR mode 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm Ee Minimum irradiance Ee in angular range **) MIR mode 1.152 Mbit/s O = 850 nm to 900 nm Ee Maximum irradiance Ee in angular range ***) O = 850 nm to 900 nm Ee Logic LOW receiver input irradiance *) According to IrDA appendix A1, fluorescent light specification Ee RXD pulse width of output signal, dafault mode after power on or reset Input pulse length TWopt > 200 ns Min Typ. Max Unit 50 (5) 81 (8.1) mW/m2 50 (5) 140 (14) 5 (500) (μW/cm2) mW/m2 (μW/cm2) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) 300 400 500 ns Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 10 27 60 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 10 17 60 ns tPW 1.7 2.0 2.9 μs SIR ENDEC compatility mode 1): Input pulse length RXD pulse width of output signal TWopt > 200 ns, see chapter “Programming” Stochastic jitter, leading edge Input irradiance = 150 mW/m2, d 1.152 Mbit/s, 576 kbit/s 70 ns Stochastic jitter, leading edge Input irradiance = 150 mW/m2, d 115.2 kbit/s 350 ns Standby/shutdown delay after shutdown active or (SD low to high transition) 1.5 ms Shutdown active time window for During this time the pulse programming duration of the output can be programmed to the application mode. see chapter “Programming” 600 μs Receiver start up time, Power on delay Shutdown recovery delay 250 μs 200 μs 0.6 After shutdown inactive (SD high to low transition) and power-on Latency tL 50 ® Note: All timing data measured with 4 Mbit/s are measured using the IrDA FIR transmission header. The data given here are valid 5 μs after starting the preamble. *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance E In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the e maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). 1) Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFBS5700. TFBS5700 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming". www.vishay.com 222 Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Recommended IRED operating peak current **) The IRED current must be controlled by an external resistor Output leakage IRED current TXD = 0 V, Tamb = 25 °C TXD = 0 V, Tamb = 85 °C Symbol Typ. Max Unit ID 200 600 mA IIRED 200 1 pA μA 500 mW/sr 0.04 mW/sr Output radiant intensity, s. figure a = 0°, 15°, TXD = High, SD = 3, recommended appl. circuit Low, VCC1 = 2.5 V, VCC2 = 2.9 V, Rs = 4.7 : Ie VCC1 = 5.0 V, D = 0°, 15° TXD = Low, SD = High (Receiver is inactive as long as SD = High) Ie Output radiant intensity Peak - emission wavelength *) Op Optical spectral bandwidth 'O Optical rise time, Optical fall time Optical output pulse duration Min 25 60 880 900 nm 45 tropt, tfopt 10 Input pulse width 217 ns, 1.152 Mbit/s topt 180 Input pulse width t < 80 μs Input pulse width t t 80 μs topt topt 217 Optical overshoot nm 40 ns 240 ns tTXD 85 μs μs 25 % *) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (> 120 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. **) Typ. conditions for If = 200 mA, VCC2 = 2.9 V, Rs = 4.7 : Table 1. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitter Operation high < 600 μs x x weakly pulled (500 k:) to VCC1 0 Time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k:) to VCC1 0 Shutdown low high x low (active) Ie Transmitting low high > 80μs x high inactive 0 Protection is active low low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low low > Min. irradianceEe < Max. irradiance Ee low (active) 0 Response to an IrDA compliant optical input signal low low > Max. irradiance Ee undefined 0 Overload conditions can cause unexpected outputs Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 223 TFBS5700 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS5700 needs only one additional external component for setting the IRED drive current. However, depending on the entire system design and board layout, additional components may be required (see figure 1). V cc2 R1 V cc1 R2 C1 GND IRED Anode V cc C2 Ground SD SD TXD TXD RXD RXD 19297 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a small ceramic version or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for setting the IRED drive current. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current is rise time. In that case another 10 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Wienfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 2. Recommended Application Circuit Components Component Recommended Value C1, C2 0.1 μF, Ceramic Vishay part# VJ 1206 Y 104 J XXMT R1 2.9 V to 5.4 V supply voltage VCC2: add a resistor in series, e.g. 4.7: R2 47 :, 0.125 W (VCC1 t 2.5 V) www.vishay.com 224 Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors I/O and Software Simplified Method In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Setting the device to the long pulse duration is nothing else than a short active SD pulse of less than 600 μs. In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Backwards also an active SD can be used to fall back into the default mode by applying that signal for a minimum of 1.5 ms. That causes a power-onreset and sets the device to the default short pulse mode. This simplified method takes more time but may be easier to handle. Programming Pulse duration Switching After Power-on the TFBS5700 is in the default short pulse duration mode. Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with an extended pulse duration as in standard SIR transceivers was added in TFBS5700. TFBS5700 is set to the “short output pulse” as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the following. To switch the transceivers from the short pulse duration mode to the long pulse duration mode and vice versa, the programming sequences described below are required. 50 % SD ts th High : FIR TXD 50 % 50 % Low : SIR 14873 Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 μs 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. After waiting th t 200 ns TXD. TXD is now enable as normal TXD input for the longer RXD - pulse duration mode. Figure 2. Mode Switching Timing Diagram Setting back to the default mode with 400 ns RXD-output pulse duration 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD is limited by the maximum allowed pulse length. TXD is now enabled as normal TXD input. The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 μs. See in the spec. “Shutdown Active Time Window for Programming” Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 225 TFBS5700 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 3. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS5700 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 4 is VISHAY's recommended profiles for use with the TFBS5700 transceivers. For more details please refer to Application note: SMD Assembly Instruction (http://www.vishay.com/docs/82602/82602.pdf). Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 4. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 226 Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors Package Dimensions in mm 19325_1 Figure 5. TFBS5700 mechanical dimensions, tolerance ± 0.2 mm if not otherwise mentioned 19294 Figure 6. TFBS5700 soldering footprint, tolerance ± 0.2 mm if not otherwise mentioned Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 227 TFBS5700 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 228 W3 max. Document Number 84670 Rev. 2.1, 25-Sep-06 TFBS5700 Vishay Semiconductors Tape Dimensions in mm 19286 Document Number 84670 Rev. 2.1, 25-Sep-06 www.vishay.com 229 TFBS5711 Vishay Semiconductors Fast Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA® Applications Description The TFBS5711 is an infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 1.152 Mbit/s (MIR), HP-SIR®, Sharp ASK® and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum a serial resistor for current control is the only external 20208 component required in implementing a complete solution. TFBS5711 has a tri-state output and is floating in shut-down mode with a weak pull-up. Features • Compliant to the latest IrDA physical layer low power specification (up to 1.152 Mbit/s) and TV Remote Control e4 • Operates from 2.7 V to 5.5 V within specification • Industries smallest footprint - 6.0 mm length - 1.9 mm height • Low Power Consumption (typ. 0.55 mA Supply Current in receive mode, no signal) • Power Shutdown Mode (< 5 PA Shutdown Current in Full Temperature Range, up to 85 °C) • Surface Mount Package, low profile (1.9 mm) Universal (L 6.0 mm x W 3.1 mm x H 1.9 mm) • Directly Interfaces with Various Super I/O and Controller Devices • Tri-state-Receiver Output, floating in shut down with a weak pull-up • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US - Patent No. 6,157,476 • Only One External Component Required • TV Remote Control supported • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Telecommunication Products (Cellular Phones, Pagers) • Digital Still and Video Cameras • Printers, Fax Machines, Photocopiers, Screen Projectors • Medical and Industrial Data Collection • Notebook Computers, Desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs • Internet TV Boxes, Video Conferencing Systems • External Infrared Adapters (Dongles) • Kiosks, POS, Point and Pay Devices including IrFM - Applications Parts Table Part Description Qty / Reel TFBS5711-TR1 Oriented in carrier tape for side view surface mounting 1000 pcs TFBS5711-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs www.vishay.com 230 Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier Comparator RXD VCC2 Controlled Driver Logic & SD TXD Control GND 18512 Pinout TFBS5711 weight 50 mg PIN 1 19428 Functional Block Diagram Pin Number Function Description 1 VCC2 IRED Anode Connect IRED anode directly to be the power supply (VCC2). An external resistor is necessary for controlling the IRED current. A separate unregulated power supply can be used at this pin. I/O Active 2 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs. When used in conjunction with the SD pin, this pin is also used to control receiver output pulse duration. I HIGH 3 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. No external pull-up or pulldown resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. O LOW 4 SD Shutdown, also used for setting the output pulse duration. Setting this pin active for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used to set the receiver output to long pulse duration (2 μs) or to short pulse duration (0.4 μs) mode I HIGH 5 VCC1 Supply Voltage 6 GND Ground Document Number 82634 Rev. 1.5, 03-Jul-06 www.vishay.com 231 TFBS5711 Vishay Semiconductors Absolute Maximum Ratings Reference point Ground (Pin 6) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6 V Test Conditions VCC1 - 0.3 Typ. + 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6 V VCC2 - 0.3 + 6.5 V Input currents For all pins, except IRED anode pin 10 mA Output sinking current Power dissipation See derating curve PD 125 °C - 25 + 85 °C Tstg - 25 + 85 °C 240 °C IIRED(DC) 125 mA IIRED(RP) 600 mA V TJ Storage temperature range Soldering temperature See recommended solder profile Average output current, pin 1 Repetitive pulsed output current, pin 1 t < 90 μs, ton < 20 % IRED anode voltage, pin 1 mA mW Tamb Junction temperature Ambient temperature range (operating) 25 500 VIREDA - 0.5 + 6.5 Vin - 0.5 + 5.5 V 50 pF Voltage at all inputs and outputs Vin < VCC1 is allowed Load at mode pin when used as mode indicator Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy d 1.3 1.5 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie *) Test Conditions Max Unit mm mW/sr *) (500)**) Due to the internal limitation measures the device is a "class 1" device. **) IrDA specifies the max. intensity with 500 mW/sr. www.vishay.com 232 Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC1 2.7 Typ. Max Unit 5.5 V Dynamic supply current SD = Low, Ee = 1 klx ICC 550 900 μA Average dynamic supply current, transmitting IIRED = 500 mA, 25 % Duty Cycle ICC 1100 1500 μA Standby supply current SD = High, T = 25 °C, Ee = 0 klx ISD 1 μA SD = High, T = 25 °C, ISD 2.5 μA SD = High, T = 85 °C, not ambient light sensitive ISD 5 μA + 85 °C Output voltage low, RXD CLoad = 15 pF, IOL = 1 mA VOL 0.4 V Output voltage high, RXD IOH = - 500 μA VOH 0.8 x VCC1 IOH = - 250 μA, CLoad = 15 pF VOH 0.9 x VCC1 RRXD 400 Ee = 1 klx*) Operating temperature range TA RXD to VCC1 impedance Input voltage low (TXD, SD) - 25 V V 500 600 k: V VIL - 0.5 0.5 VIH VCC1 - 0.5 VCC1 + 0.5 V Input leakage current (TXD, SD) Vin = 0.9 x VCC1 IICH -2 +2 μA Controlled pull down current SD, TXD = "0" to "1", 0 < Vin < 0.15 VCC1 IIRTx + 150 μA SD, TXD = "0" to "1", Vin > 0.7 VCC1 IIRTx 1 μA 5 pF Input voltage high (TXD, SD) CMOS level**) Input capacitance (TXD, SD) -1 0 CIN *) Standard illuminant A **) The typical threshold level is 0.5 x VCC1. It is recommended to use the specified min/max values to avoid increased operating current Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typ. Max Unit Minimum detection threshold irradiance Parameter 9.6 kbit/s to 1152 kbit/s O = 850 nm - 900 nm Test Conditions Ee 100 (10) 150 (15) mW/m2 Maximum detection threshold irradiance O = 850 nm - 900 nm Ee 5 (500) Logic LOW receiver input irradiance Symbol Ee Min (μW/cm2) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr(RXD) 20 60 Fall time of output signal 90 % to 10 %, CL = 15 pF tf(RXD) 20 60 ns tPW 300 400 500 ns tPW 1.7 2.0 2.9 μs RXD pulse width of output signal, input pulse length default mode after power on tPWopt > 200 ns SIR ENDEC compatibility mode*): RXD pulse width of output signal Document Number 82634 Rev. 1.5, 03-Jul-06 Input pulse length tPWopt > 200 ns, see chapter "Programming" ns www.vishay.com 233 TFBS5711 Vishay Semiconductors Parameter Stochastic jitter, leading edge Max Unit Input irradiance = 100 mW/m2, 1.152 Mbit/s, 576 kbit/s Test Conditions Symbol Min Typ. 80 ns Input irradiance = 100 mW/m2, d 115.2 kbit/s 350 ns 1.5 ms Standby /Shutdown delay After shutdown active or (SD low to high transition) Shutdown active time window for programming During this time the pulse duration of the output can be programmed to the application mode. see chapter "Programming" 600 μs Receiver start up time power on delay shutdown recovery delay After shutdown inactive (SD high to low transition) and after power-on 300 μs 200 μs Latency 0.6 tL *) Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming" Transmitter Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min IRED operating current, recommended serial resistor for MIR applications VCC2 = 3.3 V: RS = 2.0 : VCC2 = 5.0 V: RS = 5.6 : Output leakage IRED current TXD = 0 V, 0 < VCC1 < 5.5 V IIRED -1 Output radiant intensity recommended application circuit, see figure 1 IF = 250 mA, D = 0 °, D = 15 °, VCC2 = 2.7 V, TXD = High, SD = Low Ie 10 Output radiant intensity VCC1 = 5.0 V, D = 0 °, 15 ° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie ID Peak - emission wavelength*) Op Spectral bandwidth 'O Optical rise time, fall time Optical output pulse duration Optical overshoot Max Unit 400 500 mA 1 μA 25 mW/sr 0.04 D Output radiant intensity, angle of half intensity Typ. ± 24 880 mW/sr ° 900 45 nm nm tropt, tfopt 10 topt 200 Input pulse width tTXD < 80 μs topt 20 tTXD μs Input pulse width tTXD t 80 μs topt 20 85 μs 25 % Input pulse width 217 ns, 1.152 Mbit/s 217 40 ns 240 ns *) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Phillips RC5/RC6® or RECS 80. With the typical specified intensity an RC operating range of about 4 m can be expected. www.vishay.com 234 Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Recommended Circuit Diagram for IrDA and Remote Control Operation In general Vishay transceivers are using the identical circuit for IrDA and Remote Control operation. For using the IrDA transceiver as an RC transmitter no change of the operating circuit is necessary. Used with a clean low impedance power supply the TFBS5711 only needs an external series current limiting resistor. However, depending on the entire system design and board layout, additional external components may be required (see figure 1). V2 R1 IRED Anode VCC2 V1 R2 VCC1 C1 C3 C2 GND Ground SD SD Txd Txd Rxd Rxd 18560 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor and this is supply voltage dependent, see derating curve in figure 4, to avoid too high internal power dissipation. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages V1 and V2 and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. An Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at V2. Often some power supplies are not apply to follow the fast current rise time. In that case another 4.7 PF (type, see table under C1) at V2 will be helpful. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 5 V supply voltage: 5.6 : s. text 0.25 W (recommended using two 2.8 :, 0.125 W resistors in series). 3.3 V supply voltage: 2.0 : s. text 0.25 W e.g. 2 x CRCW-1206-2R0-F-RT1 for 3.3 V supply voltage R2 47 :, 0.125 W CRCW-1206-47R0-F-RT1 Document Number 82634 Rev. 1.5, 03-Jul-06 Vishay Part Number www.vishay.com 235 TFBS5711 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Programming Pulse duration Switching After Power-on the TFBS5711 is in the default short RXD pulse duration mode. Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with extended pulse duration (same as in standard SIR transceivers) is added in TFBS5711. TFBS5711 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (SD being active longer than 1.5 ms). To switch the transceivers from the short RXD pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below. 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. After that TXD is now enabled as normal TXD input and the RXD output is set for the short RXD - pulse duration mode. The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 Ps. See in the spec. "Shutdown Active Time Window for Programming" SD 50 % ts th High: TXD 50 % 400 ns 50 % Low: 2 μs 18150 Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 Ps 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns. After that TXD is enabled as normal TXD input and the RXD output is set for the longer RXD - pulse duration mode. Setting back to the default mode with a 400 ns pulse duration 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). www.vishay.com 236 Figure 2. Timing Diagram for changing the output pulse duration Simplified Method Setting the device to the long pulse duration is simply applying a short active (less than 600 Ps) pulse to SD (TXD = Low). In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Vice versa applying a 1.5 ms (minimum) pulse at SD will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. This simplified method takes more time but may be easier to handle. Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Table 2. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitter Operation high < 600 Ps x x weakly pulled (500 k:) to VCC1 0 Time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k:) to VCC1 0 Shutdown low high x low (active) Ie Transmitting high > 80 Ps x high inactive 0 Protection is active low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low > Min. Detection Threshold Irradiance < Max. Detection Threshold Irradiance low (active) 0 Response to an IrDA compliant optical input signal low > Max. Detection Threshold Irradiance undefined 0 Overload conditions can cause unexpected outputs Dry packing Recommended Method of Storage The reel is packed in a moisture proof aluminum bag to protect the device from absorbing moisture during transportation and storage. Dry box storage is recommended as soon as the dry bag has been opened to prevent moisture absorption. The following conditions should be observed, if dry boxes are not available: Aluminum bag Moisture Level Sticker BarCode ESD Sticker Label LEVEL CAUTION This bag contains MOISTURE-SENSITIVE DEVICES 4 1. Shelf life in sealed bag: 12 months at < 40 °C and < 90 % relative humidity (RH) Box 0 Reel 18298 2. After this bag is opened, devices that will be subjected to soldering reflow or equivalent processing (peak package body temp. 260 °C) must be 2a. Mounted within 72 hours at factory condition of < 30 °C/60 % RH or 2b. Stored at < 5 % RH 3. Devices require baking befor mounting if: Humidity Indicator Card is > 10 % when read at 23 °C ± 5 °C or 2a. or 2b. are not met. 4. If baking is required, devices may be baked for: 192 hours at 40 °C + 5 °C/- 0 °C and < 5 % RH (dry air/nitrogen) or 96 hours at 60 °C ± 5 °C and < 5 % RH for all device containers or 24 hours at 125 °C ± 5 °C not suitable for reels or tubes Bag Seal Date: (If blank, see barcode label) Note: Level and body temperature defined by EIA JEDEC Standard JSTD-020 Acc. to EIA JEDEC Standard JSTD-020 Document Number 82634 Rev. 1.5, 03-Jul-06 www.vishay.com 237 TFBS5711 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 Temperature/°C 160 °C max. 160 140 120 s...180 s 120 90 s max. 100 80 280 2...4 °C/s 60 260 40 240 20 220 T ≥ 255 °C for 20 s max T peak = 260 °C max. T ≥ 217 °C for 50 s max 200 0 50 100 150 200 250 300 350 Time/s 19431 Figure 3. Recommended Solder Profile for Sn/Pb soldering 180 Temperature/°C 0 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 Lead (Pb)-Free, Recommended Solder Profile The TFBS5711 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 4 is VISHAY's recommended profiles for use with the TFBS5711 transceivers. For more details please refer to Application note: SMD Assembly Instruction. 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 4. Solder Profile, RSS Recommendation Current Derating Diagram Figure 5 shows the maximum operating temperature when the device is operated without external current limiting resistor. A minimum resistor of 2 Ohms is recommended from the anode of the IRED to VCC. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Ambient Temperature (˚C) 90 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 5. Temperature Derating Diagram www.vishay.com 238 Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Package Dimensions in mm (Inches) 19612 Figure 6. Package drawing of TFBS5711, tolerance of height is + 0.1mm, - 0.2 mm, other tolerances ± 0.2 mm 19728 Figure 7. Recommended Solder Footprint Document Number 82634 Rev. 1.5, 03-Jul-06 www.vishay.com 239 TFBS5711 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 240 W3 max. Document Number 82634 Rev. 1.5, 03-Jul-06 TFBS5711 Vishay Semiconductors Tape Dimensions in mm 19613 Document Number 82634 Rev. 1.5, 03-Jul-06 www.vishay.com 241 TFDU5307 Vishay Semiconductors Fast Low Profile (2.5 mm) Infrared Transceiver Module (MIR, 1.152 Mbit/s) for IrDA® Applications Description The TFDU5307 is an infrared transceiver module compliant to the latest IrDA physical layer standard, supporting IrDA speeds up to 1.152 Mbit/s (MIR) and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This Vishay MIR transceiver is built in a low profile package using the experiences of the lead frame babyface technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum, a VCC bypass capacitor and a serial resistor for current control are the only external com- 20101 ponents required implementing a complete solution. TFDU5307 has a tri-state output and is floating in shutdown mode with a weak pull-up. Features • Compliant to the latest IrDA physical layer specification (up to 1.152 Mbit/s) and TV Remote Control, bi-directional operation included. e3 • Sensitivity covers full IrDA range. Recommended operating range is from nose to nose to 70 cm • Operates from 2.7 V to 5.5 V within specification • Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal) • Power shutdown mode (< 5 μA Shutdown Current in Full Temperature Range, up to 85 °C) • Surface mount package, low profile universal (L 8.5 mm x W 2.9 mm x H 2.5 mm) Capable of surface mount soldering to side and top view orientation • Backward pin compatible to Vishay Semiconductors SIR and MIR infrared transceivers • High efficiency emitter • Directly interfaces with various super I/O and controller devices • Tri-state-receiver output, floating in shut down with a weak pull-up • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US Patent No. 6,157,476 • Logic voltage 1.5 V to 5.5 V is independent of IRED driver and analog supply voltage • Only one external component required • TV remote control supported • Transmitter intensity can be adjusted by an external resistor for extended range (> 0.7 m) or minimum low power (> 0.2 m) IrDA compliance. • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Telecommunication products (cellular phones, pagers) • Digital still and video cameras • Printers, fax machines, photocopiers, screen projectors • Low power consumption (typ. 0.55 mA Supply current in receive mode, no signal) www.vishay.com 242 • Medical and industrial data collection • Notebook computers, desktop PCs, Palmtop Computers (Win CE, Palm PC), PDAs • Internet TV boxes, video conferencing systems • External infrared adapters (dongles) • Kiosks, POS, Point and Pay devices including IrFM - applications Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Parts Table Part Description TFDU5307-TR1 Qty / Reel Oriented in carrier tape for side view surface mounting 750 pcs TFDU5307-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs TFDU5307-TT1 Oriented in carrier tape for top view surface mounting 750 pcs TFDU5307-TT3 Oriented in carrier tape for top view surface mounting 2500 pcs Functional Block Diagram Vlogic VCC1 Tri-State Driver Amplifier SD TXD Comparator Logic & VCC2 RXD IRED Driver Control IRED C GND 18509 Pin Description Pin Number Function Description 1 IRED Anode Connect IRED anode to the VCC2 power supply through an external current limiting resistor. A separate unregulated power supply can be used at this pin. I/O Active 2 IRED Cathode IRED Cathode, internally connected to the driver transistor 3 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An onchip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 Ps. When used in conjunction with the SD pin, this pin is also used to control receiver output pulse duration. The input threshold voltage adapts to and follows the logic voltage reference applied to the Vlogic pin (pin 7). I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. The voltage swing is defined by the applied Vlogic voltage O LOW 5 SD Shutdown. Also used for setting the output pulse duration. Setting this pin active for more than 1.5 ms places the module into shutdown mode. Before that (t < 0.7 ms) on the falling edge of this signal, the state of the TXD pin is sampled and used to set the receiver output to long pulse duration (2 μs) or to short pulse duration (0.4 Ps) mode. The input threshold voltage adapts to and follows the logic voltage reference applied to the Vlogic pin (pin 7). I HIGH 6 VCC1 Supply Voltage 7 Vlogic Vlogic defines the logic voltage levels for input and output. The RXD output range is from 0 V to Vlogic, for optimum noise suppression the inputs’ logic decision level is 0.5 x Vlogic 8 GND Ground Document Number 82616 Rev. 1.5, 07-Apr-06 I www.vishay.com 243 TFDU5307 Vishay Semiconductors Pinout Definitions: TFDU5307 weight 75 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former 18101 5 6 1 2 3 4 8 7 IRED A IRED C TXD RXD SD Vcc Vlog GND version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). Absolute Maximum Ratings Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6 V - 0.5 V < Vlogic < 5.5 V Test Conditions VCC1 - 0.3 + 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6 V - 0.5 V < Vlogic < 5.5 V VCC2 - 0.3 + 6.5 V Supply voltage range, Vlogic - 0.5 V < VCC1 < 6 V - 0.3 V < VCC2 < 6.5 V Vlogic - 0.3 + 5.5 V Input current For all pins, except IRED anode pin 10 mA Output sinking current Power dissipation See derating curve, figure 4 Junction temperature Storage temperature range Repetitive pulsed output current, pin 1 to pin 2 t < 90 μs, ton < 20 % IRED anode voltage, pin 1 Voltage at all inputs and outputs Vin < VCC1 is allowed Load at mode pin when used as mode indicator www.vishay.com 244 mA mW 125 °C - 25 + 85 °C Tstg - 25 + 85 °C 260 °C IIRED(DC) 125 mA IIRED(RP) 600 mA V See recommended solder profile (figure 3) Average output current, pin 1 25 500 Tamb TJ Ambient temperature range (operating) Soldering temperature PD Typ. VIREDA - 0.5 + 6.5 Vin - 0.5 + 5.5 V 50 pF Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Eye safety information Symbol Min Typ. Virtual source size Parameter Method: (1-1/e) encircled energy d 1.8 2.0 Maximum intensity for class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie *) Test Conditions Max Unit mm (500)*) **) mW/sr Max Unit Due to the internal limitation measures the device is a "class 1" device. **) IrDA specifies the max. intensity with 500 mW/sr. Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC1 2.7 Typ. 5.5 V Idle supply current SD = Low, Ee = 1 klx ICC1 550 900 μA Average dynamic supply current, transmitting IIRED = 500 mA, 25 % Duty Cycle ICC 1100 1500 μA Shutdown supply current SD = High, T = 25 °C, Ee = 0 klx ISD 1 μA SD = High, T = 25 °C, ISD 2.5 μA SD = High, T = 85 °C, not ambient light sensitive ISD 5 μA + 85 °C Output voltage low, RXD CLoad = 15 pF, IOL = 1 mA VOL 0.4 V Output voltage high, RXD IOH = - 500 μA VOH 0.8 x Vlogic IOH = - 250 μA, CLoad = 15 pF VOH 0.9 x Vlogic RRXD 400 Ee = 1 klx*) Standby supply current Operating temperature range TA RXD to VCC1 impedance Input voltage low (TXD, SD) Input voltage high (TXD, SD) CMOS level**) Input leakage current (TXD, SD) Vin = 0.9 x Vlogic Controlled pull down current SD, TXD = "0" to "1", 0 < Vin < 0.15 Vlogic SD, TXD = "0" to "1", Vin > 0.7 Vlogic Input capacitance (TXD, SD) *) - 25 V V 500 600 k: V VIL - 0.5 0.5 VIH Vlogic - 0.5 Vlogic + 0.5 V IICH -2 +2 μA + 150 μA 1 μA 5 pF IIRTx IIRTx CIN -1 0 Standard illuminant A **) The typical threshold level is 0.5 x Vlogic. It is recommended to use the specified min/max values to avoid increased operating current. The inputs in low state are actively loaded for noise protection. See for that the "Controlled pull down current" spec. Equivalently a pull up current stabilizes the state when the inputs are in high state. Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 245 TFDU5307 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Typ. Max Unit 40 (4) 90 (9) mW/m2 Minimum detection threshold irradiance 9.6 kbit/s to 1.152 Mbit/s O = 850 nm - 900 nm Ee Maximum detection threshold irradiance O = 850 nm - 900 nm Ee No detection receiver input irradiance Threshold! No RXD output below this irradiance value allowed Ee Rise time of output signal 10 % to 90 %, CL = 15 pF, Vlogic = VCC tr(RXD) 20 60 ns Fall time of output signal 90 % to 10 %, CL = 15 pF, Vlogic = VCC tf(RXD) 20 60 ns tPW 300 400 500 ns tPW 1.7 2.0 2.9 μs Input irradiance = 100 mW/m2, 1.152 Mbit/s, 576 kbit/s 80 ns Input irradiance = 100 mW/m2, d 115.2 kbit/s 350 ns 1.5 ms RXD pulse width of output Input pulse length signal, default mode after power PWopt > 200 ns on or reset SIR ENDEC compatibility mode*): RXD pulse width of output signal Stochastic jitter, leading edge Input pulse length PWopt > 200 ns, see chapter "Programming" 5 (500) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) Standby /Shutdown delay After shutdown active or (SD low to high transition) Shutdown active time window for programming During this time the pulse duration of the output can be programmed to the application mode. see chapter "Programming" 600 μs Receiver start up time power on delay shutdown recovery delay After shutdown inactive (SD high to low transition) and after power-on 300 μs 200 μs Latency 0.6 (μW/cm2) tL *) Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore this additional mode was added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, also after recovering from the shutdown mode (SD must have been longer active than 1.5 ms). For mode changing see the chapter "Programming" www.vishay.com 246 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions IRED operating current, recommended serial resistor for MIR applications VCC2 = 3.3 V: RS = 2.0 : VCC2 = 5.0 V: RS = 5.6 : Output leakage IRED current TXD = 0 V, 0 < VCC1 < 5.5 V Output radiant intensity recommended application circuit, see figure 1 D = 0 °, If =420 mA Symbol Min ID Typ. Max Unit 450 500 mA IIRED -1 1 μA Ie 110 500 mW/sr Ie 70 500 mW/sr 0.04 mW/sr TXD = High, SD = Low **) D = 0 °, 15 °, If =420 mA 120 TXD = High, SD = Low **) Output radiant intensity VCC1 = 5.0 V, D = 0 °, 15 ° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie D Output radiant intensity, angle of half intensity Peak - emission wavelength*) Op Spectral bandwidth 'O Optical rise time, fall time Optical output pulse duration ± 24 880 ° 900 nm 45 nm tropt, tfopt 6 Input pulse width 217 ns, 1.152 Mbit/s Note: IrDA specification for MIR topt 190 (147.6) Input pulse width tTXD < 80 μs topt 20 tTXD μs Input pulse width tTXD t 80 μs topt 20 85 μs 25 % Optical overshoot 217 40 ns 240 (260) ns ns *) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (>120 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. **) Typ. conditions for If = 420 mA, VCC2 = 3.3 V, Rs = 2.3 :, VCC2 = 5.0 V, Rs = 6.4 : Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 247 TFDU5307 Vishay Semiconductors Recommended Circuit Diagram Used with a clean low impedance power supply the TFDU5307 only needs an external series current limiting resistor. However, depending on the entire system design and board layout, additional components may be required (see figure 1). V IRED R1 VCC R2 C1 GND IRED Anode VCC C2 Ground Vlogic Vlogic SD SD TXD TXD RXD RXD IRED Cathode 18147 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor and this is supply voltage dependent, see derating curve in figure 4, to avoid too high internal power dissipation. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the RXD port. Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V, Tantalum 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 5 V supply voltage: 5.6 : s. text 0.25 W (recommended using two 2.8 :, 0.125 W resistors in series). 3.3 V supply voltage: 2.0 : s. text 0.25 W e.g. 2 x CRCW-1206-2R0-F-RT1 for 3.3 V supply voltage R2 47 :, 0.125 W CRCW-1206-47R0-F-RT1 www.vishay.com 248 Vishay Part Number Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Programming Pulse duration Switching After Power-on the TFDU5307 is in the default short RXD pulse duration mode. Some ENDECs are not able to decode short pulses as valid SIR pulses. Therefore an additional mode with extended pulse duration (same as in standard SIR transceivers) is added in TFDU5307. TFDU5307 is set to the "short output pulse" as default after power on, and after recovering from the shutdown mode (SD being active longer than 1.5 ms). To switch the transceivers from the short RXD pulse duration mode to the long pulse duration mode and vice versa, follow the procedure described below. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. After that TXD is now enabled as normal TXD input and the RXD output is set for the short RXD - pulse duration mode. The timing of the pulse duration changing procedure is quite uncritical. However, the whole change must not take more than 600 μs. See in the spec. "Shutdown Active Time Window for Programming" SD 50 % ts th High: TXD 50 % Low: Setting to the ENDEC compatibility mode with an RXD pulse duration of 2 μs 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns. After that TXD is enabled as normal TXD input and the RXD output is set for the longer RXD - pulse duration mode. Setting back to the default mode with a 400 ns pulse duration 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. Document Number 82616 Rev. 1.5, 07-Apr-06 400 ns 50 % 2 μs 18150 Figure 2. Timing Diagram for changing the output pulse duration Simplified Method Setting the device to the long pulse duration is simply applying a short active (less than 600 μs) pulse to SD. In any case a short SD pulse will force the device to leave the default mode and go the compatibility mode. Vice versa applying a 1.5 ms (minimum) pulse at SD will cause the device to go back to the default mode by activating a power-on-reset and setting the device to the default short pulse mode. This simplified method takes more time but may be easier to handle. www.vishay.com 249 TFDU5307 Vishay Semiconductors Table 2. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitter Operation high < 600 μs x x weakly pulled (500 k:) to VCC1 0 Time window for pulse duration setting high > 1.5 ms x x weakly pulled (500 k:) to VCC1 0 Shutdown low high x low (active) Ie Transmitting high > 80 ms x high inactive 0 Protection is active low <4 high inactive 0 Ignoring low signals below the IrDA defined threshold for noise immunity low > Minimum irradiance Ee < Maximum irradiance Ee low (active) 0 Response to an IrDA compliant optical input signal low > Maximum irradiance Ee undefined 0 Overload conditions can cause unexpected outputs Recommended Solder Profiles Solder Profile for Sn/Pb Soldering Temperature (°C) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 2...4 °C/s 0 50 19535 100 150 200 250 300 350 Time/s Figure 3. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFDU5307 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 4 and 5 are VISHAY's recommended profiles for use with the TFDU5307 transceivers. For more www.vishay.com 250 Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Current Derating Diagram 275 T ≥ 255 °C for 10 s....30 s 250 225 Tpeak = 260 °C T ≥ 217 °C for 70 s max 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 90 2 °C...3 °C/s 50 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 4. Solder Profile, RSS Recommendation Ambient Temperature (˚C) Temperature/°C 200 Figure 6 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 : is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. 85 80 75 70 65 60 55 280 50 2.0 Tpeak = 260 °C max 260 240 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % 220 200 Temperature/°C 180 < 4 °C/s 160 Figure 6. Temperature Derating Diagram 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 5. RTS Recommendation Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 251 TFDU5307 Vishay Semiconductors TFDU5307 - TinyFace (Universal) Package (Dimensions in mm) (Mechanical Dimensions) 18100 www.vishay.com 252 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 Document Number 82616 Rev. 1.5, 07-Apr-06 W3 max. www.vishay.com 253 TFDU5307 Vishay Semiconductors Tape Dimensions in mm 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 7. Tape drawing, TFDU5307 for top view mounting www.vishay.com 254 Document Number 82616 Rev. 1.5, 07-Apr-06 TFDU5307 Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 8. Tape drawing, TFDU5307 for side view mounting Document Number 82616 Rev. 1.5, 07-Apr-06 www.vishay.com 255 Vishay Semiconductors www.vishay.com 256 Contents TFBS6711..............................258 TFBS6712..............................270 TFDU6102 ............................. 282 TFDU6103 ............................. 295 FIR TFDU6300 ............................. 308 TFDU6301 ............................. 321 TFBS6614..............................334 (9.6 kbit/s to 4 Mbit/s) www.vishay.com 257 TFBS6711 Vishay Semiconductors Low Profile Fast Infrared Transceiver (FIR, 4 Mbit/s) for IrDA® Applications Description The TFBS6711 is the smallest FIR transceiver available. It is a low profile and low-power IrDA transceiver. Compliant to IrDA’s Physical Layer specification, the TFBS6711 supports data transmission rates from 9.6 kbit/s to 4 Mbit/s with a typical link distance of 50 cm. It also enables mobile phones and PDAs to function as universal remote controls for televisions, DVDs and other home appliances. The TFBS6711 emitter covers a range of 6.5 meters with common remote control receivers. Integrated within the transceiver module is a PIN photodiode, an infrared emitter, and a low-power control IC. The TFBS6711 can be completely shutdown, achieving very low power consumption. The TFBS6711 has an I/O voltage 20208 related to the supply voltage while TFBS6712 supports low voltage logic of 1.8 V allowing direct connection to a microcontroller’s I/Os operating at 1.8 V. Features • • • • • • • • • • • • Lowest profile: 1.9 mm Smallest footprint: 6.0 mm x 3.05 mm Surface mount package e4 IrDA transmit distance: 50 cm typical Best Remote Control distance: t6.5 m on-axis Fast data rates: from 9.6 kbit/s to 4 Mbit/s Low shutdown current: 0.01 μA Operating Voltage: 2.4 V to 3.6 V Reduced pin count: 6 pins I/O voltage equal to the supply voltage Pin compatibility: TFBS4711 and TFBS5711 Integrated EMI Protection no external shield required • • • • IEC 60825-1 Class 1, Eye Safe Qualified for Lead (Pb)-free and Sn/Pb processing Compliant to IrDA Physical Layer Specification Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US patent No. 6,157,476 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • High-speed data transfer using infrared wireless communication • Mobile phones • Camera phones • • • • PDAs MP3 Players Digital Cameras IrDA Adapters or Dongles Package Options Ordering Information Part Number Qty / Reel or Tube Description and Remarks TFBS6711-TR1 1000 pcs Oriented in carrier tape for side view surface mounting TFBS6711-TR3 2500 pcs Oriented in carrier tape for side view surface mounting Note: A version oriented in the carrier tape for top view mounting is available on request www.vishay.com 258 Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 SD Logic & Controlled Driver Control TXD GND 19298 Figure 1. Functional Block Diagramm Pin Description Pin Number Function Description 1 VCC2, IRED Anode IRED anode to be externally connected to VCC2. For higher voltages as 3.6 V an external resistor might be necessary for reducing the internal power dissipation. See derating curves. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled V CC1 - supply I/O Active 2 TXD Transmit Data Input I HIGH 3 RXD Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS load. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. The RXD output echos the TXD input during transmission. O LOW 4 SD Shutdown, also used for dynamic mode switching I HIGH 5 VCC1 Supply voltage 6 GND Ground TFBS6711 Weight: 50 mg PIN 1 19428 Figure 2. Pinning Document Number 84676 Rev. 1.2, 03-Jul-06 www.vishay.com 259 TFBS6711 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 Typ. 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6.5 V Input currents For all Pins, Except IRED Anode Pin 10 mA Output sinking current Power dissipation PD 25 mA 500 mW 125 °C Ambient temperature range (operating) Tamb - 25 + 85 °C Storage temperature range Tstg - 25 + 85 °C Junction temperature TJ Soldering temperature Average output current Repetitive pulse output current IIRED (DC) < 90 μs, ton < 20 % IRED anode voltage Voltage at all inputs and outputs Vin > VCC1 is allowed Virtual source size Method: (1-1/e) encircled energy IIRED (RP) 260 °C 125 mA 600 mA IIREDA - 0.5 6.5 V Vin - 0.5 5.5 d 1.5 V mm Maximum Intensity for Class 1 operation of IEC60825-1 or EN60825-1, edition Jan. 2001 internal limitation to class 1 500 IrDA® specified maximum limit mW/sr Due to the internal limitation measures the device is a “class 1” device. It will not exceed the IrDA® intensity limit of 500 mW/sr Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhY 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s IrDA, the Infrared Data Association, implemented MIR and FIR with IrPHY 1.1, followed by IrPhY 1.2, adding the SIR Low Power Standard. IrPhY 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhY 1.4. A new version of the standard in any case obsoletes the former version. www.vishay.com 260 Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors Electrical Characteristics Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions / Pins Symbol Min VCC 2.4 Typ. Max Unit 3.6 V Transceiver Supply voltage Dynamic supply current Receive mode only. In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. SD = Low, SIR mode ICC 1.7 3 mA SD = Low, MIR/FIR mode ICC 1.9 3.3 mA SD = High T = 25 °C, not ambient light sensitive, detector is disabled in shutdown mode ISD 1 μA SD = High T = 85 °C, not ambient light sensitive ISD 5 μA + 85 °C Output voltage low IOL = 1 mA CLOAD = 15 pF VOL 0.4 V Output voltage high IOH = - 250 μA CLOAD = 15 pF VOH Shutdown supply current Shutdown supply current Operating temperature range TA - 25 0.9 x VCC V RRXD 400 600 k: Input voltage low (TXD, SD) VIL - 0.5 0.5 V Input voltage high (TXD, SD) V IH VCC - 0.5 VCC + 0.5 V Input leakage current (TXD, SD) IICH -1 +1 μA 5 pF Internal RXD pull-up Input capacitance (TXD, SD) *) CI 500 0.05 Standard illuminant A **) The typical threshold level is 0.5 x VCC (VCC = 3 V). It is recommended to use the specified min/max values to avoid increased operating/ shutdown currents. Document Number 84676 Rev. 1.2, 03-Jul-06 www.vishay.com 261 TFBS6711 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Minimum irradiance Ee in angular range **) 9.6 kbit/s to 115.2 kbit/s O = 850 nm - 900 nm, VCC = 2.4 V Ee Minimum irradiance Ee in angular range MIR mode 1.152 Mbit/s O = 850 nm - 900 nm, VCC = 2.4 V Ee Minimum irradiance Ee in angular range FIR mode 4 Mbit/s O = 850 nm - 900 nm, VCC = 2.4 V Ee Maximum irradiance Ee in angular range ***) O = 850 nm - 900 nm Ee Min Typ. Max Unit Receiver No detection receiver Input Irradiance (fluorescent light noise suppression) Ee 50 80 mW/m2 (5) (8) (μW/cm2) 100 mW/m2 (10) (μW/cm2) 120 200 mW/m2 (12) (20) (μW/cm2) 5 kW/m2 (500) (mW/cm2) 4 mW/m2 (0.4) (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 10 50 Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 10 50 ns RXD pulse width of output signal, 50%, SIR mode Input pulse length 1.4 Ps < PWopt < 25 μs tPW 1.4 1.8 2.6 μs RXD pulse width of output signal, 50%, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 250 270 ns RXD pulse width of output signal, 50%, FIR mode Input pulse length PWopt = 125 ns, 4 Mbit/s tPW 110 140 ns RXD pulse width of output signal, 50%, FIR mode Input pulse length PWopt = 250 ns, 4 Mbit/s tPW 225 275 ns RXD output jitter, leading edge Input irradiance = 150 mW/m2, 4 Mbit/s 1.152 Mbit/s d115.2 kbit/s After completion of shutdown programming sequence Power on delay 20 ns 40 ns 350 ns 500 μs 100 μs Receiver start up time Latency tL ns Note: All timing data measured with 4 Mbit/s are measured using the IrDA® FIR transmission header. The data given here are valid 5 μs after starting the preamble. **) IrDA sensitivity definition: Minimum Irradiance E In Angular Range, power per unit area. The receiver must meet the BER specie fication while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). www.vishay.com 262 Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors Optoelectronic Characteristics, continued Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Typ. Max Unit IRED operating current, switched current control Parameter For 3.3-V operation no external resistor is needed. Test Conditions ID 330 440 600 mA Output leakage IRED current VCC = VIRED = 3.3 V, TXD = Low IIRED -1 1 μA Output radiant intensity, s. figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0° TXD = High, SD = Low, R1 = 1: Ie 45 115 300 mW/sr Output radiant intensity, s. figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0°, 15° TXD = High, SD = Low, R1 = 1: Ie 25 75 300 mW/sr Output radiant intensity VCC1 = 3.6 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr r24 D Output radiant intensity, angle of half intensity Peak - emission wavelength Optical rise time, Optical fall time ° Op 880 900 nm tropt, tfopt 10 40 ns Optical output pulse duration Input pulse width 217 ns, 1.152 Mbit/s topt 200 217 230 ns Optical output pulse duration Input pulse width 125 ns, 4 Mbit/s topt 116 125 134 ns Optical output pulse duration Input pulse width 250 ns, 4 Mbit/s topt 241 250 259 ns Optical output pulse duration Input pulse width t < 80 μs Input pulse width t t 80 μs topt topt 85 μs μs 25 % Optical overshoot Document Number 84676 Rev. 1.2, 03-Jul-06 t 20 www.vishay.com 263 TFBS6711 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS6711 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 3). V CC2 V CC1 GND IRED Anode R1 R2 C1 V CC C3 C2 Ground SD SD TXD TXD RXD RXD 19299 In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V Vishay part#: 293D 475X9 016B C2 0.1 μF, Ceramic Vishay part#: VJ1206 Y 104 J XXMT R1 3.3 V supply voltage: no resistor is necessary, the internal controller is able to control the current R2 4.7 :, 0.125 W Figure 3. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (RXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. www.vishay.com 264 I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors Mode Switching The TFBS6711 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. TXD is now enabled as normal TXD input for the lower bandwidth mode. 50 % SD Setting to the High Bandwidth Mode (0.576 Mbit/s to 4 Mbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic “LOW”. The hold time of TXD is limited by the maximum allowed pulse length. TXD is now enabled as normal TXD input for the high bandwidth mode. ts th High : FIR TXD 50 % 50 % Low : SIR 14873 Figure 4. Mode Switching Timing Diagram Truth table Inputs Outputs SD TXD Input irradiance mW/m2 RXD Transmitter high x x weakly pulled (500 k:) high 0 Ie low high x high low high > 80μs x high 0 low low <4 high 0 low low > Min. irradiance Ee in angular range < Max. irradiance Ee in angular range low (active) 0 low low > Max. irradiance Ee in angular range x 0 Document Number 84676 Rev. 1.2, 03-Jul-06 www.vishay.com 265 TFBS6711 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 5. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS6711 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 6 is VISHAY's recommended profiles for use with the TFBS6711 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 6. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 266 Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors TFBS4711, TFBS5711, TFBS6711, and TFBS6712 Package (Mechanical Dimensions) 19612 Figure 7. Package drawing, tolerances: Height + 0.1, - 0.2 mm, otherwise ± 0.2 mm if not indicated 19301 19728 Soldering footprint: Side view Soldering footprint: Top view Figure 8. Soldering footprints Design Rules for Optical Windows For optical windows see the application note on the web http://www.vishay.com/docs/82506/82506.pdf. Document Number 84676 Rev. 1.2, 03-Jul-06 www.vishay.com 267 TFBS6711 Vishay Semiconductors Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm W3 max. mm 16 330 50 16.4 22.4 15.9 19.4 Figure 9. Reel dimensions [mm] 19303 Drawing-No.: 9.700-5294.01-4 Issue: prel. copy; 24.11.04 Figure 10. Tape dimensions [mm] TFBS6711-TT3 www.vishay.com 268 Document Number 84676 Rev. 1.2, 03-Jul-06 TFBS6711 Vishay Semiconductors 19304 Drawing-No.: 9.700-5295.01-4 Issue: prel. copy; 24.11.04 Figure 11. Tape dimensions [mm] TFBS6711-TR3 Document Number 84676 Rev. 1.2, 03-Jul-06 www.vishay.com 269 TFBS6712 Vishay Semiconductors Low Profile Fast Infrared Transceiver (FIR, 4 Mbit/s) for IrDA® Applications with Low voltage Logic (1.8 V) Description The TFBS6712 is the smallest FIR transceiver available. It is a low profile and low-power IrDA transceiver. Compliant to IrDA’s Physical Layer specification, the TFBS6712 supports data transmission rates from 9.6 kbit/s to 4 Mbit/s with a typical link distance of 50 cm. It also enables mobile phones and PDAs to function as universal remote controls for televisions, DVDs and other home appliances. The TFBS6712 emitter covers a range of 6.5 meters with common remote control receivers. Integrated within the transceiver module is a PIN photodiode, an infrared emitter, and a low-power control IC. The TFBS6712 can be completely shutdown, achieving very low power consumption. This type is adapted to 20208 work with a low logic I/O voltage of 1.8 V. For operation with VCC as logic voltage base TFBS6711 is available with otherwise same performance. Features • • • • • • • • • • • • Lowest profile: 1.9 mm Smallest footprint: 6.0 mm x 3.05 mm Surface mount package e4 IrDA transmit distance: 50 cm typical Best Remote Control distance: t6.5 m on-axis Fast data rates: from 9.6 kbit/s to 4 Mbit/s Low shutdown current: 0.01 μA Operating Voltage: 2.4 V to 3.6 V Reduced pin count: 6 pins I/O voltage equal to the supply voltage Pin compatibility: TFBS4711 and TFBS5711 Integrated EMI Protection no external shield required • • • • IEC 60825-1 Class 1, Eye Safe Qualified for Lead-free and Sn/Pb processing Compliant to IrDA Physical Layer Specification Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US patent No. 6,157,476 • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • High-speed data transfer using infrared wireless communication • Mobile phones • Camera phones • • • • PDAs MP3 Players Digital Cameras IrDA Adapters or Dongles Package Options Ordering Information Part Number Qty / Reel or Tube Description and Remarks TFBS6712-TR1 1000 pcs Oriented in carrier tape for side view surface mounting TFBS6712-TR3 2500 pcs Oriented in carrier tape for side view surface mounting Note: A version oriented in the carrier tape for top view mounting is available on request www.vishay.com 270 Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 SD Logic & Controlled Driver Control TXD GND 19298 Figure 1. Functional Block Diagramm Pin Description Pin Number Function Description 1 VCC2, IRED Anode IRED anode to be externally connected to VCC2. For higher voltages as 3.6 V an external resistor might be necessary for reducing the internal power dissipation. See derating curves. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled V CC1 - supply I/O Active 2 TXD Transmitter Data Input, adapted to 1.8-V logic I HIGH 3 RXD Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS load. No external pull-up or pull-down resistor is required. Adapted to low i/O voltage 1.8-V logic. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode O LOW 4 SD Shutdown, also used for dynamic mode switching I HIGH 5 VCC1 Supply voltage 6 GND Ground TFBS6712 Weight: 50 mg PIN 1 19428 Figure 2. Pinning Document Number 84674 Rev. 1.1, 25-Sep-06 www.vishay.com 271 TFBS6712 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin, GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 Typ. 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6.5 V Input currents For all pins, except IRED anode pin 10 mA Output sinking current Power dissipation PD 25 mA 500 mW 125 °C Ambient temperature range (operating) Tamb - 25 + 85 °C Storage temperature range Tstg - 25 + 85 °C Junction temperature TJ Soldering temperature Average output current Repetitive pulse output current IIRED (DC) < 90 Ps, ton < 20 % IRED anode voltage Voltage at all inputs and outputs Vin > VCC1 is allowed Virtual source size Method: (1-1/e) encircled energy IIRED (RP) 260 °C 125 mA 600 mA VIREDA - 0.5 6.5 V Vin - 0.5 5.5 d 1.5 V mm Maximum intensity for Class 1 operation of IEC60825-1 or EN60825-1, edition Jan. 2001 internal limitation to class 1 500 IrDA® specified maximum limit mW/sr Due to the internal limitation measures the device is a “class 1” device. It will not exceed the IrDA® intensity limit of 500 mW/sr Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhY 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s IrDA, the Infrared Data Association, implemented MIR and FIR with IrPHY 1.1, followed by IrPhY 1.2, adding the SIR Low Power Standard. IrPhY 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhY 1.4. A new version of the standard in any case obsoletes the former version. www.vishay.com 272 Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors Electrical Characteristics Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min VCC 2.4 Typ. Max Unit 3.6 V Transceiver Supply voltage range Dynamic supply current Receive mode only. In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. SD = Low, SIR mode ICC 1.7 3 mA SD = Low, MIR/FIR mode ICC 1.9 3.3 mA Shutdown supply current SD = High T = 25 °C, not ambient light sensitive, detector is disabled in shutdown mode ISD 1 μA Shutdown supply current SD = High T = 85 °C, not ambient light sensitive ISD 5 μA + 85 °C Output voltage “Low” IOL = 1 mA CLOAD = 15 pF VOL 0.4 V Output voltage “High” IOH = - 250 μA CLOAD = 15 pF VOH 2 V 600 k: 0.5 V Operating temperature range TA - 25 1.6 1.8 500 RRXD 400 Input voltage “Low” (TXD, SD) VIL - 0.5 Input voltage “High” (TXD, SD) VIH 1.5 1.8 2.1 V Input leakage current (TXD, SD)*) Vin > 1.6 V Input capacitance (TXD, SD) IICH -1 0.05 +1 μA 5 pF Internal RXD pull-up CI *) The typical threshold level is 0.5 x V CC (at VCC = 3V). It is recommended to use the specified min/max values to avoid increased operating/shutdown currents. Document Number 84674 Rev. 1.1, 25-Sep-06 www.vishay.com 273 TFBS6712 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Minimum irradiance Ee in angular range**) 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm, Vcc = 2.4 V Ee Minimum irradiance Ee in angular range MIR mode 1.152 Mbit/s O = 850 nm to 900 nm, Vcc = 2.4 V Ee Minimum irradiance Ee in angular range FIR mode 4 Mbit/s O = 850 nm to 900 nm, Vcc = 2.4 V Ee Maximum irradiance Ee in angular range***) O = 850 nm to 900 nm Ee Min Typ. Max Unit Receiver No detection receiver Input Irradiance (fluorescent light noise suppression) Ee 50 80 mW/m2 (5) (8) (μW/cm2) 100 mW/m2 (10) (μW/cm2) 120 200 mW/m2 (12) (20) (μW/cm2) 5 kW/m2 (500) (mW/cm2) 4 mW/m2 (0.4) (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 10 50 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 10 50 ns RXD pulse width of output signal, 50%, SIR mode Input pulse length 1.4 Ps < PWopt < 25 μs tPW 1.4 1.8 2.6 μs RXD pulse width of output signal, 50%, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 250 270 ns RXD pulse width of output signal, 50%, FIR mode Input pulse length PWopt = 125 ns, 4 Mbit/s tPW 110 140 ns RXD pulse width of output signal, 50%, FIR mode Input pulse length PWopt = 250 ns, 4 Mbit/s tPW 225 275 ns RXD output jitter, leading edge Input irradiance = 150 mW/m2, 4 Mbit/s 1.152 Mbit/s d115.2 kbit/s After completion of shutdown programming sequence Power on delay 20 40 350 ns ns ns 500 μs 100 μs Receiver start up time Latency tL Note: All timing data measured with 4 Mbit/s are measured using the IrDA® FIR transmission header. The data given here are valid 5 μs after starting the preamble. **) IrDA sensitivity definition: Minimum Irradiance E In Angular Range, power per unit area. The receiver must meet the BER specie fication while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical power delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). www.vishay.com 274 Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors Optoelectronic Characteristics, continued Tamb = 25 °C, VCC = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Min Typ. Max Unit 440 600 mA Transmitter IRED operating current, switched current control See derating curve. For 3.3-V operation no external resistor is needed. ID 330 Output leakage IRED current VCC = VIRED = 3.3 V, TXD = Low IIRED -1 1 μA Output radiant intensity, see figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0° TXD = High, SD = Low, R1 = 1: Ie 45 115 300 mW/sr Output radiant intensity, see figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0°, 15° TXD = High, SD = Low, R1 = 1: Ie 25 75 300 mW/sr Output radiant intensity VCC = 3.6 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr r24 D Output radiant intensity, angle of half intensity Peak - emission wavelength Optical rise time, Optical fall time ° Op 880 900 nm tropt, tfopt 10 40 ns Optical output pulse duration Input pulse width 217 ns, 1.152 Mbit/s topt 200 217 230 ns Optical output pulse duration Input pulse width 125 ns, 4 Mbit/s topt 116 125 134 ns Optical output pulse duration Input pulse width 250 ns, 4 Mbit/s topt 241 250 259 ns Optical output pulse duration Input pulse width t < 80 μs Input pulse width t t 80 μs topt topt 85 μs μs 25 % Optical overshoot Document Number 84674 Rev. 1.1, 25-Sep-06 t 20 www.vishay.com 275 TFBS6712 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS6712 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 3). VCC2 VCC1 GND R1 R2 C1 IRED Anode VCC C2 Ground SD SD TXD TXD RXD RXD 19430 Figure 3. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. www.vishay.com 276 A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see tavle under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V Vishay part#: 293D 475X9 016B C2 0.1 μF, Ceramic Vishay part#: VJ1 206 Y 104 J XXMT R1 3.3 V supply voltage: no resistor necessary, the internal controller is able to control the current R2 4.7 :, 0.125 W I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors Mode Switching The TFBS6712 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. Setting to the High Bandwidth Mode (0.576 Mbit/s to 4 Mbit/s) Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. TXD is now enabled as normal TXDinput for the lower bandwidth mode. 50 % SD 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic “LOW”. The hold time of TXD is limited by the maximum allowed pulse length. TXD is now enabled as normal TXD input for the high bandwidth mode. ts th High : FIR TXD 50 % 50 % Low : SIR 14873 Figure 4. Mode Switching Timing Diagram Truth table Inputs Outputs SD TXD Optical input Irradiance [mW/m2] RXD Transmitter high x x weakly pulled (500 k:) high 0 Ie low high x high low high > 80μs x high 0 low low <4 high 0 low low > Min. irradiance Ee in angular range < Max. irradiance Ee in angular range low (active) 0 low low > Max. irradiance Ee in angular range x 0 Document Number 84674 Rev. 1.1, 25-Sep-06 www.vishay.com 277 TFBS6712 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 5. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS6712 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 6 is VISHAY's recommended profiles for use with the TFBS6712 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 6. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 278 Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors TFBS4711, TFBS5711, TFBS6711, and TFBS6712 Package (Mechanical Dimensions) 19612 Figure 7. Package drawing, tolerances: Height + 0.1, - 0.2 mm, otherwise ± 0.2 mm if not indicated 19301 19728 Soldering footprint: Side view Soldering footprint: Top view Figure 8. Soldering footprints Design Rules for Optical Windows For optical windows see the application note on the web http://www.vishay.com/docs/82506/82506.pdf. Document Number 84674 Rev. 1.1, 25-Sep-06 www.vishay.com 279 TFBS6712 Vishay Semiconductors Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm W3 max. mm 16 330 50 16.4 22.4 15.9 19.4 Figure 9. Reel dimensions [mm] 19303 Drawing-No.: 9.700-5294.01-4 Issue: prel. copy; 24.11.04 Figure 10. Tape dimensions [mm] TFBS6712-TT3 www.vishay.com 280 Document Number 84674 Rev. 1.1, 25-Sep-06 TFBS6712 Vishay Semiconductors 19304 Drawing-No.: 9.700-5295.01-4 Issue: prel. copy; 24.11.04 Figure 11. Tape dimensions [mm] TFBS6712-TR3 Document Number 84674 Rev. 1.1, 25-Sep-06 www.vishay.com 281 TFDU6102 Vishay Semiconductors Fast Infrared Transceiver Module (FIR, 4 Mbit/s) for 2.7 V to 5.5 V Operation Description The TFDU6102 is a low-power infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA® speeds up to 4.0 Mbit/s (FIR), and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a lowpower CMOS control IC to provide a total front-end solution in a single package. Vishay FIR transceivers are available in different package options, including this BabyFace package (TFDU6102). This wide selection provides flexibility for a variety of applications and space constraints. The transceivers are capable of directly interfacing with a wide variety of I/O devices which perform the 20110 modulation/demodulation function, including National Semiconductor’s PC87338, PC87108 and PC87109, SMC’s FDC37C669, FDC37N769 and CAM35C44, and Hitachi’s SH3. TFDU6102 has a tri-state output and is floating in shut-down mode with a weak pull-up. Features • Supply voltage 2.7 V to 5.5 V, operating idle current (receive mode) < 3 mA, shutdown current < 5 μA over full temperature range e3 • Surface mount package, top and side view, 9.7 mm x 4.7 mm x 4.0 mm • Operating temperature - 25 °C to 85 °C • Storage temperature - 40 °C to 100 °C • Transmitter wavelength typ. 886 nm, supporting IrDA and Remote Control • IrDA compliant, link distance > 1 m, ± 15°, window losses are allowed to still be inside the IrDA spec. • Remote Control range > 8 m, typ. 22 m • ESD > 4000 V (HBM) • Latchup > 200 mA • EMI immunity > 550 V/m for GSM frequency and other mobile telephone bands/ (700 MHz to 2000 MHz, no external shield) • Split power supply, LED can be driven by a separate power supply not loading the regulated supply. U.S. Pat. No. 6,157,476 • Tri-state-Receiver Output, floating in shut down with a weak pull-up • Eye safety class 1 (IEC60825-1, ed. 2001), limited LED on-time, LED current is controlled, no single fault to be considered • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Digital still and video cameras • Printers, fax machines, photocopiers, screen projectors • Telecommunication products (cellular phones, pagers) • Internet TV Boxes, video conferencing systems • External infrared adapters (dongles) • Medical an industrial data collection Parts Table Part Description Qty / Reel TFDU6102-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU6102-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs www.vishay.com 282 Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 Logic & SD Controlled Driver Control TXD IRED C GND 18468 Pinout Definitions: TFDU6102 weight 200 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 "U" Option BabyFace (Universal) MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s IRED Detector MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. 1 2 3 4 5 6 7 8 Note: We apologize to use sometimes in our documentation the abbreviation LED and the word Light Emitting Diode instead of 17087 Infrared Emitting Diode (IRED) for IR-emitters. That is by definition wrong; we are here following just a bad trend. Typical values are for design aid only, not guaranteed nor subject to production testing and may vary with time. Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 283 TFDU6102 Vishay Semiconductors Pin Description Pin Number Function Description 1 VCC2 IRED Anode Connect IRED anode directly to V CC2. For voltages higher than 3.6 V an external resistor might be necessary for reducing the internal power dissipation. An unregulated separate power supply can be used at this pin. I/O Active 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 TXD This input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 80 μs. When used in conjunction with the SD pin, this pin is also used to receiver speed mode. I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. O LOW 5 SD Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the TXD pin is sampled and used to set receiver low bandwidth (TXD = Low, SIR) or high bandwidth (TXD = High, MIR and FIR) mode. Will be overwritten by the mode pin input, which must float, when dynamic programming is used. I HIGH 6 VCC1 Supply Voltage 7 Mode HIGH: High speed mode, MIR and FIR; LOW: Low speed mode, SIR only (see chapter "Mode Switching"). Must float, when dynamic programming is used. I Mode The mode pin can also be used to indicate the dynamically programmed mode. The maximum load is limited to 50 pF. High indicates FIR/MIR-, low indicates SIR-mode O GND Ground 8 Absolute Maximum Ratings Reference point Ground Pin 8, unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 +6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 + 6.5 V Input currents For all pins, except IRED anode pin 10 mA Output sinking current Power dissipation See derating curve, figure 5 Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature < 90 μs, ton < 20 % IRED anode voltage Voltage at all inputs and outputs Vin > VCC1 is allowed Load at mode pin when used as mode indicator www.vishay.com 284 25 mA 500 mW 125 °C Tamb - 25 + 85 °C Tstg - 25 + 85 °C 260 °C IIRED (DC) 125 mA IIRED (RP) 600 mA See recommended solder profile (see figure 4) Average output current Repetitive pulse output current PD Typ. VIREDA VIN - 0.5 + 6.5 V 5.5 V 50 pF Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors Eye safety information Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Typ. Virtual source size Parameter Method: (1 - 1/e) encircled energy d 2.5 2.8 Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie *) Test Conditions Max Unit mm *) (500)**) mW/sr Max Unit Due to the internal limitation measures the device is a "class1" device **) IrDA specifies the max. intensity with 500 mW/sr Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC 2.7 Typ. 5.5 V 3 mA Supply current (Idle)*) SD = Low, Ee = 0 klx ICC 2 Supply current (Idle)*) SD = Low, Ee = 1 klx **) ICC 2 3 mA Shutdown supply current SD = High, Mode = Floating Ee = 0 klx ISD 2.0 μA SD = High, Mode = Floating ISD 2.5 μA SD = High, T = 85 °C, Mode = Floating, not ambient light sensitive ISD 5 μA + 85 °C Output voltage low IOL = 1 mA, Cload = 15 pF VOL 0.4 V Output voltage high IOH = 500 μA, Cload = 15 pF VOH 0.8 x VCC IOH = 250 μA, Cload = 15 pF VOH 0.9 x VCC Ee = 1 klx **) Operating temperature range TA - 25 V V Output RXD current limitation high state Short to Ground 20 mA Output RXD current limitation low state Short to VCC1 20 mA RXD to VCC1 impedance SD = High RRXD 400 600 k: VIL - 0.5 0.5 V VIH VCC - 0.5 VCC + 0.5 V Input leakage current (TXD, SD) IL - 10 + 10 μA Input leakage current Mode IICH -2 +2 μA Input capacitance (TXD, SD, Mode) CIN 5 pF Input voltage low (TXD, SD, Mode) Input voltage high (TXD, SD, Mode) CMOS level ***) 500 *) Receive mode only. In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. **) Standard Illuminant A. ***) The typical threshold level is 0.5 x VCC2. It is recommended to use the specified min/max values to avoid increased operating current. Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 285 TFDU6102 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typ. Max Unit Minimum irradiance Ee in angular range **) SIR mode Parameter 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm Test Conditions Symbol Ee Min 25 (2.5) 35 (3.5) mW/m2 Minimum irradiance Ee in angular range, MIR mode 1.152 Mbit/s O = 850 nm to 900 nm Ee 65 (6.5) Minimum irradiance Ee inangular range, FIR mode 4.0 Mbit/s O = 850 nm to 900 nm Ee Maximum irradiance Ee in angular range ***) O = 850 nm to 900 nm Ee Maximum no detection irradiance *) Rise time of output signal 80 (8.0) (μW/cm2) mW/m2 (μW/cm2) 90 (9.0) 5 (500) mW/m2 (μW/cm2) kW/m2 (mW/cm2) Ee 4 (0.4) 10 % to 90 %, 15 pF tr (RXD) 10 40 Fall time of output signal 90 % to 10 %, 15 pF tf (RXD) 10 40 RXD pulse width of output signal, 50 %, SIR mode Input pulse length 1.4 μs < PWopt < 25 Ps tPW Input pulse length 1.4 μs < PWopt < 25 μs, tPW 1.5 1.8 2.6 μs 250 270 ns mW/m2 (μW/cm2) 2.1 ns ns μs - 25 °C < T < 85 °C ****) RXD pulse width of output signal, 50 %, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 125 ns, 4.0 Mbit/s tPW 100 140 ns Input pulse length PWopt = 250 ns, 4.0 Mbit/s tPW 225 275 ns Input irradiance = 100 mW/m2, 4.0 Mbit/s 20 ns Input irradiance = 100 mW/m2, 1.152 Mbit/s 40 ns Input irradiance = 100 mW/m2, 576 kbit/s 80 ns Input irradiance = 100 mW/m2, d 115.2 kbit/s 350 ns After completion of shutdown programming sequence Power on delay 500 μs 300 μs Stochastic jitter, leading edge Receiver start up time Latency tL 170 Note: All timing data measured with 4 Mbit/s are measured using the IrDA® FIR transmission header. The data given here are valid 5 μs after starting the preamble. *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER). For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). ****) Retriggering once during applied optical pulse may occur. www.vishay.com 286 Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions See derating curve (fig. 5). For 3.3 V operations no external resistor needed. For 5 V application that might be necessary depending on operating temperature range. Symbol Min Typ. Max Unit ID 500 550 600 mA 1 μA 170 350 mW/sr 0.04 mW/sr IIRED -1 Output radiant intensity recommended application circuit D = 0°, 15° TXD = High, SD = Low, VCC1 = VCC2 = 3.3 V Internally current-controlled, no external resistor Ie 120 Output radiant intensity VCC1 = 5.0 V, D = 0°, 15° TXD = Low or SD = High, (Receiver is inactive as long as SD = High) Ie Output leakage IRED current D Output radiant intensity, angle of half intensity Peak - emission wavelength Op Spectral bandwidth 'O Optical rise time, fall time Optical output pulse duration ± 24 880 ° 900 40 nm nm tropt, tfopt 10 40 ns Input pulse width 217 ns, 1.152 Mbit/s topt 207 217 227 ns Input pulse width 125 ns, 4.0 Mbit/s topt 117 125 133 ns Input pulse width 250 ns, 4.0 Mbit/s topt 242 250 258 ns Input pulse width topt tTXD μs 0.1 Ps < tTXD < 100 μs *) Input pulse width tTXD t 100 μs *) Optical overshoot topt 23 100 μs 25 % *) Typically the output pulse duration will follow the input pulse duration t and will be identical in length t. However, at pulse duration larger than 100 μs the optical output pulse duration is limited to 100 μs. This pulse duration limitation can already start at 23 μs. Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 287 TFDU6102 Vishay Semiconductors Recommended Circuit Diagram Vishay Semiconductors transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD, Mode) and the output RXD should be directly (DC) coupled to the I/O circuit. VCC2 R1 VCC1 R2 C1 C3 IRED Anode VCC C2 GND Ground Mode Mode SD SD TXD TXD RXD RXD IRED Cathode 18469 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and reduces the influence of the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for higher operating voltages and elevated temperatures, see derating curve in figure 5, to avoid too high internal power dissipation. The capacitors C2 and C3 combined with the resistor R2 (as the low pass filter) is smoothing the supply voltage VCC1. R2, C1, C2, and C3 are optional and dependent on the quality of the supply voltages VCC1 and VCC2 and injected noise. An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 and C3 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 and C3 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current is rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Wienfield Hill, 1989, Cambridge University Press, ISBN: 0 521 37095 7. Table 1. Recommended Application Circuit Components Component Recommended Value C1, C3 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 5 V supply voltage: 2 : , 0.25 W ( recommended using two 1 :, 0.125 W resistor in series) 3.3 V supply voltage: no resistors necessary, the internal controller is able to control the current e.g. 2 x CRCW-1206-1R0-F-RT1 R2 10 :, 0.125 W CRCW-1206-10R0-F-RT1 www.vishay.com 288 Vishay Part Number Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU6102 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below or selected by setting the Mode Pin. The Mode Pin can be used to statically set the mode (Mode Pin: LOW: SIR, HIGH: 0.576 Mbit/s to 4.0 Mbit/s). If not used or in standby mode, the mode input should float or should not be loaded with more than 50 pF. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. After that TXD is enabled as normal TXD input and the transceiver is set for the high bandwidth (576 kbit/s to 4 Mbit/s) mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. After that TXD is enabled as normal TXD input and the transceiver is set for the lower bandwidth (9.6 kbit/s to 115.2 kbit/s) mode. 50 % SD ts th High : FIR TXD 50 % 50 % Low : SIR Setting to the High Bandwidth Mode (0.576 Mbit/s to 4.0 Mbit/s) 14873 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. Figure 2. Mode Switching Timing Diagram Table 2. Truth table Inputs Outputs SD TXD Optical input Irradiance mW/m2 RXD Transmitter high x x weakly pulled (500 k:) to VCC1 0 low high x low (active) Ie high > 80 μs x high 0 low <4 high 0 low > Min. irradianceEe < Max. irradiance Ee low (active) 0 low > Max. irradiance Ee x 0 Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 289 TFDU6102 Vishay Semiconductors Recommended Solder Profiles for TFDU6102 Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 19535 100 150 200 250 300 350 Figure 3. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 4. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU6102 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 4 and 5 are VISHAY's recommended profiles for use with the TFDU6102 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 5. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. www.vishay.com 290 Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors Current Derating Diagram 90 Ambient Temperature (˚C) Figure 5 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 : is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 6. Temperature Derating Diagram Package Dimensions Figure 7. Package drawing TFDU6102, dimensions in mm, tolerance ± 0.2 mm if not otherwise mentioned Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 291 TFDU6102 Vishay Semiconductors Solder Footprint 20111 Figure 8. Solder footprint for top and side view mounting TFDU6102, dimensions in mm, tolerance ± 0.2 mm if not otherwise mentioned Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm W3 max. mm 24 330 60 24.4 30.4 23.9 27.4 Figure 9. Reel dimensions [mm] www.vishay.com 292 Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6102 Vishay Semiconductors Tape Dimensions 19824 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 10. Tape drawing, TFDU6102 for top view mounting, tolerance ± 0.1 mm Document Number 82550 Rev. 1.7, 21-Aug-06 www.vishay.com 293 TFDU6102 Vishay Semiconductors 19875 Drawing-No.: 9.700-5297.01-4 Issue: 1; 04.08.05 Figure 11. Tape drawing, TFDU6102 for side view mounting, tolerance ± 0.1 mm www.vishay.com 294 Document Number 82550 Rev. 1.7, 21-Aug-06 TFDU6103 Vishay Semiconductors Fast Infrared Transceiver Module (FIR, 4 Mbit/s) for 2.4 V to 5.5 V Operation Description The TFDU6103 is a low-power infrared transceiver module compliant to the latest IrDA physical layer standard for fast infrared data communication, supporting IrDA speeds up to 4.0 Mbit/s (FIR), and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power CMOS control IC to provide a total front-end solution in a single package. Vishay FIR transceivers are available in different package options, including this BabyFace package (TFDU6103). This wide selection provides flexibility for a variety of applications and space constraints. The transceivers are capable of directly interfacing with a wide variety of I/O devices which perform the 20110 modulation/ demodulation function, including National Semiconductor’s PC87338, PC87108 and PC87109, SMC’s FDC37C669, FDC37N769 and CAM35C44, and Hitachi’s SH3. TFDU6103 has a tristate output and is floating in shut-down mode with a weak pull-up. Features • Supply voltage 2.4 V to 5.5 V, operating idle current (receive mode) < 3.3 mA, shutdown current < 1 μA over full temperature range e3 • Surface mount package, top and side view, 9.7 mm x 4.7 mm x 4.0 mm • Operating temperature - 25 °C to 85 °C • Transmitter wavelength typ. 886 nm, supporting IrDA® and Remote Control • IrDA® compliant, link distance > 1 m, ± 15°, window losses are allowed to still be inside the IrDA® spec. • Remote Control range > 8 m, typ. 22 m • ESD > 1 kV • Latchup > 100 mA • EMI immunity > 550 V/m for GSM frequency and other mobile telephone bands/ (700 MHz to 2000 MHz, no external shield) • Split power supply, LED can be driven by a separate power supply not loading the regulated supply. U.S. Pat. No. 6,157,476 • Tri-state-Receiver Output, floating in shut down with a weak pull-up • Eye safety class 1 (IEC60825-1, ed. 2001), limited LED on-time, LED current is controlled, no single fault to be considered • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Digital still and video cameras • Printers, fax machines, photocopiers, screen projectors • Telecommunication products (cellular phones, pagers) • Internet TV Boxes, video conferencing systems • External infrared adapters (dongles) • Medical an industrial data collection Parts Table Part Description Qty / Reel TFDU6103-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU6103-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs Document Number 81211 Rev. 1.0, 31-Jul-06 www.vishay.com 295 TFDU6103 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 Logic & SD Controlled Driver Control TXD IRED C GND 18468 Pinout Definitions: TFDU6103 weight 200 mg In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 "U" Option BabyFace (Universal) MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s IRED Detector MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. 1 17087 2 3 4 5 6 7 8 Note: We apologize to use sometimes in our documentation the abbreviation LED and the word Light Emitting Diode instead of Infrared Emitting Diode (IRED) for IR-emitters. That is by definition wrong; we are here following just a bad trend. Typical values are for design aid only, not guaranteed nor subject to production testing and may vary with time. www.vishay.com 296 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Pin Description Pin Number Function Description 1 VCC2 IRED Anode Connect IRED anode directly to VCC2. For voltages higher than 3.6 V an external resistor might be necessary for reducing the internal power dissipation. An unregulated separate power supply can be used at this pin. I/O Active 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 TXD This input is used to transmit serial data when SD is low. An on-chip protection circuit disables the LED driver if the TXD pin is asserted for longer than 100 μs. When used in conjunction with the SD pin, this pin is also used to receiver speed mode. I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. O LOW 5 SD Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the TXD pin is sampled and used to set receiver low bandwidth (TXD = Low, SIR) or high bandwidth (TXD = High, MIR and FIR) mode. Will be overwritten by the mode pin input, which must float, when dynamic programming is used. I HIGH 6 VCC1 Supply Voltage 7 NC 8 GND Ground Absolute Maximum Ratings Reference point Ground Pin 8, unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 Typ. +6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 + 6.5 V Input currents For all pins, except IRED anode pin 10 mA Output sinking current Power dissipation See derating curve, figure 5 Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature < 90 μs, ton < 20 % IRED anode voltage mA mW 125 °C - 25 + 85 °C Tstg - 25 + 85 °C 260 °C IIRED (DC) 125 mA IIRED (RP) 600 mA + 6.5 V VIREDA Voltage at all inputs and outputs Vin > VCC1 is allowed Load at mode pin when used as mode indicator 25 500 Tamb See recommended solder profile (see figure 4) Average output current Repetitive pulse output current PD - 0.5 VIN 5.5 V 50 pF Max Unit Eye safety information Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Typ. Virtual source size Parameter Method: (1 - 1/e) encircled energy Test Conditions d 2.5 2.8 Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie mm *) (500)**) mW/sr *) Due **) to the internal limitation measures the device is a "class1" device IrDA specifies the max. intensity with 500 mW/sr Document Number 81211 Rev. 1.0, 31-Jul-06 www.vishay.com 297 TFDU6103 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Dynamic supply current Shutdown supply current Symbol Min VCC 2.4 Typ. Max Unit 5.5 V Receive mode only, idle In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. SIR mode ICC 1.8 3.0 mA MIR/FIR mode ICC 2.0 3.3 mA SD = High T = 25 °C, not ambient light sensitive, detector is disabled in shutdown mode ISD 0.01 SD = High, full specified temperature range, not ambient light sensitive ISD μA 1 μA Operating temperature range TA - 25 + 85 °C Input voltage low (TXD, SD) VIL - 0.5 0.5 V Input voltage high (TXD, SD) CMOS level *) VIH VCC - 0.3 6 V Input leakage current (TXD, SD) Vin = 0.9 x VCC1 IICH -1 +1 μA CI 5 pF Output voltage low IOL = 500 μA, Cload = 15 pF VOL 0.4 V Output voltage high IOH = 250 μA, Cload = 15 pF VOH Output RXD current limitation high state low state Short to Ground Short to VCC1 SD shutdown pulse duration Activating shutdown Input capacitance, TXD, SD RXD to VCC1 impedance SD mode programming pulse duration All modes 0.9 x VCC1 V 20 20 30 RRXD 400 tSDPW 200 500 mA mA v μs 600 k: ns *) The typical threshold level is 0.5 x VCC1 (VCC1 = 3 V) . It is recommended to use the specified min/ max values to avoid increased operating current www.vishay.com 298 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typ. Max Unit Minimum irradiance Ee in angular range **) SIR mode Parameter 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm Test Conditions Symbol Ee Min 25 (2.5) 35 (3.5) mW/m2 (μW/cm2) Minimum irradiance Ee in angular range, MIR mode 1.152 Mbit/s O = 850 nm to 900 nm Ee 65 (6.5) Minimum irradiance Ee inangular range, FIR mode 4.0 Mbit/s O = 850 nm to 900 nm Ee 80 (8.0) Maximum irradiance Ee in angular range ***) O = 850 nm to 900 nm Ee 5 (500) Maximum no detection irradiance *) Ee 4 (0.4) mW/m2 (μW/cm2) 90 (9.0) mW/m2 (μW/cm2) kW/m2 (mW/cm2) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, 15 pF tr (RXD) 10 40 Fall time of output signal 90 % to 10 %, 15 pF tf (RXD) 10 40 RXD pulse width of output signal, 50 %, SIR mode Input pulse length 1.4 Ps < PWopt < 25 μs tPW Input pulse length 1.4 Ps < PWopt < 25 μs, tPW 1.5 1.8 2.6 μs 250 270 ns 2.1 ns ns μs - 25 °C < T < 85 °C ****) RXD pulse width of output signal, 50 %, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 125 ns, 4.0 Mbit/s tPW 100 140 ns Input pulse length PWopt = 250 ns, 4.0 Mbit/s tPW 225 275 ns Input irradiance = 100 mW/m2, 4.0 Mbit/s 20 ns Input irradiance = 100 mW/m2, 1.152 Mbit/s 40 ns Input irradiance = 100 mW/m2, 576 kbit/s 80 ns Input irradiance = 100 mW/m2, d 115.2 kbit/s After completion of shutdown programming sequence Power on delay 350 ns 250 μs 100 μs Stochastic jitter, leading edge Receiver start up time Latency tL 40 ® Note: All timing data measured with 4 Mbit/s are measured using the IrDA FIR transmission header. The data given here are valid 5 Ps after starting the preamble. *) This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER). For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). ****) Retriggering once during applied optical pulse may occur Document Number 81211 Rev. 1.0, 31-Jul-06 www.vishay.com 299 TFDU6103 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions Symbol Min Typ. Max Unit Note: No external resistor current limiting resistor is needed for VCC1 = VCC2 = 3.3 V ID 330 440 600 mA IIRED -1 1 μA Output radiant intensity, see figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0° TXD = High, SD = Low, R1 = 1 : Ie 110 170 500*) mW/sr Output radiant intensity, see figure 3, recommended application circuit VCC = VIRED = 3.3 V, D = 0°, 15° TXD = High, SD = Low, R1 = 1 : Ie 100 130 500*) mW/sr Output radiant intensity VCC1 = 3.3 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr Output leakage IRED current D Output radiant intensity, angle of half intensity Peak - emission wavelength**) Op Spectral bandwidth 'O Optical rise time, Optical fall time Optical output pulse duration Optical overshoot ± 24 875 886 ° 900 45 tropt , tfopt 10 Input pulse width 217 ns, 1.152 Mbit/s topt 207 Input pulse width 125 ns, 4.0 Mbit/s topt Input pulse width 250 ns, 4.0 Mbit/s Input pulse width t < 100 μs Input pulse width t t 100 μs nm nm 40 ns 217 227 ns 117 125 133 ns topt 242 250 258 ns topt topt 20 100 μs μs 25 % t *) Maximum value is given by the IrDA-Standard **) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (125 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used. www.vishay.com 300 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Recommended Circuit Diagram Vishay Semiconductors transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD, Mode) and the output RXD should be directly (DC) coupled to the I/O circuit. V cc2 R1 V cc1 R2 C1 C3 GND IRED Anode V cc C2 Ground SD SD TXD TXD RXD RXD IRED Cathode 19789 Figure 1. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and reduces the influence of the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for higher operating voltages and elevated temperatures, see derating curve in figure 5, to avoid too high internal power dissipation. The capacitors C2 and C3 combined with the resistor R2 (as the low pass filter) is smoothing the supply voltage VCC1. R2, C1, C2, and C3 are optional and dependent on the quality of the supply voltages VCC1 and VCC2 and injected noise. An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 and C3 as close as possible to the transceiver power supply pins. An Tantalum capacitor should be used for C1 and C3 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current is rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Wienfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1, C3 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 3.3 V supply voltage: no resistors necessary, the internal controller is able to control the current e.g. 2 x CRCW-1206-1R0-F-RT1 R2 10 :, 0.125 W CRCW-1206-10R0-F-RT1 Document Number 81211 Rev. 1.0, 31-Jul-06 Vishay Part Number www.vishay.com 301 TFDU6103 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU6103 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. After that TXD is enabled as normal TXD input and the transceiver is set for the high bandwidth (576 kbit/s to 4 Mbit/s) mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. After that TXD is enabled as normal TXD input and the transceiver is set for the lower bandwidth (9.6 kbit/s to 115.2 kbit/s) mode. 50 % SD ts th High : FIR Setting to the High Bandwidth Mode (0.576 Mbit/s to 4.0 Mbit/s) TXD 50 % 50 % Low : SIR 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. 14873 Figure 2. Mode Switching Timing Diagram Table 2. Truth table Inputs TXD Optical input Irradiance mW/m 2 RXD Transmitter high x x weakly pulled (500 k:) to VCC1 0 Ie low www.vishay.com 302 Outputs SD high x low (active) high > 100 μs x high 0 low <4 high 0 low > Min. irradianceEe < Max. irradiance Ee low (active) 0 low > Max. irradiance Ee x 0 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Recommended Solder Profiles 260 240 220 200 180 160 140 120 100 80 60 40 20 0 275 10 s max. at 230 °C 240 °C max. T ≥ 255 °C for 10 s....30 s 250 225 2...4 °C/s Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 160 °C max. 120 s...180 s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 90 s max. 2...4 °C/s 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 2 °C...3 °C/s 50 25 0 50 100 19535 150 200 250 300 0 350 0 Time/s 50 100 150 200 Time/s 19532 Figure 3. Recommended Solder Profile for Sn/Pb soldering Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). Document Number 81211 Rev. 1.0, 31-Jul-06 300 350 Figure 4. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 Temperature/°C 180 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 5. RTS Recommendation Current Derating Diagram Figure 6 shows the maximum operating temperature when the device is operated without external current limiting resistor. A power dissipating resistor of 2 : is recommended from the cathode of the IRED to Ground for supply voltages above 4 V. In that case the device can be operated up to 85 °C, too. 90 Ambient Temperature (˚C) Lead (Pb)-Free, Recommended Solder Profile The TFDU6103 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 4 and 5 are VISHAY's recommended profiles for use with the TFDU6103 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 250 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 6. Temperature Derating Diagram www.vishay.com 303 TFDU6103 Vishay Semiconductors Package Dimensions in mm 20111 Figure 7. Package drawing and solder footprints for top and side view mounting TFDU6103, dimensions in mm, tolerance ± 0.2 mm if not otherwise mentioned www.vishay.com 304 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 Document Number 81211 Rev. 1.0, 31-Jul-06 W3 max. www.vishay.com 305 TFDU6103 Vishay Semiconductors Tape Dimensions 19824 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 8. Tape drawing, TFDU6103 for top view mounting, tolerance ± 0.1 mm www.vishay.com 306 Document Number 81211 Rev. 1.0, 31-Jul-06 TFDU6103 Vishay Semiconductors Tape Dimensions 19875 Drawing-No.: 9.700-5297.01-4 Issue: 1; 04.08.05 Figure 9. Tape drawing, TFDU6103 for side view mounting, tolerance ± 0.1 mm Document Number 81211 Rev. 1.0, 31-Jul-06 www.vishay.com 307 TFDU6300 Vishay Semiconductors Fast Infrared Transceiver Module (FIR, 4 Mbit/s) for 2.4 V to 3.6 V Operation Description The TFDU6300 transceiver is an infrared transceiver module compliant to the latest IrDA physical layer low-power standard for fast infrared data communication, supporting IrDA speeds up to 4 Mbit/s (FIR), HP-SIR®, Sharp ASK® and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module is a photo PIN diode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This new Vishay FIR transceiver is built in a new smaller package using the experiences of the lead frame BabyFace technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/demodulation function. At a minimum, a Vcc bypass capacitor is 20101 the only external component required implementing a complete solution. TFDU6300 has a tri-state output and is floating in shutdown mode with a weak pull-up. An otherwise identical transceiver with low-voltage (1.8 V) logic levels is available as TFDU6301. Features • Compliant to the latest IrDA physical layer specification (up to 4 Mbit/s) with an extended low power range of > 70 cm e3 (typ. 1 m) and TV Remote Control (> 9 m) • Operates from 2.4 V to 3.6 V within specification • Low power consumption (1.8 mA typ. supply current) • Power shutdown mode (0.01 μA typ. shutdown current) • Surface mount package - Universal (L 8.5 mm x H 2.5 mm x W 3.1 mm) • Tri-state-receiver output, floating in shut down with a weak pull-up • Low profile (universal) package capable of surface mount soldering to side and top view orientation • Directly interfaces with various Super I/O and controller devices • Only one external component required • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Digital cameras and video cameras • Printers, fax machines, photocopiers, screen projectors • Telecommunication products (cellular phones, pagers) • Internet TV boxes, video conferencing systems • External infrared adapters (dongles) • Medical and industrial data collection Parts Table Part Description Qty / Reel or Tube TFDU6300-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs TFDU6300-TT3 Oriented in carrier tape for side view surface mounting 2500 pcs www.vishay.com 308 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 SD Logic & Controlled Driver Control TXD GND 18468_1 Figure 1. Functional Block Diagram Pin Description Pin Number 1 Function Description I/O Active VCC2 IRED anode to be externally connected to Vcc2 (VIRED). For higher voltages IRED Anode than 3.6 V an external resistor might be necessary for reducing the internal power dissipation. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled Vcc1 - supply. 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 TXD This input is used to transmit serial data when SD is low. An on-chip protection circuit disables the IRED driver if the TXD pin is asserted for longer than 100 μs. When used in conjunction with the SD pin, this pin is also used to control the receiver mode. Logic reference: Vcc1 I HIGH 4 RXD Received data output, push-pull CMOS driver output capable of driving standard CMOS. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kOhm (typ.) in shutdown mode. High/ Low levels related to Vcc1. RXD echoes the TXD signal. O LOW 5 SD Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the TXD pin is sampled and used to set receiver low bandwidth (TXD = Low: SIR) or high bandwidth (TXD = High: MIR and FIR) mode. I HIGH 6 VCC1 Supply voltage 7 NC Internally not connected. 8 GND Ground I TFDU6301 weight 0.075 g 19531 Figure 2. Pinning Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 309 TFDU6300 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6.5 V Voltage at all I/O pins Vin < VCC1 is allowed Input currents For all pins, except IRED anode pin Typ. - 0.5 Output sinking current Power dissipation PD Junction temperature Storage temperature range Soldering temperature 25 mA 500 mW 125 °C - 25 + 85 °C Tstg - 25 + 85 °C 260 °C IIRED (DC) 150 mA IIRED (RP) 700 mA See chapter “Recommended Solder Profiles” Average output current V mA Tamb TJ Ambient temperature range (operating) 6 10 Repetitive pulse output current < 90 μs, ton < 20 % ESD protection Human body model Virtual source size Method: (1-1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie 1 1.8 kV 2.0 mm *) mW/sr (500)**) *) Due to the internal limitation measures and the IrDA defined transmission protocol the device is a "class 1" device when operated inside the absolute maximum ratings **) IrDA specifies the maximum intensity with 500 mW/sr Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any case obsoletes the former version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). www.vishay.com 310 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Dynamic Supply current Symbol Min VCC 2.4 Typ. Max Unit 3.6 V Receive mode only, idle In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. SIR mode ICC 1.8 3.0 mA MIR/FIR mode ICC 2.0 3.3 mA Shutdown supply current SD = High T= 25 °C, not ambient light sensitive, detector is disabled in shutdown mode ISD 0.01 Shutdown supply current SD = High, full specified temperature range, not ambient light sensitive ISD μA 1 μA °C Operating temperature range TA - 25 + 85 Input voltage low (TXD, SD) VIL - 0.5 0.5 V VIH VCC - 0.3 6 V IICH -1 Input voltage high (TXD, SD) CMOS level*) Input leakage current (TXD, SD) Vin = 0.9 x VCC1 Input capacitance, TXD, SD Output voltage low IOL = 500 μA Cload = 15 pF Output voltage high IOH = - 250 μA Cload = 15 pF Output RXD current limitation high state low state Short to Ground Short to VCC1 SD shutdown pulse duration Activating shutdown RXD to VCC1 impedance SD mode programming pulse duration All modes +1 μA CI 5 pF VOL 0.4 VOH V 0.9 x VCC1 V 20 20 30 RRXD 400 tSDPW 200 500 mA mA f μs 600 k: ns *) The typical threshold level is 0.5 x VCC1 (VCC1 = 3 V). It is recommended to use the specified min/max values to avoid increased operating current. Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 311 TFDU6300 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Typ. Max Unit Ee 50 (5) 80 (8) mW/m2 (μW/cm2) 1.152 Mbit/s O = 850 nm to 900 nm, VCC = 2.4 V Ee 100 (10) 4 Mbit/s O = 850 nm to 900 nm, VCC = 2.4 V Ee 130 (13) O = 850 nm to 900 nm Ee 5 (500) Minimum irradiance Ee*) in angular range**) 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm, VCC = 2.4 V Minimum irradiance Ee in angular range, MIR mode Minimum irradiance Ee inangular range, FIR mode Maximum irradiance Ee in angular range***) Symbol Min mW/m2 (μW/cm2) 200 (20) mW/m2 (μW/cm2) kW/m2 (mW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 10 40 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 10 40 ns RXD pulse width of output signal, 50 %, SIR mode Input pulse length 1.4 μs < PWopt < 25 μs tPW 1.6 2.2 3 μs RXD pulse width of output signal, 50 %, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 105 250 275 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 125 ns, 4 Mbit/s tPW 105 125 145 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 250 ns, 4 Mbit/s tPW 225 250 275 ns Stochastic jitter, leading edge Input irradiance = 100 mW/m2, 4.0 Mbit/s 1.152 Mbit/s d 115.2 kbit/s 25 80 350 ns ns ns Receiver start up time After completion of shutdown programmimg sequence Power on dalay 250 μs 100 μs Latency tL 40 Note: All timing data measured with 4 Mbit/s are measured using the IrDA® FIR transmission header. The data given here are valid 5 μs after starting the preamble. *) IrDA low power specification is 90 mW/m2. Specification takes into account a window loss of 10 %. **) IrDA sensitivity definition (equivalent to threshold irradiance): Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical power delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document "Symbols and Terminology" on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). www.vishay.com 312 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions Note: No external resistor current limiting resistor is needed Symbol Min Typ. Max Unit ID 330 440 600 mA IIRED -1 1 μA Output radiant intensity, s. figure 3, VCC = VIRED = 3.3 V, D = 0° recommended appl. circuit TXD = High, SD = Low Ie 65 180 500*) mW/sr Output radiant intensity, s. figure 3, VCC = VIRED = 3.3 V, D = 0°, 15° recommended appl. circuit TXD = High, SD = Low Ie 50 125 500*) mW/sr VCC1 = 3.3 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr Output leakage IRED current Output radiant intensity r24 D Output radiant intensity, Angle of Half Intensity Peak - emission wavelength**) Op Spectral bandwidth 'O Optical rise time, Optical fall time 875 886 deg 900 45 tropt, tfopt 10 nm nm 40 ns Optical output pulse duration Input pulse width 217 ns, 1.152 Mbit/s topt 207 217 227 ns Optical output pulse duration Input pulse width 125 ns, 4 Mbit/s topt 117 125 133 ns Optical output pulse duration Input pulse width 250 ns, 4 Mbit/s topt 242 250 258 ns Optical output pulse duration Input pulse width t < 100 μs input pulse width t t 100 μs topt topt 20 100 μs μs 25 % Optical overshoot t *) Maximum value is given by the IrDA-Standard **) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (125 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 313 TFDU6300 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFDU6300 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 3). VCC2 R1 VCC1 R2 C1 GND IRED Anode V CC C2 Ground SD SD TXD TXD RXD RXD IRED Cathode 19307 Figure 3. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for high operating voltages and elevated temperatures. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 no resistor necessary, the internal controller is able to control the current R2 10 :, 0.125 W www.vishay.com 314 Vishay Part Number CRCW-1206-10R0-F-RT1 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU6300 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. TXD is now enabled as normal TXD input for the high bandwidth mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. TXD is now enabled as normal TXD input for the lower bandwidth mode. 50 % SD ts th High : FIR Setting to the High Bandwidth Mode (0.576 Mbit/s to 4 Mbit/s) TXD 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. 50 % 50 % Low : SIR 14873 Figure 4. Mode Switching Timing Diagram Table 2. Truth table Inputs Outputs SD TXD Optical input Irradiance mW/m2 RXD Transmitter high x x weakly pulled (500 k:) to VCC1 0 Ie low high x high low high > 100 μs x high 0 low low <4 high 0 low low > Min. detection threshold irradiance < Max. detection threshold irradiance low (active) 0 low low > Max. detection threshold irradiance x 0 Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 315 TFDU6300 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). Solder Profile for Sn/Pb Soldering 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 19535 100 150 200 250 300 350 Figure 5. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 6. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU6300 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 6 and 7 are VISHAY's recommended profiles for use with the TFDU6300 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 7. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. www.vishay.com 316 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors Package Dimensions TFDU6300 (Universal) Package 19533 Figure 8. Package Drawing Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 317 TFDU6300 Vishay Semiconductors Tape and Reel Information Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Figure 9. Reel drawing Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 318 W3 max. Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6300 Vishay Semiconductors Tape Dimensions 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 10. Tape drawing, TFDU6300 for top view mounting Document Number 84763 Rev. 1.2, 21-Jun-06 www.vishay.com 319 TFDU6300 Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 11. Tape drawing, TFDU6300 for side view mounting www.vishay.com 320 Document Number 84763 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Fast Infrared Transceiver Module (FIR, 4 Mbit/s) for 2.4 V to 3.6 V Operation and Low-Voltage Logic (1.8 V) Description The TFDU6301 transceiver is an infrared transceiver module compliant to the latest IrDA physical layer low-power standard for fast infrared data communication, supporting IrDA speeds up to 4 Mbit/s (FIR), HP-SIR®, Sharp ASK® and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module is a photo PIN diode, an infrared emitter (IRED), and a low-power control IC to provide a total front-end solution in a single package. This new Vishay FIR transceiver is built in a new smaller package using the experiences of the lead frame BabyFace technology. The transceivers are capable of directly interfacing with a wide variety of I/O devices, which perform the modulation/ demodulation function. At a minimum, a Vcc bypass capacitor is the 20101 only external component required implementing a complete solution. TFDU6300 has a tri-state output and is floating in shutdown mode with a weak pull-up. An otherwise identical transceiver with supply voltage related logic levels is available as TFDU6300. Features • Compliant to the latest IrDA physical layer specification (up to 4 Mbit/s) with an extended low power range of > 70 cm (typ. 1 m) and TV Remote Control (> 9 m) e3 • Operates from 2.4 V to 3.6 V within specification • Low power consumption (1.8 mA typ. supply current) • Power shutdown mode (0.01 μA typ. shutdown current) • Surface mount package - Universal (L 8.5 mm x H 2.5 mm x W 3.1 mm) • Tri-state-receiver output, floating in shut down with a weak pull-up • Low profile (universal) package capable of surface mount soldering to side and top view orientation • Directly interfaces with various Super I/O and controller devices • Only one external component required • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs • Internal logic voltage reference of 1.8 V • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • Notebook computers, desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Digital cameras and video cameras • Printers, fax machines, photocopiers, screen projectors • Telecommunication products (cellular phones, pagers) • Internet TV boxes, video conferencing systems • External infrared adapters (dongles) • Medical and industrial data collection Parts Table Part Description Qty / Reel or Tube TFDU6301-TR3 Oriented in carrier tape for side view surface mounting 2500 pcs TFDU6301-TT3 Oriented in carrier tape for side view surface mounting 2500 pcs Document Number 84668 Rev. 1.2, 21-Jun-06 www.vishay.com 321 TFDU6301 Vishay Semiconductors Functional Block Diagram VCC1 Tri-State Driver Amplifier RXD Comparator VCC2 SD Logic & Controlled Driver Control TXD GND 18468_1 Figure 1. Functional Block Diagram Pin Description Pin Number 1 Function Description I/O Active VCC2 IRED anode to be externally connected to Vcc2 (VIRED). For higher voltages IRED Anode than 3.6 V an external resistor might be necessary for reducing the internal power dissipation. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled Vcc1 - supply. 2 IRED Cathode IRED cathode, internally connected to driver transistor 3 TXD This input is used to transmit serial data when SD is low. An on-chip protection circuit disables the IRED driver if the TXD pin is asserted for longer than 100 μs. When used in conjunction with the SD pin, this pin is also used to control the receiver mode. Logic reference: 1.8 V logic I HIGH 4 RXD Received data output, push-pull CMOS driver output capable of driving standard CMOS. No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 kOhm (typ.) in shutdown mode. High/ Low levels adapted to 1.8 V logic. RXD echoes the TXD signal. O LOW 5 SD Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the TXD pin is sampled and used to set receiver low bandwidth (TXD = Low: SIR) or high bandwidth (TXD = High: MIR and FIR) mode. I HIGH 6 VCC1 Supply voltage 7 NC Internally not connected. 8 GND Ground I TFDU6301 weight 0.075 g 19531 Figure 2. Pinning www.vishay.com 322 Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6.5 V Voltage at all I/O pins Vin < VCC1 is allowed Input currents For all pins, except IRED anode pin Typ. - 0.5 Output sinking current Power dissipation PD Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature V mA 25 mA 500 mW 125 °C Tamb - 25 + 85 °C Tstg - 25 + 85 °C 260 °C IIRED (DC) 150 mA IIRED (RP) 700 mA See chapter “Recommended Solder Profiles” Average output current 6 10 Repetitive pulse output current < 90 μs, ton < 20 % ESD protection Human body model Virtual source size Method: (1-1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001 Ie 1 1.8 kV 2.0 mm mW/sr *) (500)**) *) Due to the internal limitation measures and the IrDA defined transmission protocol the device is a "class 1" device when operated inside the absolute maximum ratings **) IrDA specifies the maximum intensity with 500 mW/sr Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any case obsoletes the former version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). Document Number 84668 Rev. 1.2, 21-Jun-06 www.vishay.com 323 TFDU6301 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Dynamic Supply current Symbol Min VCC 2.4 Typ. Max Unit 3.6 V Receive mode only, idle In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. SIR mode ICC 1.8 3.0 mA MIR/FIR mode ICC 2.0 3.3 mA Shutdown supply current SD = High T= 25 °C, not ambient light sensitive, detector is disabled in shutdown mode ISD 0.01 Shutdown supply current SD = High, full specified temperature range, not ambient light sensitive ISD TA - 25 Internally generated Vdd 1.62 Input voltage low (TXD, SD) VIL - 0.5 Input voltage high*) (TXD, SD) VIH 1.5 IICH -1 Operating temperature range Digital Reference Voltage Input leakage current (TXD, SD) Vin > 1.6 V Input capacitance, TXD, SD Output voltage low IOL = 500 μA Cload = 15 pF Output voltage high IOH = - 250 μA Cload = 15 pF Output RXD current limitation high state low state Short to Ground Short to VCC1 SD shutdown pulse duration Activating shutdown RXD to VCC1 impedance SD mode programming pulse duration *) All modes PA 1 μA + 85 °C 1.98 V 0.5 V 6 V +1 μA CI 5 pF VOL 0.4 V VOH 1.8 1.8 0.8 x Vdd V 20 20 30 RRXD 400 tSDPW 200 500 mA mA f μs 600 k: ns The typical threshold level is 0.5 x Vdd. It is recommended to use the specified min/max values to avoid increased operating current. www.vishay.com 324 Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Symbol Minimum irradiance Ee*) in angular range**) 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm, VCC = 2.4 V Ee Minimum irradiance Ee in angular range, MIR mode 1.152 Mbit/s O = 850 nm to 900 nm, VCC = 2.4 V Ee Minimum irradiance Ee inangular range, FIR mode 4 Mbit/s O = 850 nm to 900 nm, VCC = 2.4 V Ee Maximum irradiance Ee in angular range***) O = 850 nm to 900 nm Ee Min Typ. Max Unit 50 (5) 80 (8) mW/m2 (μW/cm2) 100 (10) 130 (13) mW/m2 (μW/cm2) 200 (20) 5 (500) mW/m2 (μW/cm2) kW/m2 (mW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 10 40 ns Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 10 40 ns RXD pulse width of output signal, 50 %, SIR mode Input pulse length 1.4 Ps < PWopt < 25 Ps tPW 1.6 2.2 3 μs RXD pulse width of output signal, 50 %, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 105 250 275 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 125 ns, 4 Mbit/s tPW 105 125 145 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 250 ns, 4 Mbit/s tPW 225 250 275 ns Stochastic jitter, leading edge Input irradiance = 100 mW/m2, 4.0 Mbit/s 1.152 Mbit/s d 115.2 kbit/s 25 80 350 ns ns ns 250 μs 100 μs Receiver start up time After completion of shutdown programmimg sequence Power on dalay Latency tL 40 Note: All timing data measured with 4 Mbit/s are measured using the IrDA® FIR transmission header. The data given here are valid 5 μs after starting the preamble. *) IrDA low power specification is 90 mW/m2. Specification takes into account a window loss of 10 %. **) IrDA sensitivity definition (equivalent to threshold irradiance): Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical power delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document "Symbols and Terminology" on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). Document Number 84668 Rev. 1.2, 21-Jun-06 www.vishay.com 325 TFDU6301 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC1 = VCC2 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions Note: No external resistor current limiting resistor is needed Symbol Min Typ. Max Unit ID 330 440 600 mA IIRED -1 1 μA Output radiant intensity, see figure 3, recommended appl. circuit VCC = VIRED = 3.3 V, D = 0° TXD = High, SD = Low Ie 65 180 500*) mW/sr Output radiant intensity, see figure 3, recommended appl. circuit VCC = VIRED = 3.3 V, D = 0°, 15° TXD = High, SD = Low Ie 50 125 500*) mW/sr Output radiant intensity VCC1 = 3.3 V, D = 0°, 15° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr Output leakage IRED current r24 D Output radiant intensity, Angle of Half Intensity Peak - emission wavelength**) Op Spectral bandwidth 'O Optical rise time, Optical fall time 875 886 ° 900 45 tropt, tfopt 10 nm nm 40 ns Optical output pulse duration Input pulse width 217 ns, 1.152 Mbit/s topt 207 217 227 ns Optical output pulse duration Input pulse width 125 ns, 4 Mbit/s topt 117 125 133 ns Optical output pulse duration Input pulse width 250 ns, 4 Mbit/s topt 242 250 258 ns Optical output pulse duration Input pulse width t < 100 μs Input pulse width t t 100 μs topt topt 20 100 μs μs 25 % Optical overshoot t *) Maximum value is given by the IrDA-Standard **) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. When operated under IrDA full range conditions (125 mW/sr) the RC range to be covered is in the range from 8 m to 12 m, provided that state of the art remote control receivers are used www.vishay.com 326 Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFDU6300 needs no additional external components. However, depending on the entire system design and board layout, additional components may be required (see figure 3). VCC2 R1 VCC1 R2 C1 GND IRED Anode V CC C2 Ground SD SD TXD TXD RXD RXD IRED Cathode 19307 Figure 3. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is only necessary for high operating voltages and elevated temperatures. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. A Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not able to follow the fast current rise time. In that case another 4.7 μF (type, see table under C1) at VCC2 will be helpful. Keep in mind that basic RF-design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Table 1. Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V 293D 475X9 016B C2 0.1 μF, Ceramic VJ 1206 Y 104 J XXMT R1 no resistor necessary, the internal controller is able to control the current R2 10 :, 0.125 W Document Number 84668 Rev. 1.2, 21-Jun-06 Vishay Part Number CRCW-1206-10R0-F-RT1 www.vishay.com 327 TFDU6301 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU6300 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. TXD is now enabled as normal TXD input for the high bandwidth mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. TXD is now enabled as normal TXD input for the lower bandwidth mode. 50 % SD ts th High : FIR Setting to the High Bandwidth Mode (0.576 Mbit/s to 4 Mbit/s) TXD 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts t 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th t 200 ns TXD can be set to logic "LOW". The hold time of TXD is limited by the maximum allowed pulse length. 50 % 50 % Low : SIR 14873 Figure 4. Mode Switching Timing Diagram Table 2. Truth table Inputs TXD Optical input Irradiance mW/m 2 RXD Transmitter high x x weakly pulled (500 k:) to VCC1 0 low high x high Ie low high > 100 μs x high 0 low low <4 high 0 low low > Min. detection threshold irradiance < Max. detection threshold irradiance low (active) 0 low low > Max. detection threshold irradiance x 0 www.vishay.com 328 Outputs SD Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 100 19535 150 200 250 300 350 Figure 5. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 6. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TFDU6301 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 6 and 7 are VISHAY's recommended profiles for use with the TFDU6301 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 7. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Document Number 84668 Rev. 1.2, 21-Jun-06 www.vishay.com 329 TFDU6301 Vishay Semiconductors Package Dimensions in mm TFDU6301 (Universal) Package 19533 Figure 8. Package Drawing www.vishay.com 330 Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors Tape and Reel Information Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Figure 9. Reel drawing Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 180 60 16.4 22.4 15.9 19.4 16 330 50 16.4 22.4 15.9 19.4 Document Number 84668 Rev. 1.2, 21-Jun-06 W3 max. www.vishay.com 331 TFDU6301 Vishay Semiconductors Tape Dimensions in mm 19855 Drawing-No.: 9.700-5280.01-4 Issue: 1; 03.11.03 Figure 10. Tape drawing, TFDU6301 for top view mounting www.vishay.com 332 Document Number 84668 Rev. 1.2, 21-Jun-06 TFDU6301 Vishay Semiconductors 19856 Drawing-No.: 9.700-5279.01-4 Issue: 1; 08.12.04 Figure 11. Tape drawing, TFDU6301 for side view mounting Document Number 84668 Rev. 1.2, 21-Jun-06 www.vishay.com 333 TFBS6614 Vishay Semiconductors Low Profile 4 Mbit/s (FIR) Infrared Transceiver Module Description The Vishay TFBS6614 is a very low profile (2.7 mm) 4 Mbit/s Infrared Data Transceiver module. A PIN photodiode, an infrared emitter (IRED) and a lowpower control IC are integrated in a single package that provides a total front-end solution. VLOGIC - allows a low-voltage controller to connect directly to TXD, RXD and SD/Mode logic signals of the transceiver hence eliminating the need for costly signal level converter and reducing power consumption. 18088 Features • Small size: H 2.7 mm x W 3.33 mm x L 7.98 mm • Typical 1.0 m link distance, typ. RC range e4 20 m • Battery and power management features: > Receive - 2 mA typical > Shutdown - 10 nA typical > Independent LED anode power supply > Wide voltage range 2.6 V - 5.5 V > High VCC noise rejection > 100 mVPP • The TXD-echo function is enabled • Vlogic (1.5 V - 5.5 V) - Independent digital supply voltage • Shutdown tri-states receiver output and disables TXD allowing bus interfacing • High immunity to fluorescent light noise and AC field. No external shield required • High DC ambient rejection - operates outdoors • Directly interfaces with various super I/O and controller devices • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC Applications • • • • • • • • PDAs Mobile phones Notebook computers, desktop PCs Digital photo and video cameras External infrared adapters (Dongles) Diagnostics systems Medical and industrial data collection GPS Ordering Information Part Number TFBS6614-TR3 www.vishay.com 334 Description Oriented in carrier tape for side view surface mounting Quantity / Reel 2500 pcs Document Number 82611 Rev. 2.2, 03-Sep-06 TFBS6614 Vishay Semiconductors Functional Block Diagram VCC1 Amplifier Comparator Tri-state driver RXD IRED IRED A VCC2 Current control SD Mode control IRED C TXD GND Figure 1. Functional Block Diagram Pinout TFBS6614, side view Weight 80 mg 1 2 3 4 5 Emitter 6 7 8 19906 Detector Pin Description Pin Number Function 1 IRED Anode 2 IRED Cathode 3 TXD 4 RXD 5 SD Description I high O low I high IRED Cathode, internally connected to driver transistor This input is used to transmit serial data when SD is low. An onchip protection circuit disables the LED driver if the TXD pin is asserted for longer than 100 μs. When used in conjunction with the SD pin, this pin is also used to set the receiver speed mode. Received Data Output, push-pull CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pulldown resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. Shutdown, also used for dynamic mode switching. Setting this pin active places the module into shutdown mode. On the falling edge of this signal, the state of the TXD pin is sampled and used to set receiver low bandwidth (TXD = Low, SIR) or high bandwidth (TXD = High, MIR and FIR) mode. VCC1 Supply Voltage, analog part 7 Vlogic Supply Voltage, digital part, I/O reference voltage for inputs and outputs. 8 GND Ground Rev. 2.2, 03-Sep-06 Active Connect IRED anode directly to Vcc2. For voltages higher than 3.6 V an external resistor might be necessary for reducing the internal power dissipation. An unregulated separate power supply can be used at this pin. 6 Document Number 82611 I/O www.vishay.com 335 TFBS6614 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin: GND unless otherwise noted Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Supply voltage range, transceiver Test Conditions 0 V < VCC2 < 6 V Symbol Min Max Unit VCC1 - 0.5 Typ. + 6.0 V IRED anode voltage 0 V < VCC1 < 6 V VCC2 - 0.5 + 6.5 V I/O reference voltage 0 V < VCC2 < 6 V 0 V < VCC1 < 6 V Vlogic - 0.5 + 6.0 V Input current For all pins, except IRED anode pin 10.0 mA Output sinking current Power dissipation PD Junction temperature Storage temperature range Soldering temperature 125 qC - 25 + 85 qC Tstg - 25 + 85 qC 260 qC See recommended solder profiles ( see figure 4, 5) Average output current Repetitive pulse output current < 90 Ps, ton < 20 % IIRED(DC) 125 mA IIRED(RP) 600 mA Voltage at all inputs and outputs Vin > VCC1 is allowed vin Virtual source size d Method: (1-1/e) encircled energy mA mW Tamb TJ Ambient temperature range (Operating) 25 500 5.5 1.5 2.1 V mm Maximum Intensity for Laser Class 1 Operation of IEC60825-1 or EN60825-1, edition Jan. 2001*) internal limitation to class 1 500 IrDA® specified maximum limit mW/sr Due to the internal limitation measures the device is a “ class 1” device under the specified conditions. It will not exceed the IrDA® intensity limit of 500mW/sr *) Sn/Pb and lead (Pb)-free soldering. The product passed VISHAY’s standard convection reflow profile soldering test. Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.A new version of the standard in any case obsoletes the former version. Note: We apologize to use sometimes in our documentation the abbreviation LED and the word Light Emitting Diode instead of Infrared Emitting Diode (IRED) for IR -emitters. That is by definition wrong; we are here following just a bad trend. www.vishay.com 336 Document Number 82611 Rev. 2.2, 03-Sep-06 TFBS6614 Vishay Semiconductors Optoelectronic Characteristics Transceiver Tamb = 25 qC, VCC = 2.6 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC 2.6 Typ. Max Unit 5.5 V 3 mA Supply current (Idle)*) SD = Low, Ee = 0 klx ICC 2 Supply current (Idle)*) SD = Low, Ee amb = 1 klx**) SD = Low, TXD = High ICC 2 3 mA Supply current transmitting ICC 10 mA Shutdown supply current SD = High, Ee amb = 0 klx ISD 2.0 PA Shutdown supply current SD = High, Ee amb = 1 klx ISD 2.5 PA Shutdown supply current SD = High, T = 85 qC, not ambient light sensitive ISD 5 PA + 85 qC Output voltage low IOL = 1 mA, CLoad = 15 pF VOL Output voltage high IOL = 500 PA, CLoad = 15 pF VOH 0.8 x Vlogic Output voltage high IOL = 250 PA, CLoad = 15 pF VOH 0.9 x Vlogic Output RXD current limitation high state Short to ground 20 mA Output RXD current limitation low state Short to Vlogic 20 mA RXD to VCC1 impedance SD = High 600 k: Operating temperature range TA Input voltage low (TXD, SD) - 25 0.4 V V V RRXD 400 VIL - 0.5 500 0.5 V Vlogic - 0.5 Vlogic + 0.5 V Input voltage high (TXD, SD) CMOS level***) for shutdown current < 2 PA VIH Shutdown current Vlogic = 3.3 V Vin(SD) = 2.5 V ISD 5 PA Shutdown supply Vlogic = 3.15 V Vin(SD) = 2.5 V ISD 0.5 PA Input voltage high (TXD, SD) TTL level, Vlogic = 4.5 V VIH 2.4 Input leakage current (TXD, SD) - 25 qC to 85 qC IL - 10 Input capacitance (TXD, SD, Mode) CIN V + 10 PA 5 pF *) Receive mode only. In transmit mode, add additional 85 mA (typ) for IRED current. Add RXD output current depending on RXD load. **) Standard Illuminant A. ***) The typical threshold level between 0.5 x Vlogic (Vlogicd 3 V) and 0.4 x Vlogic(Vlogic = 5.5 V). It is recommended to use the specified min/max values to avoid increased operating/shutdown current. Document Number 82611 Rev. 2.2, 03-Sep-06 www.vishay.com 337 TFBS6614 Vishay Semiconductors Receiver Tamb = 25 qC, VCC = 2.6 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Minimum detection threshold Test Conditions Symbol Min Typ. Ee irradiance 1), SIR mode 9.6 kbit/s to 115.2 kbit/s O = 850 nm to 900 nm 40 (4) Minimum detection threshold irradiance, FIR mode 4.0 Mbit/s O= 850 nm to 900 nm Ee 100 (10) Maximum detection threshold O = 850 nm to 900 nm Ee irradiance 2) Max Unit mW/m2 (PW/m2) 150 (15) 5 (500) mW/m2 (PW/m2) mW/m2 (mW/m2) No detection receiver input irradiance *) Rise time output signal 10 % to 90 %, 15 pF tr(RXD) 10 40 Fall time of output signal 90 % to 10 %, 15 pF tf(RXD) 10 40 RXD pulse width of output Input pulse length 1.4 Ps < PWopt < 25 Ps tPW RXD pulse width of output signal, 50 %, SIR mode Input pulse length 1.4 Ps < PWopt < 25 Ps - 25 qC < T > 85 qC tPW 1.5 1.8 2.6 Ps RXD pulse width of output signal, 50 %, MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 250 270 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 125 ns, 4.0 Mbit/s tPW 100 140 ns RXD pulse width of output signal, 50 %, FIR mode Input pulse length PWopt = 250 ns, 4.0 Mbit/s tPW 225 275 ns Stochastic jitter, leading edge Ee = 100 mW/m2, 4.0 Mbit/s signal, 50 %, SIR mode **) Stochastic jitter, leading edge Stochastic jitter, leading edge Ee 4 (0.4) mW/m2 (PW/m2) ns ns Ps 2.1 20 ns 2 40 ns 2 80 ns 2 ns Ee = 100 mW/m , 1.152 Mbit/s Ee = 100 mW/m , 576 kbit/s Stochastic jitter, leading edge Ee = 100 mW/m ,d115.2kbit/s 350 Receiver start up time After completion of shutdown programming sequence Power on delay 500 μs 300 μs Latency tL 170 Note: All timing data measured with 4 Mbit/s are measured using the IrDA ® FIR transmission header. The data given here are valid 5μs after starting the preamble. This parameter reflects the backlight test of the IrDA physical layer specification to guarantee immunity against light from fluorescent lamps Retriggering during applied optical pulse may occur 1) 2) These terms are equivalent to the IrDA sensitivity definitions: 1) Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the Minimum Intensity in Angular Range into the minimum Half-Angular Range at the maximum Link Length 2) Maximum Irradiance Ee In Angular Range, power per unit area. The optical power delivered to the detector by a source operating at the Maximum Intensity In Angular Range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification. For more definitions see the document “Symbols and Terminology “ on the Vishay Website http://www.vishay.com/docs/82512/82512.pdf www.vishay.com 338 Document Number 82611 Rev. 2.2, 03-Sep-06 TFBS6614 Vishay Semiconductors Transmitter Tamb = 25 qC, VCC = 2.6 V to 5.5V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter IRED operating current, switched current limiter Test Conditions Symbol Min Typ. Max Unit For 3.3 V operations no external resistor needed. For 5 V application that might be necessary depending on operating temperature range. ID 500 550 650 mA 1 PA 110 400 mW/sr 0.04 mW/sr IIRED -1 Output radiant intensity recommended application circuit D = 0 q, 15 q TXD = High, SD = Low, VCC1 = VCC2 = 3.3 V Internally current-controlled, no external resistor Ie 90 Output radiant intensity VCC1= 5.0 V, D = 0 q, 15 q = Low or SD = High (receiver is inactive as long as SD = High) Ie Output leakage IRED current D Output radiant intensity, angle of half intensity Peak - emission wavelength Op Spectral bandwidth 'O Optical rise time, fall time r24 880 886 q 900 40 nm nm tropt, tfopt 10 40 ns Optical output pulse duration Input pulse width 217 ns, 1.152 Mbit/s topt 207 217 227 ns Optical output pulse duration Input pulse width 125 ns, 4.0 Mbit/s topt 117 125 133 ns Optical output pulse duration Input pulse width 250 ns, 4.0 Mbit/s topt 242 250 258 ns Optical output pulse duration Input pulse width t < 100 μs Input pulse width t t 100 μs topt topt 20 100 μs μs 25 % Optical overshoot Mode Switching The TFBS6614 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. Document Number 82611 Rev. 2.2, 03-Sep-06 t Setting to the High Bandwidth Mode (0.576 Mbit/s to 4 Mbit/s) 1. Set SD/ Mode input to logic "High". 2. Set TXD input to logic "High". Wait ts t200 ns. 3. Set SD/ Mode to logic "Low" (the negative edge latches state of TXD, which determines speed setting). 4. After waiting th t200 ns TXD can be set to logic "Low". The hold time of TXD is limited by the maximum allowed pulse width. TXD is now enabled as normal TXD input for the high bandwidth mode. www.vishay.com 339 TFBS6614 Vishay Semiconductors Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD/ Mode input to logic "High". 2. Set TXD input to logic "Low". Wait ts t200 ns. 3. Set SD/ Mode to logic "Low" (the negative edge latches state of TXD, which determines speed setting). 4. TXD must be held for th t 200 ns. TXD is now enabled as normal TXD input for the lower bandwidth mode. SD 50% ts th High: FIR TXD 50% 50% Low: SIR Figure 2. Mode Switching Timing Diagram Truth table Inputs TXD Optical input Irradiance mW/m2 RXD Transmitter high x x weakly pulled (500 k:) to Vlogic 0 low high x low (active) Ie low high > 80 μs x high 0 low low <4 high 0 low low > Min. Detection Threshold Irradiance < Max. Detection Threshold Irradiance low (active) 0 low low > Max. Detection Threshold Irradiance x 0 www.vishay.com 340 Outputs SD Document Number 82611 Rev. 2.2, 03-Sep-06 TFBS6614 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFBS6614 needs no additional external components when the internal current control is used. For reducing the IRED drive current for low power applications with reduced range an additional resistor can be used to connect the IRED to the separate power supply. Depending on the entire system design and board layout, additional components may be required. (see figure 3). Worst-case conditions are test set-ups with long cables to power supplies. In such a case capacitors are necessary to compensate the effect of the cable inductance. In case of small applications as e.g. mobile phones where the power supply is close to the transceiver big capacitors are normally not necessary. The TFBS6614 is designed to operate in system with logical I/O level independent of the supply voltage. It can interface to IR controllers with low voltage logic from 1.5 V upwards to TTL (5 V). The reference voltage is to be connected to the Vlogic input. VCC2 R1 VCC R2 C1 IRED Anode VCC C2 GND Ground SD SD TXD TXD RXD RXD Figure 3. Recommended Application Circuit fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is optional for reducing the IRED drive current. Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (TXD, SD) and the output RXD should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage when noisy supply voltage is used or pick-up via the wiring is expected. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCCX and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. In any case, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not to follow the fast current rise time. In that case another 10 PF capacitor at VCC2 will be helpful. The recommended components in table 1 are for test set-ups Keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a small ceramic version or other Table 1. Recommended Application Circuit Components Component Recommended Value Vishay Part Number C1, C2 0.1 PF, Ceramic VJ 1206 Y 104 J XXMT R1 Supply voltage > 3.6 V: add a resistor in series e.g. 2 :. The internal controller is able to limit the current to about 550 mA. R2 10 :, 0.125 W Document Number 82611 Rev. 2.2, 03-Sep-06 www.vishay.com 341 TFBS6614 Vishay Semiconductors Recommended Solder Profiles Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Solder Profile for Sn/Pb soldering 260 10 s max. at 230 °C 240 °C max. 240 220 2...4 °C/s 200 180 160 140 120 s...180 s 120 90 s max. 100 80 2...4 °C/s 60 40 20 0 0 50 100 150 200 250 300 350 Time/s 19431 Figure 4. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFBS6614 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)-free solder paste like Sn(3.0-4.0)Ag(0.5-0.9)Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 is VISHAY's recommended profiles for use with the TFBS6614 transceivers. For more details please refer to Application note: SMD Assembly Instruction. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 280 T ≥ 255 °C for 20 s max 260 T peak = 260 °C max. 240 T ≥ 217 °C for 50 s max 220 200 180 Temperature/°C Temperature/°C 160 °C max. 160 20 s 140 120 90 s...120 s 100 50 s max. 2 °C...4 °C/s 80 60 2 °C...4 °C/s 40 20 0 0 50 100 150 200 250 300 350 19261 Time/s Figure 5. Solder Profile, RSS Recommendation Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. www.vishay.com 342 Document Number 82611 Rev. 2.2, 03-Sep-06 TFBS6614 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 Document Number 82611 Rev. 2.2, 03-Sep-06 W3 max. www.vishay.com 343 TFBS6614 Vishay Semiconductors Tape Dimensions in mm 19616 Drawing-No.: 9.700-5299.01-4 Issue: 1; 18.08.05 Figure 6. Tape drawing, TFBS6614 for side view mounting www.vishay.com 344 Document Number 82611 Rev. 2.2, 03-Sep-06 Contents TFDU7100 ............................. 346 FIR with RC Receiver www.vishay.com 3 TFDU7100 Vishay Semiconductors Infrared Transceiver Module (FIR, 4 Mbit/s) for IrDA® combined with Remote Control Receiver (36 kHz to 38 kHz Carrier) Description The TFDU7100 IrDA compliant transceiver is a multimedia module that supports IrDA data transfer up to 4 Mbit/s (FIR) and bidirectional Remote Control operating over a range of more than 18 m. Integrated within the transceiver are two PIN photodiodes, an infrared emitter (IRED) and two low-power control IC. It is ideal for applications requiring both Remote Control and IrDA communication. 19584 Features • Compliant to the latest IrDA physical layer specification (9.6 kbit/s to 4 Mbit/s) • TV Remote Control receiver with 18 m e3 receive range • Remote Control carrier frequency 36 kHz to 38 kHz • Operates from 2.7 V to 5.5 V within specification over full temperature range from - 25 °C to + 85 °C • Surface Mount Package, low profile (L 9.9 mm x 4.1 mm x 4 mm) • Compliant with IrDA Background Light Specification • EMI Immunity > 300 Vrms/m in GSM Bands verified (according IEC61000-4-3) • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Qualified for lead (Pb)-free and lead (Pb)-bearing soldering processes • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC • Split power supply, transmitter and receiver can be operated from two power supplies with relaxed requirements saving costs, US - Patent - No. 6,157,476 Applications • Remote control and IrDA communication in Multimedia • Notebook computers, Desktop PC’s, Internet TV Boxes, Video Conferencing Systems • Digital Still and Video Cameras • Printers, fax machines, Photocopiers, Screen Projectors Parts Table Part Description Qty / Reel TFDU7100-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU7100-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs www.vishay.com 346 Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors Functional Block Diagram Open Collector Output Amplifier Envelope Generator RC - Rxd Push-Pull Driver Amplifier Comparator VCC2 Rxd SD Logic & Controlled Driver Control TXD VCC1 GND 19597 Figure 1. Functional Block Diagram Pin Description Pin Number Function Description 1 VCC2 IRED Anode IRED anode to be externally connected to V CC2. An external resistor is only necessary for controlling the IRED current when a current reduction below 300 mA is intended. This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC1 - supply I/O Active 2 IRED Cathode IRED Cathode, internally connected to the driver transistor 3 TXD This Schmitt-Trigger input is used to transmit serial data when SD is low. An on-chip protection circuit disables the IRED driver if the TXD pin is asserted for longer than 80 Ps. I HIGH 4 RXD Received Data Output, push-pull CMOS driver output capable of driving standard CMOS or TTL loads. During transmission the RXD output is active (echo-on). No external pull-up or pull-down resistor is required. Floating with a weak pull-up of 500 k: (typ.) in shutdown mode. O LOW 5 SD Shutdown for IRDA channel only I HIGH 6 VCC1 Supply Voltage 7 RC-Rxd Open Collector Output. This output is active during transmission (echo-on). External pull-up resistor to be added (e.g. 10 k:). O LOW 8 GND Ground Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 347 TFDU7100 Vishay Semiconductors Absolute Maximum Ratings Reference point Pin: GND unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter - 0.3 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 + 6.0 V Supply voltage range, transmitter - 0.5 V < VCC1 < 6 V VCC2 - 0.5 + 6.0 V Voltage at RXD - 0.5 V < VCC1 < 6.0 V VRXD - 0.5 VCC1 + 0.5 V Vin - 0.5 + 6.0 V 10 mA Voltage at all inputs and outputs Vin > VCC1 is allowed Input currents For all Pins, Except IRED Anode Pin Typ. Output sinking current Power dissipation see derating curve Junction temperature TJ Ambient temperature range (operating) Storage temperature range Soldering temperature PD 125 °C - 30 + 85 °C Tstg - 40 + 100 °C 260 °C IIRED (DC) 125 mA IIRED (RP) 700 mA Repetitive pulse output current, pin 1 to pin 2 < 0.3 Ps, ton < 25 % Virtual source size Method: (1 - 1/e) encircled energy d Maximum Intensity for Class 1 IEC60825-1 or EN60825-1, edition Jan. 2001, operating below the absolute maximum ratings Ie *) mA mW Tamb See recommended solder profile (see figure 5) Average output current, pin 1 25 250 2.5 2.8 mm *) (500)**) mW/sr Due to the internal limitation measures the device is a "class1" device under all conditions. **) IrDA specifies the max. intensity with 500 mW/sr. Definitions: In the Vishay transceiver data sheets the following nomenclature is used for defining the IrDA operating modes: SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the basic serial infrared standard with the physical layer version IrPhy 1.0 MIR: 576 kbit/s to 1152 kbit/s FIR: 4 Mbit/s VFIR: 16 Mbit/s MIR and FIR were implemented with IrPhy 1.1, followed by IrPhy 1.2, adding the SIR Low Power Standard. IrPhy 1.3 extended the Low Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. A new version of the standard in any case obsoletes the former version. With introducing the updated versions the old versions are obsolete. Therefore the only valid IrDA standard is the actual version IrPhy 1.4 (in Oct. 2002). www.vishay.com 348 Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors Electrical Characteristics Transceiver Tested at Tamb = 25 °C, VCC1 = VCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Test Conditions Supply voltage Symbol Min VCC1 2.7 Typ. Max Unit 5.5 V Dynamic supply current SD = Low, Ee = 1 klx**), VCC1 ICC1 5 mA Average dynamic supply current, transmitting IIRED = 300 mA, 25 % Duty Cycle ICC 6.5 mA Shutdown supply current*) SD = High, T = 25 °C, Ee = 0 klx ISD Operating temperature range 2 mA TA - 30 + 85 °C Output voltage low, RXD Cload = 15 pF VOL - 0.5 0.15 x VCC1 V Output voltage high, RXD IOH = - 500 μA IOH = - 250 μA, Cload = 15 pF VOH 0.8 x VCC1 0.9 x VCC1 VCC1 + 0.5 V V RRxd 400 600 k: Input voltage low (TXD, SD) RXD to VCC1 impedance VIL - 0.5 0.5 V Input voltage high (TXD, SD) VIH VCC1 - 0.5 6 V -2 +2 μA + 150 μA 1 μA 5 pF Input leakage current (TXD, SD) Vin = 0.9 x Vlogic IICH Controlled pull down current SD, TXD = "0" or "1" 0 < Vin < 0.15 VCC1 IIrTX SD, TXD = "0" or "1" Vin > 0.7 VCC1 IIrTX Input capacitance (TXD, SD) *) -1 500 0 CI The Remote Control receiver is always on. The shutdown function is used for disabling the IrDA channel, only **) Standard Illuminant A Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 349 TFDU7100 Vishay Semiconductors Optoelectronic Characteristics Receiver Tested at Tamb = 25 °C, VCC1 = vCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameter Minimum detection threshold irradiance, SIR mode*)**) Maximum irradiance in angular Test Conditions Symbol 9.6 kbit/s to 115.2 kbit/s O = 850 nm - 900 nm D = 0 °, 15 ° Ee 576 kbit/s to 4 Mbit/s O = 850 nm - 900 nm D = 0 °, 15 ° Ee O = 850 nm - 900 nm Ee Min O = 850 nm - 900 nm tr, tf < 40 ns, tpo = 1.6 μs at f = 115 kHz, no output signal allowed Ee Max Unit 45 (4.5) 81 (8.1) mW/m2 100 (10) 190 (19) 5 (500) range***) Logic LOEW receiver input irradiance Typ. (μW/cm2) mW/m2 (μW/cm2) kW/m2 (mW/cm2) 4 (0.4) mW/m2 (μW/cm2) Rise time of output signal 10 % to 90 %, CL = 15 pF tr (RXD) 40 Fall time of output signal 90 % to 10 %, CL = 15 pF tf (RXD) 40 RXD pulse width of output signal, 50 % SIR Mode Input pulse length 1.4 μs < PWopt < 25 μs tPW Input pulse length 1.4 μs < PWopt < 25 μs - 25 °C < T < 85 °C**) tPW 1.5 1.8 2.6 μs RXD pulse width of output signal, 50 % MIR mode Input pulse length PWopt = 217 ns, 1.152 Mbit/s tPW 110 250 270 ns RXD pulse width of output signal, 50 % FIR mode Input pulse length PWopt = 125 ns, 4.0 Mbit/s tPW 100 140 ns Input pulse length PWopt = 250 ns, 4.0 Mbit/s tPW 225 275 ns tPW 225 Stochastic jitter, leading edge Receiver start-up time *) 2.1 ns ns μs 275 ns Ee = 200 mW/m2, 4 Mbit/s 20 ns Ee = 200 mW/m2, 1.152 kbit/s 40 ns Input irradiance = 100 mW/m2, 576 kbit/s 80 ns Ee = 200 mW/m2, d 115.2 kbit/s 350 ns After completion of shutdown programming sequence Power on delay 500 μs IrDA low power specification is 90 mW/m2. Spec takes a window loss 10 % into account. **) IrDA sensitivity definition: Minimum Irradiance Ee In Angular Range, power per unit area. The receiver must meet the BER specification while the source is operating at the minimum intensity in angular range into the minimum half-angle range at the maximum Link Length. ***) Maximum Irradiance Ee In Angular Range, power per unit area. The optical delivered to the detector by a source operating at the maximum intensity in angular range at Minimum Link Length must not cause receiver overdrive distortion and possible related link errors. If placed at the Active Output Interface reference plane of the transmitter, the receiver must meet its bit error ratio (BER) specification For more definitions see the document “Symbols and Terminology” on the Vishay Website (http://www.vishay.com/docs/82512/82512.pdf). www.vishay.com 350 Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors Remote Control Receiver*) Tested at Tamb = 25 °C, VCC1 = vCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing Test Conditions Symbol Minimum detection threshold irradianceRC Parameter O = 950 nm D = 0 °, 15 °, RC5/RC6, 36 kHz EeRC 0.4 (0.04) Maximum detection threshold irradiance O = 950 nm D = 0 °, 15 °, 36 kHz to 38 kHz EeRC 0.4 (0.04) 1 mW/m2 (μW/cm2) Minimum detection threshold irradiance) O = 850 nm - 970 nm EeRC 0.4 (0.04) 2 mW/m2 (μW/cm2) Maximum detection threshold irradiance O = 850 nm - 900 nm EeRCmax 30 - 0.5 Output voltage low, RCRXD CLoad = 15 pF, RL = 10 k: VOLRC Output voltage high, RCRXD CLoad = 15 pF, RL = 10 k: VHLRC *) Min Typ. Max Unit mW/m2 (μW/cm2) W/m2 0.15 x VCC1 VCC1 V V Timing parameters are equivalent to TSOP1238, see that datasheet. **) The RCRXD output is an open collector output, therefore a load resistor is mandatory. Optoelectronic Characteristics Transmitter Tested at Tamb = 25 °C, VCC1 = vCC2 = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing Symbol Min Typ. Max Unit IRED operating current limitation Parameter No external resistor for current limitation*) Test Conditions ID 450 550 650 mA IRED operating current limitation for low power FIR mode VCC2 = 3.3 V, RS = 18 : Ie 10 t mW/sr ID 90 mA Output leakage IRED current Txd = 0 V, 0 < VCC1 < 5.5 V IIRED -1 1 μA Output radiant intensity D = 0 °, 15 °, full IrDA cone, TXD = High, SD = Low, no external resistor for current limitation*) Ie 50 70 300 mW/sr D=0° TXD = High, SD = Low, no external resistor for current limitation*) Ie 80 200 400 mW/sr VCC1 = 5.0 V, D = 0 °, 15 ° TXD = Low or SD = High (Receiver is inactive as long as SD = High) Ie 0.04 mW/sr Peak - emission wavelength**) Op Spectral bandwidth 'O Optical rise time, fall time Optical output pulse duration Optical overshoot 880 900 45 nm nm tropt, tfopt 10 40 ns Input pulse width 1.63 Ps, 115.2 kbit/s (SIR) topt 1.6 1.63 1.75 μs Input pulse width 217 ns, 1.152 Mbit/s topt 207 217 227 ns Input pulse width 125 ns, 4.0 Mbit/s topt 117 125 133 ns Input pulse width 250 ns, 4.0 Mbit/s topt 242 250 258 ns Input pulse width 0.1 μs, < tTXD < 100 μs topt Input pulse width 0.1 μs, tTXD t 100 μs topt tTXD tTXD μs 100 μs 25 % *) Using an external current limiting resistor is allowed and recommended to reduce IRED intensity and operating current when current reduction is intended to operate at the IrDA low power conditions. E.g. for VCC2 = 3.3 V a current limiting resistor of Rs = 56 : will allow a power minimized operation at IrDA low power conditions. **) Note: Due to this wavelength restriction compared to the IrDA spec of 850 nm to 900 nm the transmitter is able to operate as source for the standard Remote Control applications with codes as e.g. Philips RC5/RC6® or RECS 80. Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 351 TFDU7100 Vishay Semiconductors Recommended Circuit Diagram Operated at a clean low impedance power supply the TFDU7100 needs no additional external components beside a resistor at the open collector RCRXD-output. However, depending on the entire system design and board layout, additional components may be required (see figure 2). VIRED R1 VCC R2 C1 IRED Anode VCC1 C2 GND R3 Ground RCRXD RC Rxd SD SD TXD Txd RXD Rxd IRED Cathode 19600 Figure 2. Recommended Application Circuit The capacitor C1 is buffering the supply voltage and eliminates the inductance of the power supply line. This one should be a Tantalum or other fast capacitor to guarantee the fast rise time of the IRED current. The resistor R1 is the current limiting resistor, which may be used to reduce the operating current to levels below the specified controlled values for saving battery power. Vishay’s transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring should be avoided. The inputs (Txd, SD) and the output Rxd should be directly (DC) coupled to the I/O circuit. The capacitor C2 combined with the resistor R2 is the low pass filter for smoothing the supply voltage. R2, C1 and C2 are optional and dependent on the quality of the supply voltages VCCx and injected noise. An unstable power supply with dropping voltage during transmission may reduce the sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as close as possible to the transceiver power supply pins. An Tantalum capacitor should be used for C1 while a ceramic capacitor is used for C2. In addition, when connecting the described circuit to the power supply, low impedance wiring should be used. When extended wiring is used the inductance of the power supply can cause dynamically a voltage drop at VCC2. Often some power supplies are not apply to follow the fast current rise time. In that case another 4.7 PF (type, see table under C1) at VCC2 will be helpful. The RCRXD output is an open collector driver. Therefore it needs an external pull-up resistor of e.g. 10 k: R3. Under extreme EMI conditions as placing an RFtransmitter antenna on top of the transceiver, we recommend to protect all inputs by a low-pass filter, as a minimum a 12 pF capacitor, especially at the Rxd port. The transceiver itself withstands EMI at GSM frequencies above 500 V/m. When interference is observed, it is picked up by the wiring to the inputs. It is verified by DPI measurements that as long as the interfering RF - voltage is below the logic threshold levels of the inputs and equivalent levels at the outputs no interference is expected. One should keep in mind that basic RF - design rules for circuit design should be taken into account. Especially longer signal lines should not be used without termination. See e.g. "The Art of Electronics" Paul Horowitz, Winfield Hill, 1989, Cambridge University Press, ISBN: 0521370957. Recommended Application Circuit Components Component Recommended Value C1 4.7 PF, 16 V 293D 475X9 016B C2 0.1 PF, Ceramic VJ 1206 Y 104 J XXMT R1 depends on current to be adjusted R2 47 :, 0.125 W CRCW-0805-47R R3 10 k:, 0.125 W CRCW-0805-10K www.vishay.com 352 Vishay Part Number Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors I/O and Software In the description, already different I/Os are mentioned. Different combinations are tested and the function verified with the special drivers available from the I/O suppliers. In special cases refer to the I/ O manual, the Vishay application notes, or contact directly Vishay Sales, Marketing or Application. Mode Switching The TFDU7100 is in the SIR mode after power on as a default mode, therefore the FIR data transfer rate has to be set by a programming sequence using the TXD and SD inputs as described below. The low frequency mode covers speeds up to 115.2 kbit/s. Signals with higher data rates should be detected in the high frequency mode. Lower frequency data can also be received in the high frequency mode but with reduced sensitivity. To switch the transceivers from low frequency mode to the high frequency mode and vice versa, the programming sequences described below are required. The SD-pulse duration for programming should be limited to a maximum of 5 Ps avoiding that the transceiver goes into sleep mode. After that TXD is enabled as normal TXD input and the transceiver is set for the high bandwidth (576 kbit/ s to 4 Mbit/s) mode. Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "LOW". Wait ts > 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of Txd, which determines speed setting). 4. TXD must be held for th > 200 ns. After that TXD is enabled as normal TXD input and the transceiver is set for the lower bandwidth (9.6 kbit/s to 115.2 kbit/s) mode. 50 % SD ts High : FIR 50 % TXD Setting to the High Bandwidth Mode (0.576 Mbit/s to 4.0 Mbit/s) th 50 % Low : SIR 1. Set SD input to logic "HIGH". 2. Set TXD input to logic "HIGH". Wait ts > 200 ns. 3. Set SD to logic "LOW" (this negative edge latches state of TXD, which determines speed setting). 4. After waiting th > 200 ns Txd can be set to logic "LOW". The hold time of Txd is limited by the maximum allowed pulse length. 14873 Figure 3. Mode Switching Timing Diagram Table 2. Truth table Inputs Outputs Remark SD TXD Optical input Irradiance mW/m2 RXD Transmitter RC-RXD high x x weakly pulled (500 k: to VCC1) 0 x low high x active low (echo) Ie x low high > 100 Ps x high 0 x x low > specified RC sensitivity (RCprotocol) x 0 active low (envelope) low low <4 high 0 x low low > minimum irradiance in angular range (IrDA) < maximum irradiance in angular range (IrDA) low (active) 0 x low low > maximum irradiance in angular range (IrDA) x 0 x Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 353 TFDU7100 Vishay Semiconductors Recommended Solder Profiles 260 240 220 200 180 160 140 120 100 80 60 40 20 0 on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 10 s max. at 230 °C 240 °C max. 275 2...4 °C/s T ≥ 255 °C for 10 s....30 s 250 160 °C max. 225 90 s max. 2...4 °C/s 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 0 50 19535 100 150 200 250 300 350 2 °C...3 °C/s 50 Time/s 25 Figure 4. Recommended Solder Profile for Sn/Pb soldering 0 0 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels www.vishay.com 50 100 150 200 Time/s 19532 250 300 350 Figure 5. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 Temperature/°C 180 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 6. RTS Recommendation Current Derating Diagram Figure 7 shows the maximum operating temperature when the device is operated without external current limiting resistor. 90 Ambient Temperature (˚C) Lead (Pb)-Free, Recommended Solder Profile The TFDU7100 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 and 6 are VISHAY's recommended profiles for use with the TFDU7100 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 354 Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 120 s...180 s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 85 80 75 70 65 60 55 50 2.0 18097 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Operating Voltage [V] at duty cycle 20 % Figure 7. Current Derating Diagram Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors Optical Window For the design of the optical windows see application note “Window Size in Housings” TFDU7100 - (Universal) Package 19586 Figure 8. Package drawing TFDU7100, dimensions in mm, tolerance ± 0.2 if not otherwise mentioned 7x1=7 0.6 2.5 1 8 1 19587 Figure 9. Recommended solder pad layout Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 355 TFDU7100 Vishay Semiconductors Tape and Reel Reel dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Figure 10. Reel dimensions, tolerance ±0.2 mm, if not otherwise mentioned Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 www.vishay.com 356 W3 max. Document Number 84773 Rev. 1.1, 27-Sep-06 TFDU7100 Vishay Semiconductors Tape Dimensions 19819 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 11. Tape dimensions, tolerance r0.2 mm, if not otherwise mentioned Document Number 84773 Rev. 1.1, 27-Sep-06 www.vishay.com 357 Vishay Semiconductors www.vishay.com 358 Contents TFDU8108 ............................. 360 VFIR (9.6 kbit/s to 16 Mbit/s) www.vishay.com 359 TFDU8108 Vishay Semiconductors Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s) IrDA® Serial Interface Compatible 2.7 V to 5.5 V Supply Voltage Range Description The TFDU8108 transceiver is part of a family of low power consumption infrared transceiver modules. It is compliant to the IrDA physical layer standard for VFIR infrared data communication, supporting IrDA speeds up to 16 Mbit/s (VFIR) and carrier based remote control modes up to 2 MHz. Integrated within the transceiver module are a PIN photodiode, an infrared emitter (IRED), and a low-power control IC. At a minimum, a Vcc bypass capacitor is the only external component required implementing a complete solution. For limiting the transceiver’s internal power dissipation one additional resistor might be necessary. The transceiver can be operated with logic I/O voltages as low as 1.8 V. 20110 Features • Compliant to the latest IrDA physical layer standard (up to 16 Mbit/s), HP-SIR®, Sharp ASK® and TV Remote Control e3 • Compliant to the IrDA "Serial Interface Specification for Transceivers" • Surface mount Soldering to side and top view orientation • Surface Mount package 9.7 x 4.7 x 4.0 mm3 for side view and top view applications • Operating supply voltage from 2.7 V to 5.5 V • Compliant to all logic levels between 1.8 V and 5 V • TV Remote Control support • Low Power consumption (4.2 mA supply current) • Power Shutdown mode (1 μA shutdown current) • Tri-State-receiver output, weak pull-up when in output is disabled • Built - In EMI Protection - No external shielding necessary • Pin to Pin compatible to legacy Vishay SIR and FIR infrared transceivers • Eye safety class 1 (IEC60825-1, ed. 2001), limited LED on-time, LED current is controlled, no single fault to be considered • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC • Split power supply, can be driven by a separate power supply not loading the regulated supply. U.S. Pat. No. 6,157,476 Applications • Notebook Computers, Desktop PCs, Palmtop computers (Win CE, Palm PC), PDAs • Digital still and video cameras • Printers, fax machines, photocopiers, screen projectors • MP3 players • Telecommunication products (Cellular Phones, Pagers) • Internet TV boxes, Video Conferencing Systems • External infrared adapters (dongles) • Medical and industrial data collection devices Package TFDU8108 Baby Face (Universal) weight 200 mg 19497 www.vishay.com 360 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Ordering Information Part Number Description Qty / Reel TFDU8108-TR3 Oriented in carrier tape for side view surface mounting 1000 pcs TFDU8108-TT3 Oriented in carrier tape for top view surface mounting 1000 pcs TFDU8108 In tube 50 pcs Functional Block Diagram Vcc1 Voltage Regulator ASIC VCC1: Analog supply voltage Vlogic: Digital supply voltage, I/O reference voltage VCC2: Independent supply voltage for the LED driver Vlogic RXD + + + Driver V Serial Interface according the IrDA standard "Serial Interface for Transceiver Control" SCLK: Clock line as timing reference*) TXD: TX/SWDAT - line*) RXD: RX/SRDAT - line*) Vcc2 Logic IRKAT AGC SCLK Serial Interface TXD GND *) see Appendix A for definitions GND 19493 Figure 1. Functional Block Diagram Definitions: In the Vishay transceiver data sheets the following nomenclature is • VFIR: 16 Mbit/s used for defining the IrDA operating modes: MIR and FIR were implement with IrPhy 1.1, followed by IrPhy 1.2, • SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the ba- adding the SIR Low Power Standard. IrPhy 1.3 extended the Low sic serial infrared standard with the physical layer Power Option to MIR and FIR and VFIR was added with IrPhy 1.4. version IrPhy 1.0 A new version of the standard in any case obsoletes the former ver- • MIR: 576 kbit/s to 1152 kbit/s sion. • FIR: 4 Mbit/s Pin Description Pin Number Function Description 1 IRED Anode IRED anode to be externally connected to VCC2 This pin is allowed to be supplied from an uncontrolled power supply seperated from the controlled VCC1 - supply. 2 IRED Cathode IRED Cathode, internally connected to driver transistor 3 TXD 4 RXD 5 SCLK Serial Clock, dynamically loaded 6 VCC Supply Voltage 7 Vlogic Supply voltage for digital part, 1.8 V to 5.5 V, defines logic swing for TXD, SCLK, and RXD 8 GND Ground Document Number 82558 Rev. 1.7, 19-Jan-06 I/O Active Transmit Data Input, dynamically loaded I HIGH Received Data Output, Tri-State CMOS driver output capable of driving a standard CMOS or TTL load. No external pull-up or pulldown resistor is required. Pin is current limited for protection against programming errors. The output is loaded with a weak 500 k: pullup, when in SD mode. The RXD echoes the optical TXD signal duration transmission. O LOW I HIGH www.vishay.com 361 TFDU8108 Vishay Semiconductors BabyFace (Universal) "U" Option BabyFace (Universal) IRED 1 Detector 2 3 4 5 6 7 8 17087 Figure 2. Pinning Absolute Maximum Ratings Reference point Ground (pin 8) unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage range, transceiver Parameter 0 V < VCC2 < 6 V Test Conditions VCC1 - 0.5 6 V Supply voltage range, transmitter 0 V < VCC1 < 6 V VCC2 - 0.5 6 V Supply voltage range, transceiver logic 0 V < VCC1 < 6 V Vlogic - 0.5 6 V VIREDA - 0.5 6 V VTXD - 0.5 Vlogic + 0.5 V V RXD - 0.5 Vlogic + 0.5 V 10 mA IRED anode voltage Transmitter data input voltage Receiver data output voltage Input currents Typ. For all pins, except IRED anode pin Output sinking current Power dissipation See derating curve, figure 7 Junction temperature Storage temperature range Repetitive pulse output current < 90 μs, ton < 20 % Virtual source size Method: (1 - 1/e) encircled energy Maximum Intensity for Class 1 Operation of IEC825-1 or EN60825-1, edition Jan. 2001 IrDA® specified maximum limit mA mW 125 °C - 25 + 85 °C Tstg - 40 + 100 °C 260 °C IIRED (DC) 130 mA IIRED (RP) 600 See recommended solder profile (see figures 4 to 6) Average output current 25 350 Tamb TJ Ambient temperature range (operating) Soldering temperature PD d 2.5 2.8 mA mm Internal limitation to class 1 500 mW/sr Due to the internal limitation measures the device is a "class1" device. It will not exceed the IrDA® intensity limit of 500 mW/sr. www.vishay.com 362 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Electrical Characteristics Transceiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Symbol Min Max Unit Supply voltage VCC1 Parameter Test Conditions VCC1 2.7 Typ 5.5 V Supply voltage Vlogic Vlogic 1.8 5.5 V Dynamic supply current Receive mode only. In transmit mode, add the averaged programmed current of IRED current as ICC2 Dynamic supply current Active, SIR, Ee = 0 klx (idle) T = - 25 °C to 85 °C ICC1 Dynamic supply current Active, VFIR, Ee = 0 klx, (idle) T = - 25 °C to 85 °C Dynamic supply current Dynamic supply current 0.8 2.5 mA ICC1 10 mA active, no load Ee = 0 klx, (idle) T = - 25 °C to 85 °C Ilogic 5 μA Ee = 1 klx*) receive mode, Ilogic 1 mA 2 2 μA μA 5 μA + 85 °C 0.4 V EEo = 100 mW/m2 (9.6 kbit/s to 4.0 Mbit/s), RL = 10 k: to Vlogic = 5 V, CL = 15 pF T = - 25 °C to 85 °C Standby supply current Standby supply current Inactive, set to shutdown mode T = 25 °C, Ee = 0 klx T = 25 °C, Ee = 1 klx*) **) ISD Shutdown mode, **) T = 85 °C ISD Operating temperature range TA Output voltage low Cload = 15 pF, Vlogic = 3 V, IOLO < + 500 μA VOLO Output voltage high Cload = 15 pF, Vlogic = 5 V, IOHI < - 250 μA VOHI - 25 0.8 x Vlogic Input voltage high (TXD, SCLK) V IL - 0.5 Input voltage high (TXD, SCLK) V IH Vlogic - 0.3 logic decision level (TXD, SCLK) ***) VIL Input leakage current (TXD, SCLK) IL Input capacitance CI V 0.5 6 0.5 x Vlogic - 10 V V + 10 μA 5 pF *) Standard illuminant A. **) In shutdown condition the device is not ambient light sensitive. ***) The device will work with less tight levels than specified min/max values of the logic input voltage. It is recommended to use the specified min/max values to minimize operating/standby supply currents. Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 363 TFDU8108 Vishay Semiconductors Optoelectronic Characteristics Receiver Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typ. Max Unit Minimum detection threshold irradiance Parameter 9.6 kbit/s to 115.2 kbit/s, SIR O = 850 nm to 900 nm Test Conditions Ee 25 40 mW/m2 Minimum detection threshold irradiance 1.152 Mbit/s, MIR O = 850 nm to 900 nm Ee 65 90 mW/m2 Minimum detection threshold irradiance 4 Mbit/s, FIR O = 850 nm to 900 nm Ee 85 90 mW/m2 Minimum detection threshold irradiance 16 Mbit/s, VFIR O = 850 nm to 900 nm Ee 140 200 mW/m2 Maximum detection threshold irradiance O = 850 nm to 900 nm Ee 5 Ee 4 Logic LOW receiver input irradiance Symbol Min 10 kW/m2 mW/m2 RXD pulse width of output signal, 50 % SIR mode Input pulse length 20 Ps, 9.6 kbit/s tPW 1.3 2.6 μs RXD pulse width of output signal, 50 % SIR mode Input pulse length 1.41 Ps, 115.2 kbit/s tPW 1.3 2.6 μs RXD pulse width of output signal, 50 % MIR mode Input pulse length 217 ns, 1.152 Mbit/s tPW 200 260 ns RXD pulse width of output signal, 50 % FIR mode Input pulse length 125 ns, 4 Mbit/s tPW 105 145 ns RXD pulse width of output signal, 50 % FIR mode Input pulse length 250 ns, 4 Mbit/s tPW 225 285 ns RXD pulse width of output signal, 50 % Input pulse length 16 Mbit/s, VFIR 39.5 ns < Pwopt < 43 ns tPW 32 42 52 ns RXD rise time of output signal 20 % to 80%, CL = 15 pF tr (RXD) 2 5 15 ns RXD fall time of output signal 20 % to 80%, CL = 15 pF tr (RXD) 2 5 15 ns RXD fall time of output signal 90 % to 10%, CL = 15 pF tr (RXD) 5 RXD Jitter, leading edge, SIR mode 125 30 ns Input irradiance = 40 mW/m2, 115.2 kbit/s 350 ns RXD Jitter, leading edge, MIR mode Input irradiance = 100 mW/m2, 1.152 Mbit/s 40 ns RXD Jitter, leading edge, FIR mode Input irradiance = 100 mW/m2, 4 Mbit/s 20 ns RXD Jitter, leading edge Input irradiance = 200 mW/m2, 16 Mbit/s, VFIR mode 5 7 ns RXD output pulse delay tRXDdel 1 μs Latency tLAT 55 100 μs Receiver Startup Time tPOR 100 500 μs www.vishay.com 364 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Transmitter Tamb = 25 °C, VCC = 2.7 V to 5.5 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Test Conditions Symbol IRED operating current internally controlled*) Parameter VCC1 = 3.3 V, the maximum current is limited internally. An external resistor can be used to reduce the power dissipation at higher operating voltages, see derating curve. ID 8 16 32 64 128 256 512 Max. output radiant intensity VCC = 3.3 V, D = 0 °,15 ° Txd = High, R1 = 0 : programmed to max. power level Ie 0.3 Output radiant intensity VCC = 5.0 V, D = 0 °, 15 ° Txd = Low, programmed to shutdown mode Ie TXD pulse width of output signal, 50 % Input pulse length 1.63 μs, 115.2 kbit/s tPW TXD pulse width of output signal, 50 % Input pulse width 0.1 μs < tTXD < 60 Ps tPW 20 60 μs TXD pulse width of output signal, 50 % Input pulse length 250 ns, (FIR, double pulse) tPW 240 260 ns TXD pulse width of output signal, 50 % Input pulse length 217.0 (MIR) t PW 115 260 ns TXD pulse width of output signal, 50 % FIR mode Input pulse length 125 ns (FIR) tPW 115 135 ns TXD pulse width of output signal, 50 % Input pulse length 41.7 ns tPW 38.3 45.0 ns Input pulse width tTXD t 60 μs Output radiant intensity, angle of half intensity D Peak - emission wavelength Op Spectral bandwidth Optical rise time, fall time Optical overshoot Min Typ. 1.45 Max mA 600 mW/sr/mA 0.04 mW/sr 2.20 μs tTXD 125 ± 24 870 ° 900 40 tropt, tfopt Unit nm nm 19 ns 15 % *) Programmable using the"serial interface“ programming sequence, see Appendix A for implementation guidance and Appendix B for intensity values and range. Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 365 TFDU8108 Vishay Semiconductors Recommended Circuit Diagram Operated with a low impedance power supply the TFDU8108 series devices need no external components. However, depending on the entire system design and board layout, additional components may be required (see figure 3). VCC2 R1 Recommended Application Circuit Components Component Recommended Value C1 4.7 μF, 16 V C2 0.1 μF, Ceramic R1 Recommended for VCC2 t 4 V Depending on current limit R2 < 10 :, 0.125 W VCC1 IRED Cathode R2 Rxd C1 GND C2 I/O and Software IRED Anode For operating the device from a Controller I/O a driver software must be implemented. Rxd Txd Vcc SCLK Mode Switching and Programming GND Vlogic The generic IrDA "Serial Interface programming" needs no special settings for the device. Only the current control table must be taken into account. For the description see the Appendix A, B and C and the IrDA document "Serial Interface specification for transceivers" Vlogic SCLK Txd 17089 Figure 3. Recommended Application Circuit All external components (R, C) are optional Vishay transceivers integrate a sensitive receiver and a built-in power driver. The combination of both needs a careful circuit board layout. The use of thin, long, resistive and inductive wiring must be avoided. The inputs (TXD, SCLK) and the output Rxd should be directly DC-coupled to the I/O circuit. R1 is used for reducing the power dissipation when operating the device at a supply voltage of VCC2 > 4 V. For increasing the max. output power of the IRED, the value of the resistor should be reduced. It should be dimensioned to keep the IRED anode voltage below 4 V for using the full temperature range. For device and eye protection the pulse duration and current are internally limited. R2, C1 and C2 are optional and dependent on the quality of the supply voltage VCC1 and injected noise. An unstable power supply with dropping voltage during transmission may reduce sensitivity (and transmission range) of the transceiver. The placement of these parts is critical. It is strongly recommended to position C2 as near as possible to the transceiver power supply pins. An electrolytic capacitor should be used for C1 while a ceramic capacitor is used for C2. www.vishay.com 366 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Recommended Solder Profiles 260 240 220 200 180 160 140 120 100 80 60 40 20 0 The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 275 90 s max. 225 50 Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 2...4 °C/s 0 T ≥ 255 °C for 10 s....30 s 250 120 s...180 s 100 19535 150 200 250 300 350 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 Figure 4. Recommended Solder Profile for Sn/Pb soldering 2 °C...3 °C/s 50 25 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. Document Number 82558 Rev. 1.7, 19-Jan-06 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 5. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 Temperature/°C 180 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Figure 6. RTS Recommendation Current Derating Diagram 600 Peak Operating Current (mA) Lead (Pb)-Free, Recommended Solder Profile The TFDU8108 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 5 and 6 are VISHAY's recommended profiles for use with the TFDU8108 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 500 400 300 200 Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25 %. 100 0 - 40 - 20 14875 0 20 40 60 80 100 120 140 Temperature (°C) Figure 7. Current Derating Diagram www.vishay.com 367 TFDU8108 Vishay Semiconductors TFDU8108 - BabyFace (Universal) Package (Mechanical Dimensions) 18473-1 Figure 8. Mechanical drawing, dimensions in mm, tolerance ± 0.2 mm if not otherwise shown www.vishay.com 368 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Recommended SMD Pad Layout 7x1=7 0.6 ( 0.7) 2.5 ( 2.0) 1 8 1 16524-1 Figure 9. Mechanical drawing, dimensions in mm, tolerance ± 0.2 mm if not otherwise shown Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Figure 10. Reel dimensions, dimensions in mm, tolerance ± 0.2 mm Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 Document Number 82558 Rev. 1.7, 19-Jan-06 W3 max. www.vishay.com 369 TFDU8108 Vishay Semiconductors Tape Dimensions 19822 Drawing-No.: 9.700-5251.01-4 Issue: 3; 02.09.05 Figure 11. Tape drawing,TFDU8108 for top view mounting, tolerance ± 0.1 mm www.vishay.com 370 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors 19875 Drawing-No.: 9.700-5297.01-4 Issue: 1; 04.08.05 Figure 12. Tape drawing, TFDU8108 for side view mounting after mounting, tolerance ± 0.1 mm Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 371 TFDU8108 Vishay Semiconductors Tube drawing 19496 Figure 13. Tube drawing www.vishay.com 372 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Appendix A Serial Interface Implementation Basics of the IrDA Definitions The data lines are multiplexed with the transmitter and receiver signals and separate clocks are used since the transceivers respond to the same address. When no infrared communication is in progress and the serial bus is idle, the IRTX line is kept low and IRRX is kept high. OFE A IRTX/SWDAT TX/SWDAT IRRX/SRDAT Infrared Controller RX/SRDAT SCLK1 Optical Transceiver SCLK SCLK2 VCC OFE B TX/SWDAT RX/SRDAT Optical Transceiver SCLK 17092 Figure 14. Interface to Two Infrared Transceivers Connector Infrared Controller IRTX+/SWDAT+ IRTX-/SWDATIRRX+/SRDAT+ IRRX-/SRDATSCLK+ SCLK- Shielded Cable VCC GND VCC LVDS Transceiver GND TX/SWDAT RX/SRDAT SCLK Optical Transceiver A_SL GND 17093 Figure 15. Infrared Dongle with Differential Signaling Functional description The serial interface is designed to interconnect two or more devices. One of the devices is always in control of the serial interface and is responsible for starting every transaction. This device functions as the bus master and is always the infrared controller. The infrared transceivers act as bus slaves and only respond to transactions initiated by the master. A bus transaction is made up of one or two phases. The first phase is the Command Phase and is present in every transaction. The second phase is the Response Phase and is present only in those transactions in which data must be returned from the slave. If the operation involves a data transfer from the slave, there will be a Response Phase following the Command Phase in which the slave will output the data. The Response Phase, if present, must begin 4 clock cycles after the last bit of the Command Phase, as shown in figures 9 and 10, otherwise it is assumed that there will be no response phase and the master can terminate the transaction. Document Number 82558 Rev. 1.7, 19-Jan-06 The SCLK line is always driven by the master and is used to clock the data being written to or read from the slave. This line is driven by a totem-pole output buffer. The SCLK line is always stopped when the serial interface is idle to minimize power consumption and to avoid any interference with the analog circuitry inside the slave. There are no gaps between the bytes in either the Command or Response Phase. Data is always transferred in Little Endian order (least significant bit first). Input data is sampled on the rising edge of SCLK. IRTX/SWDAT output data from the controller is clocked by SCLK falling edge. IRRX/SRDAT output data from the slave is clocked by SCLK rising edge. Each byte of data in both Command and Response Phases is preceded by one start bit. The data to be written to the slave is carried on the IRTX/SWDAT line. When the control interface is idle, this line carries the infrared data signal used to drive the transmitter LED. When the first low-to-high transition on SCLK is detected at the beginning of the command sequence, the slave will disable the transmitter LED. When the first low-to-high transition on SCLK is detected at the beginning of the command sequence, the slave will disable the transmitter LED. The infrared controller then outputs the command string on the IRTX/ SWDAT line. On the last SCLK cycle of the command sequence the slave re-enables the transmitter LED and normal infrared transmission can resume. No transition on SCLK must occur until the next command sequence otherwise the slave will disable the transmitter LED again. Read data is carried on the IRRX/SRDAT line. The slave disables the internal signal from the receiver photo diode during the response phase of a read transaction. The addressed slave will output the read data on the IRRX/SRDAT line regardless of the setting of the Receiver Output Enable bit in the main control register (main-ctrl-0). Non addressed slaves will tri-state the IRRX/SRDAT line. When the transceiver is powered up, the IRTX/SWDAT line should be kept low and SCLK should be cycled at least 30 times by the infrared controller before the first command is issued on the IRTX/SWDAT line, see figure 11. This guarantees that the transceiver interface circuitry will properly initialize and be ready to receive commands from the controller. In case of a multiple transceiver configuration, only one transceiver should have the receiver output enabled. www.vishay.com 373 TFDU8108 Vishay Semiconductors A series resistor (approx. 200 :) should be placed on the receiver output from each transceiver to prevent large currents in case a conflict occurs due to a programming error. Note: Generally the abbreviations IRTX/IRRX and TXD/RXD are used for the data transmission lines for the optical communication. IRTX/IRRX is mostly used at the controller, TXD/RXD at the transceiver 19505 Figure 19. Write Data Waveform with Extended Index START ADDRESS & CONTROL SCLK IRTX/ SWDAT IRRX/ SRDAT 19506 Figure 20. Read Data Waveform 19502 Figure 16. Special Command Waveform START ADDRESS,INDEX, DIR. START DATA SCLK IRTX/ SWDAT 19507 Figure 21. Read Data Waveform with Extended Index IRRX/ SRDAT Note: During a read transaction the infrared controller sets the 19503 IRTX/SWDAT line high after sending the address and index byte Figure 17. Write Data Waveform (or bytes). It will then set it low two clock cycles before the end of the transaction. It is strongly recommended that optical transceiv- Note: If the APEN bit in control register 0 is set to 1, the internal sig- ers monitor this line instead of counting clock cycles in order to nal from the receiver photo diode is disconnected and the IRRX/ detect the end of the read transaction. This will always guarantee SRDAT line is pulsed low for one clock cycle at the end of a write correct operation in case two or more transceivers from different or special command. manufacturers are sharing the serial interface. > 30 CLOCK CYCLES SCLK IRTX/ SWDAT IRRX/ SRDAT 19504 Figure 18. Initial Reset Timing www.vishay.com 374 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Switching Characteristics Maximum capacitive load = 20 pF*) Parameters Test Conditions Min. Max. Unit tCKp Symbol SCLK Clock Period Rising edge of SCLK to next rising edge of SCLK 250 infinity ns tCKh SCLK Clock High Time At 2.0 V for single-ended signals 60 ns tCKI SCLK Clock Low Time At 0.8 V for single-ended signals 80 ns tDOtv Output Data Valid (from infrared controller) After falling edge of SCLK tDOth Output Data Hold (from infrared controller) After falling edge of SCLK tDOrv Output Data Valid (from optical transceiver) After rising edge of SCLK 40 ns tDOrh Output Data Hold (from optical transceiver) After rising edge of SCLK 40 ns 40 0 ns ns tDOrf Line Float Delay After rising edge of SCLK tDIs Input Data Setup Before rising edge of SCLK 10 ns tDIh Input Data Hold After rising edge of SCLK 5 ns 60 ns *) Maximum capacitive load = 20 pF. That is is different from "Serial interface - specification". For the bus protocol see "RECOMMENDED SERIAL INTERFACE FOR TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA". In Appendix B the transceiver related data are given. Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 375 TFDU8108 Vishay Semiconductors Appendix B Application Guideline In the following some guideline is given for handling the TFDU8108 in an application ambient, especially for testing. It is also a guideline for interfacing with a controller. We recommend to use for first evaluation the Vishay IRM1802 controller. For more information see the special data sheet. Driver software is available on request. Contact [email protected]. Serial Interface Capability of the Vishay IrDA Transceivers Abstract A serial interface allows an infrared controller to communicate with one or more infrared transceivers. The basic specification of the IrDA specified interface is described in "Serial Interface for Transceiver Control, v 1.0a", IrDA. This part of the document describes the capabilities of the serial interface implemented in the Vishay IrDA transceivers TFDU8108. The VFIR (16 Mbit/s) device TFDU8108 and the FIR device TFDU6108 (4 Mbit/s) are using the same interface specification (with specific identification and programming). IrDA Serial Interface Basics The "Serial Interface for Transceiver Control" is a master/slave synchronous serial bus, which uses the TXD and RXD as data lines and the SCLK as clock line with a minimum period of 250 ns. The transceiver works always as slave and jumps into a control mode on the first rising edge of the clock line remaining there until the command phase is finished. After power-on, it is required to initialize the transceiver by at least 30 clock cycles of SCLK with TXD continuously low before starting programming. If TXD gets active (high) during the initialization period the initialization must be repeated. A data word consists of one byte preceded by one start bit. The specified serial interface allows the communication between infrared controller and transceiver through write and read transactions. In two register blocks with different functions all data is stored for operating the interface. The Main Control Registers allow write and read transactions and here the executable configuration of the device is stored. The Extended Indexed Registers contain the description of the supported functionality of the device and can be read only. Power-on After power on the transceiver is in the default mode shown in table B1. Addressing The transceiver is addressable by three address bits. There are individual and common addresses with the values shown in table B2. Registers Data Depth In general data registers use a data depth of eight bits. Sometimes it is not necessary to implement the full depth. In such cases the invisible bits are considered as a zero. Registers The register content is listed in the tables B4 to B7. Data Acknowledgment Data acknowledgement generated by the slave is available if the APEN bit is set to 1 in the common control register, see the "main_ctrl_0" register values table B4. In IrDA default state this functionality is disabled. It is recommended to enable this function. Table B1: Power-on default mode Function sleep RXD (Receive) disable (floating tri-state) TXD_LED (Emitter driver): disable APEN (Acknowledgment) disable Infrared Operating Mode (Speed) SIR Transmitter Power (Intensity setting) max. SIR power level www.vishay.com 376 TFDU8108 Power Mode (active or sleep) Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Table B2: Addressing Description Address value ADDR [2:0] Individual address 010 Common (broadcast) address 111 Table B3: Index Commands Commands INDEX [3:0] Mode write/read Actions Register Name 0h W/R Common control main-ctrl-0 register [4:0] 00h 1h W/R Infrared mode main-ctrl-1 register [7:0] 00h 2h W/R TXD power level main-ctrl-2 register [7:4] 70h 3h - Bh X Not used Ch X Not used Dh W Reset transceiver, Only one byte! R Not used Eh X Not used Fh W Not used R Extended indexing Data Bits Data TFDU8108 default Note: The main_ctrl_1 register is written software dependent on the offset value stored in ext_ctrl_7 and ext_ctrl_8 registers. The main_ctrl_1 register can be set to the following values, shown in the table. Tables B4 to B7: Control Register Values The status of the entire transceiver is stored in the control registers. Table B4: Register main-ctrl-0 Command structure: C 0 0 0 0 bit 0 INDEX [3:0], 0h bit 1 bit 2 1 bit 0 ADDR [0:2] C is the transfer direction: bit 1 bit 2 0 bit 4 0 0 0 DATA [7:0] x C = 1: WRITE or RESET transaction x C = 0: READ transaction Main-ctrl-0, register values Value Function bit 0 PM SL - Power Mode Select low power-mode (shutdown (sleep) mode) normal operation power mode shutdown Default bit 1 RX OEN - Receiver Output Enable IRRX/SRDAT line disable (tristated) IRRX/SRDAT line enabled disabled bit 2 TLED EN - Transmitter LED Enable disabled enabled bit 3 not used bit 4 APEN*) disabled not used don’t acknowledge acknowledge disabled *) APEN - Acknowledge Pulse Enable, (optional) This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will be set low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast) transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1. Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 377 TFDU8108 Vishay Semiconductors Table B5: Register main-ctrl-1 Command structure: C 1 0 0 0 bit 0 INDEX [3:0], 1h bit 1 bit 2 1 bit 0 bit 1 bit 2 bit 3 ADDR [0:2] bit 4 bit 5 bit 6 bit 7 DATA [7:0] Main-ctrl-1, register values DATA [7:0] Function 00h SIR (default) 01h MIR 02h FIR 03h Apple Talk® (FIR functionality) 05h VFIR - 16 08h Sharp IR® (SIR functionality) 20h IrDA CIR Depending on the values of "ext_ctrl_7" and "ext_ctrl_8" check for correct main_ctrl_1. In case of an error, the transceiver will load 00h into the main_ctrl_1 register and will not give an acknowledgement. Table B6: Register main-ctrl-2 Command structure: C 1 0 0 bit 0 INDEX [3:0], 1h bit 1 bit 2 1 bit 0 bit 1 bit 2 bit 3 ADDR [0:2] bit 4 bit 5 bit 6 bit 7 DATA [7:0] Main-ctrl-2, DATA [7:0], bit 4 to bit 7 DATA [7:0] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TXD IRED [mA] le [mW/sr] 15° (typ. on axis) Link distance on axis Recommended for 8xhFxh 1 x x x x x x x 512 140 (240) VFIR > 0.7 m, FIR > 1 m (link distance limited by receiver sensitivity) VFIR/FIR standard 7xh*) 0 1 1 1 x x x x 256 > 70 (120) *) SIR >1 m FIR > 0.7 m, VFIR > 0.5 m SIR, More Ext. FIR LP 6xh 0 1 1 0 128 35 (60) SIR > 0.70 m FIR > 0.50 m VFIR > 0.30 m Extended FIR Low Power 5xh 0 1 0 1 64 16 (30) SIR > 0.5 m FIR > 0.30 m VFIR > 0.30 m VFIR Low Power / FIR Low Power 4xh 0 1 0 0 (48) 3xh 0 0 1 1 32 8 (19) SIR > 0.35 m FIR > 0.20 m VFIR > 0.20 m SIR Low Power 2xh 0 0 1 0 16 40 (10) 1xh 0 0 0 1 8 (5) 0xh 0 0 0 0 x x x x 0 SIR Low Power, min without optical windows SIR > 0.15 m FIR > 0.10 m VFIR > 0.10 m Close distance, e.g. Docking station 0 *) Device is tested under this condition. Default setting is 7xh. www.vishay.com 378 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors IRED current If [mA] Intensity Ie [mW/sr] d[m] at Ee = d[m] at Ee = d[m] at Ee = d[m] at Ee = 100 mW/m2 40 mW/m2 90 mW/m2 225 mW/m2 512 240 1.55 2.45 1.63 1.03 256 120 1.10 1.73 1.15 0.73 128 60 0.77 1.22 0.82 0.52 0.37 64 30 0.55 0.87 0.58 48 22.5 0.47 0.75 0.50 0.32 32 15 0.39 0.61 0.41 0.26 16 7.5 0.27 0.43 0.29 0.18 8 3.75 0.19 0.31 0.20 0.13 Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range, on axis, for information only. IRED current If [mA] Intensity Ie [mW/sr] d[m] at Ee = d[m] at Ee = d[m] at Ee = d[m] at Ee = 100 mW/m2 40 mW/m2 90 mW/m2 225 mW/m2 512 140.0 256 70.0 1.18 1.87 1.25 0.79 0.15 0.23 1.16 128 35.0 0.10 0.59 0.94 0.62 64 0.39 17.5 0.42 0.66 0.44 0.28 48 13.1 0.36 0.57 0.38 0.24 32 8.8 0.30 0.47 0.31 0.20 16 4.4 0.21 0.33 0.22 0.14 8 2.2 0.15 0.23 0.16 0.10 Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range; 15° off-axis, for information only. Table B7: Reading Extended Indexed Registers Note: Read Data with Extended Index E_INDX is one of the Extended Indexed Registers. It must be addressed via a precursor of writing all 1s into the normal index location, thus INDEX[3:0] = Fh. It is an 8 bit address value, which must be followed by 3 SCLK cycles plus a start clock before reading the DATA value. As in the normal Read Transaction, the input signal, TXD, must be set one clock cycle on LOW (master ready to receive) and then on HIGH for the next 3 SCLKs and continuing through the entire Response Phase. The corresponding reaction of the RXD line and the 8 bit DATA value is then read out as depicted below, noting that the Read Data value comes after the 3 SCLK cycles. Read Command structure: 0 1 C 1 1 1 bit 0 INDEX [3:0], Fh bit 1 bit 2 1 bit 0 bit 1 bit 2 ADDR [0:2] bit 3 bit 4 bit 5 bit 6 bit 7 E_INDEX [0:7] Response: bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 DATA [0:7] Extended Indexed Registers Action E_INDEX [7:0] Register name DATA [7:0] in TFDU8108 Definition default in the TFDU8108 Manufacture ID 00h ext_ctrl_0 0Bh Chip information (Factory reserved) Read Support, Device ID 01h ext_ctrl_1 C6h Device ID Receiver Recovery Time Power On Stabilization 04h ext_ctrl_4 23h 100μs to 500μs Receiver Stabilization 05h ext_ctrl_5 30h 0 Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 379 TFDU8108 Vishay Semiconductors Action E_INDEX [7:0] Register name DATA [7:0] in TFDU8108 SCLK Max. Frequency (4MHz) Common Capabilities Definition default in the TFDU8108 4 MHz 06h ext_ctrl_6 03h Low Power Mode and Programmable Transmitter Power supported All listed in Receive Mode Supported Infrared Modes 07h ext_ctrl_7 2Fh Supported Infrared Modes 08h ext_ctrl_8 01h Sharp IR Mask ID: Released Ver. Set, followed by Revision Letter F0h ext_ctrl_240 0Ah Chip information (Factory reserved) Invalid Commands Handling Reset Commands and register addresses, which cannot be encoded by the Serial Interface, are ignored by the internal logic as invalid data. Below the different types invalid command handling and the slave reaction is shown. Two ways to set the serial interface into a defined state are available: The brute force method is to switch the power off and on and let the device recover in the default state. The software method is to set the IRTX/SWDAT line low for t 30 clock cycles of the clock line. If this line is detected as low for t 30 clock cycles the transceiver is set into the command start state and all registers are set to the as default implemented values. Table B8: Invalid Commands Handling Description Master Command Slave Reaction on RXD/SRDAT Invalid command in read mode Index [3:0] & C = 0 no reaction Invalid command in write mode Index [3:0] & C = 1 No acknowledgement generating independent of the value of APEN Valid command in invalid read mode Index [3:0] & C = 0 no reaction Valid command in invalid write mode Index [3:0] & C = 1 No acknowledgement generating independent of the value of APEN Valid command in valid write mode and invalid data Index [3:0] & C = 1 No acknowledgement generating independent of the value of APEN ADDR [2:0] = 111 & C = 0 no reaction Broadcast address in read mode No reaction means that the slave does not start the respond phase. C is the transfer direction: • C = 1: WRITE or RESET transaction • C = 0: READ transaction www.vishay.com 380 Document Number 82558 Rev. 1.7, 19-Jan-06 TFDU8108 Vishay Semiconductors Appendix C SCLK Serial Interface Programming Guide The serial interface port of TFDU8108 enables an interface controller to communicate using a standardized protocol, recall module ID and capability information, and implement receiver bandwidth mode switching, LED power control, shutdown and some other functions. This interface requires three signal lines: a clock line (SCLK) that is used for timing, and two unidirectional lines multiplexed with the transmitter (TXD, write) and receiver (RXD, read) signal lines. Programming sequence formats supported are • one-byte special commands • two-byte write commands • two-byte read commands • three-byte read commands One-byte special command sequences are reserved for time-critical actions, while the two-byte write command is predominantly used to set basic transceiver characteristics. More information can be found in the IrDA document "Serial Interface for Transceiver Control, v 1.0a" on http://www.IrDA.org. Serial Interface Timing Specifications In general, serial interface programming sequences are similar to any clocked-data protocol: • there is a range of acceptable clock rates, measured from rising edge to rising edge • there is a minimum data setup time before clock rising edges • there is a minimum data hold time after clock rising edges Recommended programming timing: • fSCLK < 8 MHz (according to the Serial Interface Standard, quasi-static programming is possible) • TSCLK > 125 ns, • Tsetup > 10 ns, • Thold > 10 ns The timing diagrams, see figure 22, show the setup and hold time for the serial interface programming sequences. TX 125 ns < Tclk 18496 Tsetup > 10 ns Thold > 10 ns s Figure 22. Programming Sequence Protocol Specifications The serial interface protocol is a command-based communication standard and allows for the communication between controller and transceiver by way of serial programming sequences on the clock (SCLK), transmit (TXD), and receive (RXD) lines. The SCLK line is used as a clocking signal and the transmit/ receive lines are used to write/read data information. The protocol requires all transceivers to implement the write commands, but does not require the readportion of the protocol to be implemented (though all transceivers must at least follow the various commands, even if they perform no internal action as a result). This serial interface follows but does not support all read/ write commands or extended commands, supporting only the special commands and basic write/read commands. Write commands to the transceiver take place on the SCLK and TXD lines and may use the RXD line for acknowledgment. A command may be directed to a single transceiver on the SCLK, TXD and RXD bus by specifying a unique three-bit transceiver address, or a command may be directed to all transceivers on the bus by way of a special three-bit broadcast address code. The Vishay VFIR transceiver TFDU8108 will respond to transceiver address 010 and the broadcast address 111 only; it ignores all other transceiver addresses. All commands have a common "header" or series of leading bits, which take the form shown below. first bit sent to transceiver 0 1 0/1 Sync. Bits R/W 0/1 I0 I1 last bit sent to transceiver. I2 I3 Commands Index A0 A1 A2 ... ... Transceiver Address The bits shown are placed on the TXD (DATA) line and clocked into the transceiver using the rising edge of the SCLK signal. Only the data bits are shown as it is assumed that a clock is always present, and that the transceiver samples the data on the rising edge of each clock pulse. Note: as illustrated in the diagram above, the protocol uses "Little Endian" ordering of bits, so that the LSB is sent first, and the MSB is sent last for register addresses, transceiver addresses, and read/ write data bytes. The notation that follows presents all addresses and data in LSB-to-MSB order (bits 0, 1, 2, 3, ... 7) unless otherwise stated. Document Number 82558 Rev. 1.7, 19-Jan-06 www.vishay.com 381 TFDU8108 Vishay Semiconductors One-byte Special Commands One-byte special commands are used for time-critical transceiver commands, such as full transceiver reset. A total of six special commands are possible, although only one command is available on the TFDU8108. 0 1 1 I0 Sync. Bits W Special Command Code I1 I2 I3 A0 A1 A2 0 Transceiver Address 0 Stop Bits Command Programming Sequence (Binary) RESET (Set all registers to default value) 011 1011 010 00 Two-byte Write Commands Two-byte write commands are used for setting the contents of transceiver registers which control transceiver such as shutdown/enable, receiver mode, LED power level, etc. The register space requires four register address bits (INDEX), although three codes are used for controlling the transceiver (see above). The 1111 escape code is for extended commands. The 3bit transceiver address (ADDR) is for selecting the destination, e.g. 010 to TFDU8108 and 001 to TFDU6108. The second byte is data field (DATA) for setting the characteristics of the transceiver module, e.g. SIR mode (00) or VFIR (05) when the register address is 0001. The basic two-byte write command is illustrated below: 1 1 Sync. Bits 0 W I0 I1 I2 Commands Index I3 A0 A1 A2 A3 D0..07 Transceiver Address 8 Data Bits Some important serial interface sequences are shown in table C1. 0 0 Stop Bits programming Table C1: Serial interface programming sequences Command DATA Normal (Enable all) 0Fh 01 1 0000 010 1 11110000 00 Shutdown 00h 01 1 0000 010 1 00000000 00 Receiver Mode main_ctrl_1 DATA SYNC / C / INDEX / ADDR / 1 / DATA / STOP SIR 00h 01 1 1000 010 1 00000000 00 MIR 01h 01 1 1000 010 1 10000000 00 FIR 02h 01 1 1000 010 1 01000000 00 Apple Talk 03h 01 1 1000 010 1 11000000 00 VFIR 05h 01 1 1000 010 1 10100000 00 Sharp-IR 08h 01 1 1000 010 1 00010000 00 LED Intensity main_ctrl_2 DATA 8 mA 1xh 01 1 0100 010 1 00001000 00 16 mA 2xh 01 1 0100 010 1 00000100 00 32 mA 3xh 01 1 0100 010 1 00001100 00 64 mA 5xh 01 1 0100 010 1 00001010 00 128 mA 6xh 01 1 0100 010 1 00000110 00 256 mA 7xh 01 1 0100 010 1 00001110 00 512 mA Fxh 01 1 0100 010 1 00001111 00 www.vishay.com 382 TFDU8108 Programming Sequence (Transceiver address: 010) Common Ctrl main_ctrl_0 Document Number 82558 Rev. 1.7, 19-Jan-06 Contents TFDU2201 ............................. 384 Emitter/ Detector pair www.vishay.com 383 TFDU2201 Vishay Semiconductors Low Profile Transceiver Module PIN Photodiode and Infrared Emitter Description The miniaturized TFDU2201 is an ideal PIN photodiode transmitter combination in a unique package for applications in telecommunications like mobile phones and pagers. The device is mechanically designed for lowest profile with a height of only 2.8 mm. The device is designed to be compatible to the IrDA standard when using an external receiver IC and IRED driver. 18170 Features • Package dimension: L 7.3 mm x W 4.55 mm x H 2.75 mm • SMD side view e3 • Fast PIN Photodiode for SIR and FIR applications • Detector with high efficiency and high speed at low bias voltage • Only 30 mA IRED peak current during transmission for IrDA SIR low power standard • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96/EC Applications • Mobile Phones, Pagers, Personal Digital Assistants (PDA) • Handheld battery operated equipment Parts Table Part Description Qty / Reel TFDU2201-TR1 Orientated in carrier tape for side view mounting 750 pcs. TFDU2201-TR3 Orientated in carrier tape for side view mounting 2250 pcs. Pin Description Pin Number Function Description 1 IRED GND IRED Cathode, Ground, to be used as heat sink 2 IRED GND IRED Cathode, Ground, to be used as heat sink 3 IRED Anode IRED Anode, to be driven by a current source 4 NC The pins 4, 5, 6 are internally not connected. No modulated sources or voltages > 5 V should be applied to these pins. It is recommended to ground these pins. In this case the lead frame structure will work as an internal EMI shield. 5 6 7 Danode Detector Anode 8 Dcathode Detector Cathode www.vishay.com 384 Document Number 82539 Rev. 1.3, 21-Mar-06 TFDU2201 Vishay Semiconductors Pinout TFDU2201 weight 100 mg 18228 Absolute Maximum Ratings Parameter Test Conditions Photo pin diode, reverse voltage range Symbol Min Vr - 0.3 Typ. Average IRED current < 90 μs, ton < 20 % IRED, reverse voltage range V 10 mA IIRED(DC) 100 mA IIRED(RP) 550 mA VrIRED Power dissipation See Figure 3 - 0.3 Ptot Juntion temperature Storage temperature range Soldering temperature See the chapter “Soldering conditions” for lead-bearing and Pbfree processing Virtual source size Method: (1 - 1/e) encircled energy 5 V 200 mW 125 °C Tamb - 25 + 85 °C Tstg - 40 + 85 °C 260 °C TJ Ambient temperature range (operating) Unit 12 Photo pin diode, reverse photo current Repetitive pulsed IRED current Max d 2 mm Compatible to Class 1 opration of IEC 60825 or EN60825 with worst case IrDA SIR pulse pattern, 115.2 kbit/s Electrical Characteristics Transceiver Tested for the following parameters (T = 25 °C, unless otherwise stated) Parameter Supported data rates Test Conditions Symbol Min Base band Typ. 9.6 Max Unit 4000 kbit/s Optoelectronic Characteristics Receiver Tested for the following parameters (T = 25 °:C, unless otherwise stated) Parameter Spectral sensitivity Test Conditions | D | d ± 15 °, Vr = 2 V, O = 875 nm Bias voltage range, detector Symbol Min Typ. Max Unit SO 1.0 1.2 1.8 nA/(mW/m2) 12 VRev Reverse leakage current 0.2 Spectral bandwith Max. operating irradiance | D | d ± 90 °C, VCC = 2 V Rise time at load : R = 50 : Vr = 2 V, O = 875 nm Fall time at load : R = 50 : Vr = 2 V, O = 875 nm Document Number 82539 Rev. 1.3, 21-Mar-06 O 800 Ee, max 8000 V nA 950 nm 15000 W/m2 tr 40 ns tr 40 ns www.vishay.com 385 TFDU2201 Vishay Semiconductors Transmitter Tested for the following parameters (T = 25 °C, unless otherwise stated) Test Conditions Symbol Forward current operating condition for low power IrDA operation Parameter Ie = 4 to 28 mW/sr in | D | d ± 15 ° IF1 Output radiant intensity | D | d ± 15 °, IF1 = 35 mA, 25 % duty cycle Ie 4 | D | d ± 15 °, IF1 = 350 mA, 25 % duty cycle Ie 35 Forward voltage If = 50 mA Peak emission wavelength Min Typ. Unit mA 8 14 mW/sr mW/sr Vf 1.2 1.45 V Op 880 900 nm Spectral emission bandwith Optical rise/fall time Max 30 2 MHz square wave signal (duty cycle 1 : 1) 45 nm 38 ns Recommended Solder Profiles Solder Profile for Sn/Pb Soldering 10 s max. at 230 °C 240 °C max. Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 0 50 19535 100 150 200 250 300 350 Time/s Figure 1. Recommended Solder Profile for Sn/Pb soldering Lead (Pb)-Free, Recommended Solder Profile The TFDU2201 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 2 and 3 are VISHAY's recommended profiles for use with the TFDU2201 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. www.vishay.com 386 Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 275 T ≥ 255 °C for 10 s....30 s 250 225 Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Temperature/°C Temperature (°C) 260 240 220 200 180 160 140 120 100 80 60 40 20 0 Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 2 °C...3 °C/s 50 25 0 0 19532 50 100 150 200 Time/s 250 300 350 Figure 2. Solder Profile, RSS Recommendation Document Number 82539 Rev. 1.3, 21-Mar-06 TFDU2201 Vishay Semiconductors Current Derating Diagram 280 Tpeak = 260 °C max 260 240 600 220 Temperature/°C 180 Peak Operating Current (mA) 200 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 500 400 300 Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25 %. 200 100 0 0 50 100 150 200 250 300 0 - 40 - 20 Time/s Figure 3. RTS Recommendation 14875 0 20 40 60 80 100 120 140 Temperature (°C) Figure 4. Current Derating Diagram Package Dimensions 19821 Drawing-No.: 6.550-5185.01-4 Issue: 5; 02.09.05 Figure 5. Package drawing, TFDU2201 Document Number 82539 Rev. 1.3, 21-Mar-06 www.vishay.com 387 TFDU2201 Vishay Semiconductors Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 24 330 60 24.4 30.4 23.9 27.4 www.vishay.com 388 W3 max. Document Number 82539 Rev. 1.3, 21-Mar-06 TFDU2201 Vishay Semiconductors Tape Dimensions 19820 Drawing-No.: 9.700-5227.01-4 Issue: 3; 03.09.99 Figure 6. Tape drawing, TFDU2201 for side view mounting Document Number 82539 Rev. 1.3, 21-Mar-06 www.vishay.com 389 Vishay Semiconductors www.vishay.com 390 Contents TOIM4232 ..............................392 Endec www.vishay.com 391 TOIM4232 Vishay Semiconductors SIR Endec for IrDA Applications Integrated Interface Circuit Description The TOIM4232 Endec IC provides proper pulse shaping for the SIR IrDA® front end infrared transceivers as of the 4000-series. For transmitting the TOIM4232 shortens the RS232 output signal to IrDA compatible electrical pulses to drive the infrared transmitter. In the receive mode, the TOIM4232 stretches the received infrared pulses to the proper bit width depending on the operating bit rate. The IrDA bit rate varies from 2.4 kbit/s to 115.2 kbit/s.The TOIM4232 is using a crystal clock 3.6864 MHz for its pulse stretching and shortening. The clock can be generated by the internal oscillator. An external clock can be used, too. The TOIM4232 is programmable to operate from 1200 bit/s to 115.2 kbit/s by the communication software through the RS232 port. The output pulses are software programmable as either 1.627 μs or 3/16 of bit time. The typical power consumption is very low with about 10 mW in operational state and in the order of a few microwatts in standby mode. 18080 Features • Pulse shaping function (shortening and stretching) used in SIR IrDA® applications e3 • Directly interfaces the SIR transceiver TFD..- and TFB..- series to an RS232 port • Programmable baud clock generator (1200 Hz to 115.2 kHz), 13 baud rates • 3/16 bit pulse duration or 1.627 μs pulse selectable • SO16 - package • 2.7 V to 3.6 V operation voltage, 5 V tolerant inputs • Low operating current • Lead (Pb)-free device • Qualified for lead (Pb)-free and Sn/Pb processing (MSL4) • Device in accordance with RoHS 2002/95/EC and WEEE 2002/96EC ULC Technology: High performance gate array package using multiple metal layer CMOS technology featuring sub-micron channel lengths (0.35 μm). Ordering Information Part Number TOIM4232-TR1 Qty / Reel 500 pcs Block Diagram Vcc TD_IR TD_232 Endec RD_232 RD_IR TD_LED Baud Generator BR/D RD_LED S1 S2 Logic RESET Vcc_SD Osci llator GND X1 X2 18079 www.vishay.com 392 Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors Pin Assignment and Description Pin Number Symbol Description 1 RESET Resets all internal registers. Initially must be HIGH ("1") to reset internal registers. When HIGH, the TOIM4232 sets the IrDA default bit rate of 9600 bit/s, sets pulse width to 1.627 μs. The VCC_SD output is simply an inverted reset signal which allows to shut down of a TFDx4x00 transceiver when applying the reset signal to the TOIM4232. When using devices with external SD like TFDU4203, the reset line can be used directly as shut down signal. RESET pin can be controlled by either the RTS or DTR line through RS232 level converter. Minimum hold time for resetting is 1 μs. Disables the oscillator when active. I/O Active 2 BR/ D Baud Rate control/ Data. BR/ D = 0, data communication mode: RS232 TXD data line is connected (via a level shifter) to TD_232 input pin. The TXD - signal is appropriately shortened and applied to the output TD_IR, driving the TXD input of the IR transceiver. The RXD line of the transceiver is connected to the RD_IR input. This signal is stretched to the correct bit length according to the programmed bit rate and is routed to the RS232 RXD line at the RD_232 pin. BR/ D = 1, Programming mode: Data received from the RS232 port is interpreted as Control Word. The Control Word programs the baud rate width will be effective as soon as BR/ D return to LOW. 3 RD_232 Received signal data output of stretched signal to the RS232 RXD line (using level converter). O HIGH 4 TD_232 Input of the signal to be transmitted from the RS232 port TXD line (passing the level converter). I HIGH 5 VCC_SD Outputs an inverted RESET signal. Can be used to shut down the power supply of a 4000 series transceiver (e.g., TFDU4100). VCC shutdown output function. This pin can be used to shut down a transceiver (e.g., TFDx4xxx). Output polarity: Inverted RESET input. O LOW 6 X1 Crystal input clock, 3.6864 MHz nominal. Input for external clock *) I 7 X2 Crystal *) I HIGH 8 GND Ground in common with the RS232 port and IrDA transceiver ground 9 TD_LED Transmit LED indicator driver. Use 180 : current limiting resistor in series to LED to connect to VCC. (VCC = 3.3 V) O LOW 10 RD_LED Receive LED indicator driver. Use 180 : current limiting resistor in series to LED to connect to VCC. (VCC = 3.3 V) O LOW 11 NC No connection 12 S1 User Programmable Bit. Can be used to turn ON/ OFF a front-end infrared transceiver (e.g., an infrared module at the adapter front) O LOW 13 S2 User Programmable Bit. Can be used to turn ON/ OFF a front-end infrared transceiver (e.g., an infrared module at the adapter back) O LOW 14 TD_IR Data output of shortened signal to the infrared transceiver O HIGH 15 RD_IR Data input from the infrared transceiver, min. pulse duration 1.63 μs **) I LOW 16 VCC Supply voltage I *) Crystal should be connected as shown in figure 2. In addition connect a 100 k: resistor from Pin 6 to Pin 7 and from Pin 6 and Pin 7 a 22 pF capacitor to ground, respectively. When an external clock is available connect it to Pin 6 leaving Pin 7 open. The external resistor of 100 k: is used to accelerate the start of oscillation after reset or power - on. The value depends on the "Q" of the resonator. With low Q resonators it is not necessary. The start - up time of the oscillator is between 30 μs (with piezo resonators) and above 2 ms with high Q quartzes. **) All Vishay Semiconductor SIR transceivers fulfill this condition Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 393 TOIM4232 Vishay Semiconductors Block diagram of application circuit RESET VCC_SD DTR VCC RTS BR/D TD_IR TXD TXD TD_232 RD_IR RXD RD_232 RXD RS232 9 pin connector Operating the interface circuit at a PC COM - port. When operating directly with an UART with 3 V - or 5 V - logic, in the application circuit no level converter is necessary. TOIM4232 Level converter X1 R1 X2 100 kΩ TFDU4100 TFDU420x TFDU4300 3.6864 MHz C1 C2 2 x 22 pF 18081 Table 1. Recommended Application Circuit Components Component Recommended Value Vishay Part Number C1 C2 R1 Quartz Crystal 22 pF 22 pF 100 k: 3.686400 MHz VJ 1206 A 220 J XAMT VJ 1206 A 220 J XAMT CRCW-1206-1003-F-RT1 XT49S - 20 - 3.686400M Absolute Maximum Ratings Parameter Test Conditions Supply voltage Input voltage Symbol Min VCC - 0.5 3.6 V - 0.5 5.5 V - 0.5 VCC + 0.5 V 8 mA All pins Output voltage All pins Output sinking current, max All pins Typ. IO Junction temperature, max TJ Ambient temperature (operating) Tamb - 25 Storage temperature Tstg - 25 Soldering temperature Tsldr Max Unit 125 °C 85 °C 85 °C 260 °C DC Characteristics Parameter Test Conditions Symbol Min Typ. Max Unit VCC 2.7 3.3 3.6 V Test Conditions Symbol Min Typ. Max Unit Inputs tolerate levels as high as 5.5 V max. all inputs are Schmitt trigger inputs VIH 2.0 Operating voltage VCC = 3.3 V ± 5 %, operating temperature = - 55 °C to + 125 °C Parameter Input HIGH voltage Input LOW voltage V VIL Input Schmitt trigger hysteresis 0.8 Vhyst 0.6 V V PA Input leakage no pull-up/down VIN = VDD or GND IL - 10 Output HIGH voltage IOH = - 2.0 mA VOH 2.0 IOH = - 0.5 mA VOH 2.4 Output LOW voltage IOL = + 2.0 mA VOL 0.4 V Consumption current standby Inputs grounded, no output load VCC = 3.3 V, T = 25 °C ISB 1 μA Consumption current dynamic Inputs grounded, no output load VCC = 3.3 V, T = 25 °C ICC www.vishay.com 394 ±1 10 V V 2 mA Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors Operation Description Figure 2 shows a typical example of an RS232 port interface. The TOIM4232 connects to an RS232 level converter on one side, and an infrared transceiver on the other. The internal TOIM4232 baud rate generator can be software controlled. When BR/D = 0, the TOIM4232 interprets the channels TD_232 to TD_IR and RD_IR to RD_232 as data channels. On the other hand, whenever BR/D = 1, the TOIM4232 interprets TD_232 as Control Word for setting the Baud rate. The Baud rate can be programmed to operate from 1200 bit/s to 115.2 kbit/s. As RS232 level converter, EIA232 or MAX232 or equivalent are recommended. When using the TOIM4232 directly connected to an UART it is compatible to 5 V TTL and 3.3 V CMOS logic. Typical external resistors and capacitors are needed as shown in the TFDx4xxx references. The output pulse duration can also be programmed, see chapter "Operation Description". It is strongly recommended using 1.627 μs output pulses to save battery power. As frequency determining component a Vishay XT49M Crystal is recommended, when no external clock is available. We strongly recommend not to use this 3/16 mode because 3/16 pulse length at lower bit rates consumes more power than the shorter pulse. At a data rate of 9600 bit/s, the ratio of power consumption of both modes is a factor of 12 (!). Control Byte (8 bit) First Character X S1 Second Character S0 B3 B2 B1 B0 LSB X: Do not care S1, S2: User programmable bit to program the outputs S1 and S2 S0: Irda pulse select S0 = (1): 1.627 μs pulses S0 = (0): 3/16 bit time pulses, not recommended B0 .. B3: Baud rate select words Example: To set TOIM4232 at COM2 port (2F8) to 9600 bit/s with 3/16 bit time pulse duration send to the TOIM4232 in programming mode in e.g. "Basic" OUT &H2F8, (&H6) For same port, 9600 bit/s and 1.627 μs pulse duration send OUT &H2F8, (&H16) For additionally activating S1 send OUT &H2F8, (&H36) Baud Rate Select Words B3 0 Programming the TOIM4232 For correct, data rate dependent timing the TOIM4232 is using a built-in baud rate generator. This is used when no external clock is not available as in RS232 IR-dongle applications. For programming the BR/D pin has to be set active, BR/D = 1. In this case the TOIM4232 interprets the 7 LSBs at the TD_232 input as a Control Word. The operating baud rate will change to its supposedly new baud rate when the BR/D returns back to LOW ("0") Set the UART to 8 bit, no parity, 1 stop bit. S2 1 B2 B1 B0 2nd Char Baud Rate 0 0 0 0 115.2 k 0 0 1 1 57.6 k 0 1 0 2 38.4 k 0 1 1 3 19.2 k 1 0 0 4 14.4 k 1 0 1 5 12.8 k 1 1 0 6 9.6 k 1 1 1 7 7.2 k 0 0 0 8 4.8 k 0 0 1 9 3.6 k 0 1 0 A 2.4 k 0 1 1 B 1.8 k 1 0 0 C 1.2 k 1 0 1 D forbidden 1 1 0 E forbidden 1 1 1 F forbidden Note: IrDA standard only supports 2.4 kbit/s, 9.6 kbit/s, 19.2 kbit/s, 57.6 kbit/s, and 115.2 kbit/s. Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 395 TOIM4232 Vishay Semiconductors Software for the TOIM4232 UART Programming For proper operation, the RS232 must be programmed (using 8 bit, 1 stop, no parity) to send a two character control word, YZ. The control word YZ is composed of two characters, written in hexadecimal, in format: YZ. The transfer rate for programming must be identical with the formerly programmed data rate, or after resetting the TOIM4232, the default rate of 9600 bit/s is used. Step. RESET BR/ D TD_UART RD_UART RD_IR TD_IR Description and Comments 1 High X X X X X Resets all internal registers. Resets to IrDA default data rate of 9600 bit/s 2 Low X X X X X Wait at least 2 ms, to allow start-up of internal clock. When external clock is used: Wait at least 7 μs. 3 Low High X X X X Wait at least 7 μs. TOIM4232 now is set to the Control Word programming mode 4 Low High YZ with Y = 1 for 1.627 μs Y=0 3/16 bit length X X X Sending the Control Word YZ. Examples: Send "1Z" if 1.627 μs pulses are intended to be used. Otherwise send "0Z" for 3/16 bit period pulses. "Y6" keeps the 9.6 kbit/s data rate. Z = 0 sets to 115.2 kbit/s, see programming table. Wait at least 1 μs for hold-time. 5 Low Low DATA DATA DATA DATA With BR/D = 0, TOIM4232 is in the data communication mode. Both RESET and BR/D must be kept LOW ("0") during data transmission. Reprogramming to a new data rate can be resumed by restarting from step 3. The UART itself also must set to the correct data rate *). *) For programming the UART, refer to e.g., National Semiconductor’s data sheet of PC 16550 UART V CC R3 MAX3232CSE 1 C+ + C3 3 4 VCC TOIMx232 16 1 U1 C1- V+ C2+ V- 2 C5 + 6 C7 + 2 3 C6 + C4 4 + 5 GND C2- 15 5 6 11 10 12 9 T1IN T2IN R1OUT R2OUT T1OUT T2OUT R1IN R2IN 14 7 13 8 7 8 Reset U2 Vcc BR/Data RD IR RD 232 TD IR TD 232 S2 V CC SD S1 X1 NC X2 RD LED GND TD LED C10 16 2 + 15 R4 R6 TFDU4100 C11 4 14 6 13 8 IRED Cathode RXD VCC1 GND IRED Anode U4 TXD NC SC 1 3 5 7 12 11 10 9 J1 1 6 2 7 3 8 4 9 5 RXD RTS (BR/D) TXD R1 DTR (Reset) VCC Y1 Application circuit using TFDU4100 with integrated level shifter MAX3232E. When used directly with 3 Vlogic , this one can be omitted Z2 CON9 ext. input max 3.3 V DC J2 1 2 CON2 C1 R2 + C2 C8 C9 16527 www.vishay.com 396 Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors Table 1. Recommended Application Circuit Components Component Recommended Value Vishay Part Number 1 C1 100 nF VJ 1206 Y 104 J XXMT 2 C2 10 μF, 16 V 293D106X9016B2T 3 C3 100 nF VJ 1206 Y 104 J XXMT 4 C4 100 nF VJ 1206 Y 104 J XXMT 5 C5 100 nF VJ 1206 Y 104 J XXMT 6 C6 100 nF VJ 1206 Y 104 J XXMT 7 C7 1 μF. 16 V 293D105X9016A2T 8 C8 22 pF VJ 1206 A 220 J XAMT VJ 1206 A 220 J XAMT 9 C9 22 pF 10 C10 6.8 μF, 16 V 293D 685X9 016B 2T 11 C11 100 nF VJ 1206 Y 104 J XXMT 12 Z2 3.6 V BZT55C3V6 13 R1 5.6 : CRCW-1206-5601-F-RT1 14 R2 100 k: (up to 1 M:, or omitted) CRCW-1206-1003-F-RT1 15 R3 47 : CRCW-1206-47R0-F-RT1 16 R4 20 : CRCW-1206-20R0-F-RT1 17 R6 20 : CRCW-1206-20R0-F-RT1 XT49S - 20 - 3.686400M 18 Y1 3.686400 MHz 19 U1 MAXIM MAX 3232E 20 U2 TOIM4232 21 U3 TFDU4100 22 J1 9 Pin - D - Sub 23 J2 Power connector Cannon 24 PCB VISHAY Dongle_4 R3 TOIMx232 MAX3232CSE 1 16 C+ + C3 V CC 1 U1 3 16 Reset 2 C1- V+ C2+ V- 4 C5 + 6 C7 + 2 U2 Vcc 15 BR/Data RD IR RD 232 TD IR 3 C6 + C4 5 15 C2- S2 VCC SD S1 5 GND T1OUT T2OUT R1IN R2IN Anode 3 6 U4 TXD 5 SD 8 7 GND Vlog 11 X1 14 7 13 8 1 Cathode 4 12 6 T1IN T2IN R1OUT R2OUT 2 + VCC1 13 TD 232 C10 RXD 14 4 + 11 10 12 9 R4 opt. TFDU4300 C11 NC 7 10 X2 RD LED GND TD LED 8 9 J1 1 6 2 7 3 8 4 9 5 RXD DTS (BR/D) TXD R1 DTS (Reset) VCC Y1 Z2 CON9 J2 ext. input max 3,6V DC 1 2 C1 CON2 R2 + C2 C8 C9 Application circuit using TFDU4300 with an integrated level shifter MAX3232E. When used directly with 3 Vlogic, this one can be omitted 18240 Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 397 TOIM4232 Vishay Semiconductors Table 2. Recommended Application Circuit Components Component Recommended Value Vishay Part Number 1 C1 100 nF VJ 1206 Y 104 J XXMT 2 C2 10 μF, 16 V 293D106X9016B2T 3 C3 100 nF VJ 1206 Y 104 J XXMT 4 C4 100 nF VJ 1206 Y 104 J XXMT 5 C5 100 nF VJ 1206 Y 104 J XXMT 6 C6 100 nF VJ 1206 Y 104 J XXMT 7 C7 1 μF, 16 V 293D105X9016A2T 8 C8 22 pF VJ 1206 A 220 J XAMT 9 C9 22 pF VJ 1206 A 220 J XAMT 10 C10 6.8 μF, 16 V 293D 685X9 016B 2T 11 C11 100 nF VJ 1206 Y 104 J XXMT 12 Z2 3.6 V BZT55C3V6 13 R1 5.6 k: CRCW-1206-5601-F-RT1 14 R2 100 k: (up to 1 M:, or omitted) CRCW-1206-1003-F-RT1 15 R3 47 : CRCW-1206-47R0-F-RT1 16 R4 20 : CRCW-1206-20R0-F-RT1 17 Y1 3.686400 MHz XT49S - 20 - 3.686400M 18 U1 MAXIM MAX 3232E 19 U2 TOIM4232 20 U3 TFDU4300 21 J1 9 Pin - D-Sub 22 J2 Power connector 23 PCB www.vishay.com 398 Cannon VISHAY Dongle_4 Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors VCC 3 C1 + R13 +3,3V 2 Q4 1 Q2 + C2 R2 R6 RXD RTS 1 3 Q1 D5 D6 VB1 TXD 3 Q3 1 D4 1 D7 R5 3 2 R1 2 R3 1 6 2 7 3 8 4 9 5 D1 D2 RXD RTS TXD DTR R20 SUB-D 9 3 R9 Reset 1 Q1 2 D3 +3.3 V TD232 RD232 BR/D Reset VCC R12/1 R11 TOIM4232 1 2 3 4 5 QZ1 6 R10 7 8 C3 Reset R12/2 IRED1 U1 VCC BR/Data RD IR RD 232 TD IR TD 232 S2 VCC SD S1 X1 NC X2 RD LED GND TD LED 16 15 14 13 12 2 11 4 10 6 9 8 C4 IRED cathode IRED anode RXD TXD VCC NC Gnd SC U2 1 3 5 7 TFDU4100 + Jumper C5 C6 18082 Install Jumper connection only when VCC SD supplies U2. In that case leave R11 off. Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 399 TOIM4232 Vishay Semiconductors Table 3. Recommended Application Circuit Components Component Recommended Value Vishay Part Number 1 C1 22 μF, 16 V 293D 226X9 016C 2T 2 C2 47 μF, 16 V 293D 476X9 016D 2T 3 C3 22 pF VJ 1206 A 220 J XAMT 4 C4 22 pF VJ 1206 A 220 J XAMT 5 C5 100 nF VJ 1206 Y 104 J XXMT 6 C6 6.8 μF, 16 V 293D 685X9 016B 2T 7 D1 8 D2 1N4148 9 D4 BZT55C4V7 10 D5 1N4148 11 D6 1N4145 12 D7 BZT55C3V9 13 IRED1 TSHF5400 14 Jumper CRCW-1206-000-F-RT1 15 LED1 TLLY4401 16 LED2 TLLG4401 17 Q1 BC817-25 18 Q2 VP 0610 0T 19 Q3 BC817-25 20 Q4 21 QZ1 3.686400 MHz XT49S - 20 - 3.686400M 22 R1 22 k: CRCW-1206-2202-F-RT1 23 R2 10 k: CRCW-1206-1002-F-RT1 24 R3 22 k: CRCW-1206-2202-F-RT1 25 R5 1 k: CRCW-1206-1001-F-RT1 BC817-25 26 R6 47 k: CRCW-1206-4702-F-RT1 27 R9 5.6 k: CRCW-1206-5601-F-RT1 28 R10 100 k: CRCW-1206-1003-F-RT1 29 R11 100 : CRCW-1206-1000-F-RT1 30 R12 20 : CRCW-1206-20R0-F-RT1 21 R13 1 k: CRCW-1206-1001-F-RT1 32 R17 750 : CRCW-1206-7500-F-RT1 CRCW-1206-750-F-RT1 33 R18 750 : 34 VB1 9 Pin - D- Sub 35 PCB Cannon VISHAY Dongle_3 36 U1 TOIM4232 37 U2 TFDU4100 www.vishay.com 400 1N4148 Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors Recommended Solder Profiles Storage The storage and drying processes for all VISHAY transceivers (TFDUxxxx and TFBSxxx) are equivalent to MSL4. The data for the drying procedure is given on labels on the packing and also in the application note "Taping, Labeling, Storage and Packing" (http://www.vishay.com/docs/82601/82601.pdf). 260 240 220 200 180 160 140 120 100 80 60 40 20 0 10 s max. at 230 °C 240 °C max. 2...4 °C/s 160 °C max. 120 s...180 s 90 s max. 2...4 °C/s 275 T ≥ 255 °C for 10 s....30 s 250 225 0 50 100 19535 150 200 250 300 350 Figure 1. Recommended Solder Profile for Sn/Pb soldering Tpeak = 260 °C T ≥ 217 °C for 70 s max 200 Time/s Temperature/°C Temperature (°C) Solder Profile for Sn/Pb Soldering 175 150 30 s max. 125 100 90 s...120 s 70 s max. 2 °C...4 °C/s 75 25 0 0 50 100 150 200 Time/s 19532 250 300 350 Figure 2. Solder Profile, RSS Recommendation 280 Tpeak = 260 °C max 260 240 220 200 180 Temperature/°C Lead (Pb)-Free, Recommended Solder Profile The TOIM4232 is a lead (Pb)-free transceiver and qualified for lead (Pb)-free processing. For lead (Pb)free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu, there are two standard reflow profiles: Ramp-SoakSpike (RSS) and Ramp-To-Spike (RTS). The RampSoak-Spike profile was developed primarily for reflow ovens heated by infrared radiation. With widespread use of forced convection reflow ovens the Ramp-ToSpike profile is used increasingly. Shown below in figure 2 and 3 are VISHAY's recommended profiles for use with the TOIM4232 transceivers. For more details please refer to the application note “SMD Assembly Instructions” (http://www.vishay.com/docs/82602/82602.pdf). A ramp-up rate less than 0.9 °C/s is not recommended. Ramp-up rates faster than 1.3 °C/s could damage an optical part because the thermal conductivity is less than compared to a standard IC. 2 °C...3 °C/s 50 < 4 °C/s 160 1.3 °C/s 140 120 Time above 217 °C t ≤ 70 s Time above 250 °C t ≤ 40 s Peak temperature Tpeak = 260 °C 100 80 < 2 °C/s 60 40 20 0 0 50 100 150 200 250 300 Time/s Wave Soldering For TFDUxxxx and TFBSxxxx transceiver devices wave soldering is not recommended. Figure 3. RTS Recommendation Manual Soldering Manual soldering is the standard method for lab use. However, for a production process it cannot be recommended because the risk of damage is highly dependent on the experience of the operator. Nevertheless, we added a chapter to the above mentioned application note, describing manual soldering and desoldering. Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 401 TOIM4232 Vishay Semiconductors Package Dimensions in mm Package SO16L 10.5 10.1 9.25 8.75 7.5 7.3 2.45 2.25 1.27 0.25 0.10 0.49 0.35 8.89 16 0.3 0.2 10.56 10.15 9 technical drawings according to DIN specifications 13011 1 8 Reel Dimensions Drawing-No.: 9.800-5090.01-4 Issue: 1; 29.11.05 14017 Tape Width A max. N W1 min. W2 max. W3 min. mm mm mm mm mm mm mm 16 330 50 16.4 22.4 15.9 19.4 www.vishay.com 402 W3 max. Document Number 82546 Rev. 1.5, 06-Jun-06 TOIM4232 Vishay Semiconductors Tape Dimensions in mm 18241 Document Number 82546 Rev. 1.5, 06-Jun-06 www.vishay.com 403 Notes Vishay Semiconductors www.vishay.com 404 Worldwide Sales Contacts Online Information For product information and current list of sales offices, representatives and distributors, visit our website: www.vishay.com The Americas EUROPE United States Vishay Americas One Greenwich Place Shelton, CT 06484 United States Ph: +1-402-563-6866 Fax: +1-402-563-6296 Germany Vishay EUROPE SALES GmbH Geheimrat-Rosenthal-Str. 100 95100 Selb Germany Ph: +49-9287-71-0 Fax: +49-9287-70435 Asia France Vishay S.A. 199, BLVD DE LA MADELEINE 06003 NICE, CEDEX 1 France Ph: +33-4-9337-2920 Fax: +33-4-9337-2997 Singapore Vishay intertechnology Asia Pte Ltd. 25 Tampines Street 92 Keppel Building #02-00 Singapore 528877 Ph: +65-6788-6668 Fax: +65-6788-0988 P.R.C. Vishay Trading (Shanghai) Co., Ltd. (SHANGHAI REPRESENTATIVE OFFICE) ROOM D, 15F, SUN TONG INFOPORT PLAZA 55 HUAI HAI WEST ROAD 200030 SHANGHAI P.R.C. PH: +86-21-5258-5000 FAX: +86-21-5258-7979 Netherlands Vishay BCCOMPONENTS B.V. HURKESTRAAT 31 P.O. BOX 8766 5652 AH EINDHOVEN NETHERLANDS Ph: +31-40-2590-700 Fax: +31-40-2590-777 Japan vishay japan CO., LTD. Shibuya 3-chome Square Building 3F 3-5-16 Shibuya Shibuya-Ku Tokyo 150-0002 Japan Ph: +81-3-5464-6411 fax: +81-3-5464-6433 One of the World’s Largest Manufacturers of Discrete Semiconductors and Passive Components 63 Lancaster Avenue Malvern, PA 19355-2143 One of the World’s Largest Manufacturers of Discrete Semiconductors and Passive Components United States D ata B ook infrared data co m m u nication World Headquarters © Copyright Vishay Intertechnology, Inc. Registered Trademarks of Vishay Intertechnology, Inc. All rights reserved. Printed in Germany. Specifications subject to change without notice. w w w. v i s h a y. c o m VSE-DB2802-0610