Design for Manufacturing

Transcription

IPC APEX 2012
Cheryl Tulkoff
Senior Member of the Technical Staff
[email protected]
DfM Course Abstract
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In the electronics industry. the quality and reliability of any product is highly dependent upon the
capability of the manufacturing supplier, regardless of whether it is a contractor or a captured shop.
Manufacturing issues are one of the top reasons that companies fail to meet warranty expectations,
which can result in severe financial pain and eventual loss of market share. What a surprising
number of engineers and managers fail to realize is that focusing on processes addresses only part
of the issue. Design plays a critical role in the success or failure of manufacturing and assembly.
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Designing printed boards today is more difficult than ever before because of the increased lead free
process temperature requirements and associated changes required in manufacturing. Not only has
the density of the electronic assembly increased, but many changes are taking place throughout the
entire supply chain regarding the use of hazardous materials and the requirements for recycling.
Much of the change is due to the European Union (EU) Directives regarding these issues. The
RoHS and REACH directives have caused many suppliers to the industry to rethink their materials
and processes. Thus, everyone designing or producing electronics has been or will be affected.
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This course provides a comprehensive insight into the areas where design plays an important role
in the manufacturing process. This workshop addresses the increasingly sophisticated PCB
fabrication technologies and processes - covering issues such as laminate selection, micro/via and
through hole formation, trace width and spacing, and solder mask and finishes in relation to lead
free materials and performance requirements. Challenges include managing the interconnection of
both through hole and surface mount at the bare board level. The soldering techniques will discuss
on pad design, hole design/annular ring, component location and component orientation. Attendees
will have a unique opportunity to obtain first-hand information on design issues that impact both
leaded and lead free manufacturability.
Instructor Biography
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Cheryl Tulkoff has over 20 years of experience in electronics manufacturing with an
emphasis on failure analysis and reliability. She has worked throughout the electronics
manufacturing life cycle beginning with semiconductor fabrication processes, into printed
circuit board fabrication and assembly, through functional and reliability testing, and
culminating in the analysis and evaluation of field returns. She has also managed no clean
and RoHS-compliant conversion programs and has developed and managed comprehensive
reliability programs.
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Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a
published author, experienced public speaker and trainer and a Senior member of both ASQ
and IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE
(Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability)
sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ
Certified Reliability Engineer.
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She has a strong passion for pre-college STEM (Science, Technology, Engineering, and
Math) outreach and volunteers with several organizations that specialize in encouraging precollege students to pursue careers in these fields.
Cheryl’s Background
• 22 years in Electronics
– IBM, Cypress
Semiconductor, National
Instruments
– SRAM and PLD Fab
(silicon level) Printed
Circuit Board Fabrication,
Assembly, Test, Failure
Analysis, Reliability Testing
and Management
– ISO audit trained, ASQ
CRE, Senior ASQ & IEEE
Member, SMTA, iMAPS
• Random facts:
– Rambling Wreck from
Georgia Tech
– 14 year old son David,
Husband Mike, Chocolate
Lab Buddy
– Marathoner & Ultra
Runner
• Ran Boston 2009 in 3:15
• Ran 100 miles in 24:52 on
2/4-2/5, 2012
– Triathlete – Sprint,
Olympic, and Half.
Ironman finisher in CDA,
Idaho in June ‘10
Course Outline
MODULE 1: INTRODUCTIONS
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Intro to Design for Manufacturing
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Key Global DfM Guidelines
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MODULE 2: INDUSTRY STANDARD DESIGN RULES
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Overview of Industry Standard Organizations
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Examples: IPC, JEDEC, ISO
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Description of common standards in use
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MODULE 3: OVERVIEW OF DFM TASKS
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Types of Review Processes
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Important of Good Communication
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Failure Analysis
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DfM Examples
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MODULE 4: DfM - COMPONENT
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Component Robustness
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Electrolytic Capacitors
V Chip Capacitors
Ceramic Capacitors
Temperature Sensitivity Level
Moisture Sensitivity Level
Pb-free Issues
Case Studies
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MODULE 5: DfM – PRINTED CIRCUIT BOARD
Surface Finishes
Cracking & Delamination
Laminate Selection
PTH Barrel Cracking
CAF
Trace Width and Spacing
Strain/Flexure Issues & Pad Cratering
Cleanliness
Electrochemical Migration
MODULE 6: DfM - SOLDER
Soldering
Lead Free Solder Alloy Update
Copper Dissolution
Mixed Assembly
Case Study
Module 1: Introduction
Introduction to Design for Manufacturing (DfM)
• Definition
– The process of ensuring a design can be
consistently manufactured by the designated
supply chain with a minimum number of
defects
• Requirements
– An understanding of best practices (what fails
during manufacturing?)
– An understanding of the limitations of the
supply chain (you can’t make a silk purse out
of a sow’s ear)
DfM Failures
• DfM is often overlooked in the design
process for some of the following
reasons:
– Design team often has poor insight into supply chain
(reverse auction, anyone?)
– OEM requests no feedback on DfM from supply chain
– DfM feedback consists of standard rule checks (no
insight)
– DfM activities at the OEM are not standardized or
distributed
Introduction to Design for Manufacturing (DfM)
• DfM is the process of proactively designing products to:
– Optimize all of the manufacturing functions: supplier selection and
management, procurement, receiving, fabrication, assembly, quality
control, operator training, shipping, delivery, service, and repair.
– Assure that critical objectives of cost, quality, reliability, regulatory
compliance, safety, time-to-market, and customer satisfaction are
known, balanced, monitored, and achieved.
• Successful DFM efforts require the integration of product design and
process planning into a cohesive, interactive activity know as
Concurrent, Collaborative, or Simultaneous Engineering.
– If existing processes are to be used, new products must be designed to
the parameters and limitations of these processes regardless of
whether the product is build internally or externally.
– If new processes are to be utilized, then the product and process need
to be developed concurrently and mindfully (carefully considering the
risks associated with “new”)
Why DfM?
• DfM is a proven, cost-effective strategic methodology.
• Early effective cross functional involvement:
– Reduces overall product development time (less changes, spins,
problem solving)
– Results in a smoother production launch.
– Speeds time to market.
– Reduces overall costs.
• Designed right the first time.
• Optimizes # of parts
• Optimizes # of process steps and use of correct, efficient steps
• Reduces labor costs to repair and resolve issues
• Improves overall production efficiency.
• Build right the first time = less rework, scrap, and warranty costs.
– Improved quality and reliability results in:
• Higher customer satisfaction.
• Reduced warranty costs.
Design Engineering Influence on Lifecycle Costs
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Design/product engineering typically accounts for only 8-10% of a
product budget.
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Design decisions can determine up to 70-80% of the manufacturing
cost of the product and have significant impact on quality, reliability and
serviceability.
These decisions determine cost throughout the lifecycle of the product.
Once these costs are locked in, they are very difficult to change.
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– Require Engineering Change Orders (ECOs), design spins, supplier
qualifications, and/or certification (UL, FDA) modifications
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Production decisions (material handling, process flow, assembly
equipment) account for less than 20-30% of product costs.
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Total lifecycle cost, impacted by quality, and reliability, can be better
managed and optimized by developing products and their associated
manufacturing processes together with cross functional or collaborative
teams aware of design for Manufacturing and sourcing best practices.
Why DfM?
Architectural Design for Reliability, R. Cranwell and R. Hunter, Sandia Labs, 1997
Why DfM? (cont.)
Reduce Costs by Improving
Manufacturability Upfront
Old Style Product Development - “Sequential Over The Wall”
R&D
PRODUCT
ENRG.
VALIDATION
TESTING
MANUF./
ASSEMBLY
DEALERS
DISTRIBUTORS
SERVICE
Stress
Requires 4.5 - 5
CHAMBER
Feedback Loops
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Before DfM, it was “We designed it” ~ “You build it“!
Design engineers worked independently, then transferred designs
“over the wall” to the next department or external to the company (CM).
Eventually manufacturing has to assemble the product.
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Usually inherit a product not designed for their processes and too late to make changes.
Manufacturing forced struggle to meet yield, quality, cost or delivery targets.
Often required trial & error crisis management
Followed by launch delays, then quality and reliability issues.
Key Design for Manufacturing Guidelines
• The foundation of a robust Design for Manufacturing
system is a set of design guidelines and tasks to
help the product team improve manufacturability,
increase quality, reduce lifecycle cost and enhance
long term reliability.
• These guidelines need to be customized to your
company’s culture, products, technologies and
based on a solid understanding of the intended
production system – whether internal or external.
• The next module will review global “Top 10” DfM
guidelines and tasks that are applicable to most
industries and processes.
DfM Guideline #1: Know Your History
• “Those who do not learn from history are doomed to repeat it.”
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– Learn from the past: Process yields, Returns, Corrective Actions
Processes, Recalls, etc.
– Develop and implement strategies to address and prevent recurrence of
mistakes.
Know and understand problems and issues with current and past products with
respect to:
– Manufacturability
– Delivery
– Quality
– Repairability & serviceability,
– Regulatory issues
– Recalls
– Especially critical if carrying over existing technologies into new designs.
Best approach is to have an effective system for capturing and disseminating
this historical knowledge throughout the organization.
Absolute minimum should be focused brain storming sessions (post-mortems)
to collect lessons learned/best practices from all areas of the organization.
DfM Guideline #2: Standardize Design Methods
• Standardize design, procurement, processes, assembly, and
equipment throughout your organization
– Reduces overall cycle time.
– Simplifies training and tasks.
– Reduces repeated mistakes
– Improves opportunity for bulk discounts.
– Improves opportunity for automation and operation
standardization.
• Don’t Redesign the Wheel
– Never custom design something that you can buy off the
shelf.
• Limit exotic or unique components.
– Higher prices due to low volumes and less supplier
competition.
– Lower quality for exotic components.
– More opportunity for supply chain disruptions.
DfM Guidelines #3: Simplify the Design
by Parts Reduction
Everything should be made as simple as possible, but not one bit simpler.
- Albert Einstein
• Parts reduction is one of the best ways to
reduce the cost of fabricating and
assembling a product and increase quality
and reliability.
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Reduces parts costs.
Reduces direct labor costs.
Reduces process equipment.
Reduces number or workstations.
Fewer opportunities for defective parts.
Fewer opportunities for assembly errors.
DfM Guideline #3: Simplify the Design –
Parts Reduction
• Parts reduction is also one of the best ways to reduce
structural costs.
– Fewer parts rippling through the entire organization
reduces the work load for every department at every
level.
– Fewer items to be processed by:
• Product Development
– Engineering, Purchasing, Development/Test Labs.
• Manufacturing Support
– Inventory Warehousing, Material Handling, Service Parts.
– Quality Management.
• Manufacturing facilities
– Facility Size, Equipment, Processing/Assembly Time & Labor
• Provides more opportunities for process
automation.
DfM Guidelines #3: Simplify the Design - Methods for Part Reduction
• Modular design
– Use complete modules and subassemblies, instead of designing,
fabricating and assembling everything yourself, simplifies every
level of your activities.
– Modules can be manufactured and tested before final assembly.
– Modules facilitate the use of standard components to minimize
product variations.
– Modules add flexibility to product update in the redesign
process
DfM Guidelines #3: Simplify the Design - Methods for
Part Reduction
• Parts Commonality via Multi-Use/Multi-Functional Parts
– Develop an approved or preferred parts lists or a standardized BOM
(Bill of Materials) to encourage different products lines to share
common parts.
• Designer CAD/CAE systems can be configured to access preferred
designs and parts catalogs.
– Whenever possible use one-piece structures from injection molding,
extrusions, castings and powder metals or similar fabrication techniques
instead of bolt/glue together multi part assemblies.
– Establish part families of similar parts based on proven materials,
architecture and technologies that are scaled for size or functionality
– Use Multi-functional parts that perform more that one function,
example:
• An electric conductor that also serves as a structural member,
• A cover or base plate that also serves as a heat sink
• Incorporate guiding, aligning, or self-fixturing features into housing
and structures.
DfM Guideline #4: Design for Lean Processes
Fundamental Principle of Lean
Anything that does not add
value to the product is waste
and must be reduced or
eliminated
• Lean supply, fabrication and assembly processes are
essential design considerations.
– Simple lean fabrication/processing/assembly is more
likely to be done quickly and correctly
• Right part at the right station at the right time
– Reduced throughput time equals faster time to market
and lower costs (reduced labor hours and faster turns).
– Designs that are easy to assemble manually will be more
easily automated.
– Assembly that is automated will be more uniform, more
reliable, and of higher quality.
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Develop and use standard guidelines appropriate for the process being
performed. Examples:
– Common hole sizes, lines, and spacings
– Standard soldering temperature profiles
– Standard handling, avoid MSL > 3 components
– For assembly - design for human factors – the “Visual” Factory
• Allow for visual, audio and/or tactile feedback to ensure correct
assembly operations.
– Makes it obvious to follow the correct process flow.
– Bottlenecks and problems are more easily identified
• Provide adequate access clearances for tools and hands.
• Design in self aligning and self guiding features such as tapered parts,
guide pins or groves.
• Design work to use standard tools and settings: crimpers, splicers,
cutters, solder iron tips, drill bit sizes, torque settings, wire sizes
– Minimizes tool clutter and decision making on what to use
DfM Guideline #5: Eliminate Waste
• Seven Types of Waste
1. Overproduction
 Build more than required, before required.
2. Waiting
 Stop build to look for parts, tools, material, information
3. Transportation/Moving
 Moving material, parts, tooling
 Transferring product between locations, into/out of racks
4. Process Inefficiencies
 Unnecessary operations, too many inspections, not building to customer spec
5. Inventories/Storage
 Excess raw material, excess WIP
6. Unnecessary Motions
 Walking, climbing, bending, searching, identifying
7. Defective products
 Low Yields, mistakes leading to large reworks, sorting, inspection
DfM Guideline #6: Design for Parts Handling
• Minimize handling to correctly position, orient, and
place parts and avoid multiple or complex assembly
orientations.
– Use non-symmetrical parts where possible. When symmetrical parts are needed,
use keying features to ensure proper orientation. Make orienting and mating parts
as visually obvious as possible.
– Use parts oriented in magazines, bands, tape, reels or strips when possible or use
parts designed to consistently orient themselves when fed into a process
– Reduce and avoid parts that can be easily damaged, bent, or broken.
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Parts should be designed with surfaces that can be easily grasped, placed or fixtured.
– Reduce the need for temporary fastening and complex fixtures.
– Begin assembly with a large base component with a low center of gravity
to add other parts to. Assembly should proceed vertically with other parts added on
top
• Exception: avoid upward orientation of debris /contamination sensitive features.
• Prevent dust or moisture from falling into electrical, hydraulic, pneumatic
connector or lines
– Use appropriate and safe packaging for parts but minimize the creation of waste
DfM Guideline #7: Design for Joining & Fastening
• Design for efficient joining and fastening.
– Fasteners increase the cost of manufacturing, handling and
feeding operations.
• Screws, bolts, nuts and washers are time-consuming to assemble &
difficult to automate.
• Increased potential for defects (missing and improper assembly).
– Avoid threaded fasteners when possible, consider alternative,
• Consider the use of snap-fit.
• Evaluate adhesive bonding techniques.
– Where fasteners must be used, minimize variety
• Use guidelines and standardize fasteners to minimize the
number, size, and variation.
• Self-tapping and chamfered screws are preferred.
• Use captive fasteners when possible.
DfM Guidelines #8: Use Error Proofing Techniques
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Mistakes will happen, What can go wrong will go wrong.
– Anticipate and Eliminate opportunities for error
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Use error proofing techniques in product design and assembly
– Make the correct assembly process visually obvious, well-defined and
clear cut, remove confusion and interpretation.
– Have written instructions in 1 location only – no competing documents
– Minimize wording in instructions, use pictures, icons, photos instead
– Key unique parts so that they can be inserted only in the correct location.
• Use notches, asymmetrical holes and stops to mistake-proof the
assembly process.
– Design verifiability into the product and its components.
• Sight, Sound or Field - use visual, audio or tactile feedback
• Use color coding
• Electronic products can be designed to contain self-test
diagnostics
– Avoid or simplify adjustments or modifications
DfM Guideline #9: Design for Process Capabilities
• Make use of specific production DFM guidelines or
know the process capabilities of the production
equipment you expect to use.
– Avoid unnecessarily tight tolerances and tolerances that are
beyond the inherent capability of the manufacturing processes or
operators in a continuous production situation. Tighter is not
always better!
– Perform tolerance stack up analyses on multiple, connected
processes and parts.
– Determine when new production process capabilities are needed
and allow sufficient time to develop/optimize new processes,
determine optimal process parameters and establish controlled
processes.
DfM Guideline #10: Design for Test, Repair, & Serviceability
• Defects will occur. Design for ease of test and repair will
make these processes more efficient, cost effective, and
reliable.
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Use recommended component spacing to allow for safe repair or replacement
Design in diagnostics, self tests, meaningful error messages, and diagnostic interfaces.
ESD Considerations - provide warning labels and appropriate workstations where needed.
Standardize approaches and methods.
• Minimize parts variety, minimize tools/special tools needed
Minimize disassembly steps to access replaceable/repairable Items.
• Consider unfastening and refastening, disassembly and reassembly issues.
• Use self-fastening and self-jigging Features when possible.
• Consider impact of adhesives, coating, and potting
Wiring/Hose Interconnection – consider disconnect and reconnect capabilities.
• Failed products are often returned to the manufacturer for
service and failure analysis. Where possible, use the
production test equipment/setup for returns analysis.
Module 2: Industry
Standard Design Rules
Industry Standards – IPC, JEDEC, ISO…
• Make use of existing industry
standards where possible
– Tried and true
– Well tested and accepted
– But – may represent only
minimum acceptable
requirements or concerns not
relevant to your needs.
Remember to modify and
extend requirements as
needed to customize for your
product and environments!
– Their forums provide
opportunities to solicit free
advice and feedback on
issues you face and questions
you have.
IPC Design Requirement/Guideline References
• The IPC is a global trade association dedicated to the
competitive excellence and financial success of all facets of the
electronic interconnect industry including design, printed circuit
board manufacturing and electronics assembly. http://www.ipc.org/
• Provide a forum to brings together all industry players, including
designers, board manufacturers, assembly companies, suppliers,
and original equipment manufacturers.
• Provides resources to:
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Management improvement and technology enhancement
Creation of relevant standards
Protection of the environment
Pertinent government relations.
Circuit Assembly Design Standards
• IPC-2221- Generic Standard on Printed Board Design
– IPC-2221A is the foundation design standard for all documents in the
IPC-2220 series. It establishes the generic requirements for the design of
printed boards and other forms of component mounting or interconnecting
structures, whether single-sided, double-sided or multilayer.
– 3 Performance Classes
• Class 1 General Electronic Products - consumer products,
• Class 2 Dedicated Service Electronic Products
– Communications equipment, sophisticated business machine, instruments and
military equipment where high performance, extended life and uninterrupted service
is desired but is not critical.
• Class 3 High Reliability Electronic Products
– Commercial, industrial and military products where continued performance or
performance on demand is critical and where high levels of assurance are
required...
• IPC-4101 - Specification for Base Materials for Rigid
and Multilayer Printed Boards
– Covers the requirements for base materials that are referred to as laminate or
prepreg. These are to be used primarily for rigid and multilayer printed boards
for electrical and electronic circuits.
• IPC-7351 - Generic Requirements for Surface Mount
Design and Land Pattern Standards
– Covers land pattern design for all types of passive and active components,
including resistors, capacitors, MELFs, SSOPs, TSSOPs, QFPs, BGAs, QFNs
and SONs. The standard provides printed board designers with an intelligent
land pattern naming convention, zero component rotations for CAD systems and
three separate land pattern geometries for each component that allow the user
to select a land pattern based on desired component density.
– Includes land pattern design guidance for lead free soldering processes, reflow
cycle and profile requirements for components and new component families
such as numerous forms of chip array packages and "pull-back" QFN and SON
devices.
• IPC-CM-770E – Component Mounting Guidelines for
Printed Boards
• Provides effective guidelines in the preparation and
attachment of components for printed circuit board
assembly and reviews pertinent design criteria,
impacts and issues. It contains techniques for
assembly (both manual and machines including SMT,
BGA and flip chip) and consideration of, and impact
upon, subsequent soldering, cleaning, and coating
processes.
• IPC-7095 Design and Assembly Process Implementation for BGAs
– Provides guidelines for BGA inspection and repair, addresses reliability
issues and the use of lead-free joint criteria associated with BGAs.
• IPC J-STD-001D - Requirements for Soldered Electrical & Electronic
Assemblies.
– J-STD-001D is world-recognized as the sole industry-consensus standard
covering soldering materials and processes. This revision now includes
support for lead free manufacturing, in addition to easier to understand
criteria for materials, methods and verification for producing quality soldered
interconnections and assemblies. The requirements for all three classes of
construction are included
– 3 Construction Classes defined.
• Class 1 General Electronic Products
• Class 2 Dedicated Service Electronic Products
• Class 3 High Reliability Electronic Product
• These documents are used as a reference for the case studies and
information in this workshop
JEDEC/IPC Joint Standards
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JEDEC is the leading developer of standards for the solid-state industry. Almost
3,300 participants, appointed by some 300 companies work together in 50
JEDEC committees to meet the needs of every segment of the industry,
manufacturers and consumers alike. The publications and standards that they
generate are accepted throughout the world. All JEDEC standards are available
online, at no charge. www.jedec.org
Commonly referenced JEDEC/IPC Joint Standards standards:
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J-STD-020D.01: JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW
SENSITIVITY CLASSIFICATION FOR NONHERMETIC SOLID STATE SURFACEMOUNT DEVICES:
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This document identifies the classification level of nonhermetic solid-state surface mount
devices (SMDs) that are sensitive to moisture-induced stress. It is used to determine what
classification level should be used for initial reliability qualification. Once identified, the SMDs
can be properly packaged, stored and handled to avoid subsequent thermal and mechanical
damage during the assembly solder reflow attachment and/or repair operation. This revision
now covers components to be processed at higher temperatures for lead-free assembly.
JS9704 : IPC/JEDEC-9704: Printed Wiring Board (PWB) Strain Gage Test Guideline
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This document describes specific guidelines for strain gage testing for Printed Wiring Board
(PWB)assemblies. The suggested procedures enables board manufacturers to conduct
required strain gage testing independently, and provides a quantitative method for measuring
board flexure, and assessing risk levels. The topics covered include: Test setup and equipment;
requirements; Strain measurement; Report format
ISO Standards
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ISO (International Organization for Standardization) is the world's
largest developer and publisher of International Standards.
www.iso.org
ISO is a network of the national standards institutes of 162
countries, one member per country, with a Central Secretariat in
Geneva, Switzerland, that coordinates the system.
ISO is a non-governmental organization that forms a bridge
between the public and private sectors. On the one hand, many of
its member institutes are part of the governmental structure of their
countries, or are mandated by their government. On the other
hand, other members have their roots uniquely in the private
sector, having been set up by national partnerships of industry
associations.
Therefore, ISO enables a consensus to be reached on solutions
that meet both the requirements of business and the broader
needs of society.
Some commonly used ISO Standards
– ISO 9001: Quality Management Systems
– ISO 14050: Environmental Management Systems
– ISO 13485: Medical devices -- Quality management systems -Requirements for regulatory purposes
Commonly Used Lab Test & Reference Standards
• IPC-TM-650: Test Methods Manual
– Series available for free download at
www.ipc.org
• http://www.ipc.org/ContentPage.aspx?PageID=
4.1.0.1.1.0
– Section 1.0:Reporting and Measurement Analysis Methods
– Section 2.1:Visual Test Methods
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Section 2.2:Dimensional Test Methods
Section 2.3:Chemical Test Methods
Section 2.4:Mechanical Test Methods
Section 2.5:Electrical Test Methods
Section 2.6:Environmental Test Methods
Module 3: Overview of DfM
Tasks
Common Types of DfM Review Processes
• Informal “Gut Check” Review
– Performed by highly experienced engineers.
– Difficult with transition to original design
manufacturers (ODM) in developing countries.
– “Tribal knowledge”
• Formal Design reviews
– Internal team
– External experts
• Automated (electronic) design
automation
(ADA) software
– Modules automate DfM rule checking.
• Electronic manufacturing
service (EMS) providers
– Perform DfM as a service
Design for Manufacturing (DfM)
• Formal DfM Reviews and Tools Sometimes
Overlooked
– Organization may lack specialized expertise.
– More design organizations completely insulated/disassociated from manufacturing.
– Dependence on local experience.
• DfM Reviews Needs to be Performed for:
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Bare Board
Circuit Board Assemblies
Chassis/Housing Integration Packaging
System Assembly
• DfM Needs to be conducted in conjunction with
the actual electronic assembly source.
– What is good DfM for one supplier and one set of assembly equipment may not be
good for another.
Use a Root Cause Problem Solving Methodology
• Critical that your organization has a
formal root cause problem solving
methodology used both internally and
externally.
– This is the best way to incorporate relevant
material into your customized Design for
Manufacturing and Sourcing guidelines.
• This ties in closely with DfM Guideline #1:
Know Your History!
Why 8D Problem Solving?
• Problem Statement:
– Simply fixing the symptoms of a problem, more often than
not, leads to band-aid solutions
• End up solving the same problem several times
• Other areas experience similar problems
• Solution:
– Do root cause analysis and follow through with permanent
corrective actions on significant problems
• Break the endless loop
–Drive Continuous Improvement
• Save money & efficiencies
• Reap benefits beyond the discrete issue
The 8 D Suite
Continuous
Improvement
Products/Processes
Improved
Process
• Stop & Study
Assign
• Learn
• Apply Lessons
Broadly
Review
Tools
• Mgt. Involvement
• Six Steps
Approach
• Brainstorming
• Is/Is Not
• Why- Why
• Etc.
Approve
The 8 Disciplines (8D)
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3.
4.
5.
6.
7.
8.
Create the Team
Problem Description and Data Analysis
Containment Actions
Perform Root Cause Analysis
Choose and Verify Corrective Action
Implement Corrective Action
Apply Lessons Learned
Celebrate Success / Close the Issue
(8D forms can also be used by suppliers. )
General Words of Wisdom on Failure Analysis
• Before spending time and money on Failure Analysis,
consider the following:
– Consider FA “order” carefully. Some actions you take will limit or
eliminate the ability to perform follow on tests.
– Understand the limitations and output of the tests you select.
– Use partner labs who can help you select and interpret tests for
capabilities you don’t have. Be careful of requesting a specific
test. Describe the problem and define the data and output you
need first.
– Pursue multiple courses of action. There is rarely one test or one
root cause that will solve your problem.
– Don’t put other activities on hold while waiting for FA results.
Understand how long it will take to get results
– Consider how you will use the data. How will it help you?
• Information?
• Change course, process, supplier?
• Don’t pursue FA data if it won’t help you or you have no control over the
path it might take you down. Some FA is just not worth doing.
Why is Failure Analysis Knowledge
important?
• There are always more problems than
resources!
• If you don’t analyze, learn from, and
prevent problems, you simply repeat
them. You list never gets smaller.
Failure Analysis Techniques




Returned parts failure analysis always starts with Non-Destructive
Evaluation (NDE)
Designed to obtain maximum information with minimal risk of
damaging or destroying physical evidence
Emphasize the use of simple tools first
(Generally) non-destructive techniques:
 Visual Inspection
 Electrical Characterization
 Time Domain Reflectometry
 Acoustic Microscopy
 X-ray Microscopy
 Thermal Imaging (Infra-red camera)
 Superconducting Quantum Interfering Device (SQUID)
Microscopy
93
Failure Analysis Techniques
•
Destructive evaluation techniques
–
–
–
–
–
–
–
–
–
•
Decapsulation
Plasma etching
Cross-sectioning
Thermal imaging (liquid crystal; SQUID and IR also good after decap)
SEM/EDX – Scanning Electron Microscope / Energy dispersive X-ray
Spectroscopy
Surface/depth profiling techniques: SIMS-Secondary Ion Mass
Spectroscopy, Auger
OBIC/EBIC
FIB - Focused Ion Beam
Mechanical testing: wire pull, wire shear, solder ball shear, die shear
Other characterization methods
–
–
–
–
FTIR- Fourier Transform Infra-Red Spectroscopy
Ion chromatography
DSC – Differential Scanning Calorimetry
DMA/TMA – Thermo-mechanical analysis
94
Electrical Characterization

Most critical step in the failure analysis process

Can the reported failure mode be replicated?





Least utilized to its fullest extent
Equipment often shared with production and R&D
Approach dependent upon the product




Persistent or intermittent?
Intermittent failures often incorrectly diagnosed as no trouble found (NTF)
Component
Bare board
PCB assembly
Sometimes performed in combination with environmental exposure




Characterization over specified temperature range
Characterization over expected temperature range
Humidity environment (re-introduction of moisture)
Not designed to induce damage!
95
Electrical Characterization: Components

Parametric characterization


Curve tracer




Release and return of electrical signal along a given path
Measurement of phase shift of return signal indicates potential location of
electrical open
Other characterization equipment




Applies alternating voltage; provides plot of voltage vs. current response
Valuable in characterizing diode, transistor, and resistance behavior
Time domain reflectometry (TDR)


Comparison of performance to datasheet specifications
Inductance/capacitance/resistance (LCR) meter
High resistance meter (leakage current < nA)
Low resistance meter (four wire; < milliohms)
Use of additional environmental stresses

Semiconductor-based devices


Temperature rise or temperature/humidity could trigger elevated leakage current
Passive components
96
Electrical Characterization: Bare Board




In-circuit testing (ICT)
 Primarily performed on in-line failures (bed of nails or flying
probe)
 Detection of electrical opens and shorts
 Based on triggering rules (pass/fail)
 Allows for relatively accurate identification of failure site
Time domain reflectometry (TDR)
Resistance measurements (manual)
 Binary approach
Environmental stresses
 Electrical short (temperature/humidity)
 Electrical open (temperature cycling)
 Requires continuous monitoring (intermittent behavior)
97
Electrical Characterization: PCB Assembly

Functional


JTAG (joint task action group) boundary scan






Measures voltage fluctuations as a function of time (passive)
Useful in probing operational circuitry
Digital capture provides better documentation capability
Available stand alone or PC-based
Isolation of attached components



Allows for testing ICs and their interconnections using four I/O pins (clock, input
data, output data, and state machine mode control)
Allows for relatively accurate identification of failure site, but rarely performed on
failed units (primarily replacement for In Circuit Test-ICT)
Oscilloscope


Most valuable, if product is experiencing ‘partial’, permanent failure
Attempt to perform as much electrical characterization without component
removal
Consider trace isolation (knife, low speed saw)
Environmental stresses

Approach similar to bare board
98
Some Simple FA Tools: Flexible Light
Sources & Mirrors
• Make is easier to look
under and around
areas on an assembly
• http://www.brandsplac
e.com/0246ste10150a.html
• http://minimicrostencil.
com/mini_mirror.htm
• http://www.metronusa
.com/mirrors1.htm
Failure Analysis: Temperature Tools
• Cold Spray and hot
plates to simulate
fails at temperature
extremes
Failure Analysis Tools: Dye N Pry Capability
• Allows for quick
(destructive) inspection for
cracked or fractured
solder joints under
leadless components
(BGAs, QFNs)
• http://www.electroiq.com/i
ndex/display/packagingarticledisplay/165957/articles/ad
vancedpackaging/volume12/issue1/features/solder-jointfailure-analysis.html
Failure Analysis Dremel Tool – Induce Vibrations
• A Dremel tool can be used
to induce local vibration
during debugging
• http://www.dremel.com
DfM Example: Flex Cracking of Ceramic Caps
• Due to excessive flexure of
the board
• Occurrence
– Depanelization
– Handling (i.e., placement into a test jig)
– Insertion (i.e., mounting insertion-mount
connectors or daughter cards)
– Attachment of board to other structures
(plates, covers, heatsinks, etc.)
Flex Cracking (Case Studies)
Board Depaneling
Screw Attachment
Connector Insertion
Heatsink Attachment
Flex Cracking (cont.)
Flex Cracking (cont.)
• Drivers
– Distance from flex point
– Orientation
– Length (most common at 1206 and above; observed in 0603)
• Solutions
–
–
–
–
–
–
Avoid case sizes greater than 1206
Maintain 30-60 mil spacing from flex point
Reorient parallel to flex point
Replace with Flexicap (Syfer) or Soft Termination (AVX)
Reduce bond pad width to 80 to 100% of capacitor width
Measure board-level strain (maintain below 750 microstrain,
below 500 microstrain preferred for Pb-free)
DfM Example (Plated Through Hole vs. Microvia)
• What should be the minimum diameter of
a PTH in your design?
• What should be the maximum aspect ratio
(PCB Thickness / PTH Diameter)?
• When should you switch to microvias?
• Answer: Depends!
– Supplier
– Reliability needs
PTH Diameter
• Data from 26 board shops
– Medium to high complexity
– 62 to 125 mil thick
– 6 to 24 layer
Courtesy of CAT
• Results
– Yield loss after worst-case
assembly
– Six simulated Pb-free
reflows
Yield loss can results in escapes to the customer!
Are Microvias more reliable than PTHs?
• Depends!!
• Quality
–
–
–
–
Some fabricators have no problems
Some have more problems with microvias
Some have more problems with PTHs
Some have problems with both
• Reliability
– A well-built microvia is more robust than a
well-built PTH
PTH vs. Microvia
PTH Quality
Microvia Quality
Courtesy of CAT
Summary (PTH and Microvias)
• The capability of the PCB industry in regards to
hole diameter tends to segment
– Very high yield (>13.5 mil)
– High yield (10 – 13.5 mil)
– Lower yield (< 10 mil)
• If 8 mil drill diameter or less is required
– Consider using PCQR2 to identify a capable supplier
– Consider using interconnect stress test (IST) coupons
to ensure quality for each build
– Consider transitioning to microvias (6 mil diameter)
DfM Examples (cont.)
• Utilize thermal reliefs on all copper planes when practical
–
–
–
Reduces thermal transfer rate between PTH and copper plane
Allows for easier solder joint formation during solder (especially for Pb-free)
Allows for better hole fill
PTH
Laminate
Copper
Plane
Copper
Spoke
Courtesy of D. Canfield (Excalibur Manufacturing)
Module 4: Components
Component Robustness
Robustness - Components
o
Concerns
o
o
o
Drivers
o
o
o
Potential for latent defects after exposure to Pb-free
reflow temperatures
215°C - 220°C peak → 240°C - 260°C peak
Initial observations of deformed or damaged
components
Failure of component manufacturers to update
specifications
Components of particular interest
o
o
o
o
Aluminum electrolytic capacitors
Ceramic chip capacitors
Surface mount connectors
Specialty components (RF, optoelectronic, etc.)
Ceramic Capacitors (Thermal Shock Cracks)
o
Due to excessive change in temperature
o
o
o
Maximum tensile stress occurs near end
of termination
o
o
o
Reflow, cleaning, wave solder, rework
Inability of capacitor to relieve stresses
during transient conditions.
Determined through transient thermal
analyses
Model results validated through sectioning
of ceramic capacitors
exposed to thermal shock
conditions
Three manifestations
o
o
o
Visually detectable (rare)
Electrically detectable
Microcrack (worst-case)
NAMICS
AVX
Thermal Shock Crack: Visually Detectable
AVX
Thermal Shock Crack: Micro Crack
o
o
Variations in voltage or
temperature will drive crack
propagation
Induces a different failure mode
o
Increase in electrical resistance or
decrease capacitance
DfR
Corrective Actions: Manufacturing
o
Solder reflow
o
o
o
o
o
o
Wave soldering
o
o
Room temperature to preheat (max 2-3oC/sec)
Preheat to at least 150oC
Preheat to maximum temperature (max 4-5oC/sec)
Cooling (max 2-3oC/sec)
o In conflict with profile from J-STD-020C (6oC/sec)
Make sure assembly is less than 60oC before cleaning
Maintain belt speeds to a maximum of 1.2 to 1.5 meters/minute
Touch up
o
Eliminate
Corrective Actions: Design
o
o
Orient terminations parallel to wave solder
Avoid certain dimensions and materials (wave soldering)
o
o
o
o
o
o
Maximum case size for SnPb: 1210
Maximum case size for SAC305: 0805
Maximum thickness: 1.2 mm
C0G, X7R preferred
Adequate spacing from hand soldering operations
Use manufacturer’s recommended bond pad dimensions or
smaller (wave soldering)
o
Smaller bond pads reduce rate of thermal transfer
Is This a Thermal Shock Crack? No!
o
o
Cracking parallel to the electrodes is due to stack-up or
sintering processes during capacitor manufacturing
These defects can not be detected using in-circuit (ICT) or
functional test
o
o
Requires scanning acoustic microscopy (SAM)
With poor adhesion, maximum stress shifts away from the
termination to the defect site
o
No correlation between failure rate and cooling rates (0.5 to 15ºC/sec)
Flex Cracking of Ceramic Capacitors
o
Excessive flexure of PCB under ceramic chip capacitor can
induce cracking at the terminations
Flex Cracking of Ceramic Capacitors (cont.)
o
Excessive flexure of PCB
under ceramic chip capacitor
can induce cracking at the
terminations
Pb-free more resistant to flex
cracking
o
o
Probability - Weibull
99.90
Correlates with Kemet results
(CARTS 2005)
o
o
Smaller solder joints
Residual compressive stresses
Influence of bond pad
Action Items
o
None
W eibull
1812 SAC
W2 RRX - RRM MED
90.00
Rationale
o
o
R e lia So ft's W e ib u ll++ 6 .0 - w w w .W e ib u ll.c o m
F = 162 / S= 0
1812 SnPb
SnPb
50.00
Unreliability, F(t)
o
W2 RRX - RRM MED
F = 90 / S= 0
SnAgCu
10.00
5.00
Craig Hillman
DfR Solutions
6/13/2005 21:56
1.00
1.00
10.00
Displacement (mm)
        
        
Summary
• Risk areas
– Small volume V-chip electrolytic capacitors
– Through hole electrolytic capacitors near large BGAs
– Ceramic capacitors wave soldered or touched up
• Actions
– Spec and confirm
• Peak reflow temperature requirements for SMT electrolytics
(consider elimination if volume < 100mm3)
• Time at 300°C for through-hole electrolytics
– Initiate visual inspection of all SMT electrolytic capacitors
(no risk of latency if no bulging or other damage observed)
– Ban touch up of ceramic capacitors (rework OK)
Module 4: Components
Temperature Sensitivity
Moisture Sensitivity
Peak Temperature Ratings
• AKA: ‘Temperature Sensitivity Level’ (TSL)
• Some component manufacturers are not
certifying their components to a peak
temperature of 260ºC
– 260ºC is industry default for ‘worst-case’ peak
Pb-free reflow temperature
• Why lower than 260ºC?
– Industry specification
– Technology/Packaging limitation
Industry Specification (J-STD-020)
• Package size
– Number of component
manufacturers rely on table
and reflow profile suggested
in J-STD-020C
– Larger package size,
lower peak temperature
• Issues as to specifying dwell time
– J-STD-020C: Within 5ºC of 260ºC for 20-40 seconds
– Manufacturers: At 260ºC for 5-10 seconds
J-STD-020D.1 Reflow Profile (Update)
• Specification of peak package body temperature (Tp)
– Users must not exceed Tp
– Suppliers must be equal
to or exceed Tp
• Not yet widely adopted
TSL + MSL Example
• Peak temperature rating is 245C
– Problem, right?
• Not exactly
– Thickness > 2.5mm, Volume > 350mm3
– Peak temp specified by J-STD-020 is 245C
• Higher reflow temperature possible
– May require DOE / increase in MSL
TSL + MSL (example – cont.)
• NEC has two soldering conditions
– IR50: 250C peak temperature
– IR60: 260C peak temperature
• Four packages (not parts) identified as IR50
–
–
–
–
208pinQFP(FP): 28 x 28 x 3.2
240pinQFP(FP): 32 x 32 x 3.2
304pinQFP(FP): 40 x 40 x 3.7
449pinPBGA: 27 x 27 x 1.7
• Peak temperatures could be 245C and still meet J-STD-020
requirements
– Suggests characterization separate from J-STD-020 may have been
performed
TSL (cont.)
o
Limited examples of technology and
package limitations
o
o
o
o
Surface mount connectors (primarily
overcome)
RF devices (already sensitive to SnPb reflow)
Opto-electronic (LEDs, opto-isolators, etc.)
Examples
o
o
B. Willis, SMART Group
Amphenol: “Amphenol connectors containing LEDs must NOT be
processed using Lead-free infra-red reflow soldering using
JEDEC-020C (or similar) profiles”
Micron / Aptina: “Some Pb-free CMOS imaging products are
limited to 235°C MAX peak temperature”
http://download.micron.com/pdf/technotes/tn_00_15.pdf
http://www.amphenolcanada.com/ProductSearch/GeneralInfo/Disclaimer%20for%20Connectors%20containing%20LEDs.htm
Moisture Sensitivity Level (MSL)
• Popcorning controlled
through moisture sensitivity
levels (MSL)
– Defined by IPC/JEDEC
documents J-STD-020D.1 and
J-STD-033B
• Higher profile in the industry
due to transition to Pb-free
and more aggressive
packaging
– Higher die/package ratios
– Multiple die (i.e., stacked die)
– Larger components
MSL: Typical Issues and Action Items
• Identify your maximum MSL
– Driven by contract manufacturer
(CM) capability and OEM risk
aversion
– Majority limit between MSL3 and
MSL4 (survey of the MSD Council
of SMTA, 2004)
– High volume, low mix: tends towards MSL4
Low volume, high mix: tends towards MSL3
• Not all datasheets list MSL
– Can be buried in reference or quality documents
• Ensure that listed MSL conforms to latest
version of J-STD-020
Cogiscan
MSL Issues and Actions (cont.)
•
•
Most ‘standard’ components have a
maximum MSL 3
Components with MSL 4 and higher
– Large ball grid array (BGA) packages
– Encapsulated magnetic components
(chokes, transformers, etc.)
– Optical components (transmitters,
transceivers, sensors, etc.)
– Modules (DC-DC converters, GPS, etc.)
•
MSL classification scheme in J-STD020D is only relevant to SMT packages
with integrated circuits
– Does not cover passives (IPC-9503) or
wave soldering (JESD22A111)
– If not defined by component
manufacturer, requires additional
characterization
Aluminum and Tantalum Polymer Capacitors
Aluminum Polymer Capacitor 
Tantalum Polymer Capacitor 
Popcorning in Tantalum/Polymer Capacitors
• Pb-free reflow is hotter
– Increased susceptibility to popcorning
– Tantalum/polymer capacitors are the primary
risk
• Approach to labeling can be inconsistent
– Aluminum Polymer are rated MSL 3 (SnPb)
– Tantalum Polymer are stored in moisture
proof bags (no MSL rating)
– Approach to Tantalum is inconsistent (some
packaged with dessicant; some not)
• Material issues
– Aluminum Polymer are rated MSL 3 for
eutectic (could be higher for Pb-free)
– Sensitive conductive-polymer technology may
prevent extensive changes
• Solutions
– Confirm Pb-free MSL on incoming plastic
encapsulated capacitors (PECs)
– More rigorous inspection of PECs during initial
build
Module 4: Component Summary
• Know when peak temperature indicates true
temperature sensitivity
– Component manufacturer’s peak temperature ratings
deviate from J-STD-020
– Peak temperature ratings are very specific or nuanced
in some fashion
– Ask component manufacturer for data confirming
issues at temperatures below 260C
• Consider requiring MSL on the BOM for certain
component packaging and technologies
– Focus on polymeric and large tantalum capacitors
Module 5: Printed Circuit
Boards
Surface Finishes
PCB Surface Finishes
• Definition: A coating located at the
outermost layer and exposed
copper of a PCB.
– Protects copper from oxidation that inhibits
soldering
– Dissolves into the solder upon reflow or wave
soldering.
– SnPb HASL (Hot Air Solder Leveling) being
replaced by other finished due to technology
and RoHS-Pb-free trends.
Surface Finishes, Worldwide
2003
• Options (no clear winner)
–
–
–
–
–
–
Electroless nickel/immersion gold (ENIG)
Immersion tin (ImSn)
Immersion silver (ImAg)
Organic solderability preservative (OSP)
Pb-free HASL
Others (ENEPIG, other palladium, nano
finishes etc.)
• Most platings, except for Pb-free
HASL, have been around for
several years
2007
18%
J. Beers
Gold Circuits
Pb-Free HASL
• Increasing Pb-free solderability plating of
choice
• Primary material is Ni-modified SnCu
(SN100C)
– Initial installations of SAC being replaced
– Co-modified SnCu also being offered (claim of 80
installations [Metallic Resources])
• Selection driven by
–
–
–
–
–
Storage
Reliability
Solderability
Planarity
Copper Dissolution
Pb-Free HASL: Ni-modified SnCu
• Patented by Nihon Superior in March
1998
– Claimed: Sn / 0.1-2.0% Cu / 0.002-1% Ni / 0-1% Ge
– Actual: Sn / 0.7% Cu / 0.05% Ni / 0.006% Ge
• Role of constituents
– Cu creates a eutectic alloy with lower melt temp (227C
vs. 232C), forms intermetallics for strength, and reduces
copper dissolution
– Ni suppresses formation of -Sn dendrites, controls
intermetallic growth, grain refiner
– Ge prevents oxide formation (dross inhibitor), grain
refiner
Note: Current debate if Sn0.9Cu or Sn0.7Cu is eutectic
Pb-free HASL: Storage
• PCBs with SnPb HASL have storage times of 1
to 4 years
– Driven by intermetallic growth and oxide formation
• SN100CL demonstrates similar behavior
– Intermetallic growth is suppressed through Ni-addition
– Oxide formation process is dominated by Sn element
(similar to SnPb)
• Limited storage times for alternative Pb-free
platings (OSP, Immersion Tin, Immersion Silver)
Pb-Free HASL: Intermetallic Growth
SnPb (150C for 1000 hrs)
SN100C (150C for 1000 hrs)
• Similar intermetallic thickness as
SnPb after long-term aging and
multiple reflows
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008,
http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
Pb-Free HASL: Reliability
• Contract manufacturers (CMs) and
OEMs have reported issues with
electrochemistry-based solderability
platings
– ENIG: Black Pad, Solder Embrittlement
– ImAg: Sulfur Corrosion, Microvoiding
• Some OEMs have moved to OSP and
Pb-free HASL due to their ‘simpler’
processes
Pb-Free HASL: Solderability
• Industry adage: Nothing solders like solder
o
Discussions with CMs and OEMs seem to indicate
satisfaction with Pb-free HASL performance
o
o
Additional independent, quantitative data should be gathered
Improved solderability could improve hole fill
http://www.daleba.co.uk/download%20section%20-%20lead%20free.pdf
HASL and Flow: A Lead-Free Alternative, T. Lentz, et. al., Circuitree, Feb 2008,
http://www.circuitree.com/Articles/Feature_Article/BNP_GUID_9-5-2006_A_10000000000000243033
Pb-Free HASL: Planarity
o
Recommended minimum
thickness
o
o
o
Primary issue is thickness
variability
o
o
o
100 min (4 microns)
Lower minimums can result in
exposed intermetallic
Greatest variation is among
different pad designs
100 min over small pads (BGA
bond pads); over 1000 min over
large pads
Can be controlled through air
knife pressure, pot
temperatures, and nickel
content
Pb-Free HASL: Planarity (cont.)
Sweatman and Nishimura (IPC APEX 2006)
• Air knives
– Pb-free HASL requires
lower air pressure to
blow off excess solder
• Pot Temperatures
– SnPb: 240C to 260C
– SN100CL: 255C to 270C (air knife temp of 280C)
• Ni content
– Variation can influence fluidity
• Minimum levels critical for planarity
– Some miscommunication as to critical concentrations
Pb-Free HASL (Composition)
Florida CirTech, www.floridacirtech.com/Databases/pdfs/SN100CL.pdf
AIM Solder, www.advprecision.com/pdf/LF_Soldering_Guide.pdf
•
Minimum Ni concentrations need to be
more clearly specified by licensees
–
•
Recommended maximum Cu
concentrations range from 0.7 to 1.2wt%
–
–
Balver Zinn, www.cabelpiu.it/user/File/Schede%20prodotto/schede%20nuove%20SN100CL-SN100CLe.pdf
Nihon recommends >300 ppm
Increased bridging and graininess
Nihon recommends <0.9wt%
Pb-Free HASL: Copper Dissolution
• To be discussed in detail in
solder module
• Presence of nickel is
believed to slow the copper
dissolution process
Nihon Superior
– SAC HASL removes ~5 um
– SNC HASL removes ~1 um
www.p-m-services.co.uk/rohs2007.htm
www.pb-free.org/02_G.Sikorcin.pdf
www.evertiq.com/news/read.do?news=3013&cat=8 (Conny Thomasson, Candor Sweden AB)
Copper Erosion in HASL
Pb-Free HASL: Additional Concerns
• Risk of thermal damage, including warpage and
influence on long term reliability (PTH fatigue, CAF
robustness)
– No incidents of cracking / delamination / excessive warpage
reported to DfR to date
– Short exposure time (3 to 5 seconds) and minimal temp.
differential (+5ºC above SnPb) may limit this effect
• Compatibility with thick (>0.135”) boards
– Limited experimental data (these products are not currently
Pb-free)
• Mixing of SNC with SAC
– Initial testing indicates no long-term reliability issues (JGPP)
Electroless Nickel/Immersion Gold (ENIG)
• Two material system
– Specified by IPC-4552
• Electroless Nickel (w/P)
Saturn Electronics
– 3 – 6 microns (120 – 240 microinches)
– Some companies spec a broader 1 – 8 microns
• Immersion Gold
– Minimum of 0.05 microns (2 microinches)
– Self-limiting (typically does not exceed 0.25 microns)
• Benefits
– Excellent flatness, long-term storage, robust for multiple reflow cycles, alternate
connections (wirebond, separable connector)
ENIG (Primary Issue)
• Solder Embrittlement
–
Not always black pad
• Not explained to the satisfaction
of most OEMs
• Numerous drivers
–
Phosphorus content
• High levels = weak, phosphorus-rich
region after soldering
• Low levels = hyper-corrosion (black
pad)
–
–
–
–
Cleaning parameters
Gold plating parameters
Bond pad designs
Reflow parameters?
• Results in a severe drop in
mechanical strength
–
–
Difficult to screen
Can be random
(e.g., 1 pad out of 300)
• Board fabricators need to be on top of
numerous quality procedures to
prevent defects.
Other ENIG Failure Mechanisms
• Insufficient nickel thickness
– Potential diffusion of copper through the
nickel underplate
– Can reduce storage time and number of
reflow cycles
• Bond pad adhesion
– Problem with corner balls on very large
BGAs
(>300 I/O)
• Reduced plated through hole
reliability (stress concentrators)
• Dewetting
• Crevice corrosion
(trapped residues)
• Poor performance under
mechanical shock / drop
Nickel/Gold Layer
Copper
Laminate
Solder Mask
ENIG & Mechanical Shock
35x35mm, 312 I/O BGA
R eliaSoft's W eibull++ 6.0 - w w w .W eib ull.c om
• Boards with ENIG finishes
have less shock endurance.
–
Probability - Weibull
99.00
W eibull
Pb-F ree on ENIG
W3 RR3 - SRM MED
90.00
F = 6 / S= 0
Pb-F ree on O SP
W3 RR3 - SRM MED
F = 5 / S= 1
SnPb on O SP
Not always consistent
50.00
W3 RR3 - SRM MED
• Plating is an important driver
SnNi vs. SnCu intermetallics
• Crossover into board failure
–
Very strain-rate dependent
Unreliability, F(t)
–
F = 3 / S= 3
10.00
5.00
Craig Hillman
DfR Solutions
7/29/2005 10:27
1.00
1.00
Chai, ECTC 2005
10.00
Number of Drops
100.00
           
           
           
PQFP (28x28mm, 208 I/O)
Failures
Pb-Free on ENIG
2/6
44/50, 45/50
Pb-Free on OSP
2/6
16/50, 29/50
SnPb on OSP
0/6
-Chong, ECTC 2005
Immersion Tin (ImSn)
• Single material system
– Defined by IPC-4554
• Immersion Tin
– Standard thickness: 1 micron (40 microinches)
– Some companies spec up to 1.5 microns (65 microinches)
• Benefits
– Excellent flatness, low cost, excellent bare test pad probing
• Not as popular a choice
– Environmental and health concerns regarding thiourea
(known carcinogen).
– Not good for designs with small or micro vias – etchant gets
entrapped during PCB processing and “erupts” during SMT
soldering
Immersion Silver (ImAg)
– Defined by IPC-4553
• Two versions
– Thin: Minimum thickness of 0.05
microns
– Thicker: Minimum thickness 0.12
microns
• Benefits
– Excellent flatness, low cost, longterm storage, excellent bare test
pad probing
Sulfide Corrosion and Migration of Immersion Silver
• Failures observed within
months
– Sulfur-based gases attack exposed
immersion silver
– Non-directional migration (creepage
corrosion)
• Occurring primarily in
environments with high sulfur
levels. Not recommended for
these applications.
–
–
–
–
–
–
–
–
–
Rubber manufacturing
Waste treatment plants
Petroleum refineries
Coal-generation power plants,
Paper mills
Sewage/waste-water treatment
Landfills
Large-scale farms
Modeling clay
Organic Solderability Preservative (OSP)
– Specified by IPC-4555
• Thickness
• Benefits
– Very low cost, flatness, reworkable
• Issues
–
–
–
–
–
–
Short shelf life (6-12 months)
Limited number of reflows
Some concerns about compatibility with low activity, no-clean fluxes
Transparency prevents visual inspection
Poor hole fill
Test pads must be soldered – prepare for probing through no
clean materials if they are used.
OSP & Hole Fill
• Fill is driven by capillary
action
• Important parameters
– Hole diameter, hole aspect ratio,
wetting force, thermal relief
– Solder will only fill as along as its
molten (key point)
–
OSP has lower wetting force
– Risk of insufficient hole fill
– Can lead to single-sided
architecture
• Solutions?
– Changing board solderability plating
– Increasing top-side preheat
– Increasing solder pot temperature
(some go as high as 280C)
– Changing your wave solder alloy
P. Biocca, Kester
Module 5: Printed Circuit
Boards
Robustness Concerns
Cracking and Delamination
Printed Board Robustness Concerns
Increased Warpage
Solder Mask Discoloration
Blistering
Delamination
Pad Cratering
Land
Separation
PTH Cracks
Printed Board Damage
o
Predicting printed board damage can be difficult
o
o
o
o
o
o
Driven by size (larger boards tend to experience higher
temperatures)
Driven by thickness (thicker boards experience more thermal
stress)
Driven by material (lower Tg tends to be more susceptible)
Driven by design (higher density, higher aspect ratios)
Driven by number of reflows
No universally accepted industry model
Printed Board Damage: Industry Response
• Concerns with printed board damage
have almost entirely been addressed
through material changes or process
modifications
– Not aware of any OEMs initiating design
rules or restrictions
• Specific actions driven by board size
and peak temperature requirements
Industry Response (cont.)
• Small, very thin boards
– Up to 4 x 6 and 62 mil thick
– Peak temperatures as low as 238ºC
– Minimal changes; most already using 150ºC Tg Dicy (tends to be
sufficient)
• Medium, thin boards
– Tend to have moderate-sized components; limits peak
temperatures to 245ºC-248ºC
– Rigorous effort to upgrade laminate materials (dicy-cured may not
be feasible)
Rothshild, APEX 2007
• Large, thick boards
– Difficulty in maintaining peak temperatures below 260ºC
– Very concerned
PCB Robustness: Laminate Material Selection
Board thickness
IR-240~250℃
≤60mil
Tg140 Dicy
All HF materials OK
60~73mil
Tg150 Dicy
NP150, TU622-5
All HF materials OK
73~93mil
Tg170 Dicy, NP150G-HF
HF –middle and high Tg materials OK
Board thickness
≤ 60mil
60~73mil
IR-260℃
Tg150 Dicy
HF- middle and high Tg materials OK
Tg170 Dicy
73~93mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5, GA150
93~130mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo, TU7227
93~120mil
Tg150 Phenolic + Filler
IS400, IT150M, TU722-5
Tg 150
121~160mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo
TU722-7
HF –high Tg materials OK
≧131mil
Phenolic Tg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF –high Tg materials OK
PhenolicTg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF material - TBD
≧161mil
TBD – Consult Engineering for specific
design review
≧161mil
thickness = 2OZ use material listed on column 260 ℃
thickness >= 3OZ use Phenolic base material or High Tg Halogen free materials only
3.Twice lamination product use Phenolic material or High Tg Halogen free materials only (includes HDI)
4.Follow customer requirement if customer has his own material requirement
5.DE people have to confirm the IR reflow Temperature profile
1.Copper
2.Copper
J. Beers, Gold Circuits
Printed Board Damage: Prevention
• Thermal properties of laminate material are
primarily defined by four parameters
–
–
–
–
Out of plane coefficient of thermal expansion (Z-CTE)
Glass transition temperature (Tg)
Time to delamination (T260, T280, T288)
Temperature of decomposition (Td)
• Each parameter captures a different material
behavior
– Higher number slash sheets (> 100) within IPC-4101
define these parameters to specific material categories
Thermal Parameters of Laminate
•
Out of plane CTE (below Tg or Z-axis: 50ºC to 260ºC)
– CTE for SnPb is 50ppm - 90ppm (50C to 260C rarely considered)
– Pb-free: 30ppm - 65ppm or 2.5 – 3.5%
•
Glass transition temperature (IPC-TM-650, )
– Characterizes complex material transformation (increase in CTE,
decrease in modulus)
– Tg of 110ºC to 170ºC for SnPb
– Pb-free: 150ºC to 190ºC
•
Time to delamination (IPC-TM-650, 2.4.24.1)
– Characterizes interfacial adhesion
– T-260 for SnPb is 5-10 minutes
– Pb-free: T-280 of 5-10 minutes or T-288 of 3-6 minutes
•
Temperature of decomposition (IPC-TM-650, 2.3.40)
– Characterizes breakdown of epoxy material
– Td of 300ºC for SnPb
– Pb-free: Td of 320ºC
Thermal Parameters (cont.)
B. Hoevel, et. al., New epoxy resins for printed wiring board applications, Circuit World, 2007, vol. 33, no. 2
•
Strong correlation between Td and T288
– Suggests cohesive failure during T288
•
May imply poor ability to capture interfacial weaknesses
PCB Robustness: Material Selection
• The appropriate material selection is
driven by the failure mechanism one is
trying to prevent
– Cracking and delamination
– Plated through fatigue
– Conductive anodic filament formation
PCB Delamination
•
•
•
Fiber/resin interface delamination
occurs as a result of stresses
generated under thermal cycling
due to a large CTE mismatch
between the glass fiber and the
epoxy resin (1 vs. 12 ppm/ºC)
Delamination can be
prevented/resisted by selecting
resin with lower CTE’s and
optimizing the glass surface finish.
Studies have shown that the bond
between fiber and resin is strongly
dependent upon the fiber finish
Delamination / Cracking: Observations
• Morphology and location
of the cracking and
delamination can vary
– Even within the same
board
• Failure morphology and
locations
– Within the middle and edge of the PCB
– Within prepregs and/or laminate
– Within the weave, along the weave, or at the
copper/epoxy interface (adhesive and
cohesive)
Delamination / Cracking: Case Study
• Delamination marked
by red boxes
A
– Scalloped shape is
due to pinning at the
plated through holes
(PTHs)
• Results from acoustic
microscopy confirmed
observations from
visual inspection
– No additional
delamination sites
were identified
B
Central Delamination
• Delamination appears
to span multiple layers
• Plated through holes
pin the expansion of
the delamination
Additional Observations
• Drivers
–
–
–
–
–
–
Higher peak temperatures
Increasing PCB thickness
Decreasing via-to-via pitch
Increasing foil thickness (1-oz to 2-oz)
Presence of internal pads
Sequential lamination
Sequential Lamination
• Limited information
– Controlled depth drilling
• Extensive debate about root-cause
– Non-optimized process
– Intrinsic limit to PCB capability
– Moisture absorption
Rothschild, IPC APEX 2007
Delamination / Cracking: Root-Cause
• Non-Optimized Process
– Some PCB suppliers have demonstrated improvement
through modifications to lamination process or oxide
chemistry
– Some observations of lot-to-lot variability
• Limit to PCB Capability
– Difficult to overcome adhesion vs. thermal performance
tradeoff (dicy vs. phenolic)
– High stresses developed during Pb-free exceed
material strength of standard board material
• Moisture Absorption
Cracking and Moisture Absorption
• Does moisture play a role?
– No
• DfR found delamination primarily around the
edge and away from PTH sites after MSL testing
• IBM found minimal differences after a 24 hr bake
of coupons with heavy copper (>2 oz)
• Delamination / cracking observed in board stored
for short (<2 weeks) periods of time
– Yes
• DfR customer found improvement after 48 hrs at
125C
• A number of companies now require 5 – 24 hour
bake before reflow
• IBM found improvement with coupons with nominal
copper
• DfR observed more rapid degradation of boards
exposed to moisture, even after multiple reflows
• Some customers specifying maximum moisture
absorption
• Where does the moisture come from?
Cracking and Moisture (cont.)
• Storage of prepregs and laminates
• Drilling process
– Moisture is absorbed by the side walls
(microcracks?)
– Trapped after plating
• Storage of PCBs at PCB manufacturer
• Storage of PCBs at CCA manufacturer
PCB Trace Peeling
• Delamination of trace from surface of the board
• Sources of increased stress
– Excessive temperatures during high temperature processes
– Insufficient curing of resin
– Insufficient curing of solder mask
• Sources of decreased strength
– Improper preparation of copper foil
– Excessive undercut
Plated Through Holes (PTH)
•
Voids
– Can cause large stress concentrations,
resulting in crack initiation.
– The location of the voids can provide
crucial information in identifying the
defective process
•
•
•
•
•
Around the glass bundles
In the area of the resin
At the inner layer interconnects (aka, wedge
voids)
Center or edges of the PTH
Etch pits
–
–
–
Due to either insufficient tin resist deposition or
improper outer-layer etching process and
rework.
Cause large stress concentrations locally,
increasing likelihood of crack initiation
Large etch pits can result in a electrical open
Plated Through Holes (PTH)
Spring-Loaded
Pins
•
Overstress cracking
– CTE mismatch places PTH in
compression
– Pressure applied during "bed-of-nails"
can compress PTH
– In-circuit testing (ICT) rarely performed
at operating temperatures
•
Fatigue
– Circumferential cracking of the copper
plating that forms the PTH wall
– Driven by differential expansion between
the copper plating (~17 ppm) and the
out-of-plane CTE of the printed board
(~70 ppm)
– Industry-accepted failure model: IPCTR-579
PCB Robustness: Qualifying Printed Boards
•
•
This activity may provide greatest return on investment
Use appropriate number of reflows or wave
– In-circuit testing (ICT) combined with construction analysis
(cracks can be latent defect)
– 6X Solder Float (at 288C) may not be directly applicable
•
Note: higher Tg / phenolic is not necessarily better
– Lower adhesion to copper (greater likelihood of delamination)
– Greater risk of drilling issues
– Potential for pad cratering
•
Higher reflow and wave solder temperatures may induce solder
mask delamination
– Especially for marginal materials and processes
– More aggressive flux formulations may also play a role
– Need to re-emphasize IPC SM-840 qualification procedures
Material Selection - Laminate
• Higher reflow and wave solder temperatures
may induce delamination
– Especially for marginal materials and processes
• Not all RoHS compliant laminates are Pb-free process capable!
• Specify your laminate by name – not type or “equivalent”
– Role of proper packaging and storage
• PCBs should remain in sealed packaging until assembly
– Reseal partially opened bricks
– Package PCBs in brick counts which closely emulate run quantities
• PCBs should be stored in temperature and humidity controlled
conditions
• Bake when needed
• Packaging in MBB (moisture barrier bags) with HIC (humidity
indicator cards) may be needed for some laminates
• Need to re-emphasize IPC SM-840
qualification procedures
PCB Supply Chain Best
Practices
PCBs as Critical Components
• PCBs should be considered critical components or a
critical commodity.
• Without stringent controls in place for PCB supplier
selection, qualification, and management, long term
product quality and reliability is simply not achievable.
• This section will cover some common best practices
and recommendations for management of your PCB
suppliers.
PCB Best Practices: Commodity Team
• Existence of a PCB Commodity Team with at least one
representative from each of the following areas:
– Design
– Manufacturing
– Purchasing
– Quality/Reliability
• The team should meet on a minimum monthly basis to
discuss new products and technology requirements in the
development pipeline.
• Pricing, delivery, and quality performance issues with
approved PCB suppliers should also be reviewed.
• The team is also tasked with identifying new suppliers and
creating supplier selection and monitoring criteria.
PCB Best Practices: Selection Criteria
• Established PCB supplier selection criteria in place. The criteria
should be unique to your business, but some generally used criteria
are:
– Time in business
– Revenue
– Growth
– Employee Turnover
– Training Program
– Certified to the standards you require (IPC, MIL-SPEC, ISO, etc.)
– Capable of producing the technology you need as part of their
mainstream capabilities (don’t exist in their process “niches”
where they claim capability but have less than ~ 15% of their
volume built there.)
– Have quality and problem solving methodologies in place
– Have a technology roadmap
– Have a continuous improvement program in place
PCB Best Practices: Qualification Criteria
• Rigorous qualification criteria which includes:
– On site visits by someone knowledgeable in PCB
fabrication techniques.
• An onsite visit to the facility which will produce your PCBs is
vital.
• The site visit is your best opportunity to review process
controls, quality monitoring and analytical techniques, storage
and handling practices and conformance to generally
acceptable manufacturing practices.
• It is also the best way to meet and establish relationships with
the people responsible for manufacturing your product.
– Sample builds of an actual part you will produce which
are evaluated by the PCB supplier and that are also
independently evaluated by you or a representative to
the standards that you require.
PCB Best Practices: Supplier Tiering
• Use of supplier tiering (Low, Middle, High ) strategies if
you have a diverse product line with products that range
from simpler to complex. This allows for strategic tailoring
to save cost and to maximize supplier quality to your
product design. Match supplier qualifications to the
complexity of your product. Typical criteria for tiering
suppliers include:
– Finest line width
– Finest conductor spacing,
– Smallest drilled hole and via size
– Impedance control requirement
– Specialty laminate needed (Rogers, flex, mixed)
– Use of HDI, micro vias, blind or buried vias.
• Minimize use of suppliers who have to outsource critical
areas of construction. Again, do not exist in the margins of
their process capabilities
PCB Best Practices: Relationship Mgt.
•
Relationship Management. Ideally, you choose a strategy that allows you to
partner with your PCB suppliers for success. This is especially critical is you
have low volumes, low spend, or high technology and reliability requirements for
your PCBs. Some good practices include:
– Monthly conference calls with your PCB commodity team and each PCB
supplier. The PCB supplier team should members equivalent to your team
members.
– QBRs (quarterly business reviews) which review spend, quality, and
performance metrics, and also include “state of the business updates”
which address any known changes like factory expansion, move, or
relocation, critical staffing changes, new equipment/capability installation
etc.
•
The sharing is done from both sides with you sharing any data which you think would help
strengthen the business relationship – business growth, new product and quoting opportunities,
etc. At least twice per year, the QBRs should be joint onsite meetings which alternate between
your site and the supplier factory site. The factory supplier site QBR visit can double as the
annual on site visit and audit that you perform.
– Semi-Annual “Lunch and Learns” or technical presentations performed
onsite at your facility by your supplier. All suppliers perform education and
outreach on their processes and capabilities. They can educate your
technical community on PCB design for manufacturing, quality, reliability,
and low cost factors. They can also educate your technical community on
pitfalls, defects, and newly available technology. This is usually performed
free of charge to you. They’ll often spring for free lunch for attendees as
well in order to encourage attendance.
PCB Best Practices: Supplier Scorecards
• Supplier Scorecards are in place and performed
quarterly and yearly on a rolling basis. Typical
metrics include:
– On Time Delivery
– PPM Defect Rates
– Communication – speed, accuracy, channels,
responsiveness to quotes
– Quality Excursions / Root Cause Corrective Action Process
Resolution
– SCARs (Supplier Corrective Action Requests) Reporting
– Discussion of any recalls, notifications, scrap events
exceeding a certain dollar amount
PCB Best Practices: Cont. Quality Monitoring
• Continuous Quality Monitoring is in place. Consider
requiring and reviewing the following:
–
–
–
–
–
Top 3 PCB factory defects monitoring and reporting
Process control and improvement plans for the top 3 defects
Yield and scrap reporting for your products
Feedback on issues facing the industry
Reliability testing performed (HATS, IST, solder float, etc.)
• As a starting point, review the IPC-9151B, Printed Board
Process Capability, Quality, and Relative Reliability
(PCQR2) Benchmark Test Standard and Database at:
http://www.ipc.org/html/IPC-9151B.pdf
• Your PCB suppliers may be part of this activity already. Ask
if they participate and if you can get a copy of their results.
PCB Best Practices: Prototype Development
• Prototype Development
– In an ideal environment, all of your PCBs for a given
product should come from the same factory from start
to finish – prototype (feasibility), pre-release production
(testability & reliability), to released production
(manufacturability).
– Each factory move introduces an element of risk since
the product must go through setup and optimization
specific to the factory and equipment contained there.
– While this is not always possible for prototypes, all
PCBs intended for quality and reliability testing should
come from the actual PCB production facility.
Module 5: PCB Robustness
PTH Barrel Cracking
Conductive Anodic Filaments
(CAF)
Plated Through Hole (PTH) Fatigue
PTH fatigue is the
circumferential cracking of
the copper plating that
forms the PTH wall
It is driven by differential
expansion between the
copper plating (~17 ppm)
and the out-of-plane CTE
of the printed board (~70
ppm)
Industry-accepted
failure model
•
•
•
•
IPC-TR-579
PTH Fatigue: Pb-Free
PTH and Pb-Free (cont.)
• Findings
– Limited Z-axis
expansion and
optimized copper
plating prevents
degradation
• Industry response
– Movement to
Tg of 150 - 170C
– Z-axis expansion
between 2.5 to 3.5%
PCB Conductive Anodic Filaments (CAF)
•
•
•
CAF also referred to as metallic electro-migration
Electro-chemical process which involves the transport (usually ionic) of a
metal across a nonmetallic medium under the influence of an applied
electric field
CAF can cause current leakage, intermittent electrical shorts, and dielectric
breakdown between conductors in printed wiring boards
CAF: Examples
A
A
A:A Cross-Section
254
CAF: Examples
CAF: Examples
CAF: Pb-Free
o
Major concern in telecom/server industry
o
o
o
o
Focus on specific designs
o
o
o
o
o
Different epoxy formulations
Higher quality weaves
Phenolic cured epoxy (filled)
o
o
o
Large (>12x18) / multilayer (>10)
Fine pitch (0.8, 1.0 mm) ball grid arrays
(BGAs)
Solutions?
CAF ‘resistant’ laminate
o
o
Frequency of events can increase by two
orders of magnitude
Time to failure can drop from >750h to 50h
Initially, no “qualified” printed boards
Can be much better
Sensitive to drilling
Increased price?
o
Sometimes, not always
Module 5: PCB Robustness
Strain Flexure Issues & Pad Cratering
Electro-Chemical Migration (ECM)
Cleanliness
Design for Manufacturing & Process Review
• Depanelization Process
– Look at how panel is supported during the
process so that it is never allowed to
“dangle” or flex
– Vulnerable BGA and ceramic components
along the PCB edge
NEMI study showed SAC is more
Sensitive to bend stress.
LF
Laminate Load
Bearing
Capability
LF limit
PbSn
PbSn limit
PCB deflection
Onew ay Analysis of Load (kN) By S older Alloy
0.5
0.45
0.4
Load (kN)
Sources of strain can be ICT, stuffing throughhole components, shipping/handling, mounting
to a chassis, or shock events.
Tensile force on
pad and Laminate
SAC Solder is More Vulnerable to Strain
0.35
0.3
0.25
0.2
0.15
0.1
SAC
Sn-Pb
Solder Alloy
Each Pair
Student's t
0.05
Means and Std Dev iations
Level
SAC
Sn-Pb
Number
18
18
Mean
0.230859
0.416101
Std Dev
Std Err Mean
0.056591
0.040408
0.01334
0.00952
Lower 95%
0.20272
0.39601
Upper 95%
0.25900
0.43620
ICT Strain: Fixture & Process Analysis
•
•
–
–
Review/perform ICT strain evaluation at fixture mfg and in process: 500 us, IPC 9701
and 9704 specs, critical for QFN, CSP, and BGA
http://www.rematek.com/download_center/board_stress_analysis.pdf
To reduce the pressures exerted on a PCB, the first and simplest solution is to reduce the
probes forces, when this is possible.
Secondly, the positioning of the fingers/stoppers must be optimized to control the probe
forces. But this is often very difficult to achieve. Mechanically, the stoppers must be
located exactly under the pressure fingers to avoid the creation of shear points
Strain & Flexure: Pad Cratering
o
Cracking initiating within the laminate during a dynamic
mechanical event
o
In circuit testing (ICT), board depanelization, connector insertion,
shock and vibration, etc.
G. Shade, Intel (2006)
Pad Cratering
• Drivers
– Finer pitch components
– More brittle laminates
– Stiffer solders (SAC vs.
SnPb)
– Presence of a large heat sink
– Pad Design
• Difficult to detect using
standard procedures
– X-ray, dye-n-pry, ball shear,
and ball pull
Intel (2006)
Solutions to Pad Cratering
• Board Redesign
– Solder mask defined vs. non-solder mask defined
• Limitations on board flexure
– 500 microstrain max, Component, location, and
PCB thickness dependent
• More compliant solder
– SAC305 is relatively rigid, SAC105 and SNC are
possible alternatives
• New acceptance criteria for laminate materials
– Intel-led industry effort
– Attempting to characterize laminate material using
high-speed ball pull and shear testing, Results
inconclusive to-date
Laminate Acceptance Criteria
• Intel-led industry effort
– Attempting to characterize laminate
material using high-speed ball pull and
shear testing
– Results inconclusive to-date
• Alternative approach
– Require reporting of fracture toughness
and elastic modulus
Is Pad Cratering a Pb-Free Issue?
35x35mm, 388 I/O BGA; 0.76 mm/min
Average Fracture
Paste
Solder Ball
Std Dev (N)
Load (N)
SnPb
SnPb
692
93
Sn4.0Ag0.5Cu
SnPb
656
102
Sn4.0Ag0.5Cu
935
190
Roubaud, HP
APEX 2001
PCB Cleanliness: Moving Forward
• Extensive effort to update PCB Cleanliness Standards
• IPC-5701: Users Guide for Cleanliness of Unpopulated
Printed Boards (2003)
• IPC-5702: Guidelines for OEMs in Determining
Acceptable Levels of Cleanliness of Unpopulated Printed
Boards (2007)
• IPC-5703: Guidelines for Printed Board Fabricators in
Determining Acceptable Levels of Cleanliness of
Unpopulated Printed Boards (Draft)
• IPC-5704: Cleanliness Requirements for Unpopulated
Electro-Chemical Migration: Overview
• Insidious failure mechanism
– Self-healing: leads to large number
of no-trouble-found (NTF)
– Can occur at nominal voltages (5 V)
and room conditions (25C, 60%RH)
elapsed time
12 sec.
• Due to the presence of contaminants
on the surface of the board
– Strongest drivers are halides (chlorides and bromides)
– Weak organic acids (WOAs) and polyglycols can also lead to
drops in the surface insulation resistance
• Primarily controlled through controls on cleanliness
– Minimal differentiation between existing Pb-free solders, SAC
and SnCu, and SnPb
– Other Pb-free alloys may be more susceptible (e.g., SnZn)
Cleanliness Analysis & Failure Analysis
• Cleanliness Measurement Techniques
• Failure Analysis Techniques and
Descriptions
• Components of Concern / Case Study
• Tools
270
Cleanliness Measurement Techniques
Test Name
Acronym
Method
Description
Surface Insulation Resistance
SIR
IPC-TM-650, 2.6.3.3
Performed on test article, >1E8 Ω after min 168 hrs,
standard comb pattern
[8 more test methods identified
by DfR]
Ion Chromatography
IC
IPC-TM-650, 2.3.28
Heat sample in 80˚C, 75/25 IPA/H20 solution, 1 hr,
[column specified by TM? AS11 column for anion
analysis and a CS12A column for cation analysis used
on GSFC project]. No established accept/reject
standard.
Resistance of Solvent Extract
ROSE
IPC-TM-650, 2.3.25
Pass 75/25 IPA/H20 solution over both sides of
finished PWA, measure resistivity of solution, >2E6
Ω-cm
NASA-STD-8739.2, para
11.7
Tests cleaning bath using automated equipment and a
salt-equivalency standard, <1.55 µg/cm2 (<10 µg/in2)
IPC-TM-650, 2.6.14.1
Performed on a test article, 10V, 65˚C/88.5% RH, 596
hrs, IRfinal must not degrade by more than a decade
from IRinitial, no filament growth reducing electrode
spacing by >20%, no corrosion
Sodium Chloride Salt
Equivalent Ionic
Contamination (Omega
Meter)
Technique
ROSE
EM
Equivalency Factor
1
Omega-Meter
~1.5
Ion-Chromatography
~4.0
Source: PCBA Cleanliness Guidelines, C. Hillman,
http://www.dfrsolutions.com/uploads/webcasts/PCBA_Cleanliness/in
dex.htm
Equivalency factor in last row confirmed by Trace Laboratories in
white paper Solvent Extraction Matrix Selection and its Potential
Affects on Cleanliness Test Results, K. Sellers, J. Radman, via testing.
Weak Organic Acid Detection
• ROSE and Omega-Meter tests DO NOT detect WOAs (weak organic
acids). Successfully passing these “cleanliness” tests does not ensure
cleanliness. Why?
– “Bulk” testing best used for process equipment monitoring
– ROSE has insufficient fidelity1/
– IPA reduces solubility of water soluble WOAs (more testing is planned) 1/
• ROSE and Omega-Meter are suitable for bare PCB cleanliness testing
and for finding halide residues. [note: some halides will be built into the
board by design or by low quality and cannot be removed with cleaning
by the user, they will be released at soldering temperatures]
• Ion Chromatography (IC) is only test that finds and quantifies WOAs
– No uniform/standard accept/reject limits
• WOAs change approach to cleanliness assurance:
–
–
–
item-level testing (screening) is not available
emphasis falls to production line monitoring
method of monitoring is time consuming and involves additional expense
• Lot jeopardy may be larger due to longer time between quality monitor
data sets
1/ Solvent Extraction Matrix Selection and its Potential Affects on Cleanliness Test Results, K. Sellers, J. Radman, Trace
Laboratories
STI
Washed 1/
DfR2/
Chloride
<6
<2
Nitrite
<3
<2-4
Sulfate
<3
Bromide
<10
<10
Nitrate
<3
<2-4
Phosphate
<3
Anions
Weak
Organic
Acids
<3
Formate
<3
MSA,
Adipic,
Succinic
(total)
<25
GE2/
DoD2/
IPC2/
ACI2/
“Medical”3/
(90/10 DI/IPA)
<2
<3.5
<6.1
<6.1
<10
All units in μg of ion per in2
<10
<10
<7.8
<7.8
<3
<4
<15
<6
<4
<4
<175
Acetate
Foresite
<150
<30
<4
Users are establishing their own pass/fail
limits while no standard exists
<4
<2
No obvious trend for WOA acceptance limit
Cations
May be seeing mixtures of absolute Max
limits and control limits
Lithium
<3
Sodium
<3
Ammoniu
m
<3
<4
Potassium
<3
<4
1/ Analytical Techniques to Identify Unexpected Contaminants On Electronic Assemblies, K. Freeman, STI Electronics
2/ PCBA Cleanliness Guidelines, C. Hillman, http://www.dfrsolutions.com/uploads/webcasts/PCBA_Cleanliness/index.htm
3/ Solvent Extraction Matrix Selection and its Potential Affects on Cleanliness Test Results, K. Sellers, J. Radman, Trace Laboratories
<4
Reduce & Control Cleanliness Concerns
• Incoming PCB Cleanliness
– Cleanliness testing performed using ROSE (resistivity of solvent
extracted) or Omega-Meter method (ionic cleanliness, NaCl
equivalent)
• Consider cleanliness requirements in terms of
IC (ion chromatography) test for PCBs using
WS flux
– Don’t use ROSE or Omegameter test as single option (at all? Risk
from dirty IPA)
– Inspection method with accept/reject limit
– Sampling criteria
• Control cleanliness throughout the process
from start to finish.
Recommendations – Process Qualification
• Validate compatibility of all new process
materials using SIR testing.
• Continue spot check testing of cleanliness using
ion chromatography under low profile SMT parts
BTC, CSP & Low Profile Cleanliness Issues
• Low or no standoff parts are particularly
vulnerable to cleanliness / residual flux
problems
– Difficult to clean under
– Short paths from lead to lead or lead to via
– Can result in leakage resistance, shorts,
corrosion, electrochemical migration,
dendritic growth
Cleanliness: Dendritic Growth
• Large area, multi-I/O and low standoff can trap flux
under the QFN
• Processes using no-clean flux should be requalified
– Particular configuration could result in weak organic acid
concentrations above maximum (150 – 200 ug/in2)
• Those processes not using no-clean flux will likely
experience dendritic growth without modification of
cleaning process
– Changes in water temperature
– Changes in saponifier
– Changes to impingement jets
Some Affordable Tools to consider to enhance
cleanliness
• Portable Preheater:
– Allows for controlled
rework/repair/replace
ment at a debug
bench
– Heats and volatilizes
more flux
– http://www.zeph.com
/airbathseries.htm
Temperature Indicating Labels/Strips
• Temperature (and
humidity) strips and labels
are simple, inexpensive,
and easy to use
• Quickly validates preheat
& soldering profiles
• http://www.omega.com/to
c_asp/sectionSC.asp?sec
tion=F&book=temperature
Refillable Flux/Liquid Pen
• Allows for controlled
application of fluxes,
cleaners, and other
liquids
• http://www.startinter
national.com/prodsu
mm.asp?id=34&type
=cat&level=1
Module 6: Solders
Soldering
Discussion of 2nd generation Pbfree alloys (e.g., SN100C)
Intermetallic formation
Type of Assembly- Single or Double Sided Board
• Double Sided boards with Plated Through Hole
Produce Stronger Solder Joints
– Filling the through hole barrel with solder
covers more of the lead with more solder.
– Producing a stronger joint
that is more fatigue resistance.
Single Sided vs Double Sided Plated Thru-Hole (PTH) PCBs
– Less susceptible to variation
- Thin Solder Joints of Single Sided PBC’s
Allowed
Leads
to Wiggle More Resulting In Early Solder Fatigue
during the soldering process
Larger Solid Mass & Reduced Variation of Solder in PTH
Increased Fatigue Strength and Life by 30-50x.
Typical Process Capabilities Defects Rates for Soldering Processes
Defects Per Million (Joint) Opportunities (DPMO)
Example 1,000 Joints/Board on 1,000 Boards
DPMO
Solder
Process
Standard
Best in
Class
Hand
5000
N/A
Wave
500
20 - 100
Reflow
50
<10
• Designs that avoid manual soldering operations reduce
defects.
– Main Issues: Insufficient solder or bonding, Missed joints, Heat Damage
• Reflow soldering produces less defects that wave soldering.
– Main Issues: Solder Bridges, Solder Skips/Insufficient Solder, Missing Component
Reflow Profile Optimization Tuning –
4 Main Criteria
•
Preheating Phase - Ramp & Soak vs. Straight Ramp preheating profiles
– Ramp & Soak (soak period just below liquidus), more common, more forgiving.
•
•
Allow flux solvents to fully evaporate and activate to deoxidize the surfaces to be soldered.
Allows temperature equalization across the entire assembly.
– Consistent soldering and reduces tomb stoning.
• However, If too long, flux may be consumed resulting in excessive oxidation.
• Flux my be come volatile producing solder balls or voiding defects.
– Straight Line is faster and causes less thermal damage to materials
• But more susceptible to defect and quality variation, does not work well on complex assemblies.
•
Peak Temperature and Time at (above) Liquidus (TAL)
•
Cooling Rate of SnAgCu effects the Microstructure & Bulk Intermetallics
•
Overall Time (Costs & Efficiency)
– A balance between being hot enough for long enough to achieve good consistent
solder wetting and bonding for proper joint formation, across the entire assembly.
– Yet as quickly as possible to prevent thermal damage to the components and board
and to prevent excessive copper dissolution and excessive intermetallic growth.
– Faster cooling rates produce a finer, stronger microstructure and limits intermetallics.
– Over all throughput is determined the board size/complexity and the oven's heat
transfer capabilities.
Typical Temperature Profiles in Wave Soldering

Preheating top and bottom side is essential
o
o
o
Mitigate thermal shock stress.
Activate some fluxes and heat component leads.
Needed to enable solder to wick up and fill holes.
Time-Temperature Relationships for Soldering: The sweet spot
between poor soldering and component or board damage
Maximum time-temperature “damage” curve
Maximum part temperature
Temperature
Maximum PWB temperature
Minimum solder temperature
Acceptable processing region
Minimum time-temperature curve for acceptable soldering
Time
Example: Incomplete Hole Fill
o
Poor solder hole fill can cause lead to solder joint crack failures. Can be
caused by:
o
o
o
o
Insufficient top side heating prevented solder from wicking up into PTH Barrel
Insufficient flux or flux activity for the surface finish in use
Lack of thermal relief for large copper planes
PCB hole wall integrity issues – voids, plating, contamination
Known Pb-Free Soldering Material Inherent Quality Issues
Pb-Free Solders have a tendency to create fillet lifting, tearing and pad lifting defects.
Pb-Free Solders have a tendency to
create more and larger “Void
Defects”
Reduced Wetting tendency of PbFree Solders can create insufficient
bonding and poor through hole pin
filling defects.
Module 6: Solders
Discussion of 2nd generation Pbfree alloys (e.g., SN100C)
Intermetallic formation
Divergence in Lead Free Solder Selection
??
• Considerations include
– PRICE!
– Insufficient performance
– Newly identified failure
mechanisms
• Market still unsteady;
proliferation and evolution of
material sets
• Solder seeing the fastest
increase in market share?
SnAg SnAgCu SnCu
SAC405
SAC305
SAC105
SNC
SACX
– SnCu+Ni (SNC)
SNCX
The Current State of Lead-Free
• Component suppliers
– SAC305 still dominant, but with increasing introduction
of low silver alloys (SAC205, SAC105, SAC0507)
• Solder Paste
– SAC305 still dominant
• Wave and Rework
– Sn07Cu+Ni (SN100C)
– Sn07Cu+Co (SN100e)
– Sn07Cu+Ni+Bi (K100LD)
• HASL PCB Coating
– Sn07Cu+Ni (SN100C)
Solder Trends
• SAC305 dominates
surface mount reflow
(SMT)
• SAC105 increasingly
being used in area array
components in mobile
applications
• SNC pervasive in wave
solder and HASL
– Increasing acceptance
in Japan for SMT
• Intensive positioning for
“X” alloys (SACX, SNCX)
K-W Moon et al, J. Electronic Materials, 29 (2000) 1122-1236
What are Solder Suppliers Promoting?
Company
Paste
Senju
Wire / Wave
ECO Solder (SAC305)
Nihon Genma
NP303 (SAC305),
NP601 (Sn8Zn3Bi)
NP303 (SAC305),
NP103 (SAC0307)
Metallic Resources
SAC305
SAC305,
SC995e (Sn05Cu+Co)
Koki
S3X (SAC305),
S3XNI58 (SAC305+Ni+In),
SB6N58 (Sn3.5Ag0.5Bi6In)
S3X (SAC305),
S03X7C (SAC0307+0.03Co)
Heraeus
Cookson / Alpha Metals
SAC405
SACX (SAC0307+Bi+0.1P+0.02RareEarth+0.01Sb)
Kester
K100LD (Sn07Cu+0.05Ni+Bi)
Qualitek
SN100e (Sn07Cu+0.05Co)
Nihon Superior
SN100C (Sn07Cu+0.05Ni+Ge)
AIM
SN100C (Sn07Cu+0.05Ni+Ge)
Indium
Amtech
Shenmao
Indium5.1AT (SAC305)
N/A
SAC305, Sn3.5Ag, Sn5Ag, Sn07Cu, Sn5Sb
SAC305 to SAC405, SAC305+0.06Ni+0.01Ge
Henkel
No preference
EFD
No preference
P. Kay Metals
No preference
2nd Generation Pb-Free Solder (Thoughts)
• Ni-modified SnCu and low silver SAC are the primary front
runners
– Both seem to display reliability behaviors between SAC305
and SnPb
– Very limited reliability information on low silver SAC at this
time
• Proliferation of custom alloys is unhealthy for the electronics
industry
– Too much time spent on material identification,
characterization, and risk assessment
– One customer had SAC405, SAC387, SAC305, SAC105,
SAC0307, and SAC125Ni on one board!
• Almost no component manufacturers assess these new
alloys from a physics of failure
– Test to spec mentality
– Huge risk for escapes
Intermetallic Growth Effects
• Changes in electrical
resistance
– Minimal
Sn3.8Ag0.7Cu / OSP
• Changes in shear strength
– Minimal
• Changes in pull strength
– Minimal
Sn0.5Cu / ENIG
Module 6: Solders
Copper Dissolution
Mixed Assembly
Solders: Copper Dissolution
o
o
The reduction or elimination of surface copper conductors
due to repeated exposure to Sn-based solders
Bath, iNEMI
Significant concern for
industries that perform
extensive rework
o
Telecom, military,
avionics
ENIG Plating
60 sec. exposure
274ºC solder fountain
Solders: Copper Dissolution (cont.)
• PTH knee is the point of
greatest plating reduction
• Primarily a rework/repair
issue
– Celestica identified
significant risk with >1X
rework
• Already having a
detrimental effect
– Major OEM unable to repair
ball grid arrays (BGAs)
S. Zweigart, Solectron
Copper Dissolution (Contact Time)
•
Contact time is the major driver
–
–
•
Some indications of a 25-30 second limit
Preheat and pot temp. seem to have a lesser effect
Optimum conditions (for SAC)
–
–
–
Contact time (max): 47 sec. (cumulative)
Preheat temperature: 140-150°C
Pot temperature:
260-265°C
A Study of Copper Dissolution During Pb-Free PTH Rework Using a
Thermally Massive Test Vehicle , C. Hamilton (May 2007)
Contact Time (cont.)
• Copper Erosion During Assembly By Lead Free Solder (HDPUG)
Solutions to Cu Dissolution
• Option 1: restriction on rework
– Number of reworks or
contact time
• Option 2: solder material
– Indications that SNC can
decrease dissolution rates
– Reduced diffusion rate
through Sn-Ni-Cu
intermetallics
• Option 3: board plating
– Some considering ENIG
– Some considering SNC
HASL
A Study of Copper Dissolution During Pb-Free PTH Rework Using a
Thermally Massive Test Vehicle , C. Hamilton (May 2007)
Dissolution: Copper vs. Nickel
Albrecht, SMTA 2006
Albrecht, SMTA 2006
• Nickel (Ni) plating has a dissolution rate
approximately 1/10th of copper (Cu) plating
– Given similar solder temperatures and contact times
Mixed Assembly
o
o
Primarily refers to Pb-free
BGAs assembled using
SnPb eutectic solder paste
Why?
o
o
Area array devices (e.g.,
ball grid array, chip scale
package) with eutectic
solder balls are becoming
obsolete
Military, avionics,
telecommunications,
industrial do not want to
transition to Pb-free…yet
UIC
SnPb BGAs and the Component Industry
Prismark, iNEMI SnPb-Compatible BGA
Workshop (IPC/APEX 2007)
For certain device types, HiRel dominates market share
•
•
Mil/Aero is ~10% of Hi-Rel
Hi-Rel products tend to be
of higher value
•
•
Greater profit for part
suppliers
SnPb BGAs – Supplier Response
Result is wide variation in SnPb BGA availability
Driven by market (Micron)
•
•
•
•
iNEMI SnPb-Compatible BGA Workshop
(IPC/APEX 2007)
SDR SDRAM preferred by Hi-Rel (low Pb-free penetration)
DDR SDRAM preferred by Computers (high Pb-free penetration), though SnPb available past
2011
Driven by lifecycle (Freescale)
•
•
Legacy FC-BGAs are primarily SnPb; new FC-BGAs are primarily Pb-free
Mixed Assembly: Reflow
Initial studies focused on peak temperature
Identified melt temperature of solder ball as critical
parameter
•
•
•
•
217°C for SAC305
Ensured ball collapse and intermixing
Recommendations
•
•
•
•
Minimum peak reflow temperature of 220°C
Reflow temperatures below 220°C may result in poor assembly
yields and/or inadequate interconnect reliability
For increased margin, >225 to 245°C peak
Mixed Assembly: Solder Joint Morphology
Motorola
Mixed Assembly: Peak Temp Statements
Cisco Systems:
•
•
Formation of SnPbAg phase (Tm = 179°C) may allow for lower
reflow temperatures
Intel:
Infineon:
•
•
•
•
•
> 217°C
215 - 230°C
220°C peak used in exceptional circumstances
230°C peak recommended
IBM:
•
> 210°C
245°C
Minimum time above liquidus (TAL) of 80 seconds
Need to watch for voiding
•
•
Talk to your paste supplier
Mixed Assembly: Time Above Liquidus
•
Effect is inconclusive
Kinyanjui, Sanmina-SCI,
iNEMI SnPb-Compatible BGA
Mixed Assembly: Solder Paste Volume
Moderate solder paste volume
Large solder paste volume
Some conflict
•
•
•
•
•
Sanmina claims no effect
Celestica claims significant effect
Other factors may play a greater role
Additional investigation necessary
Snugovsky, Celestica (2005)
Mixed Assembly: Effect of Pitch
Intel: reduced self alignment
•
•
•
Degree of difficulty: 0.5mm > 0.8mm > 1 - 1.27mm pitch
component
Sanmina: improved mixing
Mixed Assembly: Temp Cycling Results
HP: 0 to 100ºC, 214ºC Peak Temp
99
Cumulative Failure (%)
SnPb
30
SnAgCu/SnPb
3
SnAgCu/SnAgCu
0.3
0.03
10
100
1,000
Cycles to Failure
8,000
Mixed Assembly (Other)
• iNEMI recently reported issues with low
silver (Ag) Pb-free alloys
– SAC105, SAC0307, etc.
• High pasty range creates voiding and
shrinkage cracks
– Mixed assembly with low-silver SAC is not
recommended
Mixed Assembly: Conclusions
• A potentially lower risk than complete
transition to Pb-free
– Important note: more studies on vibration and
shock performance should be performed
• The preferred approach for some high
reliability manufacturers (military, telecom):
– Acceptance of mixed assembly could be
driven by GEIA-STD-0005-1
318
Mixed Assembly: Alternatives
• Other options on dealing with Pb-free BGAs
other than mixing with SnPb
– Placement post-reflow
• Two flux options
– Application of Pb-free solder paste
– Application of flux preform
• Two soldering options
– Hot air (manual)
– Laser soldering (automatic)
319
Case Study: Manufacturability
One of the most common drivers for failure is
inappropriate adoption of new technologies
•
•
The path from consumer (high volume, short lifetime) to high
reliability is not always clear
Obtaining relevant information
can be difficult
•
•
•
Information is often segmented
Focus on opportunity, not risks
Can be especially true for
component packaging
•
•
BGA, flip chip, QFN
Leadless Near Chip Scale
Packages
(LNCSP)
LNCSP: What is it?
• Leadless Near Chip Scale Packages
– Also known as
•
•
•
•
BTC – Bottom Termination Components
Leadframe Chip Scale Package (LF-CSP)
MicroLeadFrame (MLF)
Others (MLP, LPCC, QLP, HVLNCSP, QFN, DFN, SON, LGA, etc.)
• Overmolded leadframe with bond pads exposed on the bottom
and arranged along the periphery of the package
– External connections consist of metallized terminations that are
an integral part of the component body.
– Developed in the early to
mid-1990’s by Motorola,
Toshiba, Amkor, etc.
– Standardized by JEDEC/EIAJ in
late-1990’s
– Fastest growing package type
LNCSP Advantages: Size and Cost
• Smaller, lighter and thinner than comparable
leaded packages
– Allows for greater functionality per volume
• Reduces cost
– Component manufacturers: More ICs per frame
– OEMs: Reduced board size
• Attempts to limit the footprint of lower I/O devices
have previously been stymied for cost reasons
– BGA materials and process too expensive
Advantages: Manufacturability
• Small package without placement and solder printing
constraints of fine pitch leaded devices
– No special handling/trays to avoid bent or non planar pins
– Easier to place correctly on PCB pads than fine pitch QFPs,
TSOPs, etc.
– Larger pad geometry makes for simpler solder paste printing
– Less prone to bridging defects when proper pad design and
stencil apertures are used.
• Reduced popcorning moisture sensitivity issues –
smaller package
Advantages: Thermal Performance
• More direct thermal path with larger area
– Die  Die Attach  Thermal Pad 
Solder  Board Bond Pad

 qJa for the QFN is about half of a
leaded counterpart (as per JESD-51)
– Allows for 2X increase in power dissipation
Advantages: Inductance
• At higher operating frequencies, inductance of the
gold wire and long lead-frame traces will affect
performance
• Inductance of LNCSP is half its leaded counterpart
because it eliminates gullwing leads and shortens
wire lengths
Popular for
RF Designs
http://ap.pennnet.com/display_article/153955/36/ARTCL/none/none/1/The-back-end-process:-Step-9-LNCSP-Singulation/
LNCSP: Why Not?
• LNCSP is a ‘next generation’ technology
for non-consumer electronic OEMs due to
concerns with
– Manufacturability
– Compatibility with other OEM processes
– Reliability
• Acceptance of this package, especially in
long-life, severe environment, highreliability applications, is currently limited
as a result
LNCSP Manufacturability
Challenges
LNCSP Manufacturability: Bond Pads
•
Non Solder Mask Defined Pads Preferred (NSMD)
– Copper etch process has tighter process control than solder mask process
– Makes for more consistent, strong solder joints since solder bonds to both tops
and sides of pads
•
Use solder mask defined pads (SMD) with care
– Can be used to avoid bridging between pads, especially between thermal and
signal pads.
– Pads can significantly grow in size based on PCB manufacturer capabilities
NSMD
Images courtesy of Screaming Circuits
LNCSP Manufacturability: Bond Pads
•
Can lose solder volume and standoff height through vias in thermal pads
– May need to tent, plug, or cap vias to keep sufficient paste volume
– Reduced standoff weight reduces cleanability and pathways for flux outgassing
• Increased potential for contamination related failures
– Tenting and plugging vias is often not well controlled and can lead to placement and
chemical entrapment issues
– Exercise care with devices placed on opposing side of LNCSP
– Can create placement issues if solder “bumps” are created in vias
– Can create solder short conditions on the opposing device
– Capping is a more robust, more expensive process that eliminates these concerns
Thermal
vias
capped
with solder
mask
Images courtesy of Screaming Circuits
Bond Pads (cont.)
• Extend bond pad 0.2 – 0.3 mm
beyond package footprint
– May or may not solder to cut edge
– Allows for better visual inspection
• Need X-ray for best results
– Allows for verification of bridging,
adequate solder coverage and
void percentage
– Cannot detect head in pillow or
fractures
– Note: Lack of good criteria
for acceptable voiding of the
thermal pad. Depends upon
thermal needs.
Manufacturability: Stencil Design
• Stencil thickness and aperture design are crucial for
manufacturability
– Excessive amount of paste can induce
float, lifting the LNCSP off the board
– Excessive voiding can also be induced
through inappropriate stencil design
• Follow manufacturer’s guidelines
– Goal is 2-3 mils of post-reflow solder thickness
• Rules of thumb (thermal pad)
– Ratio of aperture/pad ~0.5:1
– Consider multiple, smaller apertures
(avoid large bricks of solder paste)
– Reduces propensity for solder balling
Manufacturability: Reflow & Moisture
•
LNCSP solder joints are more susceptible to dimensional changes
•
Case Study: Military supplier experienced solder separation under
LNCSP
•
LNCSP supplier admitted that the package was more susceptible to
moisture absorption that initially expected
– Resulted in transient swelling during reflow soldering
– Induced vertical lift, causing solder separation
•
Was not popcorning
– No evidence of cracking or delamination in component package
Corrective Actions: Manufacturing
• Verify good MSL (moisture sensitivity level)
handling and procedure procedures
• Reflow Profile: Specify and confirm
• Room temperature to preheat: maximum 2-3oC/sec
• Preheat to at least 150oC
• Preheat to maximum temperature: maximum 45oC/sec
• Cooling: maximum 2-3oC/sec
• In conflict with profile from J-STD-020C which
allows up to 6oC/sec
• Make sure assembly is less than 60oC before any
cleaning processes
Manufacturability: LNCSP Joint Inspection
Goal is 2-3 mils of post-reflow
solder thickness
Convex or absence of fillet
highly likely
•Etching of leadframe can
prevent pad from reaching
edge of package
•Edge of bond pad is not
plated for solderability
• A large convex fillet is often an indication of issues
– Poor wetting under the LNCSP
– Tilting due to excessive solder paste under the thermal
pad
– Elevated solder surface tension, from insufficient solder
paste under the thermal pad, pulling the package down
Manufacturability: Rework
• Can be difficult to replace a
package and get adequate
soldering of thermal / internal
pads.
– Mini-stencils, preforms, or rebump
techniques can be used to get
sufficient solder volume
• Not directly accessible with
soldering iron and wire
– Portable preheaters used in
conjunction with soldering iron can
simplify small scale repair
processes
• Close proximity with capacitors
often requires adjacent
components to be resoldered /
replaced as well
Manufacturability: Board Flexure
• Area array devices are known to have board
flexure limitations
– In circuit testing (ICT), board depanelization, connector
insertion, manual assembly operations, shock and
vibration, etc. are common causes.
– For SAC attachment, maximum microstrain can be as
low as 500 ue
• Use IPC-JEDEC 9701 and 9704 specifications
• LNCSPs have an even lower level of compliance
– Limited quantifiable knowledge in this area
– Must be conservative during board build
– IPC is working on a specification similar to BGAs
Example: ICT Strain: Fixture & Process Analysis
•
•
•
Review/perform ICT strain evaluation at fixture mfg and in process: 500 us,
http://www.rematek.com/download_center/board_stress_analysis.pdf
To reduce the pressures exerted on a PCB, the first and simplest solution is to reduce
the probes forces, when this is possible.
Secondly, the positioning of the fingers/stoppers must be optimized to control the
probe forces. But this is often very difficult to achieve. Mechanically, the stoppers must
be located exactly under the pressure fingers to avoid the creation of shear points
Strain & Flexure: Pad Cratering

Cracking initiating within the laminate during a dynamic mechanical
event

In circuit testing (ICT), board depanelization,
connector insertion, shock and vibration, etc.
G. Shade, Intel (2006)
Pad Cratering
• Drivers
– Finer pitch components
– More brittle laminates
– Stiffer solders (SAC vs.
SnPb)
– Presence of a large heat sink
• Difficult to detect using
standard procedures
– X-ray, dye-n-pry, ball shear,
and ball pull
Intel (2006)
Solutions to Pad Cratering
•
Board Redesign
•
Limitations on board flexure
•
More compliant solder
•
New acceptance criteria for laminate materials
– Solder mask defined vs. non-solder mask defined
– 750 to 500 microstrain, Component dependent
– SAC305 is relatively rigid, SAC105 and SNC are possible
alternatives
– Intel-led industry effort
– Attempting to characterize laminate material using high-speed
ball pull and shear testing, Results inconclusive to-date
•
Alternative approach
– Require reporting of fracture toughness and elastic modulus
Reliability: Thermal Cycling
•
Order of magnitude reduction in
time to failure from QFP
– 3X reduction from BGA
•
Driven by die / package ratio
– 40% die; tf = 8K cycles (-40 /
125C)
– 75% die; tf = 800 cycles (-40 /
125C)
•
Driven by size and I/O#
– 44 I/O; tf = 1500 cycles (-40 /
125C)
– 56 I/O; tf = 1000 cycles (-40 /
125C)
•
Very dependent upon solder bond
with thermal pad
QFP: >10,000
BGA: 3,000 to 8,000
LNCSP: 1,000 to 3,000
Thermal Cycling: Conformal Coating
• Care must be taken when using
conformal coating over LNCSPs
– Coating can infiltrate under the
LNCSPs
– Small standoff height allows coating
to cause lift
• Hamilton Sundstrand found a
significant reduction in time to
failure (-55 / 125C)
– Uncoated: 2000 to 2500 cycles
– Coated: 300 to 700 cycles
• Also driven by solder joint
sensitivity to tensile stresses
– Damage evolution is far
higher than for shear stresses
Wrightson, SMTA Pan Pac 2007
Reliability: Bend Cycling
• Low degree of compliance
and large footprint can
also result in issues during
cyclic flexure events
• Example: IR tested a
5 x 6mm QFN to
JEDEC JESD22-B113
– Very low beta (~1)
– Suggests brittle fracture, possible
along the interface
Reliability: Dendritic Growth /
• Large area, multi-I/O and low standoff can trap flux
under the LNCSP
• Processes using no-clean flux should be requalified
– Particular configuration could result in weak organic acid
concentrations above maximum (150 – 200 ug/in2)
• Aqueous Cleaning processes will likely experience
dendritic growth without modifications like:
– Increase in water temperature
– Additions of saponifiers or solvents
– Changes to number and angle of impingement jets
Electric Field (Voltage/Distance)
• Voltage is a primary driver in two processes
– Electrodissolution (oxidation reaction)
– Ion Migration
• Electrodissolution
– Applied voltage must exceed EMF
– 0.13 V for Sn/Pb, 0.25 V for Ni, 0.34 V for Cu,
0.8 V for Ag, and 1.5 V for Au
• Ion migration
– Force on the ions, and therefore velocity, is a function
of electric field strength
Electric Field Strengths (Nominal)
Logic devices
• Previous generation
– 6.4 V/mm (SO32 -- 1.27
mm pitch, 5 VDC)
• Current generation
– 20 V/mm (TSSOP80 -0.4 mm pitch, 3.3 VDC)
•
•
Power devices
• Previous generation
– 64 V/mm (SOT23 -1.27 mm pitch, 50 VDC)
• Current generation
– 140 V/mm (QFN –
0.4 mm pitch, 24 VDC)
Copper traces: 240 V/mm (0.5 mm spacing, 120 VDC)
IPC-2221A allows 300 V/mm (0.1 mm spacing, 30 VDC)
Dendritic Growth (cont.)
• Component manufacturers are increasingly aware of
this issue and separate power and ground
– Linear Technologies (left) has strong separation power
and ground
– Intersil (right) has power and ground on adjacent pins
Electro-Chemical Migration: Details
• Insidious failure mechanism
– Self-healing: leads to large number
of no-trouble-found (NTF)
– Can occur at nominal voltages (5 V)
and room conditions (25C, 60%RH)
elapsed time
12 sec.
• Due to the presence of contaminants
on the surface of the board
– Strongest drivers are halides (chlorides and bromides)
– Weak organic acids (WOAs) and polyglycols can also lead to
drops in the surface insulation resistance
• Primarily controlled through controls on cleanliness
– Minimal differentiation between existing Pb-free solders, SAC
and SnCu, and SnPb
– Other Pb-free alloys may be more susceptible (e.g., SnZn)
PCB Cleanliness: Moving Forward
• Extensive effort to update PCB Cleanliness Standards
• IPC-5701: Users Guide for Cleanliness of Unpopulated
• IPC-5702: Guidelines for OEMs in Determining
Acceptable Levels of Cleanliness of Unpopulated Printed
Boards (2007)
• IPC-5703: Guidelines for Printed Board Fabricators in
Determining Acceptable Levels of Cleanliness of
Unpopulated Printed Boards (Draft)
• IPC-5704: Cleanliness Requirements for Unpopulated
Nominal Ionic Levels
• Bare printed circuit boards (PCBs)
– Chloride: 0.2 to 1 µg/inch2 (average of 0.5 to 1)
– Bromide: 1.0 to 5 µg/inch2 (average of 3 to 4)
• Assembled board (PCBA)
– Chloride: 0.2 to 1 µg/inch2 (average of 0.5 to 1)
– Bromide: 2.5 to 7 µg/inch2 (average of 5 to 7)
– Weak organic acids: 50 to 150 µg/inch2 (average of 120)
• Higher levels
– Corrosion/ECM issues at levels above 2 (typically 5 to 10)
– Corrosion/ECM issues at levels above 10 (typically 15 to 25)
– Corrosion/ECM issues at levels above 200 (typically 400)
• General rule
– Dependent upon board materials and complexity
Cleanliness Controls: Ion Chromatography
• Contamination tends to be controlled through industrial
specifications (IPC-6012, J-STD-001)
–
–
–
–
Primarily based on original military specification
10 mg/in2 of NaCl ‘equivalent’
Calculated to result in 2 megaohm surface insulation resistance (SIR)
Not necessarily best practice
• Best practice is contamination controlled through ion
chromatography (IC) testing
– IPC-TM-650, Method 2.3.28A
Pauls
General
Electric
NDCEE
DoD*
IPC*
ACI
Chloride (mg/in2)
2
3.5
4.5
6.1
6.1
10
Bromide (mg/in2)
20
10
15
7.8
7.8
15
*Based on R/O/I testing
Best Practices: PCBA
Cleanliness
• Confirm incoming PCB cleanliness
• Clean after soldering operations
• Control and measure
– Water quality going into process
– Assembly cleanliness
LNCSP: Risk Mitigation
• Assess manufacturability
–
–
–
–
–
DOE on stencil design
Degree of reflow profiling
Control of board flexure
Dual row LNCSP is especially difficult
Cleanliness is critical
• Assess reliability
– Ownership of 2nd level interconnect
is often lacking
– Extrapolate to needed field reliability
– Some companies have reballed LNCSP
to deal with concerns
Ongoing Learning Opportunities
• Some ideas for low cost continuing education
inside and outside of your company
– E-Learning at dfrsolutions.com
– Organize “Your Company Days”, Poster
Sessions, Demos
– Use internal electronic bulletin boards an
resources
– Brown Bags &” Lunch and Learns” from your
internal gurus and from your suppliers
• PCB
• Contract Manufacturers
• Electronics Materials - paste, fluxes, cleaners
Summary & Recap
• DfM is a proven, cost-effective strategic
methodology.
• Early, effective cross functional involvement:
– Reduces overall product development time (less changes, spins, problem
solving)
– Results in a smoother production launch
– Speeds time to market
– Reduces overall costs
• Designed right the first time
• Optimizes # of parts
• Optimizes # of process steps and use of correct, efficient steps
• Reduces labor costs to repair and resolve issues
• Improves overall production efficiency
• Build right the first time = less rework, scrap, and warranty costs
– Improves quality and reliability results in:
• Higher customer satisfaction
• Reduced warranty costs
Contact Information
Any Questions:
Contact Cheryl Tulkoff,
[email protected],
512-913-8624
Connect with me on Linked In!
[email protected]
www.dfrsolutions.com

Design for Manufacturing

Transcription

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