of charge traps

Charge-Trap
Charge
Trap NAND Flash Memory
Souvik Mahapatra
p
E E Dept, IIT Bombay, India
Contributions:
C
t ib ti
S d C,
Sandya
C Pawan
P
Singh,
Si h S
Suyog G
Gupta,
t K
Kshitij
hitij Auluck,
A l k
Piyush Dak, Sandeep Kasliwal, Udayan Ganguly, Dipankar Saha,
Gautam Mukhopadhyay, Juzer Vasi
Support: Applied Materials, Intel Corporation, SRC/GRC
1
Outline
FG NAND Flash scaling challenges
SiN based charge trap flash – material dependence
P/E simulation of SiN Flash
Metal nanodot Flash
Scalability simulation of m-ND Flash
2
NAND Flash Background
CG
DSL
CD 15nm
FG 50nm
TO 9nm
WL
SL
SSL
Figure: Samsung
L=35nm
No. of cells
BL
Memory state
•Electron transfer between substrate & FG define memory
state (write & erase)
•FG surrounded by TO & CD acts as electron storage well
(non-volatility, need 10yrs), though leak out occurs over
time (retention loss)
•Repeated Write/Erase (10-100K needed) causes memory3
wear out (cycling endurance)
NAND Flash Scaling
CG
CD 15nm
FG 50nm
TO 9nm
L=35nm
•More memory, faster access, reduced cost
•Guideline (ITRS roadmap): L=35nm (2009),
(2009)
28nm (2010/11), 22nm (2013/14)…
•SLC
SLC (1bit/
(1bit/cell),
ll) MLC (2 or 3 bits/cell)
bit / ll) for
f higher
hi h
density, higher reliability issues
Scaling penalty:
(1) Loss of CG – FG coupling
(2) Cell
C ll to
t cell
ll cross talk
t lk
(3) Non-scaling of TO, FG and
CD thickness
(4) Non-scaling of operating
voltage
(5) Higher reliability concern
Solution: Discrete trapbased charge storage
CG
CD, 12nm
SiN, 6nm
TO, 6nm
4
Planer CTF
Devices & test chip demonstrated (Samsung)
•Memory window
close down with W/E
cycling
•Data keeps leaking
out (worse than FG!)
•Loss of memory
operation
ti
CTF reliability worse than FG, no product yet
5
Retention Issue
Lateral or Vertical charge
g migration
g
Trap depth of SiN is key to control charge migration
Solution – to cut SiN above STI (Samsung, 2007)
6
NAND 3D Memory
3D CTF p
proposed
p
as a way
y to move forward below
20nm node: BiCs (Toshiba), TCAT (Samsung)
7
Motivation
CTF reliability
y improvement
p
needs:
Understanding
g impact
p
of device processing
p
g on
material and electrical properties
Proper device design (structure, composition)
Detailed electrical characterization & modeling –
feedback for intelligent
g
manufacturing
g
8
SANOS Device Structure
Trap parameters:
Nt,elec, Φt,elec
Nt,hole, Φt,hole
12 nm
15 nm
20 nm
6 nm
3-6 nm
Al2O3
Si+
SixNy
N+
Dis
stance (nm
m)
Gate
N+
Trap dist.
dist
(A.U.)
Φt,elec
Φt,hole
Si+
Ev
TO
Channel
Ec
SixNy
Al2O3
SiO2
Charge tunnel from substrate to SiN via TO,
Al2O3 used for leakage blocking
9
P/E Transients
12
4
N-rich
Si-rich
Si
rich
2
0
-2
P/E Wind
P
dow (V)
10
6
ΔVFB (V)
P
E
R.I.
Total memory window
8
6
4
2
0
N0
N1
N2
N3
N4
N+
Si+
W11
W2
W3
W6
W8
-2
-4 -8
10
-5
-2
10
10
Time (s)
1
10
-4
W 11
W2
W3
Splits
W6
Refrractive Ind
dex (R.I.)
8 P/E at +18V/-18V
1.95
1
95
2.00
2.05
2.10
2.15
W8
High-k blocking dielectric:
¾ Better coupling to channel
¾ Larger memory windows
P / E state (memory window) depend on SiN composition
10
ISPP and ISPE
N0
N1
N2
N3
N4
6
5
VFB(V
V)
4
N+
3
Si+
2
1
0
-1
10
15
Vg (V)
20
6
5
4
3
2
1
0
-1
1
-2
-3
-4
0
VFB(V
V)
7
25
N0
N1
N2
N3
N4
N+
Si+
-5
-10 -15
Vg (V)
N+ SiN
¾Higher electron trapping efficiency
¾Poor erase characteristics
Si+ SiN
¾Low P saturation levels
¾Higher erase efficiency
-20
-25
11
Charge loss (Retention)
0.8
N+
5.5
04
0.4
0.6
N1
N2
N3
N4
-1.6
-1.7
-1.8
-1.9
-2.0
-2.1
Si+
ΔVFB(V)
4.5
N+
0.3
04 N
0.4
+
Si
+
0.2
0.2
ΔVFB(V)
VFFB (V)
50
5.0
0.5
E state loss
P state loss
0.1
Si+
10
2
3
10
Time (s)
10
4
0.0
1.95
2.00
2.05 2.10
RI
R.I.
0.0
2.15
N+ SiN
¾ Deep electron traps - shallow hole traps
Si SiN
Si+
¾ Shallow electron traps - deep hole traps
P/E state retention dependent on SiN composition
12
Tunnel oxide thickness dependence
VFB(V
V)
55
5.5
5.0
2.5
ΔVFB (V
V)
2.0
0.04
3/6/12
4/6/12
5/6/12
6/6/12
VFB= 2.5V
0.00
-0.04
1
10
2
10
10
Time (s)
3
10
4
Thinner TO Æ Increased electron tunnel out from SiN
13
Retention – T dependence
VFB = 5.5V
ΔVFB(V)
0.0
-0.4
0.0
ΔVFB(V)
43
10
38
10
33
10
28
10
23
10
18
10
13
tr (s)
-0.8
10
VFB = 2.5V
-0.4
25oC
150oC
-0.8 1
10
2
125oC
180oC
3
10
10
Time (s)
4
10
10
8
10
3
N1:Ea = 1.88 eV
N2:Ea = 1.38 eV
N3:Ea = 1.01 eV
25
30
35
-1
1
1/kT( V )
1/kT(eV
40
Higher activation energy in N+ → Deeper electron traps
14
Retention – E state TO thickness & T effect
0.4
25oC
150oC
¾ TO independent for > 3nm
No Trap to Band tunneling
of holes
0.2
VFB = -2.0V
0.0
0
0
0.4
ΔVFB(V))
¾ T independent
No thermal emission of
holes
ΔVFBB(V)
E state retention loss
3/6/12
5/6/12
4/6/12
6/6/12
0.2
VFB = -2.0V
0.0
1
10
Different charge loss mechanisms
for electrons and holes
125oC
180oC
2
3
10
10
Ti ((s))
Time
4
10
15
Endurance – SiN Composition
5
VFB(V
V)
4
3
2
P 16V 5ms
1
N1
N2
N3
N4
E -15V 1ms
0
Memory
y Windo
ow, VFB(V
V)
5
4
N1
N2
N3
N4
3
2
N+
1
0
10
0
1
2
10
10
10
P/E Cycles
3
10
4
10
0
1
2
10
10
10
P/E Cycles
3
Si+
10
4
Endurance degradation SiN composition dependent
Si rich devices cycle with negligible erase state degradation
Si-rich
16
Summary
• Comparison of SiN Compositions
Parameter
N+
Si+
Deep
Shallow
Hole trap depth
Shallow
Deep
Hole trap density
Very low
High
Split window
operation
Not
possible
Possible
Endurance
degradation
High
Low
Electron trap depth
17
P/E Simulation of SiN Flash
• Develop
D
l a Simulation
Si l ti framework
f
k capable
bl off providing
idi
useful insight into the physics involved during Program
/Erase (P/E) operations
operations.
• Accurately
yp
predicting
g P/E behavior of SANOS/SONOS
memories
• Simulation
Si l ti up to
t long
l
time
ti
instants,
i t t large
l
biases
bi
• For different gate stack dimensions
• For different Nitride Compositions
p
18
Simulation Methodology
•Set P/E bias
•Compute Poisson throughout
gate stack
•Assume
Assume TO and CD as pure
tunnel barriers, compute
tunneling currents in and out
of SiN
•Compute transport, continuity
and SRH (trapping detrapping)
in SiN
•Compute
Co pute ttrapped
apped c
charges,
a ges,
update Poisson
•Continue till end of P/E time
19
Simulation Flow
20
Key Models Incorporated
Tsu-Esaki tunneling formulation
Field dependent
p
capture
p
cross section
Poole Frenkel detrapping from traps
T
Trap
to
t band
b d tunneling
t
li
21
P/E: Stack Energy Band Diagrams
22
SANOS sample stack properties
SiN Si2H6/N3
type flow ratio
Dep.
Temp
(°C)
Gate Stack
Dimensions
(nm)
RI
TO
SiN
CD
N2
0 005
0.005
650
2 006
2.006
4
6
15
N2
0.005
650
2.006
6
6
12
N2
0 005
0.005
650
2 006
2.006
4
6
12
N0
0.01
800
1.987
4
6
12
N0 Æ More N rich SiN; N2 Æ More Si rich SiN
Diff
Different
t stack
t k di
dimensions
i
used
d to
t check
h k robustness
b t
23
ISPP Matching
7.5
Employing the field
d
dependent
d t σ enables
bl
accurate prediction of
ISPP
6.5
5.5
V)
Δ Vfb (V
Less than 1V change in
VT (or VFB) for every 1V
increment in applied VG
(ISPP slope <1V/V)
Exp
Lower
Field dep. σ (n = 3) Vfb Shift
σ = const (n = 0)
n
σ = σ0/(1+(E/Esat) )
4.5
3.5
2.5
Lower
ISPP Slope
1.5
0.5
-0.5
5
10
15
20
Vg (V)
24
ISPP Matching
9.5
Same parameter
S
t
values used during P/E
transient matching (to
follow)
8.5
75
7.5
3
σ = σ0/(1+(E/Esat) )
6.5
V)
Δ V fb (V
Good matching with
ISPP data for varying
gate stack thickness
and nitride
compositions
Exp: N2 (4/6/15nm)
Exp: N2 (4/6/20nm)
Exp: N0 (4/6/12nm)
N2
5.5
4.5
3.5
2.5
N0
1.5
Symbol : Exp
Line : Sim
05
0.5
-0.5
4
6
8
10
12
14
16
18
20
Normalized Vgg ((V))
25
22
P/E Matching
6
5.5
4.5
Symbol: Exp
Line: Sim
5
4
Δ Vfb (V)
Δ V fb ((V )
3.5
2.5
1.5
3
2
Vg : -17V - -12V
1
Vg : 12V-16V
0 Symbol: Exp
0.5
Line: Sim
-0.5 -6
10
10
-5
10
-4
10
-3
Time (s)
10
-2
10
-1
10
0
-1 -6
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Time (s)
Program
g
and Erase transients (N2-4/6/12
(
nm SANOS))
26
P/E Matching (Change in TO)
5.5
4.5
6
Symbol: Exp
Line: Sim
5
4
V)
Δ V fb (V
Δ V fb ( V )
3.5
2.5
3
2
Vg : -18V - -13V
1.5
1
0.5
-0.5 -6
10
Vg : 12V-17V
0 Symbol: Exp
Line: Sim
10
-5
10
-4
10
-3
Time (s)
10
-2
10
-1
10
0
-1 -6
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Time (s)
Program and Erase transients (N2
(N2-6/6/12
6/6/12 nm SANOS)
27
P/E Matching (Change in CD)
6.5
7
Symbol: Exp
5.5 Line: Sim
6
5
V)
Δ Vfb (V
V)
Δ Vfb (V
4.5
35
3.5
2.5
1.5
3
Vg : -18V - -13V
2
1
Vg : 13V-18V
0.5
-0.5 -6
10
4
0
10
-5
10
-4
10
-3
Time (s)
10
-2
10
-1
10
0
Symbol: Exp
Line: Sim
-1 -6
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
Time (s)
Program and Erase transients (N2
(N2-4/6/15
4/6/15 nm SANOS)
28
0
P/E Matching (Change in SiN)
7
7.5
Symbol: Exp
6
6.5 Line: Sim
5
4.5
Vfb (V)
ΔV
b (V)
Δ Vfb
5.5
35
3.5
2.5
4
3
Vg : -17V - -13V
2
1
1.5
Vg : 12V
12V-17V
17V
N0-4/6/12nm
0.5
-0.5 -7
10
10
-6
10
-5
10
-4
10
Time ((s))
-3
10
-2
10
-1
10
0
0
Symbol:
S
b l E
Exp
Line: Sim
-1 -6
10
10
-5
10
-4
10
-3
10
-2
10
-1
10
0
Time (s)
Program
g
and Erase transients (N0-4/6/12
(
nm SANOS))
29
Extracted parameters (SiN dependence)
Parameter
N0
N2
Parameter
N0
N2
Electron trap depth
((eV))
1.8
1.63 Hole Trap Depth (eV) 1.73 1.95
Electron trap density
(1019cm-3)
3.3
3.9
Hole Trap Density
(1019cm-3)
1.6
2.6
Electron σ const. , σ-0
(10-12 cm2)
5.7
5.7
Hole σ const. , σ-0
(10-10 cm2)
8
8
Trap-band emission
f
freq.
υ-tbt(1013 s-11)
4
4
Saturation electric field
6.25 6.25
Esat (105 V/cm)
V/ )
Values of carrier effective masses
masses, band gaps and
dielectric constants taken from published literature
30
Summary
• New
N
models
d l for
f electric
l t i field
fi ld dependent
d
d t capture
t
cross section has been proposed which gives
excellent agreement with experimental results
• The robustness of the simulator is verified across
different stack thicknesses and different nitride
compositions to accurately predict the P/E and
ISPP transients
31
Metal Nanodot (m-ND) Flash: Motivation
ƒ Nanodot Cell
– discrete nanodots as
storage node
• Floating Gate Cell
– poly-Si storage gate
Control Gate
Control
C
t l Di
Dielectric
l ti
Floating Gate
Nanodots
Tunnel Dielectric
e e e e e e e
Source
Drain
Ch
Channel
l
Complete charge loss
e
e
e e e
Source
Defect in
Tunnel Oxide
Drain
Ch
Channel
l
Only
yp
part of stored
charge is lost
Charge storage in discrete nanodots increases
immunity to tunnel oxide defects
32
m-ND Flash Process Flow
SL
DL
Wafer Clean
Tunnel Oxide 40Ǻ
Metal Deposition
Anneal
--
ILD deposition
Metal
Deposition
Anneal
Control Oxide: 120Ǻ Al2O3
Post Deposition Anneal
Metallization: 1000Ǻ Pt
Si
Si
Si l Layer
Single
L
(SL)
D lL
Dual
Layer (DL)
33
Pt Nanodot formation
500oC
700oC
900oC
5Å
Initial
Deposited
Thickness
10Å
Anneal Temperature
Optimization of deposition and annealing processes results in large density
12cm-2
2),
(
(~4x10
) small size (~3nm)
(
) and large area coverage (~30%)
(
%)
34
Cross-Section TEM
CD
CD
ILD
TO
TO
Si
Discrete SL and DL nanodot formation clearly
y visible
35
SL Memory Window
8
7
VFB (V)
6
4
2
Virgin VFB
0
-18V -> -20V
-2
-5
INT
10
-4
10
-3
10
-2
10
Time (s)
-1
10
Memo
ory Windo
ow (V)
+18V -> +20V
6
SL S1
SL-S1
SL-S3
5 T = 10ms
4
3
2
1
0
17
18
Gate Voltage (V)
19
Large Memory window & significant over erase
((split
p window possibility)
p
y)
36
Memory Window: SL vs. DL
SL
DL
Improvement in
memory window
i
over SL
6
Sa
aturation
n VFB (V)
Satu
uration VFB (V))
10
8
6
4
2
0
-2
2
-4
(b)
12nm
17nm
4
2
Improvement :
A hi d 38%
Achieved:
Expected: 42%
0
-2
-4
17 18 19 20 21 22
Eq. Gate Voltage (V) (w.r.t SL)
-6
T =10ms
16 17 18
Thick CD Split
19 20 21
22
Eq. Gate Voltage (V)
• 90% improvement in DL window over SL due to
increased CD thickness and charge storage in 2nd layer
• Memory
y window improvement
p
only
y with thick CD: 38%,,
expected (40%)
37
8
DL
6
o
25 C
o
80 C
o
150 C
4
SL
2
0
DL
0
10
1
10
2
10
3
10
4
10
-2
2
Time (s)
ΔVFB (V)
9
8
7
6
5
4
3
2
1
0
VFB (V
V)
VFB (V)
High Temperature Retention
0.4
0
4
0.2
E-state
gain
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
10
P-state
loss
DL-S1
DL-S2
DL-S3
DL-S9
DL
S9
o
o
o
25 C 80 C
150 C
o
Retention Temperature ( C)
Insignificant retention loss
Retention better than SiN memory due to deeper
potential well for m-ND’s
38
SL vs. DL P/E Endurance
6
5
4
3
2
1
0
-1
6
VFB (V))
5
VFB (V)
Solid: SL-S1
Open: SL-S3
DL S1
DL-S1
DL-S2
DL-S3
DL-S9
4
3
2
1
0
0
10
1
10
2
3
10
10
# P/E Cycles
4
10
10
0
10
1
2
10
10
# P/E Cycles
3
10
4
Better endurance for DL w.r.t SL
No window closure till breakdown
39
P/E Endurance (DL-S9)
(
)
8
5
4
3
2
1
0
-1
4
6V
2
0
-2
0
10
1
10
6V
VFB(V
V)
VFB (V
V)
6
2
3
10
10
# P/E Cycles
4
10
0
10
75000
1
10
2
3
4
10 10 10
# P/E Cycles
5
10
• 10
04 cyc
cycles
es with
t 6
6V a
and
d 7V memory
e o y window,
do , 2x10
03 cyc
cycles
es
with 8V memory window
• Maximum endurance seen when P/E-states are within
+6V/-2V
40
• No window closure till breakdown
MLC Operation (DL-S9)
4
11
4
VPASS= 6V
10
2
VFB(V)
VFB(V)
3
2
o
3 T = 80 C
1
0
01
10
0
-1
-1
-2
2
1
00
-2
-2
2
10
-1
10
0
10
1
10
Disturb Time (s)
2
10
3
10
0
10
1
10
2
10
3
10
Retention Time (s)
Excellent separation maintained between the P/E levels
g
retention stress
after read disturb and high-T
41
4
Summary
• Single and dual layer Pt metal Nanodot memory
gate stacks demonstrated
• Excellent memory window, cycling endurance
(>10K with
ith 6V window),
i d ) pre- and
d post-cycling
t
li
retention
• MLC capabilities
• No fundamental reliability show stopper for metal
dots in gate stack
• Need feasibility demonstration in scaled (sub
20nm node) cells
42
Simulation of m-ND Flash
• To demonstrate viability of m-ND cells in sub 20nm cells
(impact of cell size,
size no
no. of dots,
dots area coverage
coverage,
fluctuations, missing dots, dot to dot leakage…..)
• Full 3D electrostatics and tunneling implementation
• Solve
S l Laplace
L l
for
f potential
t ti l & electric
l t i field
fi ld in
i gate
t stack
t k
• Non
Non-local
local tunneling implementation (Tsu
(Tsu-Esaki)
Esaki) for
charging of dots (substrate to dot, dot to gate, dot to dot)
• Calculate charges in iterative manner
• Port
P td
dott charges
h
in
i equivalent
i l t device
d i simulated
i l t d using
i
43
Sentaurus Device for VT calculation
Potential, E-field, Tunnel current (2D cuts)
44
Charge Transients
45
Prediction….
Area coverage, Channel length, No. density, Missing dots…
46
Summary
• Full 3D electrostatics – tunneling framework to study mND Flash viability below 20nm node
• Immunity to fluctuations (good)
• Memory window reduction with L scaling (issue)
• Cells becomes edge critical (issue)
47