Basic Model QCPU(Q Mode) User`s Manual

Transcription

Basic Model QCPU(Q Mode)
U
User's Manual (Function Explanation, Program Fundamentals)
User's Manual
(Function Explanation,
Program Fundamentals)
SQCPU(Q)-U-KI-E
MODEL
CODE
13JR44
Basic Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals)
MODEL
SH(NA)-080188-A(0108)MEE
HEAD OFFICE : 1-8-12, OFFICE TOWER Z 14F HARUMI CHUO-KU 104-6212,JAPAN
NAGOYA WORKS : 1-14 , YADA-MINAMI 5 , HIGASHI-KU, NAGOYA , JAPAN
When exported from Japan, this manual does not require application to the
Ministry of Economy, Trade and Industry for service transaction permission.
Specifications subject to change without notice.
Mitsubishi Programmable
Logic Controller
• SAFETY INSTRUCTIONS •
(Always read these instructions before using this equipment.)
When using Mitsubishi equipment, thoroughly read this manual and the associated manuals introduced in
this manual. Also pay careful attention to safety and handle the module properly.
These SAFETY PRECAUTIONS classify the safety precautions into two categories: "DANGER" and
"CAUTION".
DANGER
Indicates that incorrect handling may cause hazardous conditions,
resulting in death or severe injury.
! CAUTION
Indicates that incorrect handling may cause hazardous conditions,
resulting in medium or slight personal injury or physical damage.
!
Note that the ! CAUTION level may lead to a serious consequence according to the circumstances.
Always follow the instructions of both levels because they are important to personal safety.
Please save this manual to make it accessible when required and always forward it to the end user.
[Design Precautions]
!
DANGER
• Install a safety circuit external to the PLC that keeps the entire system safe even when there are
problems with the external power supply or the PLC module. Otherwise, trouble could result
from erroneous output or erroneous operation.
(1) Outside the PLC, construct mechanical damage preventing interlock circuits such as
emergency stop, protective circuits, positioning upper and lower limits switches and
interlocking forward/reverse operations.
(2) When the PLC detects the following problems, it will stop calculation and turn off all output in
the case of (a). In the case of (b), it will stop calculation and hold or turn off all output
according to the parameter setting.
(a) The power supply module has over current protection equipment and over voltage
protection equipment.
(b) The PLC CPUs self-diagnostic functions, such as the watchdog timer error, detect
problems.
In addition, all output will be turned on when there are problems that the PLC CPU cannot
detect, such as in the I/O controller. Build a fail safe circuit exterior to the PLC that will make
sure the equipment operates safely at such times. Refer to " LOADING AND
INSTALLATION" in Basic Model QCPU (Q Mode) User’s Manual (Hardware Design,
Maintenance and Inspection) for example fail safe circuits.
(3) Output could be left on or off when there is trouble in the outputs module relay or transistor.
So build an external monitoring circuit that will monitor any single outputs that could cause
serious trouble.
A-1
A-1
[Design Precautions]
!
DANGER
• When overcurrent which exceeds the rating or caused by short-circuited load flows in the output
module for a long time, it may cause smoke or fire. To prevent this, configure an external safety
circuit, such as fuse.
• Build a circuit that turns on the external power supply when the PLC main module power is
turned on. If the external power supply is turned on first, it could result in erroneous output or
erroneous operation.
• When there are communication problems with the data link, refer to the corresponding data link
manual for the operating status of each station.
Not doing so could result in erroneous output or erroneous operation.
• When connecting a peripheral device to the CPU module or connecting a personal computer or
the like to the intelligent function module to exercise control (data change) on the running PLC,
configure up an interlock circuit in the sequence program to ensure that the whole system will
always operate safely.
Also before exercising other control (program change, operating status change (status control))
on the running PLC, read the manual carefully and fully confirm safety.
Especially for the above control on the remote PLC from an external device, an immediate
action may not be taken for PLC trouble due to a data communication fault.
In addition to configuring up the interlock circuit in the sequence program, corrective and other
actions to be taken as a system for the occurrence of a data communication fault should be
predetermined between the external device and PLC CPU.
!
CAUTION
• Do not bunch the control wires or communication cables with the main circuit or power wires, or
install them close to each other. They should be installed 100 mm (3.94 inch) or more from each
other.
Not doing so could result in noise that would cause erroneous operation.
• When controlling items like lamp load, heater or solenoid valve using an output module, large
current (approximately ten times greater than that present in normal circumstances) may flow
when the output is turned OFF to ON.
Take measures such as replacing the module with one having sufficient rated current.
A-2
A-2
[Installation Precautions]
!
CAUTION
• Use the PLC in an environment that meets the general specifications contained in Basic Model
QCPU (Q Mode) User’s Manual (Hardware Design, Maintenance and Inspection). Using this
PLC in an environment outside the range of the general specifications could result in electric
shock, fire, erroneous operation, and damage to or deterioration of the product.
• Hold down the module loading lever at the module bottom, and securely insert the module fixing
hook into the fixing hole in the base module. Incorrect loading of the module can cause a
malfunction, failure or drop.
When using the PLC in the environment of much vibration, tighten the module with a screw.
Tighten the screw in the specified torque range.
Undertightening can cause a drop, short circuit or malfunction.
Overtightening can cause a drop, short circuit or malfunction due to damage to the screw or
module.
• When installing more cables, be sure that the base module and the module connectors are
installed correctly.
After installation, check them for looseness.
Poor connections could cause an input or output failure.
• Completely turn off the external power supply before loading or unloading the module.
Not doing so could result in electric shock or damage to the product.
• Do not directly touch the module's conductive parts or electronic components.
Touching the conductive parts could cause an operation failure or give damage to the module.
[Wiring Precautions]
!
DANGER
• Completely turn off the external power supply when installing or placing wiring.
Not completely turning off all power could result in electric shock or damage to the product.
• When turning on the power supply or operating the module after installation or wiring work, be
sure that the module's terminal covers are correctly attached.
Not attaching the terminal cover could result in electric shock.
A-3
A-3
[Wiring Precautions]
!
CAUTION
• Be sure to ground the FG terminals and LG terminals to the protective ground conductor. Not
doing so could result in electric shock or erroneous operation.
• When wiring in the PLC, be sure that it is done correctly by checking the product's rated voltage
and the terminal layout.
Connecting a power supply that is different from the rating or incorrectly wiring the product could
result in fire or damage.
• External connections shall be crimped or pressure welded with the specified tools, or correctly
soldered.
Imperfect connections could result in short circuit, fires, or erroneous operation.
• Tighten the terminal screws with the specified torque.
If the terminal screws are loose, it could result in short circuits, fire, or erroneous operation.
Tightening the terminal screws too far may cause damages to the screws and/or the module,
resulting in fallout, short circuits, or malfunction.
• Be sure there are no foreign substances such as sawdust or wiring debris inside the module.
Such debris could cause fires, damage, or erroneous operation.
• The module has an ingress prevention label on its top to prevent foreign matter, such as wire
offcuts, from entering the module during wiring.
Do not peel this label during wiring.
Before starting system operation, be sure to peel this label because of heat dissipation.
[Startup and Maintenance precautions]
!
DANGER
• Do not touch the terminals while power is on.
Doing so could cause shock or erroneous operation.
• Correctly connect the battery. Also, do not charge, disassemble, heat, place in fire, short circuit,
or solder the battery.
Mishandling of battery can cause overheating or cracks which could result in injury and fires.
• Switch all phases of the external power supply off when cleaning the module or retightening the
terminal or module mounting screws. Not doing so could result in electric shock.
Undertightening of terminal screws can cause a short circuit or malfunction.
Overtightening of screws can cause damages to the screws and/or the module, resulting in
fallout, short circuits, or malfunction.
A-4
A-4
[Startup and Maintenance precautions]
!
CAUTION
• The online operations conducted for the CPU module being operated, connecting the peripheral
device (especially, when changing data or operation status), shall be conducted after the
manual has been carefully read and a sufficient check of safety has been conducted.
Operation mistakes could cause damage or problems with of the module.
• Do not disassemble or modify the modules.
Doing so could cause trouble, erroneous operation, injury, or fire.
• Use a cellular phone or PHS more than 25cm (9.85 inch) away from the PLC.
Not doing so can cause a malfunction.
• Switch all phases of the external power supply off before mounting or removing the module.
If you do not switch off the external power supply, it will cause failure or malfunction of the
module.
• Do not drop or give an impact to the battery mounted to the module.
Doing so may damage the battery, causing the battery fluid to leak inside the battery.
If the battery is dropped or given an impact, dispose of it without using.
• Before touching the module, always touch grounded metal, etc. to discharge static electricity
from human body, etc.
Not doing so can cause the module to fail or malfunction.
[Disposal Precautions]
!
CAUTION
• When disposing of this product, treat it as industrial waste.
A-5
A-5
REVISIONS
The manual number is given on the bottom left of the back cover.
Print Date
Aug., 2001
Jan., 2003
* Manual Number
Revision
SH (NA) 080188-A Equivalent to Japanese SH-080185-B
First edition
SH (NA) 080188-B Equivalent to Japanese version "D"
Overall reexamination
Japanese Manual Version SH-080185-D
This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent
licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property
rights which may occur as a result of using the contents noted in this manual.
 2001 MITSUBISHI ELECTRIC CORPORATION
A-6
A-6
INTRODUCTION
Thank you for choosing the Mitsubishi MELSEC-Q Series of General Purpose Programmable Controllers.
Please read this manual carefully so that equipment is used to its optimum.
CONTENTS
SAFETY INSTRUCTIONS ...........................................................................................................................................A- 1
REVISIONS ....................................................................................................................................................................A- 6
CONTENTS....................................................................................................................................................................A- 7
About Manuals................................................................................................................................................................A-16
How to Use This Manual ...............................................................................................................................................A-17
About the Generic Terms and Abbreviations..............................................................................................................A-18
1 OVERVIEW
1- 1 to 1-12
1.1 Features................................................................................................................................................................... 1- 4
1.2 Program Storage and Calculation......................................................................................................................... 1- 7
1.3 Convenient Programming Devices and Instructions .......................................................................................... 1- 9
2. SYSTEM CONFIGURATION
2- 1 to 2- 9
2.1 System Configuration............................................................................................................................................. 22.1.1 Q00JCPU .......................................................................................................................................... 22.1.2 Q00CPU,Q01CPU ............................................................................................................................ 22.1.3 Configuration of GX Developer....................................................................................................................... 22.2 Precaution on System Configuration.................................................................................................................... 22.3 Confirming the function version............................................................................................................................. 2-
1
1
3
7
8
9
3 PERFORMANCE SPECIFICATION
3- 1 to 3- 3
4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS
4- 1 to 4-28
4.1 Sequence Program ................................................................................................................................................ 4- 2
4.1.1 Main routine program....................................................................................................................... 4- 4
4.1.2 Sub-routine programs ...................................................................................................................... 4- 5
4.1.3 Interrupt programs............................................................................................................................ 4- 6
4.2 Concept of Scan Time............................................................................................................................................4-10
4.3 Operation Processing.............................................................................................................................................4-11
4.3.1 Initial processing .............................................................................................................................. 4-11
4.3.2 I/O refresh (I/O module refresh processing) ................................................................................... 4-12
4.3.3 Automatic refresh of the intelligent function module....................................................................... 4-12
4.3.4 END processing ............................................................................................................................... 4-12
4.4 RUN, STOP, PAUSE Operation Processing.......................................................................................................4-13
A-7
A-7
4.5 Operation Processing during Momentary Power Failure...................................................................................4-14
4.6 Data Clear Processing ...........................................................................................................................................4-15
4.7 Input/Output Processing and Response Lag ......................................................................................................4-16
4.7.1 Refresh mode................................................................................................................................... 4-16
4.7.2 Direct mode ...................................................................................................................................... 4-19
4.8 Numeric Values which Can Be Used in Sequence Program ............................................................................4-21
4.8.1 BIN (Binary Code) ............................................................................................................................ 4-23
4.8.2 HEX (Hexadecimal) ......................................................................................................................... 4-24
4.8.3 BCD (Binary Coded Decimal).......................................................................................................... 4-25
4.8.4 Real number (floating-point data) ..................................................................................................... 4-26
4.9 Character String Data.............................................................................................................................................4-28
5 ASSIGNMENT OF I/O NUMBERS
5- 1 to 5-19
5.1 Relationship Between the Number of Stages and Slots of the Expansion Base Unit.................................... 5- 1
5.1.1 Q00JCPU ......................................................................................................................................... 5- 1
5.1.2 Q00CPU,QO1CPU .......................................................................................................................... 5- 2
5.2 Installing Extension Base Units and Setting the Number of Stages ................................................................. 5- 3
5.3 Base Unit Assignment (Base Mode) .................................................................................................................... 5- 4
5.4 What are I/O Numbers?......................................................................................................................................... 5- 8
5.5 Concept of I/O Number Assignment .................................................................................................................... 5- 9
5.5.1 I/O numbers of main base unit,slim type main base unit and extension base unit........................ 5- 9
5.5.2 Remote station I/O number ............................................................................................................. 5-11
5.6 I/O Assignment by GX Developer.........................................................................................................................5-12
5.6.1 Purpose of I/O assignment by GX Developer................................................................................. 5-12
5.6.2 Concept of I/O assignment using GX Developer ............................................................................ 5-13
5.7 Examples of I/O Number Assignment..................................................................................................................5-16
5.8 Checking the I/O Numbers ....................................................................................................................................5-19
6 ABOUT MEMORY AND FILES HANDLED BY BASIC MODEL QCPU
6- 1 to 6-14
6.1 About Basic model QCPU's Memory................................................................................................................... 6- 2
6.2 About Program Memory......................................................................................................................................... 6- 4
6.3 About Standard ROM............................................................................................................................................. 6- 5
6.4 Executing Standard ROM Program (Boot Run) and Writing Program Memory to ROM............................... 6- 6
6.4.1 Executing Standard ROM Program................................................................................................. 6- 6
6.4.2 Write program memory to ROM ...................................................................................................... 6- 8
6.5 About Standard RAM ............................................................................................................................................. 6- 9
6.6 Program File Configuration....................................................................................................................................6-10
6.7 GX Developer File Operation and File Handling Precautions ...........................................................................6-11
6.7.1 File operation.................................................................................................................................... 6-11
6.7.2 File handling precautions................................................................................................................. 6-12
6.7.3 File capacity ..................................................................................................................................... 6-13
A-8
A-8
7 FUNCTION
7- 1 to 7-56
7.1 Function List ............................................................................................................................................................ 7- 1
7.2 Constant Scan......................................................................................................................................................... 7- 2
7.3 Latch Functions....................................................................................................................................................... 7- 5
7.4 Setting the Output (Y) Status when Changing from STOP Status to RUN Status ......................................... 7- 7
7.5 Clock Function ........................................................................................................................................................ 7- 9
7.6 Remote Operation ..................................................................................................................................................7-12
7.6.1 Remote RUN/STOP......................................................................................................................... 7-12
7.6.2 Remote PAUSE ............................................................................................................................... 7-15
7.6.3 Remote RESET................................................................................................................................ 7-17
7.6.4 Remote Latch Clear ......................................................................................................................... 7-19
7.6.5 Relationship of the remote operation and Basic model QCPU RUN/STOP switch ...................... 7-20
7.7 Selection of Module Input Response Time (I/O Response Time) ....................................................................7-21
7.7.1 Selection of input response time of the input module/composite I/O module................................ 7-21
7.7.2 Selection of input response time of the high-speed input module ................................................. 7-22
7.7.3 Selection of input response time of the interrupt module ............................................................... 7-23
7.8 Error-time Output Mode .........................................................................................................................................7-24
7.9 Hardware Error-time CPU Operation Mode Setting ...........................................................................................7-25
7.10 Setting the Switches of the Intelligent-Function Module ..................................................................................7-26
7.11 Program Write during RUN of Basic Model QCPU ..........................................................................................7-27
7.11.1 Writing Data in the Ladder Mode during the RUN Status ............................................................ 7-27
7.12 Multiple-User Debugging Function .....................................................................................................................7-29
7.12.1 Multiple-user monitoring function .................................................................................................. 7-30
7.12.2 Multiple-user simultaneous write during RUN............................................................................... 7-31
7.13 Watchdog Timer (WDT).......................................................................................................................................7-33
7.14 Self-Diagnosis Function.......................................................................................................................................7-35
7.14.1 LED display when error occurs ..................................................................................................... 7-38
7.14.2 Cancel error.................................................................................................................................... 7-38
7.15 Failure History.......................................................................................................................................................7-39
7.16 System Protect......................................................................................................................................................7-40
7.16.1 Password registration .................................................................................................................... 7-40
7.16.2 Remote password .......................................................................................................................... 7-42
7.17 GX Developer system monitor............................................................................................................................7-45
7.18 LED Display ..........................................................................................................................................................7-47
7.19 Serial Communication Function (Usable with the Q00CPU or Q01CPU) .....................................................7-49
8 COMMUNICATION WITH INTELLIGENT FUNCTION MODULE
8- 1 to 8- 7
8.1 Communication Between Basic model QCPU and Q-series Intelligent Function Modules........................... 88.1.1 Initial setting and automatic refresh setting using GX Configurator ............................................... 88.1.2 Communication using device initial values ..................................................................................... 88.1.3 Communication using FROM/TO instructions ................................................................................ 88.1.4 Communication Using The Intelligent Function Module Device..................................................... 88.1.5 Communication Using The Instructions Dedicated for Intelligent Function Modules .................... 88.2 Request of Intelligent Function Module to Basic Model QCPU......................................................................... 88.2.1 Interrupt from intelligent function module ........................................................................................ 8A-9
A-9
1
2
4
4
5
6
7
7
9. PARAMETER LIST
10 DEVICES
9- 1 to 9-12
10- 1 to 10-55
10.1 Device List...........................................................................................................................................................10- 1
10.2 Internal User Devices.........................................................................................................................................10- 3
10.2.1 Inputs (X) ...................................................................................................................................... 10- 5
10.2.2 Outputs (Y) ................................................................................................................................... 10- 8
10.2.3 Internal relays (M) ........................................................................................................................ 10-10
10.2.4 Latch relays (L) ............................................................................................................................ 10-11
10.2.5 Anunciators (F)............................................................................................................................. 10-12
10.2.6 Edge relay (V) .............................................................................................................................. 10-16
10.2.7 Link relays (B) .............................................................................................................................. 10-17
10.2.8 Special link relays (SB) ................................................................................................................ 10-18
10.2.9 Step relays (S) ............................................................................................................................. 10-18
10.2.10 Timers (T)................................................................................................................................... 10-19
10.2.11 Counters (C)............................................................................................................................... 10-24
10.2.12 Data registers (D)....................................................................................................................... 10-28
10.2.13 Link registers (W)....................................................................................................................... 10-29
10.2.14 Special link registers (SW) ........................................................................................................ 10-30
10.3 Internal System Devices....................................................................................................................................10-31
10.3.1 Function devices (FX, FY, FD) .................................................................................................... 10-31
10.3.2 Special relays (SM)...................................................................................................................... 10-33
10.3.3 Special registers (SD) .................................................................................................................. 10-34
10.4 Link Direct Devices (J \ ) ..............................................................................................................................10-35
10.5 Intelligent Function Module Devices (U \G ) ..............................................................................................10-38
10.6 Index Registers (Z).............................................................................................................................................10-39
10.6.1 Switching between main routine/sub-routine program and interrupt program........................... 10-40
10.7 File Registers (R)................................................................................................................................................10-43
10.8 Nesting (N) ..........................................................................................................................................................10-45
10.9 Pointers................................................................................................................................................................10-46
10.10 Interrupt Pointers (I)..........................................................................................................................................10-47
10.11 Other Devices ...................................................................................................................................................10-49
10.11.1 SFC block device (BL) ............................................................................................................... 10-49
10.11.2 Network No. designation device (J) .......................................................................................... 10-49
10.11.3 I/O No. designation device (U) .................................................................................................. 10-49
10.11.4 Macro instruction argument device (VD)................................................................................... 10-50
10.12 Constants ..........................................................................................................................................................10-51
10.12.1 Decimal constants (K)................................................................................................................ 10-51
10.12.2 Hexadecimal constants (H) ....................................................................................................... 10-51
10.12.3 Real number (E)......................................................................................................................... 10-51
10.12.4 Character string ( " " ) ................................................................................................................ 10-52
10.13 Useful Method of Using the Devices..............................................................................................................10-53
10.13.1 Device initial value ..................................................................................................................... 10-53
A - 10
A - 10
11 PROCESSING TIMES OF THE BASIC MODEL QCPU
11- 1 to 11- 5
11.1 Scan Time Structure ..........................................................................................................................................11- 1
11.2 Concept of Scan Time .......................................................................................................................................11- 2
11.3 Other Processing Times ....................................................................................................................................11- 5
12 PROCEDURE FOR WRITING PROGRAMS TO BASIC MODEL QCPU
12- 1 to 12- 3
12.1 Items to Consider when Creating Program .....................................................................................................12- 1
12.2 Procedure for writing program to the Basic model QCPU.............................................................................12- 2
13 OUTLINE OF MULTIPLE CPU SYSTEMS
13- 1 to 13- 6
13.1 Features...............................................................................................................................................................13- 1
13.2 Outline of Multiple CPU Systems .....................................................................................................................13- 3
13.3 Differences with Single CPU Systems.............................................................................................................13- 5
14 SYSTEM CONFIGURATION OF MULTIPLE CPU SYSTEM
14- 1 to 14- 18
14.1 System Configuration.........................................................................................................................................14- 1
14.2 Precautions For Multiple CPU System Configuration .....................................................................................14- 6
14.2.1 Function versions of Basic model QCPU, Motion CPU and PC CPU module that can be used, and
their mounting positions................................................................................................................ 14- 6
14.2.2 Precautions when using Q Series I/O modules and intelligent function modules ...................... 14- 9
14.2.3 Modules that have mounting restrictions ..................................................................................... 14-10
14.2.4 Compatible GX Developers and GX Configurators ..................................................................... 14-10
14.2.5 Parameters that enable the use of Multiple CPU System ........................................................... 14-11
14.2.6 Resetting the Multiple CPU System ............................................................................................. 14-15
14.2.7 Processing when stop errors occur .............................................................................................. 14-16
14.2.8 Reducing the time required for Multiple CPU System processing .............................................. 14-18
15 ALLOCATING MULTIPLE CPU SYSTEM I/O NUMBERS
15- 1 to 15- 4
15.1 Concept behind Allocating I/O Numbers .........................................................................................................1515.1.1 I/O modules and Intelligent function module I/O numbers ......................................................... 1515.1.2 I /O number of Basic model QCPU, Motion CPU and PC CPU module..................................... 1515.2 Setting of Control CPUs with GX Developer ...................................................................................................1516 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU SYSTEM
1
1
3
4
16- 1 to 16- 16
16.1 Automatic Refresh of CPU Shared Memory ...................................................................................................16- 2
16.2 Communication with Multiple CPU Instructions and Intelligent Function Module Devices ...................16- 9
16.3 Interactive Communications between The Basic model QCPU and Motion CPU .....................................16-12
16.3.1 Control commands from the Basic model QCPU to the Motion CPU (Motion dedicated instructions)
....................................................................................................................................................... 16-12
16.3.2 Reading and writing device data(Between Multiple CPU communication dedicated instructions)
....................................................................................................................................................... 16-13
16.4 CPU Shared Memory.........................................................................................................................................16-14
A - 11
A - 11
17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O MODULES AND INTELLIGENT
FUNCTION MODULES
17- 1 to 17- 5
17.1 Range of Control CPU Communications.........................................................................................................17- 1
17.2 Range of Non-control CPU Communications .................................................................................................17- 1
18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL QCPUs
18- 1 to 18- 3
18.1 Concept behind Scan Time...............................................................................................................................18- 1
18.2 Factor to Prolong the Scan Time......................................................................................................................18- 2
19 STARTING UP THE MULTIPLE CPU SYSTEM
19- 1 to 19- 9
19.1 Flow-chart for Starting Up the Multiple CPU System .....................................................................................1919.2 Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU Settings) .........1919.2.1 System configuration ................................................................................................................... 1919.2.2 Creating new systems ................................................................................................................. 1919.2.3 Using existing preset Multiple CPU settings and I/O allocations ............................................... 19APPENDICES
1
3
3
4
7
App - 1 to App - 20
APPENDIX 1 Special Relay List............................................................................................................................. App - 1
APPENDIX 2 Special Register List ........................................................................................................................ App - 5
APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors ...................................................................... App -18
APPENDIX 4 Enhancement of the Basic Model QCPU Functions .................................................................. App –19
APPENDIX 4.1 Specification Comparison........................................................................................................... App –19
APPENDIX 4.2 Added Functions.......................................................................................................................... App –19
INDEX
A - 12
Index- 1 to Index- 2
A - 12
(Related manual)........................... QCPU (Q Mode) User's Manual (Hardware Design,Maintenance and Inspection)
CONTENTS
1 OVERVIEW
1.1 Features
2 SYSTEM CONFIGURATION
2.1 System Configuration of Single CPU System
2.1.1 Q00JCPU
2.1.2 Q00CPU, Q01CPU
2.1.3 Configuration for Use of GX Developer
2.2 Precautions for Use of Single CPU System
2.3 System Configuration of Multiple CPU System
2.3.1 Q00CPU or Q01CPU
2.3.2 Configuration for Use of GX Developer
2.4 Precautions for Use of Multiple CPU System
2.5 Confirming the Function Version.
3 GENERAL SPECIFICATIONS
4 HARDWARE SPECIFICATION OF THE CPU MODULE
4.1 Performance Specification
4.2 Part Names
4.2.1 Q00JCPU
4.3 Switch Operation After Program Write
4.4 Reset Operation
4.5 Latch Clear Operation
5 POWER SUPPLY MODULE
5.1 Specification
5.1.1 Power supply module specifications
5.1.2 Selecting the power supply module
5.1.3 Precaution when connecting the uninterruptive power supply
A - 13
A - 13
5.2 Part Names and Settings
6 BASE UNIT AND EXTENSION CABLE
6.1 Base Unit Specification Table
6.2 Extension Cable Specification Table
6.3 Parts Names of Base Unit
6.4 Setting the Extension Base Unit
6.5 Guideline for Use of Extension Base Units (Q5!B)
7 BATTERY
7.1 Battery Specifications
7.2 Installation of Battery
8 EMC AND LOW-VOLTAGE DIRECTIVES
8.1 Requirements for conformance to the EMC Directive
8.1.1 Standards applicable to the EMC Directive
8.1.2 Installation instructions for the EMC Directive
8.1.3 Cables
8.1.4 Power supply module, Q00JCPU power supply section
8.1.5 Others
8.2 Requirement to Conform to the Low-Voltage Directive
8.2.1 Standard applied for MELSEC-Q series PLC
8.2.2 MELSEC-Q series PLC selection
8.2.3 Power supply
8.2.4 Control box
8.2.5 Grounding
8.2.6 External wiring
9 LOADING AND INSTALLATION
9.1 General Safety Requirements
9.2 Calculating Heat Generation by PLC
9.3 Module Installation
9.3.1 Precaution on installation
9.3.2 Instructions for mounting the base unit
9.3.3 Installation and removal of the module
9.4 Setting the Stage Number of the Extension Base Unit
9.5 Connection and Disconnection of the Extension Cable
9.6 Wiring
9.6.1 The precautions on the wiring
9.6.2 Connecting to the power supply module
10 MAINTENANCE AND INSPECTION
10.1 Daily Inspection
10.2 Periodic Inspection
10.3 Battery Replacement
A - 14
A - 14
10.3.1 Battery service life
10.3.2 Battery replacement procedure
10.4 When Resuming Operation after Storage of PLC without Battery
10.5 When Resuming PLC Operation after Storage of PLC with Battery Gone Flat
11 TROUBLESHOOTING
11.1 Troubleshooting Basics
11.2 Troubleshooting
11.2.1 Troubleshooting flowchart
11.2.2 Flowchart for when the "POWER" LED is turned off
11.2.3 Flowchart for when the "RUN" LED is turned off
11.2.4 When the "RUN" LED is flashing
11.2.5 Flowchart for when the "ERR." LED is on/flashing
11.2.6 Flowchart for when output module LED is not turned on
11.2.7 Flowchart for when output load of output module does not turn on
11.2.8 Flowchart for when unable to read a program
11.2.9 Flowchart for when unable to write a program
11.2.10 Flowchart for when program is rewritten
11.2.11 Flowchart for when UNIT VERIFY ERR. occurs
11.2.12 Flowchart for when CONTROL BUS ERR. occurs
11.3 Error Code List
11.3.1 Procedure for reading error codes
11.3.2 Error code list
11.4 Canceling of Errors
11.5 Input/Output Module Troubleshooting
11.5.1 Input circuit troubleshooting
11.5.2 Output circuit troubleshooting
11.6 Special Relay List
11.7 Special Register List
APPENDICES
APPENDIX 1 Error Code Return to Origin During General Data Processing
APPENDIX 1.1 Error code overall explanation
APPENDIX 1.2 Description of the errors of the error codes (4000H to 4FFFH)
APPENDIX 2 External Dimensions
APPENDIX 2.1 CPU module
APPENDIX 2.2 Power supply module
APPENDIX 2.3 Main base unit
APPENDIX 2.4 Slim type main base unit
APPENDIX 2.5 Extension base unit
APPENDIX 3 Functions Improvement of Basic Model QCPU
APPENDIX 3.1 Specification comparison
APPENDIX 3.2 Additional functions
APPENDIX 3.3 Usability of additional functions by GX Developer version
INDEX
A - 15
A - 15
About Manuals
The following manuals are also related to this product.
In necessary, order them by quoting the details in the tables below.
Related Manuals
Manual Number
(Model Code)
Manual Name
Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and
Inspection)
This manual provides the specifications of the CPU modules, power supply modules, base units,
extension cables and others.
SH-080187
(13JL97)
(Sold separately)
QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)
Describes how to use the sequence instructions, basic instructions, advanced instructions, and microcomputer programs.
(Sold separately)
QCPU (Q Mode)/QnACPU Programming Manual (PID Control Instructions)
This manual describes the dedicated instructions used to exercise PID control.
SH-080039
(13JF58)
(Sold separately)
SH-080040
(13JF59)
QCPU (Q Mode)/QnACPU Programming Manual (SFC)
This manual explains the system configuration, performance specifications, functions, programming,
debugging, error codes and others of MELSAP3.
SH-080041
(13JF60)
(Sold separately)
QCPU (Q Mode)/QnACPU Programming Manual (MELSAP-L)
This manual describes the programming methods, specifications functions, and so on that are necessary
to create the MELSAP-L type SFC program.
SH-080076
(13JF61)
(Sold separately)
Q Corresponding MELSEC Communication Protocol Reference Manual
This manual explains the communication methods and control procedures through the MC protocol for
the external devices to read and write data from/to the PLC CPU using the serial communication
module/Ethernet module.
(Sold separately)
QCPU (Q mode) Programming Manual (Structured Text)
Explains the programming methods in structured text language.
A - 16
SH-080008
(13JF89)
(Sold separately)
SH-080366E
(13JF68)
A - 16
How to Use This Manual
This manual is prepared for users to understand memory map, functions, programs
and devices of the CPU module when you use Basic model QCPU (Q00J/Q00/
Q01CPU).
The manual is classified roughly into three sections as shown below.
(1) Chapters 1 and 2
Describe the outline of the CPU module and the system
configuration. The feature of CPU module and the basics
of the system configuration of CPU are described.
(2) Chapters 3 to 6
Describe the performance specifications, executable
program, I/O No. and memory of the CPU module.
(3) Chapter 7
Describes the functions of the CPU modules.
(4) Chapter 8
Describes communication with intelligent function modules.
(5) Chapters 9 and 10
Describe parameter and devices used in the CPU
modules.
(6) Chapter 11
Describes the CPU module processing time.
(7) Chapter 12
Describes the procedure for writing parameter and
program created at the GX Developer to the CPU module.
(8) Chapters 13 to 19
Describes the overview of a Multiple CPU System, system
configuration, I/O numbers, communication between CPU
modules, and communication with I/O modules/intelligent
function modules.
REMARK
This manual does not explain the functions of power supply modules, base units,
extension cables and batteries.
For these functions, refer to the manual shown below.
• Basic Model QCPU (Q Mode) User's Manual (Hardware Design, Maintenance and
Inspection)
A - 17
A - 17
About the Generic Terms and Abbreviations
The following abbreviations and general names for Basic model QCPU are used in the manual.
Generic Term/Abbreviation
Basic model QCPU
Q Series
GX Developer
Q3
B
Q3
SB
Q5
B
Q6
B
Main base unit
Slim type main base unit
Extension base unit
Base unit
Extension cable
Power supply module
Slim type power supply module
Battery
CPU slot
Control CPU
Non-control CPU
Non-controlled module
(Non-group module)
Controlled module
CPU No.
Single CPU System
PC CPU module
Multiple CPU System
Description
General name for Q00JCPU, Q00CPU and Q01CPU modules.
Abbreviation for Mitsubishi general-purpose PLC MELSEC-Q series.
Product name for Q series compatible SW D5C-GPPW(-V) type GPP function
software package.
indicates Version "7" or later. When using the functions of the function version B,
use Version "8".
General name for Q33B, Q35B, Q38B and Q312B type main base units that accept
Q00CPU/Q01CPU, Q series power supply module, input/output module and
intelligent function module.
General name for Q32SB, Q33SB and Q35SB type slim type main base units that
accept Q00CPU, Q01CPU, slim type power supply module, I/O modules and
intelligent function modules.
General name for Q52B and Q55B type extension base unit with Q Series
input/output module, intelligent function module attachable.
General name for Q63B, Q65B, Q68B and Q612B type extension base unit with Q
Series power module, input/output module, intelligent function module attachable.
General name for Q33B, Q35B, Q38B, and Q312B type main base unit Q00JCPU
(base unit) with Q Series power module, input/output module, intelligent function
module attachable. 1
General name for Q32SB, Q33SB and Q35SB type slim type main base units that
accept Q00CPU, Q01CPU, slim type power supply module, I/O modules and
General name for Q5 B and Q6 B.
General name for main base units, slim type main base unit and extension base
units.
General name for QC05B, QC06B, QC12B, QC30B, QC50B, QC100B type extension
cable.
General name for Q61P-A1, Q61P-A2, Q63P, Q64P type power supply module,
Q00JCPU (power supply section).
General name for Q61SP slim type power supply module.
General name for Q6BAT type CPU module battery.
Slot on right-hand side of power supply module on main base unit.
Basic model QCPU, motion CPU or PC CPU module that controls I/O module or
intelligent function module mounted on main base unit or extension base unit. For
example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, CPU
No. 2 is the control CPU of the module on Slot 3.
Basic model QCPU, motion CPU or PC CPU module other than control CPU. For
example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, CPU
No. 1 and CPU No. 3 are the non-control CPUs of the module on Slot 3.
I/O module or intelligent function module other than controlled modules. For example,
when the module mounted on Slot 3 is to be controlled by CPU No. 2, the module on
Slot 3 is the non-controlled module of CPU No. 1 and CPU No. 3.
I/O module or intelligent function module to be controlled by control CPU. For
example, when the module mounted on Slot 3 is to be controlled by CPU No. 2, the
module on Slot 3 is the controlled module of CPU No. 2.
Number assigned to differentiate between Basic model QCPU, Motion CPU and PC
CPU module mounted in a Multiple CPU System. The CPU on the CPU slot is No. 1,
the one on Slot 0 is No. 2, and the one on Slot 1 is No. 3.
System in which Basic model QCPU is mounted on CPU slot for control.
MELSEC-Q series compatible PC CPU module of Contec makes.
System in which up to of three Basic model QCPU/Motion CPU/PC CPU modules are
mounted on main base unit for control.
1: In a Multiple CPU System configuration, the Motion CPU and PC CPU module can also be mounted.
A - 18
A - 18
1 OVERVIEW
MELSEC-Q
1 OVERVIEW
This manual describes the functions, programs and devices of the Basic model QCPU.
Refer to the following functions for details on power supply modules, base units,
extension cables, battery specifications and other information.
• Basic Model QCPU (Q mode) User's Manual (Hardware Design, Maintenance and
Inspections)
(1) Q00JCPU
• The Q00JCPU is a CPU module consisting of a CPU module, a power supply
module and a main base unit (five slots).
• This CPU allows connection of up to two extension base units to accept up to
16 input/output and intelligent function modules.
• The number of input/output points controllable by the main and extension base
units is 256.
When a CC-Link/LT module is used, 1024 points can be controlled by a single
module.
(2) Q00CPU, Q01CPU
• The Q00CPU and Q01CPU are stand-alone CPU modules loaded on a main
base unit or slim type main base unit.
• Either of these CPUs allows connection of up to four extension base units to
accept up to 24 input/output and intelligent function modules.
However, an extension base unit cannot be connected to the slim type main
base unit.
• The number of input/output points controllable by the main and extension base
units is 1024.
When a CC-Link/LT module is used, 1024 points can be controlled by a single
module.
• The Basic model QCPU can be used with the Motion CPU and PC CPU module
to configure a Multiple CPU System.
For detailed explanation of the multiple PLC system, refer to Chapter 13 to
Chapter 19.
1-1
1-1
1
1 OVERVIEW
MELSEC-Q
The Basic model QCPU is updated to add functions.
The added functions can be judged by the function version/serial No. of the CPU
module.
Table 1.1 indicates the added functions and the GX Developer version compatible with
the additional functions.
When using any of the added functions, confirm the function version/serial No. and GX
Developer version.
1
Table 1.1 List of Functions Added to Basic Model QCPU and Function Version/Serial No.
Compatible
Updates of Basic Model QCPU
Function version
Serial No.
B
04122 or later
GX Developer
Additional functions
• Multiple PLC system (Q00CPU, Q01CPU)
Version 8 or later
• SFC
• Function block
• Structured text (ST)
• Real number operation function
• PID operation function
1
• Remote password setting
• Increased standard RAM capacity (Q00CPU,
Q01CPU)
1
• Device initial value automatic setting
• Interrupt function from intelligent function
module
• Write during RUN function using pointer
*1 Functions irrelevant to GX Developer
POINT
Refer to Section 2.3 for the confirmation of the function version and serial No. of the
Basic model QCPU.
1-2
1-2
1 OVERVIEW
MELSEC-Q
The following table indicates the differences between the Basic model QCPUs.
Item
CPU module
Main base unit/slim type main base unit
Extension base unit
Number of extension stages
Number of input/output modules to be
installed
Power supply module
Main base unit
Extension Q52B, Q55B
base unit Q63B, Q65B, Q68B, Q612B
Extension cable
Memory card interface
RS-232
External interface
USB
Processing speed
LD X0
(Sequence instruction)
MOV D0 D1
Program capacity 1
Program memory
Memory
Standard RAM
capacity
Standard ROM
CPU shared memory 3
Number of times for write to standard
ROM
Device memory capacity
Number of input/output devices points
(Remote I/O is contained.)
Number of input/output points
File register
Serial communication function
1-3
Q00JCPU
CPU module, Power supply
module, Main base unit
(5 slots) Integrated type
Unnecessary
Q00CPU
Q01CPU
Stand-alone CPU module
Necessary (Q33B, Q35B, Q38B, Q312B)
Connectable
However, an extension base unit cannot be connected when the slim type
main base unit is used.
Up to 2 stages
Up to 4 stages
24 modules
16 modules
(Cannot be connected when the slim type main
base unit is used)
Unnecessary
Unnecessary
Necessary
Necessary
Unnecessary
Necessary
QC05B, QC06B, QC12B, QC30B, QC50B, QC100B
No
Yes (transmission rate: 9.6kbps, 19.2kbps, 38.4kbps, 57.6kbps, 115.2 kbps)
No
0.20µs
0.16µs
0.10µs
0.70µs
0.56µs
0.35µs
8k steps (32 kbyte)
8k steps (32 kbyte)
14k steps (56 kbyte)
58 kbyte
94 kbyte
——
128 kbyte 2
58 kbyte
94 kbyte
None
1k bytes (user free area 320 words)
Maximum 100,000 times
The number of device points can be changed within the range of 16.4k words.
2048 points
256 points
No
No
1024 points
Yes (64k points fixed)
Yes
(using the RS-232 interface of the CPU module)
1: 1 step of the program capacity is 4 Bytes.
2: 64k bytes for the function version A.
3: Memory added to the function version B.
The CPU shared memory is not latched.
The CPU shared memory is cleared
when the PLC is powered on or the CPU
module is reset.
1-3
1 OVERVIEW
MELSEC-Q
1.1 Features
(1) Many controllable input/output points
As the number of input/output points accessible to the input/output modules
loaded on the base units, the following numbers of input/output points are
supported.
• Q00JCPU: 256 points (X/Y0 to FF)
• Q00CPU, Q01CPU: 1024 points (X/Y0 to 3FF)
(2) Lineup according to program capacity
The optimum CPU module for the program capacity to be used can be selected.
• Q00JCPU, Q00CPU : 8k steps
• Q01CPU
: 14k steps
(3) Fast processing
The LD instruction processing speeds are as follows.
• Q00JCPU
: 0.20µs
• Q00CPU
: 0.16µs
• Q01CPU
: 0.10µs
The high-speed system bus of the MELSEC-Q series base unit can speed up
access to an intelligent function module and link refresh with a network module.
MELSECNET/H link refresh processing : 2.2ms/2k words 1
*1 This speed only applies when the SB/SW is not used with the Q01CPU and
the MELSECNET/H network module is used as the main base unit.
(4) Increase in debugging efficiency through high-speed
communication with GX Developer
The RS-232 interface of the Basic model QCPU enables program write/read or
monitor at a maximum of 115.2kbps.
(5) Saved space by a reduction in size
The installation area of the Basic model QCPU is about 60% of that of the AnS
series.
Comparison of installation space
1SX10
1SY50
1SX41
1SY41
1SX81
1SY81
1SX42
1SY42
98mm
(3.86
inch)
5 Slot Main Base Unit 245mm(9.65inch)
(depth:98mm(3.86inch))
1-4
1-4
1 OVERVIEW
MELSEC-Q
(6) Connection of up to four/two extension base units
(a) The Q00JCPU can connect up to two extension base units (three base units
including the main) and accepts up to 16 modules.
(b) The Q00/Q01CPU can connect up to four extension base units (five base
units including the main) and accepts up to 24 modules.
(c) The overall distance of the extension cables is up to 13.2m to ensure high
degree of extension base unit arrangement.
POINT
(1) When connected with a bus, the GOT uses one of the above extension base
units. Therefore, the number of available extension base units decreases by
one.
(2) When the slim type main base unit (Q3 SB) is used, an extension base unit
cannot be connected.
(7) Serial communication function for communication with personal
computer or display device
With the RS-232 interface of the Q00CPU or Q01CPU connected with a personal
computer, display device or the like, the MELSEC communication protocol
(hereafter refered to as the MC protocol) can be used to make communication.
RS-232 cable
Personal computer,
display device
Communication in
MC protocol
The serial communication function only allows communication in the MC protocol
(QnA-compatible 3C frame (format 4), QnA-compatible 4C frame (format 4, 5)).
The serial communication function does not allow communication in the
nonprocedure protocol or bidirectional protocol.
Refer to the following manual for the MC protocol.
• Q Corresponding MELSEC Communication Protocol Reference Manual
(8) Built-in standard ROM
The flash ROM for storing parameters and sequential program is installed as a
standard feature for easier protection of important program.
(9) Blocking an invalid access using the file password
The file password can be used to set the access level (read disable, write
disable) of a program to prevent program changes due to illegal access.
1-5
1-5
1 OVERVIEW
MELSEC-Q
(10) 64k points of file registers available (Q00CPU, Q01CPU)
The standard RAM capacity has been increased from 64k bytes to 128k bytes to
double the file register capacity (64k points).
The increase of battery-backed data provides sufficient space for control
programs.
(11) Remote password setting
When external access is made to an Ethernet module, serial communication
module or modem interface module, whether access to the Basic model QCPU
may be made or not can be selected using a remote password.
(12) Multiple CPU System compatibility
A Multiple CPU System can be configured by the Basic model QCPU (Q00CPU,
Q01CPU only), Motion CPU and PC CPU module.
REMARK
• The features in (10) to (12) are functions added to the Basic model CPU of
function version B.
• The remote password function can be executed when the Ethernet module or
serial communication module of function version B is used with GX Developer 8
or later.
1-6
1-6
1 OVERVIEW
MELSEC-Q
1.2 Program Storage and Calculation
(1) Program storage
Program created at GX Developer can be stored in Basic model QCPU's
program memory or standard ROM.
Q00JCPU
Q00CPU,Q01CPU
Program memory
Parameters
3
Program memory
Parameters
Program
Program
Comment
Comment
Standard ROM
Parameters
1
3
3
Standard ROM
Parameters
Program
Program
Comment
Comment
1
3
Standard RAM
2
File registers
1: The standard ROM is used when parameters, program and comment
are written to ROM.
2: The standard RAM is used for file registers.
3: Including the intelligent parameters of the intelligent function module
set on GX Configurator.
(2) Program execution
The Basic model QCPU processes program which are stored in the program
memory.
Q00J/Q00/Q01CPU
Program memory
Parameters
Execution of program
in program memory
Program
Comment
For displaying comment of
program made by GX Developer
1-7
1-7
1 OVERVIEW
MELSEC-Q
(3) Boot operation of program
The program stored on the standard ROM is booted (read) to the program
memory of the Basic model QCPU and executed.
Booting a program from the standard ROM to the program memory requires boot
file setting in the PLC parameter.
Basic model QCPU
Program memory
Execution of program booted
from the standard ROM to
the program memory.
Parameter
Program
Comment
Boot
Standard ROM
Parameter
Program
Comment
1-8
1-8
1 OVERVIEW
MELSEC-Q
1.3 Convenient Programming Devices and Instructions
The Q00J/Q00/01CPU features devices and instructions which facilitate program
creation. A few of these are described below.
(1) Flexible device designation
(a)
Word device bits can be designated to serve as contacts or coils.
[For the case of AnS]
[For the case of Basic model QCPU]
Bit designation of
word device
X0 D0.5
D0.A
The 1/0 status
of b5 of D0 is used
as ON/OFF data.
X0
MOV
D0
K4M0
M5
Switches b10
of D0 ON and
OFF (1/0).
M10
MOV K4M0
D0
: D0.5
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0
1/0
1/0
(b)
Bit designation
Word device designation
Direct processing in 1-point units is possible within a program simply by
using direct access inputs (DX ) and direct access outputs (DY ).
Direct access input
M0 DX10
M9036
SET M9052
DY100
(Always ON)
M9036
Output to output
module at
instruction execution
Read from input
module at
instruction
execution
M0
SEG K1X10 K1B0
(X10 to X13 refresh)
X10
Y100
M9036
SEG K1Y100 K1B0
(Y100 to Y103 refresh)
(c)
Differential contacts (
pulses.
/
Differential contact
X0
X1
Y100
) eliminate the need for converting inputs to
X0
PLS
M0
Y100
M0
X1
Y100
ON at leading
edge of X0
1-9
Y100
1-9
1 OVERVIEW
MELSEC-Q
(d)
The buffer memory of intelligent function module (e.g. Q64AD, Q62DA) can
be used in the same way as devices when programming.
X0
X0
+P
U4\G12
D0
FROMP
H4
Power supply module
Q00CPU
Input (16 points)
Input (16 points)
Input (16 points)
Q64AD (16 points)
Q64AD (16 points)
Q62AD (16 points)
Output (16 points)
Output (16 points)
Readout of Q64AD
buffer memory's
address 12 data
K12
D10
K1
+P
D10
D0
:U4\G12
Buffer memory address
designation
Intelligent function
module designation
Input/output Nos.:X/Y40 to X/Y4f
(e)
Direct access to link devices (LX, LY, LB, LW, LSB, LSW) of
MELSECNET/H network modules (e.g. QJ71LP21-25) is possible without
refresh settings.
X0
+P
J5\W12
D0
Power supply module
Q00CPU
QJ71LP21-25
Input (16 points)
Input (16 points)
Q68AD (16 points)
Q68AD (16 points)
Q62AD (16 points)
Output (16 points)
Output (16 points)
Direct readout of the No.5 network module's
"LW12" link register
:J5\W12
Link register designation
Network No. designation
Network No.5
1 - 10
1 - 10
1 OVERVIEW
MELSEC-Q
(2) Edge relays simplify pulse conversion processing
(a)
The use of a relay (V) that comes ON at the leading edge of the input
condition simplifies pulse processing when a contact index qualification has
been made.
[Circuit example]
M1000
RST
Z1
FOR
K1000
Reset index register (Z1)
Repetition (1000 times) designation
X0Z1 V0Z1
M0Z1
Pulsing M0 to M999
M1000
INC
Z1
NEXT
Increment Index Register (Z1) (+1)
Return to FOR instruction
[Timing chart]
ON
X0 OFF
ON
When Z1=0
V0 OFF
ON
M0 OFF
1 Scan
ON
X1 OFF
ON
When Z1=1
V1 OFF
ON
M1 OFF
1 Scan
(3) Structured program
The index registers and edge relay make it easy to structure the program that
includes pulse processing.
[Ans]
[Basic model QCPU]
X0
FOR
X1
M0
n
X10 X11
X0Z0 X1Z0 V0Z1
Y8Z2
Y8
PLS M10
M10
n pieces of similar
programs can be
described at one
time!
NEXT
PLS M0
Y18
X170 X171
PLS M170
M170
Y178
1 - 11
1 - 11
1 OVERVIEW
MELSEC-Q
(4) Ease of data processing
The reinforced data processing instructions, such as table processing
instructions, enable high-speed processing of large amounts of data.
X0
FINSP D0
R0
K2
Instruction for data insertion at table
D0
15
R0
3
R0
4
R1
10
R1
10
R2
20
R2
15
R3
30
R3
20
R4
30
R4
(5)
FIF0 table
FIF0 table
Insertion Insertion Insertion position
source designation
Easy shared use of sub-routine programs
Subroutine call instructions with arguments will make it easier to create a
subroutine programs that makes several calls.
Main routine program
M0
0
CALLP P0
Argument designation
W0
K4X0
R0
Subroutine program
designation
Argument from FD2
Argument to FD1
Argument to FD0
Argument designation
M10
CALLP
100
P0
W10 K4X10 R10
Argument from FD2
Argument to FD1
Argument to FD0
FEND
Sub-routine program
SM400 M0
P0
Always
ON
Destination data
source data
MOV FD0
FD2
MOV FD1
FD2
M0
RET
END
REMARK
For details regarding the argument input/output condition, refer to Section 10.3.1.
1 - 12
1 - 12
MELSEC-Q
This section describes the system configuration of the Basic model QCPU, cautions on
use of the system, and configured equipment.
2.1 System Configuration
2
2.1.1 Q00JCPU
This section explains the equipment configuration of a Q00JCPU system and the
outline of the system configuration.
(1) Equipment configuration
MITSUBISHI
LITHIUM BATTERY
Battery
(Q6BAT)
Basic model QCPU
(Q00JCPU)
Input/output module/
Intelligent function module
Q5 B extension base unit
(Q52B, Q55B)
Extension cable
(QC05B, QC06B, QC12B,
QC30B, QC50B, QC100B)
(Q63B, Q65B, Q68B, Q612B)
2-1
Power supply module/
2-1
MELSEC-Q
(2) Outline of system configuration
(b) System including extension base unit and GOT
(a) System including extension base units
0 1 2 3 4
Extension
cable
0F 1F 2F 3F 4F
Extension base unit (Q68B)
5 6 7 8 9 10 11 12
Extension 1
O
IU
NT
System configuration
0 1 2 3 4
00 10 20 30 40
00 10 20 30 40
0F 1F 2F 3F 4F
5 6 7 8 9 10 11 12
Extension 1
50 60 70 80 90 A0 B0 C0
O
IU
NT
5F 6F 7F 8F 9F AF BF CF
C
P
U
O
U
T
Power supply
module
2
C
P
U
O
U
T
Power supply
module
Extension
cable
Slot number
50 60 70 80 90 A0 B0 C0
5F 6F 7F 8F 9F AF BF CF
Extension 2
D0 E0 F0
DF EF FF
Inhibited
Inhibited
O
IU
NT
Power supply
module
13 14 15
Number of extension units: 2
Slot No.
:0
Loading will cause error
Extension cable connector
Both of the above systems assume that each slot of the main and extension base units is
loaded with a 16-point module.
Maximum number of
Extension Stages
Maximum number of
input/output modules to
be installed
Maximum number of
input/output points
Main base unit
Extension base unit
Extension cable
Notes
Two Extension Stages
16 modules
256 1
Unnecessary
Q52B, Q55B, Q63B, Q65B, Q68B, Q612B
(1) Do not use an extension cable longer than an overall extension length of 13.2m(43.31ft.).
(2) When using an extension cable, do not bind it together with the main circuit (high voltage and
heavy current) line or do not lay down them closely to each other.
(3) When setting the No. of the expansion stages, set it in the ascending order so that the same
No. is not set simultaneously by two extension base units.
(4) The QA1S6 B/QA65B cannot be connected as an extension base unit.
(5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN
of the extension base unit on the next stage.
(6) If 17 or more modules are installed, an error will occur.
(7) When bus-connected, the GOT occupies one extension stage and one slot.
(8) The Q00JCPU processes the GOT as a 16-point intelligent function module. Hence, connection
of one GOT decreases the number of controllable points on base units by 16 points.
(9) The bus extension connector box (A9GT-QCNB) cannot be connected to the Q00JCPU. It
should be connected to the extension base unit.
1: Indicates the maximum number of I/O points of the CPU module and does not indicate the maximum number of I/O
points of the system.
When a CC-Link/LT module is used, 1024 points can be controlled per module.
2-2
2-2
MELSEC-Q
2.1.2 Q00, Q01CPU
This section explains the equipment configuration of a Q00/Q01CPU system and the
outline of the system configuration.
(1) Equipment configuration
(a) When main base unit (Q3 B) is used
MITSUBISHI
LITHIUM BATTERY
(Q52B, Q55B)
Basic model QCPU
(Q00CPU, Q01CPU)
Battery
(Q6BAT)
Main base unit
(Q33B, Q35B, Q38B, Q312B)
Extension cable
(QC05B, QC06B, QC12B,
QC30B, QC50B, QC100B)
(Q63B, Q65B, Q68B, Q612B)
POINT
As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P.
The slim type power supply module (Q61SP) cannot be used.
2-3
2-3
MELSEC-Q
(b) When slim type main base unit (Q3 SB) is used
MITSUBISHI
LITHIUM BATTERY
Basic model QCPU
(Q00CPUC Q01CPU)
Battery
(Q6BAT)
(Q32SB,Q33SB,Q35SB)
Slim type power supply, I/O,
intelligent function modules
POINT
(1) As a power supply module, use the slim type power supply module (Q61SP).
The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used.
(2) The slim type main base unit does not have an extension cable connector.
An extension base unit or GOT cannot be connected.
2-4
2-4
MELSEC-Q
(2) Outline of system configuration
(a) When main base unit (Q3 B) is used
(a) System including extension base units
(b) System including extension base unit and GOT
Power supply
module
O
IU
NT
Power supply
module
O
IU
NT
Extension 1
180 1A0 1C0 1E0 200 220 240 260
O
IU
NT
19F 1BF 1DF 1FF 21F 23F 25F 27F
280 2A0 2C0 2E0
29F 2BF 2CF 2FF
Slot No.
00 20 40 60 80 A0 C0 E0 100 120 140 160
1F 3F 5F 7F 9F BF DF FF 11F 13F 15F 17F
12 13 14 15 16 17 18 19
180 1A0 1C0 1E0 200 220 240 260
19F 1BF 1DF 1FF 21F 23F 25F 27F
GOT
20 21 22 23
Extension 2
CPU module
O
U
T
Power supply
module
Extension
cable
Inhibited
1F 3F 5F 7F 9F BF DF FF 11F 13F 15F 17F
12 13 14 15 16 17 18 19
Extension 1
Main base unit (Q312B)
0 1 2 3 4 5 6 7 8 9 10 11
Slot No.
00 20 40 60 80 A0 C0 E0 100 120 140 160
Power supply
module
O
U
T
CPU module
Extension
cable
Power supply
module
0 1 2 3 4 5 6 7 8 9 10 11
Slot No.
:0
Loading will cause error
Assumes that each slot is loaded with a 32-point module.
Maximum number of
Extension Stages
Maximum number of
input/output modules to
be installed
Maximum number of
input/output points
Main base unit
Extension base unit
Extension cable
Notes
Four Extension Stages
24 modules
1024 1
Q33B, Q35B, Q38B, Q312B
Q52B, Q55B, Q63B, Q65B, Q68B, Q612B
(1) Do not use an extension cable longer than an overall extension length of 13.2m(43.31ft.).
(2) When using an extension cable, do not bind it together with the main circuit (high voltage and
heavy current) line or do not lay down them closely to each other.
(3) When setting the No. of the expansion stages, set it in the ascending order so that the same
No. is not set simultaneously by two extension base units.
(4) The QA1S6 B/QA65B cannot be connected as an extension base unit.
(5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN
of the extension base unit on the next stage.
(6) If 25 or more modules are installed, an error will occur.
(7) When bus-connected, the GOT occupies one extension stage and one slot.
(8) The Q00/Q01CPU processes the GOT as a 16-point intelligent function module. Hence,
connection of one GOT decreases the number of controllable points on base units by 16 points.
(9) The Q61SP cannot be used as a power supply module.
As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P.
2-5
2-5
MELSEC-Q
(b) When slim type main base unit (Q3 SB) is used
CPU module
Power supply
module
Slim type main base unit (Q35SB)
Slot number
0 1 2 3 4
00 20 40 60 80
1F 3F 5F 7F 9F
* The above system assumes that each slot is loaded with a 32-point module.
Maximum number of
extension stages
Extension not allowed
Maximum number of
input/output modules to be
5 modules
installed
Maximum number of
input/output points
type
1024 1
Q32SB,Q33SB,Q35SB
Extension base unit type
Cannot be connected.
Extension cable type
(1) The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module.
Notes
As a power supply module, use the Q61SP.
An extension base unit or GOT cannot be connected.
2-6
2-6
MELSEC-Q
2.1.3 Configuration of GX Developer
Basic model QCPU
(Q00JCPU)
Basic model QCPU
(Q00CPU, Q01CPU)
RS-232 cable
(QC30R2)
Personal Computer
GX Developer
(Version 8 or later)*
REMARK
: GX Developer Version 7 can be used when the functions added to the function
version B of the Basic model QCPU are not used.
2-7
2-7
MELSEC-Q
2.2 Precaution on System Configuration
This section describes hardware and software packages compatible with Basic model
QCPU.
(1) Hardware
(a) The number of modules to be installed and functions are limited depending on
the type of the modules.
Applicable Module
Q Series MELSECNET/H
network module
Q series Ethernet interface
module
Limit of number of
modules to be installed
Type
QJ71LP21, QJ71BR11, QJ71LP21-25,
QJ71LP21G, QJ71LP21GE
Up to one module
QJ71E71, QJ71E71-B2, QJ71E71-100
Up to one module
Q series CC-Link system
master local module
QJ61BT11
Interrupt module
QI60
Up to 2 modules
function version B or
later
One module only 1
1: Indicates the number of interrupt modules to which interrupt pointer setting has not
been made.
When interrupt pointer setting has been made, up to the following number of
modules can be used.
Q00JCPU
: 16 modules
Q00CPU, Q01CPU : 24 modules
(b) A graphic operation terminal can be used only for the GOT900 series and
F900 series (Basic OS matching Q-mode and communication driver must be
installed).
The GOT800 series, A77GOT and A64GOT cannot be used.
(c) A DeviceNet Master-Slave module (QJ71DN91) whose function version is B
or later can be used.
(2) Software package
GX Developer and GX Configurator of the versions or later in the following table
are usable with the Basic model QCPU.
Product Name
Type
Version
GX Developer
SW7D5C-GPPW-E
Ver. 8
2
GX Simulator
SW6D5C-LLT-E
Ver. 6.13P
GX Configurator-AD
SW0D5C-QADU-E
Ver. 1.10L
GX Configurator-DA
SW0D5C-QDAU-E
Ver. 1.10L
GX Configurator-SC
SW0D5C-QSCU-E
Ver. 1.10L
GX Configurator-CT
SW0D5C-QCTU-E
Ver. 1.10L
GX Configurator-TC
SW0D5C-QTCU-E
Ver. 1.10L
GX Configurator-FL
SW0D5C-QFLU-E
Ver. 1.10L
GX Configurator-DN
SW0D5C-QDNU-E
Ver. 1.10L
GX Configurator-TI
SW0D5C-QTIU-E
Ver. 1.10L
GX Configurator-PT
SW1D5C-QPTU-E
Ver. 1.10L
GX Configurator-QP
SW2D5C-QD75P-E
Ver. 2.10L
2: Ver. 7 can be used when the functions added to the function version B of the Basic
model QCPU are not used.
2-8
2-8
MELSEC-Q
2.3 Confirming the function version
The Basic model QCPU function version can be confirmed on the rating nameplate
and GX Developer's system monitor.
(1) Confirming the function version on the rating nameplate
The function version is indicated on the rating nameplate.
MODEL
Function version
SERIAL 04122 0000000000-B
LISTED 80M1
IND.CONT.EQ.
MADE IN JAPAN
(2) Confirming the function version on the system monitor (product
information List)
The product information list in the system monitor of GX Developer allows you to
confirm the function version of the Basic model QCPU.
The product information list of the system monitor also allows you to confirm the
function versions of the intelligent function modules.
Serial No.
2-9
Function version
2-9
MELSEC-Q
The table below shows the performance specifications of the Basic model QCPU.
Performance Specifications
Item
Model
Q00JCPU
Control method
3
Total number of instructions (excluding
intelligent function module dedicated
instructions)
Constant scan
(Function to make the scan time
constant)
Program 1 2
capacity
Program memory
(Drive 0)
Standard RAM
Memory
(Drive 3)
capacity
Standard ROM
(Drive 4)
CPU shared memory
5
Number of
Program memory
stored
Standard ROM
programs
Number of
Standard RAM
stored file
registers
Number of times for write to standard
ROM
Remark
Direct input/output is
possible by direct
input/output
specification (DX ,
DY )
Refresh mode
Relay symbol language, logic symbolic language
MELSAP3 (SFC), MELSAP-L, function block,
structured text (ST)
0.20µs
0.16µs
0.10µs
0.70µs
0.56µs
318
8k steps
(32 kbyte)
327
8k steps
(32 kbyte)
58 kbyte
14k steps
(56 kbyte)
128 kbyte
3
58 kbyte
94 kbyte
None
1k byte (user free area 320 words)
2
4
2
4
1
Maximum 100,000 times
2048 points (X/Y0 to 7FF)
256 points
(X/Y0 to FF)
Set parameter values
to specify
94 kbyte
0
——
——
0.35µs
1 to 2000 ms (configurable in increments of 1 ms)
Number of I/O devices points
Number of I/O points
Q01CPU
Repetitive operation of stored program
I/O control method
Programming language
(Sequence control dedicated
language)
LD X0
Processing speed
(Sequence instruction)
MOV D0 D1
Q00CPU
1024 points
(X/Y0 to 3FF)
——
Number of devices
usable on program
Number of points
accesible to
input/output modules
1: "1 step" in program capacity equals 4 bytes.
2: The maximum number of executable steps can be obtained as follows:
(Program capacity) - (File header size (Default: 34 steps))
3: 64k bytes for function version A.
4: One sequence program and one SFC program can be stored (two programs in all).
5: Memory added for function version B.
The CPU shared memory is not latched. (Refer to Section 16.4 for details.)
The CPU shared memory is cleared when the PLC is powered on or the Basic model QCPU is reset.
3-1
3-1
MELSEC-Q
Performance Specifications (continued)
Item
Q00JCPU
Model
Q00CPU
Q01CPU
Internal relay [M]
Default 8192 points (M0 to 8191)
Latch relay [L]
Default 2048 points (L0 to 2047)
Link relay [B]
Default 2048 points (B0 to 7FF)
Remark
Default 512 points (T0 to 511) (for low / high speed timer)
Select between low / high speed timer by instructions.
The measurement unit of the low / high speed timer is set
Number of device points
Timer [ T ]
with parameters.
(Low speed timer
: 1 to 1000ms, 1ms/unit , default 100ms)
(High speed timer
: 0.1 to 100ms, 0.1ms/unit , default 10ms)
3
Default 0 point (ST0 to 511) (for low / high speed retentive
timer)
Switchover between the low / high speed retentive timer is
Retentive timer [ ST ]
set by instructions.
The measurement unit of the low speed retentive timer and
Number of use points
is set with
parameters.
high speed retentive timer is set with parameters.
(Low speed retentive timer : 1 to 1000ms, 1ms/unit , default 100ms)
(High speed retentive timer : 0.1 to 100ms, 0.1ms/unit , default 10ms)
• Normal counter default 512 points (C0 to 511)
Counter [C]
• Interrupt counter maximum 128 points
(default 0 point, set with parameters)
Data register [D]
Default 11136 points (D0 to 11135)
Link register [W]
Default 2048 points (W0 to 7FF)
Annunciator [F]
Default 1024 points (F0 to 1023)
Edge relay [V]
File Register
3-2
Default 1024 points (V0 to 1023)
[R]
None
32768 points (R0 to 32767)
[ZR]
None
65536 points (ZR0 to 65535)
3-2
MELSEC-Q
Performance Specifications (continued)
Item
Q01CPU
Special link relay [SB]
1024 points (SB0 to 3FF)
Special link register [SW]
1024 points (SW0 to 3FF)
Step relay [S] 6
Model
Q00CPU
Q00JCPU
Remark
2048 points (S0 to 127/block)
Index register [Z]
10 points (Z0 to 9)
Pointer [P]
300 points (P0 to 299)
128 points (I0 to 127)
The specified intervals of the system interrupt pointers I28 to
Interrupt pointer [ I ]
The number of device
I31 can be set with parameters.(0.5 to 1000ms, Cunit in 0.5 ms) points is fixed.
Default I28 : 100ms I29 : 40ms I30 : 20ms I31 : 10ms
Special relay [SM]
1024 points (SM0 to 1023)
Special register [SD]
1024 points (SD0 to 1023)
Function input [FX]
16 points (FX0 to F) 7
Function output [FY]
16 points (FY0 to F) 7
Function register[FD]
5 points (FD0 to 4)
Device for direct access to link device.
MELSECNET/H use only.
Link direct device
Specified form at : J
\X
,J
\Y
J
\B
,J
\SW
,J
\W
,J
,
\SB
Device for direct access to the buffer memory of the
intelligent function module. Specified form at : U
\G
Intelligent function module device
Latch (power failure conpensation)
L0 to 2047 (default)
range
(Latch range can be set for B, F, V, T, ST, C, D, and W.)
RUN and PAUSE contacts can be set from among X0 to
Remote RUN/PAUSE contact
Set parameter values
to specify
7FF, respectively.
Year, month, day, hour, minute, second, day of the week
(leap year automatic distinction)
Clock function
Accuracy -3.2 to +5.27s (TYP. +1.98s) /d at 0°C
Accuracy -2.57 to +5.27s(TYP. +2.22s)/d at 25°C
Accuracy -11.68 to +3.65s(TYP. -2.64s)/d at 55°C
Max. 20ms
Allowable momentary stop time
(Min. 100VAC)
5VDC internal current consumption
H
External dimensions
W
D
Weight
0.22A 8
98mm (3.86in.)
245mm (9.65in.)
9
Varies according to the type of power
supply module.
0.25A
0.27A
98mm (3.86in.)
27.4mm (1.08in.)
97.5mm (3.84in.)
89.3mm (3.52in.)
0.66kg 9
0.13kg
6: Step relay is a device for SFC function.
7: Only FX0 to FX4 and FY0 to FY4 can be used in a program.
8: This value includes those for the CPU module and base unit.
9: This value includes those for the CPU module, base unit, and power supply module.
3-3
3-3
4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION
CONDITIONS
MELSEC-Q
4 SEQUENCE PROGRAM CONFIGURATION & EXECUTION CONDITIONS
Programs that can be executed by the Basic model QCPU are sequence programs
(MAIN) and SFC programs (MAIN-SFC).
This chapter describes the sequence program configuration and execution conditions.
For SFC programs, refer to the QCPU (Q mode)/QnACPU Programming Manual
(SFC).
The Basic model QCPU executes a sequence program and SFC program in the
following order.
Initial processing
Refresh processing of I/O modules
4
Operation processing of sequence program
Operation processing of SFC program
END processing
Fig. 4.1 Execution Sequence of Basic Model QCPU
4-1
4-1
CONDITIONS
MELSEC-Q
4.1 Sequence Program
(1) Definition of sequence program
(a)
A sequence program is created using sequence instructions, basic
instructions, and application instructions, etc.
Sequence instruction
X0
M0
K100
T0
T0
Y30
Basic instruction
X1
BIN
K4X10
D0
Application instruction
X41
FROM
4
(b)
H5
K0
D10
K1
There are 3 types of sequence program: main routine programs, sub-routine
programs, and interrupt programs.
For details regarding these programs, refer to the following sections of this
manual:
• Main routine programs
: Section 4.1.1
• Sub-routine programs
: Section 4.1.2
• Interrupt programs
: Section 4.1.3
MAIN
Main routine
program
FEND
P0
Sub-routine
program
RET
I0
Interrupt
program
IRET
END
REMARK
For details regarding the sequence instructions, basic instructions, and application
instructions, refer to the " QCPU (Q Mode)/QnACPU Programming Manual
(Common Instructions)".
4-2
4-2
CONDITIONS
MELSEC-Q
(2) Sequence program writing format
Programming for sequence programs is possible using either ladder mode, or list
mode.
(a)
Ladder mode
• The ladder mode is based on the relay control sequence ladder.
Programming expressions are similar to the relay control sequence ladder.
• Relay symbolic language programming occurs in ladder block units.
A ladder block is the smallest unit of sequence program processing, with
the ladder beginning from the left bus and ending at the right bus.
Left bus
0
Step No.
a Contact
b Contact
Coil (output)
Right bus
X0
X1
Y20
X2
X3
Y21
2
Ladder blocks
Y22
Y23
8
X4
X5
Y24
Y24
X0 to X5
: Indicate inputs.
Y20 to Y24 : Indicate outputs.
Fig.4.2 Ladder Block
(b)
List mode
The list mode uses dedicated instructions instead of the contact symbols,
coil symbols, etc., used in the ladder mode.
Contact a, contact b and coil instructions are as follows:
• a contact ............LD, AND, OR
• b contact ............LDI, ANI, ORI
• coil......................OUT
(2) Program processing
Sequence programs are processed in order, beginning from step 0 and ending at
the END/FEND instruction.
Processing of ladder mode ladder blocks begins from the left bus, and proceeds
from left to right. When one ladder block is completed, processing proceeds
downward to the next ladder block.
[List mode]
[Ladder mode]
Left to right
1) 2) 7) 8) 9)
X0 X1 X5 X6 X7
0
3) 4)
X2 X3
Top to
bottom
10)
Y10
5)
6)
X4
10
11)
END
Numbers 1) to 11) indicate the processing
order of the sequence program.
0 LD
1 AND
2 LD
3 AND
Executed in
4 ORB
order, beginning 5 OR
from step 0 to
6 AND
7 AND
the ending at
8 AND
the END
9 OUT
instruction.
10 END
X0
X1
X2
X3
X4
X5
X6
X7
Y10
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
Step No.
Fig.4.3 Sequence Program Processing
4-3
4-3
CONDITIONS
MELSEC-Q
4.1.1 Main routine program
(1) Definition of main routine program
(a)
(b)
A main routine program is a program which begins from step 0 and ends at
the END/FEND instruction. 1
The main routine program execution begins from step 0 and ends at the
END/FEND instruction.
When the END/FEND instruction is executed in the main routine program,
END processing is performed and operation is then restarted from step 0.
Step 0
Program execution
Main routine
program
Returns to step 0
END/FEND
END/FEND
END processing
(2) Execution of main routine program
The main routine program is executed every scan.
REMARK
1: For details regarding the END/FEND instruction, refer to the "QCPU (Q
mode)/QnACPU Programming Manual (Common Instructions)".
4-4
4-4
CONDITIONS
MELSEC-Q
4.1.2 Sub-routine programs
(1) Definition of sub-routine program
(a)
(b)
(c)
A sub-routine program is a program which begins from a pointer (P ) and
ends at a RET instruction.
A sub-routine program is executed only when called by a CALL instruction
(e.g. CALL(P), FCALL(P)) from the main routine program.
Sub-routine program application
1) The overall step count can be reduced by using a sub-routine program
as a program which is executed several times in one scan.
2) The step count of a constantly executed program can be reduced by
using a sub-routine program as a program which is executed only
when a given condition is satisfied.
(2) Sub-routine program management
Sub-routine programs are created after the main routine program (after FEND
instruction), and the combination of main and sub-routine programs is managed
as one program.
Create a sub-routine program as described below.
• A sub-routine program is created between the main routine program's FEND
and END instructions.
• Because there are no restrictions regarding the order in which sub-routine
programs are created, there is no need to set the pointers in ascending order
when creating multiple sub-routine programs.
Basic model QCPU
MAIN
Program memory
/standard ROM
Main routine
program
Write
MAIN file
FEND
P0
Y10
RET
Sub-routine
program
P8
Y11
RET
P1
Y12
RET
END
4-5
4-5
CONDITIONS
MELSEC-Q
4.1.3 Interrupt programs
(1) Definition of interrupt program
(a)
(b)
An interrupt program is a program which begins at the interrupt pointer
(I ), and ends at the IRET instruction. 1
Interrupt programs are executed only when an interrupt factor occurs. 1
(2) Interrupt program management
Interrupt programs are created after the main routine program (after the FEND
instruction), and the combination of main and sub-routine programs is managed
as one program.
Create an interrupt program as described below.
• An interrupt program is created between the main routine program's FEND and
END instructions.
• Because there are no restrictions regarding the order in which interrupt
programs are created, there is no need to set the interrupt pointers in ascending
order when creating multiple interrupt programs.
Basic model QCPU
MAIN
Program memory
/standard ROM
Main routine
program
Write
MAIN file
FEND
I0
Y10
IRET
Interrupt
program
I50
Y11
IRET
I28
Y12
IRET
END
Interrupt pointer
REMARK
1: See Section 10.10 for details regarding interrupt factors and interrupt pointers.
4-6
4-6
CONDITIONS
MELSEC-Q
(3) Executing interrupt programs
(a)
To run an interrupt program, interrupts must have been enabled by the EI
instruction. 1
1) If interrupt factors occur before interrupts are enabled, the interrupt
factors that occurred are stored, and the interrupt programs
corresponding to the stored interrupt factors are executed as soon as
interrupts are enabled.
2)
If the same interrupt factor occurs more than once, the interrupt factors
of I0 to I15 and I50 to I127 are stored and the interrupt factors of I28 to
I31 are discarded.
Interrupt program example
Interrupt program execution
Interrupt program for
"I0" activated
EI
Main routine
program
FEND
Program execution
End of main
routine program
I0
Interrupt program
for "I29" activated
FEND
Interrupt
program
I0
IRET
"I0" interrupt
program
I29
Interrupt
program
I29
IRET
"I29" interrupt
program
END
END
Fig.4.4 Interrupt Program Execution
(b)
When an interrupt factor occurs, the interrupt program with the interrupt
pointer number corresponding to that factor is executed.
However, interrupt program execution varies according to the condition at
that time.
1) : When multiple interruptions occur simultaneously
When multiple interrupt programs are activated simultaneously, the
programs will be executed in order, beginning from the interrupt
program with the highest priority interrupt pointer number. 3
The remaining interrupt programs remain on stand-by until processing
of the higher priority interrupt program is completed.
If the same interrupt factor as that being executed occurs before the
processing of the interrupt program being executed is completed, the
interrupt factors of I0 to I15 and I50 to I127 are stored and the interrupt
factors of I28 to I31 are discarded.
2)
4-7
When an instruction is being executed
The interrupt program may be executed by interrupting the execution
of an instruction in the main routine program. When the same device is
used in both the main routine program and interrupt program, device
data may be separated.
To prevent the separation of the device data, the following measures
must be taken.
(a) Do not specify the device, to which data will be written in the
interrupt program, directly in the main routine program, but use
another device by shifting the data with a transfer instruction, etc.
4-7
CONDITIONS
MELSEC-Q
(b)
3)
If inconvenience is caused when the instruction is interrupted in
the main routine program, execute it after disabling the
interruption with the DI instruction.
However, since the interrupt program will not interrupt during
access to the device of each argument of the instruction, data
separation will not occur on an argument basis.
Interruption during a network refresh:
If an interrupt factor occurs during a network refresh operation, the
network refresh operation is suspended, and the interrupt program is
executed.
This means that "assurance of blocks in cyclic data at each station"
cannot be secured by using a device designated as a destination of
link refresh operation on the MESSECNET/H Network System. 3
10ms
10ms
10ms
10ms
Interrupt factor
Interrupt program
execution
Network refresh
execution
Network refresh operation is suspended,
and the interrupt program is executed.
Fig.4.5 Interruption during Network Refresh Operation
4)
(c)
Interruption during END processing:
If an interrupt factor occurs during an END processing waiting period
during constant scanning, the interrupt program corresponding to that
factor will be executed.
When the interrupt program is executed in the default setting of the Basic
model QCPU, the save and restoration of the index register value and the
save and restoration of the file register block No. are performed at the time
of switching between the main routine program and interrupt program.
Refer to Section 10.6.1 for details.
(4) High-speed execution of an interrupt program and overhead time
When "Execute at a High Speed" is selected for the interrupt program in the PLC
system setting of the PLC parameter dialog box, the "save and restoration of the
index register value" is not performed at the time of switching between the main
routine program and interrupt program.
This will make it possible to shorten the duration of overhead time required for
execution of an interrupt program.
Refer to Section 11.2 for the overhead time of an interrupt program.
4-8
4-8
CONDITIONS
MELSEC-Q
REMARK
2: For details regarding the IMASK and EI instructions, refer to the "QCPU (Q mode)/
QnACPU Programming Manual (Common Instructions).
3: See Section 10.10 for details regarding the priority ranking of interrupt programs.
4: For assurance of station unit blocks in cyclic data, see the "MELECNET/H
Network System Reference Manual."
(5) Program creation restrictions
(a)
A device which is switched ON by a PLS instruction in an interrupt program
will remain ON until the PLS instruction for the same device is executed
again.
X0
END
0
X0
PLS M0
IO IRET END 0
END
0 IO
IRET END
PLS M0
0
ON
X0 OFF
ON
M0 OFF
Switched OFF by PLS M0 instruction
Switched ON by PLS M0 instruction at X0 leading edge (OFF to ON)
(b)
During execution of the interrupt program, interrupts are disabled (DI) so
that other interrupt processing is not performed.
Do not execute EI/DI instructions in the interrupt program.
(c)
Timers cannot be used in interrupt programs.
instructions to update present values and
As timers are used at OUT T
switch contacts ON and OFF, the use of a timer in the interrupt program
would make a normal time count impossible.
(d)
The following instructions cannot be used in interrupt programs.
• COM
• ZCOM
• EI
• DI
• S.TO
(e) When the interrupt program is executed when measuring time such as the
scan time or execution time, the measured time will become the value
obtained by adding the interrupt program/constant cycle execution type
program.
Thus, if the interrupt program is executed, the values stored in the following
special registers and GX Developer monitor values will become longer than
when the interrupt program is not executed.
1) Special registers
• SD520, SD521: Current scan time
• SD524, SD525: Minimum scan time
• SD526, SD527: Maximum scan time
• SD540, SD541: END processing time
• SD542, SD543: Constant scan wait time
2) GX Developer monitor values
• Scan time measurement
• Constant scan
4-9
4-9
CONDITIONS
MELSEC-Q
4.2 Concept of Scan Time
(1) Scan time
(a)
The "scan time" is a total of following the execution time of program and
END processing.
When an interrupt program is executed, the value including the execution
time of the interrupt program will be the scan time.
(b)
The scan time present value, minimum value, and maximum value are
measured at the Basic model QCPU, and the results are stored in special
registers (SD520, SD521, and SD524 to SD527). 1
The scan time can therefore be checked by monitoring the SD520, SD521,
and SD524 to SD527 special registers.
Current value
SD520
SD521
Minimum value
SD524
SD525
Maximum value
SD526
SD527
Stores less than 1 ms initial scan time (unit
s)
Stores the initial scan time in 1 ms units.
If the SD520 value is 3, and the SD521 value is 400, the initial scan time is 3.4
ms.
POINT
1: The accuracy of the scan time stored at the special registers is ± 0.1 ms.
The scan time count will continue even if a watchdog time reset instruction
(WDT) is executed at the sequence program.
(2) Constant scan setting
Constant scan is a function that repeats the execution of a main routing program
at give intervals.
When constant scanning is designated, the main routine program is executed at
each designated constant scan period.
Refer to Section 7.2 for details of constant scan.
(3) WDT (Watchdog timer)
This is the timer which monitors the scan time, and its default setting is 200 ms.
This WDT setting can be designated in a 10 ms to 2000 ms range in the PLC
RAS settings of the PLC parameter.
(Setting units: 10 ms)
POINT
The WDT measurement error is 10 ms.
Therefore, a WDT setting (t) of 10 ms will result in a "WDT ERROR" if the scan
time is in the following range: 10 ms < t < 20 ms.
4 - 10
4 - 10
CONDITIONS
MELSEC-Q
4.3 Operation Processing
4.3.1 Initial processing
This is a preprocessing for sequence operation execution, and is performed only once
as shown in the table below.
When the initial processing is completed, the Basic model QCPU goes in the
RUN/STOP/RESET switch setting status. (See Section 4.4.)
Initial processing item
Basic model QCPU status
When the power When reset is When STOP
to RUN 1
is turned on.
executed.
The Input/Output module initialization
Boot from the standard ROM
PLC parameter check
Multiple PLC system parameter matching check
Device initialization of the range not latched
(bit device: OFF, word device: 0)
Automatic allocation of the I/O number of
installed modules
Start of the MELSECNET/H network information
setting and network communication
Switch setting of intelligent function module
Setting of CC-Link information
Setting of Ethernet information
Device initial value
Setting of serial communication function
: executed,
: not executed
REMARK
1: Indicates that the parameter or program was changed in a STOP status and the
CPU was placed in a RUN status without being reset.
(The RUN/STOP/RESET switch has been moved from STOP to RUN (RUN
LED flickers) to STOP to RUN.)
Since the previous data may not be maintained in the pulse conversion
instruction (PLS, P) by the above operation depending on the program
change, fully note that normal operation may not be performed.
4 - 11
4 - 11
CONDITIONS
MELSEC-Q
4.3.2 I/O refresh (I/O module refresh processing)
In I/O refresh, an input (X) is received from the input module/intelligent function
module, and output (Y) of the Basic model QCPU is produced to the output
module/intelligent function module.
The I/O refresh is executed before the sequence program operation starts.
During constant scan execution, the I/O refresh is executed after the constant scan
delay time has elapsed.
(The I/O refresh is executed at each constant scan cycle.)
4.3.3 Automatic refresh of the intelligent function module
When automatic refresh of intelligent function modules is set, communication with the
intelligent function modules of the designated data is performed.
Refer to the manual for the intelligent function modules to use for details regarding of
the automatic refresh setting of intelligent function modules.
4.3.4 END processing
This is a post-processing to return the sequence program execution to step 0 after
completing the whole sequence program operation processing once.
• MELSECNET/H or CC-Link refresh processing
• Automatic refresh of intelligent function module
• Self-diagnostics
• Communication with external device such as GX Developer
• Processing of intelligent function module dedicated instruction (Completion
processing only)
4 - 12
4 - 12
CONDITIONS
MELSEC-Q
4.4 RUN, STOP, PAUSE Operation Processing
The Basic model QCPU has three types of operation states; RUN, STOP and PAUSE
states.
The Basic model QCPU operation processing is explained below:
(1) RUN Status Operation Processing
(a)
RUN status is when the sequence program operation is performed from
step 0 to END (FEND) instruction to step 0 repeatedly.
(b) When entering the RUN state, the output state saved at STOP by the
parameter output-mode setting during STOP to RUN.
(c) The processing time of switching from STOP to RUN until the beginning of
sequence program operation changes with system configurations, but
usually is 1 to 3 seconds.
However, this time may be longer depending on the conditions.
(2) STOP Status Operation Processing
(a)
(b)
STOP status is when the sequence program operations are stopped with
the RUN/STOP/RESET switch or remote STOP is performed. (Refer to
Section 7.6.1 for details regarding of remote STOP function.)
The STOP status is also caused by a stopping error.
When entering the STOP state, save the output state and turn off all output.
The device memory of other than the output (Y) is retained.
(3) PAUSE Status Operation Processing
(a)
The PAUSE state is when the sequence program operations are paused by
remote PAUSE function while maintaining the output and device memory
status. (Refer to Section 7.6.2 for details regarding of remote PAUSE
function.)
(4) Basic model QCPU Operation Processing with RUN/STOP state
Operation
processing
RUN/STOP
state
RUN to STOP
STOP to RUN
4 - 13
Sequence
program operation
processing
Device memory
External output
OS saves the status
Executes up to the
immediately before
END instruction
the STOP state and
and stops.
all points turn off.
Starts at step 0.
Determined by the
output mode of the
PLC parameter at
STOP to RUN.
M, L, S, T, C, D
Y
Maintains the status
immediately before the
STOP state.
Determined by the
"STOP to RUN-time
output mode" in the PLC
parameter dialog box.
Starts executing the
operation from the status
STOP state.
When a device initial value
is designated, however,
the value is set.
Local devices are cleared.
OS saves the status
STOP state and all
points turn off.
4 - 13
CONDITIONS
MELSEC-Q
POINT
The Basic model QCPU performs the following in any of RUN, STOP, and Pause
state:
• I/O module refresh processing
• Data communication with the GX Developer and serial communication module
• Refresh process of MELSECNET/H and CC-Link
For this reason, I/O monitor and test operation using GX Developer, reading/writing
from the serial communication, communication with another station using
MELSECNET/H, and communication with a remote station over the CC-Link can
be made even in the STOP or PAUSE status.
4.5 Operation Processing during Momentary Power Failure
The Basic model QCPU detects a momentary power failure to the power module when
the input power voltage is lower than the regulated ranges.
When the Basic model QCPU detects a momentary power failure, the following
operation processing is performed:
(1) When momentary power failure occurs for less than permitted
power failure time
(a)
(b)
(c)
The output is maintained when the momentary power failure occurs, and file
name of the file accessed and error history are logged. Then the system
interrupts the operation processing. (The timer clock continues.)
When a momentary power failure ends, the operation processing is
resumed.
Even if the operation is interrupted due to momentary power failure, the
watchdog timer (WDT) measurement continues. For example, if the GX
Developer PLC parameter mode WDT setting is set at 200 ms, when a
momentary failure of 15 ms occurs at scan time 190 ms, the watchdog
timer error is set.
Momentary power failure occurrence
END 0
Power recovery
END
END
QCPU interrupts the operation.
Fig.4.6 Operation Processing When Momentary Power Failure Occurs
(2) When a power failure occurs for more than the permitted power
failure time
The Basic model QCPU starts initially. (PLC power is turned on.)
The same operation processing as that after the following operation occurs.
• Power ON
• Resetting using RUN/STOP/RESET switch
• Remote setting using GX Developer
4 - 14
4 - 14
CONDITIONS
MELSEC-Q
4.6 Data Clear Processing
(1) Data clear
The Basic model QCPU clears all data except for the following, when a reset
operation is performed with RESET/L.CLR switch, or power ON to OFF to ON.
(a) Program memory data
(b) Device data with latch specification (latch clear valid)
(c) Device data with latch specification (latch clear invalid)
(d) File register data
(e) Failure history data (when special register SD storage)
Data in (b) is cleared using the remote latch clear from the GX Developer
function.
Refer to Section 7.6.4 for details regarding of the remote latch clear.
(2) Device latch specification
(a)
Specify the device latch (latch range setting) for each device in the device
setting of the PLC parameter.
There are two types of latch range settings:
1) Valid latch clear key
Sets the latch range that can be cleared with latch-clear operation
using the remote latch clear.
2) Invalid latch clear key
Sets the latch range that can not be cleared even with latch-clear
operation using the remote latch clear.
(b)
The devices that were set to invalid RESET/L.CLR switch can only be
cleared by an instruction or GX Developer clear operation.
1) Instruction to clear method
Reset with the RST instruction or send "0" with the MOV/FMOV
instruction.
2) GX Developer clear method
Clear all device memory in the online PLC memory clear (including
latch).
For the GX Developer operation method, refer to the GX Developer
Operating Manual.
POINT
To clear file registers or local devices, use the RST instruction to perform a reset
operation, or use the MOV/FMOV instruction to transmit "0".
REMARK
See following manual for the MOV/FMOV instruction.
• QCPU (Q mode)/QnACPU Programming Manual (Common instructions)
4 - 15
4 - 15
CONDITIONS
MELSEC-Q
4.7 Input/Output Processing and Response Lag
The Basic model QCPU features a refresh type input/output processing format in
which a batch communication with the input/output module occurs at END processing.
A direct communication format is also possible by using direct access inputs/outputs at
the sequence program to enable direct communication with the input/output module
when the sequence program instructions are executed.
For details regarding direct inputs and direct outputs, refer to Sections 10.2.1 and
10.2.2, respectively.
4.7.1 Refresh mode
(1) Definition of refresh mode
In the refresh mode, batch communication with the input/output modules is made
before start of the sequence program operation.
(a) The ON/OFF data of the input module are batch-imported to the input
device memory in the Basic model QCPU before start of the sequence
program operation.
(b) The operation result of the output (Y) sequence program is output to the
output device memory in the Basic model QCPU every time the result
ocurs, and the ON/OFF data of the output device memory are batch-output
to the output module before start of the sequence program operation.
Basic model QCPU
Remote input
refresh area
3
CPU (operation processing area)
3)
X0
Input (X)
device
memory
GX Developer
input area
1
1) At input
refresh
4)
Y22
Y20
5)
2
Network
module
At input
refresh
1)
Input
module
Area for
communication
with input module
Output (Y)
device
memory
At output
refresh
2)
Output
module
Network
module
• Input refresh:
Before start of the sequence program operation, input data are batch-read from the
input module (1) and ORed with the GX Developer input area or remote input refresh
area data, and the results are stored into the input (X) device memory.
• Output refresh:
Before start of the sequence program operation, the data (2) of the output (Y) device
memory are batch-output to the output module.
• When an input contact instruction has been executed:
Input information is read 3) from the input (X) device memory, and a sequence
program is executed.
• When an output contact instruction has been executed:
Output information is read 4) from the output (Y) device memory, and a sequence
• When an output OUT instruction has been executed:
The sequence program operation result 5) is stored in the output (Y) device memory.
Fig.4.7 Input/Output Information Flow at Refresh Mode
4 - 16
4 - 16
CONDITIONS
MELSEC-Q
REMARK
1: The GX Developer input area can be switched ON and OFF by the following:
• Test operation by the GX Developer
• Network refresh of MELSECNET/H network system
• Writhing from a serial communication module
• Automatic refresh of CC-Link
2: The output (Y) device memory can be switched ON and OFF by the following:
• A network refresh by the MELSECNET/H network system
• CC-Link automatic refresh
3: The remote input/output refresh area indicates the area used when automatic
refresh setting is made to the input (X) with MELSECNET/H and CC-Link.
Automatic refresh of the remote input refresh area is executed during END
processing.
4 - 17
4 - 17
CONDITIONS
MELSEC-Q
(2) Response lag
Output response lags of up to 2 scans can result from input module changes.
(See Fig.4.7)
Ladder examples
55
X5
Ladder for switching the Y5E output
ON in response to an X5 input ON.
Y5E
Fastest possible Y5E ON
Input refresh
0
Input refresh
END 0 56
Output refresh
0
END
ON
External contact
OFF
ON
X5
Q00J/Q00/
Q01CPU
devices
OFF
ON
Y5E
OFF
ON
External load
OFF
Lag time
(Minimum 1 scan)
The fastest possible Y5E ON occurs if the external contact is switched ON
immediately prior to the refresh operation. X5 then switches ON at the input refresh,
Y5E at step 56 switches ON, and the external load switches ON at the output refresh
following execution of the END instruction. In this case, the time lag between the
external contact ON and the external load ON is 1 scan.
Slowest possible Y5E ON
Input refresh
0
Input refresh
END 0 56
Output refresh
END
0
ON
OFF
External contact
ON
Q00J/Q00/
Q01CPU
devices
X5
OFF
ON
Y5E
OFF
ON
External load
OFF
Lag time
(Maximum 2 scan)
The slowest possible Y5E ON occurs if the external contact is switched ON
immediately prior to the refresh operation. X5 then switches ON at the input refresh,
Y5E at step 56 switches ON, and the external load switches ON at the output refresh
following execution of the END instruction. In this case, the time lag between the
external contact ON and the external load ON is 2 scan.
Fig.4.8 Output "Y" change in response to input "X" change
4 - 18
4 - 18
CONDITIONS
MELSEC-Q
4.7.2 Direct mode
(1) Definition of direct mode
In the direct mode the communication with the input/output modules is performed
when executing sequence program instructions.
With Basic model QCPU, direct mode I/O processing can be executed by using
direct access inputs (DX) and direct access outputs (DY).
See 10.2.1 for direct access inputs. See 10.2.2 for direct access outputs.
Basic model QCPU
CPU (operation processing area)
3)
DX0
Input (X)
device
memory
4)
Y20
DY25
5)
Remote input
refresh area
3
2) GX Developer
input area
1
2
Output (Y)
device
memory
Network
module
1)
Input
module
Output
module
• When an input contact instruction has been executed:
The input data (1) of the input module are ORed with the input data (2) of the GX
Developer input area or the data of the remote input refresh area. The results are
stored into the input (X) device memory and used as input data (3) to execute the
sequence program.
• When an output contact instruction has been executed:
Output information 4) is read from the output (Y) device memory, and a sequence
• When an output OUT instruction has been executed:
The sequence program's operation result 5) is output to the output module, and is
stored in the output (Y) device memory.
Fig.4.9 Input/Output Information Flow at Direct Mode
REMARK
1: The GX Developer input area can be switched ON and OFF by the following:
2: The output (Y) device memory can be switched ON and OFF by the following:
4 - 19
4 - 19
CONDITIONS
MELSEC-Q
(2) Response lag
Output response lags of up to 1 scans can result from input module changes.
(See Fig.4.10)
Ladder examples
DX5
55
DY5E
Ladder for switching the DY5E output
ON in response to an DX5 input ON.
Fastest possible DY5E ON
LD DX5
OUT DY5E
0
55
56
ON
DX5
OFF
ON
DY5E
OFF
The fastest possible DY5E output ON occurs if the DX5 input is switched ON
immediately prior to the step 55 operation. If DX5 is ON when step 55's LD DX5 is
executed, DY5E will switch ON within that scan.
This condition represents the minimum time lag between the DX5 input ON and the
DY5E output ON.
Slowest possible DY5E ON
LD DX5
OUT DY5E
0 55 56 END 0
55 56
ON
DX5
OFF
ON
DY5E
OFF
Lag time
(Maximum of 1 scan)
The slowest possible DY5E output ON occurs if the DX5 input is switched ON
immediately after the step 55 operation. In this case, the DY5E output will switch ON
during the next scan.
This condition represents the maximum time lag (1 scan) between the DX5 input ON
and the DY5E output ON.
Fig.4.10 Output "Y" Change in Response to Input "X" Change
4 - 20
4 - 20
CONDITIONS
MELSEC-Q
4.8 Numeric Values which Can Be Used in Sequence Programs
Numeric and alphabetic data are expressed by "0" (OFF) and "1" (ON) numerals in the
Basic model QCPU.
This method of expression is called "binary code" (BIN).
The hexadecimal (HEX) expression method in which BIN data are expressed in 4-bit
units, and the BCD (binary coded decimal) expression method are also possible for the
Basic model QCPU.
Real numbers may also be used. (See Section 4.8.4)
The numeric expressions for the BIN, HEX, BCD, and Decimal (DEC) notations are
shown in Table 4.1 below.
Table 4.1 BIN, HEX, BCD, and Decimal Numeric Expressions
BCD
DEC (Decimal)
HEX (Hexadecimal)
0
0
0
0
1
1
1
1
2
2
10
10
3
3
11
11
•
•
•
•
•
•
•
•
4 - 21
BIN (Binary)
(Binary Coded Decimal)
•
•
•
•
9
9
1001
1001
10
A
1010
1 0000
11
B
1011
1 0001
12
C
1100
1 0010
13
D
1101
1 0011
14
E
1110
1 0100
15
F
1111
1 0101
16
10
1 0000
1 0110
17
11
1 0001
1 0111
•
•
•
•
•
•
•
•
•
•
47
2F
•
•
•
•
•
•
10 1111
100 0111
•
•
32766
7FFE
0111 1111 1111 1110
——
——
32767
7FFF
0111 1111 1111 1111
-32768
8000
1000 0000 0000 0000 1000 0000 0000 0000
-32767
8001
1000 0000 0000 0001 1000 0000 0000 0001
•
•
•
•
•
•
-2
FFFE
1111 1111 1111 1110
——
-1
FFFF
1111 1111 1111 1111
——
4 - 21
CONDITIONS
MELSEC-Q
(1) External numeric inputs to Basic model QCPU
When designating numeric settings for the Basic model QCPU from an external
source (digital switch, etc.), a BCD (binary coded decimal) setting can be
designated which is the same as a decimal setting.
However, because the Basic model QCPU operation is based on BIN, if the
Basic model QCPU uses values designated in the BCD method as they are, it
handles the values as BIN.
The Basic model QCPU operation based on such values will be different from the
operation specified by the designated values.
A BIN instruction is therefore provided for the Basic model QCPU to convert BCD
input data to the BIN data which is used by the Basic model QCPU.
A program which converts numeric data to BIN data can be created at the
sequence program in order to allow numeric settings to be designated from an
external source without regard to the corresponding BIN values.
Basic model QCPU
[Numeric data designation]
BINP K4X0 D0
Digital switch
4
XF
3
2
1
X0
BCD input
BIN data
BCD D5 K4Y30
Fig.4.11 Digital Switch Data Input to Basic model QCPU
(2) External numeric outputs from Basic model QCPU
A digital display can be used to display numeric data which is output from the
Basic model QCPU.
However, because the Basic model QCPU uses BIN data, it cannot be displayed
at the digital display as is.
A BCD instruction is therefore provided for the Basic model QCPU to convert the
BIN data to BCD data. A program which converts BIN data to BCD data can be
created at the sequence program in order to display the output data in a manner
identical to decimal data.
Basic modle QCPU
[Numeric data designation]
BINP K4X0 D0
Digital display
Y3F
BCD D5 K4Y30
Y30
BCD output
BIN data
Fig.4.12 Digital Display of Data from Basic model QCPU
4 - 22
4 - 22
CONDITIONS
MELSEC-Q
4.8.1 BIN (Binary Code)
(1) Binary code
In binary code, numeric values are expressed by numerals "0" (OFF) and "1"
(ON) numerals.
When counting in the decimal system, a carry to the "tens" column occurs
following 9 (8 to 9 to 10).
In the binary system, this carry occurs following 1 (0 to 1 to 10). The binary "10"
therefore represents the decimal "2".
Binary values and their respective decimal values are shown in Fig.4.2 below.
Table 4.2 Binary and Decimal Numeric Value Comparison
DEC (Decimal)
BIN (Binary)
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
1010
11
1011
Carry
Carry
Carry
(2) Binary numeric expression
(a)
Basic model QCPU registers (data registers, link registers, etc.) consist of
n
16 bits, with a "2 " value is allocated to each of the register bits.
The most significant bit (initial bit) is used to discriminate between "positive"
and "negative".
1) When most significant bit is "0"...Positive
2) When most significant bit is "1"...Negative
The numeric expressions for the Basic model QCPU registers are shown in
Fig.4.12 below.
Bit name
Most significant bit (for positive/negative discrimination)
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
2 15 2 14 2 13 2 12 2 11 2 10 2 9
Decimal value
28
23
22
2 1 20
-32768 16384 81924096 20481024 512 256 128 64 32 16 8
4
2
27
26
25
24
1
"Negative value" when most significant bit is "1".
Fig.4.12 Numeric Expressions for Basic model QCPU Registers
(b)
4 - 23
Usable numeric data for Basic model QCPU
As shown in Fig.4.11, the numeric expression range is -32768 to 32767.
Therefore, numeric data within this range can be stored in the Basic model
QCPU registers.
4 - 23
CONDITIONS
MELSEC-Q
4.8.2 HEX (Hexadecimal)
(1) Hexadecimal notation
In the hexadecimal system, 4 bits of binary data are expressed by 1 digit.
4 bits of binary data can express 16 values (0 to 15).
In the hexadecimal system, values from 0 to 15 are expressed by 1 digit.
This is accomplished by using alphabetic characters following "9", with a carry
occurring after "F", as follows:
A comparison of binary, hexadecimal, and decimal numeric expressions is shown
in Table 4.3 below.
Table 4.3 Comparison of BIN, HEX, and DEC Numeric Expressions
DEC (Decimal)
HEX (Hexadecimal)
BIN (Binary)
0
0
0
1
1
1
2
2
10
3
3
11
•
•
•
•
•
•
•
•
•
9
9
1001
10
A
1010
11
B
1011
12
C
1100
13
D
1101
14
E
1110
15
F
1111
16
10
1
0000
17
11
1
0001
•
•
•
•
•
•
•
•
47
2F
Carry
•
10
1111
(2) Hexadecimal numeric expression
Basic model QCPU registers (data registers, link registers, etc.) consist of 16
bits.
Therefore, as expressed in hexadecimal code, the numeric value range which
can be stored is 0 to FFFFH.
4 - 24
4 - 24
CONDITIONS
MELSEC-Q
4.8.3 BCD (Binary Coded Decimal)
(1) BCD notation
BCD numeric expressions are binary expressions with a carry format identical to
that of the decimal system.
As with the hexadecimal system, BCD expressions are the equivalent of 4 binary
bits, although the BCD system does not use the A to F alphabetic characters.
A comparison of binary, BCD, and decimal numeric expressions is shown in
Table 4.4 below.
Table 4.4 Comparison of BIN, BCD, and DEC Numeric Expressions
DEC (Decimal)
BIN (Binary)
0
BCD
(Binary Coded Decimal)
0
0
1
1
1
2
10
10
3
11
11
4
100
100
5
101
101
6
110
110
7
111
111
8
1000
1000
9
1001
10
1010
1
0000
1001
11
1011
1
0001
12
1100
1
0010
Carry
(2) BCD numeric expression
Basic model QCPU registers (data registers, link registers, etc.) consist of 16
bits.
Therefore, as expressed in BCD code, the range of numeric values to be stored
is 0 to 9999.
4 - 25
4 - 25
CONDITIONS
MELSEC-Q
4.8.4 Real number (floating-point data)
(1) Real number
A real number is a single precision floating-point data.
(2) Internal representation of real number data
The internal representation of real number data handled by the Basic model
QCPU will be described.
Two word devices are used to represent real number data as shown below.
[Sign] 1. [fixed-point part]
[exponent part]
2
When real number data is represented internally, the bit locations and their
meanings are as follows.
b31
b30
b23
b22
b31
Sign
b23 b30
Exponent part (8 bits)
b16
b15
b0
b0 b22
Fixed-point part (23 bits)
• Sign: b31 indicates a sign.
0: Positive
1: Negative
n
• Exponent part: b23 to b30 represent n of 2 . n changes as indicated below
depending on the BIN value in b23 to b30.
b23
b30
n
FFH
FEH FDH
Not used 127
126
81H
80H
7FH
7EH
2
1
0
1
02H
125
01H
00H
126 Not used
• Fixed-point part: 23 bits in b0 to b22 indicate the value XXXXXX... when
1.XXXXXX... is set in binary.
(3) Calculation examples
Calculation examples are given below. ((nnnnnn)x indicates that the data is in X
representation.)
(a) When 10 is stored
(10)10 (1010) 2 (1.01000..... 2 3 ) 2
Sign:
Exponent part:
Fixed-point part:
Positive 0
3 82H (10000010)2
(010 00000 00000 00000 00000)2
Hence, the data is 41200000H as shown below.
Sign
Fixed-point part
Exponent part
0 10000010 01000000000000000000000
4
4 - 26
1
2
0
0
0
0
0
4 - 26
CONDITIONS
MELSEC-Q
(b) When 0.75 is stored
(0.75) 10 (0.11) 2 (1.100....
2 -1 )2
Sign:
Positive 0
Exponent part:
-1 7EH (01111110)2
Fixed-point part:
(100 00000 00000 00000 00000)2
Hence, the data is 3F400000H as shown below.
Sign
Exponent part
Fixed-point part
0 01111110 01000000000000000000000
3
F
4
0
0
0
0
0
POINT
(1) With the monitor function of GX Developer, the real number data of the Basic
model QCPU can be monitored.
However, if an attempt is made to monitor data that cannot be represented in
real number, e.g. "FFFFH", "-" is displayed.
(2) When 0 is represented, b0 to b31 all turn to 0.
REMARK
A binary value below a decimal point is calculated as described below.
0.1
1
-1
Bit representing 2
-1
-2
0
-2
Bit representing 2
1
-3
Bit representing 2
-4
Bit representing 2
-4
(0.1101)2=2 +2 +2 =0.5+0.25+0.125=(0.875)10
4 - 27
4 - 27
CONDITIONS
MELSEC-Q
4.9 Character String Data
(1) Character String Data
The Basic model QCPU uses ASCII code data.
(2) ASCII code character strings
ASCII code character strings are shown in the Table below.
"00H" (NUL code) is used at the end of a character string.
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
(SP)
!
"
#
$
%
&
'
(
)
*
+
0
1
2
3
4
5
6
7
8
9
:
;
@ P
A
Q
B
R
C
S
D
T
E
U
F
V
G W
H
X
I
Y
J
Z
K
[
`
a
b
c
d
e
f
g
h
i
j
k
p
q
r
s
t
u
v
w
x
y
z
{
l
|
m
}
Column
b8
b7
b6
b5
b4
b3
b2
b1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
1
1
0
0
C
Low
NUL
(Comma)
,
<
L
=
M
>
N
(Minus)
1
1
1
1
1
1
0
1
1
1
0
1
D
E
F
-
]
(Period)
.
/
?
O
^
Under
line
_
n
o
POINT
Character strings are available for the $MOV instruction only.
4 - 28
4 - 28
MELSEC-Q
This section describes the necessary information on the I/O number assignment for the
data exchange between Basic model QCPU and input/output modules or intelligent
function modules.
5.1 Relationship Between the Number of Stages and Slots of the Extension Base Unit
5.1.1 Q00JCPU
The Q00JCPU can configure a system with a total of three base units: one main base
unit and two extension base units.
Note that the number of usable slots (modules) is 16 slots including vacant slots.
For example, if you set slot 2 for "vacant, zero points" as shown below, it occupies one
slot.
Hence, the following system uses five slots, slot 0 - slot 4.
QX40
QX40
Empty, 0 points
QY40
QY40
Q00JCPU
0 1 2 3 4
5
1 slot occupied
Install modules to slots 0 - 15.
Installing any module to slot 16 or later will result in an error (SP. UNIT LAY ERR.).
Setting of extension stage
(Refer to Section 5.2)
Slot No.
Q00JCPU
0 1 2 3 4
CPU slot
1
Power supply
5 6 7 8 9 10 11 12
Q68B
Prohibit
Prohibit
2
Power supply
13 14 15
Q65B
Modules cannot be installed.
(Installing modules will result in error.)
5-1
When the GOT has been bus-connected,
one slot of extension base 1 is used.
Also one GOT occupies 16 I/O points.
When using the GOT, consider the number
of slots and the number of I/O points.
Refer to the GOT Manual for details of busconnecting the GOT.
5-1
MELSEC-Q
Power supply
Q00CPU
QX40
QX40
Empty, 0 points
QY40
QY40
The Q00CPU or Q01CPU can configure a system with a total of five base units: one
main base unit and four extension base units, or with one slim type main base unit.
Note that the number of usable slots (modules) is 24 slots including vacant slots.
1 slot occupied
Install modules to slots 0 - 23.
Installing any module to slot 24 or later will result in an error (SP. UNIT LAY ERR.).
Hence, the following system uses five slots, slot 0 - slot 4.
Setting of extension stage
(Refer to Section 5.2)
5
Q00CPU
Power supply
0 1 2 3 4
Slot No.
Q35B
CPU slot
1
Power supply
5 6 7 8 9
Q65B
2
Power supply
10 11 12 13 14
Q65B
3
Power supply
15 16 17 18 19
Q65B
Invalid
4
Power supply
20 21 22 23
Q65B
Module cannot be installed.
(Installing module will result in error.)
5-2
When the GOT has been bus-connected,
one slot of extension base 1 is used.
Also one GOT occupies 16 I/O points.
When using the GOT, consider the number
of slots and the number of I/O points.
Refer to the GOT Manual for details of busconnecting the GOT.
5-2
MELSEC-Q
5.2 Installing Extension Base Units and Setting the Number of Stages
As extension base units, you can use the Q5 B and Q6 B that are designed for
installation of Q series-compatible modules.
There are the following precautions for use of extension base units.
• When the slim type main base unit is used, an extension base unit cannot be
connected.
• The QA1S6 B and QA65B extension base units are unusable.
(1) Setting order of the extension stage numbers for extension base
units
Extension base units require the setting of the extension stage numbers using
the stage setting connector.
Assign the extension stage numbers starting from 1 to 2/4 to the extension base
units counting from the one which is connected to the main base unit.
(2) Cautions to assign extension stage numbers to extension base
units
(a)
Assign consecutive numbers to extension stages.
If you assign stage numbers to base units in "Auto" mode and assign some
stage numbers to no modules, "0" is assigned to the skipped stage as the
number of slots. Consequently, the number of vacant slots does not
increase. The I/O assignment also assigns "0" to the skipped stage as the
I/O points.
(b)
It is impossible to set and use the same extension stage number with two or
more extension base units.
(c)
You cannot use the system if two or more connector pins are inserted to the
stage setting connector.
On the contrary, you cannot use the system if no connector pin is inserted
to the stage setting connector.
Setting of extension
stage
Power supply
Q00CPU
0 1 2 3 4 5 6 7
Stage setting
connector
Q38B
Main base unit
Power supply
8 9 10 11 12 13 14 15
1
Q68B
2
5-3
Power supply
16 17 18 19 20 21 22 23
Q68B
5-3
MELSEC-Q
5.3 Base Unit Assignment (Base Mode)
There are the "Auto mode" and "Detail mode" to assign the number of modules to the
main base unit, slim type main base unit and extension base units.
(1) Auto mode
In Auto mode, base unit assignment is made according to the installable slots of
the main, slim type main and extension base units.
The I/O numbers are assigned according to the number of modules that can be
installed to the used base unit.
Since the AnS series main and extension base units were fixed to eight slots, a
three/five-slot base unit occupied eight slots.
The Basic model QCPU, which occupies only the installable slots of a base unit,
occupies only three slots when a three-slot base unit is used.
(a)
For 3-slot base unit: 3 slots are occupied
Q33B type main base unit
1
2
Q00CPU
Power supply
0
Five slots are not occupied.
Q63B type extension base unit
4
5
Power supply
3
7
8
Power supply
6
5-4
5-4
(b)
MELSEC-Q
For 5-slot base unit/Q00JCPU: 5 slots are occupied
1
2
3
4
Q00CPU
Power supply
0
Three slots are not occupied
6
7
8
9
Power supply
5
Power supply
10 11 12 13 14
(c)
1
2
3
4
5
6
7
Q00CPU
Power supply
0
9 10 11 12 13 14 15
Power supply
8
(d)
1
2
3
4
5
6
7
8
9 10 11
Q00CPU
Power supply
0
Power supply
12 13 14 15 16 17 18 19 20 21 22 23
5-5
5-5
MELSEC-Q
(2) Detail mode
(a)
In Detail mode, the number of slots is assigned to the individual base units
(main base unit, slim type main base unit and extension base units)by
setting the I/O assignment of PLC Parameter.
Use this mode to match the number of slots to the one for the AnS-series
base units (8 fixation).
Since one slot is occupied if an empty slot is set for zero points in I/O
assignment, this mode is also used to make the slot without a module and
later unrecognized.
(b)
Cautions on setting the number of slots
The number of slots can be set regardless of the number of slots of the
module being used.
However, the number of slots must be set for all the base units in use.
If the number of slot is not set for all the base units, I/O assignment may not
work correctly.
The followings result if the preset number of slots differs from that of the
installed base units.
1) When the designated number of slots is larger than that of the installed
base unit:
Among the designated slots, those after the slots occupied by the
installed base unit will be empty slots.
For example, when 8 slots are designated for a 5-slot base unit, 3 slots
will be empty slots.
Empty
Empty
Empty
Power supply
Q00CPU
0 1 2 3 4 5 6 7
Three slots are occupied.
The number of points for the empty slots is the one designated by PLC
system of PLC Parameter or with I/O assignment. (Default value is 16
points.)
2)
When the designated number of slots is smaller than that of the base
unit being used:
The slots other than those designated are disabled.
For example, when 8 slots are designated for a 12-slot base unit, the 4
slots on the right of the base unit are disabled.
(If a module is installed to the disabled slot, an error [SP. UNIT LAY
ERR.] occurs.)
Invalid
Invalid
Invalid
Invalid
Power supply
Q00CPU
0 1 2 3 4 5 6 7 8 9 10 11
Module can be installed.
(When eight slots are set)
5-6
When module is installed,
an error occurs.
5-6
MELSEC-Q
(3) Setting screen and setting items for Base mode of GX Developer
(e)
(a)
5-7
(b)
(c)
(d)
(a)
Base model name
Designate the model name of the installed base unit with 16 or less
characters. Basic model QCPU does not use the designated model name.
(It is used as a user's memo or parameter printing)
(b)
Power model name
Designate the model name of the installed power supply module with 16 or
less characters. Basic model QCPU does not use the designated model
name. (It is used as a user's memo or parameter printing)
(c)
Increase cable name
Designate the model name of the extension cable being used with 16 or
less characters. Basic model QCPU does not use the designated model
name. (It is used as a user's memo or parameter printing)
(d)
Points (Used with Basic model QCPU)
Select the number of points for the slot of the base unit being used from the
followings:
• 2 (2 slots)
• 3 (3 slots)
• 5 (5 slots)
• 8 (8 slots)
• 10 (10 slots)
• 12 (12 slots)
(e)
8 fixation/12 fixation (Used with Basic model QCPU)
Select either option to designate the number of slots for all base units to the
same number.
5-7
MELSEC-Q
5.4 What are I/O Numbers?
I/O numbers are used in sequence program for reception of ON/OFF data at Basic
model QCPU and output of ON/OFF data from Basic model QCPU to outsides.
Input (X) is used for the reception of ON/OFF data at Basic model QCPU. Output (Y)
is used for the output of ON/OFF data from Basic model QCPU.
I/O numbers are expressed as hexadecimals.
When using 16-point I/O modules, I/O numbers are consecutive numbers that 1 slot
has 16 points
0 to
F as follows.
The module that is mounted in the base unit assigns the following:
• For the input module, "X" is assigned at the beginning of the I/O number.
• For the output module, "Y" is assigned at the beginning of the I/O number.
For the case of input module
Power
supply
module
Q00CPU
For the case of output module
X 0 0 0 X 0 1 0 X 0 2 0 Y 0 3 0 Y 0 4 0
X2C
X 0 0 F X 0 1 F X 0 2 F Y 0 3 F Y 0 4 F
16 input 16 input 16 input 16 output 16 output
points
points
points
points
points
5-8
5-8
MELSEC-Q
5.5 Concept of I/O Number Assignment
5.5.1 I/O numbers of main base unit, slim type main base unit and extension base unit
Basic model QCPU assigns I/O numbers at power-on or reset according to the
following items.
As a result, you can control Basic model QCPU without using GX Developer for I/O
assignment.
To assign I/O numbers, follow the items below:
(1) Number of slots of base units
The number of slots of the main base unit, slim type main base unit and
extension base units changes depending on the Base mode setting. (For Base
mode, refer to Section 5.3.)
(a) In Auto mode, the number of slots is determined as the available number of
modules installed to each base unit.
For example, 5 slots are assigned for a 5-slot base unit, and 12 slots are
assigned for a 12-slot base unit.
(b)
In Detail mode, the number of slots is determined as the one designated by
I/O assignment of PLC Parameter.
(2) Order of I/O number assignment
The I/O numbers are assigned from left to right consecutively, starting from 0H
assigned to the module mounted on the right of the Basic model QCPU on the
main base unit or slim type main base unit.
(3) Order of I/O number assignment for extension base units
The I/O numbers for extension base units are assigned continuing from the last
number of the I/O number of the main base unit.
The I/O numbers for extension base units are assigned to the units from left (silkscreened I/O 0 of extension base unit) to right consecutively, in the order of the
setting of the stage setting connectors of the extension base units.
(4) I/O numbers of each slot
Each slot of base units occupies the points of I/O numbers of the installed I/O
modules or intelligent function modules.
When 32-point input module is installed on the right of Basic model QCPU, X0 to
X1F are assigned as I/O numbers.
(5) I/O numbers of empty slots
If the base unit has vacant slots where no I/O modules or no intelligent function
modules are installed, the points designated by PLC system setting of PLC
Parameter are assigned to the empty slots. (Default value is 16 points.)
POINT
When the assignment of base units is conducted in Auto mode, the number of
empty extension stages is not assured even if the extension stage is skipped at the
stage number setting connector of the base unit. (Smaller input/output numbers are
assigned first.)
To reverse empty extension stages for future extension, use the PLC parameter to
set the base unit.
5-9
5-9
MELSEC-Q
The following shows the example of the I/O number assignment when the base unit is
set in Auto mode without I/O assignment:
0
1
2
3
4 ............. Slot No.
Input module
Input module
Input module
Output module
Output module
Power supply module
Q00CPU
Q35B (5 slots occupied)
16
16
32
16
64
points points points points points
X3F
Y4F
5
6
7
8
9
Intelligent
function module
Output module
Empty
Y40
Intelligent
function module
X20
X0F X1F
1
IN OUT
Power supply module
Y50
Y8F
the I/O points of each slot
......... I/O numbering direction
The slot numbers of the 1st stage's extension
base unit continue from the last slot number
of the main base unit.
Empty slot points designated on the PLC system
Setting screen under the parameter mode are
allocated. (Default: 16 points)
32
32
32
16
16
points points points points points
YF0
100
AF
CF
EF
YFF
10F
10
11
12
13
14
15
16
17
Intelligent
function module
Intelligent
function module
Output module
Output module
Output module
2
IN OUT
Power supply module
D0
Input module
B0
Input module
90
Intelligent
function module
Extension
cable
X10
Intelligent
function module
X00
Allocate the I/O number with
The slot numbers of the 2nd stage's extension
base unit continue from the last slot number of
the 1st stage's extension base unit.
16
16
32
32
32
16
16
16
points points points points points points points points
X110 X120 130
150
170 Y190 Y1A0 Y1B0
X11F X12F 14F
16F
18F Y19F Y1AF Y1BF
POINT
The above example shows the case where the intelligent function module has 32
I/O points.
The number of I/O points may vary depending on the intelligent function module.
Refer to the manual of the intelligent function module being used and check the
number of the I/O points before assigning the I/O numbers.
5 - 10
5 - 10
MELSEC-Q
5.5.2 Remote station I/O number
Q64AD
QX41
QY41
QJ71LP21
QJ61BT11
Q00CPU
Power module
In a CC-Link remote I/O system, you can exercise control after assigning the inputs (X)
and outputs (Y) of the Basic model QCPU devices to the I/O and intelligent function
modules of remote stations.
Also, the inputs (X) and outputs (Y) are used as the refresh destinations (Basic model
QCPU side devices) of the link inputs and outputs (LX, LY) of the MELSECNET/H.
Take care not to overlap the I/O numbers of the MELSECNET/H refresh destinations
and the I/O numbers of the CC-Link remote I/O system.
Remote
station
Remote
station
Allocation of
Q00CPU input (X) and
output (Y) possible
CC-Link
When using Basic model QCPU device input (X) and output (Y) in remote stations, I/O
numbers that succeed the numbers used by the main base unit and extension base
units' input/output modules and intelligent function modules will be allocated.
For example, if X/Y0 to X/YFF are being used by the main base unit and extension
base units' input/output modules and intelligent function modules, then numbers above
X/Y100 can be used by the remote station.
However, the I/O numbers for remote stations should be set in consideration of
additions to the main base unit and extension base units' input/output modules and
(Example) If 256 points from X/Y0 to X/YFF are being used by the main base unit and
extension base units, and 256 points from X/Y100 to X/Y1FF are to be held back for
use with future additions, then the situation shown in the diagram below is to be
observed.
Input/Output (X/Y)
X/Y0
I/O numbers being used by the main base unit and
extension base units
to
X/YFF
X/Y100
to
Held back for future additions
X/Y1FF
X/Y200
For CC-Link remote
station
I/O numbers that can be used by remote stations
to
X/Y7FF
POINT
If network parameter setting has not been made in a CC-Link system, 1024 points
of X/Y400 to X/Y7FF are assigned to the CC-Link master/local module of lower I/O
numbers.
5 - 11
5 - 11
MELSEC-Q
5.6 I/O Assignment by GX Developer
This section describes the I/O assignment using GX Developer.
5.6.1 Purpose of I/O assignment by GX Developer
I/O assignment by GX Developer is used under the following circumstances.
(1) Reserving points when converting to module other than 16-point
modules
You can reserve the number of points in advance so that you do not have to
change the I/O numbers when the current module will be changed to one with a
different number of I/O points in the future.
For example, you can assign a 32-point I/O module to the slot where a 16-point
I/O module is installed at present.
(2) Preventing I/O numbers from changing when converting modules
You can avoid the change in the I/O numbers when an I/O module other than 16point module or intelligent function module is removed due to a malfunction.
(3) Changing the I/O numbers to those used in the program
When the designed programs I/O numbers are different from the actual system
I/O numbers, each modules I/O numbers of base units can be set to program-I/O
numbers.
(4) Setting the input response time of input modules and interrupt
modules (I/O response time)
The input response time of the input modules and interrupt modules can be
changed to match it to the system. (For details, refer to Section 7.7.)
(5) Setting the switch of intelligent function modules
Set the operation conditions of the intelligent function modules. (For details, refer
to Section 7.10.)
(6) Setting outputs during Basic model QCPU error
Set the output (retain/clear) status of the output modules and intelligent modules
when the Basic model QCPU stops the operation due to a stop error.
(For details, refer to Section 7.8.)
(7) Setting Basic model QCPU operation during a hardware error of
Set the operation (continue/stop) status of the Basic model QCPU if a hardware
error occurs in an intelligent function module. (For details, refer to Section 7.9.)
POINT
(1) The I/O assignment setting of the PLC parameters are made valid when the
PLC is powered on or the Basic model QCPU is reset.
When you have changed the PLC parameter values, power on the PLC again or
reset the Basic model QCPU.
(2) I/O assignment must be made to change the response time of the input module
or make the switch setting of the intelligent function module.
(3) If any of the I/O modules other than the 16-point modules fails without I/O
assignment being made using GX Developer, the I/O numbers after that module
may change, leading to a malfunction. Therefore, it is recommended to make
I/O assignment using GX Developer.
5 - 12
5 - 12
MELSEC-Q
5.6.2 Concept of I/O assignment using GX Developer
(1) I/O assignment for each slot
You can designate "Type" (module type), "Points" (number of I/O points), and
"Start XY" (head I/O number) individually for each slot of the base unit.
For example, to change the number of I/O points of the designated slot, you can
designate only the number of I/O points.
The items other than designated are set to the status where the base unit is installed.
The I/O assignment is conducted according to the I/O assignment setting of PLC
Parameter.
(a)
5 - 13
(b)
(c)
(d)
(e)
(a)
Slot
Displays the slot No. and the ordinal position of the slot in the base unit.
If the base unit is not designated in Detail mode, the stage number of the
base unit is shown as " ", and the ordinal number of a slot is counted
from slot 0 of the main base unit.
(b)
Type (Used with Basic model QCPU)
Select the type of module being installed from the followings:
• Empty (Empty slot)
• Input (Input module)
• Hi Input (Q series corresponding high speed module)
• Output (Output module)
• I/O Mix (I/O mixed module)
• Intelligent (Intelligent function module)
• Interrupt (Q series corresponding interruption module)
If the type is not designated, the type of the actually installed module is used.
5 - 13
MELSEC-Q
(c)
Model name
Designate the model name of the installed module with 16 or less
characters. Basic model QCPU does not use the designated model name. (It
is used as a user's memo or for parameter printing.)
(d)
Points (Used with Basic model QCPU)
To change the number of I/O points of each slot, select it from the
followings:
• 0 (0 point)
• 128 (128 points)
• 16 (16 points)
• 256 (256 points)
• 32 (32 points)
• 512 (512 points)
• 48 (48 points)
• 1024 (1024 points)
• 64 (64 points)
If the number of I/O points is not designated for a slot, the one of the
actually installed module is used.
: Setting is enabled for the Q00/Q01CPU only.
(Since the number of I/O points of the Q00JCPU is 256, you cannot set
512/1024 points.)
(e)
Start XY (Used with Basic model QCPU)
1) When the I/O number of each slot is changed, you should designate
the head I/O number according to the change.
If Start XY is not designated for a slot, the I/O number continuing from
the last number of the currently designated slot is assigned.
2)
Avoid the I/O number designation of each slot from overlapping the I/O
numbers assigned by Basic model QCPU.
An error (SP. UNIT LAY ERR.) occurs when the I/O numbers overlap.
(2) Slot status after I/O assignment
When the I/O number is assigned to a slot, the assigned I/O number takes
precedence regardless of the actual installation of a module.
(a) If the designated number of I/O points is smaller than that of the actually
installed input/output module, some I/O points of the installed module are
not used.
For example, if a slot where a 32-point input module is installed is
designated for a 16-point input module, the latter 16 points of the 32-point
input module are disabled.
(b)
(c)
(d)
5 - 14
"SP. UNIT LAY ERR." occurs if the number of points set is less than the
number of points of the installed intelligent function modules.
If the specified number of I/O points is larger than that of the actually
installed input/output modules, the points exceeding the actual points are
regarded as dummies.
The module type of the installed module must be consistent with that of the
I/O assignment.
Inconsistent I/O assignment may result in malfunctions.
5 - 14
Actually installed module
Input module
Output module
Input module/output module
Vacant slot
(e)
5 - 15
MELSEC-Q
I/O assignment
Result
Output/Empty
Empty
Input/Empty
Empty
Intelligent
Error (SP. UNIT LAY ERR.)
Empty
Empty
Input/output
Error (SP. UNIT LAY ERR.)
Intelligent
No error occurs.
Be sure to assign the I/O numbers so that the last I/O number is within the
range of FFH/3FFH or less. An error (SP. UNIT LAY ERR.) occurs when the
last I/O number exceeds FFH/3FFH. (System monitor of GX Developer
" as an I/O address.)
shows "
5 - 15
MELSEC-Q
5.7 Examples of I/O Number Assignment
This section shows the examples of the I/O number assignment using GX Developer.
(1) When changing the number of points of an empty slot from 16 to 32
points:
Reserve 32 points to the slot position currently empty (slot No. 3) so that the
input/output numbers do not change when a 32-point input module is installed in
the future. (The empty slot for slot No. 12 is not changed from 16 points.) 1
(a)
System configuration and I/O number assignment before the I/O
assignment with GX Developer
2
6
7
Output module
5
Output module
4
Output module
3
Empty
2
Input module
1
Input module
Input module
Q00CPU
Power supply module
0
Output module
Q38B
32
32
32
16
32
32
32
32
X20
X40
60
Y70 Y90
X1F X3F
X5F
6F
Y8F YAF YCF YEF
10
11
12
13
14
15
Intelligent
function module
Intelligent
function module
Empty
Output module
Output module
Output module
X00
YB0 YD0
9
Intelligent
function module
IN OUT
8
Intelligent
function module
1
Power supply module
Q68B
32
32
32
32
16
32
32
32
F0 110 130 150 170 Y180 Y1A0 Y1C0
10F
12F
14F
16F
17F Y19F Y1BF Y1DF
REMARK
1: This is the case where the number of points for an empty slot is set to 16 with
PLC system setting of PLC Parameter.
2: Since the number of I/O points of the Q00JCPU is 256, use it within the range
X/Y0 to X/YFF.
5 - 16
5 - 16
(b)
MELSEC-Q
I/O assignment with GX Developer
Designate slot No. 3 to "32 points" on the I/O assignment screen of GX
Developer.
Select 32 points.
(When the type is not selected,
the type of the installed module
will be selected.)
(c)
I/O number assignment after the I/O assignment with GX Developer
6
7
Output module
5
Output module
4
Output module
3
Output module
Input module
2
Empty
1
Input module
0
Input module
Q00CPU
X5F
7F
Y9F YBF YDF YFF
12
13
14
15
Output module
Output module
X1F X3F
Output module
32
32
32
32
32
32
32
32
X00 X20 X40 60
Y80 YA0 YC0 YE0
Empty
Power supply module
Q38B
9
10
11
Intelligent
function module
Intelligent
function module
Intelligent
function module
IN OUT
8
Intelligent
function module
1
Power supply module
Q68B
32
32
32
32
16
32
32
32
100 120 140 160 180 Y190 Y1B0 Y1D0
11F
5 - 17
13F
15F
17F
18F Y1AF Y1CF Y1EF
5 - 17
MELSEC-Q
(2) Changing the I/O number of slots
Change the I/O number of a currently vacant slot (slot No. 3) to X200 through
X21F so that the I/O numbers of slot No. 4 and later slots do not change when a
32-point input module is installed to the currently vacant slot (slot No. 3). 3
(a)
System configuration and I/O number assignment before the I/O
assignment with GX Developer
6
7
Output module
5
Output module
4
Output module
3
Output module
Input module
2
Empty
1
Input module
0
Input module
Q00CPU
X5F
6F
Y8F YAF YCF YEF
12
13
14
15
Output module
Output module
X1F X3F
Output module
16
32
32
32
32
32
32
32
Y70 Y90 YB0 YD0
X00 X20 X40 60
Empty
Power supply module
Q38B
9
10
11
Intelligent
function module
Intelligent
function module
Intelligent
function module
IN OUT
8
Intelligent
function module
1
Power supply module
Q68B
32
32
32
32
16
32
32
32
F0 110 130 150 170 Y180 Y1A0 Y1C0
10F
12F
14F
16F
17F Y19F Y1BF Y1DF
REMARK
3: Since the number of I/O points of the Q00JCPU is 256, use it within the range
X/Y0 to X/YFF.
5 - 18
5 - 18
(b)
MELSEC-Q
I/O assignment with GX Developer
Designate the head I/O number of slot No. 3 to "200" and that of slot No. 4
to "70" on the I/O assignment screen of GX Developer.
"200" is designated as the
head I/O number.
"70" is designated as the head
I/O number.
(When the head I/O number
is not designated, the I/O
number following the 3rd slot
will be assigned.)
(c)
I/O number assignment after the I/O assignment with GX Developer
5
Output module
6
7
Output module
4
Output module
3
Output module
2
Input module
1
Input module
Input module
Q00CPU
X20
X40
X200 Y70 Y90
X1F X3F
X5F
X21F Y8F YAF YCF YEF
12
13
14
15
Output module
Output module
Output module
32
32
32
32
32
32
32
32
Empty
Power supply module
0
Input module
Q38B
X00
YB0 YD0
9
10
11
Intelligent
function module
Intelligent
function module
Intelligent
function module
IN OUT
8
Intelligent
function module
1
Power supply module
Q68B
32
32
32
32
16
32
32
32
F0
110
130
150
170 Y180 Y1A0 Y1C0
10F
12F
14F
16F
17F Y19F Y1BF Y1DF
5.8 Checking the I/O Numbers
System monitor of GX Developer allows the check of the installed modules of Basic
model QCPU and their I/O numbers. (For system monitor, refer to Section 7.18.)
5 - 19
5 - 19
MELSEC-Q
(1) Data handled by Basic model QCPU
The Basic model QCPU stores such data as parameter, program and device
comments into program memory.
When ROM operation is performed, the parameter and program in the program
memory are written to standard ROM.
(2) Write of parameter and program using GX Developer
Such data as parameter, program and comment are written to the program
memory of the Basic model QCPU by GX Developer (online write to PLC).
For online write to PLC, specify the type (e.g. parameter, program, comment) of
the data to be written to the Basic model QCPU.
6
6-1
6-1
MELSEC-Q
6.1 About Basic model QCPU's Memory
(1) User Memory
A user memory can be created within the memory of the Basic model QCPU with
GX Developer/sequence program.
There are the following user memories.
• Program memory
• Standard ROM
• Standard RAM
CPU shared memory (refer to Section 16.4)
: Q00CPU, Q01CPU only
(a) Program memory
This memory stores program used by the Basic model QCPU to actually
perform arithmetic operation.
Program stored in the standard ROM is booted (read) into the program
memory for arithmetic operation. (Boot operation)
(b) Standard ROM
Parameter and program are stored in the standard ROM. These data are
used for ROM operation of the Basic model QCPU.
The parameter and program are batch-copied from the program memory to
the standard ROM. (ROMed program memory)
(c) Standard RAM
This memory stores file register data.
The file registers of the standard RAM allow fast access like the data
registers.
(2) Types of Data Stored in the Basic model QCPU Memory
The table below shows the type of data stored in a program memory, standard
RAM, and standard ROM.
Q00JCPU Built-In
Data Name
Q00/Q01CPU Built-In
Program
Standard
Program
Standard
Standard
Memory
ROM
Memory
RAM
ROM
PARAM.QPA
Parameter
IPARAM.QPA
parameter
Sequence program
SFC program
4
1
4
1
MAIN.QPG
4
1
4
1
MAIN-SFC.QPG
3
File register
Device comment
2
2
MAIN.QDR
2
2
MAIN.QCD
MAIN.QDI
: Needed,
6-2
File name
: Stored,
: Not stored
6-2
6
MELSEC-Q
REMARK
1: To execute a program actually, booting must be specified for the program
memory using the PLC parameter.
2: Data can be written with GX Developer. Device comments cannot be used in an
instruction of a sequence program.
3: The standard RAM can store only one file of 64k points of file registers.
4: The data of either the sequence program or SFC program is required.
(3) Drive Number
(a)
The Basic model QCPU uses drive numbers to control program memory,
standard RAM and standard ROM.
On GX Developer, however, specify the target memory (program memory,
standard RAM, standard ROM) to write/read the parameter, program, etc.
to/from the Basic model QCPU.
(b)
The table below shows the drive numbers used to specify a selected
memory (program memory, standard RAM or standard ROM) when using a
sequence program. The drive number must be used to specify a selected
memory when the read/write is made through access from a serial
communication module.
Memory
QCPU built-in
Drive Number
Program memory
0
Standard RAM
3
Standard ROM
4
(4) Memory Capacity and Formatting
The table below shows the size of a memory of the Basic model QCPU and
whether to format a memory.
Q00JCPU
Standard RAM
None
Q00CPU
Q01CPU
128k byte
Program memory
58k byte
94k byte
94k byte
Standard ROM
58k byte
94k byte
94k byte
Whether to Format
Not required.
5
Not required.
5
Not required.
5: Before using the Basic model QCPU, always format the memory using GX
Developer.
6-3
6-3
MELSEC-Q
6.2 About Program Memory
(1) What is the Program Memory?
(a)
The program memory is an internal RAM that stores program executed by
the Basic model QCPU.
(b)
The data storage in the program memory is backed up by Basic model
QCPU's built-in battery (Q6BAT).
(c)
Before using the Basic model QCPU, always format the memory using GX
Developer. 1
(However, if the memory is in an initial status or has been unformatted due
to battery (Q6BAT) exhaustion, the Basic model QCPU does formatting
automatically at power-on or reset of the PLC.
For details regarding the formatting procedure by the GX Developer, refer
to GX Developer manuals.
Table 6.1 Memory capacity after formatting
1
Model Name
Memory
Max. Number of Program Stored
Q00JCPU
58 kbyte
2
2
Q00CPU
94 kbyte
2
2
Q01CPU
94 kbyte
2
2
POINT
Program is stored in the program memory in 4 bytes units.
(2) Data Storage
Data on parameter and program can be stored in the program memory. For the
types of data stored in the program memory, see Section 6.1.
REMARK
1: When the program memory is formatted by GX Developer, the user setting area
and multi-block write during RUN area in the system area can also assigned.
(0-3k steps can be set to the user setting area of the system area in 1k step
increments.)
The user setting area (data) in the system area is used for registering monitor
data from GX Developer connected to serial communication module.
Presetting the user setting area of the system area enables fast monitoring from
GX Developer connected to the serial communication module, etc.
Although the designation of a user setting area speeds up monitoring from GX
Developer connected to serial communication module, it also reduces the
amount of space available for user files.
2: One sequence program and one SFC program can be stored.
6-4
6-4
MELSEC-Q
6.3 About Standard ROM
(1) What is the standard ROM?
(a)
The standard ROM is used for the ROM operation of the Basic model
QCPU.
(b)
Program stored in the standard ROM and booted (read) to the program
memory after the setting is made in the Boot File sheet of the PLC
Parameter dialog box.
(c)
Write to the standard ROM is performed by "Write the program memory to
ROM" in online write to PLC (flash ROM) of GX Developer. (Refer to
Section 6.4.2)
POINTS
Writing program memory to ROM copies the program memory data to the standard
ROM as-is.
(2) Data Storage
A standard ROM stores data such as parameter and program.
See Section 6.1 for the data to store in the standard ROM.
(3) Setting of ROM operation
When performing ROM operation, select "boot operation from standard ROM" in
the boot file setting of PLC parameter.
6-5
6-5
MELSEC-Q
6.4 Executing Standard ROM Program (Boot Run) and Writing Program Memory to ROM
6.4.1 Executing Standard ROM Program
(1) Executing Basic model QCPU program
(a)
The Basic model QCPU processes program which is stored in the program
memory.
The Basic model QCPU does not perform operation of program stored in
the standard ROM.
(b)
The program stored in the standard ROM is booted (read) to the program
memory to perform arithmetic operation.
(2) Preparation for Boot Run
Perform the following steps in preparation for boot run:
(a) Create a program using GX Developer.
Create a program used for the boot run.
6-6
(b)
Select a boot file using GX Developer.
Select "Do boot from standard ROM" in the boot file setting of PLC
parameter.
(c)
Write of parameter, program and like to standard ROM using GX Developer
1) Using online "write to PLC" of GX Developer, write parameter and
program to the program memory.
2) Write the parameter and program in the program memory to the
standard ROM by ROMing the program memory.
Refer to Section 6.4.2 for write of parameter, program and the like to
the standard ROM using GX Developer.
6-6
(d)
MELSEC-Q
Execute a program.
Resetting the Basic model QCPU with the RUN/STOP/RESET switch starts
boot from the standard ROM.
Refer to the following manuals for the reset operation of the Basic model
QCPU.
• QCPU (Q Mode) User's Manual (Hardware)
• Basic Model QCPU (Q Mode) User's Manual (Hardware Design,
Maintenance and Inspection)
(3) Operation for Stopping Boot Run
When stopping boot run, perform the following operation.
1) Format the program memory.
2) ROM the program memory.
(The parameter and sequence program in the standard ROM are
erased.)
3) Write the parameter and sequence program to the program memory.
(4) Precautions for Executing Program in the Standard ROM
6-7
(a)
When performing boot run, store the following files into the standard ROM.
• Parameter 1
• Intelligent function module parameter
• Sequence program 2
• SFC program 2
• Device comment
• Device initial value
1: Required
2: Either one sequence program or one SFC program is required.
(b)
If program is written in the program memory during the RUN status while a
boot run is performed by using a standard ROM, any change made will not
be reflected in program stored in the standard ROM.
(c)
If the PLC is powered ON/reset after writing sequence program to the
program memory, the contents of the program memory may change.
This can be caused when the boot run has been set.
1) Format the program memory.
2) Write the parameter and sequence program to the program memory.
3) Transfer the parameter written in the program memory to the ROM.
6-7
MELSEC-Q
6.4.2 Write program memory to ROM
To perform write to the standard ROM with GX Developer, perform "Write the program
memory to ROM" in online Write to PLC (Flash ROM) of GX Developer.
Files cannot be written to the standard ROM by online "Write to PLC" of GX Developer.
(1) Write the program memory to ROM
6-8
(a)
The "Write the program memory to ROM" function allows a batch of files
stored in a program memory to be written in a standard ROM.
Refer to Section 12.1 for the procedure of writing the program memory to
ROM.
This function writes the debugged program stored in the program memory
to ROM.
(b)
When the "Write a memory to ROM" function is executed, all files stored in
the standard ROM are erased before a batch of files stored in a program
memory are written. No files can be added to the standard ROM.
(c)
The memory capacity of a standard ROM is the same as that of a program
memory. A memory of a larger size than the memory capacity of a program
memory cannot be used.
(d)
For write of the program memory to ROM by GX Developer, check is made
in 180 seconds when the time check period of GX Developer is 180
seconds or shorter. To execute the "Write the program memory to ROM"
function via the CC-Link network by operating from a GX Developer at a
local station, set the length of CC-Link's CPU monitoring time (SW0A) to
180 seconds or longer.
6-8
MELSEC-Q
6.5 About Standard RAM
(1) What is the standard RAM?
(a)
The standard RAM is used when using file registers. (Q00CPU, Q01CPU
only)
(b)
The standard RAM data are backed up by the battery (Q6BAT) fitted to the
CPU module.
Even if ROM operation is to be performed with a program written to the
standard ROM, the battery is needed when the standard RAM is used by
the file registers.
(c)
Data can be written onto the standard RAM by using the online function:
"Write to PLC."
(2) Stored Data
A standard RAM holds one file: file register file. Any other files cannot be written
onto a standard RAM.
6-9
6-9
MELSEC-Q
6.6 Program File Configuration
(1) Program File Configuration
(a)
Program files consist of a file header and an execution program.
File header
34 steps
(by default)
Areas are reserved
in units of 4 bytes
Execution program
Steps secured
for write during RUN
(b)
500 steps
When a program file is stored into the program memory of the Basic model
QCPU, the program capacity is a total of the above three different areas.
1) File header: The file name, file size, and file creation data, etc., are
stored in this area.
The file header size is 25 to 35 steps (100 to 140 bytes), which
changes depending on the device setting of the PLC parameter dialog
box.
(Default:34steps)
2)
Execution program: The created program is stored in this area.
1 step is 4 bytes.
3)
Steps secured for write during RUN: This area is used when write
during RUN that will increase the number of steps is performed by GX
Developer.
When write during RUN that will increase the number of steps is
performed by GX Developer, the number of remaining steps in the
steps secured for write during RUN is displayed.
The default setting is 500 steps (2000 bytes).
The number of steps secured for write during RUN can be changed by
GX Developer (program for online write to PLC).
If the number of steps secured for write during RUN is insufficient for
write during RUN, the number of steps secured for write during RUN
can be set again. (Refer to Section 7.11.1)
(2) The size of the program displayed by GX Developer
During programming at the GX Developer, the program size (the total of the file
header size and the number of created program steps) is displayed as the
number of steps as shown below.
During programming, the size of the program created is displayed.
"Number of steps used" display
6 - 10
6 - 10
MELSEC-Q
6.7 GX Developer File Operation and File Handling Precautions
6.7.1 File operation
Using the "online" function of the GX Developer, the file operations shown in Table 6.5
below are possible with regard to files stored in the program memory and standard
ROM.
However the available file operations will vary according to the presence or absence of
a password (registered by GX Developer) and the Basic model QCPU RUN/STOP
status.
Table 6.5 File Operations from GX Developer
Operation
File Operation
Operation Description
Enabled/Disabled
A
B
C
Read from PLC
Files are read from target memory.
Write to PLC
Files are written to the program memory.
Verify the target memory and the GX Developer's
Verify with PLC
file.
Write the program
Write a batch of files from the program memory
memory to ROM
to the standard ROM.
Delete PLC data
A file stored in memory is deleted.
Format PLC memory
Memory formatting is executed.
Memory files which ate no longer contiguous are
Arrange PLC memory
re-organized to make them contiguous.
Write during RUN in
Write changes made in the ladder mode into the
the ladder mode
program memory.
: Execution enabled,
: Execution enabled on password match,
: Execution disabled
REMARK
1) The codes used at the "operation enabled/disabled" item in the above table are
explained below.
Table 6.6 Operation enabled/disabled
Code
6 - 11
Description
A
When "write prohibit" password is registered in a file
B
When "read/write prohibit" password is registered in a file
C
When Basic model QCPU RUN status is in effect
6 - 11
MELSEC-Q
6.7.2 File handling precautions
(1) Power OFF (or reset) during program operation
(a)
If power is switched off during any file operation that will not cause a file
shift, the memory data will be indefinite.
(b)
When the battery (Q6BAT) is used for backup on the Basic model QCPU,
switching power off during any of the following operations that will cause a
file shift will make the program memory data indefinite.
• File size change
• Arrange PLC memory
• New file creation
(2) Simultaneous write to the same file from multiple GX Developers
The Basic model QCPU does not allow access from other GX Developers to the
file being written.
It does not allow write from other GX Developers to the file being accessed,
either.
Therefore, to perform write from multiple GX Developers to the same file, start
the processing of next GX Developer after completing the current processing.
(3) Simultaneous access to different files from multiple GX Developers
The Basic model QCPU allows simultaneous access from multiple GX
Developers to up to 10 different files of the same CPU module.
6 - 12
6 - 12
MELSEC-Q
6.7.3 File capacity
The file size differs with the types of files used. When a program memory, standard
RAM and standard ROM are used, calculate the size of a file with reference to the
table 6.7 shown below.
Space for file storage is available as shown below:
• Program memory, standard ROM: 4 bytes
Table 6.7 List of File Size
Function
Drive header
Estimated File Size (in byte)
64
Default: 522 (increased by the parameter setting)
For Reference:
Boot setting to 96
Parameter
With the MELSECNET/H : Increased to up to 4096
With Ethernet setting : Maximum 922
With CC-Link setting : Increased to up to 251/module
With remote password setting : 64 + 20 (No. of modules
Sequence program
136
+ (4
10), increased up to 164
((number of steps) + (number of steps secured for write during RUN))
74 + (Total of comment data size of each device)
• Comment data size of a device = 10 + 10250
Device comment
a + 40
b
• a: quotient of (Number of device points) / 256
• b: remainder of (Number of device points) / 256
File register
2
(Number of file register points)
66 + 44 n + 2 (total number of device points set for device initial value)
• n: Number of device initial value settings
Intelligent parameter
68 + (24 number of set modules) + parameter size of each utility
User setting area
Set value at the time of formatting (0 to 3k)
Multi-block write during
RUN setting
Set value at the time of formatting (0/1.25k/2.5k)
*: 136 is the default (increased by the parameter setting).
6 - 13
6 - 13
MELSEC-Q
An example for calculating the amount of memory capacity required when writing the
parameter and sequence program in the program memory is shown below.
(1) Writing file
File name
Program capacity
parameter
—
sequence program
5000 steps (20000 bytes)
Represents the program capacity displayed with the GX Developer (total number of
file headers and created program steps.) (See Section 6.6.)
(2) Writing conditions
Parameter: Default setting (522 bytes)
Steps secured for write during RUN: 500 steps (2000 bytes)
(3) File memory capacity calculations
File name
Parameter
Sequence
program
File capacity
Memory capacity
522 bytes
522 bytes
Sequence program capacity
20,000 bytes
Steps secured for write during RUN
2000 bytes
File memory capacity total
20,000 bytes
22,522 bytes
A program memory capacity in units of 4 bytes (1 step) is secured.
6 - 14
6 - 14
7 FUNCTION
MELSEC-Q
7 FUNCTION
Function of Basic model QCPU module is as follows:
7.1 Function List
Functions of Basic model QCPU are listed below:
Item
Description
Reference
Constant scan
Function to make the scan time constant.
Section 7.2
Latch function
Function to maintain the device data when performing the reset operation during power off.
Section 7.3
This function selects the output (Y) status (re-output of status before STOP/output of status after
Selection of output status at switching
execution of operation) when the Basic model QCPU is switched from the STOP status to the RUN
from STOP to RUN
status.
Section 7.4
Clock function
Function to execute the Basic model QCPU internal clock.
Section 7.5
Remote operation
Function to operate the Basic model QCPU from a remote place.
Remote RUN/STOP
7
Function to stop and start operating the Basic model QCPU.
Section 7.6
Section 7.6.1
Remote PAUSE
Function to temporarily stop the Basic model QCPU.
Section 7.6.2
Remote RESET
Function to reset the Basic model QCPU.
Section 7.6.3
Remote latch clear
Function to clear the Basic model QCPU latch data.
Section 7.6.4
Selection of input response time of
input module/hybrid I/O module
This function selects the response time of input module/hybrid I/O module from among 1ms, 5ms,
10ms, 20ms and 70ms. (Default: 10ms)
Section 7.7.1
high-speed input module
This function changes the response time of the high-speed input module to any of 0.1ms, 0.2ms,
0.4ms, 0.6ms and 1ms. (Default: 0.2ms)
Section 7.7.2
interrupt module
This function changes the response time of the interrupt module to any of 0.1ms, 0.2ms, 0.4ms,
0.6ms and 1ms. (Default: 0.2ms)
Section 7.7.3
Error-time output mode setting
This function sets whether the output to the output module, hybrid I/O module or intelligent function
module will be cleared or held when the CPU module results in a stop error.
Section 7.8
Hardware error-time CPU operation
mode setting
This function sets whether the operation of the CPU module will be stopped or continued when the
hardware error of the intelligent function module occurs.
Section 7.9
Setting of intelligent function module
switches
This function makes various settings of an intelligent function module.
(Refer to the corresponding intelligent function module for settings.)
Section 7.10
Write during RUN
This function writes program when the Basic model QCPU is in the RUN status.
Section 7.11
Multiple-user debugging function
This function performs debugging from multiple GX Developers simultaneously.
Section 7.12
Watchdog timer
This function monitors operational delays caused by Basic model QCPU's hardware and program
errors.
Section 7.13
Self-Diagnosis function
This function enables the Basic model QCPU to check for failures.
Section 7.14
Failure history
This function stores a failure history of diagnosis results in the memory.
Section 7.15
System protect
This function prevents the program from being altered by the GX Developer communication
module.
Section 7.16
Password registration
This function provides read/write protection for files stored in the Basic model QCPU against
access from the GX Developer.
Section 7.16.1
Remote password
This function prevents illegal external access in the serial communication module and Ethernet
module.
Section 7.16.2
System display
This function connects to the GX Developer and monitors system configuration.
Section 7.17
LED display
This function enables the front-mounted LEDs to indicate the operating conditions of the Basic
model QCPU.
Section 7.18
Serial communication function
This function makes communication in the MC protocol with the RS-232 interface of the Q00CPU/
Q01CPU connected with a personal computer, display device or like by an RS-232 cable.
Section 7.19
7-1
7-1
7 FUNCTION
MELSEC-Q
7.2 Constant Scan
(1) What is Constant Scan?
The scan time differs because the processing time differs depending on whether
the instruction, which is used in the sequence program, is executed or not.
Constant scan is a function to execute the sequence program repeatedly while
maintaining the scan time at a constant time.
The I/O refresh is executed before the sequence program is executed. So the
I/O refresh stays constant even when the execution time of the sequence
program varies.
Scan time when constant scan is not used
Sequence program
END 0
END 0
5ms
END processing
END 0
END 0
6ms
5ms
Scan time when constant scan setting is set to 7 ms
Sequence program
END 0
END
END processing
0
END
0
END
0
Wait time
5ms
2ms
7ms
6ms
1ms
7ms
5ms
2ms
7ms
Fig. 7.1 Constant scan operation
7
7-2
7-2
7 FUNCTION
MELSEC-Q
(2) Setting the constant scan time
(a)
The constant scan time setting is performed with the parameter mode PLC
RAS.
The constant scan setting range is 1 ms to 2000 ms.
A setting can be made in modules of 1 ms.
• When executing constant scan, set the constant scan time.
• When not executing a constant scan, leave the constant scan time blank.
[Example] When the constant scan is set to 10 ms.
(b)
Set the set time of the constant scan larger than the maximum scan time of
the sequence program. Also, set the constant scan set time less than the
WDT set time.
(WDT Set Time) > (Constant Scan Set Time) > (Sequence Program maximum Scan Time)
If the sequence program scan time is larger than the constant scan set value,
the Basic model QCPU detects PRG.TIME OVER (an error code: 5010), the
sequence program is executed with the scan time by ignoring the constant
scan.
Constant scan setting
0
Constant
scan
0
Sequence
program
1
3
4
END
0
2
3.5ms
4ms
1
2
3
4
5
1
END 0
0.5ms
3
2
4
END 0
3.5ms
5.3ms
3.7ms
1
4 ms
3
2
END 0
3.4ms
0.2ms
0.6ms
4ms
Scan where the constant scan is not normal
Fig. 7.2 Operation when the Scan Time is More than the Constant Scan
If the value is larger than the WDT set time, the Basic model QCPU detects a
WDT error and stops the program execution.
7-3
7-3
7 FUNCTION
MELSEC-Q
(c)
Sequence program processing is suspended during the waiting time from
END processing execution in a sequence program until the start of the next
scan.
However, if an interrupt factor occurs after END processing execution, the
corresponding interrupt program is run.
(d)
Constant scan accuracy
The following explains the accuracy when the constant scan time has been
set.
1) Refer to Chapter 11 for errors produced when the constant scan time
has been set and the interrupt program is not executed.
2) The interrupt program is also executed during the constant scan
waiting time.
Interruption is disabled during interrupt program execution. Therefore,
if the constant scan time is reached during interrupt program
execution, the constant scan cannot be finished unless the interrupt
program ends.
When the interrupt program is used, the constant scan time may delay
by the interrupt program execution time.
REMARK
Refer to “QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)”
for the command processing time.
7-4
7-4
7 FUNCTION
MELSEC-Q
7.3 Latch Functions
(1) What is Latch Functions?
(a)
The values of each Basic model QCPU device are set back to the default
(bit device: OFF and word device: 0) when;
• The PLC power is turned on.
• The reset operation is performed.
• There is a momentary power failure for more than the permissible amount
of time.
Latch is a function to maintain the device details when the above conditions
occur.
The availability of latches does not affect the operation performed by a
program.
(b)
Latch can be used to maintain the production count, defective count,
address and other data to continue control if the PLC is powered OFF, reset
operation is performed, or an instantaneous power failure occurs for longer
than the permissible time during management of the above data for
continuous control.
(c)
The following devices can use the latch function:
(The default latch range is only the latch relay.)
1)
2)
3)
4)
5)
6)
7)
8)
9)
Latch relay(L)
Link relay(B)
Annunciator(F)
Edge relay(V)
Timer(T)
Retentive timer(ST)
Counter(C)
Data register(D)
Link register(W)
(2) Latch Range Setting
The latch range setting is performed with the PLC parameter mode device
setting.
Latch range setting can be made in two ranges: latch clear (remote latch clear
operation) valid range and invalid range.
7-5
7-5
7 FUNCTION
MELSEC-Q
(3) Clearing the Latch Range Device Data
The following table indicates the device status when latch clear is performed.
Latch Setting Made or Not
Cleared or Maintained by Latch Clear
Device without latch range specified
Latch (1) setting (device set to "The clear is possible
with latch clear.")
Latch (2) setting (device set to "The clear is impossible
with latch clear.")
Cleared
Cleared
Maintained
POINT
File registers (R) cannot be cleared with latch clear.
(See Section 10.7 for clearing file registers.)
(4) Precautions
The device details of the latch range are maintained with the battery (Q6BAT)
attached to the Basic model QCPU.
7-6
(a)
The battery is needed to latch devices if sequence program are stored onto
the standard ROM to perform ROM operation.
(b)
Note that if the battery connector is unplugged from the Basic model QCPU
connector during PLC power-off, the device contents in the latch range are
not maintained and will be indefinite values.
7-6
7 FUNCTION
MELSEC-Q
7.4 Setting the Output (Y) Status when Changing from STOP Status to RUN Status
(1) Output (Y) Status when changing from STOP Status to RUN Status
When changing from RUN status to STOP status, the RUN status output (Y) is
stored in the sequence and all the outputs (Y) are turned OFF.
The state after transition from STOP to RUN can be selected from the following
two options with the Basic model QCPU.
• The output state prior to STOP is output.
• The output is cleared.
(Default: After transition from STOP to RUN, the output (Y) state prior to STOP
is output then the program is executed.)
(a)
Previous State
After the output (Y) status before the STOP status is output, the sequence
program calculations are performed.
(b)
Recalculate (Output is 1 Scan later)
Clears all output (Y) and outputs the output (Y) after executing the
sequence program calculations.
STOP status to RUN status
Replay output?
NO (Output after calculation execution)
YES (Replay output)
Output the output (Y) status
right before changing to
STOP status.
Clear the output (Y) status.
Execute the sequence
program calculations
Fig. 7.3 Processing when Change from STOP Status to RUN Status
7-7
7-7
7 FUNCTION
MELSEC-Q
(2) Setting the Output (Y) Status when Changing from STOP Status to
RUN Status
The output (Y) status before the STOP status when switching from STOP status
to Run status can be set in the PLC System sheet of the PLC Parameter dialog
box.
Output mode setting
at stop to RUN
(3) Precaution
If an output (Y) is forcefully turned ON with the Basic model QCPU in the STOP
status, it will not remain in the ON status even if the STOP status is switched to
the RUN status.
The output status is effected as set in the PLC System setting of the output mode
at STOP to RUN.
7-8
7-8
7 FUNCTION
MELSEC-Q
7.5 Clock Function
(1) What is Clock Function?
(a)
The Basic model QCPU has a clock function in the CPU module.
Because the time data from the clock function can be read by the sequence
program, the time data can be used for time maintenance.
Also, the time data is used for time maintenance for the Basic model QCPU
system functions such as those for failure history.
The clock operations for the clock function are maintained even when the
PLC power is off or when there is a momentary power failure for more than
the permitted time, using the battery (Q6BAT).
(b)
Clock Data
The time data is the year, month, day, hour, minute, second, and day of the
week data used for the Basic model QCPU clock element. There are the
following:
Data Name
Contents
Year
Four digits in AD (Countable from 1980 to 2079)
Month
1 to 12
Day
1 to 31(Automatic leap year calculation)
Hour
0 to 23 (24 hours)
Minute
0 to 59
Second
0 to 59
Day of the week
0
Sunday
1
Monday
2
Tuesday
3
Wednesday
4
Thursday
5
Friday
6
Saturday
(2) Writing to and Reading from the Time Data Clock Element
(a)
7-9
The following two methods can be used to write to the time data clock
element.
1) Method to write from GX Developer
The time data is written in the clock element by displaying "Online"
"Set time" window.
7-9
7 FUNCTION
MELSEC-Q
2)
Method to Write from the Program
The time data is written in the clock element by using the clock
instruction (DATEWR).
A program example to write the time data using the time data write
instruction (DATEWR).
Write request
X0
0
MOVP
K2001
D0
MOVP
K8
D1
MOVP
K10
D2
Day 10
MOVP
K11
D3
Hour 11
MOVP
K35
D4
Minute 35
MOVP
K24
D5
Second 24
MOVP
K4
D6
Day Thursday: 4
DATEWR
Year 2001
Month 8
D0
Refer to "QCPU (Q mode)/QnACPU Programming Manual (Common
Instructions)" for details of the DATEWR instruction.
(b)
Reading Time Data
When reading the time data to the data register, use the time data read
instruction (DATERD) from the program.
The figure below shows an example of a program used to read the clock
data with the DATERD instruction and then store it in D10 to D16.
Read request
X1
DATERD
D10
The time data is read
in D10 to D16.
Refer to the "QCPU (Q mode)/QnACPU Programming Manual (Common
instructions) for the details of the DATERD instruction.
REMARK
1)
2)
Writing to and Reading from Time Data can be executed by special relays
(SM210 to SM213) and special registers (SD210 to SD213).
See Appendix 1 for details on special relay. See Appendix 2 for details on special
registers.
: The figure below shows the clock data stored in D10 to D16.
D10
D11
D12
D13
D14
D15
D16
7 - 10
1999
8
10
11
35
24
4
4 digits in AD
Month
Date
Hour
Minute
Second
Day of the week
Refer to Section 7.5.1(1).
7 - 10
7 FUNCTION
MELSEC-Q
(3) Precautions
(a)
The clock data is not set before shipment.
The clock data is used by the Basic model QCPU system and intelligent
function module for failure history and other functions. Be sure to set the
accurate time when operating the Basic model QCPU for the first time.
(b)
Even if a part of the time data is being corrected, all data must be written to
the clock again.
(c)
The data written in the clock element is checked in the range described in
(1) (b) of Section 7.5.
For this reason, if improbable clock data in the range described in (1) (b) of
Section 7.5 is written in the clock element, correct clock function is
unavailable.
Example
Writing to clock element
CPU module operation state
Executed
No error detected
February 30
Upon execution of DATEW command:
32 of month 13
Not executed
OPERATION ERROR (Error code 4100)
Upon activation of SM210:
SM211 turns ON
(4)
Precision
The precision of the clock function differs with the ambient temperature, as
shown below:
Ambient Temperature ( C )
Accuracy (Day difference, S)
0
-3.2 to +5.27 (TYP.+1.98)
+25
-2.57 to +5.27 (TYP.+2.22)
+55
-11.68 to +3.65 (TYP.-2.64)
(5) Comparison of Clock Data
To compare Basic model QCPU's clock data with a sequence program, use the
DATERD instruction to read the clock data. The year data is read out in 4 digits.
It can be compared as it is by using a compare instruction.
7 - 11
7 - 11
7 FUNCTION
MELSEC-Q
7.6 Remote Operation
The Basic model QCPU provides the RUN/STOP/RESET switches for switching
between the STOP status and the RUN status. The RUN/STOP/RESET switch also
provides the Reset and Latch Clear functions.
The Basic model QCPU performs self control of the operation status from an external
(GX Developer function, intelligent function module, and remote contact) source.
The following four options are available for remote operations:
• Remote RUN/STOP
• Remote PAUSE
• Remote RESET
• Remote LATCH CLEAR
REMARK
The serial communication module is used as the example to describe the intelligent
function module.
7.6.1 Remote RUN/STOP
(1) What is Remote RUN/STOP?
(a)
The remote RUN/STOP performs RUN/STOP of the Basic model QCPU
from an external source with the Basic model QCPU RUN/STOP/RESET
switch at RUN.
(b)
Using remote RUN/STOP for the following remote operations are useful:
1) When the Basic model QCPU is at a position out of reach
2)
(c)
Calculations during Remote RUN/STOP
The program calculation that performs remote RUN/STOP is as follows:
1) Remote STOP
Executes the program to the END instruction and enters the STOP
state.
2)
7 - 12
When performing RUN/STOP of the control board Basic model QCPU
from an external source
Remote RUN
When remote RUN is performed while in the STOP state using remote
STOP, the state changes to RUN and executes the program from
step 0.
7 - 12
7 FUNCTION
MELSEC-Q
(2) Remote RUN/STOP Method
There are two ways to perform remote RUN/STOP:
(a) Remote RUN contact method
The remote RUN contact is set with the PLC parameter mode PLC system
setting.
The device range that can be set is input X0 to 7FF.
By turning the set remote RUN contact ON/OFF, the remote RUN/STOP
can be performed.
1) When the remote RUN contact is OFF, the Basic model QCPU enters
the RUN state.
2)
When the remote RUN contact is ON, the Basic model QCPU enters
the STOP state.
END
Step 0
Step 0
ON
Remote RUN contact
END
0
OFF
STOP
QCPU: RUN/STOP state
RUN
STOP state
Fig. 7.4 Time Chart for RUN/STOP with Remote RUN Contact
(b)
Method using the GX Developer function, serial communication module, etc.
Basic model QCPU can be performed by the remote RUN/STOP operation
from the GX Developer function, serial communication module, etc.
The GX Developer operation is performed with on-line remote operations.
The serial communication module and Ethernet interface module are
controlled by commands complying with the MC protocol.
For details of the MC protocol, refer to the following manual.
• Q corresponding MELSEC Communication Protocol Reference Manual
Step 0
Step 0
END
ON
END
0
Remote STOP command
OFF
GX Developer
Remote RUN command
Serial
communication
module
RUN/STOP state
ON
OFF
STOP
RUN
STOP state
Fig. 7.5 Remote RUN/STOP Time Chart using GX Developer,
serial communication module, etc
7 - 13
7 - 13
7 FUNCTION
MELSEC-Q
(3) Precautions
(a)
Take note of the following, because STOP has priority in Basic model
QCPU:
1) The Basic model QCPU enters the STOP state when remote STOP is
performed from remote RUN contact, GX Developer function, or serial
communication module.
2)
When Basic model QCPU is set to the STOP state with remote STOP,
all external factors which performed a remote STOP (remote RUN
contact, serial communication module, etc.) must be set to RUN.
REMARK
The RUN/STOP state is described below:
• RUN State .................State which repeatedly executes the calculations from step 0
to the END instruction in the sequence program.
• STOP State ...............State where the sequence program calculations are stopped
and the output (Y) is all OFF.
7 - 14
7 - 14
7 FUNCTION
MELSEC-Q
7.6.2 Remote PAUSE
(1) What is Remote PAUSE?
(a)
Remote PAUSE performs the Basic model QCPU PAUSE function from an
external source, with the CPU RUN/STOP/RESET switch at RUN position.
The PAUSE function stops the Basic model QCPU calculations while
maintaining the ON/OFF state of all output (Y).
(b)
This can be used to maintain the output (Y) on even if the QCPU is changed
to the STOP state, in such areas as process control.
POINT
The output (Y) turns OFF at stop error occurrence.
To retain the output at stop error occurrence, make the output retention setting in
the I/O assignment PLC parameters.
(2) Remote PAUSE Method
There are two ways to use remote PAUSE:
(a) Remote PAUSE Contact Method
The remote PUASE contact is set in the GX Developer function parameter
mode PLC system setting.
Setting of only the remote PAUSE contact cannot be made.
When setting the remote PAUSE contact, also set the remote RUN contact.
The device range that can be set is input X0 to 7FF.
1) The PAUSE state contact (SM204) is turned on when the END
processing is executed for the scan with both remote PAUSE contact
and PAUSE permission flag (SM206) on.
2)
When the remote PAUSE contact is off or SM206 is turned off, the
PAUSE state is canceled, and the sequence program calculation is
performed again from step 0.
0
Remote PAUSE
contact
SM206
END
ON 0
0
END
END
END
0
OFF
ON
OFF
ON
SM204
RUN/PAUSE
state
OFF
RUN
ON when
PAUSE
condition
met
PAUSE
PAUSE state
Fig. 7.6 PAUSE Time Chart with Remote PAUSE Contact
7 - 15
7 - 15
7 FUNCTION
MELSEC-Q
(b)
GX Developer function, Serial Communication Module Method
The remote PAUSE operation can be performed from the GX Developer
function or serial communication module.
The GX Developer function operation is performed from on-line remote
operation.
Use the MC protocol commands to exercise control with the serial
communication module or Ethernet interface module.
Refer to the following manual for details of the MC protocol.
• Q-Compatible MELSEC Communication Protocol Reference Manual
1) When the END processing is executed for the scan where the remote
PAUSE command was accepted, the PAUSE state contact (SM204) is
turned on.
When the scan after the PAUSE state contact is turned on is executed
to the END process, it enters the PAUSE state and stops the
calculations.
2)
When the remote RUN command is received, the sequence program
calculations are performed again from step 0.
0
END
0
END
0
ON
Remote PAUSE
command
Remote RUN
command
0
END
OFF
ON
OFF
ON
OFF
SM204
RUN
RUN/PAUSE
state
ON when
PAUSE
condition
met
PAUSE
PAUSE state
Fig. 7.7 PAUSE Time Chart with GX Developer function
(3) Precaution
To set the output (Y) ON/OFF status when change to the PAUSE state, perform
an interlock with the PAUSE state contact (SM204).
M20
X000
Y070
Y70 ON/OFF is determined with the
ON/OFF of the M20 in the PAUSE state.
Y071
Turns off at PAUSE state.
Y072
Turns on at PAUSE state.
SM204
M0
SM204
7 - 16
7 - 16
7 FUNCTION
MELSEC-Q
7.6.3 Remote RESET
(1) What is Remote RESET?
(a)
The remote RESET resets the Basic model QCPU from an external source
when the Basic model QCPU is at STOP state.
Even if the Basic model QCPU RUN/STOP key switch is at RUN, the reset
can be performed when the Basic model QCPU is stopped and an error that
can be detected by the self-diagnosis function occurs.
(b)
Remote RESET can reset the Basic model QCPU remotely when an error
occurs for which the Basic model QCPU cannot be operated directly.
Remote RESET can be executed only at the STOP state. When the Basic
model QCPU is at RUN state, use Remote STOP to arrange the STOP
state.
(2) Remote RESET Method
The remote RESET can only be performed from the GX Developer function or
serial communication module operation.
To perform the remote RESET, follow the following steps:
(a) In the PLC System sheet of the PLC Parameter dialog box, turn on the
"Allow" check box in the "Remote reset" section, and then write parameters
onto the Basic model QCPU.
Allow the
remote reset
7 - 17
(b)
When the Basic model QCPU is at RUN state, use remote STOP to arrange
the STOP state.
(c)
Reset Basic model QCPU with the remote RESET operation.
1) For the GX Developer function, this is performed in on-line remote
operation.
2) The serial communication module and Ethernet interface module are
7 - 17
7 FUNCTION
MELSEC-Q
(3) Precautions
(a)
To perform the remote RESET, turn on the "Allow" check box of the
"Remote reset" section in the PLC System sheet of the PLC Parameter
dialog box, and then write parameters onto the Basic model QCPU. If the
"Allow" check box is not checked, a remote RESET operation is not
performed.
(b)
Remote RESET cannot be performed when the Basic model QCPU is at the
RUN state.
(c)
After the reset operation is complete, the Basic model QCPU will enter
operation state set at the RUN/STOP/RESET switch.
1) With the RUN/STOP/RESET switch in the "STOP" position, the Basic
model QCPU enters into the "STOP" status.
2)
(d)
With the RUN/STOP/RESET switch in the "RUN" position, the Basic
model QCPU enters into the "RUN" status.
Take care that Remote RESET does not reset Basic model QCPU if there is
an error in the Basic model QCPU due to noise.
If Remote RESET does not reset, use the RUN/STOP/RESET switch to
reset or turn the PLC off then on again.
POINT
(1) If Remote RESET is executed when the Basic model QCPU is stopped due to
an error, the Basic model QCPU enters the operation state set at the
RUN/STOP/RESET switch after it is reset.
(2) Even if the "Allow" check box of the "Remote reset" section in the PLC System
sheet of the PLC Parameter dialog box, the remote process of the GX
Developer is completed.
However, the reset process does not proceed in the Basic model QCPU and
therefore it is not reset.
If the state of the Basic model QCPU does not change though a reset process
is performed at the GX Developer, check if the "Allow" check box of the
"Remote reset" section in the PLC System sheet of the PLC Parameter dialog
box is turned on.
7 - 18
7 - 18
7 FUNCTION
MELSEC-Q
7.6.4 Remote Latch Clear
(1) What is Remote Latch Clear?
(a)
The remote latch clear resets the device data latched to the Basic model
QCPU using the GX Developer function or other function, when it is at the
STOP state.
(2) Remote Latch Clear Method
The remote latch clear can only be performed from GX Developer function or
serial communication module.
To perform the remote latch clear, follow the following steps:
(a) Use the RUN/STOP/RESET switch or the remote STOP to place the Basic
model QCPU to the STOP status.
(b)
Use the Latch Clear to bring the Basic model QCPU to the Latch Clear
status.
1) The GX Developer function operations are performed with on-line remote
operation.
2) The serial communication module and Ethernet interface module are
(c)
To return the Basic model QCPU to the RUN status after the remote latch
clear, perform a remote RUN operation.
(3) Precautions
7 - 19
(a)
Either remote latch clear cannot be performed when the Basic model QCPU
is at RUN status.
(b)
There the latch clear (remote latch clear operation) valid range and invalid
range as the device latch ranges set in the device setting in the parameter
mode.
In the remote latch clear operation, only the device range set as the "latch
clear valid" range is reset.
Refer to Section 4.6 for the way to reset the device set to latch clear invalid.
(c)
Devices that are not latched are cleared when the remote latch clear is
executed.
The data in the failure history storage memory of the Basic model QCPU
will also be cleared by a remote latch clear operation.
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7.6.5 Relationship of the remote operation and Basic model QCPU RUN/STOP switch
(1) Relationship of the Remote Operation and Basic model QCPU
Switch
The Basic model QCPU operation status is as follows with the combination of
remote operations to RUN/STOP/RESET switch.
Remote operation
RUN/STOP
RUN
1
STOP
PAUSE
2
RESET
3
Latch clear
switch
RUN
RUN
STOP
PAUSE
STOP
STOP
STOP
STOP
Cannot
operate
RESET
4
Cannot
operate
5
4
Latch clear
1 When performing the operation with remote RUN contact, "RUN-PAUSE contact" must be
set in the parameter mode PLC system setting.
2 When performing the operation with remote PAUSE contact, "RUN-PAUSE contact" must
be set in the parameter mode PLC system setting. In addition, the remote PAUSE enable
coil (SM206) must be set ON.
3 "Remote reset enable" must be set in the parameter mode PLC system setting.
4 RESET or LATCH CLEAR can be performed if the Basic model QCPU changed to the
STOP state from a remote operation.
5 This includes a situation where the Basic model QCPU is stopped due to error.
(2) Remote Operations from the Same GX Developers
When remote operations are performed from the same GX Developer, the status
of the remote operation that is executed last will be effective.
(3) Remote Operations from Multiple GX Developers
While a remote operation is being performed by one GX Developer, another
remote operation cannot be performed by another GX Developer.
After a remote operation that is being performed by one GX Developer is
cancelled, a new remote operation can be performed by another GX Developer.
For example, a remote PAUSE operation is being performed by one
GX Developer, the PAUSE status will remain active even if a remote
STOP/remote RUN operation is attempted by another GX Developer.
When a remote RUN operation is performed by the GX Developer that is
performing a remote PAUSE operation, and then that remote operation is
cancelled, a new remote operation can be performed by another GX Developer.
7 - 20
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7.7 Selection of Module Input Response Time (I/O Response Time)
7.7.1 Selection of input response time of the input module/composite I/O module
(1) Selection of Input Response Time of the Input Module/Composite
I/O Module
Selection of the input response time of the input module/composite I/O module is
to change the input response time of the input module/composite I/O module to
1ms, 5ms, 10ms, 20ms or 70ms on a module basis.
The input module/composite I/O module imports external inputs at the specified
input response time.
The default setting of the input response time is 10ms.
ON
External input
OFF
ON
Input module
OFF
Input response time
(2) Setting of Input Response Time
Set the input response time in the I/O assignment of the PLC parameter dialog
box.
Choose "Input" as the type of the slot to which the input response time is set.
For the composite I/O module, choose "Composite I/O".
Input module: Select Input.
Composite I/O module: Select Composite I/O. Select "Detail Setting".
Select "Input response time".
(3) Reactions
7 - 21
(a)
Setting of shorter input response time increases sensitivity to noise.
Take the operating environment into consideration when setting the input
response time.
(b)
The setting of the input response time is made valid when:
• The PLC is powered ON; or
• CPU module is reset.
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MELSEC-Q
7.7.2 Selection of input response time of the high-speed input module
(1) Selection of input response time of the high-speed input module
The input response time of the high-speed input module (QX40-S1) 0.1ms,
0.2ms, 0.4ms, 0.6ms or 1ms on a module basis.
The high-speed input module imports external inputs the specified input
response time.
The default value is set to 0.2ms.
ON
External input
OFF
ON
High-speed
input module
OFF
Input response time
(2) Input response time setup
Set the input response time in the I/O assignment PLC parameters.
Choose "Hi. input" as the type of the slot to which the input response time is set.
Select "Hi. Input"
Click on this for detailed setting
Select input response time
(3) Precautions
7 - 22
(a)
Setting of a higher input response time increases sensitivity to noise.
response time.
(b)
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7 FUNCTION
MELSEC-Q
7.7.3 Selection of input response time of the interrupt module
(1) Selection of input response time of the interrupt module
The input response time of the interrupt module (QI60) can be selected from
0.1ms, 0.2ms, 0.4ms, 0.6ms or 1ms on a module basis.
The interrupt module imports external inputs the specified input response time.
The default value is set to 0.2ms.
ON
External input
OFF
ON
Interrupt module
OFF
Input response time
(2) Input response time setup
Set the input response time in the I/O assignment PLC parameters.
Choose "Interrupt" as the type of the slot to which the input response time is set.
Click on this for detailed setting
Select "Interrupt"
Select input response time
(3) Precautions
7 - 23
(a)
Setting of a higher input response time increases sensitivity to noise.
response time.
(b)
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MELSEC-Q
7.8 Error-time Output Mode
(1) Error-time Output Mode Setting
The error-time output mode setting is to set whether the output to the Q series
compatible output module, hybrid I/O module or intelligent function module will be
cleared or held when the CPU module results in a stop error.
(2) Error-time Output Mode Setting
Make the error-time output mode setting in the I/O assignment of the PLC
Choose "Output", "Hybrid I/O" or "Intelligent" as the type of the slot to which the
error-time output mode is set.
Then select Detailed setting.
Choose "Clear" or "Hold" for the slot to which the error-time output mode is set.
(The default is "Clear".)
Select Type.
Select Detailed setting.
Select "Clear" or "Hold" under
Error-time output mode.
(3) Precautions
The error-time output mode setting is made valid when:
• The PLC CPU is power ON.
• The CPU module is reset.
Failure to perform either operation after changing the error-time output mode
setting will result in "PARAMETER ERROR (error code: 3000)".
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7.9 Hardware Error-time CPU Operation Mode Setting
(1) Hardware Error-time CPU Operation Mode Setting
The hardware error-time CPU operation mode setting is to set whether the
operation of the CPU module will be stopped or continued when a hardware error
occurs in the intelligent function module.
(2) Hardware Error-time CPU Operation Mode Setting
Make the hardware error-time CPU operation mode setting in the I/O assignment
of the PLC parameter dialog box.
Choose "Intelligent" as the type of the slot to which the hardware error-time CPU
operation mode is set.
Then select Detailed setting.
Choose the hardware error-time CPU operation mode of the slot to which the
hardware error-time CPU operation mode is set.
(The default is "Stop".)
Select Intelligent.
Select Detailed setting.
Select "Stop" or "Continue" under Hardware
error-time CPU operation mode.
(3) Precautions
The hardware error-time CPU operation mode setting is made valid when:
• The PLC CPU is power ON.
Failure to perform either operation after changing the hardware error-time CPU
operation mode setting will result in "PARAMETER ERROR (error code: 3000)".
7 - 25
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7.10 Setting the Switches of the Intelligent-Function Module
(1) Setting the Switches of the Intelligent-Function Module
The switches of the intelligent-function module is to set the switches of an QCPUcompatible intelligent function module using GX Developer.
The settings of the switches set by GX Developer is written from Basic model
QCPU to each intelligent function module at the leading-edge or reset of Basic
model QCPU.
Basic model
QCPU
GX Developer
Parameter
Switch setting of the
intelligent function module
at the I/O assignment
Write
Parameter
Power supply
On/QCPU
module Reset
module
Switch setting
(2) Setting the Switches of the Intelligent-Function Module
In the "I/O assignment" sheet of the PLC Parameter dialog box, specify the
desired switch setting. Select "Intelli." in the "type" column of a slot for which to
set the switches of the intelligent function module.
Select "Intelli".
Select "Switch Setting".
Designate the contents of the
intelligent function module switch.
(3) Precautions
7 - 26
(a)
Do not apply the switch setting for an intelligent function module.
If the switch setting for an intelligent function module is specified an error
(SP.PARA.ERROR) will occur.
(b)
Set "Interrupt" as the type to set the switches of the intelligent function
module using GX Developer.
Refer to the following manual for details of the interrupt module switch
setting.
• Building Block Type I/O Module User's Manual
(c)
The switch setting is made valid when:
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7 FUNCTION
MELSEC-Q
7.11 Program Write during RUN of Basic Model QCPU
There are the following two different types for program write during RUN of the Basic
model QCPU.
Write during RUN in ladder mode (refer to Section 7.11.1)
Write during RUN using pointer (refer to Section 7.12.2)
7.11.1 Writing Data in the Ladder Mode during the RUN Status
(1) Writing data in the ladder mode during the RUN Status
(a)
Writing data in the circuit mode during the RUN status is used to write a
program during the Basic model QCPU RUN status.
(b)
Changing the program can be performed without stopping the process in
Basic model QCPU program using writing data in the ladder mode during
the RUN status.
X0 X2
Y30
X1
X3 X4
SET M10
X5
END
GX Developer
Change by GX Developer and write in
Basic model QCPU at the conversion.
(c)
Writing to the program during RUN can be performed from a GX Developer
function peripheral device connected to another station in the network.
MELSECNET/H
Writing data the ladder mode during the RUN status.
Personal computer
(GX Developer)
7 - 27
7 - 27
7 FUNCTION
MELSEC-Q
(2) Precautions
Take a note of the following when writing during RUN:
(a) The memory that can be written during RUN is only program memory.
If the write during RUN is performed while booting a program from the
standard ROM, the program to be booted will not be changed.
Write the contents of the program memory to the standard ROM before
powering off the PLC or resetting the Basic model QCPU.
(b)
A maximum of 512 steps can be written at once during RUN.
(c)
The program file capacity of the Basic model QCPU is the value of adding
the "steps secured for write during RUN" to the created program capacity.
When the program file capacity is increased from the capacity secured first
by write during RUN that increases the program file capacity, the steps
secured for write during RUN can be set again at the time of write during
RUN.
Therefore, when the user memory area has a free space, write during RUN
can be performed.
However, if the steps secured for write during RUN are re-set at the time of
write during RUN, note that the scan time will increase by the value given in
the following table. (Control will be suspended during the time indicated in
the following table.)
CPU Module Model
(d)
7 - 28
Steps Secured for Write during RUN
Name
No change
Re-setting
Q00JCPU
Maximum 2.1ms
Maximum 30ms
Q00CPU
Maximum 1.7ms
Maximum 26ms
Q01CPU
Maximum 1.7ms
Maximum 36ms
Normal operation will not be performed if any of the following instructions is
written using online write.
1) Trailing edge instructions
Any of the following trailing edge instructions is executed if the
execution condition of the trailing edge instruction is OFF on
completion of write.
• LDF
• ANDF
• ORF
• MEF
• PLF
2) Leading edge instructions
The leading edge instruction is not executed if the execution condition
of the leading edge instruction (PLS instruction/ P instruction) is ON
on completion of write.
The leading edge instruction is executed when the execution condition
turns from OFF to ON again.
3) SCJ instruction
If the execution condition of the SCJ instruction is ON on completion of
write, a jump to the specified pointer is made without waiting for one
scan.
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7 FUNCTION
MELSEC-Q
7.12 Multiple-User Debugging Function
(1) What is Multiple-User Debugging Function?
The multiple-user debugging function executes debugging simultaneously from
multiple GX Developers connected to the Basic model QCPU, serial
communication module, etc.
(2) Function Explanation
There are the following combinations of multiple-user debugging functions.
Function Executed Later
Monitor
Write during RUN
Function in Execution
Monitor
Write during RUN
: Can be executed simultaneously.
: Can be executed from only one GX Developer. (While the function is being
executed by one GX Developer, it cannot be executed by other GX Developers.)
7 - 29
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7 FUNCTION
MELSEC-Q
7.12.1 Multiple-user monitoring function
(1) What is Multiple-User Monitoring Function?
(a)
The multiple-user monitoring operation can be performed by operating from
multiple GX Developers connected to the Basic model QCPU or the serial
communications module.
(b)
Multiple users can monitor at the same time. By setting a station monitor
file, high-speed monitoring can be performed. (Setting of station monitor
file is not necessary.)
(2) Operation Procedure
(a)
For multi-user monitoring operation, create a user-defined system file in the
following steps.
1) Choose "Online" "Format PLC Memory" to open the Format PLC
Memory dialog box.
2) Select "program memory/device memory" from the Target Memory list
box.
3) In the Format section, select "Create a user setting system area..." so
that its radio button is checked.
4) Specify the desired K steps in the System Area text box.
(b)
The figure below illustrates an example in which "1k step" is specified in the
System Area text box.
1)
A maximum of 15 k steps can be set in 1 k step modules as a system
area. Only 1 k step can correspond to one station monitor file.
Therefore, a maximum of 15 station monitor files can be set.
(3) Precautions
7 - 30
(a)
Monitoring can be performed even if a station monitor file is not set, but
high-speed monitoring cannot be performed.
The system area is in the same area as the program memory, so the area
of the stored program reduced when the system area is set.
(b)
When the user-set system area of 3k steps is created, the simultaneous
monitoring of one CPU from four locations can be speeded up.
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7 FUNCTION
MELSEC-Q
7.12.2 Multiple-user simultaneous write during RUN
(1) What is Multiple-User Simultaneous Write during RUN?
(a)
Multiple-user simultaneous write during RUN allows multiple users to
perform write during RUN simultaneously to one file or different files.
(b)
When multiple users perform write during RUN simultaneously to one file,
preset the pointer for write during RUN and select "Relative write during
RUN using pointer".
(2) Operation Procedure
(a)
Choose "Tools" - "Options" and set "Set write during RUN" and "Write
during RUN system".
1)
2)
1)
2)
7 - 31
Set "Perform write during RUN to PLC after conversion" under "Set
write during RUN".
Select "Normal write during RUN" or "Relative write during RUN using
pointer" under "Write during RUN system".
7 - 31
7 FUNCTION
MELSEC-Q
(b)
Display the ladder of the specified pointer and perform write during RUN of
the changed ladder.
The following figure shows an example where the personal computer A
performs write during RUN from P0 and the personal computer B performs
write during RUN from P1. The program enclosed by is the target of write
during RUN.
Write during RUN of P0 and later
in machining program is performed.
P0
X0 X2
Write during RUN of P0 and later
in machining program is performed.
Y30
P0
X1
X3 X4
P1
X0 X2
Serial
communication
module
X3 X4
SET M10
P1
X5
Y30
X1
SET M10
X5
END
END
Personal computer A
(GX Developer)
Personal computer B
(GX Developer)
(3) Precautions
The precautions for write during RUN are the same as those for write during
RUN in ladder mode in Section 7.11.1. Refer to Section 7.11.1.
7 - 32
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7 FUNCTION
MELSEC-Q
7.13 Watchdog Timer (WDT)
(1) What is Watchdog Timer (WDT)?
(a)
The watchdog timer is an internal sequence timer to detect Basic model
QCPU hardware and/or sequence program error.
(b)
When the watchdog timer expires, a watchdog timer error occurs.
The Basic model QCPU responds to the watchdog timer error in the
following way.
1) The Basic model QCPU turns off all outputs.
2) The front-mounted RUN LED goes off, and the ERR. LED starts
flashing.
3) SM1 turns ON and the error code 5001 (WDT ERROR) is stored into
SD0.
(c)
The default value of the watchdog timer is 200 ms.
The setting range is 10 to 2000 ms (10ms units).
(2) Watchdog Timer Setting and Reset
(a)
The PLC RAS setting of the PLC parameter resets the watchdog timer.
(b)
Basic model QCPU resets the watchdog timer when the END instruction is
executed.
1) When the END/FEND instruction is executed within the set value of the
watchdog timer in the sequence program and the Basic model QCPU
is operating correctly, the watchdog timer does not time out.
2)
When there is a Basic model QCPU hardware failure or the sequence
program scan time is too long, and the END/FEND instruction could
not be executed within the set watchdog timer value, the watchdog
timer times out.
(3) Precautions
(a)
An error of 0 to 10 ms occurs in the measurement time of the watchdog
timer. Set the watchdog timer for a desired value by taking such an error
into account.
(b)
The watchdog timer is reset with the WDT instruction in the sequence
program. If the watchdog timer expires while the FOR and NEXT
instructions are repetitiously executed, reset the watchdog time with the
WDT instruction.
FOR K1000
Program for repetition processing
Repetition
(1000 times)
M0
WDT
WDT reset
NEXT
7 - 33
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7 FUNCTION
MELSEC-Q
(c)
The scan time value is not reset even if the watchdog timer is reset in the
sequence program.
The scan time value is measured to the END instruction.
Internal processing time
END
Sequence program
0
WDT reset
(QCPU internal processing)
Internal processing time
END
Scan time
0
Next scan time
WDT reset (QCPU internal processing)
Watchdog timer measured time
Fig. 7.9 Watchdog Timer Reset
REMARK
Scan time is the time elapsed from the time the Basic model QCPU starts
processing a sequence program at Step 0 until the it restarts processing another
sequence program with the same filename at Step 0.
The scan time is not the same at every scan, and differs, depending on
• Whether the commands used are executed or not executed.
• Whether to execute or not an interrupt program.
Use the constant scan function to execute a program at the same scan time every
scan.
Refer to section 7.2 for details of the constant scan function.
7 - 34
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7 FUNCTION
MELSEC-Q
7.14 Self-Diagnosis Function
(1) What is Self-Diagnosis Function?
(a)
The self-diagnosis is a function performed by Basic model QCPU itself to
diagnose whether there is an error in the Basic model QCPU.
(b)
The self-diagnosis function's objective is to prevent Basic model QCPU
erroneous operation and as preventive maintenance.
The self-diagnosis processing detects and displays the error when an error
occurs when the Basic model QCPU power is turned on or during Basic
model QCPU RUN mode. It also stops Basic model QCPU calculations.
(2) Processing for Error Detection
(a)
When Basic model QCPU detects an error, it turns on ERR. LEDs. When
an error is detected, special relays (SM0, SM1) are turned ON and an error
code of the error is stored in the special register SD0. When multiple errors
are detected, error codes of the latest errors are stored in the special
register SD0. For error detection, use special relays and special registers in
program so that these devices can interlock with sequencers and
mechanical systems.
(b)
Basic model QCPU stores 16 latest error codes. (Refer to Section 7.13.)
The failure history can be checked in the GX Developer function PLC
diagnostics mode.
The failure history can be stored even when the power is shut off using the
battery backup.
(3) Basic model QCPU operation at the time of error detection
7 - 35
(a)
When an error is detected from the self-diagnosis, there are two types of
modes that the Basic model QCPU operation can change to.
1) Basic model QCPU calculation stop mode
Stops the calculation at the point when the error is detected, and turns
off all external outputs of the module for which "Clear" (default) has
been set to "Error-time output mode" in the I/O assignment of the PLC
parameter dialog box. (The outputs (Y) on the device memory are
retained.)
However, the external outputs of the module for which "Retain" has
been set to "Error-time output mode" are retained. (The outputs (Y) on
the device memory are retained.)
2) Basic model QCPU calculation continue mode
When an error is detected, the program (Instruction) area where the
error occurred is skipped and the rest of the program is executed.
(b)
The following errors can set the calculation "continue/stop" in the parameter
mode PLC RAS.
(All parameter defaults are set at "Stop".)
1) Operation error
2) Fuse blown
3) I/O unit comparison
4) Intelligent function module program execution error
For example, when the I/O module verification error is set to "continues",
the calculations are continued in the I/O address before the error occurred.
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7 FUNCTION
MELSEC-Q
(c)
For the following error, selection of calculation "Continue/Stop" can be made
in the detailed setting of I/O assignment setting.
• Intelligent function module error
(4) Error check selection
The error checking can be set to "yes/no" in the following error checking in the
parameter mode PLC RAS setting.
(All parameter defaults are set at "Yes".)
(a) Battery check
(b)
Fuse blown check
(c)
I/O unit comparison
Self-Diagnosis List
Diagnosis description
MAIN CPU DOWN
• Always
END instruction not executed
END NOT EXECUTE
• When the END instruction is executed
SFC program execution error
SFCP. END ERROR
• When the SFC program is executed
RAM check
RAM ERROR
• When the power is turned on/when reset
Calculation circuit check
OPE.CIRCUIT ERR.
FUSE BRAKE OFF
2
(Default... Yes)
I/O INT ERROR
• When an interrupt occurs
SP.UNIT DOWN
• When the FROM/TO instruction is executed
Control bus error
CONTROL-BUS ERROR.
• When the intelligent function module dedicated
instruction is executed
Momentary stop occurred
AC/DC DOWN
• Always
Battery low
BATTERY ERROR
• Always (Default...Yes)
I/0 module verification (Default...
1
Stop)
UNIT VERIFY ERROR
2
(Default... Yes)
Base allocation error
BASE LAY ERROR
1
I/O interrupt error
Intelligent function module error
Handling error
Diagnostic timing
CPU error
Fuse short (default... stop)
Hardware failure
Error message
1
3
Intelligent program execution error
SP. UNIT ERROR
1
(Default... Stop)
• When an instruction is executed
allocation error
SP.UNIT LAY ERR.
• When the power is turned on/when rest
• When switched from STOP to RUN
No parameter
MISSING PARA.
Boot error
BOOT ERROR
File setting error
FILE SET ERROR
Instruction execution not possible
CAN´T EXE.PRG.
1:Can be changed to "Continue" in the GX Developer function parameter setting.
2:Can be set to "No" in the GX Developer function parameter setting.
7 - 36
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7 FUNCTION
MELSEC-Q
Self-Diagnosis List (Continued from the preceding page)
Diagnosis description
Parameter error
Diagnostic timing
Parameter setting check
PARAMETER ERROR
Link parameter error
LINK PARA.ERROR
SFC parameter error
SFC PARA.ERROR
parameter error
SP.PARA.ERROR
REMOTE PASS.ERROR
Instruction code check
INSTRUCT CODE ERR.
No END instruction
MISSING END INS.
Pointer setting error
CAN´T SET(P)
Pointer setting error
CAN´T SET(I)
Operation check error (Default...
1
Stop)
OPERATION ERROR
Password error
Program error
Error message
FOR to NEXT instruction structure
FOR NEXT ERROR
error
CALL to RET instruction structure
error
CAN´T EXECUTE(P)
Interrupt program error
CAN´T EXECUTE(I)
Instruction execution disable
INST.FORMAT ERR.
SFC block structure error
CAN´T SET(BL)
SFC step structure error
CAN´T SET(S)
SFC syntax error
SFCP.FORMAT ERR.
SFC program execution error
SFCP.EXE.ERROR
SFC block execution error
BLOCK EXE.ERROR
SFC step execution error
STEP EXE. ERROR
Watchdog error supervision
WDT ERROR
• Always
Program time exceeded
PRG.TIME OVER
• Always
Other CPU major fault
MULTI CPU DOWN
• Always
Multiple CPU execution error
MULTI EXE.ERROR
Multiple CPU matching error
CPU LAY ERROR
Other CPU minor fault
MULTI CPU ERR.
• Always
PLC error
Multiple CPU
1:Can be changed to "continues" in the GX Developer function parameter setting.
7 - 37
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MELSEC-Q
7.14.1 LED display when error occurs
When an error occurs, the ERR. LED located on the front of Basic model QCPU turns
on.
Refer to Section 7.18 for details of the ERR. LED operation.
7.14.2 Cancel error
Basic model QCPU error cancel operation can be performed only for error that can
continue the Basic model QCPU operation.
(1) Cancellation of error
(a)
Procedures for cancellation of error
The error cancel is performed in the following manner:
1) Resolve the cause of error.
2)
Store the error code of the error to be canceled in the special register
SD50.
3)
Switch special relay SM50 from OFF to ON.
4)
The error is canceled.
(b)
Status after cancellation of error
When the CPU is recovered from canceling the error, the special relay,
special register, and LED affected by the error are set to the state before
the error occurred.
When the same error occurs after canceling the error, it is logged again in
the failure history.
(c)
Cancellation of annunciator
For the cancellation of the annunciator detected multiple times, only the first
detected "F" is canceled.
POINT
(1) When error cancellation is performed by storing the code of the error to cancel
is stored in SD50, the lower 1 digits of the code number is ignored.
(Example)
When the error codes 2100 and 2101 occur, canceling the error code 2100 will
also cancel the error code 2101.
When the error codes 2100 and 2111 occur, canceling the error code 2100 will
not cancel the error code 2111.
(2) If the cause of the error is not in the CPU module, the error cause cannot be
resolved if error cancellation is performed using the special relay (SM50) and
special register (SD50).
(Example)
Since "SP. UNIT DOWN" is an error that occurred on the Q bus, the error
cause cannot be resolved if error cancellation is performed using the special
relay (SM50) and special register (SD50).
Refer to the error code list in the Basic model QCPU (Q mode) User's Manual
(Hardware Design, Maintenance and Inspection), and resolve the error cause.
7 - 38
7 - 38
7 FUNCTION
MELSEC-Q
7.15 Failure History
The Basic model QCPU can store the failure history (results detected from the selfdiagnosis function and the time) in the memory.
POINT
The detection time uses the Basic model QCPU internal clock, so make sure to set
the correct time when first using Basic model QCPU.
(1) Storage Area
The latest 16 failures are stored in the latched Basic model QCPU failure history
storage memory.
(2) Stored data
If the same error occurs more than once during PLC power-on, it is stored into
the failure history storage memory only once.
(3) Failure History Clearing Method
The failure history storage memory are cleared using the failure history clear in
the GX Developer PLC diagnosis mode.
Data files stored in Basic model QCPU failure history storage memory can be
cleared with a failure history clear.
7 - 39
7 - 39
7 FUNCTION
MELSEC-Q
7.16 System Protect
Basic model QCPU has a few protection functions (system protect) for the program
changes to processing of general data obtained from a third party other than the
designer (access processing from GX Developer function or serial communication
module).
There are the following methods for system protects.
Item to protect
Protect valid file
• Program
File unit
• Device comments
Protection description
The attributes for a file is
changed to the following:
1) Read/Write display prohibit
2) Write prohibit
Method
Valid
Timing
Remarks
Change the attributes for
the file in the Password
Always
Registration.
The control instruction, read/write display, and write are mentioned above are as follows:
Item
Description
Read/Write display
Program read/write operations.
Write
Operation that writes the program and tests.
7.16.1 Password registration
Password is used to prohibit the data read and write of the program and comments in
Basic model QCPU from a GX Developer peripheral device.
Password Registration is applicable to the program file, device comment file and
device initial value file in the program memory.
There are two descriptions of items to be registered.
• The file name is not displayed and read/write cannot be performed as well.
• Write cannot be performed to the file. (Read only)
If the password is registered, file operations from GX Developer cannot be performed
unless the same password is input.
7 - 40
7 - 40
7 FUNCTION
MELSEC-Q
(1) Password Registration
To perform the password registration, select GX Developer Online
setup/keyword set up for writing to PLC Register password.
Password
(a)
(b)
(c)
(d)
(e)
(f)
Each item is described below:
(a) Target memory ....................Set the memory storing the file whose
password is to be registered or changed.
(b)
Data type..............................Specifies the type of a file stored in the target
memory.
(c)
Data name............................Displays a filename of a file stored in the target
memory.
(d)
Registration..........................Displays an asterisks "
password-protected file.
(e)
Password .............................Defines or changes a password.
Setting a password allows you to set the
registration condition.
(f)
Registration Condition
1) Write Protect ................Write operation is restricted by the password.
(Reading is possible.)
2) Read/Write protect.......Read/Write operation is restricted by the
password.
3) Clear.............................Password is cleared.
(Sets password currently registered in the Password.)
" that indicates a
POINT
(1) Password-protected files are limited to the program file, device comment file
and device initial value file. Other files cannot be password-protected.
(2) The password registered to a file can not read out from the file.
If the password can not be remembered, file operation other than following can
not be performed.
• Program memory: PLC memory format
• Standard ROM: storage of program memory data onto ROM
Take notes of the password registered and keep it on hand.
7 - 41
7 - 41
7 FUNCTION
MELSEC-Q
7.16.2 Remote password
The remote password function is used to prevent illegal access to the Basic model
QCPU from a remote user.
By setting a remote password to the Basic model QCPU, the remote password
function can be used.
With the remote password preset, the serial communication module and Ethernet
module of the modem function check the remote password when access is made from
a remote user to the Basic model QCPU.
(1) Setting, change and cancellation of remote password
(a)
(b)
Setting of remote password
Set the remote password on the remote password setting screen of GX
Developer, connect GX Developer to the Basic model QCPU where the
remote password will be set, and write the remote password.
The Basic model QCPU transfers the remote password to the specified one
of the following modules when the PLC is powered on or the Basic model
QCPU is reset.
• Serial communication module
• Ethernet module
• Modem interface module
Change and cancellation of remote password
By connecting GX Developer to the Basic model QCPU, the remote
password of the connected Basic model QCPU can be changed or
canceled.
Using GX Developer, set a new password or delete the remote password,
and write it to the Basic model QCPU. This enables the remote password of
the Basic model QCPU to be changed or canceled.
Change or cancellation of the remote password cannot be performed from
a remote location.
The following figure shows the outline of setting, changing and canceling
the remote password for the Ethernet module, for example.
GX Developer
Ethernet
sP
uo
pw
pe
l r
y
Transfers remote
password to QJ71E71
at power-on or reset.
Q
J
71
E
71
Q
C
P
U
Checks remote password.
GX Developer
7 - 42
Set
Change
Cancel
remote password and write to QCPU.
7 - 42
7 FUNCTION
MELSEC-Q
(2) Remote password lock/unlock processing
At the access source, unlock the remote password of the serial communication
module via modem or that of the Ethernet module via Ethernet.
On a remote password match, access to the Basic model QCPU is allowed.
The following figure shows the outline of the remote password unlock and lock
processing performed by the Ethernet module, for example.
The following figure shows the outline of setting, changing and canceling
the remote password for the Ethernet module, for example.
GX Developer
Unlocks (cancels) remote password
and makes access to QCPU.
When closing line, performs lock
processing of remote password.
Ethernet
s
u
p
p
l
y
Transfers remote
password to QJ71E71
at power-on or reset.
P
o
w
e
r
Q
J
71
E
71
Q
C
P
U
Checks remote password.
GX Developer
7 - 43
7 - 43
7 FUNCTION
MELSEC-Q
(3) Remote password setting procedure
Choose "GX Developer" [Remote password] "Remote password setup"
screen "Remote password detail setup" screen.
(a) Setting screen
Remote password setting
(b)
Detailed setting is necessary
for QJ71E71.
Setting items
Item
Setting
Setting Range/Choices
4 bytes
Password setting
Remote password input
Alphanumeric characters, special
symbols
Password valid
module setting
Model name
Select the model name.
Set the head address of the
Head I/O
module.
QJ71E71/QJ71C24/QJ71CMO
0000H to 0FE0H
Detailed setting
User connection No.
Set the user connection No.
Connection No. 1 to connection
No. 16
Automatic open UDP port
FTP communication port (TCP/IP)
System
connection
GX Developer communication port
(TCP/IP)
GX Developer communication port
Check the remote password
valid port.
(UDP/IP)
HTTP port
POINT
Refer to the following manuals for details of the remote password function.
• When the serial communication module is used
Q Corresponding Serial Communication Module User's Manual (Application)
• When the Ethernet module is used
Q Corresponding Ethernet Interface Module User's Manual (Fundamentals)
• When the QJ71CM0 is used
QJ71CM0 Modem Interface Module User's Manual (Details)
7 - 44
7 - 44
7 FUNCTION
MELSEC-Q
7.17 GX Developer system monitor
It is possible to confirm the following information for Basic model QCPUs connected to
personal computers with the GX Developer system monitor (see illustration below.)
• Installed status
• Operation status
• Module’s detailed information
• Product information
(c)
(a)
(b)
(d)
(e)
(f)
(g)
7 - 45
(a)
Installed status
You can confirm the types and points of the modules loaded on the
selected base unit.
"Not installed" will be displayed for slots in which modules have not been
mounted.
When slots have been set as "Empty" with the PLC parameter's I/O
allocation setting, the module's model will not be displayed when if a
module has been mounted.
(b)
Operation status
Enables the I/O number, the module type and the number of modules
mounted for each of the slots on the selected base unit to be confirmed.
If the operation status shows 0 empty points and an allocation error is
displayed, it means that the PC parameter's I/O allocation and the actual
status are different.
In this event, align the PLC parameter's I/O allocation with the actual status
by allocating an I/O.
(c)
Base
Enables the status of the modules mounted onto the base unit in use to be
confirmed.
The module column displays an error or warning status if even one module
is faulty.
(d)
Diagnostics
This function is used to confirm the status of Basic model QCPU and errors.
7 - 45
7 FUNCTION
MELSEC-Q
(e)
Module’s detailed information
This function is used to confirm the detailed information for selected
modules.
Refer to the instruction manual for the relevant intelligent function module
for details on the detailed information for intelligent function modules.
(f)
Base information
Enables the "Overall Information" and "Base Information" to be confirmed.
1) Overall information
Enables the number of base units in use and the number of modules
mounted on the base units to be confirmed.
2)
(g)
Base information
Enables the base name, the number of slots, the base type and the
number of modules mounted on the base unit for the selected base
unit (main base unit, extension base units 1 to 7) to be confirmed.
List of product information
Enables the individual information on the mounted CPU module,
input/output modules and intelligent function modules to be confirmed
(Type, Series, Model name, Points, I/O No., Control CPU, Serial NO.,
Function version).
Serial No.
7 - 46
Function version
7 - 46
7 FUNCTION
MELSEC-Q
7.18 LED Display
The LEDs that indicate the operation statuses of the Basic model QCPU are provided
on the front panel of the Basic model QCPU. The indications of the LEDs are
described below.
(1) The details of the LED display are shown below:
LED name
Display Description
Indicates the operation status of the CPU module.
On
: When operating with the RUN/STOP/RESET switch at "RUN".
Off
: When stopped with the RUN/STOP/RESET switch at "STOP".
Flicker
: When writing parameters ad program during STOP, and when setting the RUN/STOP/RESET
Or when an error that stops operation is detected.
switch from [STOP]
[RUN]. Perform the following operations in order to illuminate the RUN
LED after program writing.
• Set the RUN/STOP/RESET switch to [RUN]
RUN
[STOP]
[RUN].
• Reset the system with the RUN/STOP/RESET switch.
• Switch on the power to the PLC again.
Perform the following operations in order to illuminate the RUN LED after parameter writing.
• Reset the system with the RUN/STOP/RESET switch.
• Switch on the power to the PLC again.
(When the RUN/STOP/RESET switch has been set to [RUN]
[STOP]
[RUN] after the
parameters have been amended, the parameters related to intelligent function modules and
other network parameters will not be reflected back.)
Indicates the error detection status of the CPU module.
On
ERR.
: When a self-diagnosis error that does not stop the operation is detected. (Set the operation error
set mode to "continue" in the parameter mode PLC RAS setting.)
Off
: Normal
Flicker
: When an error that stops the operation is detected.
When the CPU is reset with the RUN/STOP/RESET switch. Goes off on completion of reset.
Indicates the 5VDC output status of the power supply built in the Q00JCPU.
POWER
7 - 47
On
: Normal output of 5VDC
Off
: PLC power off or 5VDC output error
7 - 47
7 FUNCTION
MELSEC-Q
(2) How to turn off the ERR. LED
To turn off the ERR. LED that is on, remove the cause of the error and then
operate the special relay SM50 and special register SD50 to cancel the error.
(This does not apply to reset operation.)
REMARK
Refer to Section 7.14.2 for canceling the error.
7 - 48
7 - 48
7 FUNCTION
MELSEC-Q
7.19 Serial Communication Function (Usable with the Q00CPU or Q01CPU)
The serial communication function is designed to make communication in the MC
protocol (*1) by connecting the RS-232 interface of the CPU module and personal
computer, display device or the like by an RS-232 cable.
The serial communication function is not used for connection of GX Developer or GX
Configurator and the CPU module.
Communication using the serial communication function can be made by the Q00CPU
or Q01CPU.
(The Q00JCPU does not have the serial communication function.)
The following explains the specifications, functions and various settings needed to
make communication with a personal computer, display device or the like using the
serial communication function.
RS-232 cable
Personal computer,
display device
Communication in
MC protocol
1 The MC protocol is the abbreviation of the MELSEC communication protocol.
The MELSEC communication protocol is a name of the communication method
to make access from the mating equipment to the CPU module in accordance
with the communication procedure of the Q series PLC (e.g. serial
communication module, Ethernet interface module).
POINT
The CPU that can make communication with a personal computer, display device
or the like using the serial communication function is only the CPU module that is
connected with the personal computer, display device or the like.
Communication cannot be made with the other station of MELSECNET/H, Ethernet
or CC-Link via the CPU module that is connected with the personal computer,
display device or the like.
7 - 49
7 - 49
7 FUNCTION
MELSEC-Q
(1) Specifications
(a)
Transmission specifications
The following table indicates the transmission specifications of RS-232
used for the serial communication function of the CPU module.
Use the serial communication function after making sure that the
specifications of the personal computer, Display device or the like match
those of the following table.
Item
Default
Communication system
Full duplex communication
Synchronization system
Asynchronous system
Transmission speed
1
19.2kbps
Setting Range


9.6kbps, 19.2kbps, 38.4kbps,
57.6kbps, 115.2kbps
Start bit: 1
Data bit: 8
Data format

Parity bit: Odd
Stop bit: 1
MC protocol format
2
Format 4 (ASCII)
(Automatic judgment)
Frame

Format 5 (binary)
QnA-compatible 3C frame
2

Transmission control
DTR/DSR control
Sum check
No
1
Transmission wait time
Write during RUN setting
1
No wait
1 Not enabled
Extension distance

Yes, No
No wait, 10ms to 150ms (10ms
increments)
Enabled, Not enabled

15m
1: Can be set in the PLC parameter setting of GX Developer.
2: The relationships between the MC protocol formats and frames are indicated in the
following table.
Function
Communication in ASCII code
Format 4
Format 5
Communication in binary code
: Usable,
7 - 50
: Unusable
7 - 50
7 FUNCTION
MELSEC-Q
(b)
RS-232 connector specifications
The following table indicates the applications of the RS-232 connector of
the CPU module.
Appearance
5
6
Pin No.
(Q00CPU,Q01CPU side)
Signal Name
1
RD (RXD)
1
2
SD (TXD)
Send data
2
3
SG
Signal ground
3
4
Receive data

4
Mini-Din 6 pins
(female)
(c)
Signal Symbol

5
DSR (DR)
Data set ready
6
DTR (ER)
Data terminal ready
RS-232 cable
The following RS-232 cable can be used for connection of the CPU module
with the personal computer, display device or the like.
• QC30R2 (cable length: 3m)
• FKRK620(KURAMO ELECTRIC) manufactured
Cable with a mini-DIN connector on one side and without connector on
the other side
indicates the cable length, which can be specified up to 15ms in
0.1m increments
FKRK620-***
21
4
3
5
6
Signal layout of Q00CPU,Q01CPU side
connector of FRRK620-***
Effective length
7 - 51
Pin No.
1
2
3
4
5
6
Metal
Signal name
RD
SD
SG
—
DR
ER
shell
Wire core
Red
Black
—
Yellow
Brown
Shield
Green
White
7 - 51
7 FUNCTION
MELSEC-Q
(2) Functions
The serial communication function allows the MC protocol commands in the
following table to be executed.
Refer to the following manual for details of the MC protocol.
• Q-Compatible MELSEC Communication Protocol Reference Manual
Function
Command
in bits
0401 (00 1)
in words
0401 (00 0)
Batch read
Batch write
in bits
1401 (00 1)
in words
1401 (00 0)
1
Processing
Reads bit devices by 1 point.
Processing Points
ASCII: 3584 points
BIN: 7168 points
Reads bit devices by 16 points.
480 words (7680 points)
Reads word devices by 1 point.
480 words
Writes to bit devices by 1 point.
ASCII: 3584 points
BIN: 7168 points
Writes to bit devices by 16 points
480 words (7680 points)
Writes to word devices by 1 point.
480 words
Device memory
Reads bit devices by 16 points or 32 points by
Random read
in words
0403 (00 0)
designating the devices at random.
Reads word devices by 1 point or 2 points by
96 points
in bits
Test
1402 (00 1)
1
(Random write)
Sets/resets bit devices by 1 point by designating
the devices at random.
94 points
Sets/resets bit devices by 16 points or 32 points
in words
1402 (00 0)
by designating the units at random.
Writes to word devices by 1 point or 2 points by
2
Registers the bit devices to be monitored by 16
Monitor
registration
in words
0801 (00 0)
points or 32 points.
Registers the word devices to be monitored by 1
point or 2 points.
Monitor
in words
0802 (00 0)
Monitors the devices registered for monitoring.
96 points
96 points
Number of points
registered for monitor
1: When performing write during RUN of the CPU module, set write during RUN setting to "Enable".
2: Set the number of processing points within the range of the following expression.
(Number of word access points) × 12 + (number of double word access points) × 14 ≤ 960
• One point of a bit device corresponds to 16 bits for word access or to 32 bits for double word access.
• One point of a word device corresponds to one word for word access or to two words for double word access.
7 - 52
7 - 52
7 FUNCTION
MELSEC-Q
(3) Accessible devices
Class
Device
Device Number
Range 1
(Default Value)
Device Code
Internal system
Function input
FX
2
000000 to 00000F
Hexadecimal
device
Function output
FY
2
000000 to 00000F
Hexadecimal
Function register
FD
000000 to 000004
Decimal
Special relay
SM
000000 to 001023
Decimal
Special register
SD
000000 to 001023
Decimal
Internal user
Input
X
000000 to 0007FF
Hexadecimal
device
Output
Y
000000 to 0007FF
Hexadecimal
Internal relay
M
000000 to 008191
Decimal
Latch relay
L
000000 to 002047
Decimal
Annunciator
F
000000 to 001023
Decimal
Edge relay
V
000000 to 001023
Decimal
Link relay
B
000000 to 0007FF
Hexadecimal
Data register
D
000000 to 011135
Decimal
Link register
W
000000 to 0007FF
Hexadecimal
000000 to 000511
Decimal

Decimal
000000 to 000511
Decimal
Timer
Contact
TS
Coil
TC
Write
Read
Current value TN
Retentive
timer
Counter
Contact
SS
Coil
SC
Current value SN
Contact
CS
Coil
CC
Current value CN
Special link relay
SB
000000 to 0003FF
Hexadecimal
Special link register
SW
000000 to 0003FF
Hexadecimal
Step relay
S
000000 to 002047
Decimal
Direct input
DX
000000 to 0007FF
Hexadecimal
Direct output
DY
000000 to 0007FF
Hexadecimal
Index register
File register
Z
000000 to 000009
Decimal
R
000000 to 032767
Decimal
ZR
000000 to 007FFF Hexadecimal
3
: Read/write enabled,
: Write disabled
1: The device number ranges given in the above table are default values.
When you have changed the number of device points on the Q00CPU or Q01CPU, use the new device number range.
2: Undefined values enter into 000005 to 00000F of FX and FY.
3: Hexadecimal when specified for the command of the MC protocol.
7 - 53
7 - 53
7 FUNCTION
MELSEC-Q
(4) Setting of transmission specifications
Use the serial communication setting PLC parameters to set the transmission
speed, sum check, transmission wait time and write during RUN setting of the
serial communication function.
(a)
When using the serial communication function to make communication with
the personal computer, Display device or the like, specify "Use serial
communication".
(b)
The default values of the transmission speed, sum check, transmission wait
time and write during RUN setting are displayed.
You can change the transmission speed, sum check, transmission wait
time and write during RUN setting according to the specifications of the
external device.
Click here to use the serial
communication function.
Selecting "Use serial
communication" allows
you to change the settings.
(5) Instructions
(a)
Connection can be switched to GX Developer during communication with
the personal computer, Display device or the like using the serial
However, the personal computer, Display device or the like that was
making communication using the serial communication function results in a
communication error.
Refer to the manual of the used device for the way to start the personal
computer, Display device or the like when the CPU module is reconnected
with the personal computer, Display device or the like.
(b)
When "Use serial communication" is set, the transmission speed changed
on the connection target setup screen of GX Developer is not made valid.
POINT
The data set in serial communication setting is made valid when:
• The PLC is powered on; or
7 - 54
7 - 54
7 FUNCTION
MELSEC-Q
(6) Error codes for communication made using serial communication
function
The following table indicates the error codes, error definitions and corrective
actions that are sent from the CPU module to the external device when errors
occur during communication made using the serial communication function.
Error Code
(Hexadecimal)
4000H
to
4FFFH
Error Item

7153H
Frame length
error
7155H
Unregistered
monitor error
7164H
Requested data
error
7167H
7168H
Disabled during
RUN
716DH
Monitor
registration error
7E40H
Command error
7E41H
Data length error
7E42H
Data count error
7E43H
Device error
7E47H
Continuous
request error
7E4FH
Device point
count error
7E5FH
7E64H
7F01H
7F21H
7 - 55
Error Definition
Corrective Action
• Refer to the Appendices of the Basic Model
QCPU (Q Mode) User's Manual (Hardware
Design, Maintenance and Inspection), and
take corrective action.
• Reconsider the sent message.
• The length of the received message is • The number of access points of the
outside the permissible range.
message should be within the permissible
range.
• A monitor request was given before
• Give a monitor request after registering the
monitor registration was made.
device to be monitored.
• Check and correct the sent
• The requested data or device
message/requested data of the device on
specifying method is in error.
the other end, and restart communication.
• A write command was specified for the • Change the setting to write during RUN
setting of write during RUN disable.
enable and restart communication.
• The command specified cannot be
• Set the CPU module to STOP and restart
executed during RUN.
communication.
• The QnA-compatible 3C/4C frame was
• Perform monitor registration again.
not used for monitor registration.
• Check and correct the sent message of the
• The command or sub-command
device on the other end and restart
specified does not exist.
communication.
• The number of points specified for
random read/write exceeds the number device on the other end and restart
of points enabled for communication.
communication.
• The requested number of points
exceeds the range of the command.
communication.
• The device specified does not exist.
• The device specified cannot be
specified for the corresponding
communication.
command.
• Do not give continuous requests from the
device on the other end.
• The next request was received before
• Match the monitoring time of timer 1 with the
the reply message was returned.
time-out period of the device on the other
end.
• The number of access points is
incorrect.
communication.
(CPU detected error)
Error that occurred in other than the
serial communication function
Request
• The request destination module I/O
destination
module I/O
number is in error.
number error
Registered point • The number of registered points
count range error (word/bit) is outside the range.
• The next data was received before
Buffer full error
completion of received data
processing.
• The command (frame) section specified
Receive header
is in error.
section error
• The ASCII code received cannot be
converted into binary.
• Correct the module I/O number of the data
send destination.
• Correct the set value of the registered points
(word/bit).
• Perform handshake with the device on the
other end, for example, to increase the
sending intervals.
communication.
7 - 55
7 FUNCTION
Error Code
(Hexadecimal)
7F22H
7F24H
7F67H
7F69H
7F6AH
7 - 56
Error Item
Error Definition
Corrective Action
• The command or device specified does • Check and correct the sent message of the
not exist.
• The remote password length is in error. communication.
• The data (e.g. ETX, CR-LF) specified • Check and correct the sent message of the
MC protocol
after the character part does not exist
message error
or in error.
communication.
• The calculated sum check does not
• Reconsider the sum check of the device on
Sum check error
match the received sum check.
the other end.
• Reduce the communication speed and
restart communication.
• Check the CPU module for occurrence of an
• The next data was received before the
instantaneous power failure.
Overrun error
CPU module completed receive
(For the CPU module, use the special
processing.
register SD53 to check.)
When an instantaneous power failure has
occurred, remove its cause.
• Match the setting of the CPU module with
Parity error
• The parity bit setting does not match.
that of the device on the other end.
• Exercise DTR control to make
• The receive buffer of the OS overflew,
Buffer full error
communication, preventing a buffer full
resulting in skipped receive data.
error.
• Check the send message of the device on
the other end, make corrections and retry.
• Error detected by the MELSECNET/H
(The station number may have been

specified. Communication with stations on
network system.
other than MELSECNET/H or Ethernet is
not available.)
Command error
7F23H
F
MELSEC-Q
H
7 - 56
MELSEC-Q
(1) Description of intelligent function modules
Basic model QCPU allows the use of the Q series-compatible intelligent function
modules.
The intelligent function module is a module that allows Basic model QCPU to
process analog values or high-speed pulses which cannot be processed with I/O
modules.
For example, an analog value is converted into a digital value with the
analog/digital conversion module, one of the intelligent function modules, before
being used.
(2) Communication with intelligent function modules
The intelligent function module is equipped with memory (buffer memory) to store
the data received from or output to external devices.
Basic model QCPU reads/writes the data from/to the buffer memory.
8.1 Communication Between Basic model QCPU and Q-series Intelligent Function Modules
The following methods enable the communication between Basic model QCPU and
intelligent function modules:
• Initial setting or automatic refresh setting using the GX Configurator
• Intelligent function module device
• Instructions dedicated for intelligent function modules
• FROM/TO instruction
The following table shows the communication timing for the communication methods
with intelligent function modules described above:
Communication method with intelligent function modules
GX Configurator
Initial setting
Power ON
Communication timing
Instruction
Basic model
RUN
STOP
execution
QCPU reset
1
—
1
—
—
—
—
—
—
—
—
Instructions dedicated for intelligent function modules
—
—
—
—
FROM/TO instruction
—
—
—
—
Automatic refresh setting
—
—
Intelligent function module device(U
8
END
processing
\G
)
Communication timing .............. : Executed
—
—: Not executed
REMARK
1: The initial setting and automatic refresh setting of GX Configurator are stored
into the program memory or standard ROM in the Basic model QCPU.
8-1
8-1
MELSEC-Q
8.1.1 Initial setting and automatic refresh setting using GX Configurator
(1) Initial and automatic refresh settings of intelligent function modules
Installing the GX Configurator compatible with the intelligent function module
enables the initial setting and automatic refresh setting with GX Developer.
When the initial setting and automatic refresh setting of the intelligent function
module is designated with GX Developer, you can write/read data without
creating the program for the communication with the intelligent function module.
Moreover, you can conduct the initial setting or automatic refresh setting without
designating the buffer memory address of the intelligent function module.
(2) Setting using the GX Configurator
This section describes the example to set the initial setting and automatic refresh
setting of A/D conversion module Q64AD.
(a) Initial setting
The initial setting of Q64AD offers the following four settings:
• Designation of enable/disable A/D conversion
• Designation of sampling/averaging processing
• Designation of time averaging/execution averaging
• Designation of average time/average execution
The initial setting of Q64AD is designated on the following initial setting
screen of GX Configurator.
[Initial setting screen]
8
The designated initial setting data is stored in the intelligent function
module.
8-2
8-2
MELSEC-Q
(b) Automatic refresh setting
For the automatic refresh setting, designate the device at Basic model
QCPU to store the following data.
• Digital output of Q64AD
• Maximum/minimum values of Q64AD
• Error code
The automatic refresh setting of Q64AD is designated on the following
automatic refresh setting screen of GX Configurator.
[Automatic refresh setting screen]
The designated automatic refresh setting data is stored in the intelligent
function parameters of Basic model QCPU.
REMARK
For the details of the GX Configurator, refer to the manual of the intelligent function
module being used.
8-3
8-3
MELSEC-Q
8.1.2 Communication using device initial values
(1) Device initial values
Using the device initial values, the initial setting of the intelligent function module
can be made without a program.
The set device initial values are written from the Basic model QCPU to the
intelligent function module when the PLC is powered on, the Basic model QCPU
is reset, or the mode is switched from STOP to RUN.
(2) Setting of device initial values
Make the following setting using GX Developer.
• Set to the device memory the intelligent function module data to be used as the
device initial values.
• In the device initial value setting, specify the range of the intelligent function
module device to be used as the device initial values.
REMARK
1) Refer to Section 10.13.1 for the device initial values.
2) Refer to Section 10.5 for the intelligent function module device.
8.1.3 Communication using FROM/TO instructions
(1) FROM/TO instructions
When the FROM/TO instruction is executed, the data stored in the buffer
memory of the intelligent function module can be read or data can be written to
the buffer memory of the intelligent function module.
The FROM instruction stores the data read from the buffer memory of the
intelligent function module to the specified device.
REMARK
1) Refer to the following manual for details of the FROM/TO instructions.
• QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)
2) For details of the buffer memory of the intelligent function module, refer to the
manual of the used intelligent function module.
8-4
8-4
MELSEC-Q
8.1.4 Communication Using The Intelligent Function Module Device
(1) Intelligent function module device
The intelligent function module device is the buffer memory of the intelligent
function module represented as a device of Basic model QCPU program.
It enables reading data stored in the buffer memory of the intelligent function
module, or enables writing data to the buffer memory of the intelligent function
module.
For example, programming can be performed as shown below when "100" is
written to the buffer memory address 0 of the intelligent function module whose
I/O numbers are X/Y20 to X/Y2F.
[MOV
K100
U2\G0 ]
Buffer memory address
I/O number X/Y20
(2) Difference from the FROM/TO instruction
The intelligent function module device can be handled as a device of Basic
model QCPU, enabling the processing of data read from the intelligent function
module with one instruction.
For example, programming can be performed as show below when the result of
adding the data imported from the intelligent function module and the data of D0
is stored into D2.
[+
U2\GO D0 D2 ]
This saves the number of steps in the entire program.
The instruction processing time is the time obtained by adding the time for
access to/from the intelligent function modules to the instruction execution time.
POINT
When reading and processing the data of the intelligent function module frequently
in the program, use the FROM instruction to read the data at one point in the
program and store and process it in a data register, instead of using the intelligent
function module device every time.
Otherwise, the intelligent function module device accesses the intelligent function
module every time the instruction is executed, resulting in longer scan time for the
program.
REMARK
For the intelligent function module device, refer to Section 10.5.
8-5
8-5
MELSEC-Q
8.1.5 Communication Using The Instructions Dedicated for Intelligent Function Modules
(1) Description of the instructions dedicated for intelligent function
modules
(a)
The instructions dedicated for intelligent function modules are the
instructions that facilitate programming using the functions of the intelligent
function modules.
For example, the OUTPUT instruction, which is the instruction dedicated for
serial communication modules, allows data transmission in user-specified
message format with no handshaking protocol.
In this case, the communication is possible without considering the buffer
memory address of the objective serial communication module.
Serial communication module
Basic model QCPU
b15
S2
b0
Channel
1
+0
+1
+2
(b)
Channel
2
transmission
set the channel
to use by control
data
transmission
A completion device should be designated for the instruction dedicated for
The designated completion device turns ON for one scan when the
execution of the instruction dedicated for intelligent function modules is
completed.
When the completion device turns ON, another instruction dedicated for
intelligent function modules can be executed to the same intelligent function
module.
To use two or more instructions dedicated for intelligent function modules to
one intelligent function module, be sure to execute the next instruction
dedicated for intelligent function modules after the completion device turns
ON.
(2) Instructions
(a)
If the instruction dedicated for intelligent function modules are executed and
Basic model QCPU is switched from RUN to STOP before the completion
device turns ON, the completion device turns ON one scan later when
Basic model QCPU is switched to RUN next time.
REMARK
For the instruction dedicated for intelligent function modules and the completion
device, refer to the manual of the intelligent function module being used.
8-6
8-6
MELSEC-Q
8.2 Request of Intelligent Function Module to Basic Model QCPU
8.2.1 Interrupt from intelligent function module
(1) Interrupt from intelligent function module
The Basic model QCPU can execute an interrupt program (I50 to I127) at the
interrupt request of the intelligent function module.
For example, the serial communication module can perform data receive
processing in an interrupt program when either of the following data
communication functions is executed.
Data receive at communication in no-procedure protocol
Data receive at communication in bidirectional protocol
By performing data receive processing in an interrupt program, the import of
receive data to the Basic model QCPU can be speeded up.
Device on other end
of communication
Data send
Serial communication module
Receive
Interrupt issue
Main program
Main program
Basic model QCPU
Interrupt program
execution
FEND
SM400
I
BUFRCVS
(2) Setting of interrupt from intelligent function module
To execute an interrupt program by making interrupt from the intelligent function
module, "Intelligent function module setting (interrupt pointer setting) must be
made in the PLC system setting of the PLC parameter dialog box.
Also, "System setting" must be made in the intelligent function module.
When executing an interrupt program by making interrupt from the intelligent
function module, refer to the manual of the used intelligent function module.
8-7
8-7
9 PARAMETER LIST
MELSEC-Q
9 PARAMETER LIST
(1) Parameter types and setting
(a) The Basic model QCPU has two different parameter types: the "PLC
parameters" set for a system that uses the PLC independently; and the
"network parameters" set for use of MELSECNET/H, Ethernet or CC-Link.
(b) In the Basic model QCPU of function version B, the following items necessary
to configure a multiple PLC system have been added to the PLC parameters.
(Refer to Section 14.2.5)
• Multiple PLC setting
• Control CPU setting (I/O assignment)
(c) In this chapter, the PLC parameters and network parameters to be set using
GX Developer are listed in a table.
For details of each setting item, refer to the reference section or reference
manual given in the table.
For the setting operation on GX Developer, refer to the GX Developer
Operating Manual.
(2) When any PLC parameter setting has been changed, power off and then on the
PLC (ON to OFF to ON), or reset the QCPU.
If the Basic model QCPU is switched from STOP to RUN without any operation
after the PLC parameter setting change, the new parameter setting may not
became valid or PARAMETER ERROR (error code: 3000) may occur.
9
9-1
9-1
9 PARAMETER LIST
MELSEC-Q
Table 9.1 Parameter List
Item
PLC name settings
Parameter No.
—
Description
Designate the label and comment for the CPU module to be used.
These settings do not affect CPU module operation
Label
0000H
Designates the label setting (name and use).
Comment
0001H
Designates the comment setting.
PLC system settings
Timer setting
Low-Speed timer
High-Speed timer
—
1000H
These are the settings required for using the CPU module.
Default values are available for PLC control.
Designates the low-speed/high-speed timer settings
Designates the contact which controls the CPU's module
RUN-PAUSE contact
1001H
RUN/PAUSE operation.
Setting of only the PAUSE contact cannot be made. (Setting of the
RUN contact or RUN contact + PAUSE contact can be made.)
Remote reset
1002H
STOP to RUN output mode
1003H
Intelligent function module setting
(interrupt pointer setting)
Number of vacant slot points
100AH
1007H
Interrupt counter
System
interrupt
settings
In Fixed cycle
interval
program setting
Module synchronization
9
PLC file setting
PLC RAS settings
WDT
settings
1008H
WDT setting
Designates the output(Y) mode at STOP-RUN switching.
Set the assignment of the interrupt pointers (I50 to I127) and the
head I/O No. and head SI No. of the intelligent function module.
Designates the number of vacant slot points in the base/extension
base midule.
Specifies time intervals at which to execute interrupt pointers (I28
to I31).
1008H
100CH
—
Developer.
Designates the interrupt counter "first No."
(n: 28 to 31)
Interrupt program/fixed scan
Enables/disables the remote reset operation from the GX
1102H
—
3000H
Specifies whether to perform the high-speed execution of an
interrupt program.
Specifies whether to bring the start of a CPU module into
synchronization with the start of an intelligent-function module.
Set the file to be used by the CPU module.
Sets the device initial value file to be used by the CPU module.
These settings are used for the RAS function.
Set the watchdog timer of the CPU module.
Designates the CPU module operation mode to be established when
Operation mode at error occurrences
3002H
Error check
3001H
Designates whether or not to detect a specified error .
Constant scan
3003H
Designates the constant scanning time.
9-2
an error is detected.
9-2
9 PARAMETER LIST
MELSEC-Q
Default Value
Setting Range
Reference Section
—
—
—
No setting
Max. of 10 characters
—
No setting
Max. of 64 characters
—
—
—
—
100 ms
1 ms to 1000 ms(1 ms units)
Section 10.2.10
10.0 ms
0.1 ms to 100.0 ms
Section 10.2.10
No setting
X0 to X7FF
Disabled
Enabled/Disabled
Section 7.6.1
Section 7.6.2
Section 7.6.3
Previous status (produce the status of Produce the status of an output (X) before STOP/Clear the
an output (X) before STOP
output (output is 1 scan later)
No setting
Head I/O No., head SI No., I50 to I127
Section 7.4
Section 10.10
Q00JCPU: 16 points, 32 points, 64 points, 128 points,
256points
16 points
Q00CPU/Q01CPU: 16 points, 32 points, 64 points, 128
points, 256 points, 512 points, 1024
Section 5.6.1
Section 5.6.2
points
No setting
C0 to C13408 (Counter setting points can be set up to 128.)
Section 10.2.11
I28: 100.0 ms
I29: 40.0 ms
2 to 1000 ms (1 ms units)
I30: 20.0 ms
Section 10.10
I31: 10.0 ms
The high-speed execution is disabled. Enable/Disable the high-speed execution.
The start of an intelligent-function
Yes/No to synchronize the start of an intelligent-function
module is synchronized.
module.
—
—
• Not used
Not used
—
—
Section 10.13.1
• Used
—
Section 4.1.3
—
—
200 ms
10 ms to 2000 ms (10 ms units)
Section 4.2
Stop
Stop/Continue
Section 7.14
Checked
Checked/Not checked
Section 7.14
No setting
1 ms to 2000 ms(1 ms units)
Section 7.2
9-3
9-3
9 PARAMETER LIST
MELSEC-Q
Table 9.1 Parameter List (continued)
Item
Device settings
Latch (1) first/last
(Latch clear valid)
Latch (2) first/last
(Latch clear invalid)
Boot file setting
SFC program start mode
SFC
Start condition
setting
Output mode for block stop
Multiple CPU setting
Parameter No.
Description
—
These settings designate the number of points for each device, the
latch range, and the local device range
2000H
2001H
2002H
7000H
8002H
8003H
8006H
—
Number of CPUs
E00H
Operation mode
E01H
Non-group input setting
E004H
Non-group output setting
Refresh setting
9-4
E002H
E003H
Designates the number of device points used.
Set the latch range where data can be cleared by remote latch
clear operation (first device number/last device number).
Set the latch range where data cannot be cleared by remote latch
clear operation (first device number/last device number).
Set whether boot will be performed from the standard ROM or not.
Set the SFC program start mode and start condition for use of an
SFC program and the output mode for a block stop.
Make setting to configure a multiple CPU system.
Set the number of CPU modules to be used in the multiple CPU
system.
Set the operation of the multiple CPU system if the CPU modules
No. 2, No. 3 result in a stop error.
If CPU No. 1 results in a stop error, the multiple CPU system
stops. (Fixed)
Set whether the input statuses of the input modules and intelligent
function modules controlled by the other CPUs will be imported or
not.
Set whether the output statuses of the output modules controlled
by the other CPUs will be imported or not.
Set the device and its number of points used to write/read data by
automatic refresh between the CPU modules of the multiple CPU
system.
9-4
9 PARAMETER LIST
MELSEC-Q
Default Value
Setting Range
Reference Section
—
—
—
X(2 k points), Y(2 k points), S(2 k points), SB(1k points) and
SW(1 k points) are fixed.
Including the above points(1.5 k words), a total range of 16.4
k words is available.
• For one device: Max. 32 k points
(There is no restriction on the total number of bit device
points.)
Section 10.1
Section 10.2
X: 8 k points
Y: 8 k points
M: 8 k points
L: 8 k points
B: 8 k points
F: 2 k points
SB: 2 k points
V: 2 k points
S: 8 k points
T: 2 k points
ST: 0 k point
C: 1 k point
D: 12 k points
W: 8 k points
SW: 2 k points
No setting
No setting
Boot not performed
Only 1 range is designated for each device of B, F, V, T, ST,
C, D, W.
Only 1 range is designated for each device of L, B, F, V, T,
ST, C, D, W.
Boot not performed, boot performed
Section 7.3
Section 7.3
Section 6.4.1
—
Refer to the QCPU (Q mode)/QnACPU Programming Manual
(SFC).
—
—
—
—
1 module
• 1 to 3 modules
Section 14.2.1
Error of CPU No. n stops all the
CPUs.
• Error of CPU No. n stops/does not stop all the CPUs.
Section 14.2.7
Non-group input is not permitted.
• Non-group input is permitted/not permitted.
Section 17.2
Non-group output is not permitted.
• Non-group output is permitted/not permitted.
Section 17.2
No setting
• Send range for each CPU module:
0 to 320 points (in units of 2 points)/module
Maximum 4416/system
• CPU module side devices: B, M, Y, D, R, ZR
The device of points set in the send range is occupied,
starting from the specified device number.
• When the send range is 1 point, B, M or Y occupies 16
points.
• When the send range is 1 point, D, W, R or ZR occupies 1
point.
Section 16.1
9-5
9-5
9 PARAMETER LIST
MELSEC-Q
Item
I/O allocations
Parameter No.
Description
—
Designates the installation status for each system module.
Type
Set the type of the module loaded.
Model name
Set the model name of the module loaded.
(CPU module not used. User's memo)
I/O allocation
400H
Points
Set the number of points of the corresponding slot.
Start XY
(First I/O number)
Set the first I/O number of the corresponding slot.
Base model name
Base setting
Power model
name
401H
Increase cable
name
Slots
Switch setting
Detailed
setting
407H
Error time output
module
H/W error time
PLC operation
mode
403H
4004H
I/O response time
405H
Control CPU
406H
X/Y allocation check
—
Serial communication setting
—
Use of serial communication
function
Message wait time
Write during RUN setting
9-6
Set the response times of the input, high-speed input, hybrid I/O
and interrupt modules.
Set the control CPU of the I/O or intelligent function module.
Enables the user to check I/O assignments,
MELSECNET/ETHERNET settings, and CC-Link settings.
Set the transmission speed, sum check, message wait time and
write during RUN enable/disable when using the serial
communication function of Q00/Q01CPU.
Using the serial communication function turns on the check box.
Baudrate
Sum check
Set the model name of the main or extension base unit used.
(CPU module not used. User's memo)
Set the model name of the power supply module loaded on the
main or extension base unit. (CPU module not used. User's
memo)
Set the extension cable model name. (CPU module not used.
User's memo)
Set the number of slots of the main or extension base unit.
Set the number of slots to all base units.
Set various switches of the intelligent function module.
Set whether the output will be cleared or held when the control
CPU results in a stop error.
Set whether the operation of the control CPU will be stopped or
continued when the hardware fault of the intelligent function
module occurs.
100EH
Set the transmission speed for data communication with the
device on the other end
Set whether to add the sum check code to the send and receive
messages according to the specifications of the device on the
other end when making data communication using the serial
Set the waiting time of the CPU module when data cannot be
received immediately after the device on the other end has sent
the data.
Set whether data will be written or not from the other end device to
the CPU module if the CPU module is during RUN.
9-6
9 PARAMETER LIST
Default Value
—
No setting
No setting
MELSEC-Q
Setting Range
—
• CPU No. 2 to No. 3: No. n/Empty (Set "CPU (Empty)" for
the slot not mounted with a CPU module.)
• Input, High-speed input, Output, Intelligent, Hybrid I/O,
Interrupt
Reference Section
—
• 16 characters
• Q00JCPU
No setting
• Q00CPU, Q01CPU
No setting
• Q 00JCPU
• Q00CPU, Q01CPU
No setting
• 16 characters
No setting
• 16 characters
: 0 points, 16 points, 32 points,
48 points, 64 points, 128 points,
256 points
: 0 points, 16 points, 32 points,
48 points, 64 points, 128 points,
256 points, 512 points, 1024 points
: 0H to F0H
: 0H to 3F0H
Section 5.6
Section 5.3
No setting
• 16 characters
No setting
• 2, 3, 5, 8, 10, 12
No setting
• Refer to the manual of the intelligent function module used.
Section 7.10
Clear
• Clear/Retain
Section 7.8
Stop
• Stop/Continue
Section 7.9
• Input, I/O combined
: 1ms, 5ms, 10ms, 20ms, 70ms
• High-speed input, Interrupt : 0.1ms, 0.2ms, 0.4ms, 0.6ms,
1ms
• No. 1, No. 2, No. 3
Section 14.2.5
—
—
—
—
—
—
—
Input, I/O combined: 10ms
High-speed input, Interrupt: 0.2ms
No. 1
19.2kbps
9.6 kbps/19.2 kbps/38.4 kbps/57.6 kbps/115.2 kbps
Yes
No/Yes
No wait
No wait/10ms to 150ms (10ms increments)
Not enabled
Not enabled/Enabled
Section 7.7
Section 7.17
9-7
9-7
9 PARAMETER LIST
MELSEC-Q
Item
Parameter No.
Network parameters
MELSECNET/H setting 1 2
5000H
Number of modules setting
Head I/O No.
5NM0H
Network No.
Total number of link slave stations
05mnH
Group No.
Valid module for other station
5001H
access
5003H
Routing parameter
5NM0H
Network setting
5NM1H
Network refresh parameter
5NM2H
Common parameter
5NM3H
Station-specific parameter
5NMAH
Common parameter 2
5NMBH
Station-specific parameter 2
5NMBH
Interrupt setting
Ethernet setting 1
9000H
Head I/O No.
9N00H
Network No.
Operation setting
9N01H
Initial setting
9N02H
Open setting
9N03H
Router relay parameter
9N04H
Routing parameter
station number related
IP
9N05H
information
9N06H
FTP parameter
9N07H
E-mail setting
9N08H
Notification setting
9N09H
Interrupt setting
CC-Link setting 3
C000H
Remote input (RX) refresh device
Remote output (RY) refresh device
Remote register (RWr) refresh
device
CNM1H
Remote register (RWw) refresh
device
Special relay (SB) refresh device
Special register (SW) refresh device
Head I/O No.
Total number of connected stations
Number of retry times
Number of stations that
automatically return to system
CNM2H
Standby master station number
CPU fault designation
Scan mode designation
Delay time setting
Station information setting
Remote device station initial setting
CNM2H
Interrupt setting
9-8
Description
Set the parameters for MELSECNET/H, Ethernet or CC-Link.
Set the network parameters of MELSECNET/H.
Set the network parameters of Ethernet.
Set the network parameters of CC-Link.
9-8
9 PARAMETER LIST
MELSEC-Q
Default Value
—
Setting Range
—
Reference Section
—
No setting
Refer to the Q Corresponding MELSECNET/H Manual.
—
No setting
Refer to the Q Corresponding Ethernet Manual.
—
No setting
Refer to the CC-Link Manual.
—
9-9
9-9
9 PARAMETER LIST
MELSEC-Q
Item
Parameter No.
Description
Detailed setting
User connection No. valid setting
—
—
Set the remote password for the Ethernet, serial communication or
modem interface module.
Enter the remote password.
Select the module model name to be checked for the remote
password set to the QCPU.
Set the head address of the module to be checked for the remote
password.
—
Set the user connection No.
System connection valid setting
—
Set the remote password valid port of the system connection.
Remote password
Password setting
Password valid
module setting
9 - 10
—
Model name
—
Head X/Y
—
9 - 10
9 PARAMETER LIST
MELSEC-Q
Default Value
No
4 bytes, alphanumeric characters, special symbols
No
QJ71E71/QJ71C26/QJ71CMO
No
0000H to 03E0H
—
No
—
Connection No. 1 to connection No. 16
Specify the remote password valid port.
• Automatic open UDP port
• FTP communication port (TCP/IP)
• GX Developer communication port (TCP/IP)
• GX Developer communication port (UDP/IP)
• HTTP port
No
9 - 11
Setting Range
Reference Section
Section 7.16.2
9 - 11
9 PARAMETER LIST
MELSEC-Q
1: N and M indicate the following.
N: Indicates the serial number of the module.
M: Indicates the network type.
M
Network Type
1H
MELSECNET/10 mode (control station), MELSECNET/H mode (control station)
2H
MELSECNET/10 mode (normal station), MELSECNET/H mode (normal station)
3H
MELSECNET/10 mode (control station)
4H
MELSECNET/10 mode (normal station)
2: m and n indicate (head I/O No. / 16).
3: N and M indicate the following.
N: Indicates the serial number of the module.
M: Indicates the network type.
M
Network Type
0H
Master station
1H
Local station
9 - 12
9 - 12
10 DEVICES
MELSEC-Q
10 DEVICES
This chapter describes all devices that can be used in Basic model QCPU.
10.1 Device List
The names and data ranges of devices which can be used in Basic model QCPU are
shown in Table 10.1 below.
Table 10.1 Device List
Parameter
Designated
Setting Range
Default Values
Class
Type
Device Name
Input
1
2048 points
X0 to X7FF
Section 10.2.1
Y0 to Y7FF
Section 10.2.2
Internal relay
8192 points
M0 to M8191
Section 10.2.3
Latch relay
2048 points
L0 to L2047
Section 10.2.4
Anunciator
1024 points
F0 to F1023
Section 10.2.5
Edge relay
1024 points
V0 to V1023
Section 10.2.6
2048 points
S0 to S127/block
Section 10.2.9
2048 points
B0 to B7FF
1024 points
SB0 to SB3FF
1
1
Step relay
Internal user
devices
Link relay
1
Special link relay
Timer
2
Retentive timer
Word devices
Counter
2
2
(ST0 to ST511)
Section 10.2.10
512 points
C0 to C511
D0 to D11135
Section 10.2.12
Link register
2048 points
W0 to W7FF
Section 10.2.13
1024 points
SW0 to SW3FF
Section 10.2.14
Function output
Special relay
Word devices
T0 to T511
0 points
11136 points
Function input
Bit devices
512 points
Change possible
for 16.4 k words or Section 10.2.7
3
less.
Section 10.2.8
Data register
Link special register
Internal
system
devices
Range Used
2048 points
Output
Bit devices
Number of Points
Reference
Section
1
16 points
16 points
1000 points
Section 10.2.11
FX0 to FXF
3
FY0 to FYF
3
SM0 to SM999
Section 10.3.1
Section 10.3.1
Impossible
Section 10.3.2
Function register
5 points
FD0 to FD4
Section 10.3.1
Special register
1000 points
SD0 to SD999
Section 10.3.3
REMARK
1: For the inputs, outputs, step relays, special link relays and special link registers,
their default values cannot be changed.
2: For the timers, retentive timers and counters, their contacts and coils are bit
devices and their current values are word devices.
3: Only FX0 to FX4 and FY0 to FY4 can be used in programs.
10
10 - 1
10 - 1
10 DEVICES
MELSEC-Q
Default Values
Class
Link direct
devices
Type
Bit device
Device Name
Range Used
Link input
8192 points
Jn\X0 to Jn\X1FFF
Link output
8192 points
Jn\Y0 to Jn\Y1FFF
Link relay
16384 points
Jn\B0 to Jn\B3FFF
512 points
Jn\SB0 to Jn\SB1FF
Link special relay
Word device
Number of Points
Link register
16384 points
Jn\W0 to Jn\W3FFF
512 points
Jn\SW0 to Jn\SW1FF
Parameter
Designated
Setting Range
Reference
Section
Impossible
Section 10.4
Intelligent
function
module
device
Word device
Buffer register
65536 points
Un\G0 to
4
Un\G65535
Impossible
Section 10.5
Index
register
Word device
Index register
10 points
Z0 to Z9
Impossible
Section 10.6
Q00JCPU
0 points
——
File register
Word device
File register
Q00CPU,
Q01CPU
R0 to R32767
ZR0 to ZR65535
Impossible
Section 10.7
64k points
Impossible
Section 10.8
Nesting
Pointers
——
——
Bit device
Other
——
——
Nesting
15 points
N0 to N14
Pointer
300 points
P0 to P299
Interrupt pointer
128 points
I0 to I127
SFC block device
128 points
BL0 to BL127
Network No
239 points
J1 to J239
Q00JCPU
I/O No
Q00CPU,
Q01CPU
Macro instruction
argument device
——
Real number constant
Character string
constants
Impossible
VD0 to VD
Impossible
K-2147483648 to K2147483647
1.17550
38 to E
Section 10.11.1
3.40282
"ABC" and "123"
5
Section 10.11.3
Section 10.11.4
Section 10.12.1
H0 to HFFFFFFFF
E
Section 10.9
Section 10.10
Section 10.11.2
U0 to 3F
Hexadecimal constants
——
Impossible
U0 to UF
——
Decimal constants
Constants
Impossible
Section 10.12.2
38
Section 10.12.3
Section 10.12.4
REMARK
4: The number of actually usable points changes depending on the intelligent
function module. For the number of buffer memory points, refer to the manual of
the intelligent function module used.
5: Character strings can be used with only the $MOV instruction.
They cannot be used with other instructions.
10
10 - 2
10 - 2
10 DEVICES
MELSEC-Q
10.2 Internal User Devices
Internal user devices can be used for various user applications.
The "number of usable points" setting is designated in advance (default value) for
internal user devices.
However, this setting can be changed by PLC parameter device setting.
[Device setting screen]
Default value
"Dev. point" can be changed
at devices where a "Dev. point"
value is shown in brackets.
(1) Setting range in the internal user device
For all Basic model QCPU internal user devices other than the input (X), output
(Y), step relay (S), special link relay, and special link registers (SW) devices, the
number of points used can be changed within a 16.4 k word (including 1.5k
words for an internal user device) range by PLC parameter device setting.
The items to consider when making such changes are discussed below.
(a) Setting range
1) The number of device points is designated in 16-point units.
2)
A maximum of 32 k points can be designated for one type of device.
1 point is calculated as 2 points (1 for coil, 1 for contact) for the timer,
retentive timer, and counter.
(2) Memory size
Use the following formula to obtain the memory size of an internal user device.
1.5 + (Bit devices size) + (Word devices size) + (Timer, retentive timer and counter size)
(a)
For bit devices:
For bit devices, 16 points are calculated as 1 word.
(Bit device size) =
10 - 3
16.4k
(M+L+F+V+B total number of points)
16
(Word)
10 - 3
10 DEVICES
MELSEC-Q
(b)
For timer (T) retentive timer (ST), and Counter (C):
For the timer, retentive timer, and counter, 16 points are calculated as 18
words.
(Timer, retentive, counter size) =
(c)
(T, ST, C total number of points)
16
18 (Word)
For word devices:
For data registers (D) and link registers (W), 16 points are calculated as 16
words.
(Word device size) =
(D, W total number of points)
16
16 (Word)
POINT
When the number of internal user device points used is changed in the parameter,
the following files created with the previous parameter setting cannot be used as
they are.
• Sequence program
• SFC program
After changing the number of internal user device points used, read the sequence
program and SFC program from the Basic model QCPU to GX Developer, and
write them again to the Basic model QCPU.
10 - 4
10 - 4
10 DEVICES
MELSEC-Q
10.2.1 Inputs (X)
(1) Definition
(a)
Inputs are commands or data transmitted to the Basic model QCPU from a
peripheral device by push-button switches, selector switches, limit switches,
digital switches, etc.
Push-button switch
Selector switch
Input (X)
Sequence
operation
Digital switch
1
(b)
2
3
The input point is the Xn virtual relay inside the Basic model QCPU, with the
program using the Xn's N/O contact or N/C contact.
Virtual relay
PB1
X0
Programmable
controller
X0
LS2
X1
X1
PB16
XF
XF
Input ladder (external device)
Program
Figure 10.1 Inputs(X)
(c)
There are no restrictions regarding the number of Xn N/O contacts and N/C
contacts used in a program.
No restrictions regarding
the quantity used.
X0
X2
X0
X1
X2
Y21
X0
Y20
Y21
Y23
Figure 10.2 Input(X) Used in Program
10 - 5
10 - 5
10 DEVICES
MELSEC-Q
(2) Reading the inputs
(a)
There are 2 types of input: "refresh inputs" and "direct access inputs".
1) Refresh inputs are ON/OFF data read from the input module using the
refresh mode. 1
Basic model QCPU
Device memory
Read of ON/OFF data
by input refresh
Input module
0
X10
2)
These inputs are indicated as "X " in the sequence program. For
example, a "10" input becomes "X10".
Direct access inputs are ON/OFF data read from the input module
using the direct mode. 2
Basic model QCPU
Device memory
Read of ON/OFF data
at instruction execution
Input module
0
DX10
ON/OFF
data
These inputs are indicated as "DX " in the sequence program.
For example, a "10" input becomes "DX10".
Direct access input can be made in a LD/AND/OR instruction that uses
an input in units of 1 point.
(b) Differences between refresh input and direct access input
Since the direct access input accesses the input module directly at
instruction execution, it imports an input faster than the refresh input.
However, the direct access input takes longer instruction processing time
than the refresh input.
Moreover, direct access inputs can only be used for inputs used with the
input module and intelligent/special function module which are installed at
main and extension base unit.
The refresh and direct input differences are shown in Table 10.2 below.
Table 10.2 Differences Between Refresh
Item
Input module installed at base/extension
base unit
Inputs of intelligent function module
installed at base/extension base unit
Inputs of I/O link module installed at
base/extension base unit
Inputs used at MELSECNET/H network
system or CC-Link system
Refresh Input
Direct Access Inputs
Usable
Usable
Usable
Unusable
REMARK
1: See Section 4.7.1 for details regarding the refresh mode.
10 - 6
10 - 6
10 DEVICES
MELSEC-Q
(c)
The same input number can be designated for a refresh input and a direct
access input.
The ON/OFF data read at the direct access input (DX) is also stored into
the device memory. (Refer to Section 10.2.1 (2).)
When refresh input is used after use of the direct access input (DX),
operation is performed using the ON/OFF data of the device memory
(ON/OFF data read at the direct access input (DX)).
Operation is performed using the ON/OFF data
read at the input refresh before the operation
start of the sequence program.
X0
Y10
DX0
Y11
Direct access input
Operation is based on the ON/OFF
data read at the input module.
Operation is based on the ON/OFF data read at
the direct access input.
X0
Y12
Figure 10.3 Refresh Input & Direct Access Input
POINT
(1) When debugging a program, an input (X) can be set to ON/OFF as described
below.
• OUT Xn instruction
OUT X1
ON/OFF command
X1
• Device test of GX Developer
(2) With the CC-Link, an input (x) can be designated as a destination device for the
• RX refresh (on Basic model QCPU side) by using a CC-Link automatic refresh
setting.
• Refresh destination (Basic model QCPU side) device of link input of
MELSECNET/H
10 - 7
10 - 7
10 DEVICES
MELSEC-Q
10.2.2 Outputs (Y)
(1) Definition
(a)
Outputs are program control results which are output to external
destinations (solenoid, electromagnetic switch, signal lamp, digital display,
etc.).
Signal lamp
Output (Y)
Digital display
Sequence
operation
Contact
(b)
Outputs occur at one N/O contact or its equivalent.
(c)
There are no restrictions regarding the number of output Yn N/O contacts
and N/C contacts used in a program.
Programmable No restrictions regarding the quantity used.
controller
Load
X0
M51
Y20
Y20
X1
Y20
Y20
X3
X2
Y21
Y22
Program
Out ladder (external device)
Figure 10.4 Output(Y) Operation
(2) Using outputs as internal relays (M)
Power supply module
CPU module
Input module
Input module
Output module
Output module
Output module
"Y" inputs corresponding to vacant slots and slots where input modules are
installed can serve as internal relays (M).
OUT Yn
Equivalent to internal relay
10 - 8
10 - 8
10 DEVICES
MELSEC-Q
(3) Output method
(a)
There are 2 types of output: "refresh outputs" and "direct access outputs".
1) Refresh outputs are ON/OFF data which is output to the output module
using the refresh mode. 1
Basic model QCPU
Device memory
Output module
Output of ON/OFF data
by output refresh
0
Y10
2)
These outputs are indicated as "Y " in the sequence program.
For example, a "10" input becomes "Y10".
Direct access outputs are ON/OFF data which is output to the output
module using the direct mode. 2
Basic model QCPU
Output module
Output of ON/OFF data
at instruction execution
Device memory
0
DY10
ON/OFF
data
These outputs are indicated as "DY " in the sequence program.
For example, a "10" input becomes "DY10".
(b)
Differences between refresh outputs and direct access outputs
With direct access outputs, the output module is directly accessed by
executing an instruction, and the processing speed is therefore slower
than that for refresh outputs.
A refresh output takes longer to process instructions than a direct
access output.
Moreover, direct access outputs can only be used for outputs used with
the output module and intelligent function module which are installed at
base unit and extension base unit.
The refresh and direct output differences are shown in Table 10.3 below.
Table 10.3 Differences Between Refresh Outputs & Direct Access Outputs
Item
Output module installed at main/extension
base unit
Outputs of intelligent function module
installed at base/extension base unit
Outputs used at MELSECNET/H network
system or CC-Link system
Refresh Input
Direct Access Outputs
Usable
Usable
Usable
Unusable
REMARK
1: See Section 4.7.1 for details regarding the refresh mode.
10 - 9
10 - 9
10 DEVICES
MELSEC-Q
10.2.3 Internal relays (M)
(1) Definition
(a)
Internal relays are auxiliary relays which cannot be latched by the
programmable controller's internal latch (memory backup).
All internal relays are switched OFF at the following times:
• When power at OFF is switched ON.
• When reset is executed.
• When latch clear is executed.
(b)
There are no restrictions regarding the number of contacts (N/O contacts,
N/C contacts) used in the program.
No restrictions regarding the quantity used.
M0 switches ON at X0 OFF to ON
X0
SET
M0
M0
K20
T0
Y20
The internal relay (M0) ON can only be used for internal
Basic model QCPU processing, and cannot be output
externally.
M0 ON/OFF information is output from the output module
to an external destination.
X1 M0
M100
X2 M0
M2047
Figure 10.5 Internal Relay
(2) Procedure for external outputs
Outputs (Y) are used to output sequence program operation results to an
external destination.
REMARK
1) When latch (memory backup) is required, use the latch relays (L).
Refer to Section 10.2.4 for the latch relays.
10 - 10
10 - 10
10 DEVICES
MELSEC-Q
10.2.4 Latch relays (L)
(1) Definition
(a) Latch relays are auxiliary relays which can be latched by the programmable
controller's internal latch (memory backup).
Latch relay operation results (ON/OFF information) are saved even in the
following cases:
• When power at OFF is switched ON.
• When reset operation is performed.
The latch is backed up by the Basic model QCPU battery.
(b)
Performing remote latch clear using GX Developer turns OFF the latch
relay. However, the latch relay that has been set to "Latch (2): Cannot be
cleared by latch clear" in the device setting PLC parameters cannot be
turned OFF if remote latch clear is performed.
(c)
L0 switches ON at X0 OFF to ON.
X0
SET
L0
L0
K20
T0
Y20
X1
The latch relay (L0) ON can only be used for internal
Basic model QCPU processing, and cannot be output
externally.
L0 ON/OFF information is output from the output
module to an external destination.
L0
L100
X2
L0
L2047
Figure 10.6 Latch Relay
(2) Procedure for external outputs
Outputs (Y) are used to output sequence program operation results to an
external destination.
REMARK
Internal relays (M) should be used when a latch (memory backup) is not required.
See Section 10.2.3 for details regarding internal relays.
10 - 11
10 - 11
10 DEVICES
MELSEC-Q
10.2.5 Anunciators (F)
(1) Definition
(a)
Anunciators are internal relays used by the user in fault detection program.
(b)
When anunciators switch ON, a special relay (SM62) switches ON, and the
Nos. and quantity of anunciators which switched ON are stored at the
special registers (SD62 to SD79).
At this time, the "ERR." LED is lit.
• Special relay :SM62.................... Switches ON if even one anunciator
switches ON.
• Special register:SD62 ................... No. of first anunciator which switched
ON is stored here.
SD63................... The number (quantity) of anunciators
which are ON is stored here.
SD64 to SD79 .... Anunciator Nos. are stored in the order
in which they switched ON.
(The same anunciator No. is stored at
SD62 and SD64.)
The anunciator No. stored at SD62 is also registered in the "fault history
area".
However, only one annunciator number is stored into the failure history
storage area while the PLC power is ON.
(c)
The use of anunciators in the fault detection program permits the user to
check for the presence/absence of fault and to check the fault content
(anunciator No.), by monitoring the special registers(SD62 to SD79) when
the special relay(SM62) switches ON.
Example
The program which outputs the No. of the ON annunciator (F5) is shown below.
[Fault detection program]
X0
X10
SET
F5
SM62
BCDP SD62 K4Y20
Output of annunciator
No. which switched ON
SM62
SD62
SD63
SD64
SD65
SD79
OFF to ON
0 to 5
0 to 1
0 to 5
0
0
Annunciator ON detection
10 - 12
10 - 12
10 DEVICES
MELSEC-Q
(2) Annunciator ON procedure and processing
(a)
Anunciator ON procedure
Anunciator operation can be controlled by the SET F and OUT
F instructions.
1) The SET F instruction switches the anunciator ON only at the leading
edge (OFF to ON) of the input condition, and keeps the anunciator ON
when the input condition switches OFF.
In cases where many anunciators are used, the OUT F instruction
can be used to speed up the scan time.
2)
The OUT F instruction can switch the anunciator ON or OFF. It takes
longer to do so than the SET F instruction. If the anunciator is
switched OFF by using an OUT F instruction, this will require the
execution of an RST F or BKRST instruction. Use a SET F
instruction to switch the anunciator ON.
POINT
If switched ON by any method other than the SET F and OUT F instructions,
the anunciator functions in the same way as the internal relay.
(Does not switch ON at SM62, and anunciator Nos. are not stored at SD62, SD64
to SD79.)
(b)
Processing at anunciator ON
1) Data stored at special registers (SD62 to SD79)
a) Nos. of anunciators which switched ON are stored in order at
SD64 to SD79.
b) The anunciator No. which was stored at SD64 is stored at SD62.
c) "1" is added to the SD63 value.
SET F50
2)
3)
SET F25 SET F1023
SD62
0
50
50
50
SD63
0
1
2
3
SD64
0
50
50
50
SD65
0
0
25
25
SD66
0
0
0
1023
SD67
0
0
0
0
SD79
0
0
0
0
Up to 16 annunciator
No. can be stored.
CPU LED indication
When any annunciator turns ON, the "ERR." LED on the front of the
Basic model QCPU is lit.
Setting the display priority for error occurrence to SD207 - SD209
allows you to select whether the ERR. LED is to be ON or OFF when
the annunciator turns ON.
(3) Anunciator OFF procedure & processing content
(a)
Anunciator OFF procedure
An anunciator can be switched OFF by the RST F , BKRST, and OUT F
instructions.
1) An anunciator No. which has been switched ON by the SET F
instruction can be switched OFF by the RST F instruction.
2)
10 - 13
Use the BKRST instruction if you want to switch all the anunciator Nos.
within a specified range.
10 - 13
10 DEVICES
MELSEC-Q
3)
The OUT F instruction can execute ON/OFF of the anunciator No. by
the same instruction.
However, if an anunciator is switched OFF by the OUT F instruction,
the "processing at anunciator OFF" (item (b) below) does not occur.
Execute the RST F or BKRST instructions after the anunciator has
been switched OFF by the OUT F instruction.
1) To switch OFF the annunciators 5 (F5)
Fault detection program
(Annunciator ON program)
Display reset input
RST F5
Program that turns OFF
annunciator 5 (F5)
2) To switch OFF all anunciators which are ON:
Fault detection program
(Annunciator ON program)
Display reset input
BKRSTP F0 K10
F0 to F9 OFF program
REMARK
For details regarding the RST and BKRST instruction, refer to the QCPU(Q
mode)/QnACPU Programming Manual(Common Instructions).
10 - 14
10 - 14
10 DEVICES
MELSEC-Q
(b)
Processing at anunciator OFF
1) Special register (SD62 to SD79) data operation when an anunciator is
switched OFF by the RST F instruction
a) The anunciator No. which was switched OFF is deleted, and all
subsequent anunciator Nos. are moved up to fill the vacant space.
b) If the anunciator No. stored at SD64 was switched OFF, the new
anunciator No. which is stored at SD64 is stored at SD62.
c) "-1" is subtracted from the SD63 value.
d) If the SD63 value is "0", SM62 is switched OFF.
SET F50
10 - 15
SET F25 SET F1023 RST F50
SD62
0
50
50
50
SD63
0
1
2
3
25
2
SD64
0
50
50
50
25
SD65
0
0
25
25
1023
SD66
0
0
0
1023
0
SD67
0
0
0
0
0
SD79
0
0
0
0
0
2)
Data stored in special registers (SD62 to SD79) when annunciator is
turned OFF by execution of BKRST instruction
a) The annunciator number specified in the BKRST instruction is
deleted and the annunciator numbers stored after the deleted one
are shifted up.
b) If the annunciator number stored in SD64 is turned OFF, the
annunciator number newly stored in SD64 is stored into SD62.
c) The data of SD63 is decremented by the number of reset
annunciators.
d) If the data of SD63 is 0, SM62 is turned OFF.
3)
LED indication
When all annunciator numbers in SD64 to SD79 turn OFF, the "ERR."
LED is extinguished.
10 - 15
10 DEVICES
MELSEC-Q
10.2.6 Edge relay (V)
(1) Definition
(a)
An edge relay is a device which stores the operation results (ON/OFF
information) from the beginning of the ladder block.
Edge relays can only be used at contacts, and cannot be used as coils.
X0
X1
X10
V1
Edge relay
Stores the X0, X1 and X10 operation results
(b)
The same edge relay number cannot be used twice in program executed by
(2) Edge relay applications
Edge relays are used for detecting the leading edge (OFF to ON) in program
configured using index qualification.
[Ladder example]
SM400
Index register (Z1) OFF
MOV K0 Z1
*1
X0Z1
Repetition (10 times) designation
FOR K10
*1
V0Z1
M0Z1
1 scan ON at X0 leading edge
SM400
INC
Increment Index Register (Z1) (+1)
Z1
Return to FOR instruction
NEXT
[Timing chart]
ON
X0 OFF
ON
When Z1=0
V0 OFF
ON
M0 OFF
1 Scan
ON
X1 OFF
ON
When Z1=1
1 scan ON at X1 leading edge
V1 OFF
ON
M1 OFF
1 Scan
REMARK
1)
10 - 16
1: The ON/OFF information for X0Z1 is stored at the V0Z1 edge relay.
For example, the X0 ON/OFF information is stored at V0, and the X1
ON/OFF information is stored at V1.
10 - 16
10 DEVICES
MELSEC-Q
10.2.7 Link relays (B)
(1) Definition
(a)
A link relay is the Basic model QCPU relay used to refresh the Basic model
QCPU from the MELSECNET/H network module's link relay (LB) and to
refresh the MELSECNET/H network module's link relay (LB) from the Basic
model QCPU data.
MELSECNET/H network module
Basic model QCPU
Link relay
Link relay
LB0
B0
Link refresh setting range
Link refresh
Internal relays or latch relays can be used for data ranges not used by the
MELSECNET/H network system.
• Range where no link relay latch occurs...Internal relay
• Range where link relay latch occurs........Latch relay
(b)
B0 switches ON at X0 OFF to ON.
X0
SET
B0
K20
T0
B0
Y20
X1
The link relay (B0) ON can only be used for internal Basic
model QCPU processing, and cannot be output externally.
B0 ON/OFF information is output from the output module
to an external destination.
B0
B100
X2
B0
B1FFF
Figure 10.7 Link Relay
(2) Using link relays in the network system
In order to use link relays in the network system, a network parameter setting is
required.
REMARK
1) For details regarding the network parameters, refer to the For Qs MELSECNET/H
Network System Reference Manual.
2) The MELSECNET/H Network Module has 16384 link relay points assigned.
Basic model QCPU has 8192 link relay points assigned. When using subsequent
points after Point 8192, change the number of link relay points by using the
Device Setting sheet of the PLC Parameter dialog box.
10 - 17
10 - 17
10 DEVICES
MELSEC-Q
10.2.8 Special link relays (SB)
(1) Definition
(a)
A special link relay indicates the communication status and error detection
of an intelligent function module, such as the MELSECNET/10H Network
Module.
(b)
Because special link relays are switched ON and OFF in accordance with
various problems which may occur during a data link, they serve as a tool
for identifying data link problems.
(2) Number of special link relay points
There are a total of 1024 special link relay points between SB0 and SB3FF.
Special link relays are assigned at a rate of 512 points per each intelligent
function module, such as the MELSECNET/10H Network Module.
REMARK
1) For details regarding special link relays used at the Basic model QCPU, refer to
the QCPU (Q mode)/QnACPU Programming Manual (Common Instructions).
10.2.9 Step relays (S)
The step relays are devices designed for SFC.
Refer to the following manual for the step relay using method.
• QCPU (Q mode)/QnACPU Programming Manual (SFC)
POINT
The step relays cannot be used in place of the internal relays in sequence
programs since the step relays are exclusively designed for SFC programs.
If the step relays are used in place of the internal relays in a sequence program, an
SFC error may occur, resulting in a system fault.
10 - 18
10 - 18
10 DEVICES
MELSEC-Q
10.2.10 Timers (T)
Timers are of a forward timer type, with the time measurement beginning when the coil
switches ON, and ending (time out) when the present value exceeds the setting value.
The present value matches the setting value when a "time-out" occurs.
There are two types of timers: a low/high-speed that allows the current value to return
to "0" when a timer coil switches OFF, and a retentive timer that retains the current
value even when a timer coil switches OFF.
Timers
Timers
Low-speed timers
High-speed timers
Retentive timers
Low-speed retentive timers
High-speed retentive timers
With a timer setting (instruction format), a device is assigned for a low-speed timer or
high-speed timer. The OUT T0 instruction is used to assign a device for a low -speed
timer. The OUTH T0 instruction is used to assign a device for a high-speed timer.
With a timer setting (instruction format), a device is assigned for a low-speed retentive
timer or high-speed retentive timer. The OUT T0 instruction is used to assign a device
for a low-speed retentive timer. The OUTH T0 instruction is used to assign a device for
a high-speed retentive timer.
Low-speed timers
(1) Definition
(a)
Low-speed timers are those that are only operative while the coil is ON.
(b)
The time measurement begins when the timer's coil switches ON, and the
contact switches ON when a "time-out" occurs. When the timer's coil
switches OFF, the present value becomes "0", and the contact switches
OFF.
[Ladder example]
X0
When X0 switches ON, the T0 coil switches ON, and the
contact switches ON 1 second later. (The low-speed timer
measures time in 100 ms units.)
K10
T0
[Time chart]
ON
X0
OFF
T0 coil
OFF
ON
1 Sec.
ON
T0 contact
OFF
(2) Measurement units
(a)
The default time measurement units setting for low-speed timers is 100 ms.
(b) The time measurement units setting can be designated in 1 ms units within a
1 ms to 1000 ms range.
This setting is designated in the "PLC system settings" in the PLC
parameter setting.
10 - 19
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10 DEVICES
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High-speed timers
(1) Definition
(a)
High-speed timers are timers which are only operative while the coil is ON.
A high-speed timer is marked with a symbol "H".
(b)
The time measurement begins when the timer's coil switches ON, and the
contact switches ON when the time elapses. When the timer's coil switches
OFF, the present value becomes "0", and the contact switches OFF.
[Ladder example]
High-speed timer display
H
K200
T200
X0
When X0 switches ON, the T200 coil switches ON, and
the contact switches ON 2 second later. (The high-speed
timer measures time in 10 ms units.)
[Time chart]
ON
X0
OFF
T200 coil
OFF
ON
2 Sec.
ON
T200 contact
OFF
10 - 20
(a)
The default time measurement units setting for high-speed timers is
10 ms.
(b)
The time measurement units setting can be designated in 0.1ms units within
a 0.1 ms to 100 ms range.
This setting is designated in the PLC system settings in the PLC parameter
setting.
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10 DEVICES
MELSEC-Q
Retentive timers
(1) Definition
(a)
Retentive timers measure the "coil ON" time.
(b)
The measurement begins when the timer coil switches ON, and the contact
switches ON when a time-out (coil OFF) occurs.
Even when the timer coil is OFF, the present value and the contact
ON/OFF status are saved. When the coil is switched ON again, the time
measurement resumes from the present value which was saved.
(c)
There are 2 retentive timer types: low-speed retentive timer, and high-speed
retentive timer.
(d)
The RST T instruction is used to clear (reset) the present value and
switch the contact OFF.
[Ladder example]
X0
K200
ST0
X0 ON time is measured as 20 seconds when the timer
measures time in 100 ms units.
Retentive timer display
X1
When X1 switches ON, the ST0 contact is reset, and
the present value is cleared.
RST ST0
[Time chart]
ON
X0
OFF
T0 coil
OFF
ON
15 Sec.
T0 present value
T0 contact
0
1
to
5 Sec.
150
151 to 200
Present value is saved when coil switches.
OFF
Contact remains ON when coil switches.
0
ON
Instruction execution
RST ST0 instruction
ON
OFF
X1
(a)
The measurement units settings for retentive timers are the same as those
for low-speed timers and high-speed timers.
• Low-speed retentive timer: Same as low-speed timer
• High-speed retentive timer: Same as high-speed timer
REMARK
In order to use retentive timers, a retentive timer "number of points used" setting
must be designated in the PLC parameters device settings.
10 - 21
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10 DEVICES
MELSEC-Q
Timer Processing & accuracy
(a)
When an OUT T instruction is executed, the following processing occurs:
timer coil ON/OFF, present value update & contact ON/OFF processing.
Timer present value update and contact ON/OFF processing do not occur
at END processing.
[Ladder example]
X0
K10
T0
[Processing at OUT T0 instruction]
Sequence
program
END
OUT T0
END
Processing content
Coil ON/OFF
Present value update
Contact ON/OFF
(b)
When the OUT T instruction is executed, the present value is added to
the scan time measured at the END instruction.
If the timer coil is OFF when the OUT T instruction is executed, the
present value is not updated.
[Ladder example]
X0
H K8
T0
[Present value update timing]
OUT T0
OUT T0
OUT T0
OUT T0
OUT T0
OUT T0
END
END
END
END
END
END
processing processing processing processing processing processing
Program
ON
X0 external input OFF
ON
QCPU's X0
OFF
T0 coil
OFF
T0 contact
OFF
ON
ON
10 ms
measurement
Measured value
at END instruction
T0 present value
1
2
1
3
2
2
3
0+2=2
Input reading timing
(+1 scan)
10 - 22
1
2
1
2
2+3=5
2
3
1
3
5+2=7
2
1
2
3
2
3
7+3=10
Timer accuracy
- (1 scan time + timer time
limit setting) to 1 scan time
10 - 22
10 DEVICES
MELSEC-Q
(c)
The timer response accuracy from the point when input (X) reading occurs,
until the point when the output occurs is + (2-scan time + timer time limit
setting).
Precautions when using timers
The following are a few precautions regarding timer use:
(a)
A given timer cannot be designated (by OUT T ) more than once in a
single scan.
If it is, the timer's present value will be updated at each OUT T
instruction, resulting in a meaningless measurement.
Sequence
program
OUT
END T
OUT
T
OUT
T
END
OUT
T
OUT
T
Present value is updated.
1 Scan
(b)
When a timer (for example. T1) coil is ON, the OUT T1 instruction cannot be
skipped using a CJ instruction, etc.
If the OUT T instruction is skipped, the timer's present value will not be
updated.
(c)
Timers cannot be used in interrupt program.
(d)
If the timer set value is "0", the contact goes ON when the OUT T
instruction is executed.
(e)
If the setting value changes to a value which is higher than the present
value following a timer "time-out", the "time-out" status will remain in effect,
and timer operation will not occur.
(f)
If two timers are used, the ON/OFF ladders should be created as shown
below.
T0
T1
K10
T1
K10
T0
1 second measurement
following T0 ON
1 second measurement
when T1 ON
T0
M0
10 - 23
ON/OFF repeated every
1 second
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10 DEVICES
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10.2.11 Counters (C)
Counters are "up counter" types, with the contact being switched ON when the count
value equals the setting value (count-out condition).
There are two counter types: counters which count the number of input condition startups (leading edges) in sequence program, and counters which count the number of
interrupt factor occurrences.
Counters
(1)
Definition
A counter is a device which counts the number of input condition leading edges
in sequence program.
(2)
Count processing
A counter is a device which counts the number of input condition leading edges
in sequence program.
(a) When and OUT C instruction is executed, the following counter
processing occurs: coil ON/OFF, present value update (count value + 1),
and contact ON/OFF.
Counter present value update and contact ON/OFF processing do not
occur at END processing.
[Ladder example]
X0
K10
C0
[Processing at OUT C0 Instruction (X0: OFF to ON)]
Sequence
program
END
OUT C0
END
Processing content
Coil ON/OFF
Contact ON/OFF
(b)
The present value update (count value + 1) occurs at the leading edge
(OFF to ON) of the OUT C instruction.
The present value is not updated in the following OUT C instruction
statuses: OFF, ON to ON, ON to OFF
[Ladder example]
X0
K10
C0
[Present value update timing]
END
Sequence
program
OUT C0
END
OUT C0
END
OUT C0
ON
X0
OFF
C0 coil
OFF
ON
10 - 24
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10 DEVICES
MELSEC-Q
(c)
Multiple counters can be used within a single scan to achieve the maximum
counting speed.
In such cases, the direct access input (DX ) method should be used for
the counter input signals. 1
OUT
C
OUT
C
END
OUT
C END
OUT
C
OUT
C
Sequence
program
OUT C
execution intervals
(3) Resetting the counter
(a)
Counter present values are not cleared even if the OUT C instruction
switches OFF. Use the RST C instruction to clear the counter's present
value and switch the contact OFF.
(b)
The count value is cleared and the contact is switched OFF at the point
when the RST C instruction is executed.
[Ladder example]
X0
RST
C0
[Counter reset timing]
END
Sequence
program
RST C0
END
RST C0
END
RST C0
ON
X0
OFF
Execution
OFF
RST C0
instruction
Count value cleared & contact OFF
(4)
Count value cleared & contact OFF
Maximum counting speed
The counter can count only when the input condition ON/OFF time is longer than
the execution interval of the corresponding OUT C instruction.
The maximum counting speed is calculated by the following formula:
n
Maximum counting
=
speed (Cmax)
100
1
[times/sec]
T
n: Duty(%) 2
T: Execution interval of the OUT C
instruction
REMARK
1)
2)
1: See Section 10.2.1 for details regarding direct access inputs.
2: The "duty" is the count input signal's ON-OFF time ratio expressed as a
percentage value.
T1
T1+T2
T2
When T1 < T2 n =
T1+T2
When T1
T2 n =
100
100
T1
T2
ON
Count input signal OFF
10 - 25
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10 DEVICES
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Interrupt counters
(1) Definition
Interrupt counters are devices which count the number of interrupt factor
occurrences.
(2) Count processing
(a)
The interrupt counter's present value is updated when an interruption
occurs. It is not necessary to create a program which includes an interrupt
counter function.
(b)
Interrupt counter operation requires more than the simple designation of a
setting value.
To use the interrupt counter for control purposes, comparison instructions
(=, <=, etc.) must also be used to enable comparisons with the setting
value, with an internal relay (M), etc., being switched ON or OFF according
to the comparison result.
The figure below shows a sample program in which M0 is switched ON
after 10 interrupt inputs occur. (In this example, "C300" is the interrupt
counter No. corresponding to I0.)
=
K10
C300
M0
(3) Setting the interrupt counter
(a)
In order to use interrupt counters, at first interrupt counter No. setting must
be designated in the PLC system settings in the PLC parameter setting.
256 points are then allocated for interrupt counters, beginning from the "first
counter No." which is designated.
If C300 is designated as the first interrupt counter No., numbers C300 to
C555 will be allocated for interrupt counters.
C300
I0
C301
I1
C302
I2
C555
I127
Interrupt counter (127 points)
Values corresponding to the interrupt counter No.
(b)
10 - 26
In order to use an interrupt counter, an "interruption permitted" status must
be established by E1 instruction at the main routine program.
10 - 26
10 DEVICES
MELSEC-Q
(4) Precautions
10 - 27
(a)
One interrupt pointer is insufficient to execute interrupt counter and interrupt
program operation.
Moreover, an interrupt program cannot be executed by an interrupt counter
setting designated in the PLC system settings in the PLC parameter setting.
(b)
If the processing items shown below are in progress when an interruption
occurs, the counting operation will be delayed until processing of these
items is completed.
The count processing starts after the execution of program is completed.
Even if the same interruption occurs again while processing of these items
is in process, only one interruption will be counted.
• During execution of sequence program instructions
• During interrupt program execution
• During execution of a fixed scan execution type program
(c)
The maximum counting speed of the interrupt timer is determined by the
longest processing time of the items shown below.
• Instruction with the longest processing time among the instructions used
in the program
• Interrupt program processing time
• The processing time of a fixed scan execution type program
(d)
The use of too many interrupt counters will increase the sequence program
processing time, and may cause a "WDT ERROR".
If this occurs, either reduce the number of interrupt counters, or reduce the
counting speed for the input pulse signal.
(e)
The interrupt counter's count value can be reset by using the RST C
instruction in the sequence program prior to the FEND instruction.
(f)
The interrupt counter's count value can be read out by using the sequence
program MOV instruction.
10 - 27
10 DEVICES
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10.2.12 Data registers (D)
(1) Definition
(a)
Data registers are memory devices which store numeric data (-32768 to
32767, or 0000H to FFFFH).
(b)
Data registers consist of 16 bits per point, with reading and writing executed
in 16-bit units.
b15
b0
Dn
(c)
If the data registers are used for 32-bit instructions, the data will be stored in
registers Dn and Dn + 1. The lower 16 bits of data are stored at the data
register No. (Dn) designated in the sequence program, and the higher 16
bits of data are stored in the designated register No. + 1 (Dn + 1).
For example, when D12 is specified in the DMOV instruction, the lower 16
bits are stored into D12 and the upper 16 bits are stored into D13.
DMOV K500000 D12
Processing object: D12, D13
D13
D12
Upper 16 bits Lower 16 bits
Two data registers can store a range of numeric data from -2147483648 to
2147483647 or from 0H to FFFFFFFFH.
(d)
10 - 28
Data stored by the sequence program is maintained until another data save
operation occurs.
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10 DEVICES
MELSEC-Q
10.2.13 Link registers (W)
(1) Definition
(a)
A link register is the Basic model QCPU memory used to refresh the Basic
model QCPU with data from the link registers (LW) of intelligent function
modules including MELSECNET/H network module.
Link registers are used to store numeric data (-32768 to 32767, or 0000H to
FFFFH).
Basic model QCPU
MELSECNET/H network module
Link register
Link register
W0
LW0
Link refresh
setting range
Link refresh
When used outside the MELSECNET/H network system's range, link
registers can serve as data registers.
(b)
Link registers consist of 16 bits per point, with reading and writing executed
in 16-bit modules.
b15
b0
Wn
(c)
If the link registers are used for 32-bit instructions, the data is stored in
registers Wn and Wn + 1. The lower 16 bits of data are stored in the link
register No. (Wn) designated in the sequence program, and the higher 16
bits of data are stored in the designated register No. + 1 (Wn + 1).
For example, if link register W12 is designated at the DMOV instruction, the
lower 16 bits are stored in W12, and the upper 16 bits are stored in W13.
DMOV K500000 W12
Processing object: W12, W13
W12
W13
In two link register points, -2147483648 to 2147483647 or 0H to
FFFFFFFFH data can be stored.
(d)
Data stored by the sequence program is maintained until another data save
operation occurs.
REMARK
The MELSECNET/H network module has 16384 link register points. The Basic
model QCPU has 2048 link register points. When subsequent points after Point
2048 are used for link registers, change a "number of points" setting of link registers
on the Device sheet of the PLC Parameter dialog box.
10 - 29
10 - 29
10 DEVICES
MELSEC-Q
(2) Using link registers in a network system
In order to use link registers in the network system, network parameter settings
must be made.
Link registers not set in the network parameter settings can be used as data
registers.
REMARK
1) For details regarding network parameters, refer to the Q Corresponding
MELSECNET/H Network System Reference Manual.
10.2.14 Special link registers (SW)
(1) Definition
(a)
Special link registers are used to store data on the communication status
and errors of an intelligent function
(b)
Because the data link information is stored as numeric data, the special link
registers serve as a tool for identifying the locations and causes of faults.
(2) Number of special link register points
There are 1024 special link register points from SW0 to SW3FF. The special link
register points are assigned at the rate of 512 points per intelligent function
module, such as a MELSECNET/H network module.
REMARK
For details regarding special link registers used in the Basic model QCPU, refer to
the QCPU(Q mode)/QnACPU Programming Manual (Common Instructions).
10 - 30
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10 DEVICES
MELSEC-Q
10.3 Internal System Devices
Internal system devices are devices used for system operations.
The allocations and sizes of internal system devices are fixed, and cannot be changed
by the user.
10.3.1 Function devices (FX, FY, FD)
(1) Definition
(a)
Function devices are used in a sub-routine program with arguments to
perform write/read of data between the sub-routine call source with
argument and the sub-routine program with argument.
Example
If FX0 and FD1 are used at the sub-routine program, and if M0 and D0 are designated by the sub-routine
CALL instruction, the M0 ON/OFF data is transferred to FX0, and the D0 data is transferred to FD1.
[Sub-routine program CALL source]
[Sub-routine program]
X0
FX0
CALL P0 M0 D0
P0
MOV FD1 R0
RET
(b) Because the function devices used for each sub-routine program CALL
source can be set, the same sub-routine program can be used without
regard to other sub-routine CALL sources.
(2) Types of function devices
There are 3 function device types: function input devices (FX), function output
devices (FY), and function register devices (FD).
(a) Function input devices (FX)
• These devices are used to designate inputs of ON/OFF data to a subroutine program.
• In the sub-routine program, these devices are used for reading and
processing bit data designated by sub-routine with argument CALL
instruction.
• All the Basic model QCPU bit data designation devices can be used.
(b)
10 - 31
Function output devices (FY)
• These devices are used to designate outputs of sub-routine program
operation results (ON/OFF data) to the sub-routine program CALL source.
• At sub-routine program with arguments, the operation results are stored at
the designated device.
• All bit data designation devices except Basic model QCPU inputs (X, DX)
can be used.
10 - 31
10 DEVICES
MELSEC-Q
(c)
Function registers
• Function registers are used to perform write/read of data between the subroutine call source and the sub-routine program.
• The function register input/output condition is automatically determined by
the Basic model QCPU. If the sub-routine program data is the source data,
the data is designated as sub-routine input data.
If the sub-routine program data is the destination data, the data is
designated as sub-routine output data.
• 1 point occupies 4 words.
The number of words used depends on an instruction in a sub-routine
program.
A one-word instruction requires 1 word.
CALLP P0 D0
MOV R0 FD0
P0
The data is stored in one point (D0).
A two-work instruction requires 2 words.
CALLP P0 D0
DMOV R0 FD0
P0
The data is stored in two points (D0 and D1).
The destination of 32-bit multiplication/division operation requires 4 words.
CALLP P0 D0
P0
D
R0 R10 FD0
The data is stored in four points (D0 to D3).
• Active devices cannot be used in a sub-routine program that contains
arguments. If devices assigned for function registers are used, values of the
function registers will not properly be returned to a calling program.
CALLP P0 D0
P0
D
R0 R10 FD0
MOV K0 D3
Since the points (D0 to D3) are used
for FD0, D3 can not be used for the
sub-routine program.
•Basic model QCPU's word data devices can be used.
REMARK
1) For a procedure for using function devices, see the QCPU (Q Mode)/QnACPU
Programming Manual (Common Instructions).
10 - 32
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10 DEVICES
MELSEC-Q
10.3.2 Special relays (SM)
(1) Definition
(a) A special relay is used to store High Performance model QCPU status data.
(2) Special relay classifications
Special relays are classified according to their applications, as shown below.
(a) For fault diagnosis
: SM0 to SM99
(b) For serial communication function : SM100 to SM129
(c) System information
: SM200 to SM399
(d) System clock/system counter
: SM400 to SM499
(e) Scan information
: SM500 to SM599
(f) Memory card information
: SM600 to SM699
(g) Instruction related
: SM700 to SM799
REMARK
1) For details regarding special relays which can be used by the Basic model QCPU,
refer to Appendix 1.
10 - 33
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10 DEVICES
MELSEC-Q
10.3.3 Special registers (SD)
(1) Definition
(a)
A special register is used to store Basic model QCPU status data (diagnosis
and system information).
(2) Special register classifications
Special registers are classified according to their applications, as shown below.
(a) For fault diagnosis
: SD0 to SD99
(b) For serial communication function : SM100 to SM129
(c)
Fuse-blown module
: SD130 to SD149
(d)
Check of input/output modules
: SD150 to SD199
(e)
System information
: SD200 to SD399
(f)
System clock/system counter
: SD400 to SD499
(g)
Scan information
: SD500 to SD599
(h)
Memory card information
: SD600 to SD699
(i)
Instruction related
: SD700 to SD799
REMARK
1) For details regarding special relays which can be used by the Basic model QCPU,
refer to Appendix 2.
10 - 34
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10 DEVICES
MELSEC-Q
10.4 Link Direct Devices (J \ )
(1) Definition
(a)
At END processing, a data refresh (data transfer) operation occurs between
the Basic model QCPU and the MELSECNET/H network system modules.
Link direct devices are used at that time to directly access the link devices
in the MELSECNET/H network modules.
(b)
Designation method
• Link direct devices are designated by network No. and device No.
Designation method: J
\
Device No.
Input...........................X0
Output........................Y0
Link relay.................. B0
Link register...............W0
Link special relay.......SB0
Link special register ..SW0
Network No.(1 to 239)
• For link register 10 (W10) of network No.2, the designation would be
"J2\W10"
MOVP K100 J2W10
Network modules at network No.2
W0
W10
• For a bit device (X, Y, B, SB), digit designation is necessary.
Designation example : J1\K1X0, J10\K4B0
(2) Designation range
Link direct device designations are possible for all the link devices in network
modules.
Device outside the range specified by the network refresh
parameters can also be designated.
(a)
Writing
1) Writing is executed within that part of the link device range set as the
send range in the common parameters of the network parameters that
is outside the range specified as the "refresh range" in the network
refresh parameters.
Basic model QCPU
Network module
LB 0
B0
Link range
Refresh
range
send range
Writing range
10 - 35
10 - 35
10 DEVICES
MELSEC-Q
2)
Although writing is also possible in the "refresh range" portion of the
link device range (specified by the refresh parameters), the link
module's link device data will be rewritten when a refresh operation
occurs.
Therefore, when writing by link direct device, the same data should
also be written to the Basic model QCPU related devices designated
by the refresh parameters.
[Refresh parameter settings]
Network No. : 1
Basic model QCPU(W0 to W3F)
Network module (LW0 to LW3F)
[Sequence program]
MOV K100 W1
"100" is written to link module LW1 when
a refresh occurs.
MOV W1
"100" is written to link module LW1 when
the MOV instruction is executed.
J1\W1
[Writing timing]
Basic model QCPU
MOV K100 W1
MOV W1
J1\W1
Network module
Writing at
instruction
execution
W0
W1
LW1
Writing at instruction execution
Writing at refresh operation
3)
(b)
10 - 36
When data is written to another station's writing range using a link
direct device, the data which is received from that station will replace
the written data.
Reading
Reading by link direct device is possible in the entire link device range of
network modules.
10 - 36
10 DEVICES
MELSEC-Q
(3) Differences between "link direct devices" and "link refresh"
The differences between "link direct devices" and "link refresh" are shown in
Table 10.4 below.
Table 10.4 Differences Between "Link Direct Devices" and "Link Refresh"
Item
Program
notation
method
Link relay
Link Direct Device
J
Link register
Link special relay
J
J
J
Number of steps
Network module access range
Access data guarantee range
Link Refresh
\K4B0 or later
B0 or later
\W0 or later
W0 or later
\K4SB0 or later
SB0 or later
\SW0 or later
SW0 or later
2 steps
1 step
All network module link
Refresh parameter
devices
designated range
Word units (16 bits)
REMARK
1) For details regarding the MELSECNET/H network system, refer to the For Q
2) For details regarding network parameters, common parameters, and network
refresh parameters, refer to the following manuals:
• Detailed information : Q Corresponding MELSECNET/H Network System
Reference Manual
• Setting procedures : GX Developer Operating Manual, Windows Version
10 - 37
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10.5 Intelligent Function Module Devices (U \G )
(1) Definition
(a)
The intelligent function module devices allow the Basic model QCPU to
directly access the buffer memories of intelligent function modules which
are installed at the base unit.
(b)
Intelligent function module devices are designated by the intelligent function
module input/ output No., and the buffer memory address.
Designation method: U
\G
Buffer memory address (setting range: 0 to16383 (decimal)) 1
Intelligent function module/special function module I/O No.
Setting: If the input/output No. is a 3-digit value, designate the first 2 digits.
For X/YF0.....X/Y1F0
Designate "1F"
Setting range: Q00JCPU: 00H to FH
Q00/Q01CPU: 00H to 3FH
When digital output values of channels (CH.1 to CH.4) of the Q64AD Type
Analog-Digital Conversion Module (X/Y0 to X/YF) installed in Slot 0 of the main
base unit are stored in D0 to D3, the output/input number and the buffer memory
address are specified as shown below.
Q64AD
BMOV U0\G11 D0 K4
11 CH.1 Digital output value
(2) Processing speed
The processing speed for intelligent function module devices is;
(a)
Read/write from/to the buffer memory of the intelligent function module is
slightly faster than the "processing speed of FROM/TO instruction". (For
example, "MOV U0\G11 D0")
(b)
When using a single instruction to perform read from the buffer memory of
the intelligent function module and another processing, use the sum of
"processing speed of FROM/TO instruction" and "processing speed of
instruction" as a guideline.
(For example, "+ U0\G11 D0 D10")
If the same buffer memory of the same intelligent function module is used
two or more times in a sequence program, the processing speed can be
increased by using the FROM instruction to read that buffer memory data to
a Basic model QCPU device.
REMARK
1)
10 - 38
1: For details regarding buffer memory addresses and applications, refer to the
manual for the intelligent function module in question.
10 - 38
10 DEVICES
MELSEC-Q
10.6 Index Registers (Z)
(1) Definition
(a)
Index registers are used in the sequence program for indirect setting (index
qualification) designations.
An index register point is used for index modification.
X0
MOVP K5 Z0
SM400
BCD D0Z0 K4Y30
Index registers consist of 16 bits per point.
(b)
There are 10 index registers (Z0 to Z9).
(c)
Index registers consist of 16 bits per point, with reading and writing
occurring in 16-bit modules.
b15
b0
Zn
(d)
If the index registers are used for 32-bit instructions, the data is stored in
registers Zn and Zn +1.
The lower 16 bits of data are stored in the index register No. (Zn)
designated in the sequence program, and the upper 16 bits of data are
stored in the designated index register No. + 1.
For example, if register Z2 is designated in the DMOV instruction, the lower
16 bits are stored in Z2, and the upper 16 bits are stored at Z3.
DMOV D0
Z2
Processing object: Z2, Z3
Z3
Z2
REMARK
For index modification using the index register, refer to the following manual.
QCPU (Q mode) / QnACPU Programming Manual (Common instructions)
10 - 39
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10 DEVICES
MELSEC-Q
10.6.1 Switching between main routine/sub-routine program and interrupt program
The following processing is performed at the time of switching between main
routine/sub-routine program and interrupt program.
• Index register (Z0 to Z9) value is saved (protected)/restored.
• File register block No. is saved (protected)/restored.
For the index register (Z0 to Z9), whether its value is saved (protected)/restored or not
saved at the time of switching between the main routine/sub-routine program and
interrupt program can be selected in the PLC system setting of the PLC parameter
dialog box.
If you do not want to write date onto index registers when using an interrupt program,
turn on the "High speed execution" check box in the "Interrupt program fixed program
setting" section of the PLC System sheet in the PLC Parameter dialog box. This will
enable you to switch between program quickly.
(1) Index register processing
(a) When "High-speed execution" is not selected
1) When the main routine/sub-routine program is switched to the interrupt
program, the main routine/sub-routine program's index register value
is first saved, and is then transferred to the interrupt program.
2)
The saved index register (Z0 to Z9) value is restored at the time of
switching from the interrupt program to the main routine/sub-routine
program.
Executed program
Index register value
Main routine/
sub-routine
program
Z0=1
Switching
Transferred
Interrupt program
Reset
Z0=1 to Z0=3
Z0=1
Saved
Index register storage area
Z0=0
Main routine/
sub-routine
program
Reset
Z0=1
Z0=1
Z0=1
Z0=1
: For interrupt program, Z0 is changed to 3.
Word devices should be used to transfer index register data from an
interrupt to a main routine/sub-routine program.
10 - 40
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10 DEVICES
MELSEC-Q
(b) When the "High-speed execution" check box is ON:
1) The index register (Z0 to Z9) value is saved/restored at the time of
switching from the main routine/sub-routine program to the interrupt
program.
2)
If data is written onto index registers by using an interrupt program, the
values of index registers used for an main routine/sub-routine program
will be corrupted.
Switching
Main routine/
sub-routine
program
Executed program
Main routine/
sub-routine
program
Index register value
Z0=1
Transferred
Z0=1 to Z0=3
Transferred
Z0=3
Index register storage area
Z0=0
Z0=0
Z0=0
Z0=0
Z0=0
Interrupt program
Reset
: For interrupt program, Z0 is changed to 3.
(c)
Before writing data onto index registers by using an interrupt program, use
the ZPUSH/ZPOP instruction to save/restore the data.
SM400
ZPUSH
I0
D0
SM400
ZPOP
D0
The points after D0 store the
data (Z0 to Z9).
The data after D0 is stored
in points (Z0 to Z9).
IRET
10 - 41
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10 DEVICES
MELSEC-Q
(2) File register block No. processing
(a)
(b)
At the time of switching from the main routine/sub-routine program to the
interrupt program, the block No. of the file register in the main routine/subroutine program is saved and then transferred to the interrupt program.
At the time of switching from the interrupt program to the main routine/subroutine program, the saved block No. of the file register is restored.
Executed program
Switching
Main routine/
sub- routine program
Transferred
Block No. of file register
Save area
10 - 42
Block 1
saved
Block 0
Interrupt program
[RSET K0]
: Block 1
Restored Main routine/
sub- routine program
Block 1
0
Restored
Block 1
Block 1
Block 1
Block 1
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10 DEVICES
MELSEC-Q
10.7 File Registers (R)
(1) Definition
(a)
File registers are expansion devices for data registers.
(b)
File register data is stored in files in the CPU standard RAM.
1) The standard RAM has 32k points assigned for file registers. File
registers can be used at the same processing speed as data registers.
MOV K100 R2
Standard RAM
File register
R0
R1
"100" is written to R2.
(c)
R2
File registers consist of 16 bits per point, with reading and writing occurring
in 16-bit modules.
b15
b0
Rn
(d)
If the file registers are used for 32-bit instructions, the data will be stored in
registers Rn and Rn + 1.
The lower 16 bits of data are stored in the file register No. (Rn) designated
in the sequence program, and the upper 16 bits of data are stored in the
designated file register No.+ 1.
For example, if file register R2 is designated in the DMOV instruction, the
lower 16 bits are stored in R2, and the upper 16 bits are stored in R3.
DMOV
D0
R2
Processing object: R2, R3
R3
R2
Two file registers can be used to store numeric data from -2147483648 to
2147483647 or from 0H to FFFFFFFFH.
(e)
The content of the file register is retained even when the power is turned off
or reset. (It is not initialized even if latch clear is conducted.)
To initialize the file register contents, perform data clear operation in a
sequence program or using GX Developer
Example: To clear R0 - R999
FMOV K0 R0 K1000
• When using GX Developer, select file register all clear in the PLC memory
clear of the Online dialog box to clear the data.
10 - 43
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10 DEVICES
MELSEC-Q
(2) File register specifying method
(a) Block switching method
In the block switching method, specify the number of used file register points
in units of 32k points (R0 to R32767).
When multiple blocks are being used, specify the file registers by switching to
the block No. to be used with the RSET instruction.
Specify each block as R0 to R32767.
RSET K1
MOV
D0
Specifying R0
for block 1
Standard RAM
R0
Block 0
R0
R32767
R0
Block 1
R32767
(b) Serial number access method
In the serial number access method, specify the file registers beyond 32k
points with consecutive device numbers.
The file registers of multiple blocks can be used as consecutive file registers.
Use "ZR" as the device name.
MOV
D0
Standard RAM
ZR32768
ZR0
(Block 0)
ZR32767
ZR32768
(Block 1)
ZR65535
(3) Precautions for use of file registers
Performing write/read to/from 64k or more points of file register numbers will not
result in an error.
However, note that undefined data will be stored when read from file registers is
performed.
POINT
The file registers cannot be deleted by performing PLC data deletion in the Online
dialog box.
They cannot be formatted, either.
10 - 44
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10 DEVICES
MELSEC-Q
10.8 Nesting (N)
(1) Definition
Nesting devices are used to nest MC or MCR master control instructions when
programming operating conditions.
(2) Designation method with master control
The master control instructions are used to open and close the ladders' common
bus so that switching of ladders may be executed efficiently by the sequence
program.
Nesting devices must be numbered in descending order (from N0 to N7) of
nested relation.
For details on how to use master control, refer to the QCPU(Q mode)/QnACPU
Programming Manual (Common Instructions).
Designated in ascending
No. order
A
N0
MC
N0
M15
MC
N1
M16
Executed when condition
"A" is satisfied.
MC
N2
M17
Executed when conditions
"A" and "B" are satisfied.
M15
B
N1
M16
C
N0
nesting
control range
N1
nesting
control range
N2
nesting
control range
N2
M17
Designated in descending
No. order
Executed when condition "
A", "B" and "C" are satisfied.
MC2 to 7 are reset.
MCR
N2
MCR
N1
Executed when conditions
"A" and "B" are satisfied.
MC1 to 7 are reset.
MC
N0
Executed when condition
"A" is satisfied.
MC0 to 7 are reset.
Executed regardless of
A, B, C condition statuses.
10 - 45
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10 DEVICES
MELSEC-Q
10.9 Pointers
(1) Definition
Pointer devices are used in jump instructions (CJ, SCJ, JUMP) or sub-routine call
instructions (CALL, ECALL).
A total of 300 pointers can be used.
(2) Pointer applications
(a)
Pointers are used in jump instructions (CJ, SCJ, JMP) to designate jump
destinations and labels (jump destination beginning).
(b)
Pointers are used in sub-routine CALL instructions (CALL, CALLP) to
designate the CALL destination and label (sub-routine beginning).
MAIN
CALL P0
FEND
P0
RET
END
REMARK
For further information on jump instructions and sub-routine call instructions, see the
QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions).
10 - 46
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10 DEVICES
MELSEC-Q
10.10 Interrupt Pointers (I)
(1) Definition
(a)
Interrupt pointers are used as labels at the beginning of interrupt program.
Interrupt pointer (interrupt program label)
I
Interrupt program
IRET
(b)
A total of 128 interrupt points (I0 to I127) can be used.
(2) Interrupt pointer No. and interrupt factor
(a)
As shown below, there are two types of interrupt factor.
• I0 to I15................................Interrupt input from the QI60 interrupt module.
• I28 to I31..............................Fixed cycle interruption by the internal timer of
• I50 to I127............................Interruption from the intelligent function
module/interrupt module. 1
REMARK
1: To use the interruption from the intelligent function module/interrupt module, the
intelligent function module setting (interrupt pointer setting) must be made in the
PLC system setting of the PLC parameter dialog box.
(Refer to Section 8.2.1 for the interruption from the intelligent function module.)
10 - 47
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10 DEVICES
MELSEC-Q
(b)
A list of interrupt pointer Nos. and interrupt factors is given in Table 10.5
below.
Table 10.5 List of Interrupt Pointer Nos. and Interrupt Factors
I No.
Interrupt Factors
Priority
I0
1st point
5
I1
2nd point
6
I2
3rd point
7
I3
4th point
8
I4
5th point
9
I5
6th point
10
7th point
11
8th point
12
I6
I7
I8
QI60 interrupt
module factor
9th point
13
I9
10th point
14
I10
11th point
15
I11
12th point
16
I12
13th point
17
I13
14th point
18
I14
15th point
19
I15
16th point
20
——
——
I28
100ms
4
I29
40ms
3
I16
to
I27
I30
Unusable
Internal timer factor
I31
20ms
2
10ms
1
I32
to
I49
Unusable
——
——
I50
to
I127
2
Interruption by
intelligent function
module/QI60
Set in the parameter which
intelligent function
module/interrupt module
(QI60) will be used.
21 to 98
REMARK
1 : The internal times shown are the default setting times.
These times can be designated in 1 ms units through a 2 ms to 1000 ms range
by the PLC system settings in the PLC parameter setting.
2 : The intelligent function module setting (interrupt pointer setting) must be made
in the PLC system setting of the PLC parameter dialog box.
(Refer to Section 8.2.1 for the interruption from the intelligent function module.)
10 - 48
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10 DEVICES
MELSEC-Q
10.11 Other Devices
10.11.1 SFC block device (BL)
The SFC block device is used to check whether the specified block of an SFC program
is active or not.
Refer to the following manual for the SFC block device using method.
• QCPU (Q mode)/QnACPU Programming Manual (SFC)
10.11.2 Network No. designation device (J)
(1) Definition
The network No. designation device is used to designate the network No. in data
link instructions.
(2) Designating network No. designation device
The network No. designation device is designated in the data link instruction as
shown below.
JP.READ Jn S1 S2 S3 D
Network No. designation device
(n: network No.)
Instruction name
Network No. designation instruction
REMARK
For details regarding data link instructions, refer to the Q Corresponding
10.11.3 I/O No. designation device (U)
(1) Definition
I/O No. designation devices are used with intelligent function module instruction
module instructions to designate I/O numbers.
(2) Designating the I/O No. designation device
I/O No. designation devices are designated with the intelligent function module
instructions as shown below.
GP.READ Un S1 S2 S3 D
I/O No. designation device
(n: I/O No.)
Instruction name
I/O No. designation instruction
REMARK
For details regarding intelligent function module instructions, refer to the
corresponding manual for the intelligent function module to be used.
10 - 49
10 - 49
10 DEVICES
MELSEC-Q
10.11.4 Macro instruction argument device (VD)
(1) Definition
Macro instruction argument devices are used with ladders registered as macros.
When a VD setting is designated for a ladder registered as a macro,
conversion to the designated device occurs when the macro instruction is
executed.
(2) Designating macro instruction argument devices
Macro instruction argument devices are designated for those devices set as VD
in ladders registered as macro instructions in macro registration at a peripheral
device.
When using macro instructions in a sequence program, designate devices to
correspond to the instruction argument devices used with the ladders registered
as macros, in ascending order.
Ladder registered as a macro (registration name: MAX)
Sequence program
M.MAX D0 D1 R0
VD0 VD1
MOV VD0 VD2
<= VD0 VD1
MOV VD1 VD2
>
Transfer to VD2
Transfer to VD1
Transfer to VD0
Name of ladder registered as a macro
Actual sequence program executed at QCPU
>
D0
D1
MOV D0 R0
<=
D0
D1
MOV D1 R0
REMARK
1)
: With the macro instruction argument device, VD0 to VD9 can be used in one
ladder registered as a macro instruction.
2) The GX Developer read mode provides an option to view a program in macro
instruction format. (Choose "View" - "Macro Instruction format display" to view
macro instructions.)
Change of macro instruction display
10 - 50
10 - 50
10 DEVICES
MELSEC-Q
10.12 Constants
10.12.1 Decimal constants (K)
(1) Definition
Decimal constants are devices which designate decimal data in sequence
program.
They are designated as "K "settings (e.g. K1234), and are stored in the Basic
model QCPU in binary (BIN) code.
See Section 4.8.1 for details regarding binary code.
The designation ranges for decimal constants are as follows.
• For word data (16 bits)............K-32768 to K32767
• For 2-word data (32 bits) ........K-2147483648 to K2147483647
10.12.2 Hexadecimal constants (H)
(1) Definition
Hexadecimal constants are devices which designate hexadecimal or BCD data in
sequence program.
(For BCD data designations, 0 to 9 digit designations are used.)
Hexadecimal constants are designated as "H " settings (e.g. H1234).
See Section 4.8.3 for details regarding hexadecimal code.
The designation ranges for hexadecimal constants are as follows.
• For word data (16 bits)........... H0 to HFFFF (H0 to H9999 for BCD)
• For 2-word data (32 bits) ....... H0 to HFFFFFFFF (H0 to H99999999 for BCD)
10.12.3 Real number (E)
(1) Definition
Real numbers are devices that designate real numbers in a sequence program.
Specify it in the form of E (example: E1.234).
X1
EMOVP E1.234 D0
Refer to Section 4.8.4. for details of the real numbers.
-126
The setting ranges for real numbers are 2
10 - 51
|absolute value|
128
2
.
10 - 51
10 DEVICES
MELSEC-Q
(3) Designation method
In a sequence program, real numbers can be designated in two ways: "normal
representation" and "exponential representation".
• Normal representation ............Designate the value to be set unchanged.
For example, specify 10.2345 as E10.2345.
• Exponential representation .....Designate the value to be set in the form of
n
(value) 10 .
For example, specify 1234 as E1.234+3. 1
REMARK
3
1: +3 in E1.234+3 indicates 10 .
10.12.4 Character string ( " " )
(1) Definition
Character string constants are devices used to designate character strings in
sequence program.
They are designated by quotation marks (e.g. "ABCD1234").
(2) Usable characters
All ASCII code characters can be used in character strings.
The Basic model QCPU is sensitive to uppercase and lowercase characters.
(3) Number of designated characters
Character strings extend from the designated character to the NUL code (00H).
You can use up to 32 characters for a character string in an instruction such as
$MOV.
POINT
Character strings may be used with only the $MOV instruction.
10 - 52
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10 DEVICES
MELSEC-Q
10.13 Useful Method of Using the Devices
Using the device initial value, the Basic model QCPU can set data to the devices and
intelligent function module without any program.
10.13.1 Device initial value
(1) Definition
(a)
The device initial value is a method of registering the data used in a
program to the device or intelligent function module buffer memory without
any program.
Use of the device initial value allows omission of the program that will set
data to devices in the initial processing program.
[Data setting by initial program]
SM402
MOV H100
D0
MOV H2020
D1
Power ON/STOP/
RESET RUN
Device memory
Device initial
value
(b)
At power ON, at reset, at STOP
RUN
Device memory
To use the device initial value, the device initial value data created
beforehand using GX Developer must have been stored into the program
memory of the Basic model QCPU as a device initial value file.
The Basic model QCPU writes the data of the specified device initial value
file to the specified device or intelligent function module buffer memory at
power on or at the time of switching from the STOP status to the RUN
status.
Basic model QCPU
GX Developer
Device initial
value range
setting
Device initial
value data
setting
10 - 53
Program memory
Device initial value write
Device initial
value file
Device initial value write
(At power ON, at reset,
at STOP
RUN)
Specified
device
Intelligent
function
module
10 - 53
10 DEVICES
MELSEC-Q
(c)
The following devices can use the device initial value.
1) Timer's current value (T)
7) Special link register (SW)
2) Retentive timer's current value (ST)
8) File register (R0 to R32767)
3) Counter's current value (C)
9) File register (ZR0 to ZR65535)
4) Data register (D)
10) Intelligent function module
5) Special register (SD)
device (U \G )
6) Link register (W)
11) Link direct device (J \W,
J \SW )
(2) Procedure for using the device initial value
(a)
Set the device initial value ranges on the "Device initial value range setting
screen".
(b)
Set the device initial value data in the device initial value ranges on the
"Device memory editing screen".
[Device initial value range setting screen]
(c)
[Device memory editing screen]
Set "Use" for the device initial value in the PLC file setting of the PLC
[PLC file setting screen]
(d)
10 - 54
Write to the Basic model QCPU the device initial values and parameter set
using GX Developer.
10 - 54
10 DEVICES
MELSEC-Q
(3) Precautions for use of the device initial value
(a)
When the device initial value and latch range overlap, the device initial value
has priority.
Hence, the data in the latch range are also changed into the device initial
value data at power on.
(b)
The device initial value cannot be used for the area that is not desired to be
set at switching from STOP to RUN (data that will be set at power on and
changed in the program).
In the main routine program, create a program that will set data to the
specified device with the MOV instruction, etc.
For the intelligent function module, use the TO instruction to write data to
the buffer memory.
(c)
When specifying the following devices in the device initial value range
setting, make "Module synchronization setting" in the PLC system setting of
the PLC parameter dialog box.
If the module synchronization setting is not made, the device initial values
may not be set to the target module properly.
• Intelligent function module device (U\G)
• Link direct device (J\W, J\SW)
REMARK
Refer to the GX Developer Operating Manual for the device initial value range
setting, the device initial value data setting operation, and the operation for writing
the device initial values to the Basic model QCPU.
10 - 55
10 - 55
MELSEC-Q
11
This chapter describes the concept of the processing times of the Basic model QCPU.
11.1 Scan Time Structure
In the RUN status, the Basic model QCPU performs the following processings
cyclically.
Processing in RUN status
Sequence program check
I/O refresh
(1) I/O refresh time
END processing of DUTY instruction
(No processing when the DUTY
instruction is not executed)
(2) Processing time for
instruction processed at END
Sequence program execution
(3) Instruction execution time
NO
Has the sequence program ended?
YES
MELSECNET/H refresh
CC-Link refresh
(4) Module refresh time
Refresh based on the intelligent
function module parameters set using
GX Configurator
Scan time
Calendar update processing
(No processing when the update
command is not given)
(5) Execution times of various
functions processed at END
Error cancel
(No processing when the cancel
command is not given)
Service processing
(6) Service processing time
Constant wait processing
(No processing when there is no setting)
WDT reset
Scan time calculation
(7) Common processing time
STOP/PAUSE status
STOP/PAUSE processing
Operating status judgment
RUN status
Hardware, system information
check (update)
Numerals in parentheses indicate the item numbers in Section 11.2.
11 - 1
11 - 1
MELSEC-Q
11.2 Concept of Scan Time
The scan time varies with the following elements.
• Number of I/O points
• Processing times of all instructions executed within one scan
• Sum of processing times of user interrupt program executed within one scan
• Processing for instruction processed at END
• Execution of various functions processed at END
• Module refreshes (e.g. refreshes made by MELSECNET/H, CC-Link, etc.)
• Service processing
• Constant scan setting (parameter setting)
The scan time is the sum of the following processing times.
(a) Refresh time of I/O data transferred from/to the following modules installed
on the main base unit, slim type main base unit or extension base unit of the
Basic model QCPU.
• Input module
• Output module
• Intelligent function module
(b) Calculate the I/O refresh time with the following expression.
(I/O refresh time) = (number of input refresh points) N1 + (number of
output refresh points) N2
Refer to the following table for N1 and N2.
N1
CPU Module
Main base unit
/slim type main
base unit
N2
Extension base
unit
Main base unit
/slim type main
Extension base
unit
base unit
Q00JCPU
2.05 s
2.95 s
1.25 s
2.20 s
Q00CPU
2.00 s
2.75 s
1.20 s
2.05 s
Q01CPU
1.95 s
2.70 s
1.15 s
2.00 s
(2) Processing time for instruction processed at END
(a) DUTY instruction
Time when the user timing clock (SM420 to SM424) specified for the DUTY
instruction is turned on/off at END processing
CPU Type
11 - 2
END Processing Time (ms)
Q00JCPU
0.15
0.21
Q00CPU
0.14
0.19
Q01CPU
0.12
0.16
11 - 2
11
MELSEC-Q
(3) Instruction execution time
(a) Sum of the processing times of the instructions used in the program
executed by the Basic model QCPU.
Refer to the following manual for the processing times of the corresponding
instructions.
• QCPU (Q Mode)/QnACPU Programming Manual (Common Instructions)
• QCPU (Q Mode)/QnACPU Programming Manual (SFC)
(b) An interrupt program has an overhead time at the start of interrupt program
and an overhead time at the end of interrupt program.
Add an overhead time at the start of interrupt program and an overhead time
at the end of interrupt program to the instruction execution time.
1) Overhead time at the start of interrupt program (B1)
Cyclic Interrupt (I28 to I31)
CPU Type
Interrupt Processing from QI60
Processing
(I0 to I15)
Without rapid start With rapid start
1
Without rapid start
With rapid start
Q00JCPU
175
150
350
325
Q00CPU
145
125
285
265
Q01CPU
135
120
270
255
1: The values assume that the QI60 is installed on slot 0 of the main base unit.
2) Overhead time at the end of interrupt program (B2)
CPU Type
Without rapid start
With rapid start
Q00JCPU
175
150
Q00CPU
145
125
Q01CPU
135
120
(4) Module refresh time
(a) Refresh of MELSECNET/H
Refresh time between the Basic model QCPU and MELSECNET/H network
module.
Refer to the following manual for the refresh time of the MELSECNET/H.
• Q Corresponding MELSECNET/H Network System Reference Manual
(b) Automatic refresh of CC-Link
Refresh time between the Basic model QCPU and CC-Link master/local
module.
Refer to the following manual for the automatic refresh time of CC-Link.
• Control & Communication Link System Master/Local Module User's
Manual
(c) Intelligent utility package (Intelligent automatic refresh)
1) Refresh time between the intelligent function module and CPU module,
which is designated on “Auto refresh setting” screen of the utility
package for the intelligent function module.
2) Calculate the intelligent automatic refresh time with the following
expression.
(Refresh time) = KN1 + KN2 (number of refresh points)
11 - 3
11 - 3
MELSEC-Q
3) As KN1 and KN2, use the values in the following table.
When the intelligent module is installed on the main base unit
CPU Type
KN1 ( 10-3ms)
KN2 ( 10-3ms)
Q00JCPU
111
55
Q00CPU
91
46
Q01CPU
85
41
When the intelligent module is installed on the expansion base unit
CPU Type
KN1 ( 10-3ms)
KN2 ( 10-3ms)
Q00JCPU
113
56
Q00CPU
92
48
Q01CPU
86
43
(Example)
When the number of automatic refresh points is 4 for the analog-digital
converter module (Q64AD) (when installed on the main base unit of
Q01CPU)
0.249 (ms) = 0.085 + 0.041 4
(5) Execution times of various functions processed at END
(a) Calendar update processing time
1) Time to write the clock data stored in SD210 to SD213 to the clock
element at END processing when a clock data set request is given
(SM210 turns from OFF to ON).
2) Time to read the clock data to SD210 to SD213 at END processing
when a clock data read request is given (SM213 turns ON).
CPU Type
END Processing Time (ms)
At clock data set request
At clock data read request
Q00JCPU
0.12
0.04
Q00CPU
0.11
0.03
Q01CPU
0.10
0.02
(b) Error cancel processing
Time to cancel the continuation error stored in SD50 on the leading edge of
SM50 (error cancel) (when it turns from OFF to ON).
CPU Type
11 - 4
Common Processing Time (ms)
Annunciator
Other error
Q00JCPU
0.17
0.10
Q00CPU
0.14
0.09
Q01CPU
0.13
0.08
11 - 4
MELSEC-Q
(6) Service processing time
(a) Monitoring using GX Developer
Processing time (unit: ms) for monitoring using GX Developer.
Added when monitoring is performed on GX Developer.
When Connected to RS-232 of Host CPU
Module
Q00JCPU
Q00CPU
Q01CPU
Function
Read of program from PLC 1
Device monitor 2
Online program correction 3
1.6
1.2
1.0
1.3
1.0
1.0
When Connected to Other Station
4
Q00JCPU
Q00CPU
Q01CPU
2.3
2.4
1.9
1.9
2.0
1.6
1.8
1.9
1.5
1.2
0.9
1.0
1: Time taken to read an 8k-step program from program memory
2: Time taken when 32 points have been set in registration monitor
3: Time taken when a 100-step ladder has been added
4: Indicates that access is made via MELSECNET/H, Ethernet, CC-Link or
serial communication module.
(b) Communication with serial communication module or Ethernet interface
module
Time to make communication with the serial communication module or
Ethernet interface module.
Refer to the following manual for communication time with the
corresponding module.
• Q-Corresponding MELSEC Communication Protocol Reference Manual
(7) Common processing time
Common processing time of the CPU module processed in the system.
The common processing times are the values in the following table.
Common processing time (ms)
Q00JCPU
CPU Type
Q00CPU
Q01CPU
0.66
0.60
0.52
The processing times in the above table assume that the constant scan function
is not used.
When the constant scan function is used, wait processing is performed for the
period of constant scan setting shortage.
11.3 Other Processing Times
(1) Constant scan accuracy
CPU Type
Without Monitor,
With Monitor, Without Without Monitor,
Without User Interrupt
User Interrupt
With User Interrupt
Q00JCPU
0.20
0.90
Q00CPU
0.12
0.60
Q01CPU
0.10
0.50
With Monitor, With User Interrupt
Sum of the following times
Interrupt program
1) Time indicated in "With Monitor,
execution time
Without User Interrupt" field on the left
(Refer to (b) in
2) Sum of interrupt program execution
Section 11.2 (3).)
times
Unit: ms
With monitor:
Indicates the status in which monitor is being performed with
GX Developer connected or communication with the external
device is being made using the serial communication function.
Without monitor: Indicates the status in which communication using GX
Developer or the serial communication function is not being
made.
11 - 5
11 - 5
MELSEC-Q
12 PROCEDURE FOR WRITING PROGRAM TO BASIC MODEL QCPU
This chapter describes the procedure for writing program created at the GX Developer
to the Basic model QCPU.
12.1 Items to Consider when Creating Program
12
To create a program with the Basic model QCPU, the program capacity, the number of
device points used, etc. must be determined in advance.
(1) Program size considerations
Examine whether programs and parameters can be stored within the program
capacity executable in the used CPU module.
The program capacities of the CPUs are shown below:
• Q00JCPU : 8 k steps
• Q00CPU
: 8 k steps
• Q01CPU
: 14 k steps
(2) Applications of devices and setting of their numbers of points
Consider the applications of the devices used in a program and their number of
points.
Refer to Chapter 10 for the devices usable with the Basic model QCPU.
(3) ROM operation considerations
When performing ROM operation, make the boot file setting of PLC parameter.
(4) Device initial value setting
Set the data necessary as initial values to the device memory of the Basic model
QCPU and the buffer memory of the intelligent function module.
Refer to Section 10.13.1 for details.
12 - 1
12 - 1
MELSEC-Q
12.2 Procedure for writing program to the Basic model QCPU
The procedure for writing program and parameter created at the GX Developer to the
Basic model QCPU standard ROM is shown below.
Procedural steps shown in
boxes are performed at the GX Developer, and those
shown in
boxes are performed in the Basic model QCPU.
12
START
Start GX Developer.
Refer to the GX Developer manual.
Set the project.
NO
Do you change
the number of device
points used?
YES
Refer to Section 10.2.
Device setting screen
Change the number of device
points in device setting of PLC
parameter.
NO
Do you perform
boot operation?
Boot file setting screen
YES
Select "boot from standard
ROM" in boot file setting of
PLC parameter.
Create a program to be
executed in the CPU module.
Ladder setting screen
1)
When the parameters and program are to be written to the program memory of the
Basic model QCPU, the operation marked " " in the above procedure is unnecessary.
12 - 2
12 - 2
MELSEC-Q
1)
NO
Is device initial value used?
Refer to Section 10.13.1.
YES
Set device memory.
Set device initial value ranges.
Connect GX Developer and
CPU module.
Refer to the GX Developer manual.
Move the RUN/STOP/RESET
switch of the CPU module to
the STOP position and switch
power on.
ERR. LED is lit.
Write to PLC screen
Select "Program memory" in write to
PLC of the Online dialog box on GX
Developer, and write parameters,
created program and device initial
values to program memory.
Write program memory to ROM screen
Write the program memory to
ROM in online write to PLC
(flash ROM) of GX Developer to
write the program memory data
to the standard ROM.
Make a reset with the RUN/
STOP/RESET switch of the CPU
module.
Refer to the following manual and make a reset.
QCPU (Q Mode) User's Manual (Hardware)
Basic Model QCPU (Q Mode) User's Manual
(Hardware Setting, Maintenance and Inspection)
END
When the parameters and program are to be written to the program memory of the
Basic model QCPU, the operation marked " " in the above procedure is unnecessary.
12 - 3
12 - 3
MELSEC-Q
13.1 Features
(1) Multi control
The optimum system can be configured to meet the control target by using the
three CPU modules of Basic model QCPU, Motion CPU and PC CPU module in
any of the following combinations as indicated below.
• Basic model QCPU + Motion CPU
• Basic model QCPU + PC CPU
• Basic model QCPU + Motion CPU + PC CPU
13
Basic model QCPU
Sequence control
Motion CPU
Motion control
PC CPU
Data processing
Data communication
(2) Configuration of high-level motion control system
In a Multiple CPU System consisting of the Basic model QCPU and Motion CPU,
sequence control and motion control can be merged to achieve a high-level
motion system.
Management
Sequence control
Motion control
Servo
amplifier
Servo
motor
13 - 1
Servo
amplifier
Servo
motor
13 - 1
MELSEC-Q
(3) Data communication and large-volume data processing
In a Multiple CPU System consisting of the Basic model QCPU and PC CPU
module, sequence control and PC application program can be connected, e.g.
machine control is processed by the Basic model QCPU and data
communication and large-volume data are processed by the PC CPU module, to
achieve a fast and highly flexible system.
Host computer
Data
management
Data
communication
13
Data base
PC CPU
(4) Communication between CPU modules in Multiple CPU System
The following data communication can be made between CPU
modules in a Multiple CPU System.
(a)
(b)
(c)
(d)
Data can be transferred between the CPU modules by merely making
automatic refresh setting.
The Basic model QCPU can read data from the CPU shared memory of the
other CPU when necessary using the intelligent function module device or
FROM instruction.
Instructions dedicated to Motion can be used to issue control commands
from the Basic model QCPU to the Motion CPU. 1
The Basic model QCPU can issue instructions dedicated to communication
between multiple CPUs, to read or write device data from/to the Motion
CPU or PC CPU module.
The Basic model QCPU can issue events to the PC CPU module. 2
REMARK
1: Refer to the manual of the Motion CPU for instructions dedicated to Motion.
2: Refer to the manuals of Motion CPU and PC CPU module for instructions
dedicated to the communication between multiple CPUs.
13 - 2
13 - 2
MELSEC-Q
13.2 Outline of Multiple CPU Systems
(1) What is a Multiple CPU System?
(a)
A multiple CPU System is a system in which multiple (up to three*1) CPU
modules are mounted on the main base unit or slim type main base unit to
control the I/O modules and intelligent function modules by the
corresponding CPU modules.
Motion CPU
PC CPU module
Basic model QCPU
Basic model QCPU
Motion CPU
PC CPU module
The allowable CPU modules are shown in the table below.
(Refer to Section 14.2.1 for the compatible version of each module.)
PLC CPU
Q00CPU,Q01CPU
Motion CPU
Q172CPU, Q173CPU,Q172CPUN,Q173CPUN
PC CPU module
CONTEC Co.,Ltd.*2
Choose the CPU modules suitable to the system size and application to configure
the system.
CPU
0
1
2
3
4
5
6
7
Basic model QCPU
Motion CPU
Input module
Input module
Output module
Intelligent
function module
Input module
Intelligent
function module
Output module
Power supply
It is necessary to set (control PLC setup) which High Performance model
QCPU and motion CPUs are to control which I/O modules and intelligent
function modules with a Multiple CPU System.
1
2
1
1
1
1
2
2
2
Setup of the controlling
CPU module 3
Control performed with
the Basic model QCPU
Control performed with the Motion CPU
(b)
The CPU module that controls the I/O modules and intelligent function
modules is known as the "Control CPU".
The I/O modules and intelligent function modules controlled by the control
CPU are known "controled modules".
Other modules not controlled by the control CPU are known as "noncontrolled modules".
REMARK
1: Refer to Section 14.2 for the combinations of applicable CPU modules.
2: For further information on PC CPU module, consult CONTEC Co.,Ltd.
Tel:+81-6-6472-7130
3: Indicates the grouping configuration on the GX Developer.
"1" under the Basic model QCPU indicates "CPU No. 1", and "1" under the I/O
module or intelligent function module indicates that the control CPU is CPU No. 1.
13 - 3
13 - 3
MELSEC-Q
(2) Multiple CPU System setup
When performing control in a Multiple CPU System, it is necessary to set the
"Number of mounted CPU modules" and "Control CPU" for all the CPU modules
mounted on the main base unit or slim type main base unit. (Refer to Chapter 9.)
(3) Multiple CPU System access range
CPU
0
1
2
3
4
5
6
7
Input module
Input module
Output module
Intelligent
function module
Input module
Intelligent
function module
Output module
It is possible to access non-control modules in the following ways.
• Refresh the input for input modules, hybrid I/O modules and intelligent
function modules. (the PLC parameter Multiple CPU setup is necessary.)
• Read the intelligent function module's buffer memory.
• Read the output data from the output modules, hybrid I/O modules and
However, it is not possible to access non-control modules in the following
ways.
• Output data to the output modules, hybrid I/O modules and intelligent
function modules.
• Writing data into the intelligent function module's buffer memory.
Motion CPU
(b)
Basic model QCPU
It is possible for a Multiple CPU System's control CPU to perform the I/O
refresh procedure on control modules and write in the buffer memory of
intelligent function modules in the same way as a Single CPU System.
Power supply
(a)
1
2
1
1
1
1
2
2
2
Possible to read with the Motion CPU
Possible to read with the Basic model QCPU
(c)
CPU module access range
Access can be made to the other CPUs via the network module of the
controlled modules.
For the access device range, refer to the user's manual of the
corresponding network module.
(4) GX Developer access range
13 - 4
(a)
It is possible to perform parameter/program read/write, monitor and test for
the Basic model QCPU connected to the personal computer.
(b)
GX Developer can make access to the modules of the Basic model QCPU
connected to the personal computer, independently of whether they are
controlled or non-controlled modules.
It can also make access to the Basic model QCPU of another station on the
same network, such as MELSECNET/H or Ethernet.
(c)
It is possible for all Basic model QCPUs on a Multiple CPU System to be
accessed from a GX Developer that is connected to other stations on the
same network.
13 - 4
MELSEC-Q
13.3 Differences with Single CPU Systems
The differences between Single CPU Systems and Multiple CPU Systems are
explained below.
(1) Function versions (see Sections 14.2.1 to 14.2.4)
(a)
The Basic model QCPU of function version B is compatible with a Multiple
CPU System. (The Q00JCPU is not compatible with a Multiple CPU
System.)
In a Multiple CPU System, the Basic model QCPU of function version A
cannot be used.
(b)
All I/O modules can be used on a Multiple CPU System.
(c)
In a Multiple CPU System, use intelligent function modules that are
compatible with a Multiple CPU System.
The intelligent function modules that are incompatible with a Multiple CPU
System can be used when CPU No. 1 is set as the control CPU.
(2) Mounting position of CPU module (see Section 14.2.1)
Mount the Basic model QCPU on the CPU slot (on the right-hand side of the
power supply module).
Mount the Motion CPU on the slot on the right-hand side of the Basic model
QCPU.
Mount the PC CPU module at the right end of the CPU modules in a Multiple
CPU System.
Only one module of each of the Basic model QCPU, Motion CPU and PC CPU
module can be used.
(3) Multiple CPU System parameters (see Section 14.2.4)
In comparison with independent CPU systems, there are more PLC parameter
items on a Multiple CPU System.
Of the PC parameters that have been added to the Multiple CPU System, the
parameters that must be set are listed below.
• Number of CPUs: Sets the number of mounted Basic model QCPUs, Motion
CPUs and PC CPU module that are in use.
• Control CPU settings: Sets which Basic model QCPU, Motion CPU and PC
CPU module controls while modules.
(4) Sameness check (see Section 14.2.5)
The Multiple CPU System parameters, such as the number of CPUs and control
CPU settings, have items that must be the same for the used CPU modules.
The CPU modules check whether the Multiple CPU System parameters are the
same (matching check) when the PLC is powered on or when the Basic model
QCPU is reset or switched from STOP to RUN.
If an error occurs in the matching check, the Multiple CPU System will not start
up.
(5) Concept of the I/O number (see Section 15.1)
The right side of the installed CPU module is I/O number "00H" in the Multiple
CPU System. For this reason, the position of I/O number "00H" varies according
to the number of installed CPUs. However, because each PC CPU module
occupies two slots (one slot for CPU and one empty slot), the I/O number
deviates by the number of points set to the empty slot. (Default: empty 16 points)
13 - 5
13 - 5
MELSEC-Q
(6) Communication with non-controlled module (see Chapter 17)
(a)
It is possible to control I/O modules and intelligent function modules
controlled by the host CPU in the same way as on an Single CPU System.
(b)
It is not possible to output ON.OFF data to modules that are not controlled
by the host CPU or write in the buffer memory of intelligent function
modules.
It is possible to read I/O data from non-control modules with PLC parameter
settings.
It is possible to confirm the status of modules controlled by other CPUs, the
control status of other CPUs, and control the host PLC.
(7) Interactive transmission between each CPU modules on a Multiple
CPU System (see Chapter 16)
It is possible to perform the following interactive transmission between each CPU
modules with a Multiple CPU System.
(a) Automatically refreshing the device data between each CPU modules with
Multiple CPU System parameter settings.
(b) Data send/receive to/from the PC CPU module via the CPU shared memory
using the multiple CPU instructions (FROM, TO, S.TO instructions)
(c) Reading CPU shared memory of Motion CPU from Basic model QCPU with
Multiple CPU instructions (FROM instruction).
(d) Control instruction from the Basic model QCPU to the Motion CPU with
motion dedicated CPU instructions.
(e) Writing and reading of the device data from the Basic model QCPU to the
Motion CPU/PC CPU module with communication dedicated instructions
between multiple CPUs.
(f) Event issuance from Basic model QCPU to PC CPU module using
instructions dedicated to multiple CPU communication
(8) Processing during resets and errors (see Sections 14.2.6 and
14.2.7)
The reset and error-time processings differ between CPU No. 1, No. 2 and No.3
of the Multiple CPU System.
(a)
In the Multiple CPU System, the whole system can be reset by resetting
CPU No. 1.
Only the CPU module No. 2 or No. 3 cannot be reset.
(b)
When a stop error occurs in the Basic model QCPU as CPU No. 1, the
Multiple CPU System stops.
When CPU module No. 2 or No. 3 results in a stop error, whether the
Multiple CPU System will be stopped or kept operated can be selected.
(9) Clock function
An intelligent function module with which the error code and time of occurrence is
stored in the buffer memory when an error is triggered is available.
The CPU No.1 time data will be stored as the time that the error occurred
regardless of whether the module concerned is a control CPU or a non-control
CPU.
13 - 6
13 - 6
MELSEC-Q
This chapter explains the system configuration of Multiple CPU Systems, and the
precautions for Multiple CPU System configuration.
14.1 System Configuration
This section explains the equipment configuration of Multiple CPU Systems, the
connections with peripheral device, and an output of the system's configuration.
(1) Equipment configuration of Multiple CPU System
(a)
When main base unit (Q3 B) is used
MITSUBISHI
LITHIUM BATTERY
Basic model QCPU
(Q00CPU,Q01CPU)
14
Battery
(Q6BAT)
Motion CPU
PC CPU module
(Q52B,Q55B)
1
Main base unit
(Q33B,Q35B,Q38B,Q312B)
Power supply module 2,
I/O module,Intelligent function
module of the Q Series
Motion only module
Extension cable
(QC05B, QC06B,QC12B,
QC30B,QC50B,QC100B)
(Q63B,Q65B,Q68B,Q612B)
Power supply module
2,
I/O module,Intelligent function
module
Motion only module
I/O module,
lntelligent function module
Motion only module
POINT
(1)
(2)
14 - 1
1: For further information on PC CPU module, consult CONTEC Co., Ltd
Tel: +81-6-6472-7130
2: As a power supply module, use the Q61P-A1, Q61P-A2, Q62P or Q64P.
Make the power consumption within the rated output current value of the
power supply module.
The slim type power supply module (Q61SP) cannot be used.
14 - 1
(b)
MELSEC-Q
When slim type main base unit (Q3 SB) is used
MITSUBISHI
LITHIUM BATTERY
Basic model QCPU
(Q00CPU,Q01CPU)
Battery
(Q6BAT)
(Q32SB,Q33SB,Q35SB)
Slim type power supply, I/O,
14
POINT
(1)
1: As a power supply module, use the slim type power supply module
(Q61SP).
The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used.
(2) The slim type main base unit does not have an extension cable connector. The
extension base or GOT cannot be connected.
14 - 2
14 - 2
MELSEC-Q
(2) Configuration of peripheral device for Basic model QCPU
Basic model QCPU
(Q00CPU,Q01CPU)
RS-232 cable
(QC30R2)
Personal computer
GX Developer Version 8 or later
POINT
(1) Refer to the Motion Controller User’s Manual for connection between the Motion
CPU and peripheral modules.
(2) The GX Developer installed in a Personal computer connected to the Motion
CPU is not used to communicate with the Basic model QCPU.
(3) Refer to the manual of the PC CPU module for the connection between the PC
CPU module and peripheral modules.
(4) Both the motion CPU and PC CPU module have restrictions depending on the
version.
When making connection with a peripheral device, always refer to the manual
of the Motion CPU or PC CPU module.
14 - 3
14 - 3
MELSEC-Q
(3) Outline of system configuration (when Basic model QCPU, Motion
CPU and PC CPU module are mounted)
When main base unit (Q3 B) is used
IN
OUT
Power supply module
16F 18F 1AF1CF 1EF
20F 22F 24F 26F 28F
23 24 25 26 27
C P U3
Empty, 16 points
C P U2
B0 D0 F0 110 130
CF EF 10F 12F 14F
150 170 190 1B0 1D0
16F 18F 1AF 1CF 1EF
1F0 210 230 250 270
20F 22F 24F 26F 28F
GOT
Must not be used.
Must not be used.
2F 4F 6F 8F AF
18 19 20 21 22
3 extension
stages
1F0 210 230 250 270
2AF
C P U1
OUT
C P U3
Empty, 16 points
C P U2
C P U1
150 170 190 1B0 1D0
290
10 30 50 70 90
13 14 15 16 17
IN
OUT
Power supply module
IN
OUT
Power supply module
1 extension
stages
2 extension
stages
18 19 20 21 22
Slot No.
PC CPU occupies 2 slots.
8 9 10 11 12
CF EF 10F 12F 14F
Must not be used.
4 extension
stages
Extension cable
2F 4F 6F 8F AF
B0 D0 F0 110 130
Must not be used.
3 extension
stages
IN
OUT
Power supply module
System
configuration
10 30 50 70 90
13 14 15 16 17
IN
OUT
Power supply module
2 extension
stages
0 1 2 3 4 5 6 7
Slot No.
8 9 10 11 12
IN
OUT
Power supply module
1 extension
stages
OUT
Extension cable
Power supply module
0 1 2 3 4 5 6 7
(b) System where extension base units and GOT are connected
Power supply module
(a) System where extension base units are connected
IN
OUT
Power supply module
(a)
Slot No.: 0
When each slot is mounted with 32-point module
CPU number
Maximum number
of extension units
CPU1: CPU No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU3: CPU No. 3 (PC CPU module)
4 extension units
Number of CPUs setting in
Maximum number Multiple CPU setting
of mounted I/O
modules
Number of mounted modules
Maximum number
of I/O points
Main base unit
model name
Extension base
unit model name
Extension cable
model name
Notes
14 - 4
1
2
3
24 modules
23 modules
21 modules
1024 (maximum number of I/O points of CPU module. 1024 points per module when CC-Link/LT is used.)
Q33B, Q35B, Q38B, Q312B
Q52B, Q55B, Q63B, Q65B, Q68B, Q612B
(1) Use the extension cables within the overall distance of 13.2m.
(2) When using the extension cable, do not bundle it with, or run it close to, the main circuit (high voltage, large current) line.
(3) Set the extension unit numbers in ascending order so that the same number is not used for different extension base units.
(4) The QA1S6_B/QA65B cannot be connected as the extension base unit.
(5) Connect the extension cable from OUT of the extension cable connector of the base unit to IN of the next extension base unit.
(6) An error occurs if modules are mounted on 26 or more slots. (Number of mounted modules including PLC No. 1)
(7) When mounting a Motion CPU, refer to the Basic Model QCPU User's Manual (Function Explanation, Program Fundamentals).
(8) Refer to Section 15.1.1 for the I/O numbers in a Multiple CPU System configuration other than the above.
(9) The PC CPU occupies two slots.
14 - 4
(b)
MELSEC-Q
When slim type main base unit (Q3 SB) is used
C P U3
Empty, 16 points
C P U2
System
configuration
C P U1
Power supply module
Slim type main base unit (Q35SB)
0 1 2 3 4
Slot No.
10 30
2F 4F
Shows a system where each slot is mounted with 32-point module.
CPU number
Maximum number
of extension units
CPU1: cpu No. 1 (Basic model QCPU), CPU2: CPU No. 2 (Motion CPU), CPU3: No. 3 (PC CPU module)
Extension not allowed
Number of CPUs setting in
Maximum number Multiple CPU setting
of mounted I/O
modules
Number of mounted modules
Maximum number
of I/O points
Slim type main
base unit model
name
Extension base
unit model name
Extension cable
model name
Notes
14 - 5
1
2
3
5 modules
4 modules
2 modules
1024 (maximum number of I/O points of CPU module. 1024 points per module when CC-Link/LT is used.)
Q32SB, Q33SB, Q35SB
(1) The Q61P-A1, Q61P-A2, Q62P or Q64P cannot be used as a power supply module.
Use the Q61SP as a power supply module.
The extension base or GOT cannot be connected.
14 - 5
MELSEC-Q
14.2 Precautions For Multiple CPU System Configuration
14.2.1 Function versions of Basic model QCPU, Motion CPU and PC CPU module that can
be used, and their mounting positions
(1) Versions applicable to Multiple CPU System
(a) Basic model QCPU
Use the function version B.
Refer to Section 2.3 for how to confirm the function version.
(b) Motion CPU
Confirm the applicable version of the Motion CPU in the programming
manual of the Motion CPU.
(c) PC CPU module
Use Version 1.07 or later of the PC CPU module bus interface driver
software package (PPC-DRV-01).
For details, confirm the version in the manual of the PC CPU module.
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MELSEC-Q
(2) Basic model QCPU, Motion CPU and PC CPU module mounting
positions
(a)
One Basic model QCPU can be mounted on the CPU slot (slot on the righthand side of the power supply module) of the main base unit.
• Mount only one PC CPU module at the right end of CPU modules.
(No CPU module can be mounted on the right side of the PC CPU
module.)
Table 14.2 Installation positions of CPU modules
1
Mounting positions of CPU modules
2
Basic model QCPU
1
—
Empty
0
1
2
1
2
PC CPU module
2
Power supply
PC CPU module
2
CPU
Empty
2
0
Basic model QCPU
1
Basic model QCPU
0
CPU
Power supply
2
Basic model QCPU
1
Empty
1
0
Motion CPU
0
Power supply
CPU
CPU
Basic model QCPU
2
CPU
Power supply
1
Empty
0
2
Motion CPU
CPU
1
Empty
Motion CPU
0
Basic model QCPU
CPU
Basic model QCPU
Power supply
3
0
Basic model QCPU
Power supply
2
Power supply
1
Power supply
CPU
PC CPU module
2
Number of CPUs
2
—
—
1: The number of CPUs indicated is the value set in the Multiple CPU setting of the PLC
2: The PC CPU module occupies two slots.
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The Motion CPU cannot be mounted on other than Slot 0.
Also, any CPU module cannot be mounted on the right side of the PC CPU
module.
(c)
0
1
2
Motion CPU
Basic model QCPU
Power supply
CPU
PC CPU module
(b)
MELSEC-Q
An empty slot is secured for future addition of a CPU module.
Set the number of CPU modules including the empty slot in the number of
CPUs setting, and set the type of the slot to be emptied as "CPU (Empty)".
POINT
When adding a Motion CPU in the future to the system that uses the Basic model
QCPU and PC CPU module, mount the PC CPU module on Slot 1 and set Slot 0
as "CPU (Empty)".
(3) Basic model QCPU, Motion CPU and PC CPU module PLC
numbers
The CPU numbers are allocated to differentiate between the Basic model QCPU,
Motion CPU and PC CPU module mounted in the Multiple CPU System. The
Basic model QCPU on the CPU slot is set as CPU No. 1, and the CPUs are
allocated in order of No. 1, No. 2 and No. 3 from left to right.
PC CPU module
Motion CPU
Basic model QCPU
Power supply
CPU slot: CPU No. 1 .... Basic model QCPU (fixed)
Slot 0 : CPU No. 2 .... Motion CPU
Slot 1 : CPU No. 3 .... PC CPU module
These CPU numbers are used to set the control CPUs in I/O assignment,
for example.
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MELSEC-Q
14.2.2 Precautions when using Q Series I/O modules and intelligent function modules
(1) Compatible I/O modules
All I/O modules (QX , QY ) are compatible with to Multiple CPU System. They
can be used by setting any of CPU No.1 to No.3 as a control CPU.
(2) Compatible intelligent function modules
(a)
The intelligent function modules compatible with the Multiple CPU System
are those of function version B or later. They can be used by setting any of
CPU No.1 to No.3 as a control CPU.
(b)
Q Series high speed count modules (QD62, QD62D, QD62E) are
compatible with by Multiple CPU System are those of function version A or
later. They can be used by setting any of CPU No.1 to No.3 as a control
CPU.
(c)
Q Series interruption modules (QI60) do not have a function version, but are
supported by Multiple CPU Systems. CPUs No.1 to No.4 can be set up as
control CPUs.
(d)
The intelligent function module of function version A can be used in a
Multiple CPU System when CPU No. 1 is set as the control CPU.
However, only the control CPU can be accessed from the serial
communication module, etc. externally. (The MELSECNET/H, serial
communication module, etc. cannot make external access to non-control
CPUs.)
If CPU No. 2 or No. 3 is set as a control CPU, "SP. UNIT VER. ERR (error
code: 2150)" will occur and the Multiple CPU System will not start up.
(3) Ranges of access to control and non-control modules
In a Multiple CPU System, non-control modules can be accessed by setting "I/O
setting outside of the group" at the "Multiple CPU settings" dialog box in "PLC
Parameter". The following table indicates accessibility to the control and noncontrol modules in the Multiple CPU System.
Accessibility
Access target
Control module
Non-control module (I/O setting outside of the group)
Disabled
Enabled
Input (X)
Output (Y)
Buffer
memory
Read
Write
Read
Write
: Accessible
: Inaccessible
REMARK
• The function version of intelligent function modules can be confirmed at the rated
name plate of the intelligent function module and with the GX Developer's "System
monitor product information list window" (see Section 2.3.)
• See Section 14.2.3 for details on restrictions on the number that can be used with
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MELSEC-Q
14.2.3 Modules that have mounting restrictions
The following table indicates restrictions on the number of modules that can be
mounted in Multiple CPU Systems. Ensure that the number of modules mounted is
within these ranges.
Product
Model
• QJ71LP21
• QJ71BR11
Q series MELSECNET/H
• QJ71LP21-25
network modules
• QJ71LP21G
• QJ71LP21GE
Q series Ethernet
interface modules
• QJ71E71
• QJ71E71-B2
• QJ71E71-100
Q series CC-Link system
• QJ61BT11
master/local modules
Interruption modules
• QI60
Number of modules that can be Number of modules that can be
mounted per system
mounted on Basic model QCPU
A total of up to four modules on
the inter-PLC network.
(However, the module that can Up to one module on the interPLC network
be controlled by the Basic model
QCPU is only one module on the
inter-PLC network)
Up to one module
Up to one module
Up to six modules
Up to two modules
Up to three modules
Only one module
: Indicates the number of interrupt modules to which the interrupt pointer setting has
not been made.
When the interrupt pointer setting has been made, the number of modules that can
be used is as follows.
Q00CPU, Q01CPU: 24 modules
14.2.4 Compatible GX Developers and GX Configurators
(1) Compatible GX Developers
GX Developer Version 8 (SW8D5C-GPPW-E) or later are compatible with on
Multiple CPU Systems.
GX Developer Version 7 (SW7D5C-GPPW-E) or earlier are not compatible with
Multiple CPU System.
(2) Compatible GX Configurators
The GX Configurator version that can be used in a Single CPU System can be
used in a Multiple CPU System without modifications.
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MELSEC-Q
14.2.5 Parameters that enable the use of Multiple CPU System
(1) Parameters that enable the use of Multiple CPU System
Compared with the Single CPU System, the Multiple CPU System includes the
"No. of CPU", "control CPU", "refresh setting (automatic refresh setting)" of PLC
parameters.
The PLC parameters must be set to the same for all the CPU modules used in
the Multiple CPU System, except some modules.
Make similar settings to the PC CPU module, if one is included, using the PC
CPU module setting utility.
For the setting method, refer to the manual of the PC CPU module.
(2) The PLC parameter settings for use with Multiple CPU System
The PLC parameters, necessity of setup, and descriptions that are required for
using Multiple CPU System are listed in table 14.3.
Table 14.3 Setting list for the Multiple CPU and I/O Assignment
PC parameter
I/O Assignment
Type
—
Model name
—
Points
—
Start
—
Standard setting
Base model name
I/O Assignment
Necessity of
Description
setup 1
2
—
—
—
Power model name
—
—
Extension cable
—
—
Points
—
Switch settings
—
—
Detailed settings
Error time output made
—
—
H/W error time CPU operation made
—
—
I/O response time
—
—
Control CPU
PLC system
settings
Number of empty slots
—
No. of CPU
Operation mode
Online module change
Multiple CPU
settings
The input condition outside of the group is taken
The output condition outside of the group is taken
Refresh setting
Send range for each CPU
PLC side devices
—
1: Necessity of setup column
: Items that must be set up for Multiple CPU System (operations not possible if not set up.)
: Items that may be set up when required for Multiple CPU System (Operations carried out
with the default values when not set up.)
—: Items that are the same as Single CPU Systems.
2: Descriptions
: Items that have the same settings for all CPU modules on the Multiple CPU System.
: Items that have the same settings for all Basic model QCPUs and PC CPU module on the
Multiple CPU System (items that do not have settings for Motion CPUs).
—: Items that can be setup up individually for each CPU modules on the Multiple CPU system.
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MELSEC-Q
After changing the parameter setting such as the Multiple CPU setting, match the
settings of all CPUs in the Multiple CPU System, and then reset CPU No. 1 or
power the PLC OFF, the ON.
It is possible to transfer across and use the CPU settings and I/O Assignments
set up for other projects with GX Developer.
(See section 19.2.3 for details on transferring and using Multiple CPU settings
and I/O Assignments.)
(a)
Number of CPUs setting (setup necessary)
1) The number of CPU modules to be used on a Multiple CPU System
are set at the PLC parameter's "Multiple CPU settings" screen in the
(PLC) Parameter dialog (indicated with the "A" arrow.)
A
2)
Ensure that the No. of CPU set for the Multiple CPU System is the
same as the number of CPUs actually mounted.
To secure the "empty slot" where a CPU module will be mounted in
the future, set "CPU (Empty)" in the I/O assignment setting of the
Parameter dialog box.
For example, when setting the number of CPUs to three in the Multiple
CPU setting and securing a slot for the Motion CPU, set CPU No. 2 to
"CPU (Empty)". (Arrow B)
B
3)
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In the following cases, "CPU LAY ERROR (error code: 7031)" occurs
in the mounted CPU modules.
• When the number of mounted CPU modules exceeds the number
set as the number of CPUs.
• When no CPU module is mounted on any of the slots set for CPU
No. 1 to No. 3.
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MELSEC-Q
(b)
Operation mode setting (optional)
This is set to continue operation of other CPUs where a stopping error has
not occurred when an error occurs at any of CPUs No.2 and No.3.
The operation mode for the CPU No.1 cannot be changed (all CPUs will
suspend operations when a stop error is triggered for the CPU No.1.)
See Section 14.2.7 for further details.
(c)
I/O settings outside of the group (optional)
This is set when the input and output (X, Y) for I/O modules and intelligent
function modules being controlled by other CPUs is to be downloaded to
the host CPU.
See Section 17.2 for further details.
(d)
Refresh setting (optional)
This is set up to automatically refresh the device data on the Multiple CPU
System.
See Section 16.1 for further details.
(e)
Control CPU settings (optional)
Sets up the control CPUs for the I/O modules and intelligent function
modules mounted on the base units on the Multiple CPU System (indicated
by the "C" arrow.)
All default settings are set for the CPU No.1.
C
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MELSEC-Q
(3) Multiple CPU setting and I/O Assignment checks
Checks, as shown in table 14.4, will be run to ascertain that all CPU modules
have the same settings (sameness check) when the description column in table
14.3 has been set with the "O" symbol and the power to the sequence is
switched on, the Basic model QCPU is reset, or the status is changed from
STOP to RUN.
(a)
The Multiple CPU System will be started up if all CPUs have the same
settings.
(b)
The operations described in table 14.4 will be performed when all CPUs do
not have the same settings.
In this event, check the Multiple CPU settings and I/O Assignment, and set
all CPUs with the same settings.
To start the Multiple CPU System, reset the Basic model QCPU for CPU
No.1 or turn off and on the CPU (power ON OFF ON).
(For the action after the Basic model is reset, see Section 14.2.6.)
Table 14.4. List of sameness check contents
Item
PLC No.1
When the power to the CPU is switched on
When CPU No.1 is reset
No sameness check will be run
• When the RUN/STOP
switch has been changed
from STOP to RUN.
• When parameters are
written with the GX
Developer
PLC No.2, 3
• A comparison check will be run on the
Multiple CPU settings and I/O
Assignments for CPU No.1.
• A "PARAMETER ERROR (error code:
3012)" will occur in the host CPU if they
do not match.
• A comparison check will be run on the Multiple CPU settings and I/O Assignments for
the CPU in the RUN mode with the lowest number.
When CPUs in the
• A "PARAMETER ERROR (error code: 3012)" will occur in the host CPU if they do not
RUN mode exist
match.
When CPUs in the
RUN mode do not
exist
do not match.
do not match.
When a stop error
occurs at CPU No.1
STOP
RUN is not allowed as a
"MULTIPLE CPU DOWN (error code:
7000)" error will occur in the host CPU.
—
POINT
After Multiple CPU System parameters unavailable with the Motion CPU are
changed for the Basic model QCPU or PC CPU module in a Multiple CPU System
including a Motion CPU, be sure to reset the Basic model QCPU for CPU No.1 or
turn off and on the CPU. (Otherwise the Basic model QCPU or PC CPU module
checks consistency with Multiple CPU System parameters of the Motion CPU,
causing a "PARAMETER ERROR (error code: 3012)."
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MELSEC-Q
14.2.6 Resetting the Multiple CPU System
In the Multiple CPU System, the whole system can be reset by resetting the Basic
model QCPU.
Resetting the Basic model QCPU resets all the CPU modules No. 2, No. 3, I/O
modules and intelligent function modules.
To restore the Multiple CPU System when any of the CPUs in the system is in a stop
error, reset the Basic model QCPU or power on the CPU again (power ON OFF
ON).
(Recovery is not allowed by resetting the CPU modules for CPU No.2 and No.3 for
which stop errors have occurred.)
PLC No.3 PC CPU module
Motion CPU
PLC No.2
Power supply
PLC No.1 Basic model QCPU
0 1 2 3 4 5 6 7
Reset is not allowed with the Multiple CPU System.
If a reset is attempted all CPUs on the Multiple
CPU System will assume the "MULTIPLE CPU DOWN" status.
The entire multiple PLC system can be reset.
POINT
(1) It is not possible to reset the CPU modules for CPU No.2 and No.3 individually
in the Multiple CPU System. If an attempt to reset any of the CPU modules for
CPU No.2 and No.3 during operation of the Multiple CPU System, a
"MULTIPLE CPU DOWN (error code: 7000)" error will occur for the other
CPUs, and the entire Multiple CPU System will be halted. However, depending
on the timing in which the CPU modules have been reset, there are cases
where errors other than the "MULTIPLE CPU DOWN" error will halt the other
CPUs.
(2) A "MULTIPLE CPU DOWN (error code: 7000)" error will occur regardless of
the operation mode set at the "Multiple CPU settings" screen within the (PLC)
Parameter dialog box. (stop/continue all other CPUs on the CPU modules for
CPU No.2 and No.3 error) when the CPU modules for CPU No.2 and No.3 are
reset (See Section 14.2.7 for details on the Multiple CPU setting operation
modes.)
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MELSEC-Q
14.2.7 Processing when stop errors occur
In the Multiple CPU System, the operation of the whole system differs between when
the Basic model QCPU results in a stop error and when the CPU module No. 2 or No.
3 results in a stop error.
(1) When the Basic model QCPU results in a stop error
(a)
When the Basic model QCPU results in a stop error, the CPU modules No.
2, No. 3 all result in "MULTI CPU DOWN (error code: 7000)" and the
Multiple CPU System stops. (Refer to POINT on the next page for details.)
(b)
Restore the system in the following procedure.
1) Confirm the error cause of the Basic model QCPU with the PLC
diagnosis function.
2) Remove the error cause.
3) Reset the Basic model QCPU or power on the PLC again.
By resetting the Basic model QCPU or powering on the PLC again, all
the CPUs in the Multiple CPU System are reset and the system is
restored.
(2) When the CPU module No. 2 or No. 3 results in a stop error
When the CPU module No. 2 or No. 3 results in a stop error, set in the
"Operation Mode" in the Multiple CPU setting whether the whole system will be
stopped or not.
The default setting is to stop all CPUs at occurrence of a stop error in all CPUs.
When it is not desired to stop all CPUs at occurrence of a stop error in any of the
CPU modules, click the checked check boxes of CPU No. 2 and No. 3. (Arrow D)
D
14 - 16
(a)
A "MULTIPLE CPU DOWN (error code: 7000)" error occurs for the CPU
modules and the Multiple CPU System will be halted when a stop error is
occurs in CPU modules for which the "All station stop by stop error of CPU
'n' " has been set. (See POINT on the next page for details.)
(b)
A "MULTIPLE CPU ERROR (error code: 7010)" error occurs for all other
CPUs but operations will continue when a stop error occurs in CPU
modules for which the " All station stop by stop error of CPU 'n' " has not
been set.
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MELSEC-Q
POINT
A "MULTIPLE CPU DOWN" stop error will be occur for the CPU on which the error
was detected when a stop error occurs.
There are cases where the timing of error detection will search for the CPU on
which the stop error that has caused the "MULTIPLE CPU DOWN" error occurs,
not the first CPU on which a stop error occurs, and the entire system will assume
the "MULTIPLE CPU DOWN" status.
For example, if a stop error occurs in the CPU No.2 and the CPU No.3 is halted as
a direct consequence of this, there are cases where the CPU No.1 will be halted
because of the stop error on CPU No.3 depending on the timing of error detection.
PC CPU module No.3
Motion CPU No.2
Basic model QCPU No.1
Power supply
Halted with an "WDT ERROR"
Halted with stop error detection on PLC No.2
(becomes "MULTIPLE PLC DOWN")
There are cases where the system will be halted
with stop error detected on the PLC No.3
depending on the timing of error detection.
(becomes "MULTIPLE PLC DOWN")
Owing to this, there are cases where a different CPU No. to the CPU that initially
caused the stop error will be stored in the error data's common information
category.
In this event, remove the reason for the error on the CPU that caused the stop error
in addition to the "MULTIPLE CPU DOWN" error when restoring the system.
(c)
14 - 17
Observe the following procedures to restore the system.
1) Confirm the cause of the CPU No.1 error with the PLC diagnostics
function.
2) Remove the cause of the error.
3) Reset the Basic model QCPU or power on the PLC again.
By resetting the Basic model QCPU or powering on the PLC again, all the
CPUs in the Multiple CPU System are reset and the system is restored.
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MELSEC-Q
14.2.8 Reducing the time required for Multiple CPU System processing
(1) Multiple CPU System processing
A bus (base unit pattern, extension cable) is used by the CPU module when
accessing the I/O module and intelligent function module, and this bus cannot be
used by plural CPU module at the same time.
The CPU modules that attempted buss access afterwards when plural CPU
module use the bus simultaneously will assume the "Standby" status until
processing for the CPU module that executed the procedure first has been
completed.
This "Standby" status (the amount of time the CPU module must wait) will cause
delays in input and output on the Multiple CPU System, and result in extended
scan times.
See Chapter 18 for details on extended scan times.
(2) Maximum standby time
The host CPU will reach the maximum standby time in the following cases with a
• When three CPU modules are used on the Multiple CPU System.
• When additional base units are in use.
• When intelligent function modules that possess vast quantities of data are
mounted onto additional base units.
• When three CPU modules simultaneously access modules mounted onto
additional base units.
(3) Reducing the time required for Multiple CPU System processing
The following methods are available for reducing the amount of time required for
Multiple CPU System processing.
• Combine modules with many access points, such as MELSECNET/H and CCLINK refresh, etc., together into a main base unit.
• Set modules with many access points, such as MELSECNET/H and CC-LINK
refresh, etc., as control module on a single CPU module, and ensure that
simultaneous access does not occur.
• Reduce the number of MELSECNET/H and CC-LINK refresh access points.
• Reduce the number of automatic refresh points between CPU modules.
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MELSEC-Q
15.1 Concept behind Allocating I/O Numbers
Multiple CPU Systems possess I/O numbers to enable interactive transmission
between the CPU modules and the I/O modules and intelligent function modules, and
I/O numbers to enable interactive transmission between the CPU modules.
15.1.1 I/O modules and Intelligent function module I/O numbers
The difference with Single CPU Systems is the 00H position (slot) of the I/O number
with Multiple CPU Systems.
However, the concept behind the sequence for allocating I/O numbers, the I/O
numbers for each slot, and the I/O numbers for empty slots is the same for both types
of system.
See Chapter 5 (Allocating I/O Numbers) for details on the concept behind the
sequence for allocating I/O numbers, the I/O numbers for each slot, and the I/O
numbers for empty slots.
(1) "00H" position for I/O numbers
(a)
(b)
(c)
15
The number of slots set with the PLC parameters' Multiple CPU settings are
occupied by the CPU modules on the Multiple CPU System.
The I/O modules and intelligent function modules are mounted from the
right of the slots occupied by the CPU modules.
I/O number of a system without PC CPU module
The I/O number for the I/O modules and intelligent function modules
mounted from the right of the slots occupied by the CPU modules is set as
"00H" and consecutive numbers are then allocated sequentially to the right.
1)
Example: Two modules are mounted
Motion CPU
Power supply
Basic model QCPU
0 1 2 3 4 5 6 7
I/O number : 00H
2)
Example: Three modules are mounted and one empty slot exists
Empty
Motion CPU
Power supply
Basic model QCPU
0 1 2 3 4 5 6 7
I/O number : 00H
(d)
Input/output number of a system with PC CPU module
The PC CPU module occupies two slots. The one on the right side among
the two slots is handled as an empty slot. (16 empty points are occupied
with default setting.) Therefore the I/O number of the slot on the right side
of the PC CPU module is "10H." (Set the empty slot at zero point using I/O
allocation of PLC Parameters dialog box, to assign "00H" to the first I/O
number.)
1) Example of setting the number of CPUs to 2
PC CPU module
Power supply
Basic model QCPU
0 1 2
Empty slot (00H to 0FH occupied)
Number of CPUs
(2 modules)
15 - 1
15 - 1
2)
MELSEC-Q
Example of setting the number of CPUs to 3
PC CPU module
Motion CPU
Power supply
Basic model QCPU
0 1 2
Number of CPUs
(3 modules)
PC CPU module
No CPU
Power supply
Basic model QCPU
0 1 2
Number of CPUs
(3 modules)
REMARK
1) If the number of CPU modules mounted on the main base unit is less than the
number set in the Multiple CPU setting, set the empty slot to "CPU (Empty)".
• The I/O number for the Multiple CPU System can be confirmed with the system
monitor.
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15 - 2
15
MELSEC-Q
15.1.2 I/O number of Basic model QCPU, Motion CPU and PC CPU module
I/O numbers are allocated to the CPU modules with the Multiple CPU System in order
to allow interactive communications between the CPU modules with the following
commands.
• Multiple CPU commands
• Motion dedicated commands
• Dedicated communication commands between multiple CPUs
The I/O numbers for the CPU modules are fixed for the slots on which they are
mounted and cannot be amended.
The table below shows the I/O number allocated to each CPU module when the
multiple CPU system is composed.
CPU module
mounting position
First I/O number
CPU slot
Slot 0
Slot 1
3E00H
3E10H
3E20H
The CPU modules I/O numbers are used in the following cases.
• When writing data to the CPU shared memory with the TO or S.TO instruction 1
• When reading the data of the CPU shared memory with the FROM instruction 1
• When reading or writing data from or to the CPU shared memory with the intelligent
function module device (U \G ) 1
• When specifying the CPU module to be accessed with the Ethernet module. 2
• When specifying the CPU module to be accessed with the serial communication
module. 2
REMARK
1: See Chapter 16 for details on among Basic model QCPU, Motion CPU and PC
CPU module.
2: For access to the Basic model QCPU by the Ethernet module or serial
communication module, refer to the "Q Corresponding MELSEC
Communication Protocol Reference Manual".
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MELSEC-Q
15.2 Setting of Control CPUs with GX Developer
Sets up the Basic model QCPU/motion CPU/PC CPU module that are to control the
Multiple CPU System's I/O modules and intelligent function modules.
(a)
I/O modules and intelligent function modules can be selected as control
CPUs for each slot.
Q38B
PC CPU model
Motion CPU
Power supply
Basic model QCPU
0 1 2 3 4 5 6 7
Q68B
Power supply
8 9 10 11 12 13 14 15
Control CPUs can be
selected for each slot.
Q68B
Power supply
16 17 18 19 20 21 22 23
15 - 4
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16 COMMUNICATION BETWEEN CPU MODULES IN MULTIPLE CPU
SYSTEM
MELSEC-Q
SYSTEM
It is possible to perform the following interactive transmission between each CPU
modules with a Multiple CPU System.
• Write/read of data between the CPU modules by automatic refresh of the CPU
shared memory
• Write/read of data to/from the PC CPU module with the Multiple CPU
instruction, or read of the CPU shared memory data of the Motion CPU from
the Basic model QCPU
• Control command from the Basic model QCPU to the Motion CPU with the
communication dedicated instruction
• Write/read of device data from the Basic model QCPU to the Motion CPU with
the communication dedicated instruction between multiple CPUs
Also, event issuance from the Basic model QCPU to the Motion CPU or PC
CPU module can be performed.
(1) Automatic refresh of CPU shared memory
In the automatic refresh of the CPU shared memory, the systems of the CPU
modules perform the write/read of data between the CPU modules in the Multiple
CPU System automatically at the time of END processing.
Since use of the automatic refresh reads the device memory data of the other
CPUs automatically, the device data of the other CPUs can also be used as the
device data of the host CPU.
CPU No.1(Basic model QCPU)
CPU No.2(Motion CPU)
CPU shared memory
CPU shared memory
Host CPU's operation
information area
information area
System area
Automatic refresh area for
writing in the CPU No.1
16
Automatic read by
main cycle processing
of CPU No. 2
User's free area
User's free area
Automatic write by
main cycle processing
of CPU No. 2
Writing performed with
the CPU No.1 END process
Device memory
For use of the CPU No.1
System area
writing in the CPU No.2
Automatic read by
END processing of
CPU No. 1
Device memory
(2) Exchanging data with multiple CPU instructions and instructions
that use Intelligent function module device (U \G )
The Basic model QCPU of the Multiple CPU System uses the TO instruction,
S.TO instruction, FROM instruction or U \G to make access to the CPU
shared memory.
The data written to the CPU shared memory of the host CPU with the TO
instruction, S.TO instruction or U \G is read by the other CPU modules.
Non-linked device data also read directly when the command is executed.
CPU shared memory
CPU shared memory
information area
information area
System area
System area
Data written with TO instruction,
S.TO instruction or U \G
Read performed with
read instruction
Write performed with TO
instruction, S.TO instruction
or U \G
Sequence program
Execution of TO
instruction, S.TO
instruction or U \G
16 - 1
Program
Execution of read instruction
16 - 1
SYSTEM
MELSEC-Q
16.1 Automatic Refresh of CPU Shared Memory
(a)
In the automatic refresh of the CPU shared memory, the CPU modules
perform the write/read of data between the CPU modules in the Multiple
CPU System automatically.
(The Basic model QCPU as CPU No. 1 performs automatic refresh
processing at END processing or COM instruction execution.)
Since use of the automatic refresh reads the device memory data of the
other CPUs automatically, the device data of the other CPUs can also be
used as the device data of the host CPU.
The automatic refresh of the CPU shared memory enables write/read of
data:
• Between Basic model QCPU and Motion CPU
• Between Basic model QCPU and PC CPU module
• Between motion CPU and PC CPU module
The following diagram shows the general operation performed when the
Basic model QCPU as CPU No. 1 performs the automatic refresh of 32
points, B0 to B1F, and the Motion CPU as CPU No. 2 performs that of 32
points, B20 to B3F.
CPU shared memory
CPU shared memory
information area
information area
System area
writing in the No.1 machine
3) Automatic read by main
cycle processing of CPU
No. 2
User's free area
User's free area
1) Automatic write by END
processing or COM instruction
execution of CPU No. 1
2) Automatic write by main
cycle processing of CPU
No. 2
Device memory
Device memory
B0 to B1F (For use of the CPU No.1)
System area
writing in the No.2 machine
4) Automatic read by
CPU No. 1 (at END
processing)
Automatic refresh processing of CPU No. 1 (at END processing or COM
instruction execution)
1): The B0 to B1F transmission device data for the CPU No.1 is
transferred across to the host CPU shared memory automatic refresh
area.
4): The data in the CPU No.2 CPU shared memory automatic refresh area
is transferred across to B20 to B3F in the host CPU.
Automatic refresh processing of CPU No. 2
2): The B20 to B3F transmission device data for the CPU No.2 is
transferred across to the host CPU shared memory automatic refresh
area.
3): The data in the CPU No.1 CPU shared memory automatic refresh area
is transferred across to B0 to B1F in the host CPU.
16 - 2
(b)
Executing automatic refresh
Automatic refresh is executed when the CPU module is in RUN status,
STOP status or PAUSE status. Automatic refresh cannot be performed
when a stop error has been triggered in the CPU module.
If a stop error occurs on one module, the other modules for which an error
has not occurred will save the data prior to the stop error being triggered.
For example, if a stop error occurs in the CPU No.2 when B20 is ON, the
B20 in the CPU No.1 will remain at ON, as shown in the operation outline in
fig. (a).
(c)
When automatic refresh is carried out, it is necessary to set the points to be
transmitted by each CPU module and the device in which the data is to be
stored (the device that will perform automatic refresh) with the PLC
parameter multiple CPU settings.
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16
SYSTEM
MELSEC-Q
(2) Automatic refresh settings
Set the points to be transmitted by each CPU and the device in which the data is
to be stored with the PLC parameter multiple CPU settings for when automatic
refresh is to performed.
Switching between
setting numbers
Range of transmission
setting for each CPU
module
Sets the header number
of the device for which
automatic refresh is to be
performed
(uses consecutive numbers
from the setup device
number to the number of
specified points)
(a)
Setting switch/range of transmission for each CPU (refresh range)
1): It is possible to set four ranges from Setting 1 to Setting 4 for the
refresh setting with the setting switch. For example, it is possible to set
the refresh function to divide ON/OFF data into bit devices with Setting
1 and other data into word devices with Setting 2.
2): The transmission range for each CPU is set in units of two CPU shared
memory points (two words.) (Becomes 2 points when specifying the
word device with the CPU device, and 32 points when specifying the
bit device.)
PLC data for which the point is set at "0" with the range of transmission
for each CPU will not be refreshed.
As the bit device becomes 16 points at one point of the CPU shared
memory when refreshing is performed with 32 points between B0 and
B1F on the CPU No.1 and with 32 points between B20 and B3F on the
CPU No.2, the number of transmission points is two for the CPU No.1
and two for the CPU No.2.
3): The numbers of transmission points are 320 points for the Basic model
QCPU and 2048 points for the motion CPU/PC CPU module, making
a total of 4416 points (4416 words) for all CPU modules.
• Basic model QCPU: 320 points
• Motion CPU: 2048 points
• PC CPU module: 2048 points
• All CPU modules: 4416 points
(4416 words)
• Setting is in units of
2 points (2 words).
The CPU shared memory
(PLC share memory)
is set in two points, and the
bit device becomes 32 points
when bit device is specified
on the CPU device.
Not refreshed as the number of points for CPU No. 3 is 0.
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SYSTEM
MELSEC-Q
4): The CPU shared memory occupied with automatic refresh refreshing
becomes the total of setting 1 to setting 4.
When the number of transmission points is set, the first and last offset
values of the used CPU shared memory are displayed in hexadecimal.
The PLC where the transmission points have been set in Setting 1 and
Setting 2 becomes the last address in the CPU shared memory of
Setting 2. (In the following figure, up to 11H is used by PLC No. 1 and
up to 23H by CPU No. 3.)
The PLC that transmits only Setting 1 becomes the last address in the
CPU shared memory of Setting 1. (In the following figure, up to the
address of Setting 1 is used by CPU No. 2.)
CPU No.1 transmission range
Last CPU device
Last address of each CPU share memory (PLC shared memory)
5): The same number of transmission points must be set for all CPUs on
the Multiple CPU System. A "PARAMETER ERROR" occurs if the
number of transmission points for one CPU is different.
(b)
CPU devices
The following devices can be used for automatic refresh purposes (other
devices cannot be set up with the GX Developer.)
Settable devices
Caution
Data register (D)
Link register (W)
None
File register (R, ZR)
Link relay (B)
• Multiples of 0 or 16 are specified for the first number.
Internal relay (M)
• The device in the left column occupies one point for
Output (Y)
1)
16 - 4
every transmission point.
CPU devices use the total amount of transmission point devices
consecutively from the specified device number to the CPU No.1 to
No.3 in the first set range.
Set a device number so that the amount of transmission point devices
can be secured.
Sixteen times the number of transmission points will be set if a bit
device is specified in the CPU device.
For example, If the total number of transmission points for CPU No.1
to No.3 is eight, then 128 points will be set between B0 and B7F when
the B0 link relay is specified.
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SYSTEM
MELSEC-Q
2)
The CPU devices are set as follows.
• It is possible to change the device and set up settings 1 to 4.
The same devices can also be specified as long as the device range
for settings 1 to 4 are not duplicated.
Setting 1: In the case of link relays
• It is possible to change the device
and set up settings 1 to 4.
Setting 2: In the case of link registers
Setting 3: In the case of link relays
• The same devices can be specified
for settings 1 to 4. However, as setting
1 in the illustration on the left uses
128 points between B0 and B7F,
B80 and higher can be used for setting 3.
No part of a device number can be
duplicated, as shown with B0 to B7F
on setting 1 and B70 to BEF on setting 3.
The first and last will be calculated automatically with the GX Developer
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SYSTEM
MELSEC-Q
• Each of the setting 1 to setting 4 devices can be set up
independently.
For example, the Basic model QCPU as CPU No. 1 can be set to the
link relay, and the Motion CPU as CPU No. 2 to the internal relay.
Refresh setting for Basic model QCPU
• When the Basic model QCPU and
Motion CPU devices have been set
up with different devices
Set the same point for all the CPU.
Refresh setting for Motion CPU
• When the Basic model QCPU and
Motion CPU devices have been set
up with the same device
16 - 6
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SYSTEM
MELSEC-Q
3)
An outline of the operations when the automatic refresh function is
divided into four ranges (Setting 1: Link relay (B), Setting 2: Link
register (W), Setting 3: Data register (D), Setting 4: Internal relay (M))
and then performed is shown in the illustration below.
CPU No.1
Other CPU's
shared memory
Reading performed
with the CPU No.1
END process
Device
Setting 1
B0
CPU No.1
CPU shared memory
Writing during the
END process
transmission
data (No.1)
to
CPU No.1
transmission
data (No.1)
CPU No.2
CPU No.2 transmission
data (No.2)
CPU No.3 reception
data (No.1)
data (No.3)
W
CPU No.1
transmission
data (No.2)
CPU No.1
transmission
data (No.2)
Maximum
320 words
CPU No.1
transmission
data (No.3)
CPU No.1
transmission
data (No.4)
data (No.4)
Setting 3
D0
ing
du
r
CPU No.1
transmission
data (No.3)
CPU No.2 reception
data (No.3)
es
s
g
rit
in
EN
Dp
Maximum
320 words
he
data (No.3)
User's free area
W
CPU No.3 reception
data (No.2)
gd
ur i
ng
t
data (No.2)
CPU No.2 reception
data (No.2)
Wr
itin
data (No.1)
th
e
CPU No.3
Maximum
2048 words
D
EN
pr
Setting 2
W0
he
EN
D
data (No.4)
du
ng
riti
gt
rin
ss
ce
pr o
roc
Maximum
2048 words
CPU No.2 reception
data (No.1)
oc
es
s
data (No.1)
CPU No.3 reception
data (No.3)
Setting 4
M0
CPU No.1
transmission
data (No.4)
CPU No.2 reception
data (No.4)
CPU No.3 reception
data (No.4)
16 - 7
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SYSTEM
MELSEC-Q
(c)
There are cases where old data and new data will become mixed up for
each PLC depending on the timing of refreshing the host CPU and reading
data from other CPUs.
When performing automatic refresh, create an interlock program that uses
the first refresh device of each CPU, and do not use the data of the other
CPUs when old and new data exist together.
The following example gives the programs of the Basic model QCPU and
Motion CPU where the refresh settings in the Multiple CPU setting are as
indicated below.
<Parameter setting>
CPU Shared Memory
Setting No.
CPU No.
Number
of points
Setting 1
Setting 2
First
Last
First
Last
CPU No. 1
2
00C0
00C1
M0
M31
CPU No. 2
2
0800
0801
M32
M63
CPU No. 1
10
00C2
00CB
D0
D9
CPU No. 2
0
—
—
—
—
Receive side program: Motion SFC
Send side program: Ladder
X0
CPU Side Device
1)
Send data processing (D0 to D9)
[
2)
SET
M0
]
[
RST
M0
]
[
RST
X0
]
6) M32
3)
[G0]
M0
4)
[F0]
Data receive processing
(D0 to D9)
5)
[F1]
SET M32
1) CPU No. 1 creates send data.
2) CPU No. 1 sets the data setting completion bit.
<Automatic refresh execution between multiple CPUs>
3) CPU No. 2 detects the completion of send data setting.
4) CPU No. 2 performs receive data processing.
5) CPU No. 2 sets the completion of receive data processing.
<Automatic refresh execution between multiple CPUs>
6) CPU No. 1 detects the completion of the receive data processing and
proceeds to the next processing.
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SYSTEM
MELSEC-Q
16.2 Communication with Multiple CPU Instructions and Intelligent Function Module Devices
(1) Communication with Multiple CPU instructions (TO instruction / S.
TO instruction / FROM instruction) and intelligent function module
device (U \G )
The Basic model QCPU of a Multiple CPU System can use an TO instruction, S.
TO instruction, FROM instruction and intelligent function module device
(U \G ) to access the CPU shared memory of the Basic model QCPU, Motion
CPU and PC CPU module.
The data written to the CPU shared memory of the host CPU with the TO
instruction, S.TO instruction or U \G can be read by the other CPU modules.
Unlike the automatic refresh of the CPU shared memory, the data at the time of
instruction execution can be read directly.
The following diagram shows the general operation performed when the data
written to the CPU shared memory by the Basic model QCPU as CPU No. 1 with
the TO instruction, S.TO instruction or U \G is read by the CPU module No. 2
with the read instruction.
CPU shared memory
CPU shared memory
information area
information area
System area
System area
Data written with TO instruction,
S.TO instruction or U \G
2)Read performed with
read instruction
1) Write performed with TO
instruction, S.TO instruction
or U \G
Sequence program
Execution of TO
instruction, S.TO
instruction or U \G
Program
Execution of read instruction
Processing of CPU No. 1
1): Data is written to the free user area of CPU No. 1 with the TO
instruction, S.TO instruction or U \G
2): The data of the free user area of CPU No. 1 is read to the specified
device with the read instruction.
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SYSTEM
MELSEC-Q
CPU shared memory
CPU shared memory
information area
information area
System area
System area
2)Read performed with
FROM instruction or
U \G
Data written with
write instruction
1) Write performed with
write instruction
Sequence program
FROM instruction execution
Program
Write instruction
execution
1): Data is written to the free user area of CPU No. 2 with the write
instruction.
2): The data of the free user area of CPU No. 1 is read to the specified
device with the FROM instruction or intelligent function module device
(U \G ).
Refer to the following manual for details of the TO instruction, S.TO
instruction and FROM instruction.
QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)
POINT
The Motion CPU and PC CPU module cannot use the TO instruction, S.TO
instruction, FROM instruction and intelligent function module device (U \G ).
Refer to the manuals of the corresponding CPU modules for how to make access
from the Motion CPU and PC CPU module to the CPU shared memory.
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SYSTEM
MELSEC-Q
(2) Precautions
(a)
The following values are set in the CPU module's first I/O number with the
FROM instruction, the TO instruction, the S. TO instruction and instructions
that use U \G .
CPU No.
CPU No.1
CPU No.2
CPU No.3
Value set in the first I/O number
3E0H
3E1H
3E2H
(b)
Do not perform writing as reading in the system area or automatic refresh
area for the CPU shared memory (see Section 16.4).
(c)
An error will not occur when CPUs accessed with the FROM instruction, the
S. TO instruction and instructions that use U \G are reset.
(d)
Establish an interlock to prevent simultaneous access during interactive
data communication with the FROM instruction, the TO instruction, the S.
TO instruction and instructions that use U \G .
There are cases where old data and new data will be mixed together if
simultaneous access is carried out.
(e)
The instruction that uses the TO instruction/ S. TO instruction/U \G
cannot be used to write data to the CPU shared memory of other CPUs.
"SP. UNIT ERROR (error code: 2115)" occurs if data is written to the CPU
shared memory of other CPUs with the instruction that uses U \G .
"SP. UNIT ERROR (error code: 2117)" occurs if data is written to the CPU
shared memory of other PLCs with the instruction that uses the S. TO
instruction.
(f)
The data of the CPU shared memory can be read with the FROM
instruction or the instruction that uses U \G .
( g) The instruction that uses U \G cannot be used to make access to a CPU
not yet mounted.
"SP UNIT ERROR (error code: 2110)" occurs if access is made to a CPU
not yet mounted with the instruction that uses U \G .
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MELSEC-Q
16.3 Interactive Communications between The Basic model QCPU and Motion CPU
16.3.1 Control commands from the Basic model QCPU to the Motion CPU
(Motion dedicated instructions)
It is possible to issue control commands from the Basic model QCPU to the Motion
CPU, and read and write device data with the Motion dedicated PLC instructions listed
below.
Instruction name
Description
S.SFCS
SP.SFCS
Requests startup of the motion SFC program.
S.SVST
SP.SVST
Requests the start of operations for the servo program.
S.CHGV
SP.CHGV
Changes the speed of the axes during positioning and JOG operations.
S.CHGT
SP.CHGV
Changes the torque control value during operation and suspension when in
the real mode.
S.CHGA
SP.CHGA
Changes the current values of the halted axes, the synchronized encoder,
and the cam axes.
For example, it is possible to start up the Motion CPU's motion SFC from the Basic
model QCPU with the S (P).SFCS instruction.
Basic model QCPU
Motion SFC
Startup
request
Motion SFC
S.SFCS instruction
POINT
The Basic model QCPU can execute up to 32 instructions of the "motion dedicated
instructions" and "communication dedicated instructions between multiple CPUs
except S(P).GINT instruction" simultaneously. However, if the Motion dedicated
PLC instructions and communication dedicated instructions between multiple CPUs
(omitting S (P).GINT instruction) are made at the same time, the instructions will be
executed in order from the first instruction accepted. If there are 33 or more
unexecuted instructions, an "OPERATION ERROR (error code: 4107)" will be
triggered.
REMARK
Refer to the Motion CPU Programming manual for details on and the necessity of
use of the motion only instructions.
16 - 12
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SYSTEM
MELSEC-Q
16.3.2 Reading and writing device data(Between Multiple CPU communication dedicated
instruction)
It is possible to read and write device data into the Motion CPU/PC CPU module from
the Basic model QCPU with the the communication dedicated instructions between
multiple CPUs listed in the table below.
(Write/read from the motion CPU to the Basic model QCPU or from the PC CPU
module to the Basic model QCPU cannot be performed.)
CPU module
Instruction name
Description
Motion
CPU
S.DDWR
SP.DDWR
Writes host CPU device data into other CPU devices.
S.DDRD
SP.DDRD
Reads other CPU device data into the host CPU.
S.GINT
SP.GINT
Requests start up of other CPU interruption programs.
PC CPU
module
For example, Basic model QCPU device data can be written into the Motion CPU's
device data with the S.DDWR instruction of the communication dedicated instruction
between multiple CPUs.
Basic model QCPU
S.DDWR instruction
Reads the device
memory
Device memory
Motion CPU
Writes in the
device memory
Device memory
POINT
The Basic model QCPU can execute up to 32 instructions of the "motion dedicated
instructions" and "communication dedicated instructions between multiple CPUs
except S(P).GINT instruction" simultaneously. However, if the Motion dedicated
PLC instructions and communication dedicated instructions between multiple CPUs
(omitting S (P).GINT instruction) are made at the same time, the instructions will be
executed in order from the first instruction accepted. If there are 33 or more
unexecuted instructions, an "OPERATION ERROR (error code: 4107)" will be
triggered.
REMARK
Refer to the Motion CPU Programming Manual for details on and the necessity of
use of the communication dedicated instructions between multiple CPUs.
16 - 13
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SYSTEM
MELSEC-Q
16.4 CPU Shared Memory
The CPU shared memory is for exchanging data between CPU modules, and consists
of 4,096 words between 0H and FFFH.
The CPU shared memory consists of four areas; the host CPU operation information
area, the system area, the automatic refresh area, and the user's free area.
An area consisting of the number of automatic refresh points from 0C0H is used as the
automatic refresh area when the automatic refresh of device data is set up.
The beginning of the user's free area starts from the address immediately after the end
of the automatic refresh area.
0C0H to 0D1H becomes the automatic refresh area if the number of automatic refresh
points is 18 (12H points,) and the area after 0D2H becomes the user's free area.
The configuration of the CPU shared memory and the necessity of accessing
sequence programs are shown in the illustration below.
Host CPU
CPU shared memory
Writing
Host CPU operation
information area
1
Other CPUs
Reading
Writing
Disable
Enable
Disable
Enable
System area
Disable
Enable
Disable
Enable
Automatic refresh area
Disable
Enable
Disable
Enable
User's free area
Enable
Enable
Disable
Enable
Reading
2
0H
to
5FH
60H
to
BFH
C0H
to
1FFH
REMARK
1: Use the TO instruction, S.TO instruction or intelligent function module device
(/U \G ) to perform write from the Basic QCPU to the free user area of the
host CPU.
Refer to the manual of the Motion CPU for write to the free user area of the host
PLC by the Motion CPU.
Refer to the manual of the PC CPU module for write to the free user area of the
host CPU by the PC CPU module.
2: Refer to the manuals of the corresponding CPU modules for read from the
Motion CPU and PC CPU module.
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SYSTEM
MELSEC-Q
(1) Host CPU operation information area (0H to 5FH)
(a)
The following information is stored in the host CPU with Multiple CPU
Systems. These will all remain as 0 and will not change in the case of
Single CPU Systems. 1
Table 16.1 List of host CPU operation information area
CPU shared
memory
address
Name
Detail
Description
2
0H
Information
availability
Information
availability flag
The area to confirm if information is stored in the host CPU's
operation information area (1H to 1FH,) or not.
• 0: Information not stored in the host CPU's operation
information area
• 1: Information stored in the host CPU's operation information
area
1H
Diagnostic error
Diagnostic error
number
The numbers of errors during diagnostics is stored with BIN.
2H
3H
4H
5H
6H
to
10H
11H
to
1BH
1CH
1DH
1EH
1FH
The year and month that the error number was stored in the
CPU shared memory's 1H address is stored with two digits of the
BCD code.
The day and time that the error number was stored in the CPU
Time the diagnosis Time the diagnosis
shared memory's 1H address is stored with two digits of the BCD
error occurred
error occurred
code.
The minutes and seconds that the error number was stored in
the CPU shared memory's 1H address is stored with two digits of
the BCD code.
Stores an identification code to determine what error information
Error information
Error information
has been stored in the common error information and individual
identification code identification code
error information.
—
SD0
SD1
SD2
SD3
SD4
Cannot be used
Stores the CPU module switch status.
Stores the CPU module's LED bit pattern.
SD5
to
SD15
SD16
to
SD26
—
SD200
SD201
Stores the CPU module's operation status.
SD203
Common error
information
Common error
information
The common information corresponding with the number of the
error during diagnostic is stored.
Individual error
information
Individual error
information
The individual information corresponding with the number of the
error during diagnostic is stored.
Empty
Switch status
LED status
CPU operation
status
—
CPU switch status
CPU-LED status
CPU operation
status
(b)
Corresponding
special register
The other CPU can read the data of the host CPU operation information
area with the read instruction.
However, since there is a delay in data update, use the read data for
monitoring.
REMARK
1: For the Motion CPU, 5H to 1CH of the host CPU's operation information area is
not used. If 5H to 1CH of the host PLC's operation information area is read from
the Motion CPU, it will be read as "0."
2: Refer to the corresponding special registers for further details.
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SYSTEM
MELSEC-Q
(2)
System area (60H to BFH)
Area used by the system (OS) of the Basic model QCPU.
(3) Automatic refresh area
Area used for the automatic refresh of the Multiple CPU System.
Write using the TO instruction, S.TO instruction or intelligent function module
device (U \G ) cannot be performed.
(4) User's free area
Area to make communication between the CPU modules with the FROM
instruction, TO instruction, S.TO instruction and/or instruction that uses intelligent
function module device (U \G ) in the Multiple CPU System.
The area later than the points set for the automatic refresh area is used.
(When automatic refresh is not made, C0H to 1FFH of the Basic model QCPU
can be used as the free user area.)
16 - 16
16 - 16
17 COMMUNICATIONS BETWEEN THE MULTIPLE CPU SYSTEM'S I/O
MODULES AND INTELLIGENT FUNCTION MODULES
MELSEC-Q
17.1 Range of Control CPU Communications
The relationship between control CPUs and control modules (I/O modules, intelligent
function modules, special function modules) is the same as with independent CPU
systems.
There is no restriction to control the control module with the control CPU.
17.2 Range of Non-control CPU Communications
It is possible for non-control CPUs to read the contents of the intelligent function
module's buffer memory.
It is also possible to load non-control module input (X) ON/OFF data and another CPU
module output (Y) ON/OFF data with the PLC parameters.
The ON/OFF data of the input modules/hybrid I/O modules controlled by the other
CPUs can be used as interlocks of the host CPU, or the output statuses to the external
devices controlled by the other CPUs can be checked, for example.
However, the non-control CPUs cannot output ON/OFF data to the output
modules/hybrid I/O modules/intelligent function modules acting as the non-controlled
modules, and cannot perform write to the buffer memory of the intelligent function
modules.
17
17 - 1
17 - 1
MELSEC-Q
(1) Loading of input (X) from input modules, hybrid I/O modules and
The "Out of group input/output settings" in the Multiple CPU setting of the PLC
parameter dialog box determine whether input can be loaded from the input
modules, hybrid I/O modules and intelligent function modules being controlled by
the other CPUs.
Out of group input/output settings
The input condition outside the group is taken:
The output condition outside the group is taken:
(a)
When "Load input condition outside of group" has been set
1)
Loads ON/OFF data from the input, hybrid I/O and intelligent function
modules being controlled by the other CPUs by performing input
refresh before a sequence program calculation starts.
2)
Input (X) loading is performed for the modules mounted onto the
following additional base unit slots.
I/O allocation type
None
Input
Intelli.
(b)
17 - 2
Mounted module
Remarks
Input module
—
—
Input module
—
Output module
17
Loads OFF data
Hybrid I/O module
—
—
3)
It is possible to load ON/OFF data from the input modules, hybrid I/O
modules and intelligent function modules by direct access input.
4)
Remote station input, such as empty slots, MELSECNET/H and CCLink, cannot be loaded.
Use automatic refresh of device data to use the ON/OFF input data for
MELSECNET/H, CC-Link and other remote stations in other PLCs.
When "Do not load input condition outside of group" has been set
It is not possible to load ON/OFF data from the input modules, hybrid I/O
modules and intelligent function modules being controlled by the other
CPUs (remains at OFF).
17 - 2
MELSEC-Q
(2) Loading output (Y)
The "Out of group input/output settings" in the Multiple CPU setting of the PLC
parameter dialog box determine whether output can be loaded to the output
modules, hybrid I/O modules and intelligent function modules being controlled by
the other CPUs.
Out of group input/output settings
The input condition outside the group is taken:
The output condition outside the group is taken:
(a)
When "Load output condition outside of group" has been set
1)
Loads to the output (Y) of the host CPU the ON/OFF data that is output
to the output, hybrid I/O and intelligent function modules by the other
CPUs by performing output refresh before a sequence program
calculation starts.
2)
Output (Y) loading is performed for the modules mounted onto the
following additional base unit slots.
I/O allocation type
None
Mounted module
Output module
Input module
Output
Output module
Hybrid I/O module
Intelli.
3)
(b)
17 - 3
The output of an empty slot or the CC-Link or other remote station
cannot be loaded.
When the ON/OFF data of the output to the CC-Link or other remote
stations is to be used by the other CPUs, use the automatic refresh of
the CPU shared memory to send to the other CPUs the ON/OFF data
of the output to the remote stations.
When "Do not load output condition outside of group" has been set
It is not possible to load the ON/OFF data output to the output modules,
hybrid I/O modules and intelligent function modules by the other CPUs into
the output (Y) of the host CPU (remains at OFF).
17 - 3
MELSEC-Q
(3) Output to output modules, hybrid I/O modules and intelligent
function modules
It is not possible to output ON/OFF data to non-controlled modules.
ON/OFF will be performed within the Basic model QCPU when the output from
the output modules, hybrid I/O modules and intelligent function modules
controlled by the other CPUs with sequence programs, etc. have been set to
ON/OFF, but this will not be output to the output modules, hybrid I/O modules or
(4) Accessing the intelligent function module buffer memory
0
1
2
3
4
5
6
7
Motion CPU No.2
Input module
Output module
Intelligent
Intelligent
functionmodule
module
function
Intelligent
function module
Input module
Output module
Intelligent
function module
PLC No.1
PLC No.1
PLC No.1
PLC No.1
PLC No.2
PLC No.2
PLC No.2
It is possible to read data from the buffer memory of intelligent function
modules being controlled by other CPUs with the commands listed below.
• FROM command
• Commands that use intelligent function module devices (U \G )
Power supply
(a)
Slot No.
Control CPU
settings
Read from buffer memory can be performed.
Readable from the buffer memory with the
FROM command and U \G
7
Input module
Output module
Intelligent
function module
Intelligent
function module
Input module
Output module
Intelligent
function module
PLC No.2
6
PLC No.2
5
PLC No.2
4
PLC No.1
3
PLC No.1
2
PLC No.1
1
PLC No.1
0
Motion CPU No.2
The following instructions cannot be used to perform write to the buffer
memory of the intelligent function modules being controlled by the other
CPUs.
• TO instruction
• S.TO instruction
• Intelligent function module device (U \G )
• Intelligent function module dedicated instruction
An "SP UNIT ERROR (error code: 2116)" will be triggered if an attempt to
write in the intelligent function module controlled by other CPUs is carried out.
Power supply
(b)
Slot No.
Control CPU
settings
Write to buffer memory
cannot be performed.
Not writable write in the buffer memory
with the TO command and U \G
17 - 4
17 - 4
MELSEC-Q
(5) Accessing MELSECNET/H modules
Only control CPUs can access MELSECNET/H modules.
Link direct devices cannot be used in MELSECNET/H modules being controlled
by other CPUs.
"OPERATION ERROR (error code: 4102)" occurs if a program that uses link
direct devices is used in MELSECNET/H modules being controlled by other
CPUs.
17 - 5
17 - 5
18 PROCESSING TIME FOR MULTIPLE CPU SYSTEM BASIC MODEL
QCPUs
MELSEC-Q
QCPUs
18.1 Concept behind Scan Time
The concept behind Multiple CPU System scanning time is the same as the Single
CPU System.
See Section 11.1 for details of the scan time concept.
This chapter provides explanations on the factors to be added to the scan time
calculated as explained in Section 11.1 and the method of calculating processing time
when configuring Multiple CPU Systems.
Input refresh time is calculated in accordance with the equation explained in
Section 11.1.
The I/O refresh time for the following values only are prolonged when bus access
overlaps with other CPUs.
(Prolonged time) =
(input points + output points)
N3
(number of other CPUs) ( s)
16
Use the following values for N3
N3
CPU type
Q00CPU
Systems with only a main base Systems that include additional
unit
base units
8.7
s
21
s
Q01CPU
(2) Total value of command execution time
Refer to the following manual for details on the processing time of special
Multiple CPU commands, and the processing time for commands that have
different processing times with Multiple CPU Systems.
• QCPU (Q mode)/QnACPU Programming Manual (Common Instructions)
(3) END process
The following tables shows the END processing time.
CPU type
18 - 1
END processing time
Q00CPU
(0.05 to 0.13)
(number of other CPUs)ms
Q01CPU
(0.05 to 0.13)
(number of other CPUs)ms
18 - 1
18
QCPUs
MELSEC-Q
18.2 Factor to Prolong the Scan Time
The processing time for Multiple CPU Systems is prolonged in comparison with Single
CPU Systems when the following functions are used.
Add the following values to the values calculated in Sections 11.1 and 18.a to acquire
the amount of time used by these functions.
• Multiple CPU System automatic refresh
• MELSECNET/H refreshing
(a)
The amount of time required to perform the refresh function set up with the
Multiple CPU settings.
This value is the total amount of time required for writing into the host
CPU's CPU shared memory, and the amount of time required to read from
other CPUs' CPU shared memories.
These values are added when setting up the refresh settings with the PLC
parameter Multiple CPU settings.
(b)
The automatic refresh period of the CPU shared memory is calculated in the
following equation.
(Automatic refresh time) = (N1 + (transmitted word points) N2) +
(N3 + (number of other CPUs) N4+
(received word points) N5) ( s)
• The number of received word points is the sum of the numbers of word points transmitted by
the other CPUs.
For example, when the host PLC is CPU No. 1, this value is the sum of the numbers of word
points transmitted by CPU No. 2 and No. 3.
• For N1 to N5, use the values in the following table.
CPU type
18
(c)
N1
N2
N3
N4
N5
Q00CPU
63
s
1.13
s
63
s
161
s
0.88
s
Q01CPU
57
s
1.03
s
57
s
146
s
0.80
s
The amount of time required for the automatic refresh process will be
prolonged by the following amount of time when processing is duplicated
with the automatic refresh function on other CPUs.
(Prolonged time) = 4
(transmitted word points) N6
For N6, use the value in the following table.
N6
CPU type
Q00CPU
Systems with only a main base Systems that include additional
unit
base units
0.54
s
1.3
s
Q01CPU
18 - 2
18 - 2
QCPUs
MELSEC-Q
(2) MELSECNET/H refresh
(a)
Refresh time between the Basic model QCPU and MELSECNET/H network
module.
Refer to the following manual for details on the refresh time for
MELSECNET/H.
• Q Corresponding MESLECNET/H Network System Refresh Manual
(b)
The amount of time required for the automatic refresh process will be
prolonged only by the following amount of time when requests for
refreshing are issued by other MELSECNET/H modules at the same time
on a Multiple CPU System.
(Prolonged time) = 4
(transmitted word points) N6
The number of words transmitted/received is the total value of the following transferal data.
(LB + LX + LY + SB)
• Link refresh data
:
+ LW+ SW
16
(LB + LX + LY + SB)
• Data transferred to the memory card's file register
:
+ LW+ SW
16
LB
:(
+ LW)
2
• Transferal between data links
16
Refer to the following table for N6
N6
CPU type
Q00CPU
Systems with only a
main base unit
0.54
s
Systems that include
additional base units
1.30
s
Q01CPU
18 - 3
18 - 3
MELSEC-Q
This Chapter explains the standard procedures for starting up the Multiple CPU System.
19.1 Flow-chart for Starting Up the Multiple CPU System
Start
Clarification of function sharing in Multiple
CPU System
•••••••••••••••••••• To use automatic refresh of PLC share memory,
reserve continuous refresh points.
For automatic refresh of PLC share memory, see
section 16.1.
•••••••••••••••••••• Select the modules for realizing the functions executed in
the Multiple CPU System.
Purpose of each device and allocation
Selection of module to be used
Installation of module
•••••••••••••••••••• Install the selected module to the main base unit and
expansion base units.
GX Developer startup
•••••••••••••••••••• Start the GX Developer Version 6 or later.
For the starting method, refer to the GX Developer
operating manual.
Multiple CPU setting, control CPU setting
and other parameter settings.
Creation of sequence programs
•••••••••••••••••••• Create parameters and sequence programs for CPU No.1
to No.4. For Multiple CPU settings and control CPU
settings, see sections 16.1 and 19.2. For automatic
refresh of device data, see section 16.1.
Parameter setting and program creation
of Motion CPU
•••••••••••••••••••• Refer to the manual of the Motion CPU.
Parameter setting and program creation
of PC CPU module
•••••••••••••••••••• Refer to the manual of the PC CPU module.
CPU power-ON
19
•••••••••••••••••••• Clarify the control and functions executed by each CPU.
Connection of personal computer and
Basic model QCPU (CPU No. 1) 1
Parameter and program writing
CPU No.1 QCPU resetting
1)
•••••••••••••••••••• Select STOP at the RUN/STOP switch of the QCPU and
turn off the RESET/L.CLR switch and turn on the PLC.
•••••••••••••••••••• Connect the personal computer where GX Developer has
been started and the Basic model QCPU with the RS-232
cable.
•••••••••••••••••••• Write the parameters and programs.
•••••••••••••••••••• Set the RESET/L. CLR switch of the QCPU of the PLC
No.1 in the RESET position.
1: When the PC CPU module is used, installing GX Developer Version 8 or
later into the PC CPU module enables the Basic model QCPU and GX
Developer to be connected via the bus.
For details, refer to the operating manual of GX Developer Version 8 or later.
19 - 1
19 - 1
MELSEC-Q
1)
Write of parameters and programs to
Motion CPU
Write of parameters and programs to PC
CPU module
•••••••••••••••••••• Refer to the manual of the Motion CPU.
•••••••••••••••••••• Refer to the manual of the PC CPU module.
Reset of Basic model QCPU as CPU No. 1 •••••••••••••••••••• Move the RUN/STOP/RESET switch of the Basic model
QCPU to the RESET position.
RUN/STOP switch setting of all CPUs
Cancellation of resetting of QCPU of
CPU No.1
Status confirmation of all CPUs
•••••••••••••••••••• Select RUN at the RUN/STOP switch of the QCPU for PLC
No.1 to No.3.
•••••••••••••••••••• Set the RESET/L. CLR switch of the QCPU for the PLC No.1
in the OFF position to cancel resetting.
Check to see if a RUN status error has occurred with all
•••••••••••••••••••• PLCs on the Mulitple CPU System when the reset status
for the CPU No.1 is canceled.
Confirmation and recovery of errors
All CPUs debugged
•••••••••••••••••••• If errors occurs, confirm the details and recover the situation
with the GX Developer's system monitor.
•••••••••••••••••••• CPU No.1 to CPU No.3 on the Multiple CPU System debugged
individually.
Start of actual operations
End
19
19 - 2
19 - 2
MELSEC-Q
19.2 Setting Up the Multiple CPU System Parameters (Multiple CPU Settings, Control CPU
Settings)
This section explains the procedures for setting up the Multiple CPU System
parameters with GX Developer.
Refer to the GX Developer's operation manual for details on setting up all other
parameters.
19.2.1 System configuration
The following shows an example procedures for setting up the Multiple CPU System
parameters.
19 - 3
Input module/PLC
No. 1
Input module/PLC
No. 1
Output module/PLC
No. 1
module/PLC No. 1
Input module/PLC
No. 2
Output module/PLC
No. 2
No CPU/PLC No. 3
Basic model
QCPU/PLC No. 1
Motion CPU/PLC
No. 2
module/PLC No. 2
Input module/PLC
No. 1
Output module/PLC
No. 2
Input module/PLC
No. 1
Output module/PLC
No. 2
Power supply
Power supply
GX Developer
19 - 3
MELSEC-Q
19.2.2 Creating new systems
Start
GX Developer started up
Refer to GX Developer operating manual
PC parameter window on the
GX Developer opened
Refer to GX Developer operating manual
Select "Multiple CPU Settings" to display the Multiple CPU
setup window.
Setting the number of CPUs (required item)
• Sets the number of CPU modules to be
mounted onto the main base unit with the
1)
19 - 4
19 - 4
MELSEC-Q
1)
Setting the operating mode (optional)
• Selects whether to halt operations for all CPUs
or continue with operations when a stop error occurs.
Default: Stop all CPUs upon a stop error of either CPU No.2
or No. 3.
(Checked)
• For example, if the tick beside the "All station stop by stop
error of CPU2" is removed, the operations for
all other CPUs will continue even when an error occurs
in the CPU No.2.
• The operation mode for the CPU No.1 cannot be changed.
Out of the group input/output settings (optional)
• Sets whether or not the I/O status of non-control
CPUs are acquired.
Default:Default: Do not acquire.
(No check)
Refresh setting (option)
• Set the device that will make data communication by automatic
refresh between the CPU modules and the number of points of
the automatic refresh area.
• The number of points of the automatic refresh area, starting from
the device number set as the first device are used consecutively.
One point of the automatic refresh area occupies the number of
points in the following table.
Device
Occupied Points
B, M, Y
16 points
D, W, R, ZR
1 point
2)
19 - 5
19 - 5
MELSEC-Q
2)
Selects "CPU (Empty)" for the slots on which CPU
modules are not to be mounted by type.
Select "Detailed Settings" on the I/O assignment window
to display the detail settings window.
Control CPU settings (required item)
• Select the control CPU (CPU No. 1 to No. 3) for each slot.
• For the intelligent function module of function version A,
set PLC No. 1 as the control CPU.
Setup of parameters other than
the Multiple CPU System settings.
Set parameters written onto the hard disk
or floppy disk.
End
19 - 6
19 - 6
MELSEC-Q
19.2.3 Using existing preset Multiple CPU settings and I/O allocations
Start
GX Developer started up
Refer to the GX Developer's operation manual
Opens the GX Developer's PC parameter setup window.
Select "Multiple CPU settings" to display the Multiple CPU
setup window.
Transferring Multiple CPU settings
Click on "Diversion Multiple CPU parameters."
Setting up transferred projects
• Select the project into which existing Multiple CPU settings
and I/O allocations are to be transferred.
• Click on "Open."
1)
19 - 7
19 - 7
MELSEC-Q
1)
The Multiple CPU settings and I/O Assignment Setting data are
read and written into the specified project when "OK" is selected.
Confirming the Multiple CPU settings
When changing the CPU devices in the "Refresh settings",
enter the device number after it has been changed.
(" " indicates the item can be changed.)
Confirm the I/O Assignment and standard settings on the
I/O Allocation Window.
Select "Detailed Settings" to display the detailed
setting window.
Confirm the control CPU settings.
2)
19 - 8
19 - 8
MELSEC-Q
2)
Setup of parameters other than
the Multiple CPU System settings.
Set parameters written onto the hard disk
or floppy disk.
End
19 - 9
19 - 9
APPENDICES
MELSEC-Q
APPENDICES
APPENDIX 1 Special Relay List
Special relays, SM, are internal relays whose applications are fixed in the
programmable controller.
For this reason, they cannot be used by sequence programs in the same way as the
normal internal relays.
However, they can be turned ON or OFF as needed in order to control the CPU and
remote I/O modules.
The headings in the table that follows have the following meanings.
Item
Number
Name
Meaning
Explanation
Set by (When set)
Function of Item
• Indicates the number of the special relay.
• Indicates the name of the special relay.
• Indicates the nature of the special relay.
• Contains detailed information about the nature of the special relay.
• Indicates whether the relay is set by the system or user, and, if it is set by the system, when
setting is performed.
<Set by>
S
: Set by system
U
: Set by user (in sequence program or test operation at a peripheral device)
S/U
: Set by both system and user
<When set> indicated only if setting is done by system.
Each END
: Set during each END processing
Initial
: Set only during initial processing
(when power supply is turned ON, or when going from STOP to
RUN)
Status change
: Set only when there is a change in status
Error
: Set when error is generated
Instruction execution : Set when instruction is executed
Request
: Set only when there is a user request
(through SM, etc.)
For details on the following items, see these manuals:
• Networks
• Far Q MELSECNET/H Network System Reference Manual (PLC to PLC
network)
APP
App - 1
App - 1
APPENDICES
MELSEC-Q
Special Relay List
(1) Diagnostic Information
Number
Name
SM0
Diagnostic errors
SM1
Self-diagnosis
error
SM5
Error common
information
SM16
Error individual
information
SM50
Error reset
SM51
Battery low latch
SM52
Battery low
SM53
AC/DC DOWN
detection
SM56
Operation Errors
SM60
Blown fuse
detection
SM61
I/O module
verification error
Annunciator
detection
Serial
communication
SM100
function using
flag
Communication
SM101 protocol status
flag
SM62
SM110 Protocol error
APP
Meaning
OFF : No error
ON : Error
OFF : No self-diagnosis
errors
ON : Self-diagnosis
OFF : No error common
information
ON : Error common
information
OFF : No error common
information
ON : Error common
information
Explanation
• Turns ON if an error occurs as a result of diagnosis.
(Includes when an annunciator is ON)
• Remains ON if the condition is restored to normal thereafter.
• Turns ON if an error occurs as a result of diagnosis.
(Does not include when an annunciator is ON)
S (Error)
S (Error)
• When SM0 is ON, ON if there is error individual information
S (Error)
ON : Error reset
U
S (Error)
S (Error)
S (Error)
S (Error)
S (Error)
S (Error)
S (Instruction
execution)
S (Power-on
or reset)
S (RS232
communication)
OFF : Normal
ON : Abnormal
• Turns ON when an abnormal protocol was used to make
communication in the serial communication function.
S (Error)
S (Error)
SM111
Communication
status
OFF : Normal
ON : Abnormal
• Turns ON when the mode used to make communication was
different from the setting in the serial communication function.
SM112
Error information
clear
ON : Cleared
• Turns ON when the error codes stored in SM110, SM111, SD110
and SD111 are cleared. (Activated when turned from OFF to ON)
SM113 Overrun error
OFF : Normal
ON : Abnormal
• Turns ON when an overrun error occurred in the serial
S (Error)
SM114 Parity error
OFF : Normal
ON : Abnormal
• Turns ON when a parity error occurred in the serial
S (Error)
SM115 Framing error
OFF : Normal
ON : Abnormal
• Turns ON when a framing error occurred in the serial
S (Error)
App - 2
Corresponding
CPU
S (Error)
• When SM0 is ON, ON if there is error common information
• Conducts error reset operation
See Section 11.3 for further information
• ON if battery voltage at CPU module drops below rated value.
OFF : Normal
• Remains ON if the battery voltage returns to normal thereafter.
ON : Battery low
• Synchronizes with the ERR. LED.
OFF : Normal
• Same as SM51, but goes OFF subsequently when battery voltage
ON : Battery low
returns to normal.
• Turns ON if an instantaneous power failure of within 20ms occurs
during use of the AC power supply module.
OFF : AC/DC DOWN not
• Reset when power is switched OFF, then ON.
detected
ON : AC/DC DOWN
• Turns ON if an instantaneous power failure of within 10ms occurs
detected
during use of the DC power supply module.
• Reset when power is switched OFF, then ON.
OFF : Normal
• ON when operation error is generated
ON : Operation error
• Turns ON if there is at least one output module whose fuse has
OFF : Normal
blown.
ON : Module with blown fuse
• Turns ON if the I/O module differs from the status registered at
OFF : Normal
power on.
ON : Error
OFF : Not detected
• Goes ON if even one annunciator (F) goes ON.
ON : Detected
OFF : Serial communication
function is not used.
• Stores the setting of whether the serial communication function is
ON : Serial communication
used or not in the serial communication setting parameter.
function is used.
OFF : GX Developer
• Stores whether the device that is communicating via the RS-232
ON : MC protocol
interface is GX Developer or MC protocol communication device.
communication device
OFF
Set by
(When Set)
U
App - 2
APPENDICES
MELSEC-Q
(2) System information
Number
Name
Meaning
Explanation
SM203 STOP contact
STOP status
• Goes ON at STOP status
SM204 PAUSE contact
PAUSE status
• Goes ON at PAUSE status
PAUSE enable
coil
Device test
SM206
request
acceptance
status
OFF : PAUSE disabled
ON : PAUSE enabled
• PAUSE status is entered if this relay is ON when the remote
PAUSE contact goes ON
OFF : Device test not yet
executed
ON : Device test executed
• Comes ON when the device test mode is executed on GX
Developer.
SM210
Clock data set
request
SM211 Clock data error
Clock data read
SM213
request
SM240
No. 1 CPU reset
flag
SM241
No. 2 CPU reset
flag
SM242
No. 3 CPU reset
flag
SM244
No. 1 CPU error
flag
SM245
No. 2 CPU error
flag
SM246
No. 3 CPU error
flag
Communication
reserved time
SM315 delay
enable/disable
flag
Presence/
SM320 absence of SFC
program
• When this relay goes from OFF to ON, clock data being stored from
SD210 through SD213 after execution of END instruction for
changed scan is written to the clock device.
OFF : No error
• ON when error is generated in clock data (SD210 through SD213)
ON : Error
value, and OFF if no error is detected.
OFF : Ignored
• When this relay is ON, clock data is read to SD210 through
ON : Read request
SD213 as BCD values.
• Goes OFF when reset of the No. 1 CPU is canceled.
OFF : No. 1 CPU reset cancel • Comes ON when the No. 1 CPU is resetting (including the case
where the CPU is removed from the base).
ON : No. 1 CPU resetting
The other CPUs are also put in reset status.
The other CPUs result in "MULTI CPU DOWN" (error code: 7000).
The other CPUs result in "MULTI CPU DOWN" (error code: 7000).
• Goes OFF when the No. 1 CPU is normal (including a
OFF : No. 1 CPU normal
continuation error).
ON : No. 1 CPU during stop
• Comes ON when the No. 1 CPU is during a stop error.
error
error
error
• This flag is enabled when the time reserved for communication
processing is set in SD315.
• Turns ON to delay the END processing by the time set in SD315
OFF : Without delay
in order to perform communication processing.
ON : With delay
(The scan time increases by the period set in SD315.)
• Turns OFF to perform the END processing without a delay of the
time set in SD315 when there is no communication processing.
(Defaults to OFF)
OFF : Ignored
ON : Set request
OFF: SFC program absence • Turns ON when an SFC program is registered.
ON : SFC program presence • OFF when an SFC program is not registered.
OFF: SFC program nonStart/stop of SFC
execution (stop)
SM321
program
ON : SFC program
execution (start)
SM322
Starting status of OFF: Initial start
SFC program
ON : Continued start
• The same value as in SM320 is set as the initial value.
(Automatically turns ON when the SFC program is present.)
• When this relay is turned from ON to OFF, the execution of the
SFC program is stopped.
• When this relay is turned from OFF to ON, the execution of the
SFC program is resumed.
• The SFC program starting mode in the SFC setting of the PLC
parameter dialog box is set as the initial value.
At initial start: OFF
At continued start: ON
Presence/
absence of
SM323 continuous
transition of all
blocks
OFF: Without continuous
transition
ON : With continuous
transition
Set the presence/absence of continuous transition for the block
where "Continuous transition bit" of the SFC data device has not
been set.
Continuous
SM324 transition inhibit
flag
OFF: When transition is
executed
ON : When transition is not
executed
• OFF during operation in the continuous transition mode or during
continuous transition, and ON when continuous transition is not
executed.
• Always ON during operation in the no continuous transition mode.
App - 3
Set by
(When Set)
Applicable
CPU
S (Status
change)
S (Status
change)
U
S (Request)
U
S (Request)
U
S (Status
change)
Serial No.
04122 or later
U
S (Initial)
S (Initial)
U
S (Initial)
U
Serial No.
04122 or later
U
S (Status
change)
App - 3
APPENDICES
Number
MELSEC-Q
Name
Meaning
Explanation
SM325
Block stop-time
output mode
SM326
SFC device clear OFF: Device cleared
mode
ON : Device held
Output at
SM327 execution of end
step
OFF: OFF
ON : Held
OFF: Held step output OFF
ON : Held step output held
Select whether the coil outputs of the active steps are held or not at
the time of a block stop.
• As the initial value, the output mode at a block stop in the
parameter is OFF when the coil outputs are OFF, and ON when
the coil outputs are held.
• When this relay turns OFF, the coil outputs are all turned OFF.
• When this relay turns ON, the coil outputs are held.
Select the device status at the time of switching from STOP to
program write to RUN.
(All devices except the step relay)
• When this relay turns OFF, the coil outputs of the steps (SC, SE,
ST) being held when transition is established are turned OFF
when the end step is reached.
Select whether clear processing will be performed or not if active
steps other than the ones being held exist in the block when the
end step is reached.
• When this relay turns OFF, all active steps are forcibly terminated
OFF: Clear processing is
Clear processing
to terminate the block.
performed.
SM328 mode when end
ON : Clear processing is not • When this relay is ON, the execution of the block is continued asstep is reached
performed.
is.
• If active steps other than the ones being held do not exist when
the end step is reached, the steps being held are terminated to
terminate the block.
Set by
(When Set)
Applicable
CPU
S (Initial)
U
U
U
Serial No.
04122 or later
U
(3) System clocks/counters
Number
Name
Meaning
Explanation
Set by
(When Set)
SM400 Always ON
ON
OFF
• Normally is ON
S (Every END
processing)
SM401 Always OFF
ON
OFF
• Normally is OFF
S (Every END
processing)
SM402
ON for 1 scan
only after RUN
ON
OFF
1 scan
SM403
After RUN, OFF
for 1 scan only
ON
OFF
1 scan
SM410 0.1 second clock
SM411 0.2 second clock
SM412 1 second clock
SM413 2 second clock
SM414 2n second clock
SM420
SM421
SM422
SM423
SM424
User timing clock
No.0
User timing clock
No.1
User timing clock
No.2
User timing clock
No.3
User timing clock
No.4
App - 4
0.05 sec.
0.05 sec.
0.1sec.
0.1sec.
0.5 sec.
0.5 sec.
1 sec.
1 sec.
n sec.
n sec.
n2
scan
n2
scan
n1
scan
• After RUN, ON for 1 scan only.
• This connection can be used for scan execution type programs
only.
• After RUN, OFF for 1 scan only.
• This connection can be used for scan execution type programs
only.
S (Every END
processing)
S (Every END
processing)
• Repeatedly changes between ON and OFF at each designated
time interval.
• When power supply is turned OFF, or reset is performed, goes
from OFF to start.
Note that the ON-OFF status changes when the
designated time has elapsed during the execution of
the program.
S (Status
change)
• This relay alternates between ON and OFF at intervals of the time
(unit: s) specified in SD414.
• Starts from OFF when the PLC is powered ON or the CPU
module is reset.
• Note that when the specified time is reached, the ON/OFF status
changes even during program execution.
S (Status
change)
• Relay repeats ON/OFF switching at fixed scan intervals.
• When power supply is turned ON, or reset is performed, goes
from OFF to start.
• The ON/OFF intervals are set with the DUTY instruction.
DUTY
Applicable
CPU
S (Every END
processing)
n1 n2 SM420
App - 4
APPENDICES
MELSEC-Q
(4) I/O refresh
Number
Name
Program to
SM580 program I/O
refresh
Meaning
OFF: Not refreshed
ON : Refreshed
Explanation
• When this special relay is turned ON, I/O refresh is performed
after execution of the first program, and the next program is then
executed.
When a sequence program and an SFC program are to be
executed, the sequence program is executed, I/O refresh is
performed, and the SFC program is then executed.
Set by
(When Set)
Corresponding
CPU
U
Serial No.
04122 or later
Set by
(When Set)
Applicable
CPU
(5) Memory cards
Number
Name
Meaning
Explanation
SM620
Drive 3/4 usable
flags
OFF : Unusable
ON : Use enabled
• Always ON
S (Initial)
SM621
Drive 3/4 protect
flag
OFF : No protect
ON : Protect
• Always OFF
S (Initial)
SM622 Drive 3 flag
OFF : No drive 3
ON : Drive 3 present
• Always ON
S (Initial)
SM623 Drive 4 flag
OFF : No drive 4
ON : Drive 4 present
• Always ON
S (Initial)
• Goes ON when file register is in use (Q00CPU, Q01CPU only)
S (Status
change)
• Goes ON while boot operation is in process
S (Status
change)
SM640 File register use
SM660 Boot operation
OFF : File register not in use
ON : File register in use
OFF : Program memory
execution
ON : Boot operation in
progress
(6) Instruction-Related Special Relays
Number
Name
OFF : Carry OFF
ON : Carry ON
OFF : Search next
Search method
ON : 2-part search
OFF : Ascending order
Sort order
ON : Descending order
OFF : Non-match found
Block comparison
ON : All match
0 : During DI
EI flag
1 : During EI
File being
OFF : File not accessed
accessed
ON : File being accessed
OFF : Error detection
BIN/DBIN
performed
instruction error
ON : Error detection not
disabling flag
performed
PID bumpless
processing
OFF: Matched
(for exact
ON : Not matched
differential)
OFF : Performs link refresh
Selection of link ON : No link refresh
performed
refresh
processing during OFF: All refresh processings
COM instruction
are executed.
execution
ON : Refresh set in SD778 is
performed.
PID bumpless
processing
OFF: Matched
(for inexact
ON : Not matched
differential)
SM700 Carry flag
SM702
SM703
SM704
SM715
SM721
SM722
SM774
SM775
SM794
Meaning
App - 5
Explanation
• Carry flag used in application instruction
• Designates method to be used by search instruction.
• Data must be arranged for 2-part search.
• The sort instruction is used to designate whether data should be
sorted in ascending order or in descending order.
• Goes ON when all data conditions have been met for the BKCMP
instruction.
• ON when EI instruction is being executed.
• Switches ON while a file is being accessed by the S.FWRITE,
S.FREAD, COMRD, PRC, or LEDC instruction.
Set by
(When Set)
Applicable
CPU
S (Instruction
execution)
U
U
S (Instruction
execution)
S (Instruction
execution)
S (Status
change)
• Turned ON when "OPERATION ERROR" is suppressed for BIN
or DBIN instruction.
U
• Specify whether the set value (SV) will be matched with the
process value (PV) or not in the manual mode.
U
• Select whether or not to perform link refresh processing in cases
where only general data processing will be conducted during the
execution of the COM instruction.
U
• Select whether all refresh processings or the refresh processing
set in SD778 will be performed when the COM instruction is
executed.
U
Serial No.
04122 or later
• Specify whether the set value (SV) will be matched with the
process value (PV) or not in the manual mode.
U
Serial No.
04122 or later
Serial No.
04122 or later
App - 5
APPENDICES
MELSEC-Q
APPENDIX 2 Special Register List
The special registers, SD, are internal registers with fixed applications in the
programmable controller.
For this reason, it is not possible to use these registers in sequence programs in the
same way that normal registers are used.
However, data can be written as needed in order to control the CPU module.
Data stored in the special registers are stored as BIN values if no special designation
has been made to it.
The headings in the table that follows have the following meanings.
Item
Number
Name
Meaning
Explanation
Set by (When set)
Function of Item
• Indicates special register number
• Indicates name of special register
• Indicates contents of special register
• Discusses contents of special register in more detail
• Indicates whether the relay is set by the system or user, and, if it is set by the system, when
setting is performed.
<Set by>
S
: Set by system
U
: Set by user (sequence program or test operation from GX Developer or the like)
S/U
: Set by both system and user
<When set> Indicated only for registers set by system
Each END
: Set during each END processing
Initial
: Set only during initial processing (when power supply is turned
ON, or when going from STOP to RUN)
Status change
: Set only when there is a change in status
Error
: Set when error occurs
Instruction execution : Set when instruction is executed
Request
: Set only when there is a user request (through SM, etc.)
For details on the following items, see these manuals:
• For Q MELSECNET/H Network System Reference Manual (PLC to PLC
• Networks
network)
App - 6
App - 6
APPENDICES
MELSEC-Q
Special Register List
(1) Diagnostic Information
Number
SD0
Name
Diagnostic
errors
Meaning
Diagnosis error code
Set by
Corresponding
(When set)
CPU
Explanation
• Error codes for errors found by diagnosis are stored as BIN data.
• Contents identical to latest fault history information.
S (Error)
• Year (last two digits) and month that SD0 data was updated is stored as BCD 2digit code.
SD1
b15
to
b8 b7
Year (0 to 99)
SD2
Clock time for Clock time for
diagnosis error diagnosis error
occurrence
occurrence
to
b0
Month (1 to 12)
(Example)
: October, 1995
H9510
• The day and hour that SD0 was updated is stored as BCD 2-digit code.
b15
to
b8 b7
Day (1 to 31)
to
b0
Hour (0 to 23)
(Example)
: 10 p.m. on 25th
H2510
S (Error)
• The minute and second that SD0 data was updated is stored as BCD 2-digit
code.
b15
SD3
to
b8 b7
b0
to
Minutes (0 to 59) Seconds (0 to 59)
(Example)
: 35 min. 48 sec.
(past the hour)
H3548
• Category codes which help indicate what type of information is being stored in
the common information areas (SD5 through SD15) and the individual
information areas (SD16 through SD26) are stored here.
b15
to
b8 b7
Individual information
category codes
SD4
Error
information
categories
Error information
category code
to
b0
Common information
category codes
• The common information category codes store the following codes:
0 : No error
1 : Unit/module No./ PLC No./Base No.
2 : File name/Drive name
3 : Time (value set)
4 : Program error location
S (Error)
• The individual information category codes store the following codes:
0 : No error
1 : (Open)
2 : File name/Drive name
3 : Time (value actually measured)
4 : Program error location
5 : Parameter number
6 : Annunciator number
App - 7
App - 7
APPENDICES
MELSEC-Q
Special Register List (Continued)
Number
Name
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
• Common information corresponding to the error codes (SD0) is stored here.
• The following four types of information are stored here:
1 Slot No.
SD5
Meaning
Slot No./Base No. 1 2
I/O No. 3
Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD6
SD7
(Not used for base No.)
(Vacant)
1: In a multiple CPU system, the slot No. or CPU No. is stored depending
on the error that occurred.
Slot 0 in the multiple CPU system indicates the slot on the right-hand
side of the CPU module at the right end. (Refer to the error code to
check which No. is stored.) No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3
2: When 255 is stored into SD5, it indicates that an instruction, etc. has
been executed for the module later than the one on the last slot where
a module can be mounted.
3: When 0FFFFH is stored in SD6 (I/O No.), the I/O No. may not be
identified due to I/O No. overlapping or like in the I/O assignment
parameter. Use SD5 to identify the error location.
SD8
SD9
2 File name/Drive name
Meaning
Drive
Number
SD10
SD11
Error common
information
Error common
information
SD12
SD5
SD6
SD7
File name
SD8
(ASCII code: 8 characters)
SD9
SD10 Extension 4
2EH(.)
SD11
SD12
SD13
(Vacant)
SD14
SD15
Error common
information
Error common
information
(Example)
File name=
MAIN. QPG
b15 to b8 b7 to b0
41H(A)
4EH(N)
20H(SP)
20H(SP)
51H(Q)
47H(G)
4DH(M)
49H(I)
20H(SP)
20H(SP)
2EH(.)
50H(P)
S (Error)
3 Time (value set)
Meaning
Time : 1 µs units (0 to 999 µs)
Time : 1 ms units (0 to 65535 ms)
Number
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD13
SD14
4
(Vacant)
Program error location
Meaning
SD5
SD6
File name
SD7
SD8
SD9 Extension 4
2EH(.)
SD10
SD11
Pattern 5
SD12
Block No.
SD13
Step No./transition No.
SD14
Sequence step No. (L)
SD15
Sequence step No. (H)
Number
SD15
5: Pattern data
15 14
0 0
to
to
4 3 2 1 0
0 0
(Not used)
(Bit number)
SFC block specified (1)/not specified (0)
SFC step specified (1)/not specified (0)
SFC transition specified (1)/not specified (0)
4: For the extension, refer to REMARKS on the next page.
App - 8
App - 8
APPENDICES
MELSEC-Q
Number
Name
Meaning
• Individual information corresponding to error codes (SD0) is stored here.
1 File name/Drive name
SD16
(Example)
File name=
MAIN. QPG
Meaning
Drive
Number
SD16
SD17
SD18
File name
SD19
SD20
SD21 Extension 4
2EH(.)
SD22
SD23
SD24
(Vacant)
SD25
SD26
SD17
SD18
SD19
b15 to b8 b7 to b0
41H(A)
4EH(N)
20H(SP)
20H(SP)
51H(Q)
47H(G)
4DH(M)
49H(I)
20H(SP)
20H(SP)
2EH(.)
50H(P)
2 Time (value actu1ally measured)
Number
Meaning
SD16
Time : 1 µs units (0 to 999 µs)
SD17
Time : 1 ms units (0 to 65535 ms)
SD18
SD19
SD20
SD21
(Vacant)
SD22
SD23
SD24
SD25
SD26
SD20
SD21
SD22
SD23
Set by
Corresponding
(When set)
CPU
Explanation
3 Program error location
Number
Meaning
SD16
SD17
File name
SD18
SD19
SD20 Extension 4
2EH(.)
SD21
SD22
Pattern 5
SD23
Block No.
SD24
Step No./transition No.
SD25
Sequence step No. (L)
Sequence step No. (H)
SD26
Error individual Error individual
information
information
SD24
S (Error)
5: Pattern data
15 14
0 0
SD25
to
to
4 3 2 1 0
0 0
(Not used)
4
Parameter number
5
(Bit number)
SFC block specified (1)/not specified (0)
SFC step specified (1)/not specified (0)
SFC transition specified (1)/not specified (0)
6 Intelligent function
Annunciator number
module parameter error
Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26
SD26
Meaning
Parameter No. 6
(Vacant)
Number
SD16
SD17
SD18
SD19
SD20
SD21
SD22
SD23
SD24
SD25
SD26
Meaning
No.
Meaning
SD16
Parameter No. 6
SD17 Error code for intelligent
function module
SD18
SD19
SD20
SD21
SD22
(Vacant)
SD23
SD24
SD25
SD26
Number
(Vacant)
6 For details of the parameter numbers, refer to the user's
manual (Functions Exlanation, Proguramming fundamentals) of the
CPU module used.
REMARK
4 Extensions are shown below.
SD10
Higher8 bits
51H
51H
51H
51H
App - 9
SD11
Lower8 bits
50H
50H
43H
44H
Higher8 bits
41H
47H
44H
52H
Extension name
QPA
QPG
QCD
QDR
File type
Parameters
Sequence program/SFC program
Device comment
File register
App - 9
APPENDICES
MELSEC-Q
Number
SD50
SD51
Name
Error reset
Battery low
latch
Meaning
Error number that
performs error reset
Bit pattern indicating
where battery
voltage drop
occurred
Bit pattern indicating
where battery
voltage drop
occurred
SD63
S (Error)
CPU error
S (Error)
Number of module
with blown fuse
I/O module
verification error
module number
• Value stored here is the lowest station I/O number of the module with the blown
fuse.
S (Error)
• The lowest I/O number of the module (F number) where the I/O module
verification number took place.
S (Error)
Annunciator number
• The first annunciator number to be detected is stored here.
Number of
annunciators
• Stores the number of annunciators searched.
AC/DC DOWN Number of times for
detection
AC/DC DOWN
SD62
b15
to
b0
0<------------------------------------------------- >
• Every time the input voltage falls to or below 85% (AC power)/65% (DC power)
of the rating during calculation of the CPU module, the value is incremented by
one and stored in BIN.
SD53
SD61
U
• When battery low occurs, the corresponding bit turns to 1 (ON).
• Remains 1 if the battery voltage returns to normal thereafter.
S (Error)
Battery low
Blown fuse
number
I/O module
verification
error number
Annunciator
number
Number of
annunciators
• Stores error number that performs error reset
• Same configuration as SD51 above
• Turns to 0 (OFF) when the battery voltage returns to normal thereafter.
SD52
SD60
Set by
Corresponding
(When set)
CPU
Explanation
SD64
When F goes ON due to OUT F or SET F , the F numbers which go
SD65
progressively ON from SD64 through SD79 are registered.
The F numbers turned OFF by RST F are deleted from SD64 - SD79, and the F
numbers stored after the deleted F numbers are shifted to the preceding
registers.
After 16 annunciators have been detected, detection of the 17th will not be stored
from SD64 through SD79.
SD66
SD67
SD68
SET SET SET RST SET SET SET SET SET SET SET RST
F50 F25 F99 F25 F15 F70 F65 F38 F110 F151 F210F50
SD69
SD70
SD71
SD72
Table of
detected
annunciator
numbers
SD73
SD74
SD75
SD76
SD77
SD78
Annunciator
detection number
SD62
0
50
50
50
50
50
50
50
50
50
50
50
SD63
0
1
2
3
2
3
4
5
6
7
8
9
SD64
0
50
50
50
50
50
50
50
50
50
50
50
99 ...(Number
detected)
8 ...(Number of
annunciators
detected)
99
SD65
0
0
25
25
99
99
99
99
99
99
99
99
15
SD66
0
0
0
99
0
15
15
15
15
15
15
15
70
SD67
0
0
0
0
0
0
70
70
70
70
70
70
65
SD68
0
0
0
0
0
0
0
65
65
65
65
65
38
SD69
0
0
0
0
0
0
0
0
38
38
38
38 110
SD70
0
0
0
0
0
0
0
0
0
SD71
0
0
0
0
0
0
0
0
0
0
SD72
0
0
0
0
0
0
0
0
0
0
0
210
0
SD73
0
0
0
0
0
0
0
0
0
0
0
0
0
SD74
0
0
0
0
0
0
0
0
0
0
0
0
0
SD75
0
0
0
0
0
0
0
0
0
0
0
0
0
SD76
0
0
0
0
0
0
0
0
0
0
0
0
0
SD77
0
0
0
0
0
0
0
0
0
0
0
0
0
SD78
0
0
0
0
0
0
0
0
0
0
0
0
0
SD79
0
0
0
0
0
0
0
0
0
0
0
0
0
S
(Instruction
execution)
110 110 110 151
151 151 210
(Number
detected)
SD79
App - 10
App - 10
APPENDICES
MELSEC-Q
Number
Name
Transmission
SD100 speed storage
area
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
Stores the
transmission speed
K96: 9.6kbps, K192: 19.2kbps, K384: 38.4kbps,
specified in the serial
K576: 57.6kbps, K1152: 115.2kbps
communication
setting.
b15
Stores the
communication
Communicatio
setting specified in
SD101 n setting
the serial
storage area
communication
setting.
to
b6 b5 b4 b3
S (Poweron or reset)
to
b0
Sumcheck yes/no
Online program correction setting
0: No
0: Disabled
1: Yes
1: Enabled
: Since the data is used by the system, it is undefined.
Message
SD102 waiting time
storage area
Stores the message
waiting time specified 0: No waiting time
in the serial
1 to FH: Waiting time (unit: 10ms)
communication
Defaults to 0.
setting.
Data sending
SD110 result storage
area
Stores the data
sending result when
the serial
communication
function is used.
The error code at data transmission is stored.
Stores the data
Data receiving receiving result when
SD111 result storage the serial
Stores the error code at the time of data receiving.
area
communication
function is used.
SD130
SD131
SD132
SD133
Fuse blown
module
SD134
SD135
SD136
SD137
SD150
SD151
SD152
I/O module
SD153 verification
error
SD154
SD155
SD156
SD157
App - 11
• The numbers of output modules whose fuses have blown are input as a bit
pattern (in units of 16 points).
(If the module numbers are set by parameter, the parameter-set numbers are
stored.)
Bit pattern in units of
• Also detects blown fuse condition at remote station output modules
16 points, indicating
the modules whose
1
1
SD130 0 0 0 (YC0) 0 0 0 (Y80) 0 0 0 0 0 0 0 0
fuses have blown
1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0: No blown fuse
(Y1A0)
SD131 (Y1F0)
1: Blown fuse
1
1
0 0 0 0 0 0 0 (Y1F 0 0 0
SD137 0 0 0 0 (Y1F
present
B0)
30)
S (Error)
S (Error)
S (Error)
Indicates a blown fuse
• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation
• When the power is turned on, the module numbers of the I/O modules whose
information differs from the registered I/O module information are set in this
register (in units of 16 points).
(If the I/O numbers are set by parameter, the parameter-set numbers are
Bit pattern, in units of
stored.)
16 points, indicating
• Also detects I/O module information
the modules with
1
verification errors.
SD150 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (X Y)
0
0: No I/O verification
1
SD151 0 0 0 0 0 0 (X Y) 0 0 0 0 0 0 0 0 0
errors
190
1: I/O verification
1
SD157 0 X Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0
error present
(1FE0)
S (Error)
Indicates an I/O module verification error
• Not cleared even if the blown fuse is replaced with a new one.
This flag is cleared by error resetting operation
App - 11
APPENDICES
MELSEC-Q
(2) System information
Special Register List
Number
Name
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
• The CPU module switch status is stored in the following format:
b15
SD200
Status of
switch
to
b8 b7
to
Vacant
Status of CPU switch
b4 b3
2
1 : CPU switch status
0: RUN
1: STOP
2 : Memory card switch
Always OFF
to
b0
S(Every
END
processing)
1
• The following bit patterns are used to store the statuses of the LEDs on the
CPU module:
b15
SD201 LED status
b4 b3
to
b0
to
Status of CPU-LED
Vacant
2
1
S (Status
change)
1 : RUN
2 : ERR.
• The CPU module operating status is stored as indicated in the following figure:
b15 to b12b11 to b8 b7
to
2
1 : Operating status of CPU
SD203
Operating
status of CPU
Operating status of
CPU
2 : STOP/PAUSE cause
Note: Priority is earliest first
SD207
Priorities 1 to 4
SD208
Priorities 5 to 8
LED display
priority
SD209
Priorities 9 to 10
b4 b3
to
b0
1
0 :RUN
1 :Vacant
2 :STOP
3 :PAUSE
0 :RUN/STOP/RESET switch
1 :Remote contact
2 :GX Developer/Serial Communication
Module from some other remote source
3 :Internal program instruction
S (Every
END
processing)
4 :Errors
• Set the ON (flicker) priorities of the LED display section at error occurrence with
error item Nos.
• Applicable to only the annunciator (error item No. 7). The priority setting area is
as shown below.
b15 to b12b11 to b8 b7 to b4 b3 to b0
SD207 Priority 4 Priority 3 Priority 2 Priority 1
SD208 Priority 8 Priority 7 Priority 6 Priority 5
Priority 10 Priority 9
SD209
Default Value SD207 = 0000H
SD208 = 0700H
SD209 = 0000H
U
Serial number
04122 or later
• With "7" set to any of priorities 1 to 10, the ERR. LED turns ON when the
annunciator turns ON.
• Without "7" being set to any of priorities 1 to 10, the ERR. LED will not turn ON
if the annunciator turns ON.
App - 12
App - 12
APPENDICES
MELSEC-Q
Number
Name
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
• The year (last two digits) and month are stored as BCD code at SD210 as
shown below:
SD210 Clock data
b15
Clock data (year,
month)
to
b12 b11
to
b8 b7
to
Year
b4 b3
to
b0
Example :
July 1993
9307H
Month
• The day and hour are stored as BCD code at SD211 as shown below:
b15
SD211 Clock data
to
to
b12 b11
b8 b7
to
b4 b3
to
Example :
31st, 10 a.m.
3110H
b0
Clock data (day,
hour)
Day
S/U
(Request)
Hour
• The minutes and seconds (after the hour) are stored as BCD code at SD212 as
shown below:
SD212 Clock data
Clock data (minute,
second)
b15
to
b12 b11
to
b8 b7
to
Minute
b4 b3
to
b0
Example :
35 min., 48 sec.
3548H
Second
• Stores the year (two digits) and the day of the week in SD213 in the BCD code
format as shown below:
b15
SD213 Clock data
Clock data
(day of week)
b12 b11
to
b8 b7
to
b4 b3
to
b0
Example :
1993,Friday
1905H
S/U
(Request)
Day of week
Sunday
0
Higher digits
of year (0 to 99)
1
Monday
2
Tuesday
3
Wednesday
4
Thursday
5
Friday
6
Saturday
• Stores the message (16 characters of ASCII data) at error occurrence (including
annunciator ON).
SD220
SD221
b15
SD222
to
b8
b7
to
b0
SD220 15th character from the right 16th character from the right
SD223
LED display
SD224
data
SD225
to
Display indicator
data
SD226
SD227
SD223
9th character from the right 10th character from the right
SD224
7th character from the right
SD225
SD226
3rd character from the right
SD227
1st character from the right 2nd character from the right
S (When
changed)
• The display device data at PRG CHK is not stored.
SD240 Base mode
0: Automatic mode
1: Detail mode
• Stores the base mode.
S (Initial)
No. of
SD241 expansion
bases
0: Basic only
1 to 4: No. of
expansion
bases
• Stores the maximum number of the expansion bases being installed.
S (Initial)
b4
Fixed to 0
b2 b1 b0
to
Base type
differentiation
Installed Q
SD242 base presence/ 0: Base not installed
1: Q
absence
B is
installed
Main base
1st expansion
base
2nd expansion
base
S (Initial)
to
4th expansion
base
SD243 No. of base
slots
(Operation
SD244 status)
App - 13
b15 to b12 b11 to b8 b7 to b4 b3 to b0
Main
SD243 Expansion 3 Expansion 2 Expansion 1
No. of base slots
SD244
Fixed to 0
Expansion 4
S (Initial)
• As shown above, each area stores the number of slots being installed.
(Number of set slots when parameter setting has been made)
App - 13
APPENDICES
MELSEC-Q
Number
Name
Meaning
SD245
No. of base
slots (Mounting No. of base slots
SD246 status)
SD250
Loaded
maximum I/O
SD254
SD246
Fixed to 0
Expansion 4
Number of modules
installed
• Indicates the number of modules installed on MELSECNET/H.
Station
No.
SD258
• Stores the number of points currently set for X devices
SD291
Number of points
allocated for Y
• Stores the number of points currently set for Y devices
SD292
Number of points
allocated for M
• Stores the number of points currently set for M devices
Number of points
allocated for L
• Stores the number of points currently set for L devices
Number of points
allocated for B
• Stores the number of points currently set for B devices
Number of points
allocated for F
• Stores the number of points currently set for F devices
SD296
Number of points
allocated for SB
• Stores the number of points currently set for SB devices
SD297
Number of points
allocated for V
• Stores the number of points currently set for V devices
SD298
Number of points
allocated for S
• Stores the number of points currently set for S devices
Number of points
allocated for T
• Stores the number of points currently set for T device
Number of points
allocated for ST
• Stores the number of points currently set for ST devices
Number of points
allocated for C
• Stores the number of points currently set for C devices
Number of points
allocated for D
• Stores the number of points currently set for D devices
Number of points
allocated for W
• Stores the number of points currently set for W devices
Number of points
allocated for SW
• Stores the number of points currently set for SW devices
SD302 Device
allocation
SD303 (Same as
parameter
SD304 contents)
SD315
Time reserved
Time reserved for
for
communication
communication
processing
processing
SD340
SD341 Ethernet
SD342 information
• Reserves the designated time for communication processing with GX Developer
or other units.
• The greater the value is designated, the shorter the response time for
communication with other devices (GX Developer, serial communication units)
becomes.
• Setting range: 1 to 100 ms
• If the designated value is out of the range above, it is assumed to no setting.
The scan time becomes longer by the designated time.
No. of modules
installed
• Indicates the number of modules installed on Ethernet.
I/O No.
• Indicates the I/O number of the installed Ethernet module.
Network No.
• Indicates the network No. of the installed Ethernet module.
SD343
Group No.
• Indicates the group No. of the installed Ethernet module.
SD344
Station No.
• Indicates the station No. of the installed Ethernet module.
App - 14
S (Initial)
• MELSECNET/H station number of first module installed
Number of points
allocated for X
SD299 Device
allocation
SD300 (Same as
parameter
SD301 contents)
S (Initial)
• MELSECNET/H group number of first module installed
SD290
SD293 Device
allocation
SD294 (Same as
parameter
SD295 contents)
Serial number
04122 or later
• MELSECNET/H I/O number of first module installed
Network
• MELSECNET/H network number of first module installed
No.
Information from
Group
1st module number
S (Initial)
• As shown above, each area stores the number of module-mounted slots of the
base unit (actual number of slots of the installed base unit).
• When SM250 goes from OFF to ON, the upper 2 digits of the final I/O number
plus 1 of the modules loaded are stored as BIN values.
I/O No.
SD257
Main
SD245 Expansion 3 Expansion 2 Expansion 1
Loaded maximum
I/O No.
SD255
SD256 MELSECNET/
H information
Set by
Corresponding
(When set)
CPU
Explanation
S (Initial)
S (Initial)
S (Initial)
END
processing
S (Initial)
App - 14
APPENDICES
MELSEC-Q
Number
Name
Meaning
Number of multiple
PLCs
SD393
Set by
Corresponding
(When set)
CPU
Explanation
• The number of CPU modules that comprise the multiple PLC system is stored.
(1 to 3, Empty also included)
• The CPU module types of No. 1 CPU to 3 and whether the CPU modules are
mounted or not are stored.
SD394 Empty (0) PLC No. 3 PLC No. 2 PLC No. 1
CPU mounting
information
SD394
Multiple PLC
system
SD395 information
S (Initial)
CPU module mounted
or not mounted
0: Not mounted
1: Mounted
Multiple PLC No.
CPU module type
0: PLC CPU
1: Motion CPU
2: PC CPU
SD396
No. 1 CPU operation • The operation information of each PLC No. is stored.
(The information on the number of multiple PLCs indicated in SD393 is stored.)
status
SD397
No. 2 CPU operation
status
b15 b14
to
Empty
b8 b7
to
b4 b3
to
b0
Classification Operation status
Mounted or not
mounted
0: Not mounted
1: Mounted
No. 3 CPU operation
status
SD398
Serial number
04122 or later
• In a multiple PLC configuration, the PLC No. of the host PLC is stored.
No. 1 CPU: 1, No. 2 CPU: 2, No. 3 CPU: 3
0: Normal
1: Minor fault
2: Medium fault
3: Major fault
FH: Reset
0: RUN
1: STEP RUN
2: STOP
3: PAUSE
4: Initial
FH: Reset
S (When
END
processing
error
occurs)
(3) System clocks/counters
Number
Name
Meaning
Explanation
SD412
1 second
counter
Number of counts in
1-second units
• Following programmable controller CPU module RUN, 1 is added each second
• Count repeats from 0 to 32767 to -32768 to 0
SD414
2n second
clock setting
2n second clock
units
• Stores value n of 2n second clock (Default is 30)
• Setting can be made between 1 and 32767
Number of counts in
each scan
• Incremented by 1 for each scan execution after the CPU module is set to
RUN.
• Count repeats from 0 to 32767 to -32768 to 0
SD420 Scan counter
Set by
Corresponding
(When set)
CPU
S (Status
change)
U
S(Every
END
processing)
(4) Scan information
Number
Name
Meaning
Explanation
Set by
Corresponding
(When set)
CPU
Current scan time
(in 1 ms units)
• Stores current scan time (in 1 ms units)
Range from 0 to 65535
S (Every
END
processing)
SD521
Current scan time
(in 100 µs units)
• Stores current scan time (in 100 µs units)
Range from 00000 to 900
(Example)
A current scan of 23.6 ms would be stored as follows:
D520=23
D521=600
S (Every
END
processing)
SD524
Minimum scan time
(in 1 ms units)
• Stores minimum value of scan time (in 1 ms units)
• Range from 0 to 65535
S (Every
END
processing)
Minimum scan time
(in 100 µs units)
• Stores minimum value of scan time (in 100 µs units)
• Range of 000 to 900
S (Every
END
processing)
SD520
Current scan
time
Minimum scan
time
SD525
Maximum scan time
Maximum scan (in 1 ms units)
time
Maximum scan time
SD527
(in 100 µs units)
SD526
App - 15
• Stores maximum value of scan time, excepting the first scan. (in 1 ms units)
• Stores maximum value of scan time, excepting the first scan. (in 100 µs units)
S (Every
END
processing)
App - 15
APPENDICES
MELSEC-Q
Number
Name
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
END processing time
(in 1 ms units)
• Stores time from completion of scan program to start of next scan. (in 1 ms
units)
END processing time
(in 100 µs units)
• Stores time from completion of scan program to start of next scan. (in 100 µs
units)
Constant scan wait
time (in 1 ms units)
• Stores wait time when constant scan time has been set.
(in 1 ms units)
SD543
Constant scan wait
time (in 100 µs units)
• Stores wait time when constant scan time has been set.
(in 100 µs units)
SD548
Scan program
execution time
(in 1 ms units)
• Stores execution time for scan execution type program during 1 scan (in 1 ms
units)
• Stores each scan
Scan program
execution time
(in 100 µs units)
• Stores execution time for scan execution type program during 1 scan (in 100 µs
units)
• Stores each scan
SD540
SD541
END
processing
time
SD542
Constant scan
wait time
Scan program
execution time
SD549
S (Every
END
processing)
S (First
END
processing)
S (Every
END
processing)
(5) Drive information
Number
Name
Meaning
Set by
Corresponding
(When set)
CPU
Explanation
• Indicates the drive 3/4 models.
b15
to
b8 b7
to
b4 b3
to
b0
0
SD620
Drive 3/4
models
Drive 3
Drive 3/4 models
0: Absent
S (Initial)
(Standard RAM) 1: Present
Drive 4
Fixed at "3".
(Standrd ROM)
Drive 4 is fixed to "3" because it has built-in Flash ROM.
Drive 3
SD622 (Standard
Drive 3 capacity
RAM) capacity
• Drive 3 capacity is stored in 1kbyte units.
(Fixed to "61" because it has 61kbyte RAM built-in.)
S (Initial)
Drive 4
SD623 (Standard
Drive 4 capacity
ROM) capacity
• Drive 4 capacity is stored in 1kbyte units.
S (Initial)
• Drive 3 use conditions are stored in bit pattern.
Drive 3 use
SD624
conditions
SD640
File register
drive
Drive 3 use
conditions
Drive number:
SD641
to
b0
b15
to
b4
0
0
0 0 0 0 0
S (Status
change)
File register (R)
1: In use
0: Not used
S (Status
change) 1
• Stores drive number being used by file register
• Stores file register file name (with extension) selected at parameters as ASCII
code.
SD642
b15
SD643 File register file File register file
name
SD644 name
SD645
to
b8 b7
Second character (A)
SD641
SD642
Fourth character (N)
Sixth character ( )
SD643
SD644
Eighth character ( )
SD645 First character of extension (Q)
SD646 Third character of extension (R)
to
b0
First character (M)
Third character (I)
Fifth character ( )
Seventh character ( )
2EH(.)
Second character of extension (D)
S (Initial)
SD646
SD647
File register
capacity
File register capacity • Stores the data capacity of the currently selected file register in 1 k word units.
SD648
File register
block number
File register block
number
• Stores the currently selected file register block number.
S (Initial)
S (Status
change) 1
1: The data is set when the CPU is stopped and then RUN or the RSET instruction is executed after parameter execution.
App - 16
App - 16
APPENDICES
MELSEC-Q
(6) Instruction-Related Registers
Number
Name
Meaning
• Patterns masked by use of the IMASK instruction are stored in the following
manner:
SD715
IMASK
SD716 instruction
mask pattern
Mask pattern
SD717
SD718
SD719
Accumulator
Set by
Corresponding
(When set)
CPU
Explanation
Accumulator
PID limit
setting
SD774
(for exact
differential)
0: With limit
1: Without limit
Refresh
processing
selection at
SD778
COM
instruction
execution
b0 to b4
(Default: 0)
0: Refresh not
executed
1: Refresh executed
b15
0: General data
processing
executed
1: General data
processing not
executed
b15
SD715 l15
to
to
b1 b0
l1 l0
SD716 l31
to
l17 l16
SD717 l47
to
l33 l32
S (During
execution)
• For use as replacement for accumulators used in A-series programs.
S/U
Specify the limit of each PID loop as shown below.
b15
b8
to
SD774
b7
to
b1
b0
U
Loop 8 to Loop 2 Loop 1
• Select whether each refresh processing will be executed or not when the COM
instruction is executed.
• Designation of SD778 is made valid when SM775 turns ON.
b15 b14
SD778 1/0
to
0
b5 b4 b3 b2 b1 b0
1/0 1/0 1/0 1/0 1/0
I/O refresh
CC-Link refresh
MELSECNET/H refresh
Automatic refresh of intelligent
function modules
Serial number
04122 or later
U
Automatic refresh of CPU shared
memory
Execution/non-execution of
general data processing
• Stores the mask patterns masked by the IMASK instruction as follows:
SD781 Mask pattern
TO
of IMASK
SD785 instruction
Mask pattern
b15
to
b1 b0
SD781 l63
to
l49 l48
SD782 l79
to
to
SD785 l127
PID limit
setting
SD794
(for inexact
differential)
App - 17
S (During
execution)
l65 l64
to
to
l113 l112
Specify the limit of each PID loop as shown below.z
0: With limit
1: Without limit
b15
SD794
to
b8
b7
to
b1
b0
Loop 8 to Loop 2 Loop 1
U
Serial number
04122 or later
App - 17
APPENDICES
MELSEC-Q
APPENDIX 3 List of Interrupt Pointer Nos. and Interrupt Factors
I No.
Priority
Ranking
Interrupt Factors
I0
1st point
5
I1
2nd point
6
I2
3rd point
7
I3
4th point
8
I4
5th point
9
I5
6th point
10
I6
7th point
11
I7
8th point
12
9th point
13
I8
QI60 interrupt module factor
I9
10th point
14
I10
11th point
15
I11
12th point
16
I12
13th point
17
I13
14th point
18
I14
15th point
19
I15
16th point
——
20
——
I28
100ms
4
I29
40ms
3
I16 to I27
I30
Unusable
Internal timer factor 1
I31
I32 to I49
I50 to I127 2
Unusable
20ms
2
10ms
——
1
——
Interrupt by intelligent function Set in the parameter which intelligent module
module/QI60
function/interrupt module (QI60) will be used.
21 to 98
REMARK
1 : The internal times shown are the default setting times.
These times can be designated in 1 ms units through a 2 ms to 1000 ms range
by the PLC system settings in the PLC parameter setting.
2 : Intelligent function module setting (interrupt pointer setting) must be made in
the PLC system setting of the PLC parameter dialog box. (Refer to Section
8.2.1 for the interruption from the intelligent function module.)
App - 18
App - 18
APPENDICES
MELSEC-Q
APPENDIX 4 Enhancement of the Basic Model QCPU Functions
The Basic model QCPU has been updated to add functions and change the
specifications.
The functions and specifications that can be used with the Basic model QCPU change
depending on the function version.
Appendix 4.1 Specification Comparison
Function Version of CPU Module
Specifications
Standard RAM capacity
Function Version A
Function Version B
Q00CPU
64k bytes
128k bytes
Q01CPU
64k bytes
128k bytes
Q00JCPU
Shared memory
: Usable/compatible,
: Unusable/incompatible
Appendix 4.2 Added Functions
Function Version of CPU Module
Added Function
Function Version B
SFC(MELSAP3)
Function block
Structured text (ST)
PID operation function
Real number operation
Intelligent function module event
interruption
Remote password setting function
E-mail parameter
Write during RUN using pointer
Increased file register R capacity (32k
points to 64k points)
Multiple CPU System compatibility
Compatibility of Multiple CPU System with
PC CPU module
App - 19
App - 19
APPENDICES
MELSEC-Q
MEMO
App - 20
App - 20
INDEX
[A]
Ind
[G]
Accuracy of scan time ................................. 4-9
Annunciator (F) ........................................ 10-12
ASCII code................................................. 4-25
Auto mode .................................................. 5- 3
GX Configurator ..............................................8- 2
GX Developer ............................................... A-17
[H]
H (Hexadecimal constants) .........................10-50
HEX (Hexadecimal) .......................................4-23
Hexadecimal constants (H) .........................10-50
High-speed retentive timer (ST) ..................10-21
High-speed timer (T)....................................10-20
[B]
Base mode.................................................. 5- 4
BCD (Binary coded decimal)..................... 4-24
BIN (Binary code) ...................................... 4-22
Boot Run ..................................................... 6- 6
[C]
C (Counter).................................................. 10-24
Character string............................................. 4-25
Clock function ................................................. 7- 9
Precision .................................................... 7-11
Concept of I/O assignment ............................ 5- 8
Constant scan ................................................ 7- 2
Constants .................................................... 10-50
Counter (C).................................................. 10-24
Count processing..................................... 10-24
Maximum counting speed ....................... 10-25
[D]
D (Data register).......................................... 10-28
Data register (D).......................................... 10-28
Decimal constants (K) ................................. 10-50
Device list ..................................................... 10- 1
Direct access input(DX) ............................... 10- 6
Direct access output(DY) ............................. 10- 9
Direct mode ................................................... 4-18
Drive Number. ................................................ 6- 3
Duty.............................................................. 10-25
[E]
Edge relay(V)............................................... 10-16
END processing ............................................ 4-11
[F]
F (Anunciator).............................................. 10-12
FD (Function register) ................................. 10-31
File register .................................................. 10-42
File size.......................................................... 6-13
Function device (FX, FY, FD) ..................... 10-31
FX (Function input)...................................... 10-31
FY (Function output) ................................... 10-31
Index - 1
[I]
I (Interrupt pointer) .......................................10-46
I/O No. designation device (Un) ..................10-48
Index register (Z)..........................................10-39
Input response time .......................................7-21
Intelligent function module device (U \G )..10-38
Internal relay (M)..........................................10-10
Internal system device .................................10-31
Internal user device ......................................10- 3
Interrupt pointer (I) .......................................10-46
Interrupt program ............................................4- 5
[J]
J (Network designation device) ...................10-48
J \B (Link relay) ...................................10-35
J \SB (Link special relay) ....................10-35
J \SW
(Link special register)...............10-35
J \W (Link register)..............................10-35
J \X (Link input) ...................................10-35
J \Y (Link output).................................10-35
[K]
K (Decimal constants)..................................10-50
[L]
L (Latch relay) ..............................................10-11
Latch function..................................................7- 5
Latch relay (L) ..............................................10-11
LED display ....................................................7-39
Link direct device .........................................10-35
Link register (W)...........................................10-29
Link relay (B) ................................................10-17
List of Interrupt factors .................................10-47
App-10
Low-speed retentive timer (ST) ...................10-21
Index - 1
Low-speed timer (T) ................................ 10-19
[M]
Ind
M (Internal relay) ......................................... 10-10
Macro instruction argument device (VD) .... 10-49
Main routine program .................................... 4- 3
[N]
N (Nesting) .................................................. 10-44
[O]
Output (Y) .................................................... 10- 8
[P]
P (Pointer).................................................... 10-45
Password....................................................... 7-35
Pointer (P).................................................... 10-45
Precautions when using timers................... 10-23
Processing at annunciator OFF.................. 10-14
Processing at annunciator ON.................... 10-12
Program memory ........................................... 6- 4
Purpose of I/O assignment ........................... 5-12
Purpose of I/O assignment using
[Q]
QI60 ............................................................... 7-23
[R]
R (File register)............................................ 10-42
Reading from the time data............................ 7- 9
Refresh input ................................................ 10- 6
Refresh mode................................................ 4-15
Refresh output.............................................. 10- 9
Remote latch clear ........................................ 7-19
Remote operation.......................................... 7-12
Remote PAUSE............................................. 7-15
Remote RESET............................................. 7-17
Remote RUN/STOP...................................... 7-12
Remote station I/O number........................... 5-11
Retentive timer (OUT ST )....................... 10-21
RUN status .................................................... 4-12
[S]
S (Step relay)............................................... 10-18
SB (Special link relay) ................................. 10-18
Scan time........................................................ 4- 9
SD (Special register) ................................... 10-34
SD520, SD521 (Scan time: present value) ... 4- 9
SD524, SD525 (Scan time: Maximum value).......4- 9
SD526, SD527 (Scan time: Minimum value)........4- 9
Index - 2
Self-diagnosis function...................................7-30
Sequence program ........................................4- 1
Setting range in the internal user device.....10- 3
Setting the number of stages ........................5- 2
Special link register (SW) ............................10-30
Special link relay (SB)..................................10-18
Special register (SD)....................................10-34
Special relay (SM)........................................10-33
ST (Retentive timer: OUT ST ) ................10-21
Standard RAM ................................................6- 9
Standard RAM capacity........................................
Standard ROM ................................................6- 5
Step relay (S) ...............................................10-18
Sub-routine program......................................4- 4
SW (Special link register) ............................10-30
Switch setting of intelligent function module .7-24
System protect ...............................................7-35
[T]
T (Timer).......................................................10-19
Accuracy...................................................10-22
Processing................................................10-22
[U]
U (I/O No. designation device) ....................10-48
U \G (Intelligent function module device)...10-38
User memory ..................................................6- 2
[V]
V (Edge relay) ..............................................10-16
VD (Macro instruction argument device).....10-49
[W]
W (Link register)...........................................10-29
WDT (Watchdog timer)..................................7-28
Write during RUN...........................................7-25
Writing to the time data .................................7- 9
[X]
X (Input)........................................................10- 5
[Y]
Y (Output).....................................................10- 8
[Z]
Z (Index register)..........................................10-39
ZR (Serial number access format of file register)
......................................................................10-39
Index - 2
WARRANTY
Please confirm the following product warranty details before starting use.
1. Gratis Warranty Term and Gratis Warranty Range
If any faults or defects (hereinafter "Failure") found to be the responsibility of Mitsubishi occurs during use of the product
within the gratis warranty term, the product shall be repaired at no cost via the dealer or Mitsubishi Service Company.
Note that if repairs are required at a site overseas, on a detached island or remote place, expenses to dispatch an
engineer shall be charged for.
[Gratis Warranty Term]
The gratis warranty term of the product shall be for one year after the date of purchase or delivery to a designated
place.
Note that after manufacture and shipment from Mitsubishi, the maximum distribution period shall be six (6) months, and
the longest gratis warranty term after manufacturing shall be eighteen (18) months. The gratis warranty term of repair
parts shall not exceed the gratis warranty term before repairs.
[Gratis Warranty Range]
(1) The range shall be limited to normal use within the usage state, usage methods and usage environment, etc.,
which follow the conditions and precautions, etc., given in the instruction manual, user's manual and caution labels
on the product.
(2) Even within the gratis warranty term, repairs shall be charged for in the following cases.
1. Failure occurring from inappropriate storage or handling, carelessness or negligence by the user. Failure caused
by the user's hardware or software design.
2. Failure caused by unapproved modifications, etc., to the product by the user.
3. When the Mitsubishi product is assembled into a user's device, Failure that could have been avoided if functions
or structures, judged as necessary in the legal safety measures the user's device is subject to or as necessary
by industry standards, had been provided.
4. Failure that could have been avoided if consumable parts (battery, backlight, fuse, etc.) designated in the
instruction manual had been correctly serviced or replaced.
5. Failure caused by external irresistible forces such as fires or abnormal voltages, and Failure caused by force
majeure such as earthquakes, lightning, wind and water damage.
6. Failure caused by reasons unpredictable by scientific technology standards at time of shipment from Mitsubishi.
7. Any other failure found not to be the responsibility of Mitsubishi or the user.
2. Onerous repair term after discontinuation of production
(1) Mitsubishi shall accept onerous product repairs for seven (7) years after production of the product is discontinued.
Discontinuation of production shall be notified with Mitsubishi Technical Bulletins, etc.
(2) Product supply (including repair parts) is not possible after production is discontinued.
3. Overseas service
Overseas, repairs shall be accepted by Mitsubishi's local overseas FA Center. Note that the repair conditions at each FA
Center may differ.
4. Exclusion of chance loss and secondary loss from warranty liability
Regardless of the gratis warranty term, Mitsubishi shall not be liable for compensation to damages caused by any cause
found not to be the responsibility of Mitsubishi, chance losses, lost profits incurred to the user by Failures of Mitsubishi
products, damages and secondary damages caused from special reasons regardless of Mitsubishi's expectations,
compensation for accidents, and compensation for damages to products other than Mitsubishi products and other duties.
5. Changes in product specifications
The specifications given in the catalogs, manuals or technical documents are subject to change without prior notice.
6. Product application
(1) In using the Mitsubishi MELSEC programmable logic controller, the usage conditions shall be that the application will
not lead to a major accident even if any problem or fault should occur in the programmable logic controller device, and
that backup and fail-safe functions are systematically provided outside of the device for any problem or fault.
(2) The Mitsubishi general-purpose programmable logic controller has been designed and manufactured for applications
in general industries, etc. Thus, applications in which the public could be affected such as in nuclear power plants and
other power plants operated by respective power companies, and applications in which a special quality assurance
system is required, such as for Railway companies or National Defense purposes shall be excluded from the
programmable logic controller applications.
Note that even with these applications, if the user approves that the application is to be limited and a special quality is
not required, application shall be possible.
When considering use in aircraft, medical applications, railways, incineration and fuel devices, manned transport
devices, equipment for recreation and amusement, and safety devices, in which human life or assets could be greatly
affected and for which a particularly high reliability is required in terms of safety and control system, please consult
with Mitsubishi and discuss the required specifications.
Microsoft Windows, Microsoft Windows NT are registered trademarks of Microsoft Corporation in the United States and
other countries.
Pentium is a registered trademark of Intel Corporation in the United States and other countries.
Ethernet is a registered trademark of Xerox. Co., Ltd in the United States.
Other company and product names herein are either trademarks or registered trademarks of their respective owners.
U
User's Manual (Function Explanation, Program Fundamentals)
User's Manual
(Function Explanation,
Program Fundamentals)
SQCPU(Q)-U-KI-E
MODEL
CODE
13JR44
Basic Model QCPU(Q Mode) User's Manual (Function Explanation, Program Fundamentals)
MODEL
SH(NA)-080188-B(0302)MEE
HEAD OFFICE : 1-8-12, OFFICE TOWER Z 14F HARUMI CHUO-KU 104-6212,JAPAN
NAGOYA WORKS : 1-14 , YADA-MINAMI 5 , HIGASHI-KU, NAGOYA , JAPAN
When exported from Japan, this manual does not require application to the
Ministry of Economy, Trade and Industry for service transaction permission.
Specifications subject to change without notice.
Mitsubishi Programmable
Logic Controller

Basic Model QCPU(Q Mode) User`s Manual

Transcription

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