IPC-6013C Qualification and Performance Specification for Flexible

Transcription

DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY
IPC-6013C
Qualification and Performance Specification for
Flexible Printed Boards
Final Draft for Industry Review – October 2012
A standard developed by IPC
Qualification and Performance Specification for Flexible Printed Boards
1 SCOPE
1.1 Statement of Scope This specification covers qualification and performance requirements of flexible printed
boards. The flexible printed board may be single-sided, double-sided, multilayer, or rigid-flex multilayer. All of these
constructions may or may not include stiffeners, plated-through holes, and blind/buried vias.
The flexible or rigid-flex printed board may contain build up HDI layers. The printed board may contain embedded
active or passive circuitry with distributive capacitive planes, capacitive or resistive components conforming to
IPC-6017.
The rigid section of the printed board may contain a metal core or external metal heat frame, which may be active or
nonactive.
Revision level changes are described in 1.7.
1.2 Purpose The purpose of this specification is to provide requirements for qualification and performance of flexible
printed boards designed to IPC-2221 and IPC-2223.
1.3 Performance Classification, Board Type, and Installation Usage
1.3.1 Classification This specification recognizes that flexible printed boards will be subject to variations in performance requirements based on end-use. These performance classes (Class 1, Class 2, and Class 3) are defined
in IPC-6011.
1.3.2 Printed Board Type Performance requirements are established for the different types of flexible printed
boards, classified as follows:
Type 1 - Single-sided flexible printed boards containing one conductive layer, with or without stiffeners.
Type 2 - Double-sided flexible printed boards containing two conductive layers with plated-through holes, with or
without stiffeners.
Type 3 - Multilayer flexible printed boards containing three or more conductive layers with plated-through holes, with
or without stiffeners.
Type 4 - Multilayer rigid and flexible material combinations containing three or more conductive layers with
plated-through holes.
Type 5 - Flexible or rigid-flex printed boards containing two or more conductive layers without plated-through holes.
1.3.3 Installation Uses
Use A Capable of withstanding flex during installation.
Use B Capable of withstanding continuous flexing for the number of cycles as specified on the procurement
documentation.
Use C High temperature environment (over 105 °C [221 °F]).
Use D UL Recognition. See UL 94 and UL 796F.
1.3.4 Selection for Procurement For procurement purposes, performance class and installation usage shall be
specified in the procurement documentation.
The documentation shall provide sufficient information to the supplier so that the supplier can fabricate the flexible
printed boards and ensure that the user receives the desired product. Information that should be included in the
procurement documentation is shown in IPC-D-325.
Note: If the drawing specifies the requirement in words, designators are not required.
The procurement documentation shall specify the thermal stress test method and the number of cycles (in relation
to reflow profiles in IPC-TM-650, Method 2.6.27) to be used to meet the requirement of 3.6.1. Selection shall be
from those depicted in 3.6.1.1, 3.6.1.2 and 3.6.1.3. If not specified (see 5.1), the default shall be per Table 1-2.
During the selection process, the user should take into consideration the following when determining the appropriate
thermal stress test method:



Wave solder, selective solder, hand solder assembly processes (see 3.6.1.1)
Conventional (eutectic) reflow processes (see 3.6.1.2)
Lead-free reflow processes (see 3.6.1.3)
PC-6016, a sectional performance specification for HDI printed boards, was cancelled by the IPC. Relevant HDI
conformance and acceptance criteria has been transferred to this revision of this specification.
1.3.4.1 Selection (Default) The procurement documentation shall specify those requirements that are a result of
the selection process within this specification. This includes all references to “AABUS”. If the requirement selection
is not made in accordance with the procurement documentation, Ordering Data (see 5.1), Customer Drawing and/or
supplier control plan (SCP), then the default requirement in Table 1-1 shall apply.
Table 1-1 Default Requirements
Category
Default Selection
Performance Class
Class 2
Installation Usage
Use A
Material
Final Finish
Fabricator defined
Finish X (Electrodeposited tin lead, fused or solder coated)
Minimum Starting Foil
1/2 oz. for all internal and external layers
Copper Foil Type
Plated Component Hole Diameter Tolerance
Plated Via Hole Diameter Tolerance
Fabricator defined
(±) 100 µm [3,937 µin]
(+) 80 µm [3,150 µin], (-) no requirement, (may be totally or partially plugged)
Non-plated Hole Diameter
Tolerance
(±) 80 µm [3,150 µin]
Conductor Width tolerance
Class 2 requirements per para. 3.5.1
Conductor Spacing tolerance
Class 2 requirements per para. 3.5.2
Dielectric Separation
Fabricator defined; Finished product within 80% of selected thickness
Lateral Conductor Spacing
100 µm [3,937 µin] minimum
Marking Ink
Contrasting color, nonconductive
Solder Mask
Solder Mask, specified
Not applied, if not specified
Class T of IPC-SM-840 if class not specified
Solderability Test
Category 2 of J-STD-003, tin-lead solder per 3.3.6
Isolation (Shorts) Testing
Per IPC-9252
Qualification not specified
See IPC-6011
Profile tolerance
Thermal Stress Test
0.5 mm [0.0197 in] for all external edges
IPC-TM-650, Method 2.6.8, Condition A or Condition C for polyester flexible
material per 3.6.1
1.3.5 Material, Plating Process and Final Finish
1.3.5.1 Laminate Material Laminate material is identified by numbers and/or letters, classes and types as specified
by the appropriate specification listed in the procurement documentation.
1.3.5.2 Plating Process The copper plating process used to provide the main conductor in the holes is identified by
a single number as follows:
1 - Acid copper electroplating only
2 - Pyrophosphate copper electroplating only
3 - Acid and/or pyrophosphate copper electroplating
4 - Additive/electroless copper
5 - Electrodeposited Nickel underplate with copper electroplating
Note: Pyrophosphate copper electroplating is no longer in use.
1.3.5.3 Final Finish and Coatings The final finish/coating can be one of the finishes/coatings specified below or a
combination of several platings and is dependent on assembly processes and end-use. If required, the thickness
shall be specified in the procurement documentation. If not specified, the thickness shall be as listed in Table 3-2.
Coating thickness may be exempted in Table 3-2 (i.e., tin-lead plate or solder coating). Designators for final finish
are as follows:
S
T
X
TLU
b1
G
GS
GWB-1
GWB-2
N
NB
OSP
HT OSP
ENIG
ENEPIG
DIG
NBEG
IAg
ISn
C
SMOBC
SM
SM-LPI
SM-DF
SM-TM
Y
Solder Coating
Electrodeposited Tin-Lead, (fused)
Either Type S or T
Electrodeposited Tin-Lead (unfused)
Lead-free Solder Coating
Gold Electroplate for Edge Printed Board Connectors
Gold Electroplate for Areas to be Soldered
Gold Electroplate for areas to be wire bonded (ultrasonic)
Gold Electroplate for areas to be wire bonded (thermosonic)
Nickel for Edge Printed Board Connectors
Nickel as a Barrier to Copper-Tin Diffusion
Organic Solderability Preservative
High Temperature OSP
Electroless Nickel Immersion Gold
Electroless Nickel/Electroless Palladium/Immersion Gold
Direct Immersion Gold
Nickel Barrier/Electroless Gold
Immersion Silver
Immersion Tin
Bare Copper
Solder Mask over Bare Copper
Solder Mask over Non-Melting Metal
Liquid Photoimageable Solder Mask over Non-Melting Metal
Dry Film Solder Mask over Non-Melting Metal
Thermal Mask Solder Mask over Non-Melting Metal
Other
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(Table 3-2)
(3.2.8)
(3.2.8)
(3.2.8)
(3.2.8)
(3.2.8)
(3.2.7.11)
1.4 Terms and Definitions The definition of all terms used herein shall be as specified in IPC-T-50 and as defined
in 1.4.1 through 1.4.10.
1.4.1 As Agreed Upon Between User and Supplier (AABUS) Indicates additional or alternate requirements to be
decided between the user and the supplier in the procurement documentation. Examples include contractual
requirements, modifications to purchase documentation and information on the drawing. Agreements can be used to
define test methods, conditions, frequencies, categories or acceptance criteria within a test, if not already
established.
1.4.2 Button Plating A selective plating technique in which copper is plated only in the hole barrel and a portion of
the outer layer pads. This method is utilized to avoid plating less ductile electrolytic copper on the outer layer layers
of flex circuitry.
1.4.3 Coverlay Film and adhesive made from separate layers of generically different chemistries.
1.4.4 Coverfilm Film made from
i) a homogeneous, single component;
ii) separate layers of generically similar chemistries; or
iii) as a composite blend
1.4.5 Covercoat Material deposited as a liquid onto the circuitry that subsequently becomes a permanent dielectric
coating.
NOTE: Covercoats may have reduced performance in tight bend radius applications.
1.4.6 Cover Material A thin dielectric material used to encapsulate circuitry, most commonly for flexible circuit
applications.
1.4.7 Target Land The land on which the microvia ends and makes connection.
1.4.8 Capture Land The land where the microvia starts, and varies in shape and size based on use (i.e.,
component mounting, via entrance conductor, etc.)
1.4.9 Microvia A microvia is defined as a blind structure (as plated) with a maximum aspect ratio of 1:1 when
measured in accordance with Figure 1-1, terminating on or penetrating a target land, with a total length of no more
than 250 µm [0.00984 in] measured from the structure’s capture land foil to the target land.
Figure 1-1 Microvia Definition
Note: X/Y = Microvia Plating Aspect Ratio, with X < 254 µm [0.00984 in] and aspect ratio < 1:1.
1.4.10 Core A single-sided, double-sided or multilayer board or flex circuit that is used as a carrier for HDI layers
and meets the requirements of one of the following performance specifications: IPC-6012, IPC-6013, IPC-6015 or
IPC-6018.
1.5 Interpretation ‘‘Shall,’’ the imperative form of the verb, is used throughout this standard whenever a requirement is intended to express a provision that is mandatory. Deviation from a ‘‘shall’’ requirement may be considered
if sufficient data is supplied to justify the exception.
The words ‘‘should’’ and ‘‘may’’ are used whenever it is necessary to express nonmandatory provisions.
‘‘Will’’ is used to express a declaration of purpose. To assist the reader, the word ‘‘shall’’ is presented in bold
characters.
1.6 Presentation All dimensions and tolerances in this specification are expressed in hard SI (metric) units and
parenthetical soft imperial (inch) units. Users of this specification are expected to use metric dimensions. All
dimensions greater than or equal to 1.0 mm [0.0394 in] will be expressed in millimeters and inches. All dimensions
less than 1.0 mm [0.0394 in] will be expressed in micrometers and microinches.
1.7 Revision Level Changes Changes made to this revision of the IPC-6013 are indicated throughout by
gray-shading of the relevant subsection(s). Changes to a figure or table are indicated by gray-shading of the Figure
or Table header.
2 APPLICABLE DOCUMENTS
The following specifications form a part of this specification to the extent specified herein. If a conflict of requirements exists between IPC-6013 and the listed applicable documents, IPC-6013, with the exception of IPC-6011,
shall take precedence.
2.1 IPC1
IPC-T-50
Terms and Definitions for Interconnecting and Packaging Electronic Circuits
IPC-CF-152
Composite Metallic Materials Specification for Printed Wiring Boards
IPC-D-325
Documentation Requirements for Printed Wiring
IPC-A-600
Acceptability of Printed Boards
IPC-TM-650 Test Methods Manual2
2.1.1
Microsectioning
2.1.1.2 Microsectioning-Semi or Automatic Technique Microsection Equipment (Alternate)
2.3.15 Purity, Copper Foil or Plating
2.3.38 Surface Organic Contaminant Detection List
2.3.39 Surface Organic Contaminant Identification Test (Infrared Analytical Method)
2.4.1
Adhesion, Tape Testing
2.4.2.1 Flexural Fatigue and Ductility, Foil
2.4.3
Flexural Fatigue, Flexible Printed Wiring Materials
2.4.3.1 Flexural Fatigue and Ductility, Flexible Printed Wiring
2.4.18.1 Tensile Strength and Elongation, In-House Plating
2.4.20 Terminal Bond Strength, Flexible Printed Wiring
2.4.22 Bow and Twist
2.4.28.1 Adhesion, Solder Resist (Mask) Tape Test Method
2.4.36 Rework Simulation, Plated-Through Holes for Leaded Components
2.4.41.2 Coefficient of Thermal Expansion - Strain Gage Method
2.5.7
Dielectric Withstand Voltage, PWB
2.5.5.7 Characteristic Impedance and Time Delay of Lines on Printed Boards by TDR
2.6.1
Fungus Resistance Printed Wiring Materials
2.6.3
Moisture and Insulation Resistance, Printed Boards
2.6.4
Outgassing, Printed Boards
2.6.7.2 Thermal Shock and Continuity, Printed Boards
2.6.8
Thermal Stress, Plated-Through Holes
IPC-QL-653
Qualification of Facilities that Inspect/Test Printed Boards, Components and Materials
IPC-SM-840
Qualification and Performance of Permanent Solder Mask
IPC-2221
Generic Standard on Printed Boards Design
IPC-2223
Sectional Design Standard for Flexible Printed Boards
IPC-2251
Design Guide for the Packaging of High Speed Electronic Circuits
IPC-4101
Specification for Base Materials for Rigid and Multilayer Printed Boards
IPC-4103
Specification for Base Materials for High Speed/High Frequency Applications
IPC-4202
Flexible Bare Dielectrics for use in Flexible Printed Wiring
IPC-4203
Adhesive Coated Dielectrics Films for Use in Fabrication of Flexible Printed Wiring
IPC-4204
Metal-Clad Flexible Dielectrics for Use in Fabrication of Flexible Printed Wiring
IPC-4552
Electroless Nickel/Immersion Gold Plating for Electronic Interconnections
IPC-4553
Specification for Immersion Silver Plating for Printed Circuit Boards
IPC-4562
Copper Foil for Printed Wiring Applications
IPC-4563
Resin Coated Copper Foil for Printed Boards Guideline
IPC-4761
Design Guide for Protection of Printed Board Via Structures
IPC-4781
Qualification and Performance Specification of Permanent, Semi-Permanent and Temporary
Legend and/or Marking Inks
IPC-4811
Specification for Embedded Passive Device Resistor Materials for Rigid and Multilayer Printed
Boards
IPC-4821
Specification for Embedded Passive Device Capacitor Materials for Rigid and Multilayer Printed
Boards
IPC-6011
Generic Performance Specification for Printed Boards
IPC-6017
Qualification and Performance Specification for Printed Boards Containing Embedded Passive
Devices
IPC-7711/21
Rework and Repair Guide
IPC-9252
Requirements for Electrical Testing of Unpopulated Printed Boards
IPC-9691
User Guide for the IPC-TM-650, Method 2.6.25, Conductive Anodic Filament (CAF) Resistance
Test (Electrochemical Migration Testing)
2.2 Joint Industry Standards3
J-STD-003
Solderability Tests for Printed Boards
J-STD-006
Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for
Electronic Soldering Applications
2.3 Other Publications
2.3.1 American Society for Testing and Materials4
ASTM B 488 Standard Specification for Electrodeposited Coatings of Gold for Engineering Uses
ASTM B 579 Standard Specification for Electrodeposited Coatings of Tin-Lead Alloy
2.3.2 Underwriters Lab5
UL 94 Tests for Flammability of Plastic Materials for Parts in Devices and Appliances
UL 796F Flexible Materials Interconnect Constructions
2.3.3 National Electrical Manufacturers Association6
NEMA LI-1 Industrial Laminate Thermosetting Product
2.3.4 American Society for Quality7
H1331 Zero Acceptance Number Sampling Plans
2.3.5 AMS8
SAE-AMS-QQ-A-250 Aluminum Alloy, Plate and Sheet
SAE-AMS-2424 Plating, Nickel Low-Stressed Deposit
2.3.6 American Society of Mechanical Engineers9
ASME B46.1 Surface Texture (Surface Roughness, Waviness and Lay)
2.3.7 Federal8
QQ-S-635 Steel
1. www.ipc.org
2. Current and revised IPC Test Methods are available through the IPC Web site (www.ipc.org/html/testmethods.htm).
3. www.ipc.org
4. www.astm.org
5. www.ul.com
6. www.nema.org
7. www.asq.org
8. www.sae.org
9. www.asme.org
3 REQUIREMENTS
3.1 General Flexible printed boards furnished under this specification shall meet or exceed the requirements of
IPC-6011 and the specific performance class as required by the procurement documentation. Descriptions and
purposes of test coupons are documented in IPC-2221. Although conformance to the detailed requirements may
be determined by examination of specific quality control coupons, these requirements apply to all coupons or
sample flexible printed boards and to deliverable flexible printed boards. These requirements are also based on the
assumption that the flexible printed board was designed to the appropriate IPC design standard.
3.2 Materials Used in this Specification All materials used in construction of the flexible printed board shall
comply with applicable specifications and the procurement documentation. The user has the responsibility to specify
on the procurement documentation materials capable of meeting the requirements of this specification and end item
use.
Note: When possible, material call-out information should be reviewed with the supplier so as to obtain concurrence
that the part will meet the requirements of this specification and, if necessary, to update the procurement
documentation accordingly.
3.2.1 Laminates and Bonding Materials Metal-clad laminates, unclad laminates, and bonding material (prepreg)
should be selected using IPC-4101, IPC-4103, IPC-4202, IPC-4203, IPC-4204, or NEMA LI 1-1989. Embedded
device materials shall be selected from IPC-4811 or IPC-4821 and should be as specified in the procurement
documentation including dielectric, conductive, resistive and insulating characteristics as applicable. The
specification sheet number, metal cladding type and metal clad thickness (weight) should be as specified in the
procurement documentation. When there are specific requirements, it is necessary to specify those requirements on
the material procurement documentation.
3.2.1.1 Flexible Material Options At the supplier’s option, flexible metal-clad dielectrics and adhesive coated
dielectric films may be manufactured using individual components per IPC-4562, IPC-4202, and IPC-4203. In
addition, materials per IPC-4204 may be substituted where individual components are specified.
3.2.2 External Bonding Materials The material used to adhere external heat sinks or stiffeners to the flexible
printed board should be selected from IPC-4101, IPC-4202, IPC-4203, IPC-4204, or as specified on the
procurement documentation.
3.2.3 Other Dielectric Materials Photoimageable dielectrics should be specified on the procurement
documentation. Other dielectric materials may be specified on the procurement documentation.
3.2.4 Metal Foils Copper foil should be in accordance with IPC-4562. Foil type, foil grade, foil thickness, bond
enhancement treatment, and foil profile should be specified on the master drawing if critical to the function of the
flexible printed board. Resin coated copper foil shall be in accordance with IPC-4563.
3.2.4.1 Resistive Metal Foil Resistive metal foil shall be specified in the procurement documentation.
3.2.5 Metal Planes/Cores Metal planes and/or metal core substrates shall be specified on the master drawing as
shown in Table 3-1.
Table 3-1 Internal or External Metal Planes
Material
Specification
Alloy
Aluminum
SAE-AMS-QQ-A-250
As Specified
Steel
QQ-S-635
As Specified
Copper
ASTM-B-152 or IPC-4562
As Specified
Copper-Invar- Copper
IPC-CF-152
As Specified
Copper-Moly- Copper
IPC-CF-152
As Specified
Other
As Specified
As Specified
3.2.6 Base Metallic Plating Depositions and Conductive Coatings The thickness of the plating/final finish
coatings shall be in accordance with Table 3-2. The copper plating thickness for the surface, PTHs, via holes, blind
and buried vias shall be as specified in Table 3-3, Table 3-4, Table 3-5 and Table 3-6. The thickness for specific use
platings shall be as specified in Table 3-2. The plating thickness for final finishes or combinations there-of selected
from those listed in 1.3.4.3 shall be as specified in Table 3-2. Fused tin-lead plating or solder coating only requires
visual coverage and acceptable solderability testing per J-STD-003. Coverage of platings and metallic coatings does
not apply to vertical conductor edges. Conductor surfaces may have exposed copper in areas not to be soldered
within the limits of 3.5.4.7.
3.2.6.1 Electroless Copper Depositions and Conductive Coatings Electroless depositions and conductive
coatings shall be sufficient for subsequent plating processes and may be either electroless metal, vacuum
deposited metal, or metallic or non-metallic conductive coatings.
3.2.6.2 Electrodeposited Copper When copper plating is specified, electrodeposited copper platings shall meet
the following criteria. Frequency of testing shall be determined by the manufacturer to ensure process control.
a)
When tested as specified in IPC-TM-650, Method 2.3.15, the purity of copper shall be no less than 99.50%.
b)
When tested as specified in IPC-TM-650, Method 2.4.18.1, using 50 - 100 µm [1,969 - 3,937 µin] thick
samples, the tensile strength shall be no less than 248 MPa [36,000 PSI] and the elongation shall be no less than
18%.
3.2.6.3 Fully Additive Electroless Copper Depositions Additive/electroless copper platings applied as the main
conductor metal shall meet the requirements of this specification. Deviations shall be AABUS.
3.2.7 Final Finish Depositions and Coatings - Metallic and Non-Metallic
3.2.7.1 Electrodeposited Tin The allowance of and the requirements for use of electrodeposited tin shall be
AABUS. It is recommended that the user refer to JEDEC/IPC JP002 for guidance on potential mitigation practices
that may delay the onset of, or prevent, tin whisker formation.
3.2.7.2 Electrodeposited Tin-Lead Tin-lead plating shall meet the composition (50-70% tin) requirements of ASTM
B-579. Fusing is required unless the unfused option is selected wherein the thickness specified in Table 3-2 (Code
T) applies.
3.2.7.3 Hot Air Solder Leveling (HASL)/Solder Coating The solder coating shall be as specified on the master
drawing and the bath or pot used for coating shall meet the requirements of J-STD-006. HASL is the process for
solder coating that involves dipping a printed board into solder and using hot air to level the resultant solder surface.
3.2.7.3.1 Eutectic Tin-Lead Solder Coating The solder used for conventional, lead-bearing coatings shall be in
accordance with the requirements of 3.2.7.3, except the thickness shall be in accordance with Table 3-2 (Code S).
3.2.7.3.2 Lead-Free Solder Coating The solder used for lead-free solder coating shall be in accordance with the
requirements of 3.2.7.3, except the thickness shall be in accordance with Table 3-2 (Code b1).
3.2.7.3.3 Deviations to these requirements shall be AABUS.
3.2.7.4 Electrodeposited Nickel Nickel plating thickness shall be as specified in Table 3-2 (Code NB). When used
as an undercoat or barrier layer for gold or other metals, the thicknesses shall be as specified in Table 3-2 (Code
NB).
3.2.7.5 Electrodeposited Gold Electrodeposited gold plating shall be in accordance with ASTM-B-488. Purity and
hardness shall be specified in the procurement documentation. The thickness shall be as specified in Table 3-2
(Code G, GS, GWB-1 and GWB-2).
Note: Industry investigations have shown that a gold-tin intermetallic phase forms under normal soldering process
parameters when the weight percent of gold in the solder joint reaches the 3-4% range. Refer to IPC-J-STD-001
and IPC-HDBK-001 for further information on gold removal to prevent the formation of brittle solder joints resulting
from high concentrations of gold dissolving into the solder joint.
3.2.7.6 Electroless Nickel Immersion Gold (ENIG) ENIG plating deposit shall be in accordance with IPC-4552.
Deposit thickness range shall be in accordance with IPC-4552 and as specified in Table 3-2 (Code ENIG).
Measurement methodology shall be by XRF Spectrometry in accordance with Appendix 4 of IPC-4552. Frequency
of sample thickness measurement for Class 1 and Class 2 shall be in accordance with IPC-4552 and for Class 3
location and extent of sampling shall be AABUS.
Caution: Immersion gold thicknesses above 0.125 µm [4,925 µin] can indicate an increased risk of having
compromised the integrity of the nickel undercoat due to excessive corrosion. Due to the influence of the design
pattern and chemistry process variability, acceptance of the solderability coupon may not represent the part.
Correlation of thickness measurements across the pattern is strongly encouraged to demonstrate uniformity of the
coating thickness.
3.2.7.7 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Electroless nickel shall be in
accordance with IPC-4552. Electroless palladium (alloyed or non-alloyed) shall be in accordance with ASTM-B-679.
Immersion gold shall be in accordance with IPC-4552. The thicknesses shall be as specified in Table 3-2 (Code
ENEPIG) and may be measured by XRF Spectrometry. Allowable thickness cited in Table 3-2 could skew to the
lower or higher part of the range for optimum connector or solderable surface metallurgy. Unlike nickel, palladium is
more resistant to immersion gold, hence the reduced thickness requirement for gold (coverage only). Measurement
location and extent shall be AABUS.
3.2.7.8 Immersion Silver Immersion silver plating shall be in accordance with IPC-4553. Pad size for thickness
measurements shall be in accordance with IPC-4553 and as specified in Table 3-2 (code IAg).
3.2.7.9 Immersion Tin Immersion tin plating deposit shall be in accordance with IPC-4554. Deposit thickness
range shall be in accordance with IPC-4554 and as specified in Table 3-2 (code ISn). Measurement methodology
shall be by XRF Spectrometry in accordance with Appendix 4 of IPC-4554. Frequency of sample thickness
measurement for Class 1 and Class 2 shall be in accordance with IPC-4554 and for Class 3 location and extent of
sampling shall be AABUS.
3.2.7.10 Organic Solderability Preservative (OSP) OSPs are anti-tarnish and solderability protectors applied to
copper to withstand storage and assembly processes in order to maintain solderability of surfaces. The coating
storage, pre-assembly baking and sequential soldering processes impact solderability. Specific solderability
shelf-life and soldering cycle requirements, if applicable, shall be specified in the procurement documentation.
This applies to both standard and high-temperature OSP formulations.
3.2.7.11 Other Metals and Coatings The allowance of and the requirements for use of other depositions as a final
finish per 1.3.5.3 such as bare copper, palladium and rhodium shall be AABUS.
Table 3-2 Final Finish and Coating Requirements
Code
Finish
Thickness
Applicable
Acceptability
Specification
Marking
Code1
S
Solder Coating over Bare Copper
Coverage & Solderable2
J-STD-003
J-STD-006
b0
b1
Lead-Free Solder Coating over Bare Copper Coverage & Solderable2
J-STD-003
J-STD-006
b1
T
Electrodeposited Tin-Lead (fused) - minimum Coverage & Solderable2
X
TLU
G
GS
GWB-1
Either Type S or T
Electrodeposited Tin-Lead Unfused minimum
Gold for edge printed board connectors and
areas not to be soldered - minimum
Gold Electroplate on areas to be soldered –
3
maximum
Gold Electroplate for areas to be wire bonded
(ultrasonic) – minimum
Electrolytic nickel under gold for areas to be
wire bonded (ultrasonic) - minimum
Gold Electroplate for areas to be wire bonded
(thermosonic) - minimum
GWB-2
Electrolytic nickel under gold for areas to be
wire bonded (thermosonic) - minimum
J-STD-003
J-STD-006
As indicated by code
J-STD-003
8.0 µm [315 µin]
J-STD-006
Class 1 and Class 2
0.8 µm [31.5 µin]
b3
b3
ASTM-B-488
b4
0.45 µm [17.72 µin]
ASTM-B-488
b4
0.05 µm [1.97 µin]
ASTM-B-488
b4
3.0 µm [118 µin]
None
b4
ASTM-B-488
b4
None
b4
None
N/A
N/A
Class 3
1.25 µm [49.21 µin]
Class 1 and Class 2
0.3 µm [11.8 µin]
Class 3
0.8 µm [31.5 µin]
3.0 µm [118 µin]
Class 1
2.0 µm [78.7 µin]
N
Nickel - Electroplate for edge printed board
connectors - minimum
NB
Nickel-Electroplate as a barrier4 - minimum
1.3 µm [51.2 µin]
None
OSP
Organic Solderability Preservative
Solderable7
None
b6
7
None
b6
HT OSP
High Temperature OSP
Electroless Nickel - minimum
ENIG
ENEPIG
Class 2 and Class 3
2.5 µm [98.4 µin]
Solderable
3.0 µm [118 µin]
b4
5
IPC-4552
Immersion Gold - minimum
0.05 µm [1.97 µin]
Electroless Nickel - minimum
Electroless Palladium - minimum
3.0 µm [118 µin]
0.05 µm [2.0 µin]
Coverage and
7
Solderable
IPC-4552
None
b4
N/A
None
b4
Immersion Gold – minimum
b4
DIG
Direct Immersion Gold (Solderable Surface)
Solderable5
None
b4
IAg
Immersion Silver
Immersion Tin
IPC-4553
IPC-4554
b2
ISn
Solderable6
Solderable7
b3
Code
Finish
Thickness
Applicable
Acceptability
Specification
Marking
Code1
C
Bare Copper
AABUS
AABUS
N/A
Note 1. These marking and labeleing codes represent the codes for surface finish categories established in IPC/JEDEC-J-STD-609.
Note 2. Hot Air Leveling (HAL) or Hot Air Solder Leveling (HASL) processes are considered to have a degree of difficulty in their control. This,
coupled with pad sizes and geometries placing additional challenges on such processes, places the creation of a practical minimum thickness
outside the scope of this specification. See also 3.3.6.
Note 3. See notation in 3.2.7.5.
Note 4. Nickel plating used under the tin-lead or solder coating for high temperature operating environments act as a barrier to prevent the
formation of copper-tin compounds.
Note 5. See also 3.2.7.6.
Note 6. Surface measurements, when required for immersion silver thickness, require a unique pad size for both thin and/or thick silver deposits.
See IPC-4553 for detailed measurement requirements.
Note 7. See 3.3.6.
Table 3-3 Surface and Hole Copper Plating Minimum Requirements for Through-Holes1
Copper – average2,3
Class 1
Class 2
Class 3
Type 2
12 µm [472 µin]
12 µm [472 µin]
12 µm [472 µin]
Type 3, 4 ≤ 6 layers and less than 1.5
mm [0.059 in] printed board thickness
25 µm [984 µin]
25 µm [984 µin]
25 µm [984 µin]
Type 3, 4 > 6 layers or greater than or
equal to 1.5 mm [0.059 in] printed
board thickness
35 µm [1378 µin]
35 µm [1378 µin]
35 µm [1378 µin]
AABUS
5 µm [197 µin]
12 µm [472 µin]
10 µm [394 µin]
20 µm [787 µin]
10 µm [394 µin]
10 µm [394 µin]
20 µm [787 µin]
20 µm [787 µin]
30 µm [1181 µin]
30 µm [1181 µin]
30 µm [1181 µin]
AABUS
5 µm [197 µin]
12 µm [472 µin]
Minimum Wrap4
Copper (Min. Thin Areas)
Type 2
Type 3, 4 ≤ 6 layers
Type 3, 4 > 6 layers5
Minimum Wrap4
Note 1. Does not apply to microvias (see 1.4.9).
Note 2. Copper plating (1.3.5.2) thickness shall be continuous and extend or wrap from hole walls onto outer surfaces.
Copper plating thickness should only be measured in PTH areas when checking minimum thickness requirements. Refer to
IPC-A-600 for discussion on copper plating thickness for hole walls.
Note 3. See 3.6.2.12.
Note 4. Wrap copper plating for filled PTHs and vias shall be in accordance with 3.6.2.12.1.
Note 5. For printed boards having a drilled hole diameter < 0.35 mm [0.0138 in] and having an aspect ratio >3.5:1, the
minimum thin area copper plating in the hole shall be 25 µm [984 µin].
Table 3-4 Surface and Hole Copper Plating Minimum Requirements for Buried Vias > 2 Layers, and Blind
Vias1
Thin areas4
Wrap3
Class 1
20 µm [787 µin]
18 µm [709 µin]
AABUS
Class 2
20 µm [787 µin]
18 µm [709 µin]
5 µm [197 µin]
Class 3
25 µm [984 µin]
20 µm [787 µin]
12 µm [472 µin]
Note 1. Does not apply to microvias (see 1.4.9).
Note 2. Copper plating (1.3.5.2) thickness shall be continuous and extend or wrap from hole walls onto outer surfaces. Refer
to IPC-A-600 for discussion on copper plating thickness for hole walls.
Note 3. Wrap copper plating for filled PTHs and vias shall be in accordance with 3.6.2.12.1.
Note 4. See 3.6.2.12.
Table 3-5 Surface and Hole Copper Plating Minimum Requirements for Microvias (Blind and Buried)1
Class 1
Class 2
Class 3
12 µm [472 µin]
12 µm [472 µin]
12 µm [472 µin]
Thin areas4
10 µm [394 µin]
10 µm [394 µin]
10 µm [394 µin]
AABUS
5 µm [197 µin]
6 µm [236 µin]
Wrap3
Note 1. See 1.4.9 for definition of microvia.
Note 2. Copper plating (1.3.5.2) thickness shall be continuous and wrap from hole walls onto outer surfaces. Refer to
IPC-A-600 for discussion on copper plating thickness for hole walls.
Note 3. Wrap copper plating for filled microvias shall be in accordance with 3.6.2.12.1 or 3.6.2.12.3.
Note 4. See 3.6.2.12.
Table 3-6 Surface and Hole Copper Plating Minimum Requirements for Buried via cores (2 layers)
Class 1
Class 2
Class 3
13 µm [512 µin]
15 µm [592 µin]
15 µm [592 µin]
Thin areas3
11 µm [433 µin]
13 µm [512 µin]
13 µm [512 µin]
AABUS
5 µm [197 µin]
7 µm [276 µin]
Wrap2
Note 1. Copper plating (1.3.5.2) thickness shall be continuous and extend or wrap from hole walls onto outer surfaces. Refer
to IPC-A-600 for discussion on copper plating thickness for hole walls.
Note 2. Wrap copper plating for filled buried via cores shall be in accordance with 3.6.2.12.1 or 3.6.2.12.3.
Note 3. See 3.6.2.12.
3.2.8 Polymer Coating (Solder Mask) When permanent solder mask coating is specified, it shall be a polymer
coating conforming to IPC-SM-840.
3.2.9 Fusing Fluids and Fluxes The composition of the fusing fluids and fluxes used in solder coating applications
shall be capable of cleaning and fusing the electrodeposited tin-lead plating and bare copper to allow for a smooth
adherent coating. The fusing fluid shall act as a heat transfer and distribution medium to prevent damage to the
bare laminate of the flexible printed board. The type and composition of the fusing fluid shall be optional to the
flexible printed board manufacturer.
Note: Fusing fluid compatibility should be confirmed with end users’ cleanliness requirements due to the diverse
interactions experienced at assembly soldering.
3.2.10 Marking Inks Marking inks shall be permanent, nonnutrient (fungistatic) polymer inks and shall be specified
in the procurement documentation. Marking inks shall be applied to either the flexible printed board or to a label
applied to the flexible printed board. Marking inks and labels must be capable of withstanding fluxes, cleaning solvents, soldering, and cleaning and coating processes encountered in later manufacturing processes. If a conductive
marking ink is used, the marking shall be treated as a conductive element on the flexible printed board and shall
conform to IPC-4781.
3.2.11 Hole Fill Insulation Material Material used for hole fill for flexible printed boards shall be as specified on the
3.2.12 Heatsink Planes, External Thickness and materials for construction of heatsink planes and insulation material shall be as specified in the procurement documentation.
3.2.13 Via Protection Materials for accomplishing via protection method shall be as specified in the procurement
documentation. The IPC-4761 design guideline for via protection provides information on material selection and
considerations.
3.2.14 Embedded Passive Materials Embedded passive materials are defined as materials and processes which
add capacitive, resistive and/or inductive functionality within the printed board, and which may be used with conventional core materials for the manufacture of flexible printed boards. These include laminate materials, resistive
metal foils, plated resistors, conductive pastes, protectant materials, etc. Embedded passive materials shall be
selected from IPC-4811 or IPC-4821 or as specified in the procurement documentation.
3.3 Visual Examination Finished flexible printed boards shall be examined in accordance with the following procedure. They shall be of uniform quality and shall conform to 3.3.1 through 3.3.9.
Visual examination for applicable attributes shall be conducted at 3 diopters (approx. 1.75X). For feature sizes
less than or equal to 0.010 in in size, visual examination shall be conducted at 4 – 10X. If the acceptable condition
of a suspected defect is not apparent, it should be verified at progressively higher magnifications (up to 40X) to
confirm that it is a defect. Dimensional requirements such as spacing or conductor width measurements may require
other magnifications and devices with reticles or scales in the instrument, which allow accurate measurements of the
specified dimensions. Contract or specification may require other magnifications.
3.3.1 Profile
3.3.1.1 Edges, Rigid Section Nicks or crazing along the edge of the printed board, edge of cutouts and edges of
non-plated holes are acceptable provided the penetration does not exceed 50% of the distance from the edge to the
nearest conductor or 2.5 mm [0.0984 in], whichever is less. The distance between the haloing penetration and the
nearest conductive feature shall not be less than the minimum lateral conductor spacing, or 100 µm [3,937 µin] if not
specified.
Edges shall be clean cut and without metallic burrs. Nonmetallic burrs are acceptable as long as they are not loose
and/or do not affect fit and function. Panels that are scored or routed with a breakaway tab shall meet the
depanelization requirements of the assembled flexible printed board.
3.3.1.2 Edges, Flexible Section The trimmed edges of the flexible printed board or the flexible section of finished
rigid-flex printed boards shall be free of burrs, nicks, or delamination in excess of that allowed in the procurement
documentation. Tears shall not be allowed in Type 1 or Type 2 flexible printed boards or within the flexible sections
of Type 3 or Type 4 flexible printed boards. When nicks and tears occur as a result of tie-in tabs to facilitate circuit
removal, the extent of these imperfections shall be AABUS. Minimum edge to conductor spacing shall be as
specified in the procurement documentation.
3.3.1.3 Transition Zone, Rigid Area to Flexible Area The transition zone is the area centered on the edge of the
rigid portion from which the flex portion extends. The inspection range is limited to 3.0 mm [0.118 in], centered on
the transition, which is the edge of the rigid portion (see Figure 3-1). Visual imperfections inherent to the fabrication
technique (i.e., adhesive squeeze-out, localized deformation of dielectric and conductors, protruding dielectric
materials, crazing, or haloing) shall not be cause for rejection. Imperfections in excess of that allowed shall be
AABUS, or as so stated on the procurement documentation.
Figure 3-1 Transition Zone
3.3.2 Construction Imperfections Imperfections include those characteristics that are both internal and external
within the printed board but are visible from the surface.
3.3.2.1 Measling Measling is acceptable for Class 1, Class 2 and Class 3 end product. Measled areas in laminate
substrates exceeding 50% of the spacing between non-common conductors are a process indicator for Class 3 end
product, indicating a variation in material, equipment operation, workmanship or process that is not a defect.
Although process indicators should be monitored as part of the process control system, disposition of individual
process indicators is not required and affected product should be used as is.
Note: Measling is an internal condition which does not propagate under thermal stress and has not been
conclusively shown to be a catalyst for CAF growth. Delamination is an internal condition which may propagate
under thermal stress and may be a catalyst for CAF growth. The IPC-9691 user’s guide for CAF resistance testing
and IPC-TM-650, Method 2.6.25, provide additional information for determining laminate performance regarding
CAF growth. Users who wish to incorporate additional criteria for measle conditions may consider incorporating the
provisions of IPC-6012, Class 3A which does not allow measles for Class 3 product.
3.3.2.2 Crazing Crazing is acceptable for all classes of end product provided the imperfection does not reduce the
conductor spacing below the minimum and there is no propagation of the imperfection as a result of thermal testing
that replicates the manufacturing process. For Class 2 and Class 3, the distance of crazing shall not span more than
50% of the distance between adjacent conductors.
3.3.2.3 Delamination/Blister Delamination and blistering is acceptable for all classes of end product provided the
area affected by imperfections does not exceed 1% of the printed board area on each side and does not reduce the
spacing between conductive patterns below the minimum conductor spacing. There shall be no propagation of
imperfections as a result of thermal testing that replicates the manufacturing process. For Class 2 and Class 3, the
blister or delamination shall not span more than 25% of the distance between adjacent conductive patterns. Refer to
IPC-A-600 for more information.
3.3.2.4 Foreign Inclusions Translucent particles shall be acceptable. Other particles trapped within the printed
board shall be acceptable, provided the particle does not reduce the spacing between adjacent conductors to below
the minimum spacing specified in 3.5.2.
3.3.2.4.1 Foreign Inclusions Between Flexible Printed Board and Stiffener Opaque foreign material determined
to be located between the flexible printed board and stiffener shall be acceptable provided the bulge or height of
non-conductive foreign material is no larger than 100 µm [3,940 µin]. It shall not be larger than 5% of the bonding
area of the stiffener. There shall be no contact with a component hole or printed board outline. No threadlike
non-conductive foreign material may protrude from the outline edge greater than 1.0 mm [0.040 in]. Opaque
foreign material shall not reduce the spacing between adjacent access openings below the minimum spacing
specified in 3.5.2.
3.3.2.5 Weave Exposure There shall be no weave exposure on the printed board for Class 3. Weave exposure or
exposed/ disrupted fibers are acceptable for Class 2 and Class 1 provided the imperfection does not reduce the
remaining conductor spacing (excluding the area(s) with weave exposure) below the minimum. Refer to IPC-A-600
for more information.
3.3.2.6 Exposed/Disrupted Fibers Exposed/disrupted fibers are acceptable for all Classes provided the
imperfection does not bridge conductors and does not reduce the remaining conductor spacing below the minimum.
3.3.2.7 Scratches, Dents, and Tool Marks Scratches, dents, and tool marks are acceptable, provided they do not
expose conductors or disrupt fibers greater than allowed in 3.3.2.4 and 3.3.2.5 and do not reduce the dielectric
spacing below the minimum specified. Dents or tool marks that cause delamination, changes in physical size of the
conductor, or reduces conductor width or spacing shall be rejectable.
3.3.2.8 Surface Microvoids Surface microvoids are acceptable, provided they do not exceed 0.8 mm [0.0315 in] in
the longest dimension, bridge conductors, or exceed 5% of the total flexible printed board area per side.
3.3.2.9 Color Variations in Bond Enhancement Treatment Mottled appearance or color variation in bond
enhancement treatment is acceptable. Random missing areas of treatment shall not exceed 10% of the total conductor surface area of the affected layer.
3.3.2.10 Pink Ring There is no existing evidence that pink ring affects functionality. The presence of pink ring may
be considered an indicator of process or design variation but is not a cause for rejection. The focus of concern
should be the quality of the lamination bond.
3.3.2.11 Coverlay and Coverfilm Separations The coverfilm shall be uniform and free of coverfilm separations,
such as wrinkles, creases, and soda strawing. Nonlamination shall be acceptable, provided such imperfections do
not violate 3.3.2.4 and all of the following:
a) At random locations away from conductors, if each separation is no larger than 0.80 x 0.80 mm [0.0315 x 0.03 15
in] and is not within 1.0 mm [0.0394 in] of the board edge or the coverfilm opening. The total number of separations
shall not exceed three in any 25 mm x 25 mm [0.984 in x 0.984 in] of cover-film surface area.
b) The total separation shall not exceed 25% of the spacing between adjacent conductors.
c) There shall be no coverfilm nonlamination along the outer edges or covercoat openings of the coverfilm that
reduces the seal below minimum edge to conductor spacing.
3.3.2.12 Covercoat Requirements
3.3.2.12.1 Covercoat Coverage Covercoat coverage manufacturing variations resulting in skips, voids, and misregistration are subject to the following restrictions:
a) Metal conductors shall not be exposed or bridged by blisters in areas where covercoat is required. Touch up, if
required to cover these areas with covercoat, shall be of a material that is compatible and of equal resistance to
soldering and cleaning as the originally applied covercoat.
b) In areas containing parallel conductors, covercoat variations shall not expose adjacent conductors unless the
area between the conductors is purposely left blank as for a test point or for some surface mount devices.
c) Covercoat need not be flush with the surface of the land. Misregistration of a covercoat-defined feature shall not
expose adjacent isolated lands or conductors (see Figure 3-2).
d) Covercoat is allowed on lands for plated-through holes to which solder connections are to be made, provided the
external annular ring requirements for that class of products are not violated. Covercoat shall not encroach upon the
barrel of this type of plated-through hole. Other surfaces, such as edge flexible printed board connector fingers and
surface mount lands, shall be free of covercoat, except as specified. Covercoat is allowed in plated-through holes
and vias into which no component lead is soldered, unless the procurement documentation requires that the holes
be completely solder filled. Covercoat may tent or plug via holes as specified by the procurement documentation.
Test points that are intended for assembly testing must be free of covercoat unless coverage is specified.
Figure 3-2 Unacceptable Covercoat Coverage
e) When a land contains no plated-through holes, as in the case of surface mount or ball grid array (BGA) lands,
misregistration shall not cause encroachment of the covercoat on the land or lack of solder-resist-definition in
excess of the following:
1) On surface mount lands, misregistration shall not cause encroachment of the covercoat over the land area
greater than 50 µm [1,970 µin] for a pitch ≥ 1.25 mm [0.04921 in]. Encroachment shall not exceed 25 µm [984
µin] for a pitch < 1.25 mm [0.04921 in], and encroachment may occur on adjacent sides, but not on opposite
sides of a surface mount land.
2) On BGA lands, if the land is solder-mask-defined, misregistration may allow a 90° breakout of the covercoat on
the land. If clearance is specified, no encroachment of the covercoat on the land is allowed, except at the
conductor attachment.
3) On BGA lands connected to via holes, which have coverlayer dams required, the dam shall be continuous
without missing peeling or cracked coverlayer, allowing a bare metal path between the BGA land and the via.
f) Blistering shall be allowed to the following extent:
1) Class 1: Does not bridge between conductors.
2) Class 2 and Class 3: Two per side, maximum size 0.25 mm [0.00984 in] in longest dimension, does not
reduce electrical spacing between conductors by more than 25%.
g) Pits and voids are allowed in nonconductor areas, provided they have adherent edges and do not exhibit lifting or
blistering in excess of allowance in 3.3.2.12.1(f).
h) Coverage between closely spaced surface mount lands shall be as required by procurement documentation.
i) When design requires coverage to the flexible printed board edge, chipping or lifting of covercoat along the flexible
printed board edge after fabrication shall not penetrate more than 1.25 mm [0.04291 in] or 50% of the distance to
the closest conductor, whichever is less.
3.3.2.12.2 Covercoat Cure and Adhesion The cured covercoat shall not exhibit tackiness or blistering in excess of
that permitted in 3.3.2.11.1(f). When tested in accordance with IPC-TM-650, Method 2.4.28.1, the maximum
percentage of cured covercoat lifting from Coupon G identified in IPC-2221 shall be in accordance with Table 3-3.
Table 3-3 Covercoat Adhesion
Maximum Percentage Loss Allowed
Surface
Class 1
Class 2
Class 3
Bare Copper
10
5
0
Gold or Nickel
25
10
5
Base Laminate
10
5
0
Melting Metals (Tin-lead plating,
fused tin-lead, and bright acid-tin)
50
25
10
3.3.2.12.3 Covercoat Thickness Covercoat thickness is not measured, unless specified on the procurement documentation. If a thickness measurement is required, instrumental methods may be used or an assessment may be
made using a microsection of the parallel conductors on Coupon E identified in IPC-2221.
3.3.2.13 Solder Wicking/Plating Penetration Solder wicking or other plating penetration shall not extend into a
bend or flex transition area and shall meet the conductor spacing requirements. Solder wicking or other plating
penetration shall not exceed the limits specified in Table 3-4. Wicking shall be measured from the machined edge
of the cover opening. Do not include squeeze-out in the measurement.
Table 3-4 Solder Wicking/Plating Penetration Limits
Class 1
Class 2
Class 3
AABUS
0.5 mm [0.0197 in]
maximum
0.3 mm [0.0118 in]
maximum
See Figure 3-3, which displays penetration limits, defined as m1 and m2.
Figure 3-3 Solder Wicking and Plating Penetration
3.3.2.14 Stiffener Bonding Mechanical stiffeners, which are bonded to the flexible area of the printed board with
either a thermo-setting adhesive or a pressure sensitive adhesive (PSA) to provide structural support, do not require
void free lamination. Voids between the stiffener and the flex circuit are common due to the irregular topography of
the flex circuitry.
Voids between the stiffener and the flex circuit are acceptable so long as the bonded stiffener meets the peel
strength requirements of 3.10.16.
Adhesive squeeze-out shall not reduce the available annular ring below the minimum solderable annular ring
requirements.
3.3.3 Plating and Coating Voids in the Hole Plating and coating voids shall not exceed that allowed by Table 3-6.
Table 3-6 Plating and Coating Voids Visual Examination
Material
Copper
Finish Coating
Class 1
Class 2
Class 3
Three voids allowed per
hole in not
more than 10%
of the holes
One void
allowed per
hole in not
more than 5% of the holes
None
Five voids allowed per
hole in not
more than 15%
of the holes
Three voids allowed per hole
in not
One void
allowed per
hole in not
Note 1. For Class 2 product, copper voids shall not exceed 5% of the hole length. For Class 1 product, copper voids shall not exceed 10% of
the hole length. Circumferential voids shall not extend beyond 90° of the circumference.
Note 2. For Class 2 and 3 product, finished coating voids shall not exceed 5% of the hole length. For Class 1, finished coating voids shall not
exceed 10% of the hole length. Circumferential voids shall not extend beyond 90° for Class 1, Class 2 or Class 3.
3.3.4 Lifted Lands When visually examined in accordance with 3.3, there shall be no lifted lands on the deliverable
(nonstressed) flexible printed board.
3.3.5 Marking If required, each individual flexible printed board, qualification flexible printed board, and set of quality
conformance test circuit strips (as opposed to each individual coupon) shall be marked. This marking is required in
order to ensure traceability between the flexible printed board /test strips and the manufacturing history and to
identify the supplier (i.e., logo). If size or space does not permit marking individual flexible printed boards, bagging or
tagging is permitted.
The marking shall be produced by the same process as used in producing the conductive pattern or by use of a
permanent fungistatic ink or paint (see 3.2.10), LASER marker, or a vibrating pencil marking on a permanently
attached label or metallic area provided for marking purposes.
Conductive markings, either etched copper or conductive ink (see 3.2.10), shall be considered as electrical
elements of the circuit and shall not reduce the electrical spacing requirements. All markings shall be compatible
with materials and parts, legible for all tests, and in no case affect flexible printed board performance.
Marking shall not cover areas of lands that are to be soldered (see IPC-A-600 for legibility requirements). In addition
to this marking, the use of bar code marking is permissible. When used, date code shall be formatted per the
supplier’s discretion in order to establish traceability as to when the manufacturing operations were performed.
For lead-free end product, the labeling requirements of J-STD-609 shall be met.
3.3.6 Solderability Only those flexible printed boards that require soldering in a subsequent assembly operation
require solderability testing. Flexible printed boards that do not require soldering do not require solderability testing
and this shall be specified on the master drawing, as in the case where press-fit components are used. Flexible
printed boards to be used only for surface mount do not require hole solderability testing.
When required by the procurement documentation, accelerated aging for coating durability shall be in accordance
with J-STD-003. The category of durability shall be specified on the master drawing; however, if not specified, Category 2 shall be used, which does not require accelerated aging for coating durability. Specimens to be tested shall
be conditioned, if required, and evaluated for surface and hole solderability using J-STD-003.
When solderability testing is required, consideration should be given to flexible printed board thickness and copper
thickness. As both increase, the amount of time to properly wet the sides of the holes and the tops of the lands
increases proportionately.
Note: Accelerated aging (steam aging) is intended for use on coatings of tin/lead, tin/lead solder, or tin, but not other
final finishes.
3.3.7 Plating Adhesion Flexible printed boards shall be tested in accordance with IPC-TM-650, Method 2.4.1,
using a strip of pressure sensitive tape applied to the surface and removed by manual force applied perpendicular to
the circuit pattern.
There shall be no evidence of any portion of the protective plating or the conductor pattern foil being removed, as
shown by particles of the plating or pattern foil adhering to the tape. If overhanging metal (slivers) breaks off and
adheres to the tape, it is evidence of overhang or slivers, but not of plating adhesion failure.
3.3.8 Edge Board Contact, Junction of Gold Plate to Solder Finish Exposed copper/plating overlap between the
solder finish and gold plate shall meet the requirements of Table 3-7. The exposed copper/plating or gold overlap
may exhibit a discolored or gray-black area, which is acceptable (see 3.5.4.4).
Table 3-7 Edge Board Contact Gap
Max. Exposed Copper Gap
Max. Gold Overlap
Class 1
2.5 mm [0.0984 in]
2.54 mm [0.0984 in]
Class 2
1.25 mm [0.04921 in]
1.25 mm [0.04921 in]
Class 3
0.8 mm [0.0315 in]
0.8 mm [0.0315 in]
3.3.9 Workmanship Flexible printed boards shall be processed in such a manner as to be uniform in quality and
show no visual evidence of dirt, foreign matter, oil, fingerprints, tin/lead, or solder smear transfer to the dielectric
surface, flux residue, and other contaminants that affect life, ability to assemble, and serviceability. Visually dark
appearances in non-plated through holes, which are seen when a metallic or nonmetallic semiconductive coating is
used, are not foreign material and do not affect life or function. Flexible printed boards shall be free of defects in
excess of those allowed in this specification. There shall be no evidence of any lifting or separation of platings from
the surface of the conductive pattern, or of the conductor from the base laminate in excess of that allowed. There
shall be no loose plating slivers on the surface of the flexible printed board.
A chip of coverlay or covercoat adhered to exposed adhesive that does not fall off when rubbed with isopropyl
impregnated applicator shall be acceptable for Class 1 and Class 2 product. No visible substance should be
observed to be adhered to the adhesive in Class 3 product.
3.4 Dimensional Requirements Inspection of dimensional requirements shall be as defined herein unless
otherwise agreed upon between user and supplier. The printed board shall meet the dimensional requirements
specified in the procurement documentation. All dimensional characteristics such as, but not limited to, printed board
periphery, thickness, cutouts, slots, notches, holes, scoring and edge board contacts to connector key area shall be
as specified in the procurement documentation. However, in the event that dimensional tolerances are not specified
in the procurement documentation, the applicable feature tolerances of the IPC-2220 design series shall apply.
Printed board dimensional locations of basic or bilateral tolerance as defined in the procurement documentation
shall be inspected in accordance with the applicable AQL classification as specified in Table 4-3.
Automated inspection technology is allowed.
Supplier in-process certification of features of accuracy to reduce inspection is allowed provided the method is
documented and demonstrates capability to meet the specified requirements. The supplier may provide a statement
of certification of accuracy based on the suppliers sampling plan which includes a process data collection and
recording system.
In the event that the supplier does not have a process certification system for dimensional accuracy the AQL levels
of Table 4-3 shall apply for each production lot.
3.4.1 Hole Size, Hole Pattern Accuracy and Pattern Feature Accuracy The hole size tolerance, hole pattern
accuracy and feature location accuracy shall be as specified in the procurement documentation.
Finished hole size tolerance shall be verified on a sample basis across all hole sizes applicable to the design. The
number of measures per hole size shall be determined by the manufacturer to adequately sample the quantity of
holes within the population.
Only specific dimensioned holes, to include both non-plated through and plated-through, shall be inspected for hole
pattern accuracy to meet board dimensional requirements of 3.4. Unless required by the master drawing, hole
pattern accuracy for other nonspecifically dimensioned holes, such as plated-through holes and vias, need not be
checked as they are database supplied locations and are controlled by annular ring requirements to surface or
internal lands. If required by master drawing, hole pattern accuracy may be certified by a statement of qualification
or by AQL sampling per 3.4.
Pattern feature accuracy shall be as specified in the procurement documentation. Pattern feature accuracy may be
certified through a statement of qualification or by AQL sampling per 3.4. However, in the event that any of these
characteristics are not specified in the procurement documentation, the applicable IPC-2220 design series shall
apply. Automated inspection technology is allowed.
Nodules or rough plating in plated-through holes shall not reduce the hole diameter below the minimum limits
defined in the procurement document.
3.4.2 Annular Ring and Breakout (External) The minimum external annular ring shall meet the requirements of
Table 3-8. The measurement of the annular ring on external layers is from the inside surface (within the hole) of the
plated hole, or unsupported hole, to the outer edge of the annular ring on the surface of the printed board as shown
in Figure 3-4.
When breakout occurs and meets the requirements of Table 3-8, the plated-through hole shall meet the
requirements of 3.6.2.1 and 3.6.2.2. When breakout is permitted at the conductor/land intersection it shall be in
accordance with Figure 3-6 (conformance is defined as dimension A being larger than dimension B).
The finished printed board with the related breakout shall meet the electrical requirements of 3.8.2 (see Figures 3-5
and 3-6). Unless prohibited by the customer, the employment of filleting or ‘‘tear drops’’ to create additional land
area at the conductor junction shall be acceptable for Class 1 and Class 2 and in accordance with general
requirements for lands with holes detailed in IPC-2221. Employment of filleting or ‘‘tear drops’’ in Class 3 product
shall be AABUS.
Figure 3-4 Annular Ring Measurement (External)
Note 1: See Figure 3-5 and 3-6 for land breakout and conductor width reduction at land.
Note 2. Minimum lateral spacing shall be maintained. See Figure 3-5 and 3-6 for visual examples of land breakout and conductor width reduction
at land.
Note 3. See 3.6.2.10 regarding annular ring requirements for functional and nonfunctional lands.
Figure 3-5 Breakout of 90° and 180°
Figure 3-6 Conductor Width Reduction
Table 3-8 Minimum Etch Annular Ring1
Characteristic
Class 1
Class 2
Class 3
Not greater than 90° breakout
of hole from land when visually
The minimum annular ring shall
assessed and a 50 µm
Not greater than 180° breakout [1,970 µin] annular ring for at least
be 50 µm [1,970 µin].
2
270° of the circumference.
The minimum external annular ring
assessed.2
EXTERNAL
The land/conductor junction shall may have 20% reduction of the
PTHs
The land/conductor junction shall
not be reduced below the
minimum annular ring in isolated
allowable width reduction in
areas due to defects such as pits,
not be reduced below the allow3.5.3.1. The conductor junction dents, nicks, pinholes, or splay in
able width reduction in 3.5.3.1.
should never be < 50 µm [1,970 the annular ring of isolated areas.
µin] or the minimum line width,
whichever is smaller.
Not greater than 90° breakout of
hole from land when visually
assessed.
assessed.
There shall be no evidence of
Microvia Capture
Land
breakout.
3.5.3.1.
The conductor junction should
3.5.3.1.
never be less than 50 µm [1,969
µin] or the minimum line width,
whichever is smaller.
90° Hole breakout is allowed
Hole breakout is allowed provided
provided the land/conductor
INTERNAL
the land/conductor junction is not
The minimum internal annular
junction is not reduced below the
3
Ring shall be 25 µm [984 µin].
PTHs
reduced below the allowable width
reduction in 3.5.3.1
3.5.3.1
90° hole breakout is allowed
Hole breakout is allowed provided
provided the land/conductor
the land/conductor junction is not
junction is not reduced below the
reduced below the allowable width
reduction in 3.5.3.1
There shall be no evidence of
3.5.3.1.
Microvia Target Land
breakout.
When microvia overshoot occurs
When microvia overshoot occurs
at target land, dielectric thickness
at target land, dielectric thickness
below the target land shall not
below the target land shall not
reduce the dielectric spacing
reduce the dielectric spacing
below that specified in 3.6.2.17.
below that specified in 3.6.2.17.
The minimum annular ring shall
be 150 µm [5,906 µin].
The minimum external annular
assessed.2
assessed.2
EXTERNAL
ring may have a 20% reduction
Unsupported holes The land/conductor junction shall The land/conductor junction shall of the minimum annular ring in
isolated areas due to defects such
as pits, dents, nicks, pinholes or
splay in the annular ring of isolated
3.5.3.1.
3.5.3.1.
areas.
3.4.2.1 Solderable Annular Ring (External) Adhesive squeeze-out, solder mask misregistration, and/or coverlay
on land areas are permitted; however, the minimum solderable annular ring shall meet the requirements of Table
3-9.
When examined in accordance with 3.3, the measurement of the annular ring on external layers is from the inside
surface (within the hole) of the plated or unsupported hole to the outer edge of the annular ring on the surface of the
flexible printed board. If breakout occurs it shall not be allowed within the conductor/land intersection and the
plated-through hole shall meet the requirements of 3.6.2.1 and 3.6.2.2.
3.4.2.1.1 Solderable Annular Ring (External - Capture Land to Microvia) Capture lands shall provide
evidence of land at a minimum. Breakout is not allowed, unless the design and procurement documentation
specify (i.e., landless microvia).
3.4.2.1.2 Solderable Annular Ring (Evidence of Land Edge) Allowance Certain flexible printed boards are
designed to have solderable annular ring on one side of the hole only. For example, some Type 1 and Type 5
flexible printed boards are manufactured with dual sided access (back bared). They depend on either the coverlay or
substrate to anchor the pad to the flexible printed board. Similarly other flexible printed board designs, including
those with PTHs, may limit access hole diameter to minimize solder volume or maximize dielectric between holes.
These types of flexible printed boards are designed with a smaller access opening (minor access) on the component
side and a larger access opening (major access) on the solderable side of unsupported holes as shown in Figure
3-7. Unless otherwise specified in the procurement documentation, the solderable annular ring requirement shall
maintain evidence of land edge for 360° at the smaller access openings.
Figure 3-7 Major and Minor Access Holes for Flexible Printed Boards with Tangency Allowance
3.4.2.2 Squeeze-Out of Adhesive of Coverlay and Ooze-Out of Covercoat Squeeze-out (j) of coverlay adhesive
or ooze-out of covercoat on the foil surface, as shown in Figure 3-8, shall meet the requirements of Table 3-9. On
the land area, as shown in Figure 3-8, the minimum solderable annular ring (k) shall meet the requirements of Table
3-10.
Note: Missing material or skips in the bead of adhesive squeeze-out at coverlay edges are permissible as shown in
Figure 3-9. Surface finish is not required to be present in these areas, but shall meet the requirements of 3.5.4.7.
Figure 3-8 Squeeze-Out of Cover Film Adhesive and Ooze-Out of Covercoat
Figure 3-9 Missing material or skips in the bead of adhesive squeeze-out at coverlay edges
1. Coverfilm
2. Conductors with access lands
3. Edge of access hole in machined Coverfilm
4. Squeeze-out of adhesive of coverlay
5. Flaking or skips in the bead of adhesive squeeze-out
Table 3-9 Allowable Squeeze-Out of Coverlay Adhesive and Ooze-Out of Covercoat
Class
70.0 µm [2,756 µin] Foil and
Below
Above 70.0 µm [2,756 µin] Foil
1 and 2
≤ 300 µm [11,810 µin]
≤ 500 µm [19,690 µin] or AABUS
3
≤ 200 µm [7,870 µin]
≤ 400 µm [15,750 µin] or AABUS
Table 3-10 Minimum Solderable Annular Ring on Land Area
Class
Solderable Annular Ring
1
2
3
A solderable annular ring for at least 240° of the circumference.
A 50 µm [1,970 µin] solderable annular ring for at least 270° of the
circumference.
A 50 µm [1,970 µin] solderable annular ring for 360° of the
circumference.
3.4.2.3 Stiffener Access Hole Registration of the stiffener to the flexible printed board shall not reduce external
annular ring requirements below that specified in 3.4.2.
3.4.3 Bow and Twist (Individual Rigid or Stiffener Portions Only) Unless otherwise specified in the procurement
documentation, when designed in accordance with IPC-2221 and IPC-2223, the rigid or stiffener portions of the
flexible printed board shall have a maximum bow and twist of 0.75% for applications that use surface mount
components and 1.5% for all other applications. For any product grouped in pallet arrays for assembly purposes,
bow and twist requirements of the array will need to be AABUS.
Bow, twist, or any combination thereof shall be determined by physical measurement and percentage calculation in
accordance with IPC-TM-650, Method 2.4.22, which describes four procedures used to determine bow and twist of
either cut to size panels or finished flex or rigid-flex printed boards including single-sided, double-sided and
multilayer.
3.4.4 Array Sub-Pallets Additional tooling holes, conductive patterns and areas for coupons may be added by the
supplier within the non-part portion of the sub-pallet. ‘‘Keep-out’’ zones for any supplier-added features or other
restrictions on the array sub-pallet shall be documented in the design.
3.5 Conductor Definition All conductive areas on flexible printed boards, including conductors, lands, and planes,
shall meet the visual and dimensional requirements of 3.5.1 through 3.5.4.8. The conductor pattern shall be as
specified in the procurement documentation. Verification of dimensional attributes shall be performed in accordance
with IPC-A-600. AOI inspection methods are allowed. Internal conductors are examined during internal layer processing prior to multilayer lamination.
3.5.1 Conductor Width and Thickness When not specified on the master drawing the minimum conductor width
shall be 80% of the conductor pattern supplied in the procurement documentation. When not specified on the
master drawing, the minimum conductor thickness shall be in accordance with 3.6.2.13 and 3.6.2.14.
3.5.2 Conductor Spacing The conductor spacing shall be within the tolerance specified on the master drawing.
Minimum conductor spacing may be reduced in isolated areas per Table 3-11. Minimum spacing between the
conductor and the edge of the flexible printed board shall be as specified on the master drawing.
If minimum spacing is not specified, the allowed reduction in the nominal conductor spacings shown in the
engineering documentation due to processing shall be 20% for Class 3 and 30% for Class 1 and Class 2 (minimum
product spacing requirements as previously stated apply) (see Figure 3-10).
Table 3-11 Conductor Spacing Requirements
Class 1 & Class 2
Class 3
Minimum conductor spacing may be reduced an
additional 30% due to conductor edge roughness,
spikes, etc.
spikes, etc.
Figure 3-10 Unnecessary Copper Between Conductor and Nodule of Conductor
3.5.3 Conductor Imperfections The conductive pattern shall contain no cracks, splits, or tears. The physical
geometry of a conductor is defined by its width x thickness x length. Any combination of defects specified in 3.5.3.1
and 3.5.3.2 shall not reduce the equivalent cross-sectional area (width x thickness) of the conductor by more than
20% of the minimum value (minimum thickness x minimum width) for Class 2 and Class 3 and 30% of the minimum
value for Class 1. The total combination of defect area lengths on a conductor shall not be >10% of the conductor
length or 25 mm [0.984 in] for Class 1 or 13 mm [0.512 in] for Class 2 or Class 3, whichever is less.
3.5.3.1 Conductor Width Reduction Allowable reduction of the minimum conductor width (specified or derived)
due to misregistration or isolated defects (i.e., edge roughness, nicks, pinholes, and scratches), which expose base
material, shall not exceed 20% of the minimum conductor width for Class 2 and Class 3 and 30% of the minimum
conductor width for Class 1.
Note: The allowable reductions assume that the manufacturer at front end tooling (CAM) understands their etch
allowance and adds a producibility compensation to the original artwork design.
3.5.3.2 Conductor Thickness Reduction Allowable reduction of the minimum conductor thickness due to isolated
defects (i.e., edge roughness, nicks, pinholes, depressions, and scratches) shall not exceed 20% of the minimum
conductor thickness for Class 2 and Class 3 and 30% of the minimum conductor thickness for Class 1.
3.5.4 Conductive Surfaces
3.5.4.1 Nicks and Pinholes in Ground or Voltage Planes Nicks and pinholes are acceptable in ground or voltage
planes for Class 2 and Class 3 if they do not exceed 1.0 mm [0.0394 in] in their longest dimension and there are no
more than four per side per 625 cm2 [96.88 in2]. For Class 1, the longest dimension shall be 1.5 mm [0.0591 in] with
no more than six per side, per 625 cm2 [96.88 in2].
3.5.4.2 Solderable Surface Mount Lands Defects along the edge of the land or internal to the land shall not
exceed the requirements in 3.5.4.2.1 through 3.5.4.2.2.
3.5.4.2.1 Rectangular Surface Mount Lands Defects such as nicks, dents, and pin holes along the external edge
of the land shall not exceed 20% of either the length or width of the land for Class 2 or Class 3 printed boards, or
30% for Class 1, and shall not encroach the pristine area, which is defined by the central 80% of the land width by
80% of the land length as shown in Figure 3-11. Defects internal to the land shall not exceed 10% of the length or
width of the land for Class 2 or Class 3 printed boards, or 20% for Class 1, and shall remain outside of the pristine
area of the surface mount land. Electrical test probe ‘‘witness’’ marks within the pristine area for Class 1, Class 2 and
Class 3 are considered cosmetic in nature and are acceptable provided the requirements for final finish are met.
3.5.4.2.2 Round Surface Mount Lands (BGA Pads) Defects such as nick, dents and pin holes along the edge of
the land shall not radially extend towards the center of the land by more than 10% of the diameter of the land for
Class 1, 2 or 3 printed boards and shall not extend more than 20% around the circumference of the land for Class 2
or Class 3 printed boards or 30% for Class 1 as shown in Figure 3-12. There shall be no defects within the pristine
area which is defined by the central 80% of the land diameter. Electrical test probe ‘‘witness’’ marks within the
pristine area for Class 1, Class 2 and Class 3 are considered cosmetic in nature and are acceptable provided the
requirements for final finish are met.
3.5.4.3 Wire Bond Pads (WBP) The wire bond pad shall have a final conductor finish as specified in 1.3.5.3 for
ultrasonic (GWB-1) and thermosonic (GWB-2) wire bonding of gold electroplate or electroless nickel/immersion gold
(ENIG), or as specified in the procurement documentation. The final finish coating thickness shall be per Table 3-2
for the applicable coating used. The pristine area shall consist of the central 80% of the pad width by 80% of the pad
length of the wire bond pad as shown in Figure 3-11. The maximum surface roughness in the pristine area of the
wire bond pad shall be measured in accordance with an applicable test method as agreed upon between user and
supplier and shall be 0.8 µm [32 µin] RMS (Root-Mean-Square). If using IPC Method 2.4.15, it is recommended that
the roughness-width cutoff identified in Method 2.4.15 be adjusted to approximately 80% of the maximum length of
the wire bond pad in order to obtain the RMS value within the pristine area. There shall be no pits, nodules,
scratches, electrical test probe ‘‘witness’’ marks, or other defects in the pristine area that violate the 0.8 µm [32 µin]
RMS roughness requirement. For more information on surface roughness, refer to ASME B46.1.
Figure 3-11 Rectangular Surface Mount Lands
Figure 3-12 Round Surface Mount Lands
3.5.4.4 Board Edge Connector Lands On gold or other noble metal-plated edge flexible printed board connector
lands, except as noted below, the insertion or contact area shall be free of the following:
a) Cuts or scratches that expose nickel or copper.
b) Solder splashes or tin-lead plating.
c) Nodules or metal bumps that protrude above the surface.
Pits, dents, or depressions are acceptable if they do not exceed 150 µm [5,910 µin] in their longest dimension and
there are not more than three per land and do not appear on more than 30% of the lands. The imperfection limits do
not apply to a band 150 µm [5,910 µin] wide around the perimeter of the land, including the insertion area.
3.5.4.5 Dewetting For tin, tin/lead reflowed, or solder coated surfaces, dewetting on conductors, areas of solder
connection, and ground or voltage planes is allowed to the extent listed below:
a) Conductors and planes not intended for solder connection for all classes.
b) Individual areas of solder connection: Class 1, 15%; Class 2 and Class 3, 5%.
3.5.4.6 Nonwetting For tin, tin/lead reflowed or solder coated surfaces, nonwetting is not permitted on any con-
ductive surface where a solder connection will be required.
3.5.4.7 Final Finish Coverage Final finish shall meet the solderability requirements of J-STD-003.
3.5.4.7.1 Exposed Copper (Areas not to be soldered) Exposed copper on areas not to be soldered is permitted
on 5% of the surfaces for Class 1, Class 2 and Class 3. Coverage does not apply to vertical conductor edges.
3.5.4.7.2 Tin-Lead under Solder Mask (Areas not to be soldered) Solder mask overlap or encroachment onto tin
lead or solder on areas not to be soldered is acceptable provided the overlap does not exceed 150 µm [5,906 µin].
3.5.4.8 Cap Plating of Filled Holes When cap plating of the filled hole is specified on the procurement
documentation, plating voids exposing the via fill are not allowed, unless covered by solder mask. Visually
discernable depressions (dimples) and protrusions (bumps) over filled holes are acceptable.
3.5.4.9 Copper Filled Microvias Visually discernable depressions (dimples) and protrusions (bumps) over copper
filled microvias are acceptable.
3.5.4.10 Conductor Edge Outgrowth There shall be no evidence of outgrowth on edges of conductors that have
been solder coated or tin-lead plated and fused when tested in accordance with IPC-TM-650, Method 2.4.1 (see
IPC-2221).
3.5.4.11 Nonfunctional Lands A fabricator shall not remove nonfunctional lands without specific approval of the
design activity or unless allowed on the master drawing.
3.6 Structural Integrity Flexible printed boards shall meet structural integrity requirements for thermally stressed
evaluation coupons specified in 3.6.2.
Although the A and B or A/B coupons are assigned for this test, the allowance for the usage of printed boards to
establish acceptance criteria for the product shall be AABUS. Areas selected from printed boards shall contain
holes and copper features so that all criteria within this specification can be evaluated. Microsections selected from
printed boards shall be removed from opposite panel corners, shall be inspected in the x and y axis, and shall each
have three (3) holes minimum.
The production flexible printed board and all other coupons in the quality conformance test circuitry that contain
plated-through holes shall be capable of meeting the requirements of this section. Structural integrity shall be used
to evaluate test specimens from Type 2 through Type 4 flexible printed boards by microsectioning techniques.
Characteristics not applicable to Type 2 flexible printed boards (i.e., requirements for innerlayer separations,
innerlayer inclusions, and inner foil cracks) are not evaluated. Dimensional measurements that are only possible
through the use of microsectioning techniques are also defined in this section. Blind and buried vias shall meet the
requirements of plated-through holes. Refer to IPC-2221 for appropriate coupon design of blind and buried vias for
plated hole evaluation.
The evaluation of all properties and requirements shall be performed on the thermally stressed coupon and all
requirements must be met; however, per supplier election, certain properties and conditions as defined below may
be evaluated in a coupon(s) that has not been thermally stressed:












Copper voids
Plating folds/inclusions
Burrs and nodules
Glass fiber protrusion
Wicking
Final coating plating voids
Etchback
Negative etchback
Plating/coating thickness
Internal and surface copper layer or foil thickness
Laminate (rigid)
Annular Ring
3.6.1 Thermal Stress Testing Test coupons or printed boards shall be thermally stressed. Per the applicable
criteria listed in 1.3.3, one or more of the following Test Methods shall be required. Consideration should be given
to low temperature laminate material and bond ply (thermal plastics).
3.6.1.1 Thermal Stress Testing, Method 2.6.8 Test coupons or printed boards shall be thermally stressed in
accordance with IPC-TM-650, Method 2.6.8, Test condition A.
3.6.1.2 Thermal Stress Testing, Method 2.6.8 Test coupons or printed boards shall be thermally stressed in
accordance with IPC TM-650, Method 2.6.8, Test condition B.
3.6.1.3 Thermal Stress Testing, Method 2.6.27 (230 °C)Test coupons or printed boards shall be thermally
stressed in accordance with IPC-TM-650, Method 2.6.27, 230° C reflow profile.
3.6.1.4 Thermal Stress Testing, Method 2.6.27 (260 °C)Test coupons or printed boards shall be thermally
stressed in accordance with IPC-TM-650, Method 2.6.27, 260° C reflow profile.
3.6.1.5 Deviations to Thermal Stress Testing Deviations to these requirements shall be AABUS.
3.6.1.6 Microsection Requirements Following stress, test coupons or printed boards shall be microsectioned.
Microsectioning shall be accomplished per IPC-TM-650, Method 2.1.1 or 2.1.1.2, on test coupons or printed boards.
Evaluation of all applicable holes and vias, including blind and buried, for all such structures found on the finished
printed board shall be inspected in the vertical cross section in accordance with Table 4-3. The grinding and
polishing accuracy of the microsection shall be such that the viewing area of each of the holes is within 10% of the
drilled diameter of the hole.
Plated-through holes shall be examined for foil and plating integrity at a magnification of 100X ± 5%. Referee examinations shall be accomplished at a magnification of 200X ± 5%. Each side of the hole shall be examined independently. Examination for laminate thickness, foil thickness, plating thickness, lay-up orientation, lamination and plating
voids, etc., shall be accomplished at magnifications specified above. For foils less than 3/8 oz., higher
magnifications may be required to confirm minimum thickness requirement. Plating thicknesses below 1.0 µm [39.4
µin] shall not be measured using metallographic techniques.
Microvias shall be examined for plating integrity and interconnection integrity at a magnification of 200X ± 5%. Referee examinations shall be accomplished at a magnification of 400 - 500X. Each side of the hole shall be
examined independently. The grinding and polishing accuracy of the microsection shall be such that the viewing
area of the microvia is within 10% of the drilled hole diameter for three microvias. For copper filled microvias, the
grinding and polishing accuracy is not required.
Note: Alternate techniques used to supplement microsection evaluation shall be AABUS.
3.6.2 Requirements for Microsectioned Coupons or Production Boards When examined in microsection, the
coupons shall meet the requirements of Table 3-12 and 3.6.2.1 through 3.6.2.18.
3.6.2.1 Plating Integrity Plating integrity in the plated-through holes shall meet the requirements detailed in Table
3-12. For Class 2 and Class 3 product, there shall be no separation of plating layers (except as noted in Table 3-12),
no plating cracks, and internal interconnections shall exhibit no separation or contamination between plated hole
wall and internal layers.
Metal core or thermal planes, when used as electrically functional circuitry, shall meet the above requirements when
made from copper; but those made from dissimilar metals may have small spots or pits at their junction with the hole
wall plating. Those areas of contamination or inclusions shall neither exceed 50% of each side of the
interconnection, nor occur in the interface of the copper cladding on the core and the copper plating in the hole wall
when viewed in the microsection evaluation.
3.6.2.2 Plating Voids Any copper plating thickness less than that specified for minimum thin areas in Table 3-2
shall be considered a void. Allowances for plating voids are established in Table 3-12 for all Classes of end
product. For Class 2 and Class 3 product, the following criteria shall also be met:
a) There shall be no more than one plating void per test specimen, regardless of length or size.
b) There shall be no plating void in excess of 5% of the total flexible printed board thickness, excluding stiffeners.
c) There shall be no plating voids evident at the interface of an internal conductive layer and the plated-through hole
wall.
d) Circumferential plating voids greater than 90° are not allowed.
Conductor finish plating or coating material between the base material and copper plating (i.e., behind the hole wall
copper plating) is evidence of a void. Any plated hole exhibiting this condition shall be counted as having a single
void for panel acceptance purposes.
If a void is detected during evaluation of a microsection which meets the above criteria, resample in accordance with
Table 4-2 using samples from the same lot to determine if the defect is random. If the additional test coupons or
production boards have no plating voids, the product which the test coupon or production boards represent are
considered acceptable; however, if a plating void is present in the microsections, the product shall be considered
nonconforming.
Table 3-12 Plated-Through Hole Integrity After Stress
Property
Copper voids
Plating folds/inclusions
Class 1
Class 2
Class 3
Three voids allowed per
One void allowed per test
One void allowed per test
hole. Voids in the same
specimen, provided the
specimen, provided the
plane are not allowed.
additional microsection
additional microsection
No void shall be longer
criteria of 3.6.2.2 are met
criteria of 3.6.2.2 are met
than 5% of flexible
printed board thickness.
No circumferential
voids greater than 90° are
allowed
The minimum copper thickness in Table 3-3 through Table 3-6 must be met. For positive
etchback, measurements should follow the topography of the dielectric. When negative
etchback results in folds in the copper plating, the copper thickness shall meet the minimum
requirements as measured from the face of the internal layer; negative etchback limits shall
not be exceeded. See Figure 3-20. Sample must be microetched to evaluate.
Burrs1 and nodules
Allowed if minimum hole diameter is met. The minimum copper thickness in Table 3-3
through Table 3-6 must be met
Allowed if minimum hole diameter is met. The minimum copper thickness in Table 3-3
1
Glass fiber protrusion
through Table 3-6 must be met
Wicking (maximum copper plating
205 µm [8,070 µin],
180 µm [7,090 µin],
160 µm [6,300 µin],
penetration including 80 µm [315
provided the additional
µin] etchback
microsection criteria
allowance)
of 3.6.2.9 are met
of 3.6.2.9 are met
of 3.6.2.9 are met
175 µm [6,890 µin],
150 µm [5,910 µin],
130 µm [5,120 µin],
Wicking (maximum copper plating
penetration including 50 µm [1,968
µin] smear removal allowance)
of 3.6.2.9 are met
of 3.6.2.9 are met
of 3.6.2.9 are met
Interplane inclusions (inclusions at Allowed on only one side
the interface between internal
of hole wall at each
None allowed
lands and through-hole plating)
land location on 20% of each
available land
Internal foil cracks2
“C”cracks allowed on only one
side of hole,
None allowed
provided it does not extend
through foil thickness
External foil cracks2 (type ‘‘A’’ ‘‘B’’ “D” cracks not allowed ‘‘A’’
‘‘D’’ and ‘‘B’’ cracks not allowed
and ‘‘D’’ cracks)
and ‘‘B’’ cracks allowed
‘‘A’’ cracks allowed
Barrel/Corner cracks2 (type ‘‘E’’
None allowed
and ‘‘F’’ cracks)
Interplane separation (separation
Allowed on only one side
at the interface between internal
of hole wall at each land
None allowed
lands and through-hole plating)
location on 20% of
each available land
Separations along the vertical
Allowed (see Figure 3-13), provided it does not extend
edge of the external land(s)
beyond the vertical edge of the external copper foil
Plating Separation
Allowed at knee, maximum
None allowed
length 130 µm [5,120 µin]
Acceptable, provided dimensional and plating requirements are met
Hole wall dielectric/ plated barrel
separation
Lifted lands after thermal stress or
Allowed, provided the finished flexible printed board meets the visual criteria of 3.3
rework simulation
Note 1.
As measured from the end of the protrusion into the hole.
Note 2.
Copper crack definition: See Figure 3-14.
“A” crack = A crack in the external foil.
“B” crack = A crack that does not completely break plating (minimum plating remains).
“C” crack = A crack in the internal foil.
“D” crack = A crack in the external foil and plating - complete break in foil and plating.
“E” crack = A barrel crack in plating only.
“F” crack = A corner crack in the plating only.
Figure 3-13 Separation at External Foil
Figure 3-14 Crack Definition
3.6.2.3 Flexible Laminate Integrity For Class 1, Class 2, and Class 3 flexible printed boards, there shall be no
adhesive voids outside of any thermal zone (see Figure 3-15) in excess of 0.50 mm [0.0197 in]. Boundary line voids
that overlap into a thermal zone shall not be in excess of 50.0 µm [0.00197 in]. Multiple voids between two
adjacent PTHs in the same plane shall not have a combined length which exceeds these limits.
3.6.2.4 Rigid Laminate Integrity Laminate cracks in a thermal zone (Figure 3-15) are acceptable with the exception
that cracks between two uncommon conductors in either the horizontal or vertical direction shall not decrease the
minimum dielectric spacing. Boundary line cracks that overlap into a thermal zone shall not be in excess of 80 µm
[3,150 µin] for Class 2 or Class 3 products, and 150 µm [5,906 µin] for Class 1 products. Multiple cracks between
two adjacent PTHs in the same plane shall not have a combined length which exceeds these limits.
Figure 3-15 Typical Microsection Evaluation Specimen
Note 1.
Thermal zones are defined by a 0.08 mm [0.0031 in] perimeter around the entirety of each via or through-hole structure (including
internal and external lands).
Note 2. Laminate anomalies or imperfections outside of the thermal zones are not evaluated on specimens which have been exposed to
thermal stress or rework simulation.
Note 3. Delamination/Blistering is evaluated regardless of whether any portion of the anomaly is within or without a thermal zone.
Note 4. Plating Voids.
Note 5. Laminate anomalies or imperfections in the non-evaluation areas are not evaluated on specimens which have been exposed to thermal
stress or rework simulation.
3.6.2.5 Delamination or Blistering For Class 2 and Class 3 there shall be no evidence of delamination or blistering.
For Class 1, if delamination or blistering is present, evaluate the entire board per 3.3.2.3.
3.6.2.6 Etchback (Type 3 and Type 4 Only) When specified on the procurement documentation, flexible printed
boards shall be etched back for the lateral removal of adhesive, resin and/or glass fibers from the drilled hole wall
prior to plating. The etchback shall be between 5 µm [197 µin] (copper exposed) and 80 µm [3,150 µin] (maximum
material removed) with a preferred depth of 13 µm [512 µin], unless in contact with a fluoropolymer (see 3.6.2.6.1).
Shadowing is permitted on one side of each land (see Figure 3-16). When no etchback is specified and the printed
board manufacturer elects to use etchback, the manufacturer s
hall be qualified to perform etchback through demonstration of qualification test coupons or printed boards.
Note: Due to the various materials used in the construction of rigid-flex printed boards, varying degrees of etchback
amongst the various materials is to be expected in the finished product. Adhesiveless constructions exhibit minimal
etchback at the flexible dielectric to metal interface.
Caution: Etchback greater than 50 µm [1,970 µin] may cause folds or voids in the plating, which then may not meet
the required copper thickness.
Figure 3-16 Etchback Depth Allowance
The combination of dielectric removal from etchback, wicking and random tears or drill gouges resulting from hole
formation and/or hole cleaning shall not exceed the sum of the maximum allowable etchback and the maximum
allowable wicking. Measurement for maximum dielectric removal is depicted in Figure 3-17.
Figure 3-17 Maximum Dielectric Removal Resulting From Etchback
3.6.2.6.1 Etchback of Fluoropolymer Dielectrics When in contact with a fluoropolymer layer, etchback shall be
between a negative etchback of 25 um and a positive etchback of 50 um.
3.6.2.7 Smear Removal
3.6.2.7.1 Smear removal on Non-Fluoropolymer Laminates (Type 3 and Type 4 Only) Smear removal is removal
of resin debris that results from the formation of the hole. Smear removal shall be sufficient to meet the acceptability
criteria for plating separation (see Table 3-12). Smear removal shall not be etched back greater than 25 m [984 in];
random tears or drill gouges which produce small areas where the 25 m [984 in] depth is exceeded shall not be
evaluated as smear removal. Smear removal is not required of Type 1 and Type 2 printed boards (see Figure 3-18).
3.6.2.7.2 Resin Smear on Fluoropolymer Laminates Allowable resin smear shall be 25% of the vertical inner layer
actual measured thickness for Type 3 and 4 printed boards. There is no requirement for Type 1 and Type 2 printed
boards. Resin removal (etchback) caused by smear removal shall meet the requirements of Table 3-12. Two or three
point plating connection is not required.
a. If fluoropolymer resin smear is greater than 25% of the actual measured layer thickness, then further referee
testing is required for acceptance by resampling and preparing two additional sets of microsections from the same
panel and evaluating using the criteria in above. For the panel to be accepted, both microsections shall meet the
acceptance criteria.
b. Smear that is fully detached shall meet minimum copper thickness requirements of Table 3-3 through Table 3-6 as
measured from the end of the smear to the inside of the finished hole wall.
c. Smear that is partially detached from the layer interface shall meet the minimum requirements per items a and b
above.
Figure 3-18 Smear Removal Allowance
3.6.2.8 Negative Etchback Negative etchback shall not exceed the dimensions in Figure 3-19 when measured as
shown in Figure 3-19. Negative etchback shall not be allowed when etchback has been specified on the procurement documentation. When negative etchback results in folds or inclusions in the copper plating, the copper
thickness shall meet the minimum requirements as measured from the face of the internal layer as shown in Figure
3-20.
Note: Dimension “X” within Figure 3-19 depicts the most prevalent amount (70 – 80% of the total thickness) of
etched internal copper foil.
Figure 3-19 Negative Etchback
Figure 3-20 Plating Folds/Inclusions – Minimum Measurement Points
Note 1. Minimum measurement points. Folds that are not enclosed are acceptable if minimum thickness is met where
indicated.
Note 2. Enclosed folds (inclusions) acceptable if minimum thickness is met where indicated.
Note 3. Measure copper plating between lines on inclusions (must meet minimum thin area requirement).
Note 4. Areas with the appearance of plating folds where there is no plating demarcation evident between the void and
the inside edge of the plating. The thickness measurement of A - B shall comply with the minimum plating thickness
in 3.6.2.14.
3.6.2.9 Wicking (Copper Plating) When etchback is specified on the master drawing, the maximum copper plating
penetration, when measured from the edge of the drilled hole, shall not exceed the values in Table 3-12, which is
the sum of copper wicking and etchback allowances (see Figure 3-16), or shall not violate the minimum conductor
spacing below the minimum requirements in 3.5.2. See also 3.6.2.10.1 regarding minimum conductor spacing.
When etchback is not specified on the master drawing (smear removal only), the maximum copper plating penetration, when measured from the edge of the drilled hole, shall not exceed the values in Table 3-12, which is the
sum of copper wicking and smear removal allowances (see Figure 3-18), or shall not violate the minimum conductor
spacing below the minimum requirements in 3.5.2).
3.6.2.10 Annular Ring and Breakout (Internal) Internal annular ring, if not determined by alternate techniques that
are AABUS, shall be measured by microsection to verify conformance to Table 3-8 as shown in Figure 3-21.
Measurements for internal annular ring are taken at the copper hole wall plating/internal land interface to the outer
most tip of the internal land as shown in Figure 3-21. Negative etchback is evaluated per 3.6.2.8 and Figure 3-19.
External pads of vias produced as sequentially laminated structures may be evaluated in-process prior to additional
lamination(s) (see 3.4.2). When sequentially produced vias are evaluated in-process their compliance shall be
documented. Lands not associated with a sequential via structure shall be evaluated as internal annular ring at
microsection. Microsection analysis is performed per 3.6.2. Unless prohibited by the customer, the employment of
filleting or ‘‘tear drops’’ to create additional land area at the conductor junction shall be acceptable for Class 1 and
Class 2 and in accordance with general requirements for lands with holes detailed in IPC-2221. Employment of
filleting or ‘‘tear drops’’ in Class 3 product shall be AABUS.
Figure 3-21 Annular Ring Measurement (Internal)
Note: The printed board design may have nonfunctional lands of varying sizes for conductor routing spacing
constraints.
The functional lands shall meet the minimum annular ring requirement. Non-functional lands which are less than the
functional land diameter are not required to meet the minimum annular ring requirement.
Note: Consideration should be given to how the microsection cut is ‘‘clocked,’’ or rotated. Misregistration can occur
randomly as opposed to orthogonally and therefore an orthogonal cut will not guarantee that a microsection view will
portray hole breakout, if it exists. See Figure 3-22 and Figure 3-23 for an example of how breakout may or may not
be detected within a microsection based on the rotation.
For Class 2 printed boards, if internal annular ring breakout is detected in the vertical cross section, but the degree
of breakout cannot be determined, internal registration may be assessed by nondestructive techniques other than
microsection, such as special patterns, probes, and/or software, which are configured to provide information on the
interpolated annular ring remaining and pattern skew. Techniques include, but are not limited to the following:





The optional F coupon.
Custom designed electrically testable coupons.
Radiographic (x-ray) techniques.
Horizontal microsection.
CAD/CAM data analysis as correlated to pattern skew by layer.
Note: Microsectioning or statistical sampling shall be used to verify correlation of the approved technique, and a
calibration standard established for the specific technique employed.
Figure 3-22 Microsection Rotations for Breakout Detection
Figure 3-23 Comparison of
Microsection Rotations
3.6.2.10.1 Breakout (Internal) Conditions If misregistration to the point of breakout is detected in vertical
micro-sections, the concerns are that:
a) The conductor width minimum may be compromised at the land junction and,
b) There is insufficient electrical spacing.
Note: Electrical spacing may be further compromised due to the combined copper plating penetration of both
etchback and wicking.
The extent and direction of misregistration shall be determined. Actual printed boards or appropriate test coupons
shall then be tested to determine compliance. This may be accomplished by the techniques listed in 3.6.2.10.
3.6.2.10.2 Microvia to Target Breakout at the target land is allowed up to 180°. Breakout, if it occurs, shall
neither reduce the intended contact area (at the target land) below that specified on the applicable slash sheet
nor reduce the minimum electrical spacing below that specified on the procurement documentation.
Note: If using an ablation-type process, tangency may be required as a minimum (due to potential reduction in
dielectric separation).
The extent and direction of misregistration shall be determined. Actual printed boards or appropriate test coupons
shall then be tested to determine compliance. This may be accomplished by the techniques listed in 3.6.2.10.
3.6.2.11 Lifted Lands Lifted lands, with the exception of blind microvias, are allowed on the thermally stressed
microsection.
3.6.2.12 Plating/Coating Thickness Based on microsection examination or the use of suitable electronic measuring equipment, plating/coating thickness shall meet the requirements of Table 3-2 through Table 3-6 or be as
specified on the procurement documentation. Measurements in the plated-through hole shall be reported as an
average thickness per side of the hole. Isolated thick or thin sections shall not be used for averaging. Isolated areas
of reduced copper thickness due to glass fiber protrusions shall meet the minimum thickness requirements of Table
3-3 through Table 3-6 as measured from the end of the protrusion to the hole wall.
If copper thickness less than the minimum specified in Table 3-3 through Table 3-6 is detected in isolated areas, it
should be considered a void and resampled in accordance with Table 4-2 using samples from the same lot to
determine if the defect is random. If the additional test coupons or printed boards have no isolated areas of reduced
copper thickness, the product which the test coupons or printed boards represent are considered acceptable;
however, if reduced copper thickness is present in the microsections, the product shall be considered
nonconforming.
3.6.2.12.1 Copper Wrap Plating Copper wrap plating minimum as specified in Table 3-3 through Table 3-6 shall be
continuous from the filled plated hole onto the external surface of any plated structure and extend by a minimum of
25 µm [984 µin] where an annular ring is required (see Figure 3-24 and Figure 3-25). Reduction of surface wrap
copper plating by processing (sanding, etching, planarization, etc.) resulting in insufficient wrap plating is not
allowed (see Figure 3-26).
Note: Cap plating, if required, over filled holes is not considered in wrap copper thickness measurements.
Figure 3-24 Surface Copper Wrap Measurement (Applicable to all filled plated-through holes)
Figure 3-25 Wrap Copper in Type 4 PCB (Acceptable)
Note: Dimension lines and arrows indicate where wrap copper has been removed.
Figure 3-26 Wrap Copper Removed by Excessive Sanding/Planarization (Not Acceptable)
3.6.2.12.2 Copper Cap Plating of Filled Holes When copper cap plating of filled holes (resin, conductive ink,
copper, etc.) for solderable lands (attachment of surface mount devices) is specified by the procurement
documentation (see also Figure 3-27), the requirements in Table 3-13 and the following shall apply. The cap
protrusion (bump) and depression (dimple) shall be measured as shown in Figure 3-28 and Figure 3-29. Voids
over resin filled holes are not allowed as shown by example in Figure 3-30. Separation of copper cap plating to fill
material is acceptable. Separation of the cap plating to underlying plating shall not be acceptable.
Table 3-13 Cap Plating Requirements1
Class 1
Class 2
Class 3
Copper Cap – Minimum
Thickness
AABUS
5 µm [0.0002 in]
12 µm [472 µin]
Filled via Depression
(Dimple) - Maximum
AABUS
127 µm [0.005 in] 76 µm [0.003 in]
Filled Via Protrusion
(Bump) - Maximum
AABUS
50 µm [0.002 in]
50 µm [0.002 in]
Note 1: Does not apply to copper filled microvias.
Figure 3-27 Copper Cap Thickness
Figure 3-28 Copper Cap Filled Via Height (Bump)
Figure 3-29 Copper Cap Depression (Dimple)
Figure 3-30 Copper Cap Plating Voids
3.6.2.12.3 Plated Copper Filled Microvias (Blind and Buried) When specified by procurement documentation,
microvias shall be completely filled with copper, except that voids shall be acceptable provided they are completely
encapsulated, in total do not exceed 25% of the area of the filled microvia, and copper plating adjacent to
encapsulated voids shall meet the requirements for thin area plating in Table 3-5 within areas defined by
dimensions “X” and “Y” in Figure 1-1 and as shown in Figure 3-31, and shall not include plating from subsequent
plating steps. Voids not fully encapsulated within these limits are not acceptable, as shown in the example in
Figure 3-32.
Figure 3-31 Example of Acceptable Voiding in a Copper Filled Microvia
Note 1: Copper cap plating.
Note 2: Void/Cavity.
Figure 3-32 Example of Nonconforming Void in Copper Filled Microvia
Note 1: Copper cap plating.
Note 2: Void/Cavity.
Microvias that are copper filled are exempt from copper wrap requirements when overplated with 5 µm [0.0002 in]
minimum copper. Separation of the overplate to underlying plating and copper fill shall not be acceptable. The
requirements for minimum surface conductor thickness (3.6.2.15) shall apply.
Requirements for protrusions (bumps) or depressions (dimples) in blind, copper filled microvias in the microsection
evaluation shall be AABUS. There are no requirements for buried copper filled microvias.
3.6.2.13 Microvia Contact Dimension The microvia to target land contact dimension shall not be reduced by
more than 50% of the capture land hole diameter as defined in Figure 3-33 and Table 3-14. For Class 1 and
Class 2 product, any inclusions on the surface of the target land shall not be considered part of the contact area.
The length defined in Note 1 of Figure 3-33 is exempt from the requirements of Table 3-15. The microvia
contact dimension may be determined by another method AABUS.
Figure 3-33 Microvia Contact Dimension
Note 1. Contact Dimension at Target Land
Note 2. Microvia Diameter at Capture Land
Minimum Contact Dimension
Allowable Inclusions within the
Minimum Microvia Contact
Dimension
Table 3-14 Microvia Contact Dimension
Class 1
Class 2
50% Total
One, Not to Exceed 10% of Note 2 (Dimension 2)
Class 3
50% Continuous
No inclusions within the
50% contact area
3.6.2.14 Minimum Internal Layer Copper Foil Thickness If the internal conductor thickness is specified by a foil
weight, the minimum internal copper thickness after processing shall be in accordance with Table 3-15 for all
classes. This table is based on minimum copper foil thickness allowances per IPC-4562 followed by two successive
scrubbings. Each scrub is expected to remove a specific amount of copper and is represented in the table by a
variable processing allowance reduction. When the procurement documentation specifies a minimum copper
thickness for conductors, the conductor shall meet or exceed that minimum thickness.
3.6.2.15 Minimum Surface Conductor Thickness The minimum total (copper foil plus copper plating) conductor
thickness after processing shall be in accordance with Table 3-16 and the following.
a) When the procurement documentation specifies a minimum copper thickness for external conductors, the
specimen shall meet or exceed that minimum thickness.
b) When the copper thickness associated with the area of a land is locally reduced resulting in a stepped thickness,
the minimum total (copper foil plus copper plating) thickness shall be maintained within the minimum annular ring
requirement or the minimum land feature size tolerance whichever is less greater.
c) Where selective (button) plating is performed, the minimum copper foil thickness requirements of Table 3-15
apply. When pattern or panel plating is performed, all lands and conductors must meet the minimum copper foil
thickness requirements of Table 3-16.
d) The minimum surface conductor thickness after processing values given in Table 3-16 are determined by the
following equation:
Minimum Surface Conductor Thickness = a + b - c
Where:
a = Absolute copper foil minimum (IPC-4562 nominal less 10% reduction).
b = Minimum copper plating thickness (10 µm [394 µin] for Type 2; 20 µm [787 µin] for Type 3 and 4 < 6 layers; 30
µm [1,181 µin] for Type 3 and 4 > 6 layers).
c = A maximum variable processing allowance reduction.
Table 3-15 Internal Layer Foil Thickness after Processing
Weight
Minimum Final
Finish after
Processing
(µm) [µin]
Absolute Cu Min. (IPC-4562
Maximum Variable Processing
less 10% reduction) (µm)
Allowance Reduction1(µm) [µin]
[µin]
1/8oz. [5.10]
4.60 [181]
1.50 [59]
3.1 [122]
1/4 oz. [8.50]
7.70 [303]
1.50 [59]
6.2 [244]
3/8 oz. [12.00]
10.80 [425]
1.50 [59]
9.3 [366]
1/2 oz. [17.10]
15.40 [606]
4.00 [157]
11.4 [449]
1 oz. [34.30]
30.90 [1,217]
6.00 [236]
24.9 [980]
2 oz. [68.60]
61.70 [2,429]
6.00 [236]
55.7 [2,193]
3 oz. [102.90]
92.60 [3,646]
6.00 [236]
86.6 [3,409]
4 oz. [137.20]
123.50 [4,862]
Above 4 oz.
[137.20]
IPC-4562 value
less 10% reduction
6.00 [236]
6.00 [236]
117.5 [4,626]
6 µm [236 µin] below minimum thickness
of calculated 10% reduction of foil
thickness in IPC-4562
Note 1.
Process allowance reduction does not allow for rework processes for weights below 1/2 oz. For 1/2 oz. and above, the process
allowance reduction allows for one rework process.
Table 3-16 External Conductor Thickness after Plating1,2
Weight3,4
1/8 oz.
Minimum Surface Conductor
Maximum
Absolute Cu
Plus minimum
Plus minimum
Thickness after Processing (µm) [µin]
Variable
Min.
Plus minimum
plating for
plating for
Processing
(IPC-4562 less plating for Type 2
Type 3, 4
Type 3, 4
Allowance
5
10% reduction) (10 µm) [394 µin]
≤ 6 layers
> 6 layers
6
Type 3, 4
Type 3, 4
5
5 Reduction
Type 2
(µm) [µin]
(20 µm) [787 µin] (30 µm) [1181 µin]
≤ 6 layers
> 6 layers
(µm) [µin]
4.60 [181]
14.60 [575]
24.60 [967]
34.60 [1,362]
1.50 [59]
13.1 [516]
23.1 [909]
33.1 [1,303]
1/4 oz.
7.70 [303]
17.70 [697]
27.70 [1,091]
37.70 [1,484]
1.50 [59]
16.2 [638]
26.2 [1,031]
36.2 [1,425]
3/8 oz.
10.80 [425]
20.80 [819]
30.80 [1,213]
40.80 [1,606]
1.50 [59]
19.3 [760]
29.3 [1,154]
39.3 [1,559]
1/2 oz.
15.40 [606]
25.40 [1,000]
35.40 [1,394]
45.40 [1,787]
2.00 [79]
23.4 [921]
33.4 [1,315]
43.4 [1,709]
1 oz.
30.90 [1,217]
40.90 [1,610]
50.90 [2,004]
60.90 [2,398]
3.00 [118]
37.9 [1,491]
47.9 [1,886]
57.9 [2,280]
2 oz.
61.70 [2,429]
71.70 [2,823]
81.70 [3,217]
91.70 [3,610]
3.00 [118]
68.7 [2,705]
78.7 [3,098]
88.7 [3,492]
3 oz.
92.60 [3,646]
102.60 [4,039]
112.60 [4,433]
122.60 [4,827]
4.00 [157]
98.6 [3,882] 108.6 [4,276] 118.6 [4,669]
123.50 [4,862]
133.50 [5,236]
143.50 [5,650]
153.50 [6,043]
4.00 [157]
129.5 [5.098] 139.5 [5,492] 149.5 [5,886]
4 oz.
Note 1: The values in this table assume a single plating operation.
Note 2. When selective (button) plating is performed, refer to 3.6.2.15.
Note 3. Starting foil weight of design requirement per procurement documentation.
Note 4. For copper foil above 4 oz., utilize the formula provided in 3.6.2.15.
Note 5. Reference: Min. Cu Plating Thickness
Type 2 = (10 µm) [394 µin]
Type 3 and 4 < 6 layers = (20 µm) [787 µin]
Type 3 and 4 > 6 layers = (30 µm) [1,181 µin]
Note 6. Process allowance reduction does not allow for rework processes for weights below 1/2 oz. For 1/2 oz. and above, the process
allowance reduction allows for one rework process.
3.6.2.16 Metal Cores All metal core printed boards, which have clearance between the PTHs and the metal core,
shall require a horizontal microsection prepared to view the metal core/hole fill insulation. Specimens shall have
been subjected to thermal stress in accordance with 3.6.1 prior to microsectioning. Wicking, radial cracks, lateral
spacing, or voids in the hole-fill insulation material shall not reduce the electrical spacing between adjacent
conductive surfaces to <100 µm [3,937 µin]. Wicking and/or radial cracks shall not exceed 750 µm [29,530 µin] from
the plated-through hole edge into the hole-fill. (see Figure 3-34).
Figure 3-34 Metal Core to Plated-Through Hole Spacing
3.6.2.17 Dielectric Spacing The minimum dielectric spacing shall be specified on the procurement documentation.
Figure 3-35 provides an example of a measurement technique for minimum dielectric spacing.
Note: Minimum rigid dielectric spacing may be specified to be 30 µm [1,181 µin]; however, low profile copper foils
should be used and the voltages employed should be taken into consideration so as not to cause breakdown
between layers. If the minimum dielectric spacing and the number of reinforcing layers are not specified, the
minimum dielectric spacing shall be 90 µm [3,543 µin] and the number of reinforcing layers shall be selected by the
supplier to ensure the minimum dielectric spacing. When the nominal rigid dielectric thickness on the drawing is less
than 90 µm [3,543 µin], the minimum rigid dielectric spacing is 25 µm [984 µin] and the number of reinforcing layers
may be selected by the supplier. Products designed for transmission line impedance applications may have
special requirements and measurement methods specified within the procurement documentation.
Figure 3-35 Measurement of Minimum Dielectric Spacing
3.6.2.18 Material Fill of Blind and Buried Vias and Microvias Non-copper material fill in blind, buried and microvia
structures are subject to the following requirements:



Fill (other than copper) shall be 50% minimum for Class 2 and Class 3. They may be completely void of fill
material for Class 1.
Fill material within the blind via shall be planar with the surface within +/- 0.076 mm [0.003 in].
When cap plating is specified, fill material within the blind via shall meet the dimple/bump requirements of
Table 3-13.
3.6.2.19 Nail Heading No evidence exists that nail heading affects functionality. The presence of nail heading may
be considered an indicator of process or design variation but is not a cause for rejection.
3.7 Solder Mask Requirements When solder mask is required on printed boards, it shall meet the
qualification/conformance requirements of IPC-SM-840. If a solder mask performance class is not specified for
Class 1 or Class 2, IPC-SM-840 Class T shall be used. For Class 3 board performance, IPC-SM-840 Class H shall
be used. The following other conformance requirements apply:
3.7.1 Solder Mask Coverage Solder mask coverage manufacturing variations resulting in skips, voids, and misregistration are subject to the following restrictions:
a.
Metal conductors shall not be exposed in areas where solder mask is required. Touch up, if required to
cover these areas with solder mask, shall be of a material that is compatible to and of equal resistance to
soldering and cleaning as the originally applied solder mask.
b.
In areas containing parallel conductors, solder mask variations shall not expose adjacent conductors
unless the area between the conductors is purposely left blank as for a test point or for some surface
mount devices.
c.
Conductors under components shall not be exposed or shall be otherwise electrically isolated. If the
component pattern is not readily apparent, the area covered by a component shall be shown in the
procurement document.
d.
Solder mask need not be flush with the surface of the land. Misregistration of a solder mask defined
feature shall not expose adjacent isolated lands or conductors.
e.
Solder mask is allowed on lands for plated-through holes to which solder connections are to be made provided the external annular ring requirements for that Class of products are not violated; mask shall not
encroach upon the barrel of this type of plated-through hole. Other surfaces such as edge board connector
fingers and surface mount lands shall be free of solder mask except as specified. Solder mask is allowed
in plated-through holes and via holes into which no component lead is soldered unless the procurement
document requires that the holes be completely solder filled. Solder mask may tent or plug via holes and
may be required for that purpose. Test points that are intended for assembly testing must be free of solder
mask unless coverage is specified.
f.
When a land contains no plated-through holes, as in the case of surface mount or ball grid array lands,
misregistration shall not cause encroachment of the solder mask on the land or lack of
solder-mask-definition in excess of the following:
1) on surface mount lands misregistration shall not cause encroachment of the solder mask over the
land area greater than 50 µm [1,970 µin] for a pitch of 1.25 mm [0.04921 in] or greater; and encroachment
shall not exceed 25 µm [984 µin] for a pitch less than 1.25 mm [0.04921 in]; encroachment may occur on
adjacent sides but not on opposite sides of a surface mount land.
2) on ball grid array lands, if the land is solder-mask defined, misregistration may allow a 90° breakout
of the solder mask on the land; if clearance is specified, no encroachment of the solder mask on the land
is allowed except at the conductor attachment.
g.
Pits, voids and bubbles are allowed in nonconductor areas provided they have adherent edges and do not
exhibit lifting or blistering in excess of allowance in 3.7.2.
h.
Coverage between closely spaced surface mount lands shall be as required by procurement
documentation.
i.
When design requires coverage to the board edge, chipping or lifting of solder mask along the board edge
after fabrication shall not penetrate more than 1.25 mm [0.04921 in] or 50% of the distance to the closest
conductor, whichever is less.
3.7.2 Solder Mask Cure and Adhesion The cured solder mask coating shall not exhibit tackiness, delamination, or
blistering to the following extent:
a.
Class 1 does not bridge between conductors.
b.
Class 2 and Class 3 two per side, maximum size 0.25 mm [0.00984 in] in longest dimension, does not
reduce electrical spacing between conductors by more than 25%.
Rework and touch up, if required to cover these areas with solder mask, shall be of a material that is compatible to
and of equal resistance to soldering and cleaning as the originally applied solder mask. When tested in accordance
with IPC-TM-650, Method 2.4.28.1, the maximum percentage of cured solder mask lifting from the G coupon or
production printed board shall be in accordance with Table 3-17.
Table 3-17 Solder Mask Adhesion
Maximum Percentage Loss Allowed
Surface
Class 1
Class 2
Class 3
Bare Copper
10
5
0
Gold or Nickel
25
10
5
Base Laminate
10
5
0
Melting Metals (Tin-lead
plating, fused tin-lead, and
bright acid-tin)
50
25
10
3.7.3 Solder Mask Thickness Solder mask thickness is not measured unless specified in the procurement documents. If a thickness measurement is required, instrumental methods may be used or assessment may be made
using a microsection of the parallel conductors on the E coupon.
3.8 Electrical Requirements When tested as specified in Table 4-3 and Table 4-4, the flexible printed board shall
meet the electrical requirements detailed in the following paragraphs.
3.8.1 Dielectric Withstanding Voltage Applicable coupons tested as outlined below shall meet the requirements of
Table 3-18, without flashover, sparkover, or breakdown between conductors or conductors and lands. The dielectric
withstanding voltage test shall be performed in accordance with IPC-TM-650, Method 2.5.7. The dielectric
withstanding voltage shall be applied between common portions of each conductor pattern and adjacent common
portions of each conductor pattern. The voltage shall be applied between conductor patterns of each layer and the
electrically isolated pattern of each adjacent layer.
Table 3-18 Dielectric Withstanding Test Voltages
Voltage for spacing 80 µm [3,150 µin] or
greater
Voltage for spacing 24 to 80 um [0.0010 in to
0.00315 in]
Voltage for spacing < 24 um [0.0010 in]
Time
Class 1
Class 2
Class 3
No
requirements
500 Vdc +15, -0
500 Vdc +15, -0
No
requirements
250 Vdc +15, -0
250 Vdc +15, -0
No
requirements
AABUS
AABUS
No
requirements
30 sec +3, -0
30 sec +3, -0
3.8.2 Electrical Continuity and Isolation Resistance Flexible printed boards shall be tested in accordance to
IPC-9252. Electrical continuity and isolation resistance testing for sub-lamination is not required.
3.8.2.1 Continuity Flexible printed boards and qualification test boards shall be tested in accordance with the
procedure outlined below. There shall be no circuits whose resistance exceeds the values established in the
procurement documentation. Specialized circuitry consisting of long runs of very narrow conductors, or short runs of
very large conductors may increase or decrease these values. The acceptability criteria for these specialized
conductors must be specified in the procurement documentation.
A current shall be passed through each conductor or group of interconnected conductors by applying electrodes on
the terminals at each end of the conductor or group of conductors. The current passed through the conductors shall
not exceed that specified in IPC-2221 for the smallest conductor in the circuit. For qualification as referenced in 4.1.1
and 4.1.2, the test current shall not exceed one ampere. Boards with designed resistive patterns shall meet the
resistance requirements specified on the master drawing.
3.8.2.2 Isolation Resistance Printed boards or qualification test boards shall be tested in accordance with the
following procedure. The isolation resistance between conductors shall meet the values established in the procurement documentation.
The voltage applied between networks must be high enough to provide sufficient current resolution for the measurement. At the same time, it must be low enough to prevent arc-over between adjacent networks, which could
induce defects within the product. For manual testing, the voltage shall be 200 volts minimum and shall be applied
for a minimum of five seconds. When automated test equipment is used, the minimum applied test voltage shall be
the maximum rated voltage of the printed board. When not specified, use the default value of 40 volts DC.
3.8.3 Circuit/Plated-Through Hole Shorts to Metal Substrates Printed boards shall be tested in accordance with
3.8.1 except that polarizing voltage of 500 volts (DC) shall be applied between conductors and/or lands and the
metallic heatsink in a manner such that each conductor/land area is tested (e.g., using a metallic brush or aluminum
foil). The board shall be capable of withstanding 500 volts (DC) between circuitry/plated-through holes and the
metal core substrates. There shall be no flashover or dielectric breakdown.
3.8.4 Moisture and Insulation Resistance (MIR) Test coupons shall be tested in accordance with the procedure
outlined below. The test coupon shall not exhibit subsurface imperfections in excess of that allowed in 3.3.2. Insulation resistance shall meet the minimum requirements shown in Table 3-20 (at 500 volts DC). Non-component
flush printed boards shall have a minimum requirement of 50 MΩ for all classes. Insulation resistance requirements
in the as-received condition are detailed in special requirement section (see 3.10.9).
Table 3-19 Insulation Resistance
Class 1
Class 2
Class 3
As received
Maintain
electrical
function
500 MΩ
500 MΩ
After
exposure to
moisture
Maintain
electrical
function
100 MΩ
500 MΩ
The moisture and insulation resistance for printed boards shall be performed in accordance with IPC-TM-650,
Method 2.6.3. When Test Method A within IPC-TM-650, Method 2.6.3 is required per the procurement
documentation, conformal coating in accordance with IPC-CC-830 shall be applied to the external conductors prior
to chamber exposure. Final measurements shall be made at room temperature within two hours after removal from
the test chamber. All layers have a 100 ± 10 volts DC polarizing voltage applied during chamber exposure. Mealing
of the conformal coating shall not extend more than 3 mm [0.12 in] from the edge of the test coupon or production
printed board.
3.8.4.1 Dielectric Withstanding Voltage After MIR A dielectric withstanding voltage test shall be performed after
moisture and insulation resistance in accordance with 3.8.1.
3.9 Cleanliness Type 4 and Type 5 flexible printed boards requiring permanent solder mask coating shall be tested
and evaluated in accordance with 3.10.11.
3.9.1 Cleanliness Prior to Solder Mask Application When a printed board requires a permanent solder mask
coating, the uncoated boards shall be within the allowable limits of ionic and other contaminants prior to the
application of solder mask coating. When noncoated printed boards are tested per 3.9, the contamination level shall
not be greater than 1.56 µg/cm2 of sodium chloride equivalence.
3.9.2 Cleanliness After Solder Mask, Solder, or Alternative Surface Coating Application When specified,
printed boards shall be tested per 3.9 and meet the requirements in the procurement documentation.
3.9.3 Cleanliness of Inner Layers After Oxide Treatment Prior to Lamination When specified, inner layers shall
be tested per 3.9 and meet the requirements of the procurement documentation.
3.10 Special Requirements When specified on the procurement documentation, some or all of the special requirements listed in this section (3.10) shall apply. A notation in the procurement documentation will designate which are
required.
3.10.1 Outgassing When specified, flexible printed boards shall be tested in accordance with the procedure outlined below. The degree of outgassing shall not result in a Total Mass Loss (TML) of more than 1.0% and Collectible
Volatile Condensable Material (CVCM) of less than one tenth of one percent (0.1%). Mass loss shall be
determined on test coupons or production printed boards of representative substrates when tested in accordance
with IPC-TM-650, Method 2.6.4. In lieu of testing, outgassing data from a NASA or OEM database shall be acceptable.
3.10.2 Organic Contamination Noncoated printed boards shall be tested in accordance with the procedure
outlined below. Any visual evidence of organic residue shall constitute a failure.
The printed board shall be tested in accordance with IPC-TM-650, Methods 2.3.38 or 2.3.39. The first is a
qualitative method in which very pure acetonitrile is dripped across the test coupon or production printed board and
collected on a microscope slide. It is dried and compared with a slide having dried, uncontaminated acetonitrile on it
for visual evidence of organic residue. If evidence of organic contamination is detected by this test, Method 2.3.39 is
used to determine the nature of the contaminant by the use of infrared spectrophotometric analysis using the
Multiple Internal Reflectance (MIR) method.
3.10.3 Fungus Resistance Completed printed boards or representative wiring sections from the lot shall not
support fungus growth when tested in accordance with IPC-TM-650, Method 2.6.1.
3.10.4 Vibration The test coupon or production printed board shall pass the circuitry test in 3.8.2 following the
vibration test procedure below and shall not exhibit bow or twist in excess of that allowed in 3.4.3 following testing.
The printed boards shall be subjected to both a cycling and resonance dwell test with the flat surface of the board
mounted perpendicular to the axis of vibration in accordance with IPC-TM-650, Method 2.6.9.
Cycling Test – The cycling test shall consist of one sweep from 20 to 2000 Hz performed in 16 minutes. Input
acceleration over the 20 to 2000 Hz frequency range shall be maintained to 15 Gs.
Resonance Dwell – Test coupons or production printed boards shall be subjected to a 30 minute resonance dwell
with 25 Gs input or a maximum of 100 Gs output measured at the geometric center of the test coupon or production
printed board. The test coupons or production printed boards shall be restrained from movement by fixturing on all
four sides.
3.10.5 Mechanical Shock The test printed boards shall pass the circuitry test in 3.8.2 after being subjected to
mechanical shock testing as follows.
The mechanical shock test shall be performed in accordance with IPC-TM-650, Method 2.6.5. The printed boards
shall be subjected three times to a shock pulse of 100 Gs with a duration of 6.5 milliseconds in each of the three
principal planes. The test coupons or production printed boards shall be restrained from movement by fixturing on
all four edges.
3.10.6 Impedance Testing Requirements for impedance shall be specified on the procurement documentation.
Impedance testing may be performed on a test coupon or a designated circuit in the production wiring. Time domain
reflectometers (TDR) are used for electrical testing, but for large impedance tolerances (± 10%), mechanical
measurements from a microsection utilizing a special test coupon can be used to calculate and verify impedance
values. See IPC-2251 for the equations for calculating impedance from the test coupon and IPC-TM-650, Method
2.5.5.7, for the methodology using the TDR technique.
3.10.7 Coefficient of Thermal Expansion (CTE) When boards that have metal cores or reinforcements with a
requirement to constrain the thermal expansion in the planar directions, the Coefficient of Thermal Expansion shall
be within ± 2 ppm/°C for the CTE and temperature range specified on the procurement documentation. Testing shall
be by the strain gauge method in accordance with IPC-TM-650, Method 2.4.41.2. Testing of boards less than 1.5
mm [0.060 in] thick and other methods of determining the CTE shall be AABUS.
3.10.8 Thermal Shock When specified on the procurement documentation, flexible printed boards or test coupons
shall be tested in accordance with the procedure outlined below.
The specimen shall be tested for thermal shock in accordance with IPC-TM-650, Method 2.6.7.2, except the temperature range shall be -65 +125 °C [-85 to 257 °F]. Microsection evaluation in accordance with IPC-TM-650,
Method 2.6.7.2, is not required. Following removal from the test chamber, the specimen shall meet the circuitry
requirements of 3.8.2. The resistance value shall not vary by more than ± 10%.
3.10.9 Surface Insulation Resistance (As Received) Test coupons shall be tested in accordance with the procedure outlined below. The insulation resistance shall be no less than that shown in Table 3-19.
Test coupons or production boards should be conditioned at 50 ± 5 °C [122 ± 9 °F] with no added humidity for a
period of 24 hours. After cooling, the insulation resistance test shall be performed in accordance with the ambient
temperature measurements specified in IPC-TM-650, Method 2.6.3.
3.10.10 Metal Core (Horizontal Microsection) When specified, metal core printed boards which have clearance
between the plated-through holes and the metal core shall require a horizontal microsection prepared to view the
metal core/hole fill insulation. Test coupons or production boards shall have been subjected to thermal stress in
accordance with 3.6.1 prior to microsectioning. Wicking, radial cracks, lateral spacing or voids in the hole-fill
insulation material shall not reduce the electrical spacing between adjacent conductive surfaces to less than 100 µm
[3,937 µin]. Wicking and/or radial cracks shall not exceed 75 µm [2,953 µin] from the plated-through hole edge into
the hole-fill.
3.10.11 Ionic (Resistivity of Solvent Extract) When specified, printed boards or test coupons shall be tested for
ionic contamination in accordance with IPC-TM-650, Method 2.3.25, paragraph 4 Resistance of Solvent Extract
Method. When flexible printed boards are tested per this section, the contamination level shall not be greater than
an equivalent of 1.56 µg/cm2 of sodium chloride.
Equivalent test methods may be used in lieu of the method specified; however, it shall be demonstrated to have
equal or better sensitivity and employ solvents with the ability to dissolve flux residue or other contaminants as does
the solution presently specified.
3.10.12 Rework Simulation
3.10.12.1 Through Hole Components When specified, printed boards or test coupons shall be tested in
accordance with IPC-TM-650, Method 2.4.36 and then microsectioned and examined in accordance with 3.6. Lifted
lands are allowed.
3.10.12.2 Surface Mount Components When specified, 100% surface mount printed boards shall be tested in
accordance with the procurement documentation.
3.10.13 Bending Test The bending test shall conform to Figure 3-34, unless otherwise agreed to by the user. The
bending test requirements shall be as specified on the appropriate document/drawing. See IPC-2223 for guidance
on minimum bend radii. The following parameters shall be specified as a minimum:
Direction of bend (a)
Degree of bend (b)
Number of bend cycles (c)
Diameter of mandrel (d)
Points of application to be specified by user
Bend cycle is defined as taking one end of the specimen and bending it around a mandrel and then bending back to
the original starting position, traveling 180° in one direction and 180° in the opposite direction. A bend cycle may
also be defined as bending (using opposite ends) the ends toward each other (bend the same direction) and then
bending them back to the original starting position, with each end traveling 90° in one direction and 90° in the
opposite direction.
Figure 3-34 Bending Test
The specified number of bend cycles shall be performed with the mandrel placed in contact with the specimen on
one side and then again with the mandrel placed in contact with the specimen on the opposite side. After completion
of the bending test in both directions, the flexible or rigid-flexible printed board shall be tested for electrical defects in
accordance with 3.8 and shall meet the requirements of 3.3.
3.10.14 Flexible Endurance Flexible endurance testing shall be carried out using IPC-TM-650, Method 2.4.3.1; as
an alternate, IPC-TM-650, Method 2.4.3 may be used. Flexible endurance testing can also be accomplished with
special test equipment specific to the circuit application. The outline length of the coupon may be deviated from in
order to accommodate the test method fixture and circuit design. Accordingly, the final configuration of the coupon
should be determined with regard for the end product application and by user/supplier agreement.
The flexibility endurance test requirements shall be specified in the appropriate document/drawing. The following
parameters shall be specified as a minimum:





Number of flex cycles
Diameter of the bend mandrels or separation of the loop-defining plates
Flexing rate
Points of application
Travel of loop
The method for determining end of life is an electrical discontinuity during monitoring, or passing the predetermined
number of flex cycles without electrical discontinuity.
3.10.15 Bond Strength (Unsupported Lands) When flexible printed boards are tested in accordance with
IPC-TM-650, Method 2.4.20, the unsupported land shall withstand 1.86 kg pull or 35 kg/cm2 [498 PSI], whichever is
less, after subjection to five cycles of soldering and unsoldering. Calculations of land area of the unsupported hole
do not include the area occupied by the hole.
3.10.16 Bond Strength (Stiffener) Using a sharp instrument (i.e., scalpel or razor blade), cut a pattern approximately 13 mm [0.512 in] wide by 76 mm [2.99 in] long through the flexible printed board to the stiffener so that
approximately half way through the peeling operation the sample will be perpendicular to the pull.
Pull the flexible printed board at a rate of 57 mm/minute [2.24 in/minute]. Take readings at the beginning, middle,
and end of the pull and average these readings to determine acceptability. The peel strength between the flexible
printed board and the stiffener shall be a minimum of 1.4 kg per 25 mm [0.984 in] width when bonded with
thermoset adhesive and 0.38 kg per 25 mm [0.984 in] width when bonded with pressure sensitive adhesive.
3.10.17 Destructive Physical Analysis Lot acceptance shall require the destructive physical analysis (DPA) of a
representative printed board per lot. The DPA printed board shall be selected from a single common inspection lot
from a panel that has previously passed acceptance testing for structural integrity after stress in accordance with
Table 4-3. Each DPA printed board shall be thermally stressed, microsectioned and inspected in accordance with
3.6. DPA microsections shall include a minimum of three holes of each applicable PTH and via structure, including
blind and buried, found on the finished printed board. Disposition of lots where DPA has failed shall be AABUS.
3.11 Repair Repair of bare flexible printed boards shall be AABUS for each set of procurement documentation (see
IPC-7711/21A).
3.11.1 Circuit Repair Allowance of circuit repairs on Class 1, Class 2, and Class 3 flexible printed boards shall be
AABUS. As a guideline, there should be no more than two circuit repairs for each 0.09 m2 [0.969 ft2] or less of layer
area per side. Circuit repairs on any impedance-controlled circuits shall not violate the impedance requirement and
shall have the agreement of the user. Circuit repairs shall not violate the minimum electrical spacing requirements.
3.12 Rework Rework is permitted for all classes. The touch-up of surface imperfections in the base material or
removal of residual plating materials or extraneous copper will be permitted for all products when such action does
not affect the functional integrity of the printed board.
4 QUALITY ASSURANCE PROVISIONS
4.1 General General Quality Assurance Provisions are specified in IPC-6011 and each sectional specification. The
requirements specific to flexible printed boards are contained in this specification and include the Qualification
Testing, Acceptance Testing and Frequency of Quality Conformance Testing.
4.1.1 Qualification Qualification is AABUS (see IPC-6011). The qualification should consist of capability analysis
assessments (see IPC-9151), pre-production samples, production sample, or test coupons (see IPC-6011) that are
produced by the same equipment and procedures planned for the production printed boards. Qualification should
include those applicable tests as referenced in Table 4-3 and Table 4-4. Qualification as agreed by the user may
consist of documentation that supplier has furnished similar product to other users or to other similar specifications.
4.1.2 Sample Test Coupons If test coupons are used in lieu of actual production lots, the following information is
provided based on previous use of standardized test coupons. Sample test coupons may be used for qualification or
for ongoing process control. Master drawings, databases, or artwork are available from IPC. For each type (see
1.3.2) the master drawing and artwork is listed as follows:
Type 1 Master Drawing IPC-100041 within IPC-A-41 artwork.
Note: IPC-100001 is the universal drilling and profile master drawing.
Table 4-1 specifies test coupons A through H from IPC-A-41, IPC-A-42, and IPC-A-43 to be used from the test
specimen for qualification and process capability evaluations. Equivalent production printed board coupon
descriptions can be found in IPC-2221.
4.2 Acceptance Testing and Frequency Acceptance testing and frequency shall be performed as specified in
Table 4-3 to the requirements of this specification and IPC-6011 using either quality conformance coupons and/or
production printed boards. The quality conformance test coupons are described in IPC-2221 which indicates the
purpose of the coupon and its frequency on a manufacturing panel. When ‘‘Sample’’ is indicated in Table 4-3, use
the C=0 Zero Acceptance Number Sampling Plan specified in Table 4-2.
4.2.1 C=0 Zero Acceptance Number Sampling Plan The C=0 Zero Acceptance Number Sampling Plan shall be in
accordance with the requirements of ASQ H1331. The C=0 Zero Acceptance Number Sampling Plan provides
greater or equal protection for the Lot Tolerance Percent Defective (L.T.P.D.) protection at the 0.10 ‘‘consumer risk’’
level. The Index Values at the top of each sample size column associates to the A.Q.L. level. For a lot to be
accepted, all samples (shown in Table 4-2) shall conform to the requirements. Disposition of rejected lots shall be
fully documented.
4.2.2 Referee Tests Two additional microsection sets from the same panel may be prepared and evaluated for
microsection defects that are considered to be isolated, random in nature, or caused by microsection preparation.
For acceptance, both referee sets must be defect free.
4.3 Quality Conformance Testing Quality Conformance Testing shall be performed and consist of inspections
specified in Table 4-4 in a facility which meets the requirements of IPC-QL-653, unless otherwise specified by the
user. Class 3 testing results may be extended to reliability test and evaluation for Class 2.
4.3.1 Coupon Selection Two sets of test coupons of the most complex pattern of each type of material processed
during the inspection period shall be selected from lots that have passed acceptance testing.
Table 4-1 Qualification Testing
TEST
Visual Examination
Profile
Requirement
Paragraph
TYPE 1 & 5
TYPE 2
TYPE 3 & 4
3.3
3.3.1
Entire Board
Entire Board
Entire Board
Edges, Rigid Section
3.3.1.1
Entire Board
Entire Board
Entire Board
Edges, Flexible Section
3.3.1.2
Entire Board
Entire Board
Entire Board
Transition Zone, Rigid Area to Flexible Area
3.3.1.3
Entire Board
Entire Board
Entire Board
3.3.2
Entire Board
Entire Board
Entire Board
Construction Imperfections
Haloing
3.3.1.1
Entire Board
Entire Board
Entire Board
Measling
3.3.2.1
Entire Board
Entire Board
Entire Board
Crazing
3.3.2.2
Entire Board
Entire Board
Entire Board
Foreign Inclusions
3.3.2.4
Entire Board
Entire Board
Entire Board
Weave Exposure
3.3.2.5
Entire Board
Entire Board
Entire Board
Scratches, Dents, & Tool Marks
3.3.2.6
Entire Board
Entire Board
Entire Board
Surface Microvoids
3.3.2.7
Entire Board
Entire Board
Entire Board
Color Variations in Bond Enhancement Treatment
3.3.2.8
Entire Board
Entire Board
Entire Board
Pink Ring
3.3.2.9
N/A
N/A
N/A
Coverfilm Separations
3.3.2.10
Entire Board
Entire Board
Entire Board
TEST
Covercoat Requirements
Requirement
Paragraph
3.3.2.11
TYPE 1 & 5
Entire Board
TYPE 2
Entire Board
TYPE 3 & 4
Entire Board
Covercoat Coverage
3.3.2.11.1
Entire Board
Entire Board
Entire Board
Covercoat Cure & Adhesion
3.3.2.11.2
Entire Board
Entire Board
Entire Board
Covercoat Thickness
3.3.2.11.3
Entire Board
Entire Board
Entire Board
Solder Wicking/Plating Penetration
3.3.2.12
Entire Board
Entire Board
Entire Board
Stiffener
3.3.2.13
Entire Board
Entire Board
Entire Board
Plating & Coating Voids in the Hole
3.3.3
N/A
Entire Board
Entire Board
Lifted Lands
3.3.4
Entire Board
Entire Board
Entire Board
Marking
3.3.5
Entire Board
Entire Board
Entire Board
Solderability
3.3.6
A, B, A/B, C
A, B, A/B, C
A, B, A/B, C
Plating Adhesion
3.3.7
C
C
C
Edge Board Contact, Junction of Gold Plate to Solder Finish
3.3.8
Only as Required
Only as Required
Only as Required
Workmanship
3.3.9
Entire Board
Entire Board
Entire Board
Entire Board
Entire Board
Entire Board
Dimensional Requirements
Hole Size & Hole Pattern Accuracy
Etched Annular Ring (External)
3.4
3.4.1
3.4.2
Entire Board
Entire Board
Entire Board
Solderable Annular Ring (External)
3.4.2.1
Entire Board
Entire Board
Entire Board
Squeeze-out of Adhesive of Coverlayer & Ooze-out of Cover
Coat
3.4.2.2
Entire Board
Entire Board
Entire Board
Stiffener Access Hole
3.4.2.3
Entire Board
Entire Board
Entire Board
3.4.3
Entire Board
Entire Board
Entire Board
Bow & Twist (Individual Rigid or Stiffener Portions Only)
Conductor Definition
3.5
Conductor Imperfections
3.5.1
Entire Board
Entire Board
Entire Board
Conductor Spacing
3.5.2
Entire Board
Entire Board
Entire Board
3.5.3
Entire Board
Entire Board
Entire Board
Conductor Width Reduction
3.5.3.1
Entire Board
Entire Board
Entire Board
Conductor Thickness Reduction
3.5.3.2
Entire Board
Entire Board
Entire Board
3.5.4
Entire Board
Entire Board
Entire Board
3.5.4.1
Entire Board
Entire Board
Entire Board
Conductor Surfaces
Nicks & Pinholes in Ground or Voltage Planes
Surface Mount Lands (Rectangular)
3.5.4.2.1
Entire Board
Entire Board
Entire Board
Surface Mount Lands (Round)
3.5.4.2.2
Entire Board
Entire Board
Entire Board
Wire Bond Bads
3.5.4.3
Entire Board
Entire Board
Entire Board
Edge Connector Lands
3.5.4.4
Entire Board
Entire Board
Entire Board
Dewetting
3.5.4.5
Entire Board
Entire Board
Entire Board
Nonwetting
3.5.4.6
Entire Board
Entire Board
Entire Board
Final Finish Coverage
3.5.4.7
Entire Board
Entire Board
Entire Board
Conductor Edge Outgrowth
3.5.4.8
Entire Board
Entire Board
Entire Board
Structural Integrity
3.6
Thermal Stress Testing
3.6.1
A, B, or A/B
A A, B, or A/B
A, B, or A/B
Requirements for Microsectioned Coupons
3.6.2
A, B, or A/B
A, B, or A/B
A, B, or A/B
Plating Integrity
3.6.2.1
N/A
A, B, or A/B
A, B, or A/B
Plating Voids
3.6.2.2
N/A
A, B, or A/B
A, B, or A/B
Laminate Integrity (Flexible)
3.6.2.3
A, B, or A/B
A, B, or A/B
A, B, or A/B
Laminate Integrity (Rigid)
3.6.2.4
A, B, or A/B
A, B, or A/B
A, B, or A/B
Delamination or Blistering
3.6.2.5
A, B, or A/B
A, B, or A/B
A, B, or A/B
Etchback
3.6.2.6
N/A
N/A
A, B, or A/B
Smear Removal
3.6.2.7
N/A
N/A
A, B, or A/B
Negative Etchback
3.6.2.8
N/A
N/A
A, B, or A/B
Wicking (Copper Plating)
3.6.2.9
N/A
N/A
A, B, or A/B
Annular Ring (Internal)
3.6.2.10
N/A
N/A
A, B, or A/B
Plating/Coating Thickness
3.6.2.12
A, B, or A/B
A, B, or A/B
A, B, or A/B
Requirement
Paragraph
TEST
Minimum Layer Copper Foil Thickness
3.6.2.13
TYPE 1 & 5
A, B, or A/B
TYPE 2
A, B, or A/B
TYPE 3 & 4
A, B, or A/B
Minimum Surface Conductor Thickness
3.6.2.14
A, B, or A/B
A, B, or A/B
A, B, or A/B
Metal Cores
3.6.2.15
A, B, or A/B
N/A
A, B, or A/B
Dielectric Thickness
3.6.2.16
A, B, or A/B
A, B, or A/B
A, B, or A/B
Material Fill of Blind Buried Vias
3.6.2.17
A, B, or A/B
A, B, or A/B
A, B, or A/B
Electrical Requirements
3.8
Dielectric Withstanding Voltage
3.8.1
E
E
E
Circuitry
3.8.2
D, H
D, H
D, H
Continuity
3.8.2.1
D, H
D, H
D, H
Isolation Resistance(Circuit Shorts)
3.8.2.2
D, H
D, H
D, H
Circuit/Plated-Through Hole Shorts to Metal Substrates
3.8.3
Only as Required
Only as Required
Only as Required
Moisture & Insulation Resistance
3.8.4
E
E
E
Cleanliness
3.9
Entire Board
Entire Board
Entire Board
Special Requirements
3.10
Only as Required
Only as Required
Only as Required
Outgassing
3.10.1
Organic Contamination
3.10.2
Only as Required
Only as Required
Only as Required
Fungus Resistance
3.10.3
Only as Required
Only as Required
Only as Required
Impedance Testing
3.10.6
Only as Required
Only as Required
Only as Required
Coefficient of Thermal Expansion (CTE)
3.10.7
Only as Required
Only as Required
Only as Required
Thermal Shock
3.10.8
D
D
D
Surface Insulation Resistance (As Received)
3.10.9
E
E
E
Ionic (Resistivity of Solvent Extract)
3.10.11
Entire Board
Entire Board
Entire Board
Rework Simulation
3.10.12
N/A
A, B, or A/B
A, B, or A/B
Bending Flexibility
3.10.13
H
H
H
Flexible Endurance
3.10.14
H
H
H
Bond Strength (Unsupported Lands)
3.10.15
A, B, or A/B
A, B, or A/B
A, B, or A/B
Bond Strength (Stiffener)
3.10.16
Only as Required
Only as Required
Only as Required
Repair
Circuit Repair
3.11
Only as Required
Only as Required
Only as Required
3.11.1
Only as Required
Only as Required
Only as Required
3.12
Only as Required
Only as Required
Only as Required
Rework
Table 4-2 C=0 Sampling Plan for Equipment Classes per Lot Size
Lot Size
Class 1
1
2.5
1
4.0
Class 2
1
6.5
1
1
2.5
Class 3
1
4.0
1
1
1.0
**
2.51
4.01
1-8
5
3
2
1.5
**
5
3
0.10
**
5
3
9-15
5
3
2
8
5
3
**
13
5
3
16-25
5
3
3
8
5
3
**
13
5
3
26-50
5
5
5
8
5
5
**
13
5
5
51-90
7
6
5
8
7
6
**
13
7
6
91-150
11
7
6
12
11
7
125
13
11
7
151-280
13
10
7
19
13
10
125
20
13
10
281-500
16
11
9
21
16
11
125
29
16
11
501-1,200
19
15
11
27
19
15
125
34
19
15
1,201-3,200
23
18
13
35
23
18
192
42
23
18
3,201-10,000
29
22
15
38
29
22
294
50
29
22
10,001-35,000
35
29
15
46
35
29
345
60
35
29
Note 1. Index Value is associated to the A.Q.L. value. If a particular product is determined to be ‘‘critical’’ by the user and a smaller index value
is required, the user shall designate the requirement in the procurement document and should state the ‘‘critical’’ requirement on the master
drawing.
**Denotes inspect entire lot.
Table 4-3 Acceptance Testing and Frequency
Sample
Inspection
Material
Requirement
and Method Production
Section
Board
Test Frequency
Test
Coupon
By Board
Class 1
3.2.1 -3.2.14
1
Class 2
1
Class 3
1
Manufacturer’s Certification
Remarks
Verifiable
Certificate of
Compliance or
SPC Program
VISUAL
3.3.1.1
X
Sample (4.0)
Sample (2.5)
Sample (2.5)
Per Board
Edges, Flex Section
3.3.1.2
3.3.1.3
X
Sample (4.0)
Sample (4.0)
Sample (2.5)
Sample (2.5)
Sample (2.5)
Sample (2.5)
Per Board
Sample (4.0)
Sample (2.5)
Sample (2.5)
Transition Zone, Rigid Area
to Flex Are
Construction Imperfection
3.3.2
X
X
3.3.3
Plating and Coating Voids in
Hole
Marking and Traceability
X
3.3.5
X
(Retained
Coupons)
Sample (4.0)
Sample (2.5)
Sample (1.0)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Board
Per Board
Per Panel
Applicable
to Types 2, 3
& 4 Only
Per Board
Edge Board Contact,
Junction of Gold Plate to
Solder Finish
3.3.8
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per Panel
Lifted Lands
3.3.4
X
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Board
Workmanship
3.3.9
X
Plating Adhesion
Covercoat Cure and
Adhesion
Solder mask cure and
adhesion
Cleanliness
3.3.7
X
C
X
G
3.7.2
X
G
3.9
X
3.3.2.11.2
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Board
PHYSICAL
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per panel (1
coupon)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per panel (1
coupon)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per panel
(1 coupon)
N/A
N/A
Sample (4.0)
Per lot
Sample (2.5)
Sample (2.5)
Sample (2.5)
Sample (2.5)
Per Panel
SOLDERABILITY
Surface
7
Hole
Dimensional: Flexible
Printed Board
3.3.6
3.3.6
3.4
Hole Size and Hole Pattern
Accuracy
3.4.1
Etched Annular Ring
(External)
3.4.2
(External)
Bow and Twist (Individual
Board or Stiffener Portion
Only)
Conductor Imperfection
M
X
Sample (4.0)
Sample (4.0)
A/B
or S
DIMENSIONAL REQUIREMENTS
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Panel
Per Board
Sample (6.5)
Sample (4.0)
Sample (4.0)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Board
CONDUCTOR DEFINITION (INTERNAL AND EXTERNAL LAYERS)
3.5
Sample (6.5)
Sample (4.0)
Sample (2.5)
X
Per Board
3.4.2.1
3.4.3
X
X
X
X
Per Board
Per Board
Per Board
3.5.3.1
3.5.3.2
Conductor Thickness
Reduction
Conductor Spacing
X
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per Board
Per Board
3.5.2
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per Board
Nicks or Pinholes in Ground
or
Voltage Planes
3.5.4.1
X
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per Board
Surface Mount Lands
3.5.4.2
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Minimum 10
evaluations per
panel
Dewetting/Nonwetting/ Final
Finish Coverage
3.5.4.4
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per Board
3.5.4.5
3.5.4.6
3.5.4.7
X
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per Board
Sample (6.5)
Sample (4.0)
Sample (2.5)
3.5.4.8
X
Per Board
6
STRUCTURAL INTEGRITY AFTER STRESS TYPES 3-4 (MICROSECTION)
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
3.6.2.3
3.6.2.4
A/B
3.6.2.6
Sample (2.5)
Sample (1.5)
Sample (0.1)
3.6.3.7
Flexible and Rigid Laminate
Integrity
Etchback, Smear Removal
and Negative Etchback
(Type 3 and Type 4 Only)
3.6.2.1
3.6.2.9
Plating Integrity and Wicking
Plating Voids
3.6.2.2
Per panel
5
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per Panel
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (2.5)
Sample (1.5)
Sample (0.1)
Per panel
5
A/B
Sample (6.5)
Sample (4.0)
Sample (4.0)
Per panel
5
2 A/B
Annular Ring and Breakout
(Internal)
3.6.2.10
3.6.2.10.1
3.6.2.12
Minimum Layer/Copper Foil
Thickness
3.6.2.13
Thickness
3.6.2.14
Metal Cores
3.6.2.15
3.6.2.16
Material Fill of Buried Vias
3.6.2.17
STRUCTURAL INTEGRITY AFTER STRESS TYPE 2 (MICROSECTION)
Sample (6.5)
Sample (4.0)
Sample (2.5)
A/B
3.6.2.3
3,5
6
Plating Integrity
Plating Voids
3.6.2.1
3.6.2.2
3.6.2.12
Thickness
3.6.2.14
3.6.2.16
A/B
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per panel
A/B
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per panel
A/B
Sample (6.5)
Sample (4.0)
Sample (2.5)
A/B
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per panel
A/B
Sample (6.5)
Sample (4.0)
Sample (2.5)
Per panel
ELECTRICAL REQUIREMENTS
Continuity
Isolation Resistance
SPECIAL REQUIREMENTS
3.8.2.1
3.8.2.2
X
X
Per panel
Sample (2.5)
2
Sample (2.5)
2
2
100%
2
100%
100%
100%
2
2
Per panel
4
Dielectric Withstand Voltage
3.8.1
Circuits/Plated-Through
Hole Shorts to Metal
Substrates
3.8.3
Insulation Resistance (As
Received
3.10.9
Moisture Insulation
Resistance
3.8.4
Thermal Shock
3.10.8
Ionic (Resistivity of Solvent
Extract)
3.10.11
3.10.2
Fungus Resistance
3.10.3
Outgassing
3.10.1
Impedance Testing
3.10.6
Repair
X
Only Applicable When Imposed by Contract
3.11
Circuit Repair
3.11.1
Rework
3.12
3.10.7
Coefficient of Thermal
Expansion (CTE
Note 1. Numbers in parentheses are the AQL level.
Note 2. For Type 1 and Type 2 flexible printed boards, visual or AOI inspection may be used in lieu of electrical testing.
Note 3. For Class 2 product, the degree of breakout following evaluation of vertical cross sections may be assessed by methods other than
horizontal microsection.
Note 4. Measurement location must be larger than collimated source.
Note 5. For each manufacturing panel, when utilizing the A/B coupon design, the two A/B coupons shall be selected from opposite corners of
the panel and evaluated in opposing axes (one in the “Y” axis and the other in the “X” axis). Structural integrity sample can be used as ½ of the
registration pair.
Note 6. All via structures shall be represented in the thermally stressed evaluations.
Note 7. Hole solderability testing not required for Type 2 double-sided printed boards without plated-through holes. The A coupon is
considered inactive for new designs. Usage of the “A” coupon for hold solderability testing shall be AABUS.
Table 4-4 Quality Conformance Testing
Inspection
Rework Simulation
Bond Strength
(Unsupported Lands)
Dielectric Withstanding
Voltage
Moisture and Insulation
Resistance
Requirement
and Method
Section
3.10.12
Test Coupon
Test Frequency
Type 1, 5
Type 2 - 4
B or A/B
Class 1
Not required
3.10.15
B or A/B
As required
Not required
3.10.16
3.8.1
Board
E
Board
E
Not required
Not required
3.8.4
E
E
Not required
Class 2
Two coupons
per QTR
Two coupons
per QTR
AABUS
Two coupons
per QTR
Two coupons
per QTR
Class 3
Two coupons
per month
Two coupons
per month
AABUS
Two coupons
per month
Two coupons
per month
5 NOTES
5.1 Ordering Data The procurement documentation should specify the following:
a.
Title, number, issue, revision letter, and date of current applicable master drawing.
b.
Specific exceptions, variations, additions or conditions to this specification that are required by the user.
c.
Part Identification and Marking instructions.
d.
Information for preparation for delivery, if applicable.
e.
Special tests required and frequency.
5.2 Superseded Specifications This specification supersedes and replaces IPC-6013B.
APPENDIX A
Appendix A presents the performance requirements of IPC-6013C in an abbreviated form and alphabetical order.
Special conditions, lengthy requirements, and tutorial information may be shortened or partially omitted in this
appendix. See the referenced paragraph in this appendix for the full specification requirements.
Requirement
Requirement
Class 1
Class 2
Class 3
Characteristic Inspection
Paragraph
The
minimum
annular
ring
3.4.2 and
Etched Annular Ring (External
Not greater than 180°
Table 3-7
Plated-Through Holes)
breakout of hole from land breakout of hole from land shall be 50 µm [1,968
µin].
when visually assessed. when visually assessed
and a 50 µm
[1,970 µin] annular ring for
at least 270° of the
circumference.
Etched Annular Ring (External
The minimum annular ring 3.4.2 and
Table 3-7
Unsupported Holes)
breakout of hole from land breakout of hole from land shall be 150 µm [5,906
µin
].
when visually assessed. when visually assessed.
Etched Annular Ring (Internal
Plated-Through Holes)
Bending Test
Hole breakout is allowed
90 ° hole breakout is The minimum annular ring
provided the land/
allowed provided the land/ shall be 25 µm [984 µin].
conductor junction is not conductor junction is not
reduced below the allow- reduced below the allowable width reduction in
able width reduction in
3.5.3.1.
3.5.3.1.
As specified in appropriate document/drawing.
Peel strength between the flexible printed board and the stiffener shall be
≥1 .4 kg per 25 mm [0.984 in] width.
Bond Strength (Unsupported As per IPC-TM-650, Method 2.4.20, unsupported land shall withstand 1.86 kg
Lands)
pull or 35 kg/cm2 [498 PSI], whichever is less, after subjection to five cycles of
soldering and unsoldering.
Bow & Twist (Individual Rigid or Surface applications: 0.75% bow & twist (or determined by user and supplier).
Stiffener Portion Only)
All other applications: 1.5% bow & twist (or determined by user and supplier).
Characteristic Inspection for
Material
2
2
Circuit Repair
No more than two repairs for each 0.09 m [0.969 ft ]; no impedance or
minuimum electrical spacing req. violated.
Circuitry
Testing conducted in accordance with IPC-9252.
Circuits/Plated-Through Hole Metal core flexible printed board shall withstand 500 volts DC between
Shorts to Metal Substrates
circuitry/ plated-through holes and metal core substrates w/o flashover or
dielectric breakdown.
Cleanliness
Type 4 & Type 5 flexible printed boards shall be tested and evaluated in
accordance with 3.10.11.
Coefficient of Thermal
If have metal cores/reinforcements with a req. to constrain thermal expansion in
Expansion
planar directions, CTE shall be within ± 2 ppm/ °C for CTE & temp range spec
on master drawing; testing w/ strain gauge method, according to IPC-TM-650,
Method 2.4.41.2 unless AABUS.
Color Variations in Bond
Mottled appearance/color variation accept; Random missing areas of treatment
shall not be >10%.
Enhancement Treatment
Conductor Definition
Meet visual & dimension req., pattern & thickness as specified in procurement
documentation.
No outgrowth on edges of conductors that have been solder coated or electrodeposited tin-lead plated and fused when tested according to IPC-TM-650,
Method 2.4.1.
Cross-sectional area of Cross-sectional area of conductor not reduced >20%
conductor not reduced
of minimum value; total defect not >10% of conductor
>30% of minimum value. or 13.0 mm [0.512 in] (whichever is less).
No cracks, splits or tears.
3.4.2 and
Table 3-7
3.10.13
3.10.16
3.10.15
3.4.3
3.2
3.11.1
3.8.2
3.8.3
3.9
3.10.7
3.3.2.8
3.5
3.5.4.8
3.5.3
Conductor Spacing
Conductive Surfaces
Conductor Thickness
Reduction
Construction Imperfections
Continuity
Covercoat Coverage
spikes, etc.
Minimum conductor
spacing may be reduced
an additional 20% due to
conductor roughness,
spikes, etc.
Reduction of conductor Reduction of conductor thickness not > 20% of
minimum.
thickness not > 30% of
minimum.
Reduction of conductor Reduction of conductor width not > 20% of minimum.
width not > 30% of minimum
Measling, crazing, blistering and delamination.
No circuits with resistance > the values established in the procurement
documentation; current passed through for evaluation will not be > values in
IPC-2221 for smallest conductor of circuit.
Conductors not exposed where covercoat required.
Blistering does not bridge Two per side, max size 0.25 mm [0.00984 in] in long
between conductors.
est dim, spacing between conductors not reduced by
more than 25%.
Covercoat Cure and Adhesion Max % loss allowed:
Bare Copper - 10
Gold or Nickel - 25
Base Laminate - 10
Melting Metals - 50
Max % loss allowed:
Bare Copper - 5
Gold or Nickel - 10
Base Laminate - 5
Melting Metals - 25
Max % loss allowed:
Bare Copper - 0
Gold or Nickel - 5
Base Laminate - 0
Melting Metals -10
3.5.2
3.5.4
3.5.3.2
3.5.3.1
3.3.2
3.8.2.1
3.3.2.11.1
3.3.2.11.2
Covercoat Requirements
See 3.3.2.11.1 through 3.3.2.11.3.
Covercoat Thickness
Coverfilm Separations
Not measured unless required by procurement documentation.
Uniform coverfilm, free of separations. Nonlamination good if according to
3.3.2.4, not > 0.80 x 0.80 mm [0.0315 x 0.0315 in], not > 3 in 25 x 25 mm [0.984
x 0.984 in] space, not > 25% of spacing between conductors.
3.3.2.11.3
3.3.2.10
Crazing
Imperfection does not reduce the conductor spacing below the minimum and
there is no propagation of the imperfection as a result of thermal testing that
replicates the manufacturing process. For Class 2 and Class 3, the distance of
crazing shall not span more than 50% of the distance between adjacent
conductors.
3.3.2.2
Delamination/Blistering
Acceptable for all classes of end product provided the area affected by
imperfections does not exceed 1% of the board area on each side and does not
reduce the spacing between conductive patterns below the minimum conductor
spacing. There shall be no propagation of imperfections as a result of thermal
testing that replicates the manufacturing process. For Class 2 and Class 3, the
blister or delamination shall not span more than 25% of the distance between
adjacent conductive patterns.
Solder connection: 15% Solder connection: 5%
3.3.2.3
Dewetting
Dielectric Withstand Voltage
Dimensional Requirements
Edge Board Contact, Junction
of Gold Plate to Solder Finish
3.3.2.11
Conductors and planes are permitted.
The minimum dielectric spacing shall be specified on the procurement
documentation.
See Table 3-15; the dielectric withstanding voltage test shall be performed in
accordance with IPC-TM-650, Method 2.5.7.
As specified in procurement documentation.
Copper: 2.5 mm
[0.0984 in]
Copper: 1.25 mm
[0.04921 in]
Copper: 0.8 mm
[0.031 in]
Gold: 2.5 mm
[0.0984 in]
Gold: 1.25 mm
[0.04291 in]
Gold: 0.8 mm
[0.031 in]
3.5.4.5
3.6.2.16
3.8.1
3.4
3.3.8
No cuts or scratches that expose nickel or copper; Pits, dents, or depressions
accept if not exceed 0.15 mm [0.00591 in] in longest dimension with no more
than 3 per land, and not appear in > 30% of lands.
3.5.4.4
Edges, Flexible Section
Free of burrs, nicks, or delamination in excess of that allowed in the
procurement documentation (except if a result of tie-in tabs to facilitate circuit
removal). Tears shall not be allowed in Type 1 or Type 2 flexible printed
boards or in the flexible sections of Type 3 or Type 4 flexible printed boards.
3.3.1.2
Accept if penetration not > 50% of distance from edge to nearest conductor or
2.5 mm [0.0984 in], whichever is less.
Electrical Requirements
Etchback (Type 3 & Type 4
Only)
Final Finish Coverage
3.3.1.1
3.8
Between 5 µm [197 µin] (copper exposed) and 80 µm [3,150 µin] (maximum
material removed).
Exposed copper beyond termination areas or beyond required solder fillet
areass allowed up to 5%.
3.6.2.6
3.5.4.7
Shall meet requirements of J-STD-003.
Flexible Endurance
As specified in appropriate document/drawing, according to IPC-TM-650,
Method 2.4.3.
3.10.14
Foreign Inclusions
Translucent particles trapped within the printed board shall be acceptable.
Other particles trapped within the printed board shall be acceptable provided
the particle does not reduce the spacing between adjacent conductors to below
the minimum spacing specified in 3.5.2.
3.3.2.4
Fungus Resistance
Haloing
No fungus growth when tested in accordance with IPC-TM-650, Method 2.6.1.
Does not penetrate more than 2.5 mm [0.0984 in] or 50% of distance to closest
conductor, whichever is less.
3.10.3
3.3.1.1
As specified in procurement documentation; TDR used for electrical testing, but
for large impedance tolerances (± 10%), mechanical measurements from a
microsection utilizing a special test coupon.
Surface Insulation Resistance
As received: 500 MΩ
As received: Maintain
(As Received)
electrical function
After exposure to
After exposure to
After exposure to
moisture: 100 MΩ
moisture: 500 MΩ
moisture: Maintain
electrical function
Ionic (Resistivity of Solvent
Testing in accordance to IPC-TM-650, Method 2.3.25, with contamination level
2
Extract)
of <1.56 µg/cm of sodium chloride.
Isolation Resistance (Circuit
Isolation resistance between conductors shall meet values established in the
Shorts)
procurement documentation; 200 volt minimum for manual testing for at least
3.10.6
Hole Size and Hole Pattern
Accuracy
Impedance Testing
3.4.1
3.10.9
3.10.11
3.8.2.2
five seconds; for automated tests, use the maximum rated voltage of the
printed board; if not specified, use the default value in Table 1-1.
No laminate voids in Zone B (see Figure 3-16) in excess of 50 µm [1,968 µin].
3.6.2.3
Laminate Integrity (Rigid)
See section 3.6.2.4 and Figure 3-14.
3.6.2.4
Lifted Lands
Marking
No lifted lands on the deliverable (non-stressed) flexible printed board.
Conductive marking must be compatible with materials, and not reduce
electrical spacing requirements.
Manufacturer’s Certification.
Material
3.3.4
3.3.5
Measling shall be acceptable. Measled areas in laminate substrates
Measling
Metal Cores
Minimum Layer/Copper Foil
Thickness
Thickness
Moisture and Insulation
Resistance
exceeding 50% of the spacing between non-common conductors are a
process indicator for Class 3 end product, indicating a variation in
material, equipment operation, workmanship or process that is not a
defect.
3.3.2.1
Wicking, radial cracks, lateral spacing, or voids in the hole-fill insulation material
shall not reduce electrical spacing between adjacent conductive surfaces to <
100 µm [3,937 µin].
Shall be in accordance with Table 3-12.
3.6.2.15
Shall be in accordance with Table 3-13.
3.6.2.14
No measling, blistering or delamination in excess of that allowed in 3.3.2;
insulation resistance meet requirements of Table 3-16; moisture & insulation
resistance testing according to IPC-TM-650, Method 2.6.3.
3.6.2.13
3.8.4
Negative Etchback
Not to exceed 25.0 µm
[984 µin] if etchback not [984 µin] if etchback not [512 µin] if etchback not
specified on procurespecified on procurespecified on procurement
ment documentation.
ment documentation.
documentation.
Maximum size 1.0 mm [0.0394 in].
Nicks and Pinholes in Ground Maximum size 1.5 mm
or Voltage Planes
[0.0591 in].
Nonwetting
For tin, tin/lead reflowed, or solder coated surfaces, only allowed outside minimum solderable area or annular ring requirement.
Tested according to IPC-TM-650, Method 2.3.38 or 2.3.39, with no positive id of
organic contamination.
Outgassing
Testing in accordance to procurement documentation; not resulting in a Total
3.6.2.8
3.5.4.1
3.5.4.6
3.10.2
3.10.1
Mass Loss (TML) of more than 1.0% and Collectible Volatile Condensable
Material (CVCM) of less than 0.1%.
Pink Ring
Plating Adhesion
Plating and Coating Voids in
the Hole
Plating Integrity
Plating Voids
Repair
Requirements for
Microsectioned Coupons
Acceptable.
No portion of protective plating or conductor pattern foil shall be removed.
Testing in accordance with IPC-TM-650, Method 2.4.1.
Shall meet requirements of Table 3-2 or as specified in procurement documenta
tion, isolated areas of reduced copper thickness shall be measured and evaluated to the copper plating void rejection criteria specified in 3.3.3.
Copper: 3 voids per hole Copper: 1 void per hole in Copper: none
in ≤10% of holes.
≤5% of holes.
Finish Coating: 3 voids
Finished Coating: 1 void
Finish Coating: 5 voids
per hole in ≤5% of holes. per hole in ≤5% of holes.
per hole in ≤15% of holes.
No separation of layers (except as noted in Table
3-11).
Areas of contamination or inclusions not to exceed 50% of each side of the
interconnection or occur in the interface of the copper cladding on the core and
the copper plating in the hole wall.
Meet requirements
No more than 1 void per specimen, regardless of
established in Table 3-11. length or size.
No plating void in excess of 5% of total flex printed
board thickness.
No plating voids evident at internal layer and PTH
hole wall interface.
AABUS.
See Table 3-11 and 3.6.2.1 through 3.6.2.18
3.3.2.9
3.3.7
3.6.2.12
3.3.3
3.6.2.1
3.6.2.2
3.11
3.6.2
Resin Fill of Blind and Buried
Vias
No fill requirement for blind vias. Buried vias shall be 60% filled with the
laminating resin or similar via filling material for Class 2 and Class 3. Buried
vias may be completely void of fill material for Class 1.
3.6.2.17
Rework
Scratches, Dents, and Tool
Marks
Smear Removal (Type 3 &
Type 4 Only)
Does not affect functional integrity of board.
Not expose conductors or disrupt fibers > allowed in 3.3.2.4 and 3.3.2.5, and do
not reduce dielectric spacing below minimum.
Shall be sufficient to completely remove resin from surface of the conductor
interface (see Figure 3-16).
3.12
3.3.2.6
Solder Wicking/Plating
Migration
Solderability
(External)
Special
Stiffener
Stiffener Access Hole
Structural Integrity
500 µm [19,685 µin]
maximum
300 µm [11,811 µin]
maximum
100 µm [3,937 µin]
maximum
Solderability testing and accelerated aging will be in accordance to J-STD-003.
Meet requirements of Table 3-9.
When bonded with thermoset adhesive, the total area of voids shall not
exceed 10% of the total area of stiffener. When bonded with other
adhesive types, the total area of voids shall not exceed 1/3 of the total
area of the stiffener.
Shall not reduce external annular ring requirements below that specified in
3.4.2.
Shall meet structural integrity requirements for thermally stressed (after solder
float) evaluation coupons specified in 3.6.2.
3.6.2.7
3.3.2.12
3.3.6
3.4.2.1
3.10
3.3.2.13
3.4.2.3
3.6
Surface Microvoids
Not exceed 800 µm [31,500 µin] in longest dimension, bridge conductors, nor
exceed 5% of printed area.
Surface Mount Lands
Defects along edge of land not >20%; internal
Defects along edge of
land not >30%; internal defects not >10%.
defects not >20%.
Thermal Shock
Testing/evaluation according to IPC-TM-650, Method 2.6.7.2, with temp range
between -65 to 125 °C [-85 to 257 °F].
Thermal Stress Testing
Specimens conditioned by baking at 120 to 150 °C [248 to 302 °F] for six hours,
depending on thickness and according to IPC-TM-650, Method 2.6.8. After
microsectioning, plated-through holes shall be examined for foil and plating at
100X ± 5%. Referee examinations made at 200X (± 5%).
Transition Zone, Rigid Area to Imperfections in excess of that allowed shall be AABUS, or as so stated on the
Flexible Area
Visual
Finished product shall be examined, be of uniform quality, and conform to 3.3.1
through 3.3.9.
There shall be no weave
Acceptable if does not reduce conductor spacing
Weave Exposure
exposure on the printed
below minimum.
Workmanship
board
Shall be free of defects and of uniform quality - no visual of dirt, foreign matter,
oil, fingerprints.
3.3.2.7
3.5.4.2
3.10.8
3.6.1
3.3.1.3
3.3
3.3.2.5
3.3.9

IPC-6013C Qualification and Performance Specification for Flexible

Transcription

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