TZ1000 Series

Transcription

TZ1000 Series

TZ1000 Series
MCU Serial Peripheral Interface
Application Processor Lite ApP Lite™
TZ1000 Series
Reference Manual
MCU Serial Peripheral
Interface
Revision 1.0
2015-01
2015-01-22
1 / 46
Rev.1.0
© 2015 Toshiba Corporation
TZ1000 Series
Table of Contents
Preface ................................................................................................................................................................. 6
Intended Audience .................................................................................................................................................... 6
Conventions in this Document .................................................................................................................................. 6
Abbreviation .............................................................................................................................................................. 7
1. Overview .......................................................................................................................................................... 8
2. Block Diagram .................................................................................................................................................. 9
2.1. Internal Configuration and Data Procedure ..................................................................................................... 10
3. Input and Output Signals................................................................................................................................ 12
3.1. Function signal and SPIM signal ..................................................................................................................... 12
3.2. External Pin and SPIM Signal Connection ...................................................................................................... 13
4. Configuration .................................................................................................................................................. 14
5. Function .......................................................................................................................................................... 15
5.1. About the SPIM ................................................................................................................................................ 15
5.2. Clocks .............................................................................................................................................................. 16
5.3. Serial Transfer Mode........................................................................................................................................ 16
5.3.1. Transmission and Reception mode ............................................................................................................................ 16
5.3.2. Transmission mode .................................................................................................................................................... 16
5.3.3. Reception mode ......................................................................................................................................................... 16
5.3.4. EEPROM read mode .................................................................................................................................................. 16
5.4. Connection Interface ........................................................................................................................................ 17
5.4.1. Motorola Serial Peripheral Interface (SPI) .................................................................................................................. 17
5.4.2. National Semiconductor Microwire ............................................................................................................................. 22
5.5. DMA Interface .................................................................................................................................................. 29
5.5.1. Transmit FIFO watermark level................................................................................................................................... 29
5.5.2. Receive FIFO watermark level ................................................................................................................................... 31
5.5.3. DMA handshake ......................................................................................................................................................... 32
5.6. APB Interface ................................................................................................................................................... 33
5.7. Power Management ......................................................................................................................................... 34
5.8. Start-up and Stop Procedure ........................................................................................................................... 35
5.8.1. Start-up procedure...................................................................................................................................................... 35
5.8.2. Stop procedure ........................................................................................................................................................... 39
5.9. Dynamic Clock Gating Setting Procedure ....................................................................................................... 41
6. Precaution for Usage ..................................................................................................................................... 43
6.1. Access Restriction Associated with Register Access ....................................................................................... 43
6.2. Precaution for Dynamic Clock Gating .............................................................................................................. 43
6.3. Precaution for through-current on MOSI pin .................................................................................................... 44
6.4. Precaution for BUSY status ............................................................................................................................. 44
7. Revision History ............................................................................................................................................. 45
RESTRICTIONS ON PRODUCT USE............................................................................................................... 46
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List of Figures
Figure 2.1 SPIM0 internal block diagram ................................................................................................... 9
Figure 2.2 APL03_SSIMx internal block diagram .................................................................................... 10
Figure 5.1 SPIM slave selection (Connection examples) ........................................................................ 15
Figure 5.2 Ratio of sclk_out/ssi_clk at maximum transfer rate ................................................................ 16
Figure 5.3 Data transfer with SPI Protocol (SCPH = 0) ........................................................................... 17
Figure 5.4 Continuous data transfer with SPI protocol (SCPH = 0) ........................................................ 18
Figure 5.5 Data transfer with SPI protocol (SCPH = 1) ........................................................................... 18
Figure 5.6 Continuous data transfer with SPI protocol (SCPH = 1) ........................................................ 19
Figure 5.7 FIFO status in transmission and reception mode with SPI protocol ...................................... 19
Figure 5.8 FIFO status in transmission mode with SPI protocol ............................................................. 20
Figure 5.9 FIFO status in reception mode with SPI protocol ................................................................... 20
Figure 5.10 FIFO status in EEPROM read mode with SPI protocol ........................................................ 21
Figure 5.11 Master single transfer with Microwire protocol (MDD = 0).................................................... 22
Figure 5.12 FIFO status at reception of master single transfer with Microwire protocol ......................... 22
Figure 5.13 Continuous transfer of single transfer frame with Microwire protocol (reception format) .... 23
Figure 5.14 FIFO status in continuous transfer of single transfer frame with Microwire protocol (reception
format).................................................................................................................................................. 23
Figure 5.15 Transfer of continuous transfer frame with Microwire protocol (reception format)............... 24
Figure 5.16 FIFO status in transfer of continuous transfer frame with Microwire protocol (reception
format).................................................................................................................................................. 24
Figure 5.17 Single transfer with Microwire protocol (transmission format) ............................................. 25
Figure 5.18 FIFO status in single transfer with Microwire protocol (transmission format) ...................... 25
Figure 5.19 Continuous transfer with Microwire protocol (transmission format) ..................................... 26
Figure 5.20 FIFO status in continuous transfer with Microwire protocol (transmission format) .............. 26
Figure 5.21 Continuous transfer with handshake with Microwire protocol (transmission format) ........... 27
Figure 5.22 Control word transfer with Microwire protocol ...................................................................... 27
Figure 5.23 FIFO status of Control word transfer with Microwire protocol .............................................. 28
Figure 5.24 Case1: Transmit FIFO watermark level ................................................................................ 29
Figure 5.25 Case2: Transmit FIFO watermark level ................................................................................ 30
Figure 5.26 Receive FIFO watermark level ............................................................................................. 31
Figure 5.27 Burst transfer (pclk = hclk) .................................................................................................... 32
Figure 5.28 Back-to-Back burst transfer (hclk = 2*pclk) .......................................................................... 32
Figure 5.29 Single transfer (pclk = hclk) .................................................................................................. 33
Figure 5.30 Burst transfer + Back-to-Back single transfers (hclk = 2*pclk) ............................................. 33
Figure 6.1 Bit allocation of register access .............................................................................................. 43
Table 3.1
Table 3.2
Table 4.1
Table 5.1
Table 7.1
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List of Tables
Signal correspondence ............................................................................................................. 12
External pin signals .................................................................................................................. 13
List of configuration .................................................................................................................. 14
Power mode and operation ...................................................................................................... 34
Revision History ........................................................................................................................ 45
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********************************************************************************************
ARM and AMBA are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or
elsewhere. All rights reserved.
********************************************************************************************
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Synopsys Proprietary. Use with permission.
Portion Copyright (C) 2011,2012 Synopsys,Inc, Used with permission.
All rights reserved. Synopsys & DesignWare are registered trademarks of Synopsys, Inc.
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Preface
This document provides the specification for the MCU Serial Peripheral Interface designed for the
TZ1000 Series.
Intended Audience
This document is intended for the following users.
Driver software developers.
System designers
Conventions in this Document
● The following notational conventions apply to numbers:
Hexadecimal number:
0xABC
Decimal number:
123 or 0d123 (only when it should be explicitly indicated that
the number is decimal)
Binary number:
0b111 (It is possible to omit the "0b" when the number of
bit can be distinctly understood from a sentence.)
● Low active signals are indicated with a name suffixed with "_N".
● A signal is asserted when it goes to its active level while it is deasserted when it goes to its
inactive level.
● A set of multiple signals may be referred to as [m:n].
Example: S[3:0] indicates four signals, S3, S2, S1 and S0, collectively.
● In the text, register names are enclosed in brackets [ ].
Example:[ABCD]
● A set of multiple registers, fields or bits of the same type may be described collectively using "n".
Example: [XYZ1], [XYZ2], and [XYZ3] to [XYZn]
A range of register bits are referred to as [m:n].
Example: [3:0] indicates a range from bit 3 to bit 0.
● Values set in registers are indicated using either a hexadecimal or binary number.
● Example: [ABCD].EFG = 0x01 (hexadecimal), [XYZn].VW = 1 (binary)
● Words and bytes are defined as follows:
Byte:
8 bits
Halfword:
16 bits
Word:
32 bits
Doubleword:
64 bits
● Register bit attributes are defined as follows:
R:
Read-only
W:
Write-only
W1C:
Clear by write of 1 (a write of "1" clears the corresponding bit to 0)
W1S:
Set by write of 1 (a write of "1" sets the corresponding bit to 1)
R/W:
Read/Write
R/W0C:
Read/Clear by write of 0
R/W1C:
Read/Clear by write of 1
R/W1S:
Read/Set by write of 1
RS/WC:
Set by read/Clear by write (set after a read and cleared after a data write)
● Registers only support word access unless otherwise specified.
● Any registers defined as Reserved in the text must not be rewritten. Also, any values read from
such registers should not be used.
● Any bits for which default values are defined as "-" would return undefined values if read.
● When a data is written to a register containing both writable and read-only (R) bit fields, its
default values should be written to read-only (R) bit fields. For any bit fields with default values
defined as "-", refer to the definitions of the relevant register.
● Default values should be written to any reserved bit fields in a write-only register. For any bit
fields with default values defined as "-", refer to the definitions of the relevant register.
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Abbreviation
These specifications introduce a part of the abbreviation which they used
APB
ARM® AMBA® Advanced Peripheral Bus
RIS
Raw Interrupt Status
MIS
Masked Interrupt Status
PMU
Power Management Unit
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1. Overview
This module is SPI master controller (SPIM).
The main feature of the SPIM is as follows.
● Connection to the 32-bit APB
● Synchronous serial interface (SCLK, MIMO, MOSI, and SS_n)
● Serial data transfer rate:
- Max 6 MHz (with SPI clock 12 MHz)
- Dividing ratios of 2 to 65534 available
● Serial master mode is supported.
● Following serial transfer protocols are supported.
- Motorola SPI
- National Semiconductor Microwire
- Data lengths of 4 to 16 bits available
● Transmit FIFO and receive FIFO
● Interrupt mode or polling mode
● DMA handshake transfer (burst transfer request and single transfer request) is supported.
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2. Block Diagram
The internal block diagram of this module is shown in Figure 2.1. (The SPIM0 represents the
multiple SPIM blocks in this module.)
SPIM0
APL03_SSIM3
spim0pClk
spim0sClk
io_spim0_rxd_i
pclk
io_spim0_txd_o
ssi_clk
io_spim0_ssi_oe_e_N
io_spim0_ss_in_i_N
spim0pReset_n
spim0sReset_n
spim0_ssi_sleep
presetn
io_spim0_ss_0_n_o
ssi_rst_n
io_spim0_sclk_out_o
ssi_sleep
spim0_ssi_en_int
pmu_ssi_en_int
spim0_dma_rx_req
spim0_dma_rx_single
spim0_dma_rx_ack
spim0_T0_*
APB bus
spim0_T0_
PRDATA[31:0]
paddr[7:0]
penable
spim0_dec
pwrite
spim0_dma_tx_single
spim0_dma_tx_ack
psel
spim0_mux
pwdata[31:0]
1
0
Figure 2.1
spim0_dma_tx_req
prdata[31:0]
irq_spim0
SPIM0 internal block diagram
The SPIM is supplied with clocks and reset signals by the PMU. It issues an interrupt request to the
CPU. The DMA transfer request of the SPIM is connected to the SDMAC. The SPIM
(APL03_SSIM*) register space is 256 Bytes, and it is located at the start of the 4-KB space to be
shared by the bus.
The SPIM in the TZ1000 Series is as follows;
● SPIM0: Receive FIFO=8, Transmit FIFO=8, Master mode, and External pin connection
● SPIM1: Receive FIFO=8, Transmit FIFO=8, Master mode, and External pin connection
● SPIM2: Receive FIFO=8, Transmit FIFO=2, Master mode, Internal acceleration sensor connection,
and External pin connection
● SPIM2: Receive FIFO=8, Transmit FIFO=2, Master mode, Internal gyro sensor connection, and
External pin connection
(The SPIM2 and SPIM3 connections depend on a product package.)
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2.1. Internal Configuration and Data Procedure
APL03_SSIMx
Figure 2.2
APL03_SSIMx internal block diagram
The APL03_SSIMx internal blocks are outlined below.
- APB Interface Unit

This block interfaces to the APB.
- Register Block

This block controls the SPIM operation, its status, and the interrupt generation.
- Transmit FIFO Control

This block controls the transmit FIFO.
- Transmit FIFO Memory

Transmit FIFO.
- Receive FIFO Control

This block control the receive FIFO.
- Receive FIFO Memory

Receive FIFO.
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- FSM Control

This block is a state machine to control a data transfer.
- Clock Pre-scale

This block calculates the timing for the following operations.

SCLK clock generation in a master mode.

Transfer clock rate generation.
- Shift Control Logic

This block controls shift operation of a serial data.
- DMA Interface

This block generates a DMA request signal.
- Interrupt Logic

This block generates an interrupt request signal.
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3. Input and Output Signals
3.1. Function signal and SPIM signal
The function signal names and the corresponding SPIM signal names are shown in the following
table. The function signal names are used in Section 5 Function.
Function
Signal Name
pclk
ssi_clk
presetn
ssi_rst_n
paddr
penable
psel
pwdata
pwrite
prdata
rxd
txd
ss_in_n
ssi_oe_n
ss_0_n
sclk_out
dma_tx_ack
dma_rx_ack
dma_tx_req
dma_tx_single
dma_rx_req
dma_rx_single
ssi_intr
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Table 3.1 Signal correspondence
SPIM
Description
Signal
Bus clock signal
pclk
ssi_clk
Peripheral serial clock signal
presetn
Bus reset signal
ssi_rst_n
Peripheral reset signal
paddr
penable
psel
APB signals
pwdata
pwrite
prdata
rxd
Received data signal
txd
Transmit data signal
ss_in_n
Slave select input
ssi_oe_n
Output enable signal
ss_0_n
Slave select output
sclk_out
Serial bit-rate clock
dma_tx_ack
DMA Transmit Acknowledgment
dma_rx_ack
DMA Reception Acknowledgment
dma_tx_req
Transmit FIFO DMA Request
dma_tx_single
DMA Transmit FIFO Single Signal
dma_rx_req
Receive FIFO DMA Request
dma_rx_single
DMA Receive FIFO Single Signal
ssi_intr
Interrupt signal
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3.2. External Pin and SPIM Signal Connection
The connections between the SPIM signals and the external pin signals are shown in the following
table.
These connections can be changed by the pin share settings.
Pin Name
MCU_SPIM0_CS_N
MCU_SPIM0_CLK
MCU_SPIM0_MOSI
MCU_SPIM0_MISO
MCU_SPIM1_CS_N
MCU_SPIM1_CLK
MCU_SPIM1_MOSI
MCU_SPIM1_MISO
MCU_SPIM2_CS_N
MCU_SPIM2_CLK
MCU_SPIM2_MOSI
MCU_SPIM2_MISO
MCU_SPIM3_CS_N
MCU_SPIM3_CLK
MCU_SPIM3_MOSI
MCU_SPIM3_MISO
MCU_GPIO_12
MCU_GPIO_13
MCU_GPIO_14
MCU_GPIO_15
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Table 3.2 External pin signals
Pin
Internal Connection Signal
Direction
Connect
Share
(Block: Signal)
output
PIN
FMOD1
SPIM0: ss_0_n
output
PIN
FMOD1
SPIM0: sclk_out
output
PIN
FMOD1
SPIM0: txd
input
PIN
FMOD1
SPIM0: rxd
output
PIN
FMOD1
SPIM1: ss_0_n
output
PIN
FMOD1
SPIM1: sclk_out
output
PIN
FMOD1
SPIM1: txd
input
PIN
FMOD1
SPIM1: rxd
output
Sensor/PIN
FMOD1
SPIM2: ss_0_n
output
Sensor/PIN
FMOD1
SPIM2: sclk_out
output
Sensor/PIN
FMOD1
SPIM2: txd
input
Sensor/PIN
FMOD1
SPIM2: rxd
output
Sensor/PIN
FMOD1
SPIM3: ss_0_n
output
Sensor/PIN
FMOD1
SPIM3: sclk_out
output
Sensor/PIN
FMOD1
SPIM3: txd
input
Sensor/PIN
FMOD1
SPIM3: rxd
output
PIN
FMOD2
SPIM3: ss_0_n
output
PIN
FMOD2
SPIM3: sclk_out
output
PIN
FMOD2
SPIM3: txd
input
PIN
FMOD2
SPIM3: rxd
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4. Configuration
The function configuration for each SPIM channel is shown in the following table.
Table 4.1 List of configuration
Configuration option
Serial master or slave
configuration
Receive FIFO buffer depth
Transmit FIFO buffer depth
Peripheral ID Code
Include DMA Handshaking
Interface Signals
Configure interrupt pin out
Active interrupt level
pclk and ssi_clk synchronous
Default frame format
Default serial clock polarity
Default serial clock phase
Toggle slave select signal
between frames when in SPI
mode and SCPH=0
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Values
SPIM0
SPIM1
SPIM2
SPIM3
Master
Master
Master
Master
8
8
0x41334d33
8
8
0x41334d33
8
2
0x41334d32
8
2
0x41334d32
Yes
Yes
Yes
Yes
Combined
Combined
Combined
Combined
Interrupt
Interrupt
Interrupt
Interrupt
Active-high Active-high Active-high Active-high
Synchronous Synchronous Synchronous Synchronous
Motorola SPI Motorola SPI Motorola SPI Motorola SPI
0
0
0
0
0
0
0
0
Toggle
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Toggle
Toggle
Toggle
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5. Function
The function signal names are used in this section. For the function signal names, refer to Table 3.1.
5.1. About the SPIM
The SPIM is an synchronous serial interface. The following serial protocols are supported.
● Motorola Serial Peripheral Interface (SPI)
- 4-lline full-duplex serial protocol. 4 different modes depending on the clock phase and polarity.
- A slave selection signal is implemented. High of the signal shows an idle state, and Low, an
active state. For detail, refer to Section 5.4.1,
● National Semiconductor Microwire
- Half-duplex serial protocol. A serial master transfers a command to a serial slave, and data
transfer is executed. For detail, refer to Section 5.4.2.
The connections of the slave selection signal (SS) in the SPIM system are shown in the following
figure.
Figure 5.1
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SPIM slave selection (Connection examples)
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5.2. Clocks
The SPIM uses a bus clock (pclk) and a serial clock (ssi_clk). The pclk frequency should be equal to
or higher than that of ssi_clk. In the SPIM in the TZ1000 Series, the ssi_clk synchronizes the pclk.
The maximum frequency of the serial transfer clock (sclk_out) is 1/2 of ssi_clk frequency. The
sclk_out frequency is calculated by the following formula.
sclk_out frequency = ssi_clk /(SCKDV)
SCKDV: [SPIMn_BAUDR] register value
An even number among 0 to 65534 is available.
When SCKDV=0 is set, the sclk_out is disabled and no data are transferred. The minimum value of
the SCKDV is 2.
Figure 5.2 Ratio of sclk_out/ssi_clk at maximum transfer rate
5.3. Serial Transfer Mode
The transfer mode is set with the TMOD bit in the [SPIMn_CTRLR0] register. For the Microwire
protocol, the mode is set with the [SPIMn_MWCR] register.
5.3.1. Transmission and Reception mode
TMOD=0b00 enables data transmission and reception.
5.3.2. Transmission mode
TMOD=0b01 enables data transmission only.
5.3.3. Reception mode
TMOD=0b10 enables data reception only.
5.3.4. EEPROM read mode
TMOD=0b11 enables EEPROM read.
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5.4. Connection Interface
5.4.1. Motorola Serial Peripheral Interface (SPI)
The signals in this section are as follows.
● sclk_out: Serial clock issued by a serial master
● sclk_in: Serial clock received by a serial slave
● ss_0_n:
Slave selection signal issued by a serial master
● ss_in_n: Slave selection signal received by a serial slave
● ss_oe_n: Output enable signal between a serial master and a serial slave
● txd:
Transmission data between a serial master and a serial slave
● rxd:
Reception data between a serial master and serial slave
The SPI protocol constructs a serial data frame by setting a clock polarity (SCPOL) and a clock
phase (SCPH). The serial data length per frame can be selected among 4 to 16 bits. The timing chart
with SPCH=0 is shown in Figure 5.3.
The sclk_out/in 0 means the clock with SCPOL=0, and the sclk_out/in 1, the clock with SCPOL=1.
When SCPOL=0, the transmission data txd is transmitted at the falling edge of the sclk_out/in.
When SCPOL=1, the txd is transmitted at the rising edge of the clock. The first of the data is issued
without the clock. When SCPOL=0, the reception data rxd is received at the rising edge of the
sclk_out/in. When SCPOL=1, the rxd is received at the falling edge of the clock.
Figure 5.3 Data transfer with SPI Protocol (SCPH = 0)
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When serial data transfer continues with SCPH=0, the ss_0_n/ss_in_n toggles at the frame
boundary.
The timing chart is shown in Figure 5.4.
Figure 5.4 Continuous data transfer with SPI protocol (SCPH = 0)
The timing chart with SPCH=1 is shown in Figure 5.5.
When SCPOL=0, the transmission data txd is transmitted at the rising edge of the sclk_out/in.
When SCPOL=1, the txd is transmitted at the falling edge of the clock. The first of the data is issued
with the clock. When SCPOL=0, the reception data rxd is received at the falling edge of the
sclk_out/in. When SCPOL=1, the rxd is received at the rising edge of the clock.
Figure 5.5 Data transfer with SPI protocol (SCPH = 1)
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When serial data transfer continues with SCPH=1, the ss_0_n/ss_in_n does not toggle at the frame
boundary and remains 0 until the transfer completion.
The timing chart is shown in Figure 5.6.
Figure 5.6 Continuous data transfer with SPI protocol (SCPH = 1)
Figure 5.7 shows the FIFO status in the transmission and reception mode with the SPI protocol.
When the transmit FIFO is written, the data is stored by the FIFO, and the serial data
transmission starts at the txd. At the same time, a reception data from the rxd is stored by the
receive FIFO. The count of the transmission data is the same as the count of the reception data in
this mode.
Figure 5.7
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FIFO status in transmission and reception mode with SPI protocol
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Figure 5.8 shows the FIFO status in the transmission mode with the SPI protocol. When the
transmit FIFO is written, the data is stored by the FIFO, and the serial data transmission starts at
the txd. A reception data from the rxd is not stored by the receive FIFO.
Figure 5.8
FIFO status in transmission mode with SPI protocol
Figure 5.9 shows the FIFO status in the reception mode with the SPI protocol. When a dummy data
is written to the transmit FIFO, the data is stored by the FIFO, and the serial data transmission
starts at the txd. At the same time, a reception data from the rxd is stored by the receive FIFO. The
count of the reception data is set to the NFD in the [SPIMn_CTRLR1] register.
Figure 5.9
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FIFO status in reception mode with SPI protocol
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Figure 5.10 shows the FIFO status in the EEPROM read mode with the SPI protocol. When an
opecode and an address for the EEPROM are written to the transmit FIFO, they are stored by the
FIFO, and the serial data transmission starts at the txd. At the same time, a reception data from
the rxd is stored by the receive FIFO. The count of the reception data is set to the NFD in the
[SPIMn_CTRLR1] register.
Figure 5.10 FIFO status in EEPROM read mode with SPI protocol
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5.4.2. National Semiconductor Microwire
In the Microwire protocol, Control word is transferred at first, and then, the data transmission or
reception is executed. This format is a half-duplex serial protocol. The ssi_oe_n changes the input or
the output. The length of the Control word is 1 to 16 bits, which is set to the CSF field in the
[SPIMn_CTRLR0] register. The serial data length per frame is selected among 4 to 16 bits. The
setting of the transmission or reception (MDD bit), the continuous transfer (MWMOD bit), and the
handshake setting (MHS bit) are set to the [SPIMn_MWCR] register. The timing chart and the
FIFO status are shown in Figure 5.11 and Figure 5.12, respectively.
Figure 5.11 Master single transfer with Microwire protocol (MDD = 0)
Figure 5.12 FIFO status at reception of master single transfer with Microwire protocol
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Figure 5.13 shows the (reception) timing chart of the continuous transfer of a single transfer frame.
Figure 5.14 shows its FIFO status.
Figure 5.13 Continuous transfer of single transfer frame with Microwire protocol (reception
format)
Figure 5.14 FIFO status in continuous transfer of single transfer frame with Microwire protocol
(reception format)
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Figure 5.15 shows the timing chart of the continuous transfer frame (reception). Figure 5.16 shows
its FIFO status.
Figure 5.15 Transfer of continuous transfer frame with Microwire protocol (reception format)
Figure 5.16 FIFO status in transfer of continuous transfer frame with Microwire protocol
(reception format)
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Figure 5.17 shows the (transmission) timing chart of a single transfer frame. Figure 5.18 shows its
FIFO status.
Figure 5.17 Single transfer with Microwire protocol (transmission format)
Figure 5.18 FIFO status in single transfer with Microwire protocol (transmission format)
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Figure 5.19 shows the (transmission) timing chart of the continuous transfer. Figure 5.20 shows its
FIFO status.
Figure 5.19 Continuous transfer with Microwire protocol (transmission format)
Figure 5.20 FIFO status in continuous transfer with Microwire protocol (transmission format)
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Figure 5.21 shows the (transmission) timing chart of the continuous transfer with the handshake.
Figure 5.21 Continuous transfer with handshake with Microwire protocol (transmission format)
Figure 5.22 shows the timing chart of the Control word transfer. Figure 5.23 shows its FIFO
status.
Figure 5.22 Control word transfer with Microwire protocol
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Figure 5.23 FIFO status of Control word transfer with Microwire protocol
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5.5. DMA Interface
The SPIM has DMAC request function. The control signals are as follows. Every signal is connected
to the DMAC.
dma_tx_req
dma_rx_req
dma_tx_single
dma_rx_single
dma_tx_ack
dma_rx_ack
SPIM transmission burst transfer request
SPIM reception burst transfer request
SPIM transmission single transfer request
SPIM reception single transfer request
SPIM transmission acknowledgment
SPIM reception acknowledgment
5.5.1. Transmit FIFO watermark level
An example (1) for setting a transmit FIFO watermark level when DMAC is used for SPIM
transmission.
Transmit FIFO watermark level
SPIM_DMATDLR = 2
DMAC transfer destination burst count FIFO_DEPTH - SPIM_DMATDLR = 6
SPIM transmit FIFO stage count
FIFO_DEPTH = 8
Total DMAC transfer count
30
In this case, the DMAC block transfer count is as follows:
Total DMAC transfer count/DMAC transfer destination burst count = 30/6 = 5
The SPIM issues a burst transfer request to the DMAC until reaching the transmit FIFO
watermark level. When the data count reaches the watermark level, the SPIM suspends to issue
the DMA transfer request. The SPIM transmits data for the transmit FIFO to have empty space.
This operation proceeds in the following steps.
(1) DMA transfer count=6 6 items put into the transmit FIFO with 2 empty stages ->
Transfer request is suspended.
(2) Transfer data until reaching the watermark level (=2) (6 empty stages in the transmit FIFO)
(3) When the data count of the transmit FIFO reaches the watermark level, the DMA transfer
request is issued.
After that, the steps (1) through (3) repeat until the data of the total DMAC transfer count have
been transferred.
Figure 5.24 Case1: Transmit FIFO watermark level
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An example (2) for setting a transmit FIFO watermark level when DMAC is used for SPIM
transmission.
Transmit FIFO watermark level:
DMAC transfer destination burst count:
SPIM transmit FIFO stage count:
Total DMAC transfer count:
SPIM_DMATDLR = 6
FIFO_DEPTH - I2C.IC_DMA_TDLR = 2
FIFO_DEPTH = 8
30
In this case, the DMAC block transfer count is as follows:
Total DMAC transfer count/DMAC transfer destination burst count = 30/2 = 15
The SPIM issues a burst transfer request to the DMAC until reaching the transmit FIFO
watermark level. When the data count reaches the watermark level, the SPIM suspends to issue the
DMA transfer request. The SPIM transmits data for the transmit FIFO to have empty space. This
operation proceeds in the following steps.
(1) DMA transfer count=2
2 items are put into the transmit FIFO with 6 empty stages.
4 items are put into the transmit FIFO with 4 empty stages. During
the transfer, SPIM transmits one.
5 items are put into the transmit FIFO with 3 empty stage.
7 items are put into the transmit FIFO with 1 empty stage. ->
Transfer request is suspended.
(5) Transfer data until reaching the watermark level (= 6) (2 empty stages in the transmit FIFO).
(6) When the data count of the transmit FIFO reaches the watermark level, the DMA transfer
request is issued.
8 items are put into the transmit FIFO with no empty stages. ->
Transfer request suspended.
(8) After that, steps (5) through (7) repeat until the data of the total DMAC transfer count have
been transferred.
Figure 5.25 Case2: Transmit FIFO watermark level
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5.5.2. Receive FIFO watermark level
An example for setting a receive FIFO watermark level when DMAC is used for SPIM reception:
Receive FIFO watermark level:
DMAC transfer destination burst count:
SPIM_DMARDLR
SPIM_DMARDLR +1
The SPIM issues a burst transfer request to the DMAC when reaching the receive FIFO watermark
level plus 1. The DMAC reads the data from the SPIM and sends it to the destination.
Depending on the watermark level setting, if the DMAC transfer is not enough fast, an overflow
may occur at the receive FIFO. If this occurs, a measure must be taken to reduce the watermark
level settings.
Figure 5.26 Receive FIFO watermark level
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5.5.3. DMA handshake
The following example is in the case that the DMA clock (hclk) timing is the same as the SPIM clock
(pclk) one. It is a burst transfer, not a single one, but the following figure shows the waveforms of
the dma_tx_req (the request of the SPIM transmission burst transfer) and the dma_tx_single (the
request of the SPIM transmission single transfer).
When one or more data are transferred, the dma_tx_single is asserted. When a burst transfer is
executed, the dma_tx_req is also asserted. When the dma_tx_ack is received, both the dma_tx_req
and the dma_tx_single are deasserted.
Figure 5.27 Burst transfer (pclk = hclk)
The following example is in the case of that the frequency of the DMA clock (hclk) is double of that of
the SPIM clock (pclk). It is a burst transfer, not a single one, but the following figure shows the
waveforms of the dma_tx_req (the request of the SPIM transmission burst transfer) and the
dma_tx_single (the request of the SPIM transmission single transfer).
Figure 5.28 Back-to-Back burst transfer (hclk = 2*pclk)
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The following example is in the case that the DMA clock (hclk) timing is the same as the SPIM clock
(pclk) one for the single transfer. The following figure shows the waveform of the dma_rx_single (the
request of the SPIM reception single transfer).
When data is transferred, the dma_rx_single is asserted. When the dma_rx_ack is received, the
dma_rx_single is deasserted.
Figure 5.29 Single transfer (pclk = hclk)
The following example is in the case of that the frequency of the DMA clock (hclk) is double of that of
the SPIM clock (pclk). It is a combination of a burst transfer and a single one. The following figure
shows the waveforms of the dma_tx_req (the request of the SPIM transmission burst transfer) and
the dma_tx_single (the request of the SPIM transmission single transfer). The first request is a
burst transfer and the followings are single transfer requests.
Figure 5.30 Burst transfer + Back-to-Back single transfers (hclk = 2*pclk)
5.6. APB Interface
32-bit APB interface is set by the configuration. The AMBA2 format is applied.
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5.7. Power Management
The power modes of the TZ1000 Series are shown in the following table.
Table 5.1 Power mode and operation
Power mode State of SPIM0/1/2/3
ACTIVE
Run (Note)
SLEEP0
Run (Note)
SLEEP1
Run (Note)
SLEEP2
Clock gating
WAIT
Clock gating
RETENTION
Retention
RTC
Power Down
STOP
Power Down
Note: The clock can be started or stopped by software.
● ACTIVE/SLEEP0/SLEEP1:
Normal operation.
When the clock stop is set by software, the communication operation stops and every signal
operation. To prevent that, the clock should be stopped after the interrupt disable is set. It is
inhibited that the clock stops while a data frame is being transferred, because the restart of the
transfer may not be done successfully. The clock should stop after it is confirmed that the SPIM
transfer is in the stop state.
When the clock start is set, the transfer re-starts with the same state where the clock stopped.
● SLEEP2/WAIT/ RETENTION:
Both pclk and ssi_clk stop, so the counter also stops and every signal holds its own data. If the
interrupt and others are asserted, they will not be able to be deasserted. It is necessary to set the
disable to them before the clock stop. And, it is inhibited that those clocks stops while a data
frame is being transferred.
When returning from this mode, every signal is restored to the data in the previous mode.
● RTC/STOP:
Before the transition to this mode, it should be checked that the following settings are done to
disable the corresponding function.
- SSI_EN = 0 in the [SPIMn_SSIENR] register
- BUSY = 0 in the [SPIMn_SR] register (n is a channel number: 0, 1, 2, or 4.)
When returning from this mode, the registers are initialized. So, the operation should re-start
after the configuration of the registers completes.
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5.8. Start-up and Stop Procedure
5.8.1. Start-up procedure
The start-up procedure after power-on is as follows.
For detail of the PMU registers, refer to the PMU section.
The following setting is supposed that the main bus (the bus connected to the CPU) is supplied with
clocks.
Each channel of the SPIM will be supplied with a clock by this setting.
("*" shows the signal which also controls another function. The setting should be done together with
another setting.)
The order of the setting procedure is a frequency setting at first, then clock supply, and reset
deassertion at last.
● SPIM clock frequency setting
PMU register
Bit name
CSM_MAIN
PRESCAL_MAIN
Description
CSMSEL_MAIN
PSSEL_CD_PPIER0
PSSEL_CD_PPIER2
Note:
Note:
Note:
Note:
0x0000000u
u:
0x0: SiOSC4M,
0x1: OSC12M,
0x2: PLL,
0x3 :ADPLL,
0x4: OSC32K/SIOSC32K
0x5-0x7: reserved
0x****u***
u:
0x0: not generate clock
0x1: divided by 1, 0x2: divided by 2,
0x9: divided by 9, 0xA: divided by 10,
0xB: divided by 12, 0xC: divided by 18,
0xD: divided by 24, 0xE: divided by 36,
0xF: divided by 48
0x**u***** u: same as above
CSM_MAIN sets the source of the clock. The PLL is set by another register and the
frequency is changed by the setting. (For detail, refer to the PMU section.)
PRESCAL_MAIN has a setting to another power domain.
PSSEL_CD_PPIER0 setting specifies all circuits in the PPIER0 power domain.
(The SPIM2 and SPIM3 are in the PPIER0 power domain.)
The setting of the PSSEL_CD_PPIER1 is applied to all circuits which belong to the
PPIER1 power domain.
(The SPIM0 and SPIM1 are in the PPIER1 power domain.)
The start-up sequence of the SPIM0 is as follows.
Setting of the external shared pins at first, then release of the standby for the external pins, Clock
supply, deassertion of the reset ,and output enable for the external pins at last.
● Setting of the external shared pins of the SPIM0
It is necessary that the GCONF should configure the shared pins to input or output data. (For
detail, refer to "Hardware Specification 6.1. Setting Multiple function I/O.")
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● Standby mode release of the external pins in the SPIM0
When the external pins are used, it is necessary to release the standby mode of the pins. (For
detail, refer to the PMU section.)
● SPIM0 clock supply
PMU register
CG_OFF_POWERDOMAIN
CG_OFF_PM_2
CG_OFF_PP_1
Bit name
CG_PP1
CG_PM
CG_mpierclk_h2hp1_hclk
CG_ppier1clk_spim0_sclk
CG_ppier1clk_spim0_pclk
CG_ppier1clk_h2pp1_hclk
value
0x00000801
0x00010000
0x00000301
Note: Bit 9 and 8 in the CG_OFF_PP_1 register corresponds to the SPIM0.
● Reset deassertion of the SPIM0
PMU register
SRST_OFF_POWERDOMAIN
SRST_OFF_PM_2
SRST_OFF_PP_1
Bit name
SRST_PP1
SRST_PM
SRST_asyncrst_h2hp1_hrstn
SRST_asyncrst_spim0_srstn
SRST_asyncrst_spim0_prstn
SRST_asyncrst_h2pp1_hrstn
value
0x00000801
0x00010000
0x00000301
Note: Bit 9 and 8 in the SRST_OFF_PP_1 register corresponds to the SPIM0.
● Output enable for the external pins of the SPIM0
GCONF register
Bit name
OE_CTRL
SPIM0_OE
value
0x0000**1*
Note: Bit 4 in the OE_CTRL register corresponds to the SPIM0.
Note: "*" shows the signal which also controls another function.
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PMU register
CG_OFF_POWERDOMAIN
CG_OFF_PM_2
CG_OFF_PP_1
Bit name
CG_PP1
CG_PM
value
0x00000801
0x00010000
0x00000C01
Note: Bit 11 and 10 in the CG_OFF_PP_1 register corresponds to the SPIM1.
PMU register
SRST_OFF_PM_2
SRST_OFF_PP_1
Bit name
SRST_PP1
SRST_PM
value
0x00000801
0x00010000
0x00000C01
Note: Bit 11 and 10 in the SRST_OFF_PP_1 register corresponds to the SPIM1.
GCONF register
Bit name
OE_CTRL
SPIM1_OE
value
0x0000**2*
PMU register
CG_OFF_POWERDOMAIN
CG_OFF_PM_1
Bit name
CG_PM
value
0x00000001
0x0C000003
Note: Bit 27 and 26 in the CG_OFF_PM_1 register corresponds to the SPIM2.
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PMU register
SRST_OFF_PM_1
Bit name
SRST_PM
value
0x00000001
0x0C000003
Note: Bit 27 and 26 in the SRST_OFF_PM_1 register corresponds to the SPIM2.
GCONF register
Bit name
OE_CTRL
SPIM2_OE
value
0x0000**4*
PMU register
CG_OFF_POWERDOMAIN
CG_OFF_PM_1
Bit name
CG_PM
value
0x00000001
0x30000003
Note: Bit 29 and 28 in the CG_OFF_PM_1 register corresponds to the SPIM3.
PMU register
SRST_OFF_PM_1
Bit name
SRST_PM
value
0x00000001
0x30000003
Note: Bit 29 and 28 in the SRST_OFF_PM_1 register corresponds to the SPIM3.
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GCONF register
Bit name
OE_CTRL
SPIM3_OE
value
0x0000**8*
Multiple channels can start up simultaneously by the following setting. The above values are
written to the corresponding registers separately, or the ORed value of these values is written to the
corresponding registers.
The following setting is the same for the SPIM0, SPIM1, SPIM2, and SPIM3.
● Setting of the SPIM and operation start
- When the reset is deasserted, the SPIM is in the disable state.
It starts to operate by writing to the following registers.
- [SPIMn_CTRLT0], [SPIMn_CTRLT1], [SPIMn_BAUDR], and [SPIMn_SER] registers are set
for the transfer mode, the clock phase, the polarity, the dividing ratio, the transfer count,
and others.
- Set SSI_EN = 1 in the [SPIMn_SSIENR] register.
(n is a channel number: 0, 1, 2 or 3)
5.8.2. Stop procedure
● In the case of that the transfer of the SPIM is stopped.
- The transfer of SPIM stops immediately when The SSI_EN in the [SPIMn_SSIENR] register is
set to 0. To avoid stopping transfer in the middle of a frame, please make sure that SPIM
transfer is not underway by polling BUSY status in [SPIMn_SR] before setting SSI_EN=0
(See 7.4. Precaution for BUSY status).
● In the case that the SPIM is not used (the whole block stops);
The following two ways are used.
- No reset assertion

Only the clock supply is stopped by the following PMU register setting.
- Reset assertion

The reset assertion and the clock stop are set by the following PMU register.
The stop sequence of the SPIM0 is as follows;
The reset assertion and then the stop of the clock supply
● SPIM0 reset
PMU register
SRST_ON_PP_1
Bit name
Value
0x000000300
Note: Bit 9 and 8 in the SRST_ON_PP_1 register corresponds to the SPIM0.
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● SPIM0 clock supply stop
PMU register
CG_ON_PP_1
Bit name
value
0x00000300
Note: Bit 9 and 8 in the CG_ON_PP_1 register corresponds to the SPIM0.
● SPIM1 reset
PMU register
SRST_ON_PP_1
Bit name
value
0x000000C00
Note: Bit 11 and 10 in the SRST_ON_PP_1 register corresponds to the SPIM1.
PMU register
CG_ON_PP_1
Bit name
value
0x00000C00
Note: Bit 11 and 10 in the CG_ON_PP_1 register corresponds to the SPIM1.
● SPIM2 reset
PMU register
SRST_ON_PM_1
Bit name
value
0x0C0000000
Note: Bit 27 and 26 in the SRST_ON_PM_1 register corresponds to the SPIM2.
PMU register
CG_ON_PM_1
Bit name
value
0x0C0000000
Note: Bit 27 and 26 in the CG_ON_PM_1 register corresponds to the SPIM2.
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● SPIM3 reset
PMU register
SRST_ON_PM_1
Bit name
value
0x300000000
Note: Bit 29 and 28 in the SRST_ON_PM_1 register corresponds to the SPIM3.
PMU register
CG_ON_PM_1
Bit name
value
0x300000000
Note: Bit 29 and 27 in the CG_ON_PM_1 register corresponds to the SPIM3.
Multiple channels can stop simultaneously by the following setting. The above values are written to
the corresponding registers separately, or the ORed value of these values are written to the
corresponding registers.
5.9. Dynamic Clock Gating Setting Procedure
The TZ1000 Series can be set to stop the clock supply unless the clock is necessary. When it is set,
the following operation reduces the power dissipation.
("*" shows the signal which also controls another function. The setting should be done together with
another setting.)
● Clock supply only when the bus access to the SPIM.
● Clock supply stop for the SPIM when the SPIM is disabled (SSI_EN = 0 in the [SPIMn_SSIENR]
register or the spim_sleep is 1 (when the operation stops, the signal becomes 1)).
● SPIM0 dynamic clock gating setting
PMU register
DCG_POWERDOMAIN
DCG_PM_2
DCG_PP_1
Bit name
DCG_PM
DCG_PP1
DCG_mpierclk_h2hp1_hclk
DCG_ppier1clk_spim0_sclk
DCG_ppier1clk_spim0_pclk
DCG_ppier1clk_h2pp1_hclk
value
0x*****8*1
0x***1****
0x*****3*1
Note: Bit 9 and 8 in the DCG_PP_1 register corresponds to the SPIM0.
PMU register
DCG_POWERDOMAIN
DCG_PM_2
DCG_PP_1
Bit name
DCG_PM
DCG_PP1
value
0x*****8*1
0x***1****
0x*****C*1
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PMU register
DCG_POWERDOMAIN
DCG_PM_1
Bit name
DCG_PM
value
0x*******1
0x*C*****3
Note: Bit 27 and 26 in the DCG_PM_1 register corresponds to the SPIM2.
PMU register
DCG_POWERDOMAIN
DCG_PM_1
Bit name
DCG_PM
value
0x*******1
0x3******3
The setting of the dynamic clock gating can be cleared by writing 0 to the corresponding bit.
● SPIM0 dynamic clock gating deassertion (SPIM0 only)
PMU register
Bit name
DCG_PP_1
value
0x*****0*1
PMU register
Bit name
DCG_PP_1
value
0x*****0*1
PMU register
Bit name
DCG_PM_1
value
0x*0*****3
PMU register
Bit name
DCG_PM_1
value
0x0******3
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6. Precaution for Usage
6.1. Access Restriction Associated with Register Access
The registers in this module are assigned to a 4 KB space with 32-bit interval in the little endian
format. The bit allocations are as follows.
This module is connected to the bus with 32-bit wide. When 8-bit or 16-bit data is accessed, the
operation is in units of 32-bit only. This means that 8-bit or 16-bit access results in reading or
writing the other bits than the content bits. So, 32-bit access is recommended. Otherwise, a read
error or a write error may occur.
The register whose valid bits are clearly defined (for example, only the lower 16 bits exists) can be
also accessed with other than 32-bit wide.
The write to a non-existing bit in a register is ignored. The read of the bit returns 0.
bit
31
Low
Low
Low
Low
Low
Low
Low
address0:
address1:
address2:
address3:
address0:
address2:
address0:
write 8bit
write 8bit
write 8bit
write 8bit
write 16bit
write 16bit
write 32bit
15
7
Reg0[7:0]
Reg1[7:0]
Reg2[7:0]
Reg3[7:0]
Reg0[15:0]
Reg2[15:0]
Reg3[31:0]
valid bits
invalid bits
31
Low
Low
Low
Low
Low
Low
Low
address0:
address1:
address2:
address3:
address0:
address2:
address0:
read
read
read
read
read
read
read
8bit
8bit
8bit
8bit
16bit
16bit
32bit
15
7
Reg0[7:0]
Reg1[7:0]
Reg2[7:0]
Reg3[7:0]
Reg0[15:0]
Reg2[15:0]
Reg3[31:0]
valid bits
invalid bits
Figure 6.1 Bit allocation of register access
6.2. Precaution for Dynamic Clock Gating
When the dynamic clock gating is set, the following should be noted. When the interrupt generation
and the interrupt cause are cleared, the SPIM operating clock (ssi_clk) is necessary. The clear can
be done only when the operation is enabled (SSI_EN = 1 in the register [SPIMn_SSIENR] (n is a
channel number: 0, 1, 2, or 3)).
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6.3. Precaution for through-current on MOSI pin
When the I/O pin assigned to MOSI function is neither pulled up nor pulled down with a register,
through-current could flow through the above I/O or the I/O of the connected device, because the
SPIM can turn off the output driver of the IO cell. To prevent the through-current, please enable the
pull-up or pull-down of the I/O cell assigned to MOSI function by setting GCONF registers before
use of SPIM. Please note that this procedure is not necessary if pull-up or pull-down register is
connected MOSI pin on your board.
6.4. Precaution for BUSY status
The BUSY status is not set when the data are written into the transmit FIFO. This bit gets set
only when the target slave has been selected and the transfer is underway. After writing data
into the transmit FIFO, the shift logic does not begin the serial transfer until a positive edge of
the sclk_out signal is present. The delay in waiting for this positive edge depends on the baud
rate of the serial transfer. Before polling the BUSY status, you should first poll the TFE status
(waiting for 1) or wait for BAUDR * ssi_clk clock cycles.
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7. Revision History
Revision
0.1
0.2
Date
2014-03-14
2014-03-17
0.4
2014-07-14
0.5
2014-09-29
0.6
2014-10-17
0.7
2014-12-05
0.8
2015-01-20
1.0
2015-01-22
2015-01-22
Table 7.1 Revision History
Description
Newly released
Modified copyright notation.
Added ARM and Synopsys copyright notation.
Added .Setting GCONF: OE_CTRL register.
Modified references of shared pin information.
Added precaution for through-current on MOSI pin.
Modified 7.3. Precaution for through-current on MOSI pin section.
Modified the list of supported transfer format and removed
description about collision detection support. (See Errata #39.)
Modified 6.8.2 Stop procedure.
Added precaution for BUSY status.
Official version
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• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to
any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR
LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND
LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO
SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation,
for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology
products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export
laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export
Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in
compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES
OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
2015-01-22
46 / 46
Rev.1.0

TZ1000 Series

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