Getting Started with Reconfigurable Logic

Getting Started with Reconfigurable
Logic
(CPLDs and FPGAs)
Prepared By Dr. Hossam Eldin Mostafa
Alexandria University, Faculty of Engineering, Alexandria, Egypt
www.cs.ucf.edu/~ahossam/
Main
CPLD Starter Kit
Hardware
Software
Examples
Documentation
Block diagram of XC9500 series
Pin diagrams XC9536-PC44
XC9536 Datasheet
PLCC Socket
This page is last updated on 1st December 2003
Getting Started with Reconfigurable
Logic
(CPLDs and FPGAs)
What is CPLD
A lot of logic devices are housed in CPLD and those connections can be specified by the program. For example, in case of the 7400 IC, 4 circuits
of 2 input NAND gate are housed. In case of 7404, 6 circuits of inverter are housed. These are separate IC. Therefore, to compose a circuit, it is
necessary to do each wiring among the pins using the printed board. In case of CPLD, it has wiring among the logic in the IC. So, the wiring on
the printed board can be made little.
The capacity of CPLD is limited. There is limitation on the number of the pins, too. So, don't do excessive expectations. The outline
specification of the part of the XC9500 series of Xilinx Inc. is shown below.
Parts name
XC9536-15PC44C
XC9572-15PC44C
XC9572-15PC84C
XC95108-15PC84C
Number of pins
44pin PLCC
44pin PLCC
84pin PLCC
84pin PLCC
Specification
2FB/36macrocells/800gates
4FB/72macrocells/1600gates
4FB/72macrocells/1600gates
6FB/108macrocells/2400gates
The point which CPLD is convenient for is the thing about which it is possible to rewrite many time because it is recording the
contents of the circuit to the flash memory. In the XC9500 series, rewriting in about 10,000 times is said to be possible. Also, because
the pin for the rewriting is preparatory, the contents can be rewritten in the condition to have mounted to the actual circuit if there is
wiring (In Circuit Programming).
Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLDs. The concept is to have a
few PLD blocks or macrocells on a single device with general purpose interconnect in between. Simple logic paths can be
implemented within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in
between to make these connections.
CPLDs are great at handling wide and complex gating at speeds e.g. 5ns which is equivalent to 200MHz. The timing model for
CPLDs is easy to calculate so before you even start your design you can calculate your in to output speeds.
Why use a CPLD
1- Ease of Design:
CPLDs offer the simplest way to implement design. Once a design has been described, by schematic and/or HDL entry, a designer
simply uses CPLD development tools to optimise, fit, and simulate the design. The development tools create a file, which is then used
to customise (program) a standard off-the-shelf CPLD with the desired functionality. This provides an instant hardware prototype and
allows the debugging process to begin. If modifications are needed, design changes are just entered into the CPLD development tool,
and the design can be re-implemented and tested immediately.
2- Lower Development Costs:
CPLDs offer very low development costs. Ease of design, as described above, allows for shorter development cycles. Because CPLDs
are re-programmable, designers can easily and very inexpensively change their designs. This allows them to optimise their designs
and continues to add new features to continue to enhance their products. CPLD development tools are relatively inexpensive and in
the case of Xilinx, are free. Traditionally, designers have had to face large cost penalties such as re-work, scrap, and development
time. With CPLDs, designers have flexible solutions thus avoiding many traditional design pitfalls.
3- More Product Revenue:
CPLDs offer very short development cycles, which means your products get to market quicker and begin generating revenue
sooner. Because CPLDs are re-programmable, products can be easily modified using ISP over the Internet. This in turn allows you to
easily introduce additional features and quickly generate new revenue from them. (This results in an expanded time for revenue).
Thousands of designers are already using CPLDs to get to market quicker and then stay in the market longer by continuing to
enhance their products even after they have been
introduced into the field. CPLDs decrease Time To Market (TTM) and extend Time In Market (TIM).
4- Reduced Board Area:
CPLDs offer a high level of integration (large number of system gates per area) and are available in very small form factor packages.
This provides the perfect solution for designers of products which must fit into small enclosures or who have a limited amount of
circuit board space to implement the logic design. The CoolRunner? CPLDs are available in the latest chip scale packages, e.g. CP56
which has a pin pitch of 0.5mm and is a mere 6mm by 6mm in size so are ideal for small, low power end products.
5- Cost of Ownership:
Cost of Ownership can be defined as the amount it costs to maintain, fix, or warranty a product. For instance, if a design change
requiring hardware rework must be made to a few prototypes, the cost might be relatively small. However, as the number of units
that must be changed increases, the cost can become enormous. Because CPLDs are re-programmable, requiring no hardware
rework, it costs much less to make changes to designs implemented using them. Therefore cost of ownership is dramatically
reduced. And don't forget the ease or difficulty of design changes can also affect opportunity costs. Engineers who are spending a lot
of time fixing old designs could be working on introducing new products and features - ahead of the competition. There are also
costs associated with inventory and reliability. PLDs can reduce inventory costs by replacing standard discrete logic devices.
Standard logic has a predefined function and in a typical design lots of different types have to be purchased and stocked. If the
design is changed then there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs i.e. you only
need to stock one device and if your design changes you simply reprogram. By utilising one device instead of many your board
reliability will increase by only picking and placing one device instead of many. Reliability can also be increased by using the ultra
low power CoolRunner CPLDs i.e. lower heat dissipation and lower power operation leads to decreased Failures In Time (FIT).
In 1985, a company called Xilinx introduced a completely new idea. The concept was to combine the user control and time to market
of PLDs with the densities and cost benefits of gate arrays. A lot of customers liked it - and the FPGA was born. Today Xilinx is still
the number one FPGA vendor in the world! An FPGA is a regular structure of logic cells? or modules and interconnect which is
under the designer’s complete control. This means the user can design, program and make changes to his circuit whenever he
wants. And with FPGAs now exceeding the 10 million gate limit (Xilinx Virtex? II is the current record holder), the designer can
dream big!
CPLD Starter Kit
What is included
The components listed in the following table are included with the starter kit (The images of the components are shown in the
above image)
Download the above table in PDF format (kit_components.pdf) or in Exel format (kit_components.xls)
What is NOT included
The following components are NOT included with the starter kit.
1- +5v Power Supply
2- Parallel Port Adaptor
OR
Parallel Port Male Connector
4- DB25 Male -Female Cable
5- Bread Boards
6- Connecting Wires
HARDWARE
JTAG Parallel Port Programmer
To download the the schematic in PDF format click here jtag.pdf
(All the components are included with the starter kit)
CPLD Board
To download the the schematic in PDF format click here xc9536.pdf
(All the components are included with the starter kit)
Application Board
To download the the schematic in PDF format click here application.pdf
(Components are NOT included with the starter kit)
Whole System
D
VCC SENSE
DONE
PROG
DIN
CTRL
CLK
TMS_IN
4
3
C3
100p
C4
100p
D3
LED
R1
1K
120
R10
120
R9
120
R8
120
R7
C1
22n
2
D1
9
U1C
3
U2A
6
U2B
11
U5D
8
U2C
C2
100p
D2
2
5
12
9
C5
100p
U1D
U1B
6
R4
R2
1K
5
1N4004
R5
120
R6
120
R11
330
R12
330
R13
330
R14
330
R15
330
3
U1A
R3
5.6K
11
1N4004
8
12
120
2
4
5
15(S3)
13(S4)
6(D4)
2(D0)
5(D3)
3(D1)
4(D2)
8(D6)
11(*S7)
12(S6)
DB-25 PARALLEL PORT CONNECTOR
25(GND)
10
1
4
13
10
5
4
3
2
VCC
GND
VCC
1
GND
TDI
TDO
DIN
TCK
D/P
CCLK
TMS
VCC pin14
GND pin 7
74LS125
74HC125
CPLD
HEADER
*PROG
FPGA
HEADER
Notes:
U1
U2
U1 and U2 power:
1
Dr. Hossam Eldin Mostafa (www.cs.ucf.edu/~ahossam)
Alexandria University, Faculty of Engineering, Alexandria, Egypt
jtag.opj
November 2003
Xilinx CPLD & FPGA Parallel Port Programmer
13
C
B
A
1
D
C
B
A
D
5
4
TDO
TDI
TCK
3
VCC
32
XC9536 CPLD
30
15
17
TMS
VCCIO
U1
VCC = 5VDC
Programmer_TDO
Programmer_TDI
Programmer__TCK
16
GND
5
4
GTS1(I/O)
GTS2(I/O)
GCK1(I/O)
GCK2(I/O)
GCK3(I/O)
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
U1
13
14
18
19
20
22
24
25
1
2
3
4
8
9
11
12
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PD0
PD1
PD2
PD3
26
27
28
29
33
34
35
36
37
38
43
44
2
2
VCC
R1
1K
D1
LED
1
1
Dr. Hossam Eldin Mostafa (www.cs.ucf.edu/~ahossam)
Alexandria University, Faculty of Engineering, Alexandria, Egypt
xc9536.opj
November 2003
Programmer_TMS
39
41
GSR(I/O)
VCC
31
42
40
GND
23
XC9536 CPLD BOARD
5
6
7
21
GND
C
B
A
VCC
10
D
C
B
A
VCC
5
R20
1K
D9
LED
R19
6.8k
5
12
13
C2
33p
11
U1D
Y1 12M
R18
3.3K
e
4
f
c
b
R9
330
a
VCC
g
d
VCC
gf e dc ba
9
10
U1C
8
7 SEGMENT MODULE
C1
33p
CLOCK GENERATOR MODULE
4
CLK_OUT
3
R17
10K
D1
2
D2
LED
L0
D3
LED
L1
D4
LED
L2
D5
LED
L3
D6
LED
R1
330
L4
D7
LED
R2
330
L5
D8
LED
R3
330
L6
LED
R4
330
VCC
R12
10K
R10
10K
DIP SWITCHES MODULE
SW DIP-4
SW1
R11
10K
R5
330
LED MODULE
P3 P2 P1 P0
R13
10K
R6
330
R14
10K
R7
330
R15
10K
R8
330
L7
VCC
R16
10K
PUSH BUTTONS MODULE
3
2
1
S3 S2 S1 S0
1
Dr. Hossam Eldin Mostafa (www.cs.ucf.edu/~ahossam)
Alexandria University, Faculty of Engineering, Alexandria, Egypt
November 2003
application.opj
APPLICATION BOARD
8
7
6
5
1
2
3
4
D
C
B
A
14
7
D
C
B
A
XILINX WebPACK Tutorial
Prepared by Dr. Hossam Eldin Mostafa
Faculty of Engineering, Alexandria University, Alexandria, Egypt.
(www.cs.ucf.edu/~ahossam/)
The Xilinx Inc. is providing the software tools to design CPLDs and FPGAs.This software is called WebPACK.
WebPACK is available free-of-charge by registering. You can download them from the XILINX site www.xilinx.com.
As for the WebPACK tool, a new type is released in order. Therefore, the operation is may be a little bit different from the tool which
is introduced on this webpage.
This section is a step by step approach to your first simple design. The following pages are intended to demonstrate the basic PLD
design entry and implementation process. In this example tutorial a simple HEX to seven segment decoder is designed in VHDL.
The design is initially targeted at a XC9536 CPLD.
Example Project
In this example(see the left image), we will design a Hex to seven segment decoder. The circuit accepts 4 binary bits as inputs (I3 I2 I1
I0) and produces 7 binary bits as outputs (O6 O5 O4 O3 O2 O1 O0). It is directed to derive a common anode seven segment display.
The right image shows the test circuit for this design using XC9536, DIP switches modules to generate the inputs and the seven
segment module to see the outputs. The pin out os the CPLD is illustrated and will be defined in the VHDL program. You can
download the above image in PDF format from decoder.pdf
The VHDL file that will be writtrn can be downloaded here decoder.vhd.
The whole Webpack project can be downloaded from here decoder.zip
Developing the project using WebPACK
Start WebPACK ISE Software
Select Start > Programs > Xilinx WebPACK > WebPACK Project Navigator. The following window will be displayed.
Sources in Project is the window to display a device name, a source module name and so on. Processes for Current Source is
the window to display a various function menu. The window on the right( HDL Editor workspace window ) is the window to
display a source code. The window most below( Transcript window ) is the window to display the log of the processing elapse
Creat a New Project
It is recommended that you create the folder which stores files of the project before beginning work. I made a folder which stores the
related files of the test project as C:\CPLD_projects\. Select File -> New Project… the dialog of the project creation of file is
displayed.
A Project Name, the place which saves a project, the kind of the device and the language to use and so on are set by this dialog.
Click Value of the device and the language to use and choose the contents which fit in from the displayed pull-down menu. Sources
in Project of Project Navigator changes when the registration of the project is done.
Other device families can be chosen here including FPGAs. Even if the flow is intended to be purely schematic, the schematic
diagram will be converted into HDL and synthesised through the chosen synthesis tool.
You can change the title of the project by choosing Source -> Properties or double-clicking
Making of a source file
A source type selection dialog is displayed when choosing Project -> New Source or clicking the
Select "VHDL Module" from the displayed item. When using a language except VHDL, select a corresponding language. Type "File
Name", and confirm the file saving path of "Location" and click "Next".
Type "Entity Name" and "Architecture Name". The ports can be specified by this dialog. However, in this example we specifie
them by the description of VHDL from behind. Click "Next" without assigning the ports. This table automatically generates the entity
in the decoder VHDL module. Following confirmation screen is displayed. Click "Finish" if there is not mistake in the contents.
The window (HDL Editor window) of the source code is displayed in HDL Editor workspace window of Project Navigator
Display or non-display of each window can be controlled with the View menu.
To spread a source code window, click Project Workspace of the View menu and removes checking. You can expand by clicking
, too. To make display a source code window in whole HDL Editor workspace window, click the window maximization
button in the upper right like usual window control. The basic part of the format of VHDL is already written in the displayed source
code window.
This time, you adde the following to entity and architecture to implement the decoder.
You can download the VHDL file from decoder.vhd
After doing the above-mentioned change, save a file by File -> Save or by the
the input and output pins of the CPLD inside the VHDL file.
button. The attribute keyword is used to define
Syntax check
By the following operation, the grammar of the made source file is confirmed. Double-click "Check Syntax" which is displayed in the
Process for Current Source window. This has the checking of format (Syntax). If the checking result is to be OK, Check Syntax
has a green checking mark. Also, "Done: completed successfully." is displayed in the end of the situation display window.
When checking a format without saving a file, the following dialog which shows that a file isn't saved is displayed. It is saved if you
click "Yes".
I attempt to make an intentional error occur as the example. I delete the last semicolon(;) of the port declaration of entity and I attempt
to execute Check Syntax
Check Syntax has a red X mark. Also, "Done: failed with exit code: 0001." is displayed in the end of the situation display window.
The position of the error can be known with the situation display window.
ERROR : (VHP__0162). C:\CPLD_projects\decoder\decodr.vhd Line 11. Read symbol ATTRIBUTE, expecting ';'.
An error is detected at the 11th line. When double-clicking , the mark which shows an error on the left side of the source code is
displayed. Because the mark shows the line which detected an error. So, check previous lines and so on.
Fitting
the file which will be written to the CPLD is generated fron the VHDL file using this process. Double-click "Fitter" which is displayed
at the Process for Current Source window. The fitting processing begins with this operation.
Fit Design has a green checking mark if the fitting result is to be OK. Also, "Done: completed successfully" is displayed in the end
of the situation display window.
The Confirmation of the Fitting Result
In case of complicated circuits, the various data must be confirmed. This time, we confirm the situation of the assigned pin.
Double-click Fitter Report which is displayed in the Process for Current Source window. A report window is displayed. There is
following figure in it. This figure shows the assignment of the pins.
If we did not predefine the inputs and output pins (using the attribute keyword), the tool will selecting pins automatically. So, the
design may not look neat.
In the Fitter report, the usage of the CPLD resources are listed as shown below
Invoking the Programmer
Note that the JTAG Parallel Port programmer will work directly on Windows 98. On Windows XP, 200, NT, some drivers may be
needed so try to use the programmer on Win98 Operating System.
The operation after this is the work to do after connecting a personal computer and CPLD device with the JTAG programmer (You
will build this programmer using the components supplied with the kit). Double-click Configure Device (iMPACT) which is
displayed at the Process for Current Source window.
The window of JTAG Programmer is shown below.
When using the parallel port of the PC, it specifies Parallel by Output -> Cable Setup -> Cable Communication Setup. Data is
transferred to CPLD if pushing the OK button. When a cable isn't connected, it becomes an error.
Select the CPLD (using the left mouse button) and right click the mouse to choose the operation or select Operations from the main
menu
The first operation is to erase the CPLD
It will ask you if you want to override the write protect. Select OK
Sometimes due to the parallel cable exessive length or another unknown reasons, the program hangs and does not say that it
completes the erasure successfully. Actually, it erases the CPLD successfully. But you should press CTRL + ALT + DEL and end the
programmer task and invoks it again by clicking on the iMPACT in the WebPACK project navigator.
Select the CPLD and with the mouse right button, choose Blank Check to check if the device has been erased successfully
If the devie has been erased, the Device is Blank message will be displayed
To program the device, select it with the left mouse button and with the right mouse button, choose Program
Unckeck the Erase Before Programmin box(Because we have already erased the device). Make sure that Verify box is checked.
When you do so, the following dialog will appear informing you that programming the device before erasing it may harm the
device. Discard this message and press OK and then press OK on the Programming window.
A progress bar appears indicating the progress of the programming.
When programming is OK, a Programming Succeded message appears.
Now, you can try the program you have just downloaded if you connect the CPLD inputs to the DIP switched and the CPLD outputs
to the seven segment,
Block diagram of XC9500 series
You can jump to the page of the explanation when you click the part where the pointer become the hand.
If you want to know more detailed specification, refer to the following PFD file.
I/O Blocks
An I/O block is composed of input buffer, output buffer,
multiplexer for the output control and grounding control and so on.
Multiplexer for the output control(OE MUX) controls an output
enable or stop. It is controlled by the signal from the macrocell or the
signal of the GTS(Global Three-State control) pin. It can always
make output '1' or '0', too. There are four GTS in XC95216 and
XC95288 and in case of the other device, they are two.
A slew rate control is the one to make the rising and the falling of
the output pulse smooth. It is used when suppressing the occurrence
of the noise.
A grounding control is used when making input/output pin (I/O)
an earth terminal. In case of the circuit where much noise occurs, it
isn't sometimes possible to do noise reducing by the standard earth
terminal.
At the actual circuit, a pull-up resistor is more connected with the
input/output pin. This circuit makes an input/output pin '1'
condition compulsorily during programming of CPLD to make an
influence by the condition of the I/O pin little. This circuit is detached
in usual operation
in usual operation.
Each input/output pin can handle a 24-mA current.
FastCONNECT Switch Matrix
FastCONNECT Switch Matrix controls the input signals to the
Function Block.
All the signals from the input-output port and the signals of the
Function Block are connected with FastCONNECT Switch
Matrix. The signals which are specified by the program out of
these signals are applied to the Function Block. The output
signals from the Function Block are applied to the Function
Block through the wired AND buffer. This provides additional
logic capability and increases the effective logic fan-in of the
destination Function Block without any additional timing delay.
It is automatically invoked by the development software where
applicable.
Function Block
Function block is composed of the programmable AND
array, product term allocator and macrocell.
36 pieces of signals inputted to the Function Block are
divided into the true and complement signals by the
programmable AND array and become 72 kinds of
signals.
In Product Term Allocator, it applys the signal with
combination of them to the macrocell.
A macrocell is composed of one D/T type flip-flop. The
signals of set/reset/clock to this flip-flop are supplied by
the Product Term Allocator.
The output of the logic circuit can be connected with the
pin without using a flip-flop, too.
need.
There are 18 independent macrocells in one Function
Block.
There are 18 pieces of output in the Function Block and
they are connected with FastCONNECT Switch Matrix
and I/O blocks. Also, the set/reset signal(GSR : Global
Set/Reset) and the clock signal(GCK : Global Clocks) are
inputted to the Function Block and are used for the
condition of the operation of the flip-flop according to
PTOE(Product Term Output Enable) signal is output to I/O block from Product Term Allocator.
The number of the Function Blocks depends on the device. As for XC9536, 2 blocks are mounted, as for XC9572, 4 blocks are mounted and as for XC95108, 6
blocks are mounted.
It isn't sometimes possible to use all macrocells by the limitation on the number of the pins. For details, confirm pin diagrams. There are few cases which connect all
macrocells with the pin actually. Generally, there are macrocells to use only in the logic inside.
In-System Programming
XC9500 devices are programmed in-system via a standard 4-pin
JTAG(Joint Test Action Group) protocol. The devices fully support
IEEE 1149.1 boundary-scan(JTAG).
Because it is equipped with the pin for independent JTAG, the
program can be changed as it mounted CPLD on the printed
board.
While programing, all input ports in the I/O block are set to the 'H'
level.
The wires to use in JTAG are the following four. Each use is shown
below.
TMS(Test Mode Select):
This signal is decoded by the TAP controller to control test
operations.
TCK(Test Clock):
This clock drives the test logic for all devices on
boundary-scan chain.
TDI(Test Data In):
This signal is used to transmit serial test instructions and
data.
TDO(Read Data):
Read back data from the target system is read at this pin.
Pin diagrams ( XC9536-PC44/XC9572-PC44 )
The figure on the left is the top view of CPLD of 44 pins.
The following item is used to know the position of the pin.
*The direction of the printed name.
*A corner in the upper left is shaved.
A pin numbering is counterclockwise given from the center of the line in the topside.
Note is necessary to the pin arrangement by the Function Block and the macrocell
because it a little irregular-ly.
In case of XC9536-PC44, the macrocells which corresponds to the input/output pins are
34 macrocells in the 36 macrocells.
In case of XC9572-PC44, they are 34 macrocells in the 72 macrocells.
The macrocells which don't correspond to the input/output pins can be used only in the
logic circuits inside.
The pins colored purple are pins for JTAG.
Pin Diagram of XC9536-15PC44C
FB : Function Block number
Pin
number
FB Macrocell
Pin
number
FB Macrocell
1
2
1
23
GND
2
1
1
24
1
17
3
1
2
25
2
17
4
1
4
26
2
16
1
3
27
2
15
28
2
14
29
2
13
5
GCK1
6
1
5
GCK2
7
1
7
GCK3
8
1
6
30
TDO
9
1
8
31
GND
10
GND
32
VccIO 3.3V/5V
11
1
9
33
2
12
12
1
10
34
2
11
13
1
11
35
2
10
14
1
12
36
2
9
15
TDI
37
2
8
16
TMS
38
2
7
17
TCK
39
2
6
GSR
18
1
13
40
2
5
GTS2
19
1
14
41
20
1
15
42
VccINT 5V
2
3
GTS1
21
VccINT 5V
43
2
4
22
1
44
2
2
16
Pin Diagram of XC9572-15PC44C
FB : Function Block number
Pin
number
FB Macrocell
Pin
number
FB Macrocell
1
1
2
23
GND
2
1
5
24
4
2
3
1
6
25
4
5
4
1
8
26
4
8
1
9
27
4
9
28
4
11
29
4
14
5
GCK1
6
1
11
GCK2
7
1
14
GCK3
8
1
15
30
TDO
9
1
17
31
GND
10
GND
32
VccIO 3.3V/5V
11
3
2
33
4
15
12
3
5
34
4
17
13
3
8
35
2
2
14
3
9
36
2
5
15
TDI
37
2
6
16
TMS
38
2
8
17
TCK
39
2
9
GSR
18
3
11
40
2
11
GTS2
19
3
14
41
20
3
15
42
VccINT 5V
2
14
GTS1
21
VccINT 5V
43
2
15
22
3
44
2
17
17
9
1
XC9536 In-System Programmable
CPLD

December 4, 1998 (Version 5.0)
1
1*
Product Specification
Features
Power Management
•
•
5 ns pin-to-pin logic delays on all pins
fCNT to 100 MHz
•
•
•
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5 V in-system programmable (ISP)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3 V or 5 V I/O capability
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
CSP packages
Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
•
•
•
•
•
•
•
•
•
•
ICC (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC9536 device.
(83)
ance
erform
High P
Typical ICC (mA)
•
•
Operating current for each design can be approximated for
specific operating conditions using the following equation:
(50)
(50)
ower
Low P
(30)
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture overview.
December 4, 1998 (Version 5.0)
0
50
Clock Frequency (MHz)
100
X5920
Figure 1: Typical ICC vs. Frequency For XC9536
1
XC9536 In-System Programmable CPLD
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
36
18
I/O
Function
Block 1
Macrocells
1 to 18
I/O
I/O
I/O
Blocks
I/O
I/O
I/O
FastCONNECT Switch Matrix
I/O
36
18
Function
Block 2
Macrocells
1 to 18
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
X5919
Figure 2: XC9536 Architecture
Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly
2
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
VCC
VIN
VTS
TSTG
TSOL
Warning:
Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 s @ 1/16 in = 1.5 mm)
Value
Units
-0.5 to 7.0
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
-65 to +150
+260
V
V
V
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.
Recommended Operating Conditions
Symbol
1
Parameter
VCCINT
Supply voltage for internal logic and input buffer
VCCIO
Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
VIL
VIH
VO
Min
Max
Units
4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0
5.25
(5.5)
5.25 (5.5)
3.6
0.80
VCCINT +0.5
VCCIO
V
V
V
V
V
V
Note 1. Numbers in parenthesis are for industrial-temperature range versions.
Endurance Characteristics
Symbol
Parameter
tDR
Data Retention
NPE
Program/Erase Cycles
December 4, 1998 (Version 5.0)
Min
Max
Units
20
-
Years
10,000
-
Cycles
3
XC9536 In-System Programmable CPLD
DC Characteristics Over Recommended Operating Conditions
Symbol
VOH
Parameter
Test Conditions
Min
Output high voltage for 5 V operation
IOH = -4.0 mA
VCC = Min
Output high voltage for 3.3 V operation IOH = -3.2 mA
VCC = Min
Output low voltage for 5 V operation
IOL = 24 mA
VCC = Min
Output low voltage for 3.3 V operation IOL = 10 mA
VCC = Min
Input leakage current
VCC = Max
VIN = GND or VCC
I/O high-Z leakage current
VCC = Max
VIN = GND or VCC
I/O capacitance
VIN = GND
f = 1.0 MHz
Operating Supply Current
VI = GND, No load
(low power mode, active)
f = 1.0 MHz
VOL
IIL
IIH
CIN
ICC
Max
Units
2.4
V
2.4
V
0.5
V
0.4
V
±10.0
µA
±10.0
µA
10.0
pF
mA
30 (Typ)
AC Characteristics
Symbol
Parameter
tPD
tSU
tH
tCO
fCNT1
fSYSTEM 2
tPSU
tPH
tPCO
tOE
tOD
tPOE
tPOD
tWLH
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock to output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
XC9536-5
XC9536-6
XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
5.0
3.5
0.0
6.0
3.5
0.0
4.0
100.0
100.0
0.5
3.0
4.0
100.0
100.0
0.5
3.0
7.0
5.0
5.0
9.0
9.0
4.0
7.5
4.5
0.0
4.5
83.3
83.3
0.5
4.0
7.0
5.0
5.0
9.0
9.0
4.0
10.0
6.0
0.0
6.0
66.7
66.7
2.0
4.0
8.5
5.5
5.5
9.5
9.5
4.0
15.0
8.0
0.0
8.0
55.6
55.6
4.0
4.0
10.0
6.0
6.0
10.0
10.0
4.5
12.0
11.0
11.0
14.0
14.0
5.5
Units
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note: 1. fCNT is the fastest 16-bit counter frequency available.
fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG.
2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
4
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
VTEST
R1
Output Type
Device Output
R2
VCCIO
VTEST
R1
R2
CL
5.0 V
5.0 V
160 Ω
120 Ω
35 pF
3.3 V
3.3 V
260 Ω
360 Ω
35 pF
CL
X5906
Figure 3: AC Load Circuit
Internal Timing Parameters
Symbol
Parameter
Buffer Delays
tIN
Input buffer delay
tGCK
GCK buffer delay
tGSR
GSR buffer delay
tGTS
GTS buffer delay
tOUT
Output buffer delay
tEN
Output buffer enable/disable delay
Product Term Control Delays
tPTCK Product term clock delay
tPTSR Product term set/reset delay
tPTTS Product term 3-state delay
Internal Register and Combinatorial delays
tPDI
Combinatorial logic propagation delay
tSUI
Register setup time
tHI
Register hold time
tCOI
Register clock to output valid time
tAOI
Register async. S/R to output delay
tRAI
Register async. S/R recovery before clock
tLOGI
Internal logic delay
tLOGILP Internal low power logic delay
Feedback Delays
tF
FastCONNECT matrix feeback delay
Time Adders
tPTA3
Incremental Product Term Allocator delay
tSLEW Slew-rate limited delay
XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15
Min Max Min Max Min Max Min Max Min Max
Units
1.5
1.5
4.0
5.0
2.0
0.0
1.5
1.5
4.0
5.0
2.0
0.0
2.5
1.5
4.5
5.5
2.5
0.0
3.5
2.5
6.0
6.0
3.0
0.0
4.5
3.0
7.5
11.0
4.5
0.0
ns
ns
ns
ns
ns
ns
3.0
1.0
5.5
3.0
1.0
5.5
3.0
2.0
4.5
3.0
2.5
3.5
2.5
3.0
5.0
ns
ns
ns
0.5
1.5
0.5
1.0
3.0
1.0
9.0
1.0
9.0
2.0
10.0
2.5
11.0
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
6.0
6.0
8.0
9.5
11.0
ns
0.8
3.5
0.8
3.5
1.0
4.0
1.0
4.5
1.0
5.0
ns
ns
2.5
1.0
2.5
1.0
0.5
6.0
5.0
1.5
3.0
0.5
6.0
5.0
2.5
3.5
0.5
6.5
7.5
3.5
4.5
0.5
7.0
10.0
0.5
8.0
10.0
Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet.
December 4, 1998 (Version 5.0)
5
XC9536 In-System Programmable CPLD
XC9536 I/O Pins
Function
Macrocell
Block
PC44
1
1
2
1
2
3
1
3
5
1
4
4
1
5
6
1
6
8
1
7
7
1
8
9
1
9
11
1
10
12
1
11
13
1
12
14
1
13
18
1
14
19
1
15
20
1
16
22
1
17
24
1
18
–
Note: [1] Global control pin
VQ44
CS48
40
41
43
42
44
2
1
3
5
6
7
8
12
13
14
16
18
–
D6
C7
B7
C6
B6
A6
A7
C5
B5
A4
B4
A3
B2
B1
C2
C3
D2
-
BScan
Notes
Order
105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
[1]
[1]
[1]
Function
Macrocell
Block
PC44
2
1
1
2
2
44
2
3
42
2
4
43
2
5
40
2
6
39
2
7
38
2
8
37
2
9
36
2
10
35
2
11
34
2
12
33
2
13
29
2
14
28
2
15
27
2
16
26
2
17
25
2
18
Note: [1] Global control pin
VQ44
CS48
39
38
36
37
34
33
32
31
30
29
28
27
23
22
21
20
19
-
D7
E5
E6
E7
F6
G7
G6
F5
G5
F4
G4
E3
F2
G1
F1
E2
E1
-
BScan
Notes
Order
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0
[1]
[1]
[1]
XC9536 Global, JTAG and Power Pins
6
Pin Type
PC44
VQ44
CS48
I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
TDI
TDO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GND
No Connects
5
6
7
42
40
39
17
15
30
16
21,41
32
23,10,31
—
43
44
1
36
34
33
11
9
24
10
15,35
26
17,4,25
—
B7
B6
A7
E6
F6
G7
A1
B3
G2
A2
C1,F7
G3
A5, D1, F3
C4, D3, D4, E4
December 4, 1998 (Version 5.0)
XC9536 In-System Programmable CPLD
Ordering Information
XC9536 -5 PC 44 C
Device Type
Temperature Range
Number of Pins
Speed
Package Type
Packaging Options
Speed Options
-15
-10
-7
-6
-5
PC44 44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Thin Quad Pack (VQFP)
CS48 48-Pin Chip Scale Package (CSP)
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7.5 ns pin-to-pin delay
6 ns pin-to-pin delay
5 ns pin-to-pin delay
Temperature Options
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
Component Availability
Pins
44
Type
Code
XC9536
–15
–10
–7
–6
–5
Plastic
PLCC
PC44
C,I
C,I
C,I
C
C
Plastic
VQFP
VQ44
C,I
C,I
C,I
C
C
48
Plastic
CSP
CS48
C
C
C
C = Commercial (0°C to +70°C), I = Industrial (–40°C to +85°C)
Revision Control
Date
6/3/98
11/2/98
12/04/98
Reason
Revise datasheet to reflect new CSP package pinouts & ordering code.
Revise datasheet to reflect new AC characteristics and Internal Timing Parameters.
Revise datasheet to remove PCI compliancy statement and remove tLF.
December 4, 1998 (Version 5.0)
7
PLCC socket
PLCC socket is used to mount CPLD device on the printed board. PLCC is the abbreviation of "Plastic Leaded Chip Carrier".
There are lead pins to connect a printed board with the bottom of the socket. Because it is 0.1 inches in the pin interval, it is possible to mount on the universal
printed board, too.
To know the direction of the socket, you see from the top and you make a diagonal corner the upper left. The center of the line in the topside is the 1st pin. I
think that you can find the mark of the triangle which shows the 1st pin inside the socket which puts CPLD.
As for the size of the socket, 44 pins are about 23 mm x 23 mm and 84 pins are about 37 mm x 37mm.
The figure on the left shows a pin diagram of the bottom view for 44 pins.
It is necessary to be careful so as not to make a mistake because there are many numbers
of the pins.
The figure below shows a pin diagram of the bottom view for 84 pins.
Method of removing a device
A thin screwdriver can be used to remove CPLD device from the PLCC socket. There are ditches
for removing at the corner of PLCC socket. Put the tip of the screwdriver in the ditch, and make
the top lift a device and remove it. Do alternately with the side of the opposite angle and lift slowly.
Because there is possibility to give the damage to the device when handling violently, remove it
carefully.