Wafer-to-Wafer Bonding and Packaging

Wafer-to-Wafer Bonding
and Packaging
EE C245
Dr. Thara Srinivasan
Lecture 25
Picture credit: Radant MEMS
U. Srinivasan ©
Lecture Outline
• Reading
• Senturia, S., Chapter 17, “Packaging.”
• Schmidt, M. A. “Wafer-to-Wafer Bonding for
Microstructure Formation,” pp. 1575-1585.
• Tummala, R.R. “Fundamentals of Microsystems
Packaging,” pp. 556-66.
EE C245
• Today’s Lecture
•
•
•
•
MEMS Packaging: Why a Whole Lecture?
Wafer Bonding Methods for MEMS
Bonding Tools and Characterization
Packaging: Die-Level, Wafer-Level…
U. Srinivasan ©
2
1
MEMS and the Package
• Packaging electronics
• Provide electrical interconnects, protect electronics
• Dice up wafer, assemble into ceramic/plastic package
• Single package, many chips
• Packaging MEMS
• Provide electrical (and other, i.e., fluidic, optical) interconnects,
protect micromechanical elements, interface with outside
environment
• Dicing cannot be done after release unless precautions taken
• Environment inside package important
• Package should not mechanically stress MEMS
EE C245
• Single chip, many packages
• Packaging, test and calibration important to MEMS design
3
U. Srinivasan ©
Current MEMS Packages
Die Level
Wafer Level
Wafer bonded package
with glass frit seal and
lateral feedthroughs
(sealed MEMS is then
placed into ceramic
package)
Cronos Relay
Die level release and
ceramic package
Motorola
Accelerometer
CMOS
region
Bosch Gyroscope
EE C245
MEMS
region
U. Srinivasan ©
BSAC/Sandia
Wafer bonded package
with glass frit seal and
lateral feedthroughs
Partial Hexsil cap assembled
onto Sandia iMEMS chip
using wafer-to-wafer transfer4
2
Lecture Outline
MEMS Packaging
Wafer Bonding Methods for MEMS
Bonding tools and characterization
Packaging: die-level, wafer-level…
EE C245
•
•
•
•
5
U. Srinivasan ©
Wafer Bonding in MEMS
• Wafer-level packaging
• MEMS device construction
• Sealed structures, i.e., pressure
sensors and fluidic channels
• Multiwafer structures, i.e., µTAS,
microturbines, optical devices, inkjet
print heads
EE C245
Motorola pressure sensor
U. Srinivasan ©
Jensen group, MIT
MIT microturbine
6
3
Sealed Structures
• Microfluidic channel structures
• Pressure sensors and valves
EE C245
Caliper Technologies
Redwood Microsystems MEMS valve
U. Srinivasan ©
7
Wafer Bonding Methods
EE C245
• Surface bonding
• Metallic layer bonding
• Insulating layer bonding
U. Srinivasan ©
8
4
Fusion Bonding
• Two ultra-smooth (<10 Å roughness) wafers are bonded
without adhesives or applied external forces
• Technique
EE C245
• Surface preparation: O2 plasma, hydration, or HF dip
• Room temperature contacting leads to hydrogen bonding, van
der Waals forces
• Annealing at 600-1200°C brings bond to full strength
• Low temperature fusion bonding also possible using Ziptronix
surface preparation
• Mechanism
• Hydrophilic ~ Si – O – Si
• Hydrophobic ~ Si – Si
Ziptronix
9
U. Srinivasan ©
Anodic Bonding
• Bonds an electron conducting material, Si, to an ion conducting material,
e.g. sodium glass (Pyrex)
• Technique
• Voltage applied ~ 200-1500 V
• Elevated temperature ~ 180-500°C
• Positive ions in glass migrate, creating
depletion layer near Si surface; voltage
drop creates large E-field pulling surfaces
into contact
EE C245
• Pro and con
– CTE mismatch concerns
+ Hermetic sealing
U. Srinivasan ©
10
5
Anodic Bonding
1. after 5 sec
EE C245
Only center bond pin active
2. after 20 sec
All bond pins active
3. after 2,5 min
4. after 8 min
Bond front spreads
Bond 98% completed
ø100 mm,
Pyrex® 500 µm,
430 °C,
800 V,
N2 - 1000
mbar
11
U. Srinivasan ©
Metal Layer Bonding
• Pattern seal rings and bond pads photolithographically
• Eutectic bonding
•
•
+
–
Uses eutectic point in metal-Si phase diagrams to form silicides
Au and Si have eutectic point at 363°C
Low-T process, can bond slightly rough surfaces
Au contamination of CMOS
• Solder bonding
• PbSn (183°C), AuSn (280°C)
+ Lower-T process, can bond really rough surfaces
EE C245
• Thermocompression
•
•
•
+
U. Srinivasan ©
Commonly done with electroplated Au, other soft metals
T ~ room temperature to 300°C
P ~ 1-2 MPa
Lowest-T process, can bond rough surfaces, topography
12
6
Thermocompression Bonding
EE C245
• Transfer of hexsil actuator onto CMOS wafer
Angad Singh, et al.,
Transducers ‘97
U. Srinivasan ©
13
Bonding with Insulating Layers
• Adhesives, i.e.
epoxies, BCB
EE C245
• Glass frit bonding
• Stencil or screen
printed glass paste
• 350-450°C: glass
flows
• Hermetic
• Wide sealing layer
required (500 µm)
U. Srinivasan ©
Screen
Glass Paste
Cap Wafer
Cap Wafer
Glass Frit Frame
Device Wafer
P: 1000 mbar
T: 425°C
Device
14
7
Glass Frit Bonding
EE C245
Packaged
switch by
Radant MEMS
Suss MicroTEC
U. Srinivasan ©
15
Wafer Bonding Methods
Techniques
Flat surface required
Anodic
strong bond
high-voltage
Fusion (Direct)
strong bond
high temp
Surface-activated
varies
varies
Hermetic
Non-flat surface ok
Specific metals required
Eutectic
strong bond
flat surface req’d
Thermocompression
non-flat surface ok
high force
Solder
self-aligning
solder flow possible
Metallic interlayer
Non-flat surface ok
Varies
Glass frit
hermetic
common in MEMS
large area
medium-hi temp
Adhesive
versatile
non-hermetic
Insulating interlayer
EE C245
Drawbacks
Hermetic
“Surface” bonding
U. Srinivasan ©
Advantages
16
8
Lecture Outline
MEMS Packaging
Wafer Bonding Methods for MEMS
Bonding Tools and Characterization
Packaging: Die-Level, Wafer-Level…
EE C245
•
•
•
•
17
U. Srinivasan ©
Bonding Tool
EE C245
Suss SB 6e Bonder
U. Srinivasan ©
18
9
Wafer Bonding Considerations
Topography: planar or textured?
Material: insulating or conducting?
Hermeticity required?
Maximum temperature or force allowed?
Biocompatibility?
EE C245
•
•
•
•
•
19
U. Srinivasan ©
Bond Characterization
• Nondestructive
• Visual inspection
• Imaging ~ IR transmission, ultrasonic, X-ray
topography
X-ray
• Destructive
• Cross-sectional analysis using SEM or TEM
• Defect etching a cross-sectioned sample
• Bond strength measurement techniques
EE C245
• Pressure burst test
• Tensile-shear test
• Knife-edge test
U. Srinivasan ©
Acoustic
IR
20
10
Lecture Outline
MEMS Packaging
Wafer Bonding Methods for MEMS
Bonding Tools and Characterization
Packaging: Die-Level, Wafer-Level…
EE C245
•
•
•
•
21
U. Srinivasan ©
Issues Specific to MEMS Packaging
• MEMS are micromechanical structures
• Damaged during dicing step?
• Package environment important: hermeticity required?
EE C245
• Considerations
•
•
•
•
•
•
U. Srinivasan ©
Bonding method
Stack thickness
Mechanical stress of package
Coefficient of thermal expansion mismatch
Thermal management
Electrical feedthrough method
22
11
Packaging Approaches
EE C245
• Die-level vs. wafer level
23
U. Srinivasan ©
Die Level Packaging
• Conventionally, MEMS have been
diced, then released to protect them
from the sawing process.
• But die-level release is expensive
and slow
Cronos Relay
• Die are then packaged in ceramic
cavity packages.
EE C245
• Ceramic packages are large and
expensive
Fabricate
U. Srinivasan ©
Singulate
Release
Package
Ceramic
Cavity
Package
24
12
Dicing After Release?
EE C245
Analog Devices’
upside-down-saw
process
Texas Instruments’
fabrication and packaging
for DMD chip
25
U. Srinivasan ©
Wafer Level Packaging
• Alternately, do the MEMS release at the wafer level
• Release Æ seal Æ dice
• Wafer level packaging must follow the wafer level release, to
avoid damaging the MEMS.
• Much smaller packages are possible.
Release
EE C245
Fabricate
U. Srinivasan ©
Wafer bond
Chip Scale Package (CSP)
Singulate
26
13
Wafer-level packaged MEMS
Clarisay
surface
acoustic wave
filters
Packaged
gyroscope by
IMEC, Bosch
and STS
EE C245
Packaged
switch by
Radant MEMS
U. Srinivasan ©
27
Wafer-Level MEMS Package Types
• Bulk wafer caps
• Current Industry
standard
• Micro-assembled
hexsil caps
• Berkeley
EE C245
• In situ caps
• Toyota
• Berkeley
U. Srinivasan ©
28
14
Bulk Wafer Caps
• Industry standard, examples:
•
•
•
•
Motorola accelerometers
Bosch gyroscopes
Clarisay SAW filter
Radant MEMS switch
• Pros and cons
EE C245
+
+
+
–
Robust
Hermetic
Wafer-level
Large on-chip area required for
seal ring
29
U. Srinivasan ©
Micro-Assembled Caps
• Fabricate microcaps on donor
wafer
• Transfer microcaps to target
wafer by wafer bonding and
separation
• Thin seal ring requires little
real estate (~1% of bulk cap)
M. Cohn PhD, J. Heck PhD,
Howe group
EE C245
• Potentially much less expensive
than wafer-bonded caps
U. Srinivasan ©
Align
Bond
Separate
30
15
Micro-Assembled Cap Fabrication
• The hexsil process makes “honeycomb” type, high-aspectratio structures from thin film deposition
Recess etch
Electroplate gold bumps & seal ring
EE C245
Deep trench etch
Release etch
Deposit & pattern sacrificial,
structural layers
Thermocompression-bond to target wafer
U. Srinivasan ©
31
Microcap Assembly
CMOS region
MEMS
region
EE C245
Several hexsil caps assembled
onto bare gold die
U. Srinivasan ©
Partial Hexsil cap assembled onto
Sandia iMEMS chip
Heck PhD, Howe group,
Sandia Labs
32
16
In Situ Sealing
• Seal MEMS devices on wafer scale postrelease
• Microshells fabricated over MEMS
• Release etch frees MEMS through access
holes
• Access holes are sealed using film deposition,
possibly at low pressure
+ Simplifies packaging process
– Adds development to fabrication process
T. Corman et al.
EE C245
shell
MEMS
U. Srinivasan ©
Lebouitz et al., BSAC
Toyota
33
Hermeticity
EE C245
• Hermetic package has internal cavity with acceptable level of
gas-tightness
• Metals, glasses, semiconductors are considered hermetic
materials; plastic seals are not
• Getters (certain metal alloys) can absorb and react with gases in
package to keep pressure low
U. Srinivasan ©
T. Corman et al
34
17
Wafer Level Package Interconnects
• Through-silicon vias
+ Small area required
+ True chip scale package (BGA-ready)
– Expensive processing
cap
EE C245
wafer
35
U. Srinivasan ©
Wafer Level Package Interconnects
• Lateral surface feedthroughs
wafer
EE C245
+ Simplest fabrication
– Larger on-chip area required
– Not a true chip scale package
(substrate required)
– Wire bonding required
U. Srinivasan ©
T. Corman
36
18
Wafer Level Package Interconnects
• Hybrid approach, e.g., Shellcase
“T” contact, ChipScale
• Feedthroughs on MEMS wafer are
contacted by sawing through wafer
backside
+ Small area required
+ True chip scale package (BGAready)
– Shellcase proprietary
Top cover wafer
MEMS wafer
Contact pad on the die
External lead
ChipScale
Top cover wafer
MEMS wafer
EE C245
Bottom cover wafer
Shellcase
U. Srinivasan ©
37
Packaging Testing and Failure
• Failure mechanisms
• Delamination, e.g. due to temperature cycling
• Environmental exposure and loss of hermeticity
• Testing hermeticity
EE C245
• Helium leak detection
• Radioisotope method
• IR method
U. Srinivasan ©
38
19
Packaging for Fluidics
• In addition to electronic
interfaces…
• Fluidic interface for
sample introduction
• Optical interface for
detection
• Implantable devices
Cepheid
EE C245
• Biocompatibility
• Don’t shock the patient
U. Srinivasan ©
39
20