DesignCon 2003 How To Apply SERDES Performance To Your Design Article

Transcription

Article
Product Information from Fairchild’s Interface & Logic Group
For more information, visit us at www.fairchildsemi.com
DesignCon 2003
High-Performance System Design Conference
How To Apply SERDES Performance
To Your Design
Edmund H Suckow
Fairchild Semiconductor
Article
Abstract
Applications containing SERDES devices continue to evolve as demand for dense high-speed communication increases.
By compressing numerous data inputs down to differential pairs, increased through-put is achieved in these various
applications. Unfortunately, SERDES device specifications are sometimes difficult to understand and have, in the past, led
designers to operate the devices short of the performance they are capable of. This article covers the typical issues that
arise during a SERDES design, or more importantly, the questions that are mentioned while attempting to select the correct
interface technology for the application at hand.
Author(s) Biography
Ed Suckow is an Applications Engineer for the SERDES product family at Fairchild Semiconductor. He is responsible for
research & definition for SERDES and LVDS technology. He formerly worked in GTLP applications with Fairchild
Semiconductor, power supply design with NASA, and project management for the U.S. ARMY.
Article
Table of Contents
SERDES Introduction........................................................................................................................4
Applications ..................................................................................................................................4
SERDES Definition............................................................................................................................5
PLL Characteristics.......................................................................................................................6
Output Drive .................................................................................................................................7
Encoding.......................................................................................................................................8
Datasheet Specification Review..........................................................................................................8
Jitter..............................................................................................................................................8
Failsafe and Termination Circuitry................................................................................................10
Lock Time...................................................................................................................................11
Media Evaluation.............................................................................................................................12
CAT-5 Cable ..............................................................................................................................13
Printed Circuit Board...................................................................................................................15
SERDES Summary..........................................................................................................................17
Future Roadmap..........................................................................................................................17
Table of Figures
Figure 1. Configuration comparison between multi-drop and point-to-point applications.....................5
Figure 2. Flow diagram for a serializer deserializer pair. .....................................................................6
Figure 3. Clock embedded into serializer output. ...............................................................................6
Figure 4. Flow diagram for Phase Lock Loop (PLL) control circuit....................................................7
Figure 5. Jitter transfer function for serializer....................................................................................10
Figure 6. Typical LVDS termination technique using internal failsafe. ................................................10
Figure 7. LVDS termination technique using external failsafe circuitry. ..............................................11
Figure 8. SERDES 10:1 demo board used in media evaluation.........................................................12
Figure 9. Serialized measurement at deserializer input after 1m of CAT-5, TCLK 40Mhz. ................13
Figure 10. Serialized measurement at deserializer input after 5m of CAT-5e, TCLK 40Mhz. ............14
Figure 11. Serialized measurement at deserializer input after 10m of CAT-5, TCLK 40Mhz. ............15
Figure 12. Serialized signal at deserializer input after 3” of PCB with connectors...............................16
Figure 13. Serialized signal at deserializer input after 16” of PCB with connectors.............................17
Article
SERDES Introduction
Designers feel comfortable designing with technologies that they are familiar with. Time to market is shorter,
potential risks are minimized, and, most importantly, costs are less difficult to project. As systems advance,
higher speeds and increased through-put are critical points. However, essential requirements are still need in
this advancing electronics market. New designs must still be introduced to market in a short time period;
risks must be carefully assessed; and costs are required to decrease. As these requirements evolve,
technology evolves, likewise the designers must stay current with new technologies. Serializers and
deserializers are an emerging technology that allows designers to cross some of the former bandwidth
bridges that existed with previous technologies. As with all new interface technologies, SERDES has a slight
learning curve.
What follows is a technical discussion on the SERDES family of devices, including jitter, timing requirements,
transmission media evaluation, and termination techniques. This analysis will apply to a range of SERDES
devices including the popular 28:4 family used in Flat Panel Display (FPD) applications and the 10:1 family
that are frequently used in communication applications. Encoding features will be also be discussed for
specific high-end SERDES devices. Lab data from Fairchild Semiconductor’s Ensigna Lab will point out
tradeoffs associated with these specifications to the designer.
After reviewing this paper, the designer will be better prepared for a design containing SERDES technology. Through a
better understanding of SERDES, the designer will be capable of selecting between two different SERDES devices to
achieve optimal performance for the application at hand.
Applications
As mentioned above, communication systems and displays are prime candidates for seeing a SERDES device. Both
applications have requirements for wide widths of data that need minimal skew between outputs and between devices.
There are also drive needs that SERDES technology provides. The 10:1 devices (1023/1224) offered by various vendors
have enough drive to allow a small multi-drop or multi-point configuration. A common configuration for devices with Low
Voltage Differential Switching (LVDS) outputs is a simple point-to-point type over printed circuit board (PCB) or cable.
The 10:1 devices can use an output termination resistor sized down to 27Ω, which is required when several devices are
coupled onto a single parallel path, i.e. multi-drop. For more information on termination schemes, refer to the Failsafe and
Termination Circuitry Section that follows.
The figure below shows some of the differences between multi-drop and point-to-point. The current direction for the
backplane market is a point-to-point topology with a master switch. SERDES is easily applied to this environment due to
the minimal wires that must run through the switch. Redundancy is also an available advantage for a switch interface.
Article
Figure 1. Configuration comparison between multi-drop and point-to-point applications.
SERDES Definition
SERDES technology is composed of a dedicated serializer / deserializer pair. Without a coupled pair, the
technology can not achieve the forecasted bandwidths. A custom serialized output is the result of stringent
timing components and reproducible signal positioning. On typical inputs, TTL signals (0V to 3.3V swing)
enter the serializer “horizontally” and are then “vertically” aligned such that in one clock period, one set of
parallel bits, or just one word, is transmitted. The figure below shows this basic serialization concept. It is
easily realized that the internal frequency of the serializer must be faster than the incoming TTL data.
Article
Figure 2. Flow diagram for a serializer deserializer pair.
The frequency of this internal clock is set by the compression / decompression factor of the device pair. One
would expect a 10:1 serializer to simply have an internal frequency of 10 times the TTL frequency.
However, this is not always the case. The 10:1 SERDES pair that is currently on the market began as a
custom pair that required the two devices to only be connected by a single data pair. How does the clock
get shared between the two devices?
The 10:1 family uses an embedded clock to synchronize the serializer and deserializer. This embedded clock is made up of
a start bit, always high, and stop bit, always low. The placement of these two bits is crucial to the low skew operation of
the device. Between these bits are ten distinct data bits, making the total length of one serialized signal actually12 bits.
When looking at the entire sequence, it is difficult to see exactly where the oscilloscope is triggered in the data pattern.
For this reason, it is common to insert a known data pattern, K 28.5 or similar, when trouble shooting.
Figure 3. Clock embedded into serializer output.
PLL Characteristics
A phase lock loop is used to keep time for the serializer deserializer pair. The PLL is internal to each device and is required
to lock to the input clock frequency, perform the correct multiplication factor, and maintain its output with minimal jitter. A
PLL is used because of its inherent feedback path allowing constant correction if a minor change is seen in the input signal
edge position or period. To understand the SERDES technology, it is important to have a basic understanding of how a
PLL operates.
All SERDES PLLs have an input frequency (typically CLKIN) and an internal core frequency that needs to be synchronized
with this frequency. The internal frequency is responsible for the serialization timing. For, without the PLL running, data
compression is not possible. A phase detector is used up front in the loop to assign a phase delta value. This delta is
Article
typically fed into a filter that controls the voltage sent to the Voltage Controlled Oscillator (VCO). The VCO accepts the
voltage level and modifies its ring frequency accordingly. A “divide by” transfer function is then responsible for the final
ratio of the CLKIN to the PLL frequency. The figure below shows this sequence of events. Naturally, it is not as simple
as it appears. There are several key factors to keep in mind for PLL operation: the time it takes to lock, power consumed,
the resolution of each loop correction factor, and the effect that jitter has on the circuit.
Perhaps, the most qualified test for comparing two PLLs from two separate vendors is a jitter bandwidth test. The
equipment involved makes this test expensive but the results can be very beneficial in choosing between two or more
vendors. (See the Jitter section later in this article for more information.)
Figure 4. Flow diagram for Phase Lock Loop (PLL) control circuit
Output Drive
Low Voltage Differential Switching (LVDS) is the most common drive used for SERDES technology. The major advantage
associated with LVDS is common-mode noise rejection. Due to the differential pair, any noise is seen by both signals and
the differential measurement between the two is theoretically unchanged. This noise rejection characteristic allows the use
of low amplitude pulses (typically around 400mV). Higher speeds are then achievable due to the decreased voltage levels.
Emitted Coupled Logic (ECL) is also used in some high performance SERDES devices. Versions of ECL are used in place of
LVDS when higher drive and higher speeds are required. One version seen lately is the Low Voltage Positive Emitter
Coupled Logic (LVPECL), capable of driving 50mA continuous compared to 5mA or 6mA associated with LVDS. This is
often the driver of choice when driving a cable greater than 15 meters in length at high speeds. ECL type devices are
commonly achieving speeds of 2Ghz, compared to the 600Mhz associated with LVDS. However, the power tradeoff is a
tough one to accept. Power consumption is roughly based on the magnitude of 5 or 6 times above that of LVDS. For this
reason, ECL based Serializers have a more focused application list than the broad list of LVDS Serializer applications.
Article
Encoding
Another characteristic that is seen on the high performance SERDES devices is 8B/10B encoding. Incorporated from fiber
channel standards, 8B/10B encoding is used to “DC balance” a word and minimize errors. Instead of sending an 8 bit word
composed of all 0s and one 1, a device with 8B/10B encoding truncates the word into a DC balanced 10 bit word made of 0s
and 1s, decreasing the amount of data dependant jitter. However, frequency overhead is now required since it takes 10
bits to send 8 bits of data. On the other hand, a system with fewer errors spends less time repeating data submissions,
thus increasing overall system throughput. Extra silicon is also required to facilitate the encoding algorithms, which
increases the price of the device. Detailed timing diagrams on this encoding scheme can be found in any Fiber Channel
standards document. Fairchild Semiconductor’s FIN7216 employs this type of encoding.
Datasheet Specification Review
With several vendors offering SERDES devices, and most of the devices being very similar, it is important to understand
datasheet specifications. Comparing two “similar” specifications, jitter for example, can appear to be clear while a minor
adjustment in one vendor’s testing methodology discredits any comparison between the two specifications. It is therefore
important to not only understand the specification itself but also be familiar with the way in which the characterization data
was collected. Even with lengthy interface device datasheets, information for every design application is still not present.
It is too difficult to present characterization data applicable to each designer. If a question arises on a specific SERDES
device, do not hesitate to call the vendor. Not only is it common for vendor’s application engineers to communicate with a
specific designer on a design win, it is expected.
The key word involved with comparing two datasheets is interoperability. Designers are oftentimes required to have a
second source but cannot guarantee that each vendor will only be communicating with its own complementing pair.
Interoperability is therefore a crucial detail. Here at Fairchild we have designed a SERDES Interoperability Demo Board for
the 10:1 family. (More details on this project are listed in the Medial Evaluation Section later in the article.) A demo board
not only allows chip designers to pretest for interoperability over set conditions, it allows the customer to do a “hands on
evaluation” of the devices. Below is a break down of a few specific datasheet details that arise more frequently than others
do.
Jitter
When differential signals reach speeds over several hundred Mhz, eye opening measurements are needed to evaluate
signal integrity. These measurements are often summarized as jitter. Jitter can be defined as simply the time delta between
when the event actually occurred and when the event was supposed to occur, with an event usually describing a rising or
falling edge. It can be broken down into several types.
The collective jitter for a signal is called total jitter (TJ) and is made up of deterministic and random components.
Deterministic jitter (DJ) is a bounded measure, meaning that it is repeatable over time and measured between two bounded
peaks in a jitter histogram. Random jitter (RJ) is not bounded and has a Gaussian distribution, meaning that the measured
RJ histogram is constantly growing with the number of hits in the measurement region or field.
While designing a SERDES application, should a designer be concerned with jitter? It is important to remember that the
link between the serializer and deserializer is fixed. All drive amounts and jitter are set by the type serializer. However, in
order for the serializer to provide a clean signal to the deserializer, a tight clock must be provided. This specification
appears in serializer datasheets as t JIT and applies to the TTL signal coming into the TCLK pin of the device. The way this
Article
jitter value is specified can vary between vendors so a call to the respective vendor may be in order. Naturally, the
designer wants to pay close attention to not introducing any further jitter to the SERDES link. Common differential design
techniques include: matched trace lengths, close coupling, and tightly controlled impedance (100Ω for LVDS signals).
When placing bypass capacitors for each device, using several vias and keeping power traces wider than typical signal
traces can decrease inductance.
Any jitter on this TCLK input trace directly affects the internal PLL of the serializer and therefore, affects the placement of
data bits in the serialized stream. The design of the internal PLL controls how jitter on this TCLK line is couple to the
serialized stream. Perhaps the best way to evaluate a specific vendor’s serializer is to record a Jitter Transfer Function
(JTF). This is a measure of the amount of jitter either amplified or filtered by the PLL and lets the designer see the overall
jitter performance of a device.
There are numerous ways to conduct this and what follows is only one method. The test consists of injecting specific
controlled jitter into the TTL TCLK line and measuring the DJ on the LVDS clock out line. A common approach is to set
the jitter amplitude to a small percentage of the bit period (typically 10% of the bit interval), 1ns was used for this test.
Setting the jitter amplitude smaller than 1ns is possible but requires even more detailed jitter measurement techniques on
the output. Larger amplitudes are easier to observe. The goal of this test is to characterize the jitter transfer of the PLL by
noting patterns in the JTF; specific values are immaterial.
The variable that is modified during the data collection is the frequency of the jitter, which is the rate that the clock edge is
being shifted from –500ps to +500ps (if 1ns is used). In the transfer function below, sinusoidal jitter was injected over the
carrier frequency. The carrier frequency is the actual TTL frequency the serializer requires to operate, typically 40Mhz to
120Mhz. When selecting the resolution for jitter frequencies where measurements will be posted, note that the plot will be
presented using a logarithmic scale for the ‘x’ frequency axis. The plot below shows a starting jitter frequency of 10Khz
and a final jitter frequency of 5Mhz. The max frequency is often declared by jitter generator limitations.
Article
Figure 5. Jitter transfer function for serializer.
The JTF in the plot above shows one device with data collected at three separate carrier frequencies. Starting at the left of
the plot, one can see that the 1ns of jitter sent into the device is evident on the output. This means that the PLL is able to
track low frequency jitter, i.e. this jitter is within the bandwidth of the PLL. As the frequency of the jitter increases, the
output jitter from the PLL gradually increases to a peak due to moderate PLL phase margin. Thus, for jitter at this
frequency, the PLL actually increases the jitter. When comparing two serializers, the device with the lowest peak and
lowest bandwidth generally transfers the lowest total jitter. The rate the waveform falls from the peak to the final level is
also significant, for it plays a role in determining the bandwidth. In addition, the steeper slope attenuates the high
frequency jitter components better. At the very high jitter frequencies, the final resting point of the waveform can be
thought of as the jitter inherent to the PLL design. As the carrier frequency increases, the core PLL jitter decreases;
however, the product ratio of inherent PLL jitter and clock frequency may actually increase at higher carrier frequencies.
Note the difference the carrier frequency makes in the overall JTF pattern. Therefore, it is important to do any preliminary
jitter evaluations at the frequency the future design will be operating.
Failsafe and Termination Circuitry
Serializers with LVDS output buffers require a termination resistor (RT) at the input to the deserializer. This resistance is
placed physically close to the deserializer and should match the impedance of the differential media as close as possible.
In multi-drop or multi-point applications, it is important to realize the drop in impedance that is caused by having all
deserializer input capacitances on a single node. The best way to measure this impedance is to use Time Domain
Reflectometry (TDR). This process sends a small pulse with a steep edge, usually less than 50ps, and monitors the
reflection to characterize inductance and capacitance seen in the trace. The TDR equipment then uses these values to
calculate the impedance for the media.
Figure 6. Typical LVDS termination technique using internal failsafe.
Shown in the figure above is the common approach to LVDS termination. This technique relies on the internal failsafe
circuitry. Failsafe is a term used to describe the effect various fault conditions have on the deserializer. For example, if the
application involved a cable link between the serializer and deserializer and the cable were disconnected from the serializer,
the cable would act as a noise antenna. If the noise exceeded the deserializer’s internal comparator threshold, erroneous
TTL data would appear on the output. Typical receiver threshold values range from +/-10mV to +/-50mV, meaning that on
a device with 50mV threshold, the input differential must be >50mV to cause a valid response.
The internal threshold could be designed to an even higher value since LVDS signals can operate as low as +/-200mV, but
keep in mind that signals can be attenuated in some applications. Since LVDS devices see a broad application arena, one
Article
designer may be planning to have a fully functional system switching around +/- 75mV. However, the margin for noise
would then only be 25mV.
In systems where noise may go through the threshold range for the deserializer, it may be necessary to employ an external
failsafe circuit. This is only necessary if the noise is present when the link between the serializer and deserializer enters a
tri-state mode and no LVDS signals are present. An external failsafe circuit is simply a light pull-up and pull-down on the
differential pair, shown in the figure below, to overcome the noise on the line to guarantee a known static state when noise
is present on the cable.
Figure 7. LVDS termination technique using external failsafe circuitry.
It is important to realize that one should only apply enough failsafe bias to overcome the noise since the circuitry will be
always present, including under normal SERDES operation. Excessive current in the pull-up and pull-down resistors will
overpower the drive of the serializer and degrade signal integrity. When sizing resistors RPU, RPD, and RT, also remember
that the Thevenin equivalent of the three must still match the effective impedance of the transmission media. The
Thevenin equivalent for the external failsafe circuit shown above is the parallel combination of RT || (RPU + RPD). The
desired common mode voltage for the link must also be considered. The common mode voltage is the level the LVDS
signal toggles around, typically 1.2V. Numerous application notes from various vendors exist on this subject. After
designing a failsafe circuit, a breadboard test that noise can be applied to will aide in circuit validation.
Some vendors use a technique known as active failsafe. This circuitry is internal to the deserializer and actually monitors
the condition of the LVDS signal. When the lower threshold limit is broken for the differential signal the deserializer
switches the output to a known valid state and continues to monitor the differential pair for a valid signal. As opposed to
the external failsafe mentioned above, the active failsafe has minimal effect on the LVDS signal since it is only seen when
the device enters failsafe mode. If the IC contains this type of failsafe, it is not necessary to apply external failsafe.
Contact the respective vendor to verify if this applies.
Lock Time
In the 10:1 family of SERDES, the serializer has SYNCH pins that, when pulled high, causes the device to output a
synchronization pattern that allows the deserializer to easily pick out the clock and lock the PLL. In turn, the deserializer
has a /LOCK pin that remains high until the internal PLL in locked. Connecting the SNYCH and /LOCK pins acts as a
feedback loop between the two devices. The end result is that the serializer will continue to output a SYNCH pattern, a
slow series of equal length lows and highs, until the deserializer acknowledges that its PLL is locked. At that point, the
deserializer will drive the /LOCK pin low and the serializer will output data that is on the TTL inputs. The time required to
Article
lock is listed in the datasheet for each vendor. No inverter logic is needed for lock feedback connection between the two
devices. This type of feedback is currently only available on the 10:1 family. Other SERDES devices do not have the
/LOCK pin on the deserializer. It should be noted that the feedback synchronization method is not required for the 10:1
devices. The deserializer can lock to random data but the lock time can vary. It is recommended that the designer use the
feedback loop in 10:1 SERDES applications to maintain reproducible lock times.
SERDES devices such as the 28:4 and 21:3 families used in displays have a separate twisted pair going from the clock
output of the serializer to the clock input of the deserializer, making it easier for the deserializer to distinguish the clock and
lock. This lock occurs prior to an average vendor specification of 10ms. In this time both the serializer and deserializer
have locked to their respective clocks and correct data is transmitted.
Media Evaluation
Because SERDES requires minimal wires between the serializer deserializer pair, the technology is open to numerous cable
types. Below is a comparison on a variety of lengths of what is commonly called CAT-5 cable. Associating a frequency
with a given length cable is very beneficial when selecting an interface technology for a specific application.
In this section, a demo board designed by Fairchild Semiconductor Ensigna Lab was used for all empirical data. The
board’s primary goal was to establish interoperability, as previously mentioned, but a demo board can be used for much
more if proper features are added. One of these features allows the ability to evaluate various types of media. As shown
in figure 8 below, RJ-45 connectors are located on the board edge. One connector is tied to the output of the serializer
while the opposite connector is connected to the input of the deserializer. This allows for easy access to swapping in any
number of cable lengths.
Figure 8. SERDES 10:1 demo board used in media evaluation.
Article
CAT-5 Cable
Several different length cables were constructed of CAT-5 cable and placed between the serializer and deserializer devices
for the 10:1 family. In each cable only one of the four twisted pairs was used with an RJ-45 connector on each end. Due to
the density of CAT-5, a maximum of four 10:1 devices could transmit over a single cable. If each of the devices were
operating at their max transfer rate of 660Mbs, a single cable could maintain 2.64Gbs.
The first length of cable evaluated was 1 meter. The media was composed of 100Ω unshielded twisted pair (UTP). A
shielded cable will provide increased signal integrity. A scope capture that was made at the 100Ω termination resistor just
before the deserializer is shown below. The start bit begins the sequence, which is always a High pulse for the 10:1
devices, at the far left and the remaining 9 bits follow. A Low pulse precedes the start bit, which is actually the stop bit for
the previous word. The scope has the horizontal resolution set to show only a data bit eye diagram for the first 4 data bits.
The purpose of this experiment is not to demonstrate the performance of the 10:1 serializer in the demo board but to
observe the change in eye pattern when cable length is changed. Scope acquisition is set to infinite persistence to show
jitter. In all plots a differential probe was used, which actually measures the absolute differential between two traces
regardless of their polarity. Therefore, the waveform amplitudes are read as double what the independent waveforms are.
Figure 9. Serialized measurement at deserializer input after 1m of CAT-5, TCLK 40Mhz.
Shown below is a plot with 5 meters of CAT-5e cable, an enhanced version of standard CAT-5, separating the serializer
and deserializer. One can see the eye pattern begins to close slightly due to horizontal jitter on a few edges but the overall
integrity of the eye is very good. The same clock frequency is sent to the TCLK input of the serializer, 40Mhz.
Article
It is important here to point out the data dependant jitter on some of the rising and falling edges. The TTL data sent to the
serializer is not a simple one/zero combination that repeats. Data used in each of the scope plots is “random” in nature.
Ten vectors containing a wide variety of one and zero combinations were generated and repeated. Therefore, data
dependant jitter exists in the plots, which is evident by two distinct falling edges on bit 1 below. A device employing
8B/10B encoding would minimize this type of jitter.
Figure 10. Serialized measurement at deserializer input after 5m of CAT-5e, TCLK 40Mhz.
Lastly, 10 meters of CAT-5 was used to link the serializer and deserializer, while the clock input frequency remains the same
as the previous plots. Here the eye amplitudes begin to close but even more prominent is the increased data dependent
jitter. At this frequency, the resulting jitter is minimal compared to the overall eye width, or unit interval (UI). If the TTL
clock input frequency was increased to 66Mhz, this 300ps of data dependant jitter may be an issue. Because of the
accurate strobe positioning the 1:10 deserializer has, a fair amount of random and deterministic jitter is allowed. Refer to
the vendor’s datasheet for specific values.
Article
Figure 11. Serialized measurement at deserializer input after 10m of CAT-5, TCLK 40Mhz.
In any design, the only way to know if the eye pattern is large enough for the strobe positioning for the deserializer is to
use a Bit Error Rate Test (BERT). When comparing two vendors IC’s it is important to use the same data pattern, perhaps
a standard K28.5 pattern.
Printed Circuit Board
As always, PCB can be used as a sole transmission media, as would be the case in a backplane or multi-drop environment.
During the cable tests mentioned above the serialized signal traveled through about 1.5” of PCB prior to reaching the RJ-45
connector and then traveling through the cable media. For the PCB tests in this section a pseudo point-to-point backplane
was added to the demo board. This board consisted of a 100mil connector at each end with two serpentine traces with
electrical lengths of 3” and 16”. The lengths are selectable by the placement of 0Ω resistors. With no cable present in the
RJ-45 connectors, the serialized signal is directed through the PCB interconnect.
The 3” evaluation is shown below. Impedance mismatches are easily observed (note the sharp spikes in the upper and
lower LVDS limits.) Jitter is minimal when compared to even the shortest length of cable above. Shortening stub lengths
and using a quality differential connector with impedance matching throughout would increase signal integrity. Again, the
purpose of this plot is not to show the performance of the IC in the demo board, but to allow the reader to compare 3” and
16” PCB traces in a controlled environment.
Article
Figure 12. Serialized signal at deserializer input after 3” of PCB with connectors.
The board was then modified to channel the serialized signal through a 16” PCB trace with all other conditions remaining
unchanged, shown below. Edges roll over more sharply at the upper and lower corners due to the increased trace length.
Still, there is ample upper and lower margin before encroaching the estimated max deserializer threshold limit of 100mV.
Article
Figure 13. Serialized signal at deserializer input after 16” of PCB with connectors.
SERDES Summary
The general advantages of SERDES have been proven, with the major one being dense throughput with minimal traces
between the serializer and deserializer. The high frequency of the data bits in this serialized path partners well with LVDS
technology, capable of noise rejection and minimal power consumption.
As shown above SERDES devices can drive both cable and PCB over various lengths. Keeping in mind some of the
general topics mentioned in this paper, a designer can easily convert an existing TTL application to a high-speed SERDES
system. Application details such as impedance matching, matched line lengths, and jitter sources play a key role in the
success of the design. The designer must note these items and follow the vendor’s guidelines in the datasheet to assure
tolerances are met. After a designer has climbed the SERDES learning curve, expanded throughput applications become
even easier to achieve.
Future Roadmap
SERDES devices have been around for over five years, but until recently have had little visibility as a true interface device.
Due to the recent surge in LVDS technology and the realization of its common mode versatility, SERDES now has an
excellent partner for future expansion. With some vendors already releasing full duplex devices, expect to see larger
through-put and much larger packages in the BGA variety. As redundancy become increasingly popular, newer SERDES
Article
releases will be similar to the FIN7216 and offer completely redundant data communication with unlimited timing control.
Expect to see more encoding schemes adopted and more elastic buffer implementation. Regardless of the device features,
understanding datasheet specifications and applying that performance to the design at hand will always be required.

DesignCon 2003 How To Apply SERDES Performance To Your Design Article

Transcription

Similar documents

An 8b/10b Encoding Serializer/Deserializer (SerDes) Circuit for High

Need for frequency synchronization

POLLuTION LEGAL LIABILITY

Fairchild specializes in the manufacturing of custom

System Architectures Using OIF CEI

to the Museum Aircraft pdf page

Grim Clock.indd