Circuit Note CN-0058


Circuit Note CN-0058
Circuit Note
Devices Connected/Referenced
Circuit Designs Using Analog Devices Products
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Quad SPST Switch with Minimal
Charge Injection
Dual, Precision, Very Low Noise
Operational Amplifier
Sample-and-Hold Circuit Using the ADG1211 Switch
only 1 pC compared to the next best solutions on the market,
which have 10 pC to 20 pC of charge injection. The ADG1211
also has low capacitance and leakage current, making it an ideal
choice for this circuit.
This circuit is a sample-and-hold amplifier (SHA) function,
which is basic to the data acquisition and analog-to-digital
conversion process. In some programmable logic controller
(PLC) output modules, a sample-and-hold in each channel
stores the output samples from a single high performance DAC.
The sample-and-holds are often implemented using analog
switches or multiplexers and buffers. The circuit shown in
Figure 1 provides a precise, fast sample-and-hold circuit capable
of processing industrial-level signals of up to ±10 V.
This is a precise, fast sample-and-hold circuit. During the
sample mode, SW2 is closed, and the output, VOUT, follows the
input signal, VIN. In the hold mode, SW2 is opened, and the
signal is held by the hold capacitor, CH.
Due to switch and capacitor leakage current, the voltage on the
hold capacitor decays (droops) with time. The ADG1211
minimizes this droop due to its low leakage specifications. The
ADG1211 has 20 pA leakage typically at 25°C and 100 pA
maximum. The droop rate is further minimized by the use of a
polystyrene hold capacitor.
Switches and multiplexers are useful in data acquisition
applications where instantaneous analog values must be
captured. The input signal from the analog switch charges a
hold capacitor that is connected to the input of an op amp.
Ideally, the closed switch conveys nothing but the input signal
to the capacitor. However, the switch also delivers a packet of
charge when it switches, called charge injection. The ADG1211
quad SPST switch has excellent charge injection performance of
A second switch, SW1, which operates in parallel with SW2, is
included in this circuit to reduce pedestal error. Since both
Figure 1. High Precision Fast Sample-and-Hold Circuit (Simplified Schematic: Decoupling and All Connections Not Shown)
Rev. A
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Circuit Note
switches are at the same potential, they have similar transients,
which act as a common-mode signal to the op amp, thereby
minimizing charge injection effects. Pedestal error is also
reduced by the compensation network RC and CC. This compensation network also reduces the hold-time glitch, while
optimizing the acquisition time.
The circuit in Figure 1 gives the following results: droop rate of
2 mV/ms, pedestal error of less than 0.5 mV, and acquisition
time of 3 ms.
The circuit must be constructed on a multilayer PC board with
a large area ground plane. Proper layout, grounding, and
decoupling techniques must be used to achieve optimum
performance (see Tutorial MT-031 and Tutorial MT-101).
MT-031 Tutorial, Grounding Data Converters and Solving the
Mystery of "AGND" and "DGND." Analog Devices.
MT-088 Tutorial, Analog Switches and Multiplexers Basics.
Analog Devices.
MT-090 Tutorial, Sample-and-Hold Amplifiers. Analog Devices.
MT-101 Tutorial, Decoupling Techniques. Analog Devices.
Data Sheets
ADG1211 Data Sheet
AD8672 Data Sheet
11/09—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
1/09—Revision 0: Initial Version
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