A 1.8V Sample-and-Hold with Reduced Flicker Noise Hur A. Hassan, Izhal b. Halin,

IEICE Electronics Express, Vol.* No.*,*-*
A 1.8V Sample-and-Hold with
Reduced Flicker Noise
Hur A. Hassan,1a) Izhal b. Halin,2b) and Ishak b. Aris1,2c)
1
Department of Electrical and Electronic Engineering, University Putra Malaysia,
43400, UPM, Serdang, Malaysia
a)
[email protected]
b) [email protected]
c)
[email protected]
Abstract: In this paper, CMOS Sample-and-Hold (S/H) is presented. The S/H
circuit is an important component in Analog-to-digital Converter (ADC). In low
frequency application, the boost clock technique is used to constitute a rail-to-rail
signal voltage with low distortion. The operational amplifier works as a unity gain
buffer in the S/H circuit. However, a two-stage op-amp is proposed with enhanced
low flicker noise performance. Furthermore, a comparison between the
folded-cascode op-amp and the two stage op-amp is presented. Noise
minimization is mainly achieved through using the inter-relationship of the design
parameters of the op-amp. This design is simulated in 0.18µm standard technology.
A very low input noise voltage 18 nV/ Hz is realized. The power dissipation is
about 55 µW at 1.8 V supply voltage, 1 MHz clock sampling.
Keywords: S/H, Flicker Noise, ADC
Classification: Integrated Circuit
References
1.
Morteza Mousazadeh, Khayrollah Hadidi and Abdollah Khoei "A novel
open-loop high-speed CMOS sample-and-hold," AEU-International Journal of
Electronics and Communications, Elsevier, Vol. 62, no.8, pp.588-596, August
2007.
2.
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.
3.
Yael Nemirovsky, Igor Brouk, and Claudio G. Jakobson." 1/f Noise in CMOS
Transistors for Analog Applications," IEEE Transactions on Electronic
Devices, Vol. 48, no. 5, May, 2001.
4.
Li Zhiyuan, Ye Yizheng, and Ma Jianguo. "Design procedure for optimizing
CMOS low noise operational amplifiers," Journal of Semiconductors, Vol.30,
no.4, April, 2009.
5.
Koichi TANNO, Kiminobu SAT, Hisashi TANAKA, and Okihiko ISHIZUKA,
"Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit,"
IEICE Transactions on Fundamentals of Electronics, Vol.E88, no. 10,
© IEICE 2008
pp.2696-2698, October, 2005.
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
1
IEICE Electronics Express, Vol.* No.*,*-*
6.
P.K. Chan, L.S. Ng, L. Siek, and K.T. Lau. "Designing CMOS folded-cascode
operational amplifier with flicker noise minimization," Microelectronics
Journal, Elsevier, Vol. 32, no.1, pp. 69-73, April, 2000.
1. Introduction
As demand for low power, low noise CMOS ADCs grows, more highly linear low
noise S/H circuits are required. The S/H circuit requires in design a high Signal to
Noise Ratio (SNR). To realize it, the analog switch should supply enough
overdrive voltage to the gates of the MOSFET. Otherwise, the analog switch
cannot be turned on/off deeply with a low voltage supply. To overcome this issue a
boosting technique is required. Most S/H circuits need a buffer amplifier when in
hold mode. This buffer is needed to isolate loading in the previous stage of the
circuit. Therefore, to fulfil the linearity of the ADC, the performance of the buffer
is high gain, rail to rail input and low noise with stable as possible as [1].
Some applications with low frequency suffer from flicker noise (1/f) that
requires an ADC. One of these applications is the Compressed Natural Gas Direct
Injection (CNGDI). However, flicker noise is a significant noise source appearing
from the random trapping of charge carriers at the oxide-silicon interface of
MOSFETs [2]. Moreover, PMOS devices are quieter than NMOS as the former
carry holes in a burred channel [3].
The practice design adopts large size p-channel input transistors with high
transconductance. However, if the p-channel input transistors and silicon area are
too large, parasitic capacitance will increase substantially. In op-amp circuits,
flicker and thermal noise are dominant [4]. While keeping a focus on low noise
frequency application, a two-stage op-amp topology with drive noise equations is
designed. The results are compared with the folded cascode op-amp as a reference
basis.
2. S/H Circuit Design
The conversion process of ADC begins with the S/H circuit. The purpose of the
S/H circuit is to sample an analog input during the sample phase and hold the
signal at a constant voltage during the hold phase. The overall S/H circuit is shown
in Fig. 1(a) where the sampling switch (Ms) and the dummy switch (Md) are
supported with clocks by using BS1 and BS2, respectively [5]. These circuits are
controlled by a non-overlapped two phase clock ( andϖ). The BS1 circuit
generates a boosted (Vdd + Vin ) signal clock for the MOS switch (Ms), while the
BS2 generates clock for Md. Consequently, the charge injection and the clock
feedthrough, which is caused by the error, are reduced by dummy switch.
Furthermore, the circuit block is combined by M6, C1 and C2.
© IEICE 2008
In this research two types of op-amps in S/H circuit were presented, two stage
op-amp and folded cascode op-amp, as well as a comparison between them that has
low input and output flicker noise performance. The noise source in the CMOS
op-amp originates from the thermal noise and flicker noise.
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
2
IEICE Electronics Express, Vol.* No.*,*-*
For low frequency below 10 KHz, the flicker noise component is larger than the
thermal noise component [6]. By neglecting the contribution of thermal noise
currents, the total current noise can be approximated as:
it2
K g2
≈ F m
∆f CoxWLf
(1)
Where KF is the flicker noise coefficient, gm the transconductance parameter, Cox
the gate oxide capacitance per unit area, L the channel length, W the channel width,
µ the effective mobility and f the bandwidth. Thus, the total of output current
noise for the first stage of the two stage op-amp PMOS differential input pair M1,
M2 and NMOS transistors M3 and M4 is shown in Fig. 1(b).
io2 = g m2 1veq2 1 + g m2 2veq2 2 + g m2 3veq2 3 + g m2 4 veq2 4
2
eqT
v
=v
2
eq1
+v
2
eq 2
 g m2 3  2
+  2  veq 3 + veq2 4
 g m1 
(
)
(1)
(2)
V2eqT is the total input refereed noise at the input of transistor M1, and gm1 = gm2,
gm3 = gm4. After submitting the value of noise sources of transistors M1, M2, M3
and M4 in equation (3), getting flicker noise refereed at the input of transistor M1.
v 2flic ker =
2 

1 + K n µ n L1 ∆f
fW1L1Cox  K p µ p L23 
2K p
(3)
Where Kn and Kp are flicker noise coefficients for NMOS and PMOS, respectively.
3. Design Folded-Cascode Op-Amp
A more stable folded cascode op-amp topology with high gain and high swing
input voltage is designed in the S/H circuit. For an efficient circuit design approach
to minimize noise, the CMOS folded cascade op-amp structure is illustrated, as
shown in Fig. 1(c).
From the above noise analysis of the two stage op-amp, the mathematical
treatment for the folded cascode amplifier can be applied.
© IEICE 2008
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
3
IEICE Electronics Express, Vol.* No.*,*-*
Fig.1. (a) Structure of S/H Circuit (b) bootstrap circuit (c) two Stage
op-amp (d) folded-cascode op-amp .
veq2
∆f
© IEICE 2008
=
2K p  1  K n µ n
 +
C oxW1 f  L1  K p µ p
 I D 3  L1  I D 8  L1  I D10  L1 

 +
 +

 I  L2  I  L2  I  L2 
 D1  3  D1  8  D1  10 
(4)
The extra noise term is added in equation (4) since M8, M10 are generated. From
the above equation, the total input noise for the folded cascode amplifier depends
on the process parameters and design parameters. The design parameters can be
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
4
IEICE Electronics Express, Vol.* No.*,*-*
controlled by transistor lengths of M1, M3, M8 and M10, as well as the biasing
current ratios of ID3/ID1, ID8/ID1 and ID10/ID1. Although the above equation gives the
noise performance with design parameters, it does not denote the optimal design
strategy due to that, there are many choices in design. Noise minimization leads to
low biasing currents and long channel lengths for M3, M8 and M10 but has no
effect on the other performance such as input common mode voltage range, gain
bandwidth and slew rate.
Typically, for the practice design of the folded cascode amplifier, the biasing
currents are often chosen such that ID1 = ID8= ID10, ID3 = 2ID8. For KF1= KF8= KF10,
equation (4) can be simplified to:
veq2
∆f
≈
2K F1
CoxW1 f
 1  K µ  2L L
L 
 +  F 3 n  21 + 21 + 21 
 L1  K F 1µ p  L3 L8 L10 
(5)
As seen from equation (5), L8 and L10 are made larger than L1 and the second term
is much greater than the third and the fourth terms in the bracket. Thus, the
aforementioned equation can be simplified as:
veq2
2 K F1
≈
∆f CoxW1 f
 1  K µ  2L 
 +  F 3 n  21 
 L1  K F 1µ p  L3 
(6)
4. Simulation Results
The implementation and simulation of the S/H circuit has been accomplished
using Mentor Graphic BSIM 3.3 TSMC 0.18µm technology. The threshold voltage
is 0.37 V and 0.39 V for NMOS and PMOS, respectively. A sinusoidal signal of 1
V p-p with frequency 35 KHz was applied to S/Hs. As seen from Fig. 2(a), shows
the transient response of the S/H circuit, where Vin is boosted to (Vdd + Vin) to
generate the clock signal for the MOS switch Ms. The effect of the charge injection
and the clock feedthrough causes the hold error in the S/H circuit. These problems
are solved with a dummy switch
The performance of the op-amp is required to have high gain, high input
voltage swing and low noise. However, the output noise model has been plotted in
nV/sqrt Hz verses frequency in linear behaviour. The flicker noise is obtained by
measuring the input refereed noise for the op-amp Fig. 2(b). From the plot
observed that, the input referred noise for the two op-amps is equal to 18 nV/ Hz,
while the output noise for the two stage is 39 µV/ Hz lower than the output noise
of folded cascode op-amp equal to 202 µV/ Hz. However, the output noise of
amplifier is important in S/H circuit dut to that, the noise will effect on the next
stage of circuit. The noise behaviour plot of the amplifier is gain, output noise and
input referred noise. The output simulation provides the information of the
equivalent input noise for each frequency. However, the power dissipation of the
overall S/Hs is 55 µW for the two stage op-amp. Table I shows the performance
summaries of the proposed topology.
© IEICE 2008
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
5
IEICE Electronics Express, Vol.* No.*,*-*
(a)
(b)
Fig. 2. (a) Input Signal, Output of Bootstrap Circuit, Output of S/H Circuit (b)
Input Refereed Noise, Gain and Output Noise for Two Stage Op-Amp
(triangle line), Input Refereed Noise, Gain and Output Noise for
Folded-Cascode Op-Amp (Without triangle line)
© IEICE 2008
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
6
IEICE Electronics Express, Vol.* No.*,*-*
Table I. Simulation Results Summary
Parameter
DC Gain (dB)
Unity-Gain
Bandwidth (MHz)
Phase Margin
(degree)
Input-Referred Noise
(nV/ Hz)
Power Supply (V)
Power Dissipation
(mW)
Max. Output Voltage
(V)
Min. Input Voltage
(mV)
Two Stage
Op-Amp
Folded
Cascode
66
81
5.5
14
52
56
18
18
1.8
1.8
0.039
[4]
[6]
82.8
79.5
86
8.6
51.2
66.5
32.67
41
1.8
5
0.17
1.12
1.75
1.6
1.45 V
1.44
2
15
7
0
n/a
5. Conclusion
In this paper, a CMOS high precision Sample-and-Hold circuit has been presented
with low distortion and rail to rail input. The heart of this circuit is a two-stage
op-amp and folded-cascode op-amp with low noise enhancement. Extensive Eldo
simulation results in Mentor Graphic TSMC confirm the validity of the noise
minimization methodology. The simulation results indicate that, the circuit is well
suited for operation at 1.8V and 1MS/s. This device is compatible for standard
CMOS 0.18µm technology. This circuit can be used in high resolution and high
speed applications such as Successive Approximation Register, Pipeline and Flash
ADCs.
© IEICE 2008
[DOI: **.****/*****************]
Received September **, 2008;
Accepted September **, 2008;
Published in October **, 2008 issue
7