SA 20.6: 5GSample/s Track-Hold and 3GSample/s Quasi-Sample-Hold ICs A. Hülsmann, T. Jakobus

SA 20.6: 5GSample/s Track-Hold and 3GSample/s
Quasi-Sample-Hold ICs
Z. Lao, A. Thiede, H. Lienhart, M. Schlechtweg, W. Bronner, J. Hornung,
A. Hülsmann, T. Jakobus
of 30ps, necessary for short transition times between the two
operating modes.
Fraunhofer-Institute of Applied Solid-State Physics, Freiburg, Germany
The quasi-sample-and-hold amplifier (quasi-SHA) samples the
input signal for a short time and holds the sampled value for the
duration of the duty cycle. The main difference between THA and
quasi-SHA lies in the switch driver circuit. Instead of abroad-band
amplifier, a static frequency divider followed by a NAND gate are
applied to form a pulse with a 1/4 of the period for tracking and 3/
4 for holding.
Two fully-differential track-and-hold and quasi-sample-and-hold
circuits are based on AlGaAs/GaAs-HEMTs with 60GHz fT. The
less complex of these circuits exhibits 7b linearity measured under
worst case. The ICs work up to 5GSample/s at a differential input
of 2Vp-p for the track-and-hold and 3GSample/s for the quasisample-and-hold. The THA can be directly merged with the sourcefollower input stage of a A/D converter and is also suitable for Si
bipolar technology.
There are different approaches to THA circuits, but the highspeed differential THAs is usually that proposed by P. Vorenkamp
[1-6]. While operating up to 1GSample/s [2, 3], the input buffer
required in this approach distorts the linearity of the original
input signal [2-6]; and the bias voltage of the series linearization
diode limits the input voltage swing to 1Vp-p at -5V supply [3, 6].
The design presented is an evolution of above mentioned THA [6].
The THA exhibits high linearity, small pedestal error, large inputvoltage range and a high-sampling rate. It consists of the input
stage that operates as a switched source follower sampler, the
switch driver and the output buffer. Differential configuration is
used throughout the design to improve overall linearity, minimize
common-mode pedestal and noise, and reduce effective droop rate.
Figure 1 depicts the principle THA. The transistor Q has a high
impedance to the signal source and provides a current gain to
charge the hold capacitance CH. The switches S1 and S2 are
controlled by the clock signal to track the input signal when they
are on or retain the last value of the input signal when they are
off. The circuit of Figure 2 is a fully differential implementation of
the circuit shown in Figure 1. The transistor Q1 (Q1') with resistance Rs (Rs’) represents the switch S1, and transistors Q2 (Q2') - Q3
(Q3') the switch S2 in Figure 1, respectively. During the track mode
(when node T is high), transistors Q (Q’) and Q1 (Q1') act as twostage source-followers charging and discharging the hold capacitance CH (CH’). The two cascaded source-followers improve the
decoupling capability and provide efficient drive for the hold
capacitance. During the hold mode (when node H is high), the
current I0 (I0') is switched away from the transistor Q1 (Q1') and
flows across resistor Rs, causing an additional voltage drop of
approximately 1V. Q1 (Q1') is now reverse biased and the holdcapacitance CH is isolated from input signal. The maximum input
voltage swing is determined by I0 Rs + ∆Vgs(Q) and the Rs by the time
constant τ1 ≈ (1/gm(Q)+ Rs)(Cgd(Q1)+ Cds(Q2)). τ1 should be smaller than
τ2 ≈ (1/gm(Q1))(CH+ Cgd(Q3)+ Cds(Q3)+ Cgd(Q4)), which represents the
analog bandwidth of the THA. In this design, Rs = 200Ω, Is1 =
0.8mA, I0 = 4mA and CH = 1 pF. An another important function of
Rs it to prevent ringing during the track phase. It effectively
dampens the negative impedance caused by the source-followers
with their large hold capacitance CH. This results in minimizing
the pedestal error and transient settling time.
Providing an on-chip switch driver and an output buffer (Q 4-Q6,
Q4'-Q6') facilitates IC test. The output buffer offers a high impedance to the hold capacitance to keep the held voltage from discharging. The switch driver converts a 500mVp-p sine wave input
voltage into an approximately rectangular signal by which the
hold capacitance is alternately switched between track and hold.
This is achieved by a broadband amplifier with a differential active
source-follower [7]. The resulting switch-pulse has a rise/fall-time
© IEEE 1998
Figure 4 is a micrograph of the 0.7x0.9mm2 THA IC chip. It is based
on 0.2µm gate length enhancement and depletion AlGaAs/GaAsHEMTs (fT = 60 and 50GHz) [8].
The circuits are measured on wafer using 50Ω coplanar test
probes. Figure 5 shows the measured performance at 5GHz
sampling rate at a sine-wave input of 500MHz and an input
amplitude of 2Vp-p. This is the highest sampling rate reported in
any technology. The THA output is fed directly into a spectrum
analyzer. Figure 6 shows the measured spectrum of a 2.5GHz
analog input sampled by a 2.501GHz clock. The resulting 1MHz
beat frequency is then analyzed for distortion, which is found to be
better than -45dB. This corresponds to 7 effective bits. The actual
linearity is better than this value because the circuit operates
under the worst condition at a frequency of 2.5GHz above the
Nyquist rate and the nonlinear slewing take place during the track
time and hold “edges” of the signal waveform [1]. The pedestal
error is approximately 2mV. Figure 7 shows measured performance of the quasi-SHA at 250MHz input signal and 6GHz clock.
The actual sampling rate is 3GSample/s due to the function of the
switch driver. The power dissipation is 500mW for the THA and
550mW for the quasi-SHA with a single power supply voltage of 5V. Table 1 summarizes performance of the THA circuit.
Acknowledgments:
The authors thank G. Weimann for encouragement and the entire
process laboratory staff for circuit processing.
References:
[1] Razavi, B., “Design of Sample-and-Hold Amplifiers for High-Speed
Low-Power A/D Converters,” IEEE CICC, Digest of Technical Papers, pp.
59-66, 1997.
[2] Baumheinrich, T., et al., “A 1GSample/s 10b Full Nyquist Silicon
Bipolar Track&Hold IC”, ISSCC Digest of Technical Papers, pp. 142-143,
Feb., 1997.
[3] Pregardier, B., et al., “A 1GSample/e 8b Silicon Bipolar Track & Hold
IC,” ISSCC Digest of Technical Papers, pp. 58-59, Feb., 1995.
[4] Karanicolas, A., “A 2.7V 300Msample/s Track-and-Hold Amplifier,”
ISSCC Digest of Technical Papers, pp. 140-141, Feb., 1997.
[5] Fiocchi, C., et al., “A 10b 250MHz BiCMOS Track and Hold,” ISSCC
Digest of Technical Papers, pp. 144-145, Feb., 1997.
[6] Vorenkamp, P., et al., “Fully Bipolar, 120MS/s 10b-Track-and-Hold
Circuit”, IEEE JSSC, vol. 27, pp. 988-992, 1992.
[7] Lao, Z., et al., “25Gb/s AGC Amplifier, 22GHz Transimpedance
Amplifier and 27.7GHz Limiting Amplifier ICs using AlGaAs/GaAsHEMTs,” ISSCC Digest of Technical Papers, pp. 356-357, Feb., 1997.
[8] Jakobus, T., et al., “Stability of an AlGaAs/GaAs/AlGaAs E/D-HEMT
process with double pulse doping,” Int. Symp. GaAs and Related Compounds, Inst. Phys. Conf. Ser. no. 129, Chapter 11, pp. 887-892, 1992.
20.6-1
Figure 1: Block diagram of the principle THA.
Figure 3: Principle diagram of the switch driver
for the quasi-sample-hold operations.
Figure 2: Schematic diagram of the differential THA.
Figure 5: Measured performance of the THA
Sampling frequency
Analog bandwidth
Differential analog input range
Feedthrough (at fin=2.5GHz)
Droop rate
Pedestal
Slew rate
Harmonic distortion
(at fin=2.5GHz, fclk=2.501GHz)
Voltage swing of clock signal
Supply voltage
Power dissipation
Chip size
Figure 6: Measured output spectrum
© IEEE 1998
Table 1:
5GSample/s
3GHz
2Vp-p
-30dB
1.8mV/ns
2mV
10.7V/ns
-45dB
500mVp-p
-5V
500mW
0.7x0.9mm2
Performance characteristics of the
THA IC.
20.6-2
SA 20.6: 5GSample/s Track-Hold and 3GSample/s Quasi-Sample-Hold ICs
Figure 7: Measured performance of the quasi-SHA at
fclk= 6 GHz and Vin = 2Vp-p.
Figure 4: THA IC chip micrograph.
© IEEE 1998
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Figure 1:
© IEEE 1998
Block diagram of the principle THA.
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Figure 2:
© IEEE 1998
Schematic diagram of the differential THA.
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Figure 3:
© IEEE 1998
Principle diagram of the switch driver
for the quasi-sample-hold operations.
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Figure 4:
© IEEE 1998
THA IC chip micrograph.
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Figure 5:
© IEEE 1998
Measured performance of the THA
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Figure 6:
© IEEE 1998
Measured output spectrum
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Figure 7:
© IEEE 1998
Measured performance of the quasi-SHA at
fclk= 6 GHz and Vin = 2Vp-p.
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Sampling frequency
Analog bandwidth
Differential analog input range
Feedthrough (at fin=2.5GHz)
Droop rate
Pedestal
Slew rate
Harmonic distortion
(at fin=2.5GHz, fclk=2.501GHz)
Voltage swing of clock signal
Supply voltage
Power dissipation
Chip size
Table 1:
© IEEE 1998
5GSample/s
3GHz
2Vp-p
-30dB
1.8mV/ns
2mV
10.7V/ns
-45dB
500mVp-p
-5V
500mW
0.7x0.9mm2
Performance characteristics of the
THA IC.
20.6-11