doc4-Channel Sampling Considerations for 10GBASE-T IEEE 802.3an Interim Meeting September 2004
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4-Channel Sampling Considerations for 10GBASE-T IEEE 802.3an Interim Meeting September 2004
4-Channel Sampling Considerations for 10GBASE-T IEEE 802.3an Interim Meeting September 2004 Scott Powell, Broadcom 1 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Agenda • 4 Channel Sampling – Challenges & alternatives • Phase Insensitive Sampling – Zero excess bandwidth channel • 4 Channel Sampling with Single Free Running Clock – Modified master/slave • Summary/Conclusions 2 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 4 Channel Sampling Traditional Analog/Digital Phase Compensation Tx signals Rx signals PHY must accuratly re-align (conceptual) tٛ ADC FFE t2 ADC FFE t3 ADC FFE t4 ADC FFE Phase delays differ on each wire • Optimal baud spaced samples are ≈ at pulse peak • Independently adjusted phase for each channel – Same frequency 3 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Implementation Challenges PLL PLL ADC PLL Pair 3 Pair 4 FFE ADC PLL ADC – Each PLL independently adapts to optimal frequency/phase VCO3 Pair 2 FFE VCO2 ADC FFE VCO4 Pair 1 VCO1 • Approach 1: independent PLL per channel FFE • Theoretically possible but has implementation challenges – Difficulties with multiple VCOs on same die – interactions almost inevitable – Injection locking has been shown to be the root cause failure mechanism in previous products 4 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Implementation Challenges mux • Approach 2: Single VCO with phase selector Pair 4 N phases FFE mux Pair 3 ADC ADC FFE ADC FFE mux Pair 2 PLL VCO FFE ... ADC mux Pair 1 – Single PLL generates N phases of a single recovered clock – Mux on each channel independently selects optimal phase • 50~60dB Echo suppression requires very large number of phases: N10G >> N1G – Phase steps cause transient echo cancellation errors 5 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Implementation Challenges • Decision directed timing recovery has ADC+FFE PLL ADC VCO1 latency in PLL loop FFE • Jitter tolerance and latency are opposing goals – Latency requires PLL bandwidth to be reduced – Jitter tolerance requires PLL bandwidth to be increased • Low jitter requirement may constrain design options for ADC, FFE, slicer – Eg: FFT based filters offer lower complexity but higher latency 6 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 System Solution to Implementation Challenges • Approach 3: Move timing recovery after FFE: – Digital interpolator instead of analog VCO or phase selector Free running DPLL RX ADC FFE interp • Removes latency restriction on ADC and FFE Advantage #1 – Opens opportunity for design innovation • Free running clock removes requirement for high precision phase selector 7 Advantage #2 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 System Solution to Implementation Challenges • Approach 3: Move timing recovery after FFE: – Digital interpolator instead of analog VCO or phase selector DAC Echo Canc. TX Free running RX ADC + DPLL FFE interp • ADC, DAC, echo canceller, FFE all on same clock – Removes need for FIFOs 8 Advantage #3 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 System Solution to Implementation Challenges • Approach 3: Move timing recovery after FFE: – Digital interpolator instead of analog VCO or phase selector DAC DAC DAC DAC Free running single clk RX pair 4 RX pair3 RX pair 2 RX pair1 Echo Canc. Echo Canc. Echo EchoCanc. Canc. TX pair 4 TX pair 3 TX pair2 TX pair 1 ADC +++ FFE FFE ADC ADC FFE ADC + FFE 4 channels DPLL DPLL DPLL DPLL interp interp interp interp • FFE in each channel performs independent phase adjustment Advantage #4 – Analog PLL per channel not required – Removes requirement for large phase selecter – Single clock for all 4 channels (may want intentional fixed offset) 9 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Transmitter Requirements • Standard does not need to specify receiver implementation – All three options can be permitted with appropriate transmitter • Two main transmitter features must be adopted by task force to permit option 3: 1. Zero excess bandwidth channel • Permits (but does not require) digital timing recovery after equalizer 2. Slave optionally transmits with recovered clock • Permits (but does not require) single free running clock at both ends of link • Neither of these features precludes implementation options 1 or 2 10 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Agenda • 4 Channel Sampling – Challenges & alternatives • Phase Insensitive Sampling – Zero excess bandwidth channel • 4 Channel Sampling with Single Free Running Clock – Modified master/slave • Summary/Conclusions 11 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Zero Excess Bandwidth • Well known technique for phase insensitive sampling – Signal bandwidth constrained to < Fbaud/2 – Permits sampling phase to be adjusted digitally (through interpolation) • Severe insertion loss channel is already close to a zero excess bandwidth channel – Additional zero at Fbaud/2 does not change much Insertion Loss (linear scale) 12 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Tx Filtering for Phase Insensitivity: Minimal Rate Loss ungerboeck_1_0504.pdf slide 16 • Cable Model #3: 100m Class E (Cat 6) screened • TX PSD with cosine roll-offs: zero excess bandwidth and 25% excess bandwidth • Modulation rates fT=1/T = 400 to 1400 Mbaud; PT=10dBm, N0=-135 dBm/Hz, Γ = 4 (6 dB). Achievable rate [Gbit/s] with 6 dB gap to capacity Cable model #3: 100m Class E (Cat 6) screened 2.7 2.6 Shapes of ST (f ) 2.5 2.4 2.3 f1 = 1 / 4T f 2 =1 / 2T Zero excess BW f1 = 1 / 4 T f 2 = 5 / 8T 25% excess BW 2.2 2.1 Zero excess bandwidth and 25% excess bandwidth 2 1 / 2T 1.9 1.8 200 13 Negligible rate loss with zero excess bandwidth filter 2.8 400 600 800 1000 1200 Modulation rate fT [Mbaud] 1400 1600 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Tx Filtering for Phase Insensitivity: Minimal SNR loss ungerboeck_1_0704.pdf slide 21 Cable type =" ClassEs"; f T = 820.72 MBaud (12 - PAM); practical TX filter; PT = 5 dBm; alien NEXT + AWGN (-140 dBm/Hz); opt. FFE S NRm m s ewm f, S NRm m s eM F , S NRm m s eG Rf [dB ] 60 55 SNR mmseWMF [dB] : optimum h(D) for each length 50 40 35 SNR pRF+ mmseFFE [dB] : fixed h IIR (D) 30 (worst - case sampling phase) 25 20 14 Negligible SNR loss with zero excess bandwidth filter SNR MF+ mmseFFE [dB] : fixed h IIR (D) 45 25.85 dB 24 .92 dB SNR req ≈ 23 dB 0 10 20 30 24.54 dB 40 50 60 Cable length [m ] 70 80 90 100 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Without null With null @ Fbaud/2 Implementation: Background • Phase insensitive sampling – Single free-running PLL for all four channels • Define: – “Physical Channel” ≡ Tx filter + cable/connectors + FFE – “Prototype Channel” ≡ precoder feedback filter Physical Channel Precoder PAM Symbols 2kM + DAC Tx Filter Rx Filter ADC FFE H(z) Prototype Channel Spectrally Flat • Fixed prototype channel, adaptive physical channel – FFE will adapt to make physical channel = prototype channel 15 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Implementation of Zero Excess Bandwidth Channel • A combination of THP, Tx filter, cable, Rx FFE – THP (fixed, digital): places null in prototype channel H(z) at Fbaud/2 – Tx Filter (fixed, analog): gradual roll-off eliminates images • Does not need to implement spectral null (see ungerboeck_1_0704.pdf slide 19) – Cable (fixed, analog): approx inverse of THP response – Rx FFE (adaptive, digital): adapts to make channel = prototype channel • Implements spectral null Remove DAC Images Precoder 2kM PAM Symbols + DAC Tx Filter Inserts zero @ Fbaud/2 Rx Filter ADC FFE H(z) Fixed Spectral Null @ Fbaud/2 Adapts to match physical channel to prototype channel No Null in Transmit Spectrum Conceptual “equivalent” channel: actual implementation may differ 16 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Agenda • 4 Channel Sampling – Challenges & alternatives • Phase Insensitive Sampling – Zero excess bandwidth channel • 4 Channel Sampling with Single Free Running Clock – Modified master/slave • Summary/Conclusions 17 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Master/Slave Full Duplex Communications • Only used in 1000BT – 10BT, 100TX, 1000X do not have master/slave concept • Asymmetric PHYs – Slave transmits with recovered clock – Each PHY must support both master and slave modes Master Slave TX Free running Recover Clock RX 18 RX TX IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Modified Master/Slave Configuration • Modified and traditional master/slave sides interoperate – modified master ↔ traditional slave traditional master ↔ modified slave • Symmetric configuration – Both PHYs can have identical configurations, if desired – Permits phase insensitive timing recovery – Permits single free running clock for all 4 channels Master Slave TX RX Free running Recover Clock RX 19 RX -or- Recover Clock Recover Clock Free running TX TX IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Agenda • 4 Channel Sampling – Challenges & alternatives • Phase Insensitive Sampling – Zero excess bandwidth channel • 4 Channel Sampling with Single Free Running Clock – Modified master/slave • Summary/Conclusions 20 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Summary Challenges of Traditional 4-Channel Sampling Advantages of Phase Insensitive Sampling 1. Independently controlled phase 1. No restrictions on ADC/FFE 2. Multiple VCO’s have interaction 2. Single VCO, no high precision for each channel difficulties (injection locking, jitter coupling) 3. Phase selectors require large number of phases due to large echo 4. Analog PLL loop delay restricts ADC & FFE implementation options implementation phase selector 3. Single free running clock for all 4 channels 4. ADC, DAC, echo canceller, FFE for all 4 channels in same clock domain 5. Transmitter requirements do not preclude traditional 4-channel sampling 21 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004 Conclusions • Common 4-channel sampling approaches used in gigabit phys have implementation challenges for 10GBASE-T • Simple transmitter modifications will permit alternate 4-channel sampling approaches to be considered – Modifications do not preclude traditional approaches • Phase insensitive sampling offers implementation advantages and opportunities for innovation for 10GBASE-T PHYs – Disadvantages need to be independently quantified and weighed against advantages … goal for next meeting ? 22 IEEE 802.3an 10GBASE-T Task Force Interim Meeting September 2004
