ECE 272 Lab Manual Fall 2014

Transcription

ECE 272 Lab Manual
Fall 2014
Copyright Information
c
Copyright 2014
Oregon State University
School of Electrical Engineering & Computer Science (EECS)
This document is the property of Oregon State University and the School of EECS. Limited use of this document
is allowed, according to the following criteria:
Materials are free to use, except for the cost of reproduction, and must always bear this statement in any reproduction.
Materials created using this information may not be labeled as TekBots’ materials, without the prior written consent
of both Oregon State University and the School of EECS.
Disclaimer of Liability
Oregon State University, Platforms for Learning, TekBots and other partner schools are not responsible for special,
consequential, or incidental damages resulting from any breach of warranty, or under any legal theory, including
lost profits, downtime, goodwill, damage to, or replacement of equipment or property, or any costs of recovering,
reprogramming, or reproducing any data stored in or used with our products.
The aforementioned parties are also not responsible for any personal damage, including that to life and health,
resulting from use of any of our products. You take full responsibility for your product/ application, no matter how
life-threatening it may be.
Internet Access
We maintain Internet systems for your use. They can be used to obtain free TekBots’ software and documentation
and also to purchase TekBots products. These systems may also be used to communicate with members of TekBots
and other customers. Access information is shown below:
E-mail: [email protected]
Web: http://www.tekbots.com
ECE 272 Manual
Contents
0 Preface
9
0.1 Lab Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
0.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
0.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
0.4 Installing Lattice Diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
0.5 Building the Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
0.6 Lab Manual Conventions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
0.7 Etiquette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
0.8 Resources
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
0.9 Academic Dishonesty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
0.10 Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1 Basic Combinational Logic and the MachXO2
17
1.1 Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6.1 Start Diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.6.2 Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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CONTENTS
1.6.3 Schematic Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7 Design Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.8 Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.8.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.8.2 Spreadsheet View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.8.3 Creating the Programming File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9 Program Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9.1 Program the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.9.2 Assemble the Push Button board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.10 Test Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.11 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.12 Challenge - Extra Credit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 Combinational Logic (Custom Remote Control)
29
2.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.1 Make a block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.2 Make a functional truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5.3 Minimize the logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.6 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7.1 Creating the Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.7.2 Changing the Verilog Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7.3 Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.8 Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ECE 272 Manual
CONTENTS
2.10 Test Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.11 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3 Combinational Logic (Seven Segment Driver)
37
3.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.7 Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.8.1 Test Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.9 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Modular Combinational Logic Using HDL
45
4.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4 Verilog Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4.1 Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.2 Instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.4.3 Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.4.4 Reg Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5 Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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4.6 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.7 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.7.2 Make a functional truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.7.3 Plan the design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.8 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.10 Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.12 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5 Finite State Machine Using HDL
57
5.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5 High Level Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5.2 Make a state diagram on paper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.6 Design Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.6.1 Start a new project and code a state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.6.2 Add a clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.6.3 Add a clock counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.8 Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.10 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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6 Final Design Project
63
6.2 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.5 ADC Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.6 Checkpoint 1: Interface the ADC with the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.7 Checkpoint 2: Display 4 Digits on the 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.8 Checkpoint 3: Interface the ADC with the 7-Segment Display . . . . . . . . . . . . . . . . . . . . . . . . 67
6.9 Checkpoint 4: Decode the Raw Output from the ADC and Display
. . . . . . . . . . . . . . . . . . . . . 68
6.9.1 Tips: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.10 Checkpoint 5: Combine Voltmeter with the Tekbot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.11 Study Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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CONTENTS
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Section 0
Preface
9
SECTION 0. PREFACE
0.1
Lab Overview
Welcome to the ECE 272 lab manual!
ECE 272 is an introduction to digital logic design, which is taught in ECE 271. This lab focuses on design hierarchy
that begins with schematic capture and finishes with Verilog Hardware Description Language. Interfacing digital logic
to a TekBot provides a unique opportunity to connect digital logic to a larger system. Chapter 2 creates a remote
control to move the TekBot. Chapter 4 uses digital logic to select between an analog controller and the digital remote
developed in chapter 2. Chapter 5 replaces the analog controller with a finite state machine. The final project, chapter
6, connects an Analog Digital Converter to digital logic. Adding an ADC allows for several interesting ECE 272 final
projects, such as measuring the voltage across the batteries, the current through the motors, or other interesting
signals within the TekBot. This lab provides the skills and tools to design digital logic systems and integrate them with
other digital or analog systems.
0.2
Objectives
• Materials
• Download and Install Diamond
• Build Modules
• Lab Manual Conventions
• Etiquette
• Resources
• Academic Dishonesty
• Preparation
0.3
Materials
• Lattice MachX02 Breakout development kit
• ADC Breakout board
• Button board
• Buck boost board
• TekBot from ECE 112 or ECE 199
• 4 Digit 7 Segment Display Board
• USB to mini cable
• Tool kit
• Soldering iron tip and barrel nut
• Solder
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0.4. INSTALLING LATTICE DIAMOND
0.4
Installing Lattice Diamond
1. Create an account on Lattice’s webpage
http://www.latticesemi.com/
2. Navigate to ’Products, Design Software & Intellectual Property, Lattice Diamond’
3. Click ’Downloads’ and select the most recent version for your operating system, for example ’Diamond 3.1 64-Bit
for Windows’
If you are not logged in, the actual program download may not appear
4. Request license by clicking on ’Licensing’ then ’Lattice Diamond Software Free License’ and following the instructions
Find your physical address by following the instructions at the top of the page
Make sure you choose your Wi-Fi adapter, not your Ethernet port
5. Download license file and place it into the correct folder
6. Install based on your operating system
Choose node-locked license when prompted for license settings
If you are using Windows 8, Diamond must be run in compatibility mode. This can be done
by right-clicking the shortcut, selecting properties, then checking the compatibility mode box
in the compatibility tab and selecting Windows 7
0.5
Building the Modules
To save time, while Lattice Diamond is installing, students will prebuild the modules used in later labs and solder
pins on the Lattice board. Building the modules are straight-forward yet time consuming processes and will take precious time away from implementing student designs. All modules come prepackaged with the necessary components.
1. Seven Segment Display Board
Mount and solder the four digit display on the top of the board with decimal places toward the pin-holes on the
bottom. Solder two(2) 2x5 male headers into their positions at the bottom of the board, along with a 1x8 row of
male headers in the adjacent slot.
2. ADC Breakout Board
Solder two(2) 1x10 rows of male headers on the left and right of the board. Then solder a 1x3 row of male
headers to the three holes at the top (WR-RD, RD). Finally, place a jumper connecting the pins labled WR-RD.
3. Eight Button Board
Solder all eight(8) buttons into their appropriate places. Solder a 1x8 row of male pins into J1-J8 and a 1x5 row
of male pins to the other five pin slots. Finally, solder the eight(8) zener diodes into D1-D8.
4. Add Pins to Lattice MachX02 Board
You will need many pins on your FPGA to handle the multitude of inputs and outputs being implemented. Some
important pins are 107-104 and 100-97 which are connected to the LEDs on the board. Use these pins to test
some of your designs.
TA Signature:
(Lattice Diamond installed and modules built)
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SECTION 0. PREFACE
0.6
Lab Manual Conventions
This lab uses the following symbols. Many of these are important and should not be ignored or skipped.
This symbol indicates an important note that should be remembered/memorized. Paying
attention to notes like these will make tasks easier and more efficient.
This symbol designates caution, and the information in this caution-table should be read
thoroughly, and adhered to, before moving ahead. If the caution warning is ignored, the task
may appear impossible and/or lead to damaged TekBot and systems.
This symbol represents something that helps you make your task easier by reminding you
to perform a particular task before the next step. These reminder symbols are not normally
critical things to complete, but can make things easier.
The innovation symbol will give information to enrich your experience. These sections will
give more insight into the what, why, and how the task being done. Use these to learn more,
or to get ideas for cool innovations.
Italicized writing is used to indicate the exact text on the menu or button for the next step in the lab manual.
The entire lab is divided into various sections, in order to break up the tasks. Typically, each section will have the
Section Overview as the introductory paragraphs and information detailing the tasks in the Procedure paragraphs. Towards the end, there are Study Questions (which will be your homework from this lab), and/or Challenges. Challenges
are extra credit and are great learning opportunities.
0.7
Etiquette
Proper etiquette in the labs is very important when working with other students or the Teaching Assistants (TAs).
Engineers work with many different types of people and need to be able to do so efficiently. Another part of proper
lab etiquette is also cleanliness in the lab. Engineers work in a variety of spaces. Sometimes they work in spaces that
are exclusively theirs, but many work in shared spaces. When sharing work spaces, it’s important to respect others
that must use that space by keeping it clean and removing any mess when finished.
Students
Students are expected to:
• Prepare for each lab.
Some labs require a prelab and background research before lab. Students should review appropriate sections
in the lab manual before going to lab. This is important to make sure all the required tools are available and you
have time to think conduct any necessary background research before lab.
• Ask questions.
Students should talk to their peers and the TAs when questions arise. Other people may have a different
perspective on an issue.
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0.8. RESOURCES
• Respect their peers.
Everybody comes from a different background and has a different level of knowledge.
Teaching Assistants (TAs)
Teaching Assistants are expected to:
• Ensure the lab is prepared.
TAs make sure the lab is kept in good working condition and the provided materials are ready for the students
during lab.
• Fairly assess student performance.
TAs should outline their requirements for full credit on prelabs and study questions at the beginning of the term
and grade to this standard for the term.
• Help students think through problems in lab.
TAs will not give instant answers to problems encountered. They are available to guide students towards the
correct answer.
Workspace
Keeping a workspace clean is very important. A messy workspace can be a safety hazard and create a chaotic
environment. It is much easier to lose a small component when there are other items cluttering the table top. It is also
important to keep a workspace clean because there are other classes that use the same room for their labs. Respect
the lab and the other people that are working in the lab.
0.8
Resources
There are many sources of information available for students in need of help. There is a hierarchy that students
should follow to ask questions before going straight to the instructor. When a student has a question they should start
on the first level to ask questions and progress from there without skipping levels.
1. Peers
A student’s peers should be the first people to ask when a question arises. Asking peers not only helps the
student with the question, but it reinforces the concept to the person asked when they explain it. A student has
many peers so the total amount of time available with peers is much more than any other resource.
2. Teaching Assistants
Teaching Assistants (TAs) have gone through this material before and are confident with the content, making
them a valuable source of information. They have recent experience as a student in course and can offer insight
regarding the course.
3. Instructor
Going to the instructor or professor with a question should only happen when other students and the TAs couldn’t
help. There is only a limited amount of time that an instructor is available for students to ask questions. Instructors will know the most about a topic and how it pertains to the course. Try to visit their office hours at least once
during the term. Bring prepared questions or some suggestions on how to improve the lab.
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SECTION 0. PREFACE
0.9
Academic Dishonesty
The following is taken from the Oregon University System, Oregon State University Student Conduct Code1 and
for more information please refer to it.
1. Academic or Scholarly Dishonesty is defined as an act of deception in which a Student seeks to claim credit for
the work or effort of another person, or uses unauthorized materials or fabricated information in any academic
work or research, either through the Student’s own efforts or the efforts of another.
2. It includes:
(a) CHEATING – use or attempted use of unauthorized materials, information or study aids, or an act of deceit
by which a Student attempts to misrepresent mastery of academic effort or information. This includes but
is not limited to unauthorized copying or collaboration on a test or assignment, using prohibited materials
and texts, any misuse of an electronic device, or using any deceptive means to gain academic credit.
(b) FABRICATION – falsification or invention of any information including but not limited to falsifying research,
inventing or exaggerating data, or listing incorrect or fictitious references.
(c) ASSISTING – helping another commit an act of academic dishonesty. This includes but is not limited
to paying or bribing someone to acquire a test or assignment, changing someone’s grades or academic
records, taking a test/doing an assignment for someone else by any means, including misuse of an electronic device. It is a violation of Oregon state law to create and offer to sell part or all of an educational
assignment to another person (ORS 165.114)
(d) TAMPERING – altering or interfering with evaluation instruments or documents.
(e) PLAGIARISM – representing the words or ideas of another person or presenting someone else’s words,
ideas, artistry or data as one’s own, or using one’s own previously submitted work. Plagiarism includes
but is not limited to copying another person’s work (including unpublished material) without appropriate
referencing, presenting someone else’s opinions and theories as one’s own, or working jointly on a project
and then submitting it as one’s own work.
3. Academic Dishonesty cases are handled initially by the academic units, following the process outlined in the
University’s Academic Dishonesty Report Form, and will also be referred to SCCS for action under these rules.
0.10
Preparation
Proper preparation allows for a smoother and more efficient lab time. Make sure to follow these steps before
starting each lab.
1. Start with a clean work space.
Often times, the electronic components used in lab are very small, and if dropped, they could be easily lost
(among usual desktop clutter). Therefore, put away papers, keyboards, mice, clothing, etc.
2. Keep your parts neatly organized.
Often times, parts come neatly packaged and ready for use. Do not dump all of these parts together, such as in
a box. Instead, if parts come separated in small bags, try to keep them that way. When taking parts out of their
packages, using a small container to keep them organized. Some people use ice cube trays, kitchen bowls, or
other containers.
3. Care for your tools.
The quality of electronics assembly is based on your own experience, and on the tools you use for the assembly.
Hence, try to keep your tools in the best condition possible. When using cutting tools, try not to cut things that the
tools are not designed to cut. An important lab rule to remember is to take care of your soldering iron properly.
1 http://arcweb.sos.state.or.us/pages/rules/oars
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0.10. PREPARATION
4. Make sure you have everything you will need.
When working with electronics, there is nothing more annoying than not having the parts you need, and/or having
to stop what you are doing to go find them. Prevent this by double-checking that you have what is needed before
starting the lab. This includes manuals, tools, components, pens, and paper.
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SECTION 0. PREFACE
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Section 1
Basic Combinational Logic and the
MachXO2
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SECTION 1. BASIC COMBINATIONAL LOGIC AND THE MACHXO2
1.1
Section Overview
The 7400-series logic chips were the most common digital logic devices around for many years. Most digital logic
implementations have moved either towards Programmable Logic Devices (PLDs) or towards Field Programmable
Gate Arrays (FPGAs).
The MachXO2 used in the TekBots program is an FPGA made by Lattice Semiconductor. There is more information about this board in Appendix A. This section will introduce you to Lattice’s FGPA development suite, Diamond, by
walking you through a simple schematic capture design.
1.2
Objectives
In this section, the following items will be covered:
1. Using the Lattice Diamond software to draft digital logic designs
2. Programming the MachXO2 provided in the ECE 272 kit
3. Verifying combinational logic designs
1.3
Materials
1. Lattice Diamond 2.2 software (Currently installed on the lab computers)
2. MachXO2 breakout board
3. Button Board (8pushbtn.0)
4. USB to mini-USB cable
1.4
Procedure
There are 6 steps to digital logic design:
Figure 1.1: This six step process is used for designing in ECE 272.
1. Design: The context of the design is established in the ”Design” step. The context involves defining the desired
output, input, and all of the logic required to connect the two. In this step, all of the minimizations and layout is
planned for the entry process. While this step is not always the most lengthy, it involves the most thought and
effort.
2. Design Entry: The actual drafting of the digital logic design occurs in this step. Drafting includes entering the
logic gates and blocks to build the design in the software tool.
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1.5. DESIGN
3. Design Simulation: Before committing to hardware, this step tests the design in a controlled computer simulation. If the design does not function as specified in the ”Design” step, it is revised.
4. Synthesize and Map Design: When the design simulates correctly, the source files are synthesized into a
design file that configures the FPGA. Mapping the design to pins assigning the inputs and outputs of the design
to IO pins on the MachXO2 FPGA.
5. Program Hardware: After the design file is created it is used to configure (program) the MachX02 FPGA. Programming uses the USB to mini-USB cable and the Lattice Diamond software to send a bit stream to configure
the FPGA.
6. Test Hardware: Verify hardware operation once the FPGA has been programmed. The FPGA should operate
exactly as the simulation predicted, but timing problems or incorrect assumptions about the hardware can require
the designer to return to the ”Design” step.
1.5
Design
A good design is the key to any successful project. In electrical engineering, many of our designs stem from a
’Block Diagram’ developed near the start of a project and evolved throughout the course of it. Block diagrams can
encompass all levels of detail and abstraction in a project, so choosing the scale of the initial diagram can be a
challenge. A good starting point is to represent each piece of hardware with a block and define all interfaces with it.
Figure 1.2 shows the start of a simple block diagram for this lab.
Figure 1.2: Incomplete block diagram for Section 1
At the beginning of a project, the block diagram should include:
• Labelled blocks representing each piece of hardware used in the project
• All interfaces (connections) between blocks, represented with lines
• Which signals are carried on each interface
• How the interfaces connect to each block, for example: pin numbers
Depending on the project, more detail is added to the block diagram, often with very detailed blocks inside of the main
hardware blocks.
Figure 1.3 is the design that will be drafted in Diamond.
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Figure 1.3: Section1 Combinational Logic
There are a few design choices that are dictated by the hardware.
1. The buttons on the button board are active low. This means that without a pullup resistor, the button’s output
will float when they are unpressed and output logic low (0) when they are pressed. With a pullup resistor on the
output, the output will be pulled up to a logic high when unpressed and logic low when pressed. Refer to Figure
1.4 to get a partial schematic of the button board. The full schematic can be found in the appendices.
Figure 1.4: Example of an active low button
2. The LEDs on the MachXO2 are active low. This means they turn on when a logic low signal is sent to the FPGA
pin and they turn off when a logic high signal is sent.
1.6
Design Entry
1.6.1
Start Diamond
Click Start → All Programs → Lattice Diamond 2.2 (64 bit) → Lattice Diamond
Installation instructions for Diamond can be found on the ECE272 page on TekBots.com
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1.6. DESIGN ENTRY
1.6.2
Create a New Project
A project in Lattice Diamond is a collection of sources (Schematic or HDL), testbenches, and simulation outputs.
Follow these steps to create the project for this section:
1. Click File → New → Project
2. Click Next to advance
3. In the Project Name field, enter ”section1”. Note that the project name automatically creates a subdirectory in
the main directory path. However, the main directory must be specified.
4. In the Project Location field, browse to the directory that will store all projects and create a new folder for
Section1. Diamond does not automatically create a folder for each project. Click Next.
Using the C:\drive to store projects will make the software operate quicker than using the
Z:\drive. Using the Z:\allows access to project files from any lab machine and is regularly
backed up. The files in C:\are stored locally and can only be accessed from one computer.
Keep a back up on Z:\to avoid frustrating crashes that will cause all project files to be
corrupted.
5. In the Add Source window, leave everything blank and click Next.
6. Set the Device Settings to match Figure 1.5 and then click Next.
Figure 1.5: Copy these values for all projects
7. Select Lattice LSE as the Synthesis Tool and click Next.
8. Review the Project Information and click Finish.
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9. The project’s Input Files folder is empty at this point. To add a source, Click File → New → File
10. In the New File window, under Source Files, select Schematic Files.
11. In the File name field, enter ”section1 schematic”
12. Make sure that the Add to Implementation box is checked and then click New.
13. The Diamond project screen will now be showing the blank schematic file.
1.6.3
Schematic Entry
Follow these steps to create the schematic shown in Figure 1.3:
Add Symbols:
Follow these steps to add logic gates to the schematic:
Figure 1.6: Add symbol process
1. Click the Symbol button
2. Select the lattice.lib library.
3. Select and2.
4. Place one AND gate onto the schematic.
5. Add both of the other gates from Figure 1.3 onto the schematic.
Connect the Symbols:
Use Figures 1.7 and 1.8 to understand how to properly draft a schematic. Proper design has inputs on the
left stretching vertically and logic gates connected to the correct input lines. Use this general structure to create a
schematic that reveals the structure, intent, and flow of the design.
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1.7. DESIGN SIMULATION
Figure 1.8: Good Layout
Figure 1.7: Bad Layout
1. Click the Wire button
2. Wire all of the symbols together. Left click once for each segment, right click to stop placing wire.
3. Add hanging wires off of the inputs and output so that they can be named and designated as inputs or outputs
in the next step.
The marker for hanging wires and nodes are the same: a small square. Always double
check these to make sure that you have made the connection that you intended.
Define Inputs and Outputs
Labeling the inputs and outputs on the schematic allows diamond to create a netlist during the synthesis process.
A netlist contains all inputs, outputs, and gates for the design.
and rename the hanging wires A, B, C, and Z. The labels must be placed on the
1. Click the Net Name button
very end of the hanging wires or Diamond will not correctly place IO markers in the next step.
2. Click the IO Port button
and specify the type as Input, and add a marker to A, B, and C.
3. Add an Output marker to Z.
4. Save the schematic (Ctrl-S).
1.7
Design Simulation
This design is trivial and the simulation of it will not fit in this lab. Simulation of digital logic designs will be in a
future section of ECE 272.
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1.8
1.8.1
Assign Pins
Synthesis
During synthesis, the design is minimized and transformed into a netlist describing the hardware. Minimizations
reduce the amount of hardware and space required for the design. After synthesizing, Diamond knows how many
inputs and outputs are required for the design. Follow this process to synthesize the design.
Figure 1.9: Synthesize Design
1. Open the Process tab to the left of the schematic and double click Synthesize Design.
1.8.2
Spreadsheet View
Spreadsheet view is a tool that will connect A, B, C, and Z from the schematic to Inputs/Output pins on the
MachXO2. Use Figure 1.10 to organize the information required for Spreadsheet view. The PULLMODE setting
determines if the port reads high (1) or low (0) when the port is undriven. PULLMODE UP assigns a pullup resistor
to pull the pad voltage up to VCC. This results in an input port reading logic high when it is undriven. The FPGA pins
are printed on the silkscreen of the MachXO2 board.
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1.8. ASSIGN PINS
Figure 1.10: This table should be recreated for every ECE 272 project
Without a pullup resistor an input pin will float between logic high and logic low when the button is unpressed.
Floating inputs cause eratic behavior.
Run Spreadsheet View
Follow these steps to run Spreadsheet view and configure the IO pins.
Figure 1.11: Spreadsheet View
1. Click Tools → Spreadsheet View
2. In Spreadsheet View, select Port Assignments along the bottom edge. This page contains all the inputs and
outputs from your schematic.
3. Assign the IO pins that you chose for each input and output in the Pin column.
Outputs in Spreadsheet View should be assigned to the active low LEDs on the MachXO2 so the output
can be quickly verified. Figure 1.12 contains the FPGA pins for the LEDs.
Inputs in Spreadsheet View should be assigned to empty IO pins on the MachXO2 and later connected to
the active low buttons on the button board.
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Figure 1.12: MachXO2 LED pinout
4. Select whether the port will use a pullup or pulldown resistor in the PULLMODE column.
5. Save the pin assignments (Ctrl-S).
LEDs are an extremely useful tool for circuit verification, since they visually show the designer what is happening during any given moment. Carefully picking which signals get
assigned to the LEDs can make troubleshooting much easier and save you a lot of time
later.
1.8.3
Creating the Programming File
The programmer needs a .jed (JEDEC programming specification) file in order to program the MachXO2. This
step uses Diamond to generate a .jed programming file.
1. Open the Process tab to the left of the schematic and double click JEDEC File under Export Files.
1.9
1.9.1
Program Hardware
Program the FPGA
Use this process to program the .jed file onto the FPGA. :
Figure 1.13: Programmer
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1.10. TEST HARDWARE
1. Plug the MachXO2 into the computer with the provided USB cable.
Communication between the Breakout Board and a PC via the USB connection cable requires installation of the FTDI chip USB hardware drivers. Loading these drivers enables the
computer to recognize and program the Breakout Board. Refer to the Diamond Installation
instructions for FTDI driver installation instructions.
2. Click Tools → Programmer
3. Click OK to identify the correct cable.
If Diamond cannot identify the target device, manually select ”LCMXO2-7000HE” from the Device dropdown
menu.
4. In the File Name column, browse to the .jed file that Diamond created in the project directory.
5. Click Program
1.9.2
Assemble the Push Button board
The inputs A, B, and C will be provided by the push button board. J1-J8 correspond to each of the buttons in order.
For the applications in this lab, if SW COM is tied to ground, the outputs J1-J8 can be connected to the FPGA and the
buttons will operate as active low buttons. To assemble the push button board, follow these steps. All required parts
should be in the kit.
1. Solder the buttons onto the board, making sure the buttons are installed in the proper direction.
2. Solder the diodes onto the board, making sure the diodes are installed in the proper direction.
3. Solder male header onto the board in J1-J8, GND, VCC, SW COM, COM LVL, and COM EN.
Soldering the header into either side of the PCB will function identically, however, it will be
easier to use the buttons if they are placed on the opposite side as the buttons.
1.10
Test Hardware
Create and fill in a truth table that shows your hardware operates correctly. This truth table has 3 inputs and 1
ouput. Look at Figure 1.14. Assume that A and B are active low buttons and Z is connected to an active low LED.
The filled in row indicates that when A is not pushed, B is pushed, then the output Z turns on the LED. This truth table
should match your simulation results.
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Figure 1.14: Truth Table for Section 1 Testing
TA Signature:
(The MachXO2 board logic is operational & lab work is displayed)
1.11
Study Questions
1. Turn in a printed copy of the schematic designed in this lab.
2. Describe any problems encountered in this lab and your solutions to those problems.
3. Research discrete logic ICs, such as the 7400 series logic chips. Discuss two advantages and two disadvantages to using an FPGA versus discrete logic ICs.
1.12
Challenge - Extra Credit
Research a ring oscillator. This circuit is a great way to explore the propagation delay of a simple logic gate (the
inverter). Credit for the challenge is allocated based on lessons learned from experiments that you design yourself.
Here are some beginning ideas:
1. Try to implement a ring oscillator with an integrated circuit of 7400 series logic chips. These ICs will need to
be purchased either online, from TekBots in KEC 1110, from the IEEE store in the Dearborn basement, or from
a local electronic parts store. How fast does it oscillate? How does the propagation time relate to the VCC
powering the integrated circuit?
2. Try to implement the ring oscillator with the FPGA. How fast does it oscillate? Can the FPGA be reconfigured to
operate faster or slower?
3. Try to implement the ring oscillator with hand made inverters (either CMOS or RTL). How fast does it oscillate?
Does it vary with temperature?
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Section 2
Combinational Logic (Custom Remote
Control)
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SECTION 2. COMBINATIONAL LOGIC (CUSTOM REMOTE CONTROL)
Pre-Lab
1. In the space provided, draw a block diagram for a custom remote control using the following description:
The remote control will use three buttons which are separate from the FPGA board as inputs to the combinational logic. There will be a block for combinational logic with four outputs going to the motor controller board
on the TekBot. Make sure to label each block, the input and output names, Pins used on the FPGA, GND, and
Vcc.
Make sure your block diagram is neat and organized.
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2.1. SECTION OVERVIEW
2.1
Section Overview
One of the most challenging concepts in robotics and control designs is the system used in remote operated vehicles (ROVs). Such systems need to be able to work in remote locations, (sometimes under extreme conditions) and
perform for long periods of time. In order to implement this capability in this system, the top priority is to control the
device effectively, so that it does not waste valuable energy and does not damage itself.
There are two main types of controls used in modern robotics: local control and remote control. Local control refers to
the usage of artificial intelligence, so that the robot itself can think without external control. This intelligence is usually
very basic, and can be compared to an insect’s brain (with only simple functions such as obstacle avoidance). Remote
control allows the ROV to be directed from a different location, but the time to transmit these commands to the robot
can be significant. It takes between 4 and 21 minutes to send a radio signal to Mars1 .Section 2 focuses on designing
a custom remote controller for the TekBot.
2.2
Objectives
1. Defining the problem — what is the controller really doing?
2. Defining the inputs to the combinational logic
3. Defining the outputs from the combinational logic
2.3
Materials
2. MachXO2 breakout board
4. A TekBot with a working motor controller and batteries
5. Button board (8pushbtn)
2.4
Procedure
Figure 2.1: Use this process for designing the custom remote control.
1 http://mars.jpl.nasa.gov/mgs/faqs/faq
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2.5
Design
Figure 2.2 shows all of the different actions that the remote control should accept.
Figure 2.2: The remote control should use all of these actions
2.5.1
Make a block diagram
1. Add the power source used for each of the three blocks. The FPGA takes 5V in from the mini-USB port and the
motor controller board takes 9V from the charger board.
The boards need to share a common ground between them or you will have problems with floating outputs.
2. Label the FPGA pins on the block diagram.
The FPGA pins are printed on the breakout board. Find which ones will be convenient to use for the inputs
and outputs and label them on the block diagram.
3. Label which outputs on the FPGA are connected to Le, Ld, Re, and Rd on the Motor Controller board.
Le stands for left motor enable, Ld stands for left motor direction, Re stands for right motor enable, and Rd
stands for right motor direction.
Figure 2.3: Incomplete Remote Control block diagram
Don’t forget to connect all of the grounds, so that there is a common ground for your seperate
boards.
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2.6. DESIGN ENTRY
2.5.2
Make a functional truth table
1. Add the binary value of the inputs for each row. Remember the buttons are active low. If A = 0, that means
button A is being pressed.
2. Add the binary value for the outputs for each row. Use Figure 2.4 for a reference on how the motor controller
operates.
Remote Control Functional Table
TekBotActions
Forward
Backward
SwingLeft
SwingRight
SpinLeft
SpinRight
DoNothing
DoNothing
Inputs, ABC
Left Motor Direction
Right Motor Direction
Forward
Stopped
Outputs: Le,Ld,Re,Rd
Figure 2.4: Motor Control Inputs for the Tekbot Motor Control Board
2.5.3
Minimize the logic
1. Write out the canonical form for Le(A,B,C), Ld(A,B,C), Re(A,B,C), and Rd(A,B,C). Use Σ or Π.
2. Use four K-maps to make minimized logic for Le, Ld, Re, and Rd. Write out the minimized Boolean Equations
for each output.
2.6
Design Entry
Enter the design using the same process as in Section 1.
2.7
Design Simulation
In this section the design is tested by entering in all possible input combinations and comparing the simulated output to the desired output. If they match, the design is verified and the process can advance. If there are discrepancies,
debug and try again until the desired output is achieved.
2.7.1
Creating the Testbench
Follow this process and refer to Figure 2.5 to create a Verilog testbench. A testbench contains commands for
simulation.
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Figure 2.5: Testbench generation process
1. Synthesize the design. Double click Synthesize Design on the Process tab.
2. Right click the top level source on the Hierarchy tab and click Verilog Test Fixture Template.
Diamond puts this testbench into the source files folder on the File List tab.
2.7.2
Changing the Verilog Template
Input all of the simulation directives here. These tell the simulator what different combination of inputs to use
and how long to hold each combination. The output will be displayed based on the input directives inserted in the
testbench.
Figure 2.6: The lines of code between initial begin and end should match this.
1. Change the text between ”initial begin” and ”end” to match Figure 2.6.
The #10 at the beginning of each line denotes how long the simulation is to use that combination of inputs before moving on to the next line. It is measured in nanoseconds.
2.7.3
Running the Simulation
1. Run Simulation Wizard. Tools → Simulation Wizard
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2.8. ASSIGN PINS
2. Welcome Screen: Click Next to pass the welcome screen.
3. Simulator Project Name: Type any name for Simulator Project Name. This will create a new folder within your
project folder that holds the simulation files. Ensure Active-HDL is selected for as the Simulator and click next.
Click Yes to create the simulation folder.
4. Process Stage: This option selects the amount of realism the simulation will use. Select RTL for simulating ideal
conditions (no gate or trace delay).
5. Add and Reorder Source: Ensure that all of the source files and the testbench file are located here in the box
(they should be auto-populated by default. If they are missing, backtrack and find where a mistake was made).
Click Next to advance.
6. Parse HDL files for simulation: Ensure that no errors appear in the output box and that the testbench is selected
as the ”Simulation Top Module.” Click Next.
7. Summary: Make sure all check-boxes are selected and click Finish.
8. Prompt: If a prompt appears, the simulation has previously ran. Click Yes to overwrite old settings and the
simulator will open.
ActiveHDL must be closed and restarted before you can simulate again.
Zooming in and out of the simulation makes the outputs easier to see. Zoom by holding the
Ctrl key and scrolling with the scroll wheel or by using the zoom controls on the top toolbar.
2.8
Assign Pins
Follow the same process for using Spreadsheet view as in Section 1.
2.9
Program Hardware
1. Program the MachXO2 using the same process as in Section 1.
2. Wire the FPGA to the Tekbot using the block diagram made earlier as a guide.
Remember to power and ground the FPGA from the USB Buck Boost converter or a computer.
The I/O pins on the FPGA cannot be used to control the motor controller board unless the
FPGA is also supplied with a ground from the Tekbot charger board. The boards need to
share a common ground between them or there will be undefined logic with floating outputs.
3. Take a wire from GND on the FPGA and connect it to a GND on the motor controller board.
2.10
Test Hardware
Validate that the hardware performs according to the functional table completed earlier in Section 2.
TA Signature:
(TekBot functions properly & work is displayed)
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2.11
Study Questions
1. Make a modified block diagram using Figure 2.3, that includes a block of logic for reverse lights. Include the
required logic to turn on the backup lights when the TekBot is moving backwards. Use A, B, and C as inputs for
this combinational logic.
2. Make a modified block diagram using Figure 2.3, that includes a block of logic for reverse lights. Include the
required logic to turn on the backup lights when the TekBot is moving backwards. Use Le, Ld, Re, and Rd as
inputs for this combinational logic. Include the required logic to turn on the reverse lights.
3. Recreate a block diagram similar to Figure 2.3 and a functional truth table like the one used in this lab to use the
digital logic board to control a L293 motor controller chip. The datasheet for this chip is on the lab website. Note
that this chip uses tri-state buffers which are described in page 80 of the ECE 271 textbook. Do not use the
block diagram or the functional truth table from the datasheet; those are not examples of what we are looking
for.
(Hint: This is the same motor controller IC that was used in ECE 111.)
2.12
The Section 2 project currently uses 4 or 5 wires (A, B, C, Ground, and possibly Power). Redesign this project to
only use 2 wires (Analog signal and ground). Use an R2R ladder as an analog encoder and use a discrete analog
digital converter (ADC) as the analog decoder. Draw the exact schematic for the analog encoder, analog decoder,
and how everything connects together.
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Section 3
Combinational Logic (Seven Segment
Driver)
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SECTION 3. COMBINATIONAL LOGIC (SEVEN SEGMENT DRIVER)
Pre-Lab
Using the appendix, fill in the letter designations for each segment of the seven-segment display in Figure 3.1.
Figure 3.1: Fill in the letter for each segment here
Figure 3.2 shows all of the different outputs that the seven segment decoder should produce. Shade in the
segments that should be on for each input, 0-F.
Figure 3.2: The decoder should produce all 16 outputs
Turn in the block diagram as part of the Pre-Lab questions. Use clean paper and write neatly.
1. Add the power source used, if any, for each of the three blocks. See Figure 3.6 for information about how to
power the 7 segment display board.
2. Label all FPGA pins that are used for this project on the block diagram.
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Figure 3.3: Incomplete block diagram for the remote control
1. Use the shading in Figure 3.2 and the diagram in Figure 3.4 to fill in the functional truth table below.
Figure 3.4: This diagram indicates which segments are which on the display (should match what was found in the
pre-lab.)
Input Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
¯ C¯ D
¯
Inputs, A¯B
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SegA
0
SegB
0
SegC
0
SegD
0
SegE
0
SegF
0
SegG
1
Make sure to double check the above table for accuracy. Errors this early in the design can
lead to a lengthy debugging process.
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Minimize the logic
1. Use seven K-maps to make minimized logic for SegA , SegB , SegC , SegD , SegE , SegF , and SegG .
2. Write out the minimized Boolean Equations for each output.
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3.1
Section Overview
Being able to display numbers is useful for a variety of applications. Seven segment displays are used to display
numbers in alarm clocks, VCRs, microwaves, and many other devices. Section 3 builds a seven-segment display
decoder, which is described in Example 2.10 of the ECE 271 textbook. The decoder will take a 4 bit bus as input from
buttons and output a 7 bit bus for the seven segment display.
3.2
Objectives
1. Define the problem, what is the decoder really doing?
2. Define the inputs to the combinational logic.
3. Define the outputs from the combinational logic.
3.3
Materials
2. MachXO2 Breakout Board
3. Seven segment display board (4digit.0)
4. Button board (8pushbtn.0)
6. TekBot charger board.
3.4
Procedure
Figure 3.5: Use this process for designing the seven segment display.
3.5
Design Entry
Enter the design using the same process as in Section 1.
A larger workspace in Diamond will be needed to fit the entire minimized schematic. To
change the schematic size click Edit → Sheet.
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3.6
Design Simulation
Simulate the design to verify correct operation of the digital logic. Use Section 2 as a guide for this process.
3.7
Assign Pins
Follow the same process for using Spreadsheet View as in Section 1.
3.8
Program Hardware
1. Program the FPGA
3.8.1
Test Hardware
1. Wire together the FPGA and Seven Segment Board as depicted in the block diagram made earlier. Refer to
figure 3.6 for wiring instructions. Make sure that every labelled pin on the diagram is connected. The select pins
should be attached according to the table on the left of the diagram.
2. Test to see if the buttons cause the correct outputs on the seven segment display.
Figure 3.6: Display Board wiring diagram.
TA Signature:
(Seven Segment display is working and all lab steps are shown)
3.9
Study Questions
1. When is a simulation necessary? Was it useful for this section?
2. Attach the detailed block diagram, digital logic schematic, and simulation results for this project.
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3.10. CHALLENGE - EXTRA CREDIT
3.10
Set up the 4digit 7 segment display board so different digits can display multi-digit numbers, such as 12:34.
Reference the table provided earlier in Figure 3.6 for selecting the different digits. The remaining push buttons can
be used as the input to select the digit. Note that the display board does not allow for multiple digits to be illuminated
simultaneously; however, by switching between the digits quickly enough it appears as though several digits are lit at
the same time. This method of displaying data visually is a concept called persistence of vision (POV).
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Section 4
Modular Combinational Logic Using HDL
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SECTION 4. MODULAR COMBINATIONAL LOGIC USING HDL
Pre-Lab
1. Read the Introduction to Verilog section of the lab manual, then write a Verilog module based on the block
diagram in Figure 4.1. Pay careful attention to net names.
(Hint: The AND and OR gates can be implemented with single line operators)
Figure 4.1: Prelab Block Diagram
module prelab_block (
endmodule
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2. Write out the Verilog for a 2:1 multiplexer with 1-bit inputs and output.
(Hint: Look in the textbook for help.)
module mux2 (
endmodule
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4.1
Section Overview
The schematic capture feature of Diamond is useful for visualizing layouts, but quickly becomes tedious for even
moderately complex layouts, as experienced in the prior section. Using an HDL (Hardware Description Language),
such as Verilog, is a quick and efficient way to draft digital logic designs and avoid most of the small bugs that make
schematic capture frustrating.
The key to using an HDL is to create a solid design before starting to program. Since we are describing hardware
with our code, the easiest way to transition from design to implementation is by using block diagrams. This section
will introduce you to Verilog and walk you through the implementation of a design using verilog in Diamond.
4.2
Objectives
1. An introduction to using Verilog
2. A Verilog reference design
3. Step by step requirements for drafting a complete digital logic design on paper
4. Using the schematic viewer to inspect the synthesized Verilog description
4.3
Materials
1. Lattice Diamond 2.2 Software (Currently installed on the lab computers)
2. MachXO2
3. Small breadboard and resistors
4. A working TekBot with the analog control board
5. Button board (8pushbtn)
6. The ECE 271 textbook, Digital Design and Computer Architecture by David and Sarah Harris
4.4
Verilog Introduction
This section will describe the general components and use of verilog. Example code has been provided on the
Tekbots webpage, which should help with the visualization of the concepts covered.
Verilog, from a high level, is comprised of modules and instances. Modules are a general set of inputs and outputs
with a defined relationship, while instances are a specific application of a module. A good analogy for modules and
instances are integrated circuit chips: hundreds of physical chips with the same part number exist in various designs,
but they all operate based on a single definition. Similarly, we define a ”chip” once with a module, then we can use it
repeatedly in different designs by simply instantiating it.
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4.4. VERILOG INTRODUCTION
4.4.1
Modules
Projects are going to start with a ’top module’. The top module is what is synthesized and implemented onto our
board. What this means for us is that any inputs and outputs that we want to connect to pins on our MachX02 need
to be defined in the top module. These top level inputs and outputs will also be used for simulation. Many different
ways of formatting verilog code exist online. Any of these styles can be used, but the format shown in Figure 4.2 will
generally produce easier to read and, more importantly, easier to debug code. Anywhere where a name is contained
inside of angle brackets, it should be replaced with an intuitive name of your choosing. Be aware that some words are
reserved by Verilog.
Figure 4.2: Module Example Code
4.4.2
Instances
The process of creating an instance from a module is called instantiation, and includes giving the instance a unique
name and connecting signals to the inputs and outputs.
The code in Figure 4.3 shows an example of an instance. The instance starts with the name of the module that
it’s instantiating, then gives the instance a unique name. Each of the inputs and outputs from the module is then
connected to a corresponding wire. Inputs can be tied to registers, but outputs cannot be directly tied to registers.
Building off of the chip analogy, the dots ’.’ represent pins that must be connected to, while the wire being connected
is contained by the parenthesis (). If an input or output is a bus (more than one bit), make sure that the connected
wire is a bus of the same length.
Figure 4.3: Instance Example Code
Modules are often stored in separate files, as can be seen in the reference design, and can still be instantiated into
other modules if both files are selected as input files for the project. This separation makes code much cleaner and
easier to debug, while at the same time allowing modules to easily be used in many projects. Input files don’t even
have to be verilog files to be instantiated. For instance, schematic capture circuits can be instantiated into a module
by using the file name as a module name and looking up the input and output names from the schematic.
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4.4.3
Wires
Wires are used for making connections that exist inside of the block, but aren’t inputs or outputs. If an instance
interfaces with an input or output signal, then that net can be directly connected to the instance, a wire is not required.
Multi-wire buses can also be declared. Wires and buses are declared as shown in Figure 4.4.
Figure 4.4: Wire Example Code
4.4.4
Reg Data Types
Reg types are used to store values, and can be referenced similarly to wires, but can only be modified synchronously. This means that assignments to a reg must always occur inside of ’always’ statements. A reg can not be
modified by multiple ’always statements’; all changes must occur within the same statement. Regs, like wires, can be
multiple bits. Examples of declaring and assigning to regs are shown in Figure 4.5.
Figure 4.5: Register Example Code
4.5
Reference Design
A reference design is available on the Tekbots webpage, titled LED StateMachine 272.zip. In order to use the
reference design, unzip the folder, then create a new project like in other labs. When Diamond prompts you for source
files, click ’Add Source...’ and select the three files contained in the zip file. Once the project has been created,
the verilog files can be opened by clicking the ’File’ tab on the left side, then double clicking each of the input files:
’LED FSM top.v’, ’Clock Counter.v’, and ’State Machine.v’.
This project is a simple LED scroll pattern in order to show module/instance interaction, a clock instance, a clock
counter, and a state machine in a functional setting. When programmed, the 8 LEDs should show a scrolling pattern,
where two, 3-LED bars rotate around the array.
IMPORTANT: This is a reference design, not skeleton code. The modules can be instantiated into new designs,
but the top module should not be copied into other designs or be the basis for them. New designs should start with a
blank .v file.
Figure 4.6 shows the block diagram for this project, compare the names of nets, instances, and module inputs/outputs to the actual code. The LEDs are placed in an external block because, while they are part of the breakout
board, they are not part of the chip that is being programmed.
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4.5. REFERENCE DESIGN
Figure 4.6: Reference Design Block Diagram
Key things to note from each input file: LED FSM top:
• This is a top module, so it is effectively what is programmed onto the board. Inputs and outputs from this module
get tied to physical pins on the chip.
• A clock instance is used in this module. It is a built in module, so it is only know by looking up the code in a
datasheet or reference design. The frequency can be modified by changing what is currently ”2.08”. Only certain
frequencies exist, 2.08MHz is the slowest, but others can be found in datasheets on the Lattice webpage.
• The state machine and clock counter are instantiated here from external files. Notice how the formatting doesn’t
change at all from the example above; imagine that all of the files get appended to each other when it gets
programmed.
Clock Counter:
• Registers are used in this module since the output is based on a changing input signal. Notice how the count
register is only modified inside of the always statement. Special assignment called non-blocking assignments
are also used: ’<=’. Non-blocking assignments are used for non-sequential assignments inside of a triggered
action. More information about these can be found online.
• An ’always’ statement is also used here. It is used to look for edges of changing signals, and execute a sequence
when one occurs. They must be used when modifying registers, but cannot be used to modify wire signals.
These statements will often be seen with no edges, like ’always @ (*)’. This means that whenever any of the
signals change, run the sequence. It is often used for simple combinational logic.
State Machine:
• A Moore state machine is implemented in this module. Formatting can be found in the example pdf provided on
the Tekbots webpage.
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4.6
Procedure
Figure 4.7: Use this process for designing an intelligent remote.
4.7
Design
The custom remote control, Section 2, gave the TekBot an ability to understand commands. This section uses the
analog control board to override the commands from the buttons and force the TekBot to automatically back up and
turn when it runs into an object. Essentially the remote control should only work when the analog control board is
outputting a ’forward’ signal.
4.7.1
Figure 4.8 is the layout for your block diagram. It is incomplete. A completed block diagram will be turned in with
the study questions so write neatly.
2. Label which inputs on the FPGA are connected to the analog control board LeftDirection and RightDirection, Al
and Ar.
3. Label which outputs on the FPGA are connected to Le, Ld, Re, and Rd.
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4.7. DESIGN
Figure 4.8: Incomplete block diagram for the smart remote control
The Analog Control board outputs 5.6V but the maximum input voltage for the FPGA is 3.3V.
Use level shifters to reduce the voltage to avoid destroying the FPGA.
3.75 volts is the absolute maximum voltage that should be connected to an input pin. This value is found on page 42
of the MachX02 data sheet1 . Voltage dividers, diode circuits, inverters, or other types of level shifters will be sufficient.
4.7.2
The TekBot should operate according to the functional table below:
Controller
AnalogControl
AnalogControl
AnalogControl
Section2
Section2
Section2
Section2
Section2
Section2
Section2
Section2
4.7.3
Inputs: Al, Ar, A, B, C
00xxx
01xxx
10xxx
11000
11001
11010
11011
11100
11101
11110
11111
TekBotAction
Automatic Reverse
Automatic Turn
Automatic Turn
Section2 Command
Section2 Command
Section2 Command
Section2 Command
Section2 Command
Section2 Command
Section2 Command
Section2 Command
Outputs: Le, Ld, Re, Rd
Plan the design
Figure 4.9 has the design needed for this section. There are three types of modules, Section 2, an AND gate, and
4 multiplexers. There are six instances that all need unique names that obey the Verilog naming conventions 2 . There
1 http://www.latticesemi.com/documents/38834.pdf
2 http://www.xilinx.com/itp/xilinx4/data/docs/dev/ngd2ver10.html
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are 14 nets used inside of Section 4. Assign each net a unique name.
Figure 4.9: This is the schematic for the smart remote control
4.8
Design Entry
1. Create a new project.
2. Create a new source with Verilog module as the source type.
Chapter 4 in the textbook has numerous examples on how to format Verilog modules
3. Add the schematic source file from Section 2 to the project.
4. Instantiate the Section 2 schematic in your Section 4 Verilog source file.
The module name for the schematic is the name of the schematic file.
5. Type an instantiation of the Section 2 schematic into Section A of Figure 4.10.
Section 4.3 in the textbook covers how to create instances of modules.
6. Write the name of the net that connects to each port of the Section 2 instance into the ( )’s.
7. Create a 2 input mux module.
Refer to the Verilog Reference sheet for a model for a mux that has two 4 bit buses entering as inputs and
one 4 bit bus as an output.
Modify this module to have two 1 bit inputs, 1 select bit, and 1 bit output. Place the module definition in
Section B of Figure 4.10.
8. Create four instances of the mux in Section A of Figure 4.10 and make identifiable instance names.
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9. Add the line supply0 GND; into Section A of Figure 4.10.
This will create a net called GND that will be used for grounding inputs of the multiplexers.
10. Make an AND gate in section A of Figure 4.10.
(Hint: This will not need a separate module.)
11. Synthesize the design
Process tab ⇒ Synthesize Design
12. View the HDL Schematic
click Tools ⇒ HDL Diagram
13. Print this HDL Schematic to turn in with your Study Questions.
Figure 4.10: This is the screen for a Verilog source in Lattice Diamond.
4.9
Design Simulation
Follow the same process for using the simulator as in Section 2.
4.10
Assign Pins
4.11
Program Hardware
1. Program the Lattice FPGA
2. Wire the Tekbot and FPGA as depicted in the block diagram created earlier.
Be sure to use voltage dividers to connect the two analog inputs of the FPGA to the left and right dir
(direction) pins on the Analog Control Board.
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TA Signature:
4.12
Study Questions
1. Include a detailed block diagram of Section 4, the HDL Schematic, and a copy of the Verilog source.
2. Discuss two advantages and two disadvantages to using HDL versus schematic capture from previous sections.
3. A standard 2 input multiplexer is built using 3 gates, why are two of the multiplexers in this design built using only
1 gate?
4. Write the Verilog equivalent of Section 3, the seven-segment display encoder. Include A - F outputs. Explain the
benefit of using HDL instead of schematic capture for this application.
Look at HDL Example 4.24 on the Verilog reference sheet, available at Tekbots.com, for guidance.
4.13
Make a self-checking test bench to verify correct operation of Section 4. Look at page 215 of the textbook for more
information. For full credit turn in a copy of the verilog source with a written explanation of how it works.
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Section 5
Finite State Machine Using HDL
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SECTION 5. FINITE STATE MACHINE USING HDL
Pre-Lab
1. Write out the Verilog for a 2:4 decoder.
(Hint: Look in the textbook for help.)
module decoder2_4(
endmodule
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5.1
Section Overview
Section 4 used an analog controller to control the timing of a TekBot that automatically backs up and spins away
from the object that bumped it. This section uses a finite state machine to control the timing of backing up and spinning
away from the obstacle.
5.2
Objectives
1. Step by step requirements for drafting a complete finite state machine design on paper.
2. Using HDL examples 4.32 on the Verilog reference sheet, available at Tekbots.com, to describe a finite state
machine.
5.3
Materials
2. MachXO2 Breakout Board
3. TekBot with the motor control board
4. ECE 271 textbook, Digital Design and Computer Architecture by David and Sarah Harris
5.4
Procedure
Figure 5.1: Use this process for designing an intelligent remote.
5.5
High Level Preparation
Section 5 is going to digitally reproduce the analog control board.
5.5.1
2. Label which inputs on the FPGA are connected to the right and left bumper of the sensor board. Are these going
to be active high or active low? Do they need pull-up or pull-down resistors?
3. Label which outputs on the FPGA are connected to right enable, right direction, left enable, and left direction of
the motor control board.
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5.5.2
Make a state diagram on paper
1. The bump-bot created in this lab will drive straight until it hits an obstacle. If an obstacle is hit, the Tekbot will
back up, spin away from the object, and continue driving forward. The state diagram for this project is shown in
Figure 5.2.
Figure 5.2: This is the state diagram for the digital version of the analog control board
The reset, left bumper and right bumper inputs are all active low. With active low inputs, if(Lbum) will
evaluate to ”True” when the left bumper is not pressed. In order for the if statement to evaluate true when the
left bumper is pressed, use an exclamation point if(!Lbum).
2. Label each state with a digital encoding.
How many bits are needed for 5 seperate states?
3. Label the outputs for each state. This is going to be a Moore State Machine, so the outputs depend only on the
current state.
A Mealy state machine’s output depends on current state and current input, rather than just
the current state.
5.6
Design Entry
5.6.1
Start a new project and code a state machine
1. Start a new project, like in previous sections, with a new Verilog source file
2. Using references such as the LED State Machine on the lab webpage, the textbook, or other online resources,
write the Moore state machine described by the state machine diagram in figure 5.2.
The reference design is discussed in Section 4 and can be very helpful for seeing how the code is actually
applied.
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5.6.2
Add a clock source
The MachXO2 has a built in oscillator with user-definable clock speed. For this lab we want the slowest speed,
2.08 MHz. The objective for this Section is to change state every half second so this frequency will have to be reduced
using a counter variable as a clock divider.
For a full table of the selectable frequencies and much more information about the
MachXO2’s advanced clock features, refer to the ”MachXO2 sysCLOCK PLL Design and
Usage Guide” on latticesemi.com
1. Refer to the LED StateMachine 272.zip project from the lab website.
2. Copy the OSCH instantiation template and paste it into the section5 Verilog module.
5.6.3
Add a clock counter
Because the internal oscillator cycles over 2 million times per second, changing states will happen too fast to
observe. The target time for reversing and spinning is 0.5 seconds each. In order to observe the state changes, the
effective frequency must be lowered by adding a clock counter. A counter is used in a loop to trigger events after a
certain number of cycles. In this lab the counter variable triggers an event that advances the finite state machine to
the next state.
1. In the LED StateMachine 272.zip project, one of the input files contains a functional clock counter
2. Add this file as an input file by selecting File, Add, Existing File, then navigating to the correct .v file
3. The module is configured for another project, so it must be modified. Read the comments and figure out which
value the counter should reach and how many bits the count register should be for a 0.5 second period
4. Instantiate the clock counter module into the top module
5.7
Design Simulation
Since the state machine is making the Tekbot reverse and spin for half a second each, the simulation will need
to be run for a longer amount of time to see the states change. This is done by selecting ’Run Until...’ from the
’Simulation’ dropdown and choosing a time for the simulation to run for. After the simulation has finished, ’Zoom to Fit’
from the simulation toolbar will fit the waveform to the screen.
5.8
Assign Pins
5.9
Program Hardware
1. Program the MachXO2.
2. Wire the Tekbot and FPGA as depicted in block diagram made earlier.
In Section 4 the left and right direction pins on the analog control board were used as inputs. In this project,
the buttons will act like swtiches because the timing will be handled by your digital state machine. Use the signal
pins coming from the left and right bumpers instead of the direction pins on the analog control board.
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The bumper circuit is no longer powered from the analog control board but by using the
MachXO2’s PULLMODE setting the bumpers can be powered from the MachXO2. Dont
forget to connect the ground pins on the bumpers or the circuit will be left open.
TA Signature:
5.10
Study Questions
2. Explain two advantages of using a digital equivalent of the analog control board.
3. Explain two disadvantages of using a digital equivalent of the analog control board.
5.11
Make a state machine that doesn’t use the same timing for every action. Make it back up for half a second and turn
for a quarter second. There are many ways to implement this, so think of several options. For full points, implement
this on a Tekbot, print out the Verilog source, and explain the method you used.
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Section 6
Final Design Project
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SECTION 6. FINAL DESIGN PROJECT
Pre-Lab
1. Draw out a state machine that will cycle through displaying different digits on the multiple digit seven segment
display. How quickly should that state machine cycle through the digits so that the digits don’t appear to blink?
Research persistence of vision if you need more information.
2. Read what the final project will create and choose an analog voltage to measure with the ADC. Here are some
suggestions:
The voltage across the batteries to estimate the remaining battery charge within the TekBot.
A voltage in the TekBot motor controller to estimate how hard the motors are working.
3. The final project will use an Analog to Digital Converter (ADC) in order to allow the measurement of voltages by
the FPGA. The ADC used in this lab will not function correctly without the proper control signals. A module has
been provided on the Tekbots webpage that generates the control signals for WR-RD Stand-Alone Mode. Using
this module or the ADC0820 datasheet, draw two periods of the control signals for WR-RD Stand-Alone Mode
on the provided axis. Note that the signals are inverted. Label the time axis in microseconds (us) wherever a
change occurs.
Figure 6.1: Prelab Question 3 Graphs
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6.1
Section Overview
It is important to be able to actually use the concepts learned in this course to create real systems and designs.
This lab presents a design problem that will use concepts from previous labs. In order to interface with the analog
world, embedded systems use Analog to Digital Converters (ADCs). An ADC takes an analog voltage as input and
outputs a digital value. In this lab, the digital value will be converted to seven segment output on multiple digits.
6.2
Objective
Build a system that will take an analog voltage as an input and output 0 - 255 on the seven segment board. Refer
to Figure 6.2 for a block diagram of this project.
Figure 6.2: Incomplete Block Diagram for Final Project.
This design is easier to visualize if split into a series of less difficult pieces.
1. Use a potentiometer to generate an analog voltage for the ADC. Connect the ADC to the FPGA and display the
ADC’s binary output on the MachXO2’s onboard LEDs.
2. Design and test a module that will display all four digits of the seven segment display
3. Interface the two modules so that the raw output from the ADC is displayed on the seven segment display
4. Decode the raw ADC data into an analog voltage value
5. Attach device to the Tekbot to display the voltage at a chosen point
6.3
Materials
2. MachXO2 Breakout board
3. A working TekBot with the motor control board
4. The ECE 271 textbook, Digital Design and Computer Architecture by Drs. David and Sarah Harris
6.4
Procedure
There are 6 steps to digital logic design
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Figure 6.3: Use this process for designing the final project.
6.5
ADC Introduction
Analog to Digital Converters, or ADCs, are the electronic bridge between the analog and digital worlds. The
implementations are often very different, but the functionality remains the same: the ADC will input an analog voltage
and represent the value with a certain number of bits. In our application, the ADC outputs 8 bits and operates at 5
volts. In order to maximize the operable range, VREF+ should be connected to 5V and VREF- should be connected
to ground; this can be done using the provided jumpers. The control signals, WR, RD, and CS, are generated by a
provided module and are described in detail in the ADC’s datasheet.
Figure 6.4: ADC Visual Representation
Figure 6.4 shows a visual representation and the mathematical relationship between Vin and Dout, as well as
some examples of typical voltages.
6.6
Checkpoint 1: Interface the ADC with the FPGA
As discovered in the prelab, the ADC operates based on serial control signals. A Verilog module that generates
the required signals can be found on the lab webpage.
1. Write a Verilog module that outputs the control signals to the ADC and displays the output data on the LEDs.
2. Simulate the new project
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6.7. CHECKPOINT 2: DISPLAY 4 DIGITS ON THE 7-SEGMENT DISPLAY
3. If everything simulated correctly, program the FPGA
4. Assemble ADC board by soldering male header into all open holes.
5. Configure ADC hardware by attaching a jumper across WR-RD, a jumper from 5V to VREF+, and a jumper from
GND to VREF6. If it hasn’t been assembled already, attach header to the Buck-Boost board
7. Wire the three boards together and test the system by varying the voltage at VIN of the ADC with a potentiometer
The ADC operates at 5V, so use the Buck-Boost board to raise the voltage from the FPGA
from 3.3V to 5V and power the ADC
6.7
Checkpoint 2: Display 4 Digits on the 7-Segment Display
Figure 6.5: Display Board Wiring Diagram and Digit Select Table.
Tips:
1. Refer to Figure 6.5 for usage of the Seven Segment Display board (4digit.0).
2. Refer to HDL Example 4.24 on the Verilog reference sheet, available at Tekbots.com, for an example on how to
write a decoder in Verilog for a seven segment display.
3. A state machine should be used to cycle between the four digits (four states). Use the 7-Seg SEL inputs to
choose which digit is being displayed.
4. A multiplexer works well for switching the value displayed on each digit.
5. The frequency at which the digits are cycles will determine the brightness of the LEDs, refer to the Pre-Lab.
6.8
Checkpoint 3: Interface the ADC with the 7-Segment Display
Display the raw output from the ADC on the 7-Segment Display.
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Tips:
1. Use math to extract the individual digit that is needed from the 0-255 range. For example, to grab the hundreds
digit:
hundreds = input_8_bit / 100
Verilog truncates any remainder and leaves the whole number result of the division.
2. The modulus operator (%) will be useful for obtaining individual numbers.
3. After extracting an individual 0-9, the number can be sent to a decoder for seven segment output.
4. If any modules have a bus that needs to be separated into wires for each bit or several wires that need to be
combined into a bus for another input, refer to section 4.2.9, Bit Swizzling, in the textbook.
6.9
Checkpoint 4: Decode the Raw Output from the ADC and Display
Display an analog voltage range on the seven segment board, for example: 3.456 Volts. This effectively creates a
voltmeter.
6.9.1
Tips:
1. Consider an input from 0 to 5V that corresponds to an output from 0 to 255, what conversion is necessary to get
the voltage?
2. A decimal point will have to be added. There is one decimal point per digit, operated with an eighth pin. During
which states will it be on?
3. The digit isolation developed for checkpoint 3 should be done after the number conversion
6.10
Checkpoint 5: Combine Voltmeter with the Tekbot
Select an analog voltage to digitize. Figure 6.6 shows a portion of the motor controller board used in ECE 112
and ECE 199. The voltage across R12 indicates the amount of current going through the motor connected to J3.
Connecting the ADC to test pad T12 would display the current being used by the motor. This is one example of
something meaningful. Use this example analog voltage, another analog voltage on the TekBot, or an analog voltage
approved by the TA.
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6.11. STUDY QUESTIONS
Figure 6.6: Excerpt of the TekBot Motor Controller Board.
TA Signature:
(A meaningful analog voltage is digitized and displayed on the seven segment display board)
6.11
Study Questions
2. What was the toughest aspect of ECE 272? What should be changed or added to the ECE 272 manual to make
this course better?
3. What would you like to explore further about Lattice Diamond or Digital Logic Design?
4. What section of ECE 272 did you dislike the most? Why?
5. What was your favorite section of ECE 272? Why?
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ECE 272 Lab Manual Fall 2014

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