ATB352 Ultra-Low Power Configurable Piezo Interface Datasheet ATB352 Introduction

ATB352
ATB352 Ultra-Low Power Configurable Piezo Interface Datasheet
Revision 1.0
October 2014
Introduction
Main Features
The ATB352 is a user interface controller based on SEP
technology that enables seamless touch buttons on any
surface. It allows the user to configure a combination of
buttons and LEDs as well as selecting the
communication interface. The ultra-low energy
consumption offered by ATB352 makes it suitable for
applications with tight energy requirements such as
those which are battery operated.
SEP is a new and exciting user interface technology that
has significant advantages over both traditional
mechanical buttons and other surface touch
technologies such as capacitive sensing. It enables
designers to use entirely new materials such as metal
and wood, to create beautiful and seamless user
interfaces.
In addition, SEP offers lower manufacturing costs due
to the reduction in manufacturing process, reduction in
material wastage and the elimination of additional
panels needed for a conventional user interface. The
inherent robustness of SEP and its ability to operate in
harsh environments combined with the field replaceable
nature of the SEP module, also reduces aftermarket
maintenance and inventory costs.
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ATB352
Configurable channels: Piezo input (channels 1-5),
LED output (all channels) or Buzzer output
(channel 9)
Press and hold up to 5 seconds
Selectable interface mode
2
- I C up to 100 kHz (4 possible addresses)
- SPI up to 50 kHz (mode 0)
- Digital Direct Outputs (DDO)
2
Maximum of 15 channels available (in I C mode)
DDO mode configurability through external
EEPROM with full support from Aito UX Design
Studio
Ultra-low power: less than
idle state
Configurable press sensitivity and detection area
Supply Voltage 1.8V to 3.6V
Configurable feedback patterns
- Up to 31 individual configurable output patterns
applicable to LEDs and audio
Configurable input-output feedback link
- Feedback pattern routing using links between
input events and output channels for full UI
design flexibility
- Up to 11 individual input-output links supported
External interrupt line for host notification
- Open drain interrupt output
Support for 10mm piezo discs
Wide operating temperature range of -40 to
+85°C
RoHS compliant QFN32 package (5x5 mm)
Figure 1. The AB352 is an interface between an analog piezo panel and a digital host
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ATB352
ATB352 Pinout
Table 1. Pin descriptions for ATB352
Pin
I2C Mode
(1)
Name
Function
1
CH1
2
CH2
3
CH3
4
CH4
5
CH5
6
7
8
9
CH6
CH7
NC
CH8
10
CH9
11
12
13
CH10
CH11
CH12
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
LED output
LED output
Not Connected
LED output
LED output /
Buzzer
LED output
LED output
LED output
14
CH13
LED output
15
CONF1
16
CONF2
17
CONF3
18
CH14
19
SPI Mode
(2)
Type
Name
Function
Type
Name
Function
Type
I/OD
CH1
I/OD
CH2
I/OD
CH3
I/OD
CH4
SPI Clock
I
CH5
CH6
CH7
NC
CH8
LED output
LED output
Not Connected
LED output
OD
OD
X
OD
CH6
CH7
NC
CH8
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
LED output
LED output
Not Connected
LED output
OD/PP
CH9
LED output / Buzzer
OD/PP
CH9
LED output / Buzzer
OD/PP
OD
OD
OD
CH10
CH11
CH12
LED output
LED output
LED output
OD
OD
OD
CH10
CH11
CH12
LED output
LED output
LED output
OD
OD
OD
OD
CH13
LED output
OD
DOUT1
Direct Output for CH1
PP
I
CONF1
Mode Configuration 1
I
CONF1
Mode Configuration 1
I
I
CONF2
Mode Configuration 2
I
CONF2
I
CS
SPI Chip Select
I
DOUT2
LED output
OD
CH14
LED output
OD
DOUT3
CH15
LED output
OD
CH15
LED output
OD
DOUT4
20
SLEEP
Analog Switch
Control
PP
SLEEP
PP
SLEEP
21
SCL
I2C Clock
OD
MISO
PP
SCL
I2C Clock
OD
22
SDA
I2C Data
OD
MOSI
I
SDA
I2C Data
OD
23
24
RST
NC
Reset pin
Not Connected
I
X
RST
NC
Reset pin
Not Connected
I
X
RST
NC
I
X
25
INT
Interrupt pin
OD
INT
Interrupt pin
OD
DOUT5
Reset pin
Not Connected
Direct Output for
CH5
External wake up
signal
Ground
Ground
Power Supply
Power Supply
Voltage Reference
Not Connected
Mode
Configuration 1
Mode
Configuration 2
Mode
Configuration 3
I/OD
CH1
I/OD
CH2
I/OD
CH3
I/OD
CH4
I/OD
SCK
OD
OD
X
OD
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
Piezo input / LED
output
DDO Mode
Analog Switch
Control
SPI Master In Slave
Out
SPI Master Out Slave
In
External wake up
External wake up
I
WAKEUP
I
signal
signal
27
GND
Ground
PW
GND
Ground
PW
28
GND
Ground
PW
GND
Ground
PW
29
VDD
Power Supply
PW
VDD
Power Supply
PW
30
VDD
Power Supply
PW
VDD
Power Supply
PW
31
VREF
Voltage Reference
I
VREF
Voltage Reference
I
32
NC
Not Connected
X
NC
Not Connected
X
(1)
Channel pins naming: Piezo input PZx / LED output LEDx / Buzzer BUZZER (x - channel number)
(2)
Type: I = Input / PW = Power pin / PP = Push-pull / OD = Open-drain
26
2
WAKEUP
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WAKEUP
GND
GND
VDD
VDD
VREF
NC
Mode Configuration
2
Direct Output for
CH2
Direct Output for
CH3
Direct Output for
CH4
Analog Switch
Control
I/OD
I/OD
I/OD
I/OD
I/OD
OD
OD
X
OD
I
PP
PP
PP
PP
PP
I
PW
PW
PW
PW
I
X
Revision 1.0
ATB352
Operation States
There are two operation states in ATB352, active and
active idle. The base state is active idle and it is entered
when there is no input or output activity such as a key
press or feedback generation. In this state the energy
consumption is minimal and the selected
communication interface remains operational. When
there is activity in any of the piezo keys or the host
commands direct pattern playing the ATB352 goes to
active state until all input and output activity has
stopped.
Interface Configuration
The interface mode is configured by hardware using
pins CONF1 and CONF2. They should be connected to
either Ground or Vdd to give them low or high logic
level respectively. Additionally if the ATB352 is
2
configured for I C mode CONF3 pin allows selecting up
2
to 4 different I C slave addresses. The modes are
selected as shown in Table 2.
(1)
SPI Mode
In SPI mode the ATB352 is configured as a 4-wire SPI
slave device and supports a clock frequency up to 50
kHz. To communicate with ATB352 the master device
should operate in SPI mode 0 (clock base value is 0 and
Channel 5 is reserved to be used for SCK signal and pins
17, 21 and 22 are used for CS, MISO and MOSI
respectively. Figure 2 and Table 3 show the timing
characteristics to be observed by the master device. The
master must give a minimum of 400µs between SPI
transactions.
The CS pin cannot be connected to ground and must be
used by the master device as show in Figure 2.
Table 3. SPI characteristics
Table 2. ATB352 Interface Configuration
CONF2
High
High
Low
Low
High
Low
2
The interface complies with a Standard-mode I C device
2
C-bus specification and user
9 October 2012.
2
The ATB352 supports 3 interface modes: I C, SPI and
DDO (Digital Direct Outputs). The interface mode
selection impacts the pinout as shown in Table 1.
CONF1
High
High
High
High
Low
Low
All channels are available (CH1 CH15) and pins 21 and
22 are used for SCL and SDA signals respectively.
CONF3
High
Low
High
Low
(1)
X
(2)
X
Interface Mode
2
I C (0x58)
2
I C (0x59)
2
I C (0x5A)
2
I C (0x5B)
SPI
DDO
Used as SPI CS
(2)
Used as DOUT1
Symbol
T1
T2
T3
T4
T5
I2C Mode
T6
2
Parameter type
CS falling to MISO valid
CS falling to first SCK
edge
SCK shift edge to MISO
change
MOSI valid to SCK
sample edge
Last SCK edge to CS
rising
CS rising to MISO HighZ
Min
Max
29
30
Units
µs
µs
75
ns
15
ns
10
ns
50
ns
2
In I C mode the ATB352 is configured as an I C slave
device and supports a clock frequency up to 100 kHz
(Standard-mode).
CS
CLK
MOSI
MISO
T1
T4
T2
T5
T6
T3
Figure 2. SPI timing diagram
3
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Revision 1.0
ATB352
Direct Low
DDO Mode
In DDO mode the key press and release events are
signaled through the digital outputs pins (DOUTx) which
are directly mapped to the same numbered channel
with support for piezo input (1-5). In this mode channels
13 to 15 are not available as they are reserved to be
used as digital outputs.
The register data in this mode must be stored in an
2
external EEPROM with I C interface. The EEPROM must
be dedicated to the ATB352 and cannot be in a shared
2
I C bus with other devices to avoid bus conflicts. The
2
ATB352 starts-up as an I C master device and attempts
to communicate with the external EEPROM using the
standard address range 0x50 (1010000b) to 0x57
(1010111b). When an address is acknowledged the chip
will read the data in the EEPROM and place it in its own
registers.
In case the EEPROM data is found to be incorrect (e.g.
missing identification bytes or wrong checksum) the
ATB352 will go to active idle state but the SLEEP pin will
be active high instead of active low as it occurs in
regular active idle state. This provides a way to
troubleshoot whether the EEPROM data is corrupted or
it is simply misconfiguring the chip
If no EEPROM is found the ATB352 will reconfigure as
2
an I C slave with address 0x60 and can be accessed by
any master device to write/read register data. In this
mode the chip is always in active state and the event
buffer is not populated, its registers will always read 0.
In Direct Low mode the output is high if the key is idle
and low while the key is being pressed as depicted in
Figure 3. Key presses and releases generate the output
state transitions.
Key press
Idle
Vdd
Idle
Figure 3. Direct Low Output Signal
Direct High
The signal behavior is the same as in Direct Low mode
but with reversed polarity.
Key press
Key release
Pressed
Vdd
Idle
GND
Idle
DOUTx
Figure 4. Direct High Output Signal
Pulse
In this mode the output is low and goes high for 30ms
with each key press as depicted in Figure 5. Key
releases have no influence in the output state.
Pulse Mode
Key press
The output signal can behave in 4 different ways for
more flexibility and easier system integration. The
output mode can be selected through register 1 in page
13 (OUTMODE) using the values show in Table 4.
DOUTx
Pressed
GND
Output Signals
Key press
DOUTx
Vdd
GND
30 ms
30 ms
Figure 5. Pulse Mode Output Signal
Table 4. Output Mode Configuration
OUTMODE
0x00
0x01
0x02
0x03
Key release
Output Mode
Direct Low
Direct High
Pulse
Toggle
Toggle
The output state changes between low and high with
each key press as depicted in Figure 6. The initial state
is low and key releases have no influence in the output
state.
The DOUTx pins are in Hi-Z until OUTMODE register is
written after which they will be configured as push-pull
with output low, except if OUTMODE is selected to be
Direct Low where the pins will be set to output high.
Key press
Key press
Key press
Vdd
DOUTx
GND
Figure 6. Toggle Mode Output Signal
4
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Revision 1.0
ATB352
EEPROM
The ATB352 supports EEPROMs up to 2Mbit in size and
2
with an I C interface capable of operating at 100 kHz. It
is recommended to connect the EEPROM address pins
(A0, A1 and A2) to ground if they are available. The WP
(write protect) input can be connected to either ground
or Vcc
EEPROM Data Format
The data placed in the EEPROM must comply with the
format described in this section and it must start from
the
second byte (address 1). The first two
data bytes are used by ATB352 to identify a valid
EEPROM and must be 0x0A and 0xEE. After the two
identification bytes comes the register data packaged in
the form of page frames. A page frame consists of:
 Header (2 bytes): Page number in the Aito
Enhanced Register Interface and number of
bytes to be written into that page
 Data (N bytes): Data bytes to be placed into
must coincide with
the number of bytes in the header
 Checksum (1 byte): The sum of all the bytes in
the page frame using an unsigned byte
All the data in each frame starts being placed from
register 1 onward so byte padding is required if it is only
desired to write in higher numbered registers but not in
lower numbered ones. The number of page frames is
variable and it depends on the desired chip
configuration. The termination byte 0x80 must be
placed after the last page frame.
EEPROM Data Example
example configuration for
ATB352:
 CH1 and CH2 as Piezo Input
 CH3 and CH4 as LED Output
 Sensitivity value 240, Detection area value 192
and Stiffness 240 for CH1 and CH2
 Press event on CH1 is linked to output CH3
using Pattern 1 and press event on CH2 is
linked to output CH4 using Pattern 2
5
For simplification all the pattern parameters will be 255.
The data would be placed in the ATB352 registers as
described in Table 5. For more detailed information on
the ATB352 registers please refer to the Aito Chip User
Manual.
Table 5. Configuration data in ATB352 registers
Register
1
2
3
4
81h
81h
41h
41h
01h
02h
NOT USED
NOT USED
03h
04h
NOT USED
NOT USED
01h
02h
NOT USED
NOT USED
240
(F0h)
192
(C0h)
240
(F0h)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
240
(F0h)
192
(C0h)
240
(F0h)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
255
(FFh)
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
Page
1 (01h)
Channel Modes
2 (02h)
Input Event
3 (03h)
Output Channel
4 (04h)
Pattern
10 (0Ah)
Sensitivity
11 (0Bh)
Detection area
12 (0Ch)
Stiffness
25 (19h)
Delay
26 (1Ah)
Pulse Count
27 (1Bh)
Pulse Duration
28 (1Ch)
Pulse Interval
29 (1Dh)
Burst Count
30 (1Eh)
Burst Interval
31 (1Fh)
Parameter 1(2)
The register data must be divided into page frames
according with the described format. If we take page 1
as an example the first byte in the page frame is 01h
(page number), second byte 04h (number of bytes to be
written), third to sixth bytes are the register data and
the last byte is the checksum which is equal to 89h for
the example values.
The entire configuration would be placed into the
EEPROM memory as shown in Table 6.
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Revision 1.0
ATB352
Table 6. ATB352 configuration data in EEPROM
EEPROM
byte
0
1
address
2
3
4
5
6
7
0x0000
(XX)
Reserved
0x0A
(Identification)
0xEE
(Identification)
0x01
(Page)
0x04
(Number of
bytes)
0x81
(Data)
0x81
(Data)
0x41
(Data)
0x0008
0x41
(Data)
0x89
(Checksum)
0x02
(Page)
0x02
(Number of
Bytes)
0x01
(Data)
0x02
(Data)
0x07
(Checksum)
0x03
(Page)
0x0010
0x02
(Number of
bytes)
0x03
(Data)
0x04
(Data)
0x0C
(Checksum)
0x04
(Page)
0x02
(Number of
bytes)
0x01
(Data)
0x02
(Data)
0x0020
0x09
(Checksum)
0x0A
(Page)
0x02
(Number of
bytes)
0xF0
(Data)
0xF0
(Data)
0xEC
(Checksum)
0x0B
(Page)
0x02
(Number of
bytes)
0x0028
0xC0
(Data)
0xC0
(Data)
0x8D
(Checksum)
0x0C
(Page)
0x02
(Number of
bytes)
0xF0
(Data)
0xF0
(Data)
0xEE
(Checksum)
0x0030
0x19
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0xFF
(Data)
0x19
(Checksum)
0x1A
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0x0038
0x1A
(Checksum)
0x1B
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0xFF
(Data)
0x1B
(Checksum)
0x1C
(Page)
0x02
(Number of
bytes)
0x0040
0xFF
(Data)
0xFF
(Data)
0x1C
(Checksum)
0x1D
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0xFF
(Data)
0x1D
(Checksum)
0x0048
0x1E
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0xFF
(Data)
0x1E
(Checksum)
0x1F
(Page)
0x02
(Number of
bytes)
0xFF
(Data)
0x0050
0xFF
(Data)
0x1E
(Checksum)
0x00
(Page)
0x00
(Data)
0x00
(Data)
0x00
(Data)
0x00
(Data)
0x0058
0x00
(Data)
0x08
(Data)
0x0E
(Checksum)
The thicker lines in Table 6 indicate the separation
between page frames for better readability. As
previously described the first byte in address 0x0000 is
0x0001. The first two data bytes are the identification
bytes 0x0A and 0xEE and they are followed by all the
page frames.
6
0x06
(Number of
bytes)
0x80
(Termination
byte)
Please note that the last page frame (starting from
EEPROM address 0x0052) is only for activating the
Configure Channels command in register 6
(COMMANDS) of page 0 and it requires padding bytes
for register 0 to 5 which are read only. After the last
page frame comes the termination byte 0x80.
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Revision 1.0
ATB352
Reference Design
Ultra-low power control
Each of the ATB352 channels should be configured into
its specific mode using the Channel Modes page (01h) in
the Aito Register Interface as referred in the Aito Chip
Reference Manual. All unused channels should be left
unconnected.
All the channels configured as Piezo input need a
dedicated RC filter and a resistor to VREF as shown in
the reference designs. The recommended values for the
1nF, and 1M for the
load resistor. It is recommended to have a 100nF
capacitor between piezo common and chassis ground.
This protects the input circuitry from electrostatic
discharges by forming a low-impedance path to ground.
If chassis ground is not appropriate, the power supply
ground should be used instead. If the environment is
particularly susceptible for ESD, a film type capacitor is
recommended, otherwise a ceramic capacitor is
sufficient. It is also recommended to place a 4.7 µF and
100nF capacitors on VREF line and power supply.
The resistors should have a maximum tolerance of 1%
and the 4.7 µF and 100nF filter capacitors at VREF and
Vdd can be either ceramic or tantalum.
Important Note: In multiple chip applications each Aito
Chip must have its own dedicated VREF circuitry.
The ultra-low power control circuit (US Patent No
8,810,105 Aito B.V) is designed using two widely
available standard components, an analog switch and
analog comparator. The active idle energy consumption
is largely dominated by the analog comparator. Both
components can be freely selected according with the
cost and energy requirements of each application.
Analog Switch
The most critical parameter for this component is the
onthe reference design presented in this document it was
selected SN74LVC1G66 from Texas Instruments which
Analog Comparator
The analog comparator has two important parameters,
maximum input hysteresis voltage (VHYST) and maximum
input offset voltage (VOFFSET). Those two parameters
need to be taken into consideration for dimensioning
the threshold resistor RTH (R15 on the reference designs)
reference designs). The value of RTH is given by the
equation below:
The Aito Chip can drive the buzzer and LEDs directly if
channels are active low, i.e. chip sinks current when
LED is active. BUZZER output is active high. If more
current is needed then the BUZZER and LEDx lines
should be used to control a transistor that
sources/sinks the required current directly from/to
Vdd/Ground instead of Aito Chip.
For the reference design presented in this datasheet it
was selected TS881 from STMicroelectronics which has
a typical current consumption of 210nA. The VHYST and
VOFFSET for this part are 4.2mV and 12mV respectively
(VHYST and VOFFSET symbols in TS881 datasheet). If those
values are taken into the given equation and assuming a
VDD of 3.3V the result is:
.
It is recommended to use a resistor value as close as
possible to the lower limit, for the case of these
reference designs a value of 51k was selected.
7
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Revision 1.0
ATB352
I2C Mode Reference Design
2
Figure 7 shows ATB352 configured in I C mode (address 0x58 CONF1, CONF2 and CONF3 connected to Vdd) with 4
2
piezos, 1 LEDs, 1 buzzer and 9 unused channels. Please note that in I C mode the SDA and SCL pins are open-drain as well
2
as the INT pin and need to have pull-up resistors. For the INT pin a 4
he I C lines
pull2
length and capacitance of the lines and bus speed. For more information on sizing of I C pull-up resistors and general bus
2
design please refer to the I C specification. The bill of materials for this design is shown in Table 7.
Vdd
ATB352
30
C1
C2
100n 4.7µ
Vdd
R4
4.7k
27
28
To Host
(optional)
R2
R3
4.7k
4.7k
4.7k
2
3
4
GND
GND
21
22
R10
1M
Piezo
R11
1M
C7 1n
31
INT
SCL
SDA
10
CH9: BUZZER
R12
1M
Piezo Common
Dome
C8 100n
R13
10k
C9
4.7µ
C10
100n
Vdd
R18
1k
Piezo Buzzer
26
R19
5
LED1
R14
3.3M
Vdd
1k
TS881
+
Vdd
CH6: NOT USED
WAKEUP
19
CH15: NOT USED
15
CONF1
16
CONF2
17
CONF3 CH5: LED5
Piezo
Vdd
SN74LVC1G66
OUT/IN VDD
CTL
IN/OUT GND
6
Vdd
Piezo
Piezo
20
SLEEP
25
560k R6
560k R7
560k R8
C4 1n
560k
R9
C5 1n
1M
C6 1n
RST
VREF
To Host
R1
23
C3
1n
R5
1
CH1: PZ1
CH2: PZ2
CH3: PZ3
CH4: PZ4
VDD
VDD
29
-
R15
51k
R17
2.2M
C11
R16
3.3M
1n
Figure 7. ATB352 I2C mode example application
SPI Mode Reference Design
Figure 8 shows ATB352 configured in SPI mode (CONF1 connected to ground and CONF2 to Vdd) with 4 piezos, 1 LEDs, 1
buzzer and 8 unused channels. The interrupt line must have a 4.7k pull-up resistor. The bill of materials for this design is
shown in Table 9.
Vdd
ATB352
30
29
C1
C2
100n 4.7µ
Vdd
R1
4.7k
27
28
To Host
(optional)
VDD
VDD
23
C3
1n
CH1: PZ1
CH2: PZ2
CH3: PZ3
CH4: PZ4
R5
1
2
3
4
GND
GND
560k R6
560k R7
560k R8
C4 1n
560k
R9
C5 1n
1M
C6 1n
SLEEP
VREF
To Host
17
22
21
5
INT
CS
MOSI
MISO
SCK CH9: BUZZER
31
SN74LVC1G66
OUT/IN VDD
CTL
IN/OUT GND
10
Vdd
CONF2
CH6: LED6
Piezo Common
Dome
C8 100n
Vdd
R13
10k
C9
4.7µ
C10
100n
Vdd
Piezo Buzzer
R4
5
LED1
1k
R14
3.3M
Vdd
TS881
+
Vdd
16
26
Piezo
R12
1M
R3
1k
6
CH7: NOT USED
WAKEUP
19
CH15: NOT USED
15
CONF1
Piezo
R11
1M
20
4.7k
25
R10
1M
C7 1n
RST
R2
Piezo
Piezo
C11
R17
2.2M
R15
51k
R16
3.3M
1n
Figure 8. ATB352 SPI mode example application
8
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Revision 1.0
ATB352
DDO Mode Reference Design
Figure 9 shows ATB352 configured in DDO mode (CONF1 and CONF2 connected to ground) with 4 piezos, 1 LEDs, 1
buzzer and 6 unused channels. The EEPROM should be as close as possible to the chip. The bill of materials for this
design is shown in Table 11.
Vdd
ATB352
30
29
C1
R1
C2
100n 4.7µ
4.7k
27
28
Vdd
23
Vdd
C3
1n
EEPROM
WP
VDD
A2
SCL
A1
SDA
A0
GND
R2
R3
4.7k
4.7k
CH1: PZ1
CH2: PZ2
CH3: PZ3
CH4: PZ4
22
15
14
17
18
25
3
4
560k R6
560k R7
560k R8
C4 1n
560k
R9
C5 1n
1M
C6 1n
Piezo
Piezo
R10
1M
RST
Piezo
R11
1M
20
31
SN74LVC1G66
OUT/IN VDD
CTL
IN/OUT GND
SCL
SDA
CONF1
CONF2
CH9: BUZZER 10
DOUT1
DOUT2
26
DOUT3 WAKEUP 6
CH6: NOT USED
DOUT4
CH12: NOT USED 13
DOUT5 CH5: LED5 5
Piezo Common
Dome
C8 100n
R13
10k
C9
4.7µ
C10
100n
Vdd
R4
1k
Piezo
R12
1M
Vdd
Piezo Buzzer
R18
LED1
1k
R14
3.3M
Vdd
TS881
+
Vdd
19
2
C7 1n
VREF
21
R5
1
GND
GND
SLEEP
16
To Host
VDD
VDD
C11
R17
2.2M
R15
51k
R16
3.3M
1n
Figure 9. ATB352 DDO mode example application
9
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Revision 1.0
ATB352
Bill of Materials for Reference Designs
I2C Mode Example Application
Table 7. Full BOM
Qty
1
1
1
4
1
1
1
4
1
4
4
2
2
1
1
3
6
2
Table 8. BOM per group
Reference
Description
Value
ATB352
TS881
SN74LVC1G66
Piezo1, Piezo2, Piezo3, Piezo4
Dome
Buzzer
LED1
R1, R2, R3, R4
R13
R5, R6, R7, R8
R9, R10, R11, R12
R18, R19
R14, R16
R17
R15
C1, C8, C10
C3, C4, C5, C6, C7, C11
C2, C9
Aito Chip
Analog Comparator
Analog Switch
Piezo Disk
6x6 mm Metal mode
Piezo Buzzer
LED
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
4.7k
10k
560k
1M
1k
3.3M
2.2M
51k
100n
1n
4.7µ
Group
Aito
Chip
Piezo
key
Buzzer
LED
Qty
1
1
4
1
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
Part
Value
ATB352
Dome
Resistor
Resistor
Resistor
Resistor
Resistor
Analog Comparator
Analog Switch
Capacitor
Capacitor
Capacitor
Piezo Disk
Resistor
Resistor
Capacitor
Buzzer
Resistor
LED
Resistor
4.7k
10k
3.3M
2.2M
51k
100n
4.7µ
1n
1M
560k
1n
1k
1k
SPI Mode Example Application
Table 9. Full BOM
Qty
1
1
1
4
1
1
1
2
1
4
4
2
2
1
1
3
6
2
Table 10. BOM per group
Reference
Description
Value
ATB352
TS881
SN74LVC1G66
Piezo1, Piezo2, Piezo3, Piezo4
Dome
Buzzer
LED1
R1, R2
R13
R5, R6, R7, R8
R9, R10, R11, R12
R3, R4
R14, R16
R17
R15
C1, C8, C10
C3, C4, C5, C6, C7, C11
C2, C9
Aito Chip
Analog Comparator
Analog Switch
Piezo Disk
6x6 mm Metal mode
Piezo Buzzer
LED
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
4.7k
10k
560k
1M
1k
3.3M
2.2M
51k
100n
1n
4.7µ
Group
Aito
Chip
Piezo
key
Buzzer
LED
10
www.aitochip.com
Qty
1
1
2
1
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
Part
Value
ATB352
Dome
Resistor
Resistor
Resistor
Resistor
Resistor
Analog Comparator
Analog Switch
Capacitor
Capacitor
Capacitor
Piezo Disk
Resistor
Resistor
Capacitor
Buzzer
Resistor
LED
Resistor
4.7k
10k
3.3M
2.2M
51k
100n
4.7µ
1n
1M
560k
1n
1k
1k
Revision 1.0
ATB352
DDO Mode Example Application
Table 11. Full BOM
Qty
1
1
1
1
4
1
1
1
1
3
4
4
2
2
1
1
3
6
2
11
Table 12. BOM per group
Reference
Description
ATB352
EEPROM
TS881
SN74LVC1G66
Piezo1, Piezo2, Piezo3, Piezo4
Dome
Buzzer
LED1
R1, R2, R3
R13
R5, R6, R7, R8
R9, R10, R11, R12
R4, R18
R14, R16
R17
R15
C1, C8, C10
C3, C4, C5, C6, C7, C11
C2, C9
Aito Chip
2
I C EEPROM
Analog Comparator
Analog Switch
Piezo Disk
6x6 mm Metal mode
Piezo Buzzer
LED
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
Value
Group
Aito
Chip
4.7k
10k
560k
1M
1k
3.3M
2.2M
51k
100n
1n
4.7µ
www.aitochip.com
Piezo
key
Buzzer
LED
Qty
1
1
3
1
2
1
1
1
1
3
2
2
1
1
1
1
1
1
1
1
Part
Value
ATB352
Dome
Resistor
Resistor
Resistor
Resistor
Resistor
Analog Comparator
Analog Switch
Capacitor
Capacitor
Capacitor
Piezo Disk
Resistor
Resistor
Capacitor
Buzzer
Resistor
LED
Resistor
4.7k
10k
3.3M
2.2M
51k
100n
4.7µ
1n
1M
560k
1n
1k
1k
Revision 1.0
ATB352
Host Interface
Input Events
The ATB352 communicates with the host system using
2
I C or SPI buses. An open drain active-low interrupt line
( INT ) is provided to notify the host system of new
events. The event buffer can contain at most 7 events.
Table 14 lists the registers existing in the ATB352 which
are a sub-set of the Enhanced Aito Register Interface, a
standard register interface used in several Aito products
to create a common framework that is easily
recognizable by developers using more than one Aito
Chip product. Full register description as well as
functional details of ATB352 can be found in the Aito
Chip User Manual.
Recommended Operation
The flowchart in Figure 10 shows the typical actions
that the host should take to operate the ATB352.
Reset (Power-on,
External, Software)
Interrupt line pulled low
Read EVENTTYP E and
EVEN TP ARAM
Interru pt line releas ed
The input events available in ATB352 are numbered
from 1 to 12 and described in Table 13.
Table 13. ATB352 Input Events
Event number
1 to 5
6 to 10
Description
Press event on channel 1 to 5
Release event on channel 1 to 5
As an example, if the intention is to link a release event
of button at channel 5 to an output action, then event
number 10 should be used as input event.
Reset Events
The ATB352 supports all the reset events as described
in the Aito Chip User Manual.
Output Mode Specific Parameter
Page 1Fh contains the registers that define the feedback
pattern Parameter 1. This parameter affects the pattern
behavior depending on output channel mode it is linked
to:
 Buzzer output: it sets the audio output
frequency. The output frequency will be equal
to the value of Parameter 1 times 16 if the

Write register pages:
- 01h: Chan nel modes
- 02h: Inpu t event
- 03h: Outpu t ch an nel
- 04h: Pattern
- 0Ah: Sensitivity
- 0Bh: Detection area
- 0Ch: Stiffness
- 19h – 1Fh: Delay – Parameter 1
frequency will always be 256 Hz.
LED output: It turns the LED ON if the value of
less than 128 the LED will be turned off.
Write 0x08 to
COMMANDS in page 0
(Con figure Channels)
Interru pt line pulled low
Read EVENTTYP E and
EVEN TP ARAM
Poll Interrup t line or
wait fo r falling edge
interrup t
No
Interru pt line
low?
Yes
Figure 10. Typical operation flowchart
12
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Revision 1.0
ATB352
Table 14. ATB352 registers
Register
0
1
2
3
4
5
6
7
8
CHIP
FAMILY
CHIP
TYPE
CHIP
REV
EVENT
TYPE
EVENT
PARAM
COMMANDS
PLAY
PATTERN
STOP
PATTERN
Channel 1
Channel
2
Channel
3
Channel
4
Channel
5
Channel 6
Channel 7
Channel 8
Link 1
Link 2
Link 3
Link 4
Link 5
Link 6
Link 7
Link 8
Link 1
Link 2
Link 3
Link 4
Link 5
Link 6
Link 7
Link 8
Link 1
Link 2
Link 3
Link 4
Link 5
Link 6
Link 7
Link 8
Channel 1
Channel
2
Channel
3
Channel
4
Channel
5
(1)
(1)
(1)
Channel 1
Channel
2
Channel
3
Channel
4
Channel
5
(1)
(1)
(1)
Channel 1
Channel
2
Channel
3
Channel
4
Channel
5
(1)
(1)
(1)
OUTMODE
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
Pattern 6
Pattern 7
Pattern 8
Page
0 (00h)
Generic
1 (01h)
Channel
Modes
2 (02h)
Input Event
3 (03h)
Output
Channel
4 (04h)
Pattern
10 (0Ah)
Sensitivity
11 (0Bh)
Detection
area
12 (0Ch)
Stiffness
13 (0Dh)
Output
Mode
25 (19h)
Delay
26 (1Ah)
Pulse Count
27 (1Bh)
Pulse
Duration
28 (1Ch)
Pulse
Interval
29 (1Dh)
Burst Count
Page
Length
(8)
Page
Length
(18)
Page
Length
(31)
Page
Length
(31)
Page
Length
(31)
Page
Length
(5)
Page
Length
(5)
Page
Length
(5)
Page
Length
(1)
Page
Length
(11)
Page
Length
(11)
Page
Length
(11)
Page
Length
(11)
Page
Length
(11)
Page
Length
(11)
Page
Length
(11)
30 (1Eh)
Pattern 1
Pattern 2 Pattern 3 Pattern 4 Pattern 5
Pattern 6
Pattern 7
Pattern 8
Burst
Interval
31 (1Fh)
Pattern 1
Pattern 2 Pattern 3 Pattern 4 Pattern 5
Pattern 6
Pattern 7
Pattern 8
Parameter
1(2)
(1)
Not existing
(2)
As described on page 11, this parameter can be audio frequency or LED On/Off state depending on the output channel mode.
13
www.aitochip.com
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
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.
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.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
27
(1)
(1)
Link
31
Link
31
Link
31
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Revision 1.0
ATB352
Electrical Characteristics
Table 15. Absolute maximum ratings for ATB352
Parameter
Storage temperature
Voltage on any I/O pin with respect to GND
Maximum current through any I/O pin
Maximum total current through all I/O pins
Voltage on Vdd with respect to GND
Conditions
Min
-55
-0.3
Max
150
Vdd + 0.3
±6
±48
4.1
-0.3
Units
°C
V
mA
mA
V
functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability and lifetime. For good heat dissipation and current drive it is
recommended to solder the central ground pad.
Table 16. DC characteristics
Parameter
Supply voltage
Supply current in active state
Conditions
(1)
Supply current in active idle state
(1)
(1)
Supply current for reference designs in active idle state
(excluding EEPROM)
Operating temperature
Power-on reset threshold
Input voltage on any pin
Output high voltage
Output low voltage
Vdd = 1.8V
Vdd = 3.3V
Vdd = 1.8V
Vdd = 3.3V
Vdd = 1.8V
Vdd = 3.3V
Min
1.8
Typ
Max
3.6
0.7
1.4
0.1
0.1
mA
0.5
0.5
0.6
0.9
-40
+85
1.75
Vdd
I(OHmax) = -6 mA
I(OLmax) = 6 mA
Units
V
Vdd 0.3
0.3
°C
V
V
V
V
This value refers only to the ATB352 and does not include the current consumption of surrounding components such as pull-up resistors or buzzer.
14
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Revision 1.0
ATB352
Revision History
Revision 1.0
- Updated maximum EEPROM size support to 2Mbit.
- Removed External components important parameters table.
- Added ultra-low power control section.
Revision 0.1
- Preliminary version
15
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Revision 1.0
ATB352
Disclaimer
All information supplied by or on behalf of Aito BV in relation to its products and services, whether in the nature of
data, recommendations or otherwise, is believed to be reliable, but Aito BV assumes no liability whatsoever in
respect of the application, processing or use made of such information, products or services, or any consequence
thereof.
16
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Revision 1.0