RENESAS TECHNICAL UPDATE TE TN-RX*-A111A/E Date: Nov. 17, 2014

Transcription

RENESAS TECHNICAL UPDATE TN-RX*-A111A/E
Date: Nov. 17, 2014
RENESAS TECHNICAL UPDATE
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
Renesas Electronics Corporation
Product
Category
Title
MPU & MCU
Document
No.
Corrections to User’s Manual regarding the
FASR.EXS bit for the Flash Memory in the RX111
Group
Information
Technical Notification
Category
Lot No.
Applicable
RX111 Group
Product
All
Reference
Document
TN-RX*-A111A/E
Rev. 1.00
RX111 Group User's Manual:
Hardware Rev.1.10
(R01UH0365EJ0109)
Specification Changes to Improve
the Products in the RX111 Group
(TN-RX*-A110A/E)
Corrections to Descriptions for
the Flash Memory in the RX111
Group User’s Manual
(TN-RX*-A109A/E)
This document describes corrections to the description for the FASR.EXS bit in section 35. Flash Memory of RX111 Group
User's Manual: Hardware Rev.1.10.
• Page 1104 of 1243
Description for the EXS bit of 35.4.8 Flash Area Select Register (FASR) is corrected as follows:
Before correction
Set this bit to 1 when programming the extra area using the FEXCR register.
Set this bit to 0 when not programming the extra area.
After correction
Set this bit to 1 before issuing a software command (unique ID read, start-up area information program, or access
window information program) for the extra area. Set this bit to 0 before issuing a software command (program, block
erase, or blank check) for the user area.
After issuing a software command, do not change the value until changing it for issuing the next software command.
©2014. Renesas Electronics Corporation, All rights reserved.
Page 1 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1125 of 1243
Figure 35.10 in (3) Programming and Erasure Procedures of 35.7.3 Software Command Usage is corrected as follows:
Before correction
Start in ROM P/E mode
Set programming address
in FSARH and FSARL
registers
in FWBH and FWBL
registers
Write 81h to FCR register
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
FSTATR0.ILGLERR bit = 0?
FSTATR0.PRGERR bit = 0?
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
Continue ROM
programming?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in ROM P/E mode
Figure 35.10 ROM Programming Procedure
Page 2 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
FASR.EXS bit = 0
in registers FSARH and FSARL
Set programming data
in registers FWBH and FWBL
FCR register = 81h
FSTATR1.FRDY flag = 1?
No
Yes
FCR register = 00h
No
Yes
FSTATR0.ILGLERR flag = 1 or
FSTATR0.PRGERR flag = 1?
Yes
FRESETR.FRESET bit = 1
No
Continue ROM programming?
Sequencer
initialization
Yes
No
End in ROM P/E mode
Figure 35.10 Procedure to Issue the Program Command for the ROM
Page 3 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1126 of 1243
Before correction
Start in E2 DataFlash
P/E mode
in FSARH and FSARL
registers
Set programming data in
FWBL registers
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
Continue ROM
programming?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in E2 DataFlash
P/E mode
Figure 35.11
E2 DataFlash Programming Procedure
Page 4 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
Start in E2 DataFlash P/E mode
FASR.EXS bit = 0
in registers FSARH/FSARL
in the FWBL register
FCR register = 81h
No
Yes
FCR register = 00h
No
Yes
No
Yes
Continue E2 DataFlash
programming?
Sequenser
initialization
Yes
No
End in E2 DataFlash P/E mode
Figure 35.11
Procedure to Issue the Program Command for the E2 DataFlash
Page 5 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1127 of 1243
Before correction
Set start address of
erasure block in FSARH
and FSARL registers
Set end address of erasure
block in FEARH and
FEARL registers
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
FSTATR0.ERERR bit = 0?
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
Continue ROM erasure?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in ROM
P/E mode
Figure 35.12 ROM Block Erase Procedure
Page 6 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
FASR.EXS bit = 0
Set the beginning address of the erasure
block in registers FSARH and FSARL
Set the last address of the erasure block
in registers FEARH and FEARL
FCR register = 84h
No
Yes
FCR register = 00h
No
Yes
FSTATR0.ERERR flag = 1?
No
Yes
Continue ROM erasure?
Sequencer
initialization
Yes
No
End in ROM P/E mode
Figure 35.12 Procedure to Issue the Block Erase Command for the ROM
Page 7 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1128 of 1243
Before correction
P/E mode
Set start address of
erasure block in FSARH
and FSARL registers
Set end address of erasure
block in FEARH and
FEARL registers
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
FSTATR0.ERERR bit = 0?
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
erasure?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in E2 DataFlash
P/E mode
Figure 35.13 E2 DataFlash Block Erase Procedure
Page 8 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
FASR.EXS bit = 0
Set the beginning address of the erasure
block in registers FSARH and FSARL
Set the last address of the erasure block
FCR register = 84h
No
Yes
FCR register = 00h
No
Yes
FSTATR0.ERERR flag = 1?
Yes
No
Continue E2 DataFlash erasure?
Sequencer
initialization
Yes
No
Figure 35.13 Procedure to Issue the Block Erase Command for the E2 DataFlash
Page 9 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1129 of 1243
Before correction
Set target start address in
FSARH and FSARL
registers
Set target end address in
FSARH and FSARL
registers
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
FSTATR0.BCERR bit = 0?
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
Continue ROM blank
check?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in ROM
P/E mode
Figure 35.14 ROM Blank Check Procedure
Page 10 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
FASR.EXS bit = 0
Set the blank check start address
Set the blank check end address
FCR register = 83h
No
Yes
FCR register = 00h
No
Yes
FSTATR0.BCERR flag = 1?
No
Yes
Sequencer
initialization
End in ROM P/E mode
Figure 35.14 Procedure to Issue the Blank Check Command for the ROM
Page 11 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1130 of 1243
Before correction
P/E mode
Set target start address in
FSARH and FSARL
registers
Set target end address in
FEARH and FEARL
registers
FSTATR1.FRDY bit
= 1?
No
Yes
FSTATR1.FRDY bit
= 0?
No
Yes
FSTATR0.BCERR bit = 0?
Sequencer
initialization
No
Write 1 to
FRESETR.FRESET bit
Yes
blank check?
Yes
Write 0 to
FRESETR.FRESET bit
No
End in E2 DataFlash
P/E mode
Figure 35.15 E2 DataFlash Blank Check Procedure
Page 12 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
FASR.EXS bit = 0
Set blank check start address
Set blank check end address
FCR register = 83h
No
Yes
FCR register = 00h
No
Yes
FSTATR0.BCERR flag = 1?
No
Yes
Sequencer
initialization
Figure 35.15 Procedure to Issue the Blank Check Command for the E2 DataFlash
Page 13 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
• Page 1131 of 1243
Figure 35.16 in (4) Start-Up Area Information Program/Access Window Information Program of 35.7.3 Software
Command Usage is corrected as follows:
Before correction
Figure 35.16 is a simple flowchart of the procedure for the start-up area information program/access window
information program.
FASR.EXS bit = 1
DFLCTL.DFLEN bit = 1
Set programming data in
FWBH and FWBL registers
Write 81h or 82h
to FEXCR register
FSTATR1.EXRDY bit
= 1?
No
Yes
Ye 00h to
Write
s
FEXCR
register
Sequencer
initialization
No
FSTATR1.EXRDY bit
= 0?
Write 1 to
FRESETR.FRESET bit
Yes
FSTATR0.EILGLERR bit = 0?
No
Write 0 to
FRESETR.FRESET bit
Yes
FASR.EXS bit = 0
DFLCTL.DFLEN bit = 0
Setting to 0 is unnecessary when accessing
the E2 DataFlash after the above step.
End in ROM P/E mode
Figure 35.16 Simple Flowchart of the Procedure for the Start-Up Area Information Program/Access
Window Information Program
Page 14 of 15
Date: Nov. 17, 2014
TN-RX*-A111A/E
After correction
Figure 35.16 shows the procedure to issue the start-up area information program command and access window
information program command. When the sequencer has directly entered ROM/PE mode from E2 DataFlash access
disabled mode, set the DFLCTL.DFLEN bit to 1 at the beginning of the procedure.
FASR.EXS bit = 1
in registers FWBH and FWBL
Write 81h or 82h to FEXCR register
FSTATR1.EXRDY flag = 1?
No
Yes
FEXCR register = 00h
FSTATR1.EXRDY flag = 0?
No
Yes
FSTATR0.EILGLERR flag = 1 or
No
Yes
Sequencer
initialization
End in ROM P/E mode
Figure 35.16 Procedure to Issue the Start-Up Area Information Program Command/Access Window
Information Program Command
Page 15 of 15

RENESAS TECHNICAL UPDATE TE TN-RX*-A111A/E Date: Nov. 17, 2014

Transcription

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