Lecture 2
Transcription
Lecture 2
Lecture 2: CMOS Transistor Theory Original Lecture notes © 2010 David Money Harris Modified by Konstantinos Tatas Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 2 Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance – I = C (DV/Dt) -> Dt = (C/I) DV – Capacitance and current determine speed 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 3 MOS Capacitor Gate and body form MOS capacitor V <0 Operating modes + – Accumulation – Depletion (a) – Inversion 0<V <V g g polysilicon gate silicon dioxide insulator p-type body t + - depletion region (b) Vg > Vt + - inversion region depletion region (c) 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 4 Terminal Voltages Vg Mode of operation depends on Vg, Vd, Vs + + – Vgs = Vg – Vs Vgs Vgd – Vgd = Vg – Vd Vs Vd – Vds = Vd – Vs = Vgs - Vgd + Vds Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds 0 nMOS body is grounded. First assume source is 0 too. Three regions of operation – Cutoff – Linear – Saturation 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 5 nMOS Cutoff No channel Ids ≈ 0 Vgs = 0 + - g + - s d n+ n+ Vgd p-type body b 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 6 nMOS Linear Channel forms Current flows from d to s V – e from s to d Ids increases with Vds Similar to linear resistor gs > Vt + - g + - s d n+ n+ Vgd = Vgs Vds = 0 p-type body b Vgs > Vt + - g s + d n+ n+ Vgs > Vgd > Vt Ids 0 < Vds < Vgs-Vt p-type body b 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 7 nMOS Saturation Channel pinches off Ids independent of Vds We say current saturates Similar to current source Vgs > Vt + - g + - Vgd < Vt d Ids s n+ n+ Vds > Vgs-Vt p-type body b 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 8 I-V Characteristics In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 9 Channel Charge MOS structure looks like parallel plate capacitor while operating in inversions – Gate – oxide – channel Qchannel = CV Cox = eox / tox C = Cg = eoxWL/tox = CoxWL V = Vgc – Vt = (Vgs – Vds/2) – Vt gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, eox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 10 Carrier velocity Charge is carried by e Electrons are propelled by the lateral electric field between source and drain – E = Vds/L Carrier velocity v proportional to lateral E-field – v = mE m called mobility Time for carrier to cross channel: – t=L/v 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 11 nMOS Linear I-V Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds t W mCox L V V Vds gs t 2 V Vgs Vt ds Vds 2 3: CMOS Transistor Theory V ds W = mCox L ACOE419 – Digital IC and VLSI Design 12 nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt Now drain voltage no longer increases current Vdsat I ds Vgs Vt 2 V 2 gs Vt 3: CMOS Transistor Theory V dsat 2 ACOE419 – Digital IC and VLSI Design 13 nMOS I-V Summary Shockley 1st order transistor models 0 Vds I ds Vgs Vt 2 2 Vgs Vt 2 3: CMOS Transistor Theory Vgs Vt V V V ds ds dsat Vds Vdsat ACOE419 – Digital IC and VLSI Design cutoff linear saturation 14 Example We will be using a 0.6 mm process for your project – From AMI Semiconductor – tox = 100 Å 2.5 V =5 2 – m = 350 cm /V*s 2 – Vt = 0.7 V 1.5 V =4 Plot Ids vs. Vds 1 V =3 – Vgs = 0, 1, 2, 3, 4, 5 0.5 V =2 – Use W/L = 4/2 l V =1 0 Ids (mA) gs gs gs gs gs 0 3.9 8.85 1014 W W mCox 350 8 L 100 10 L 3: CMOS Transistor Theory 1 2 W 120 μA/V 2 L ACOE419 – Digital IC and VLSI Design 3 4 5 Vds 15 pMOS I-V All dopings and voltages are inverted for pMOS – Source is the more positive terminal Mobility mp is determined by holes – Typically 2-3x lower than that of electrons mn – 120 cm2/V•s in AMI 0.6 mm process Thus pMOS must be wider to provide same current – In this class, assume mn / mp = 2 0 Vgs = -1 Vgs = -2 -0.2 Ids (mA) Vgs = -3 -0.4 Vgs = -4 -0.6 -0.8 -5 Vgs = -5 -4 -3 -2 -1 0 Vds 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 16 Capacitance Any two conductors separated by an insulator have capacitance Gate to channel capacitor is very important – Creates channel charge necessary for operation Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 17 Gate Capacitance Approximate channel as connected to source Cgs = eoxWL/tox = CoxWL = CpermicronW Cpermicron is typically about 2 fF/mm polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, eox = 3.9e0) p-type body 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 18 Diffusion Capacitance Csb, Cdb Undesirable, called parasitic capacitance Capacitance depends on area and perimeter – Use small diffusion nodes – Comparable to Cg for contacted diff – ½ Cg for uncontacted – Varies with process 2: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 19 Example 1 Consider an nMOS transistor in a 0.6 μm process with W/L = 4/2λ. In this process, the gate oxide thickness is 100 Å and the mobility of electrons is 350 cm^2/V · s. Give the Ids equation for the linear and saturation regions 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 20 Example 2 A 90nm long transistor has a gate oxide thickness of 16 Å. What is its gate capacitance per micron of width? 3: CMOS Transistor Theory ACOE419 – Digital IC and VLSI Design 21