SUGGESTED EXERCISES 3
The bias circuit below is used in a design with VG=5V and RS=1kΩ. For an enhancement
MOSFET with kn’(W/L) =2mA/V2, the source voltage was measured and found to be 2V.
What must Vt be for this device? If a device for which Vt is 0.5V less is used, what does
Vs become? What bias current results?
In the circuit below, let RG=10MΩ, RD=10kΩ, and VDD=10V. For each of the following
two transistors, find the voltages VD and VG.
a) Vt=1V and kn’W/L=0.5mA/V2.
b) Vt=2V and kn’W/L=1.25mA/V2.
Using the feedback bias arrangement shown in the circuit of problem 2, with a 9V supply
and an NMOS device for which Vt=1V and kn’W/L=0.4mA/V2, find RD to establish a
drain current of 0.2mA. If resistor values are limited to those on the 5% resistor scale(
See appendix G in Sedra), what value would you choose? What values of current and VD
In the circuit below, the NMOS transistor has |Vt|=0.9V and VA=50V and operates with
VD=2V. What is the voltage gain vo/vi ? What do VD and the gain become for I increased
A CS amplifier using an NMOS transistor biased in the manner of the circuit below, for
which gm=2mA/V is found to have an overall voltage gain Gv of -16V/V. What value
should a resistance Rs inserted in the source lead have to reduce the voltage gain by a
factor of 4?
The overall voltage gain of the amplifier below was measure with a resistance Rs of 1kΩ
in place and found to be -10 V/V. When RS is shorted, but the circuit operation remained
linear the gain doubled. What must gm be? What value of RS is needed to obtain an
overall voltage gain of -8V/V?