Computer Simulation Problems Section 8.1: The MOS Differential

Computer Simulation Problems
(a) For v GI = V C2 = 0 V, find Vovand Vcs for each of QI and
Also find Vs, VDI' and VD2 .
(b) If the current source requires a minimum voltage of
0.5 V, find the input common-mode range.
Q2'
ImJ Problems identified by this icon are intended to dem­
onstrate the value of using SPICE simulation to verify hand
analysis and design, and to investigate important issues such
as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multisim sim­
ulations for all the indicated problems can be found in the
corresponding files on the CD. Note that if a particular
parameter value is not specified in the problem statement,
you are to make a reasonable assumption.
* difficult problem; ** more difficult; *** very challenging
andlor time-consuming; D: design problem.
Section 8.1: The MOS Differential Pair
8.1 For an NMOS differential pair with a common-mode
voltage VCM applied, as shown in Fig. 8.2, let VDD = Vss =
1.0 V, k~ = 0.4 rnAN2, (WIL)I.2 = 12.5, V"' = 0.5 V, 1=0.2
rnA, RD = 10 ill, and neglect channel-length modulation.
(a) Find VDvand Vcs for each transistor.
(b) For VCM = 0, find ~~, IDI' I D2 , VDI' and Vm .
(c) Repeat (b) for VCM = +0.3 V.
(d) Repeat (b) for VCM =-0.1 V.
(e) What is the highest value of VCM for which Ql and Q2
remain in saturation?
(f) If current source I requires a minimum voltage of 0.2 V
to operate properly, what is the lowest value allowed for Vs
and hence for Vc ,,?
8.2 For the PMOS differential amplifier shown in Fig.
P8.2 let VIP = -0.8 V and k; WIL = 4 rnAN2 • Neglect
channel-length modulation.
8.3 For the differential amplifier specified in Problem 8.1
let vG2 = 0 and VGI = V id · Find the value ofv id that corresponds
to each of the following situations:
(a) i DI =iD2 =0.1 rnA; (b) iDI =0.15 rnA and i02=0.05 mA;(c)
i Dl = 0.2 rnA and iD2 = 0 (Q2 just cuts off); (d) iDl = 0.05 rnA
and iD2 = 0.15 rnA; (e) i DI = 0 rnA (QI just cuts off) and im =
0.2 rnA. For each case, find vs' V D" v D2 ' and (vD2 - VOl)'
I:mI 8.4 For the differential amplifier specified in Prob­
lem 8.2, let v G2 = 0 and VCI = V id• Find the range of V id needed
to steer the bias current from one side of the pair to the
other. At each end of this range, give the value of the volt­
age at the common-source terminal and the drain voltages.
8.5 Consider the differential amplifier specified in Prob­
lem 8.1 with Gz grounded and VCI = v ut . Let V id be adjusted to
the value that causes i Ol = 0.11 rnA and iD2 = 0.09 rnA. Find
the corresponding values of v GS2 ' vs' V CSI ' and hence V id•
What is the difference output voltage vD2-vDl? What is the
voltage gain (vD2 - vDl)lv ut? What value of Vid results in iDl =
0.09 rnA and iD2 = 0.11 rnA?
o
8.6 Design the circuit in Fig. P8.6 to obtain a dc voltage
of +0.2V at each of the drains of QI and Q2 when
v GI = v G2 = 0 V. Operate all transistors at V 0 v = 0.2 V
and assume that for the process technology in which the cir­
cuit is fabricated, V tn = 0.5 V and flnCox = 250 J.!A/V2.
Neglect channel-length modulation. Determine the values of
R, RD, and the WIL ratios of Q], Q2' Q3' and Q4' What
is the input common-mode voltage range for your design?
+2.5V
VDD = +1.2V
0.5 rnA
+1.2V
0.1 mAl
lO.4 mA
4kO
4kO
-Vss = -1.2 V
-2.5V
Figure PB.2
Figure PB.6
Problems
the lowest value that VDD must have to ensure saturation­
mode operation for QJ andQ2 at all times? Assume
VI = 0.5 V.
8.18 A MOS differential amplifier is designed to have a
differential gain Ad equal to the voltage gain obtained from
a common-source amplifier. Both amplifiers utilize the
same values of RD and supply voltages, and all the transis­
tors have the same WIL ratios. What must the bias current I
of the differential pair be relative to the bias current I D of
the CS amplifier? What is the ratio of the power dissipation
of the two circuits?
8.19 A differential amplifier is designed to have a differen­
tial voltage gain equal to the voltage gain of a common­
source amplifier. Both amplifiers use the same values of RD
and supply voltages and are designed to dissipate equal
amounts of power in their equilibrium or quiescent state. As
well, all the transistors use the same channel length. What
must the width W of the differential-pair transistors be rela­
tive to the width of the CS transistor?
D 8.20 Figure P8.20 shows a MOS differential amplifer
with the drain resistors RD implemented using diode­
connected PMOS transistors, Q3 and Q4' Let QJ and Q2
be matched, and Q3 and Q4 be matched.
669
(c) If f.in = 4 f.ip and all four transistors have the same chan­
nellength, find ( WI, 21 W 3 , 4) that results in Ad = 10 VN.
8.21 Find the differential half-circuit for the differential
amplifier shown in Fig. P8.2l and use it to derive an expres­
sion for the differential gain Ad = v a/ v id in tenns of gm ,
RD , and Rs . Neglect the Early effect. What is the gain with
Rs = O? What is the value of Rs (in tenns of 11 gm) that
reduces the gain to half this value?
Vid
o-------J
2
I
2
Figure PB.21
*8.22 The resistance Rs in the circuit of Fig. P8.2l can be
implemented by using a MOSFET operated in the triode
region, as shown in Fig. P8.22. Here Q3 implements R s '
with the value of Rs detennined by the voltage Vc at the
gate of Q3'
Vid~
+-~
2
1 - - - - 0 VG2
Figure PB.20
(a) Find the differential half-circuit and use it to derive an
expression for Ad in tenns of gml,2' gm3,4' raj ,2' and
r a34 ·
(b) Neglecting the effect of the output resistances r a' find
Ad in tenns of f.in' f.ip, (WIL)J,2' and (W1Lh,4'
I
I
2
2
Figure PB.22
670
Chapter 8
Differential and Multistage Amplifiers
(a)WithvGJ = vG2 = 0 V,andassumingthatQJ andQ2
are operating in saturation, what dc voltages appear at the
sources of QJ and Q2' Express these in terms of the over­
drive voltage Vov at which each of QJ and Q2 operates,
and VI'
(b) For the situation in (a), what current flows in Q3? What
overdrive voltage VbV3 is Q3 operating at, in terms of Vc,
ating? Find an expression for r DS for each of Q3 and Q4
and hence for R, in terms of (WIL)J,2, (W1Lh,4' and
gmJ,2'
(b) Now with vGJ = v i/2 and vG2 = -v j /2, where vid
is a small signal, find an expression of the voltage gain
Ad =vo/vid in terms of gmJ,2' R D, (W1Lh,2, and
( W1L h,4'
Vov,and VI?
o *8.24 Figure PS.24 shows a circuit for a differential
amplifier with an active load. Here QJ and Q2 form the differ­
ential pair, while the current source transistors Q. and Qs
form the active loads for QJ and Q2' respectively. The de
bias circuit that establishes an appropriate dc voltage at
the drains of QJ and Q2 is not shown. It is required to
design the circuit to meet the following specifications:
(c) Now consider the case v GI = + vidl2 and
v G2 = - v j /2, where vid is a small signal. Convince
yourself that Q3 now conducts current and operates in the
triode region with a small vDS' What resistance rDS does it
have, expressed in terms of the overdrive voltage VOV3 at
which it is operating. This is the resistance Rs. Now if all
three transistors have the same WIL, express Rs in terms of
Vov , VOV3 ' and gmJ,2'
(d) Find VOV3 and hence Vc that result in (i)
Rs = I/gm1,2; (ii) Rs = O.5/gmJ ,2·
*8.23 The circuit of Fig. PS.23 shows an effective way of
implementing the resistance Rs needed for the circuit in
Fig. PS.21. Here Rs is realized as the series equivalent of
two MOSFETs Q3 and Q4 that are operated in the triode
region, thus, Rs = rDS3 + r DS4 ' Assume that QJ and Q2
are matched and operate in saturation at an overdrive volt­
age Vov that corresponds to a drain bias current of 112.
Also, assume that Q3 and Q4 are matched.
(a) Differential gain Ad = SO VN.
(b) 1REF =1= lOO/lA.
(c) The dc voltage at the gates of Q6 and Q3 is +1.5 V.
(d) The dc voltage at the gates of Q7' Q., and Qs is -1.5 V.
The technology available is specified as follows: J.inCox =
3J.ip Cox = 90/lAN2; Vrn = !VIP I = 0.7 V, VAn = I~pl = 20 V.
Specify the required value of R and the WIL ratios for all
transistors. Also specify 1D and IVGsl at which each transis­
tor is operating. For dc bias calculations you may neglect
channel-length modulation.
+2.5V
Q3
tf
IREFt
II
0 VG2
VGI
R
Vid!2
1---0 -vj2
o--J
Vod
Figure PS.23
(a) With v GI = v G2 = 0 V, what dc voltages appear at the
sources of QI and Q2? What current flows through Q 3
and Q4? At what overdrive voltages are Q3 and Q4 oper­
-2.5V
Figure PS.24
+
678 Chapter 8
Differential and Multistage Amplifiers
8.82 A differential amplifier for which the total emitter bias
current is 500 JlA uses transistors for which f3 is specified to
lie between 80 and 200. What is the largest possible input bias
current? The smallest possible input bias current? The largest
possible input offset current?
**8.83 In a particular BIT differential amplifier, a produc­
tion error results in one of the transistors having an emitter­
base junction area twice that of the other. With both inputs
grounded, find the current in each of the two transistors and
hence the dc offset voltage at the output, assuming that the
collector resistances are equal. Use small-signal analysis to
find the input voltage that would restore current balance to
the differential pair. Repeat using large-signal analysis and
compare results.
o 8.84 A large fraction of mass-produced differential­
amplifier modules employing 20-kn collector resistors is
found to have an input offset voltage ranging from +3 mV to
-3 mY. By what amount must one collector resistor be
adjusted to reduce the input offset to zero? If an adjustment
mechanism is devised that raises one collector resistor while
correspondingly lowering the other, what resistance change
is needed? If a potentiometer connected as shown in Fig.
P8.81 is used, what value of potentiometer resistance (speci­
fied to I significant digit) is needed?
(b) Current source ! is implemented with the modified
Wilson current mirror shown in Fig. P8.87.
Recalling that for the simple mirror R5S = r0 IQs and for the
Wilson mirror Rss = gm7ro7ro5' and assuming that all tran­
sistors have the same I f'A I and k' WI L, show that for case (a)
CMRR =
2(~r
r;)V
and for case (b)
CMRR =
2J2(iov
r
where Vov is the overdrive voltage that corresponds to a
drain current of 112. For k'WIL = 10 mA/V~ J = I mA,
and 1V41 = 10 V, find CMRR for both cases.
I
I
It!
I
Section 8.5: The Differential Amplifier with
Active Load
o 8.85 In an active-loaded differential amplifier of the
form shown in Fig. 8.32(a), all transistors are characterized
WI L = 3.2 mAN2 , and I f'A I = 20 V. Find the bias
by
current J for which the gain v / v id = 100 VN.
e
lEI 0 8.86 It is required to design the active-loaded differ­
ential MOS amplifier of Fig. 8.32 to obtain a differential gain of
50 VN. The technology available provides JinCo, =
4Jip Cox = 400 JlAN2,
= 0.5 V, and V~I = 20 V/Jlm
and operates from ± I V supplies. Use a bias current J =
200 JlA and operate all devices at a ~ = 0.2 V.
IVII
I
IV
(a) Find the WIL ratios of the four transistors.
(b) Specify the channellengtb required of all transistors.
(c) IfVcM = 0, what is the allowable range of va?
(d) If I is delivered by a simple NMOS current source
operated at the same Vav and having the same channel
length as the other four transistors, determine the CMRR
obtained.
8.87 Consider the active-loaded MOS differential ampli­
fier of Fig. 8.32(a) in two cases:
(a) Current source I is implemented with a simple current
mirror.
Figure P8.87
o 8.88 Consider an active-loaded differential amplifier
such as that shown in Fig. 8.32(a) with the bias current
source implemented with the modified Wilson mirror of Fig.
P8.87 with J = 200 JlA. The transistors have IV,I = 0.5 V
and k / WIL = 5 mAN2• What is the lowest value of the total
power supply (VDD + Vss) that allows each transistor to oper­
ate with IVvsI ;0: IVas[?
*8.89 (a) Sketch the circuit of an active-loaded MOS dif­
ferential amplifier in which the input transistors are cas­
coded and a casco de current mirror is used for the load.
(b) Show that if all transistors are operated at an overdrive
voltage Vov and have equal Early voltages If'A I, the gain is
given by
Ad = 2(
f'A /
Vov )2
682
Chapter 8
Differential and Multistage Amplifiers
(s) With VA = v;/2 and VB = -v;/2, find the voltage
gain volv id' Assume an Early voltage of 5 V.
VDD
~
o *8.109 In a particular design of the CMOS op amp of
Fig. 8A1 the designer wishes to investigate the effects of
increasing the W;L ratio of both Q, and Q2 by a factor of 4.
Assuming that all other parameters are kept unchanged,
refer to Example 8.5 to help you answer the following
questions:
J--o
Vo
(a) Find the resulting change in IVovl and in gm of Q, and
Q2'
(b) What change results in the voltage gain of the input
stage? In the overall voltage gain?
(c) What is the effect on the input offset voltages? (You
might wish to refer to Section 8A).
-Vss
Figure P8.l06
Section 8.6: Multistage Amplifiers
8.107 Consider the circuit in Fig. 8A1 with the device
geometries (in J.lm) shown in the Table P8.107. Let IREF =
225 J.lA, IVt! = 0.75 V for all devices, PnCox = 180 J.lAIV2,
J1p Cox = 60 J.lAN2, IV4 = 9 V for all devices, VDD = Vss =
1.5 V. Determine the width of Q6' W, that will ensure that
the op amp will not have a systematic offset voltage. Then,
for all devices evaluate I D , IVovl, IVGS I, gm' and roo Provide
your results in a table similar to Table 8.1. Also find A" A2 ,
the open-loop voltage gain, the input common-mode range,
and the output voltage range. Neglect the effect of VA on the
bias current.
1
o *8.108 The two-stage CMOS op amp in Fig. P8.l08 is
fabricated in a 0.18-J.lm technology having k~ = 4k; =
400 J.lAN2, Vtn = -VtP = OA V.
(a) With A and B grounded, perform a dc design that will
result in each of Q" Q2' Q3' and Q4 conducting a drain cur­
rent of 200 J.lA. Design so that all transistors operate at 0.2
V-overdrive voltages. Specify the WIL ratio required for
each MOSFET. Present your results in tabular form. What is
the dc voltage at the output (ideally)?
(b) Find the input common-mode range.
(c) Find the allowable range of the output voltage.
8.110 Consider the amplifier of Fig. 8A1, whose parame­
ters are specified in Example 8.5. If a manufacturing error
results in the W;L ratio of Q7 being 5010.8, find the current
that Q7 will now conduct. Thus find the systematic offset
voltage that will appear at the output. (Use the results of
Example 8.5.) Assuming that the open-loop gain will remain
approximately unchanged from the value found in Example
8.5, find the corresponding value of input offset voltage,
Vos·
8.111 Consider the input stage of the CMOS op amp in
Fig. 8A1 with both inputs grounded. Assume that the two
sides of the input stage are perfectly matched except that
the threshold voltages of Q3 and Q4 have a mismatch ~Vt.
Show that a current gm3~Vt appears at the output of the
first stage. What is the corresponding input offset volt­
age?
*8.112 Figure P8.112 shows a bipolar op-amp circuit that
resembles the CMOS op amp of Fig. 8Al. Here, the input
differential pair Q,-Q2 is loaded in a current mirror formed by
Q3 and Q4' The second stage is formed by the current­
source-loaded common-emitter transistor Q5' Unlike the
CMOS circuit, here there is an output stage formed by the
emitter follower Q6' The function of capacitor Cc will be
explained later in Chapter 10. All transistors have f3 = 100,
WBEI = 0.7 V, and ro = 00.
(a) For inputs grounded and output held at 0 V (by negative
feedback, not shown) find the emitter currents of all transis­
tors.
(b) Calculate the gain ofthe amplifier with RL = 10 kil.
Table P8.l07
Transistor
WIL
Q,
Q2
Q3
Q4
Qs
Q6
Q7
3010.5
30/0.5
10/0.5
10/0.5
60/0.5
W/0.5
60/0.5
Q.
6010.5
J
Problems 683
VDD =+ 1 V
Figure PS.l0S
-5V
Figure PS.112
08.113 It is required to design the circuit of Fig. 8.42 to
provide a bias current Is of 225 J..lA with Q8 and Q9 as
matched devices having WIL =6010.5. Transistors QIO' Qll'
and Q13 are to be identical and must have the same gm as Qs
and Q9' Transistor Q12 is to be four times as wide as Q13'
Let k~ = 3k; = 180 J..lAN 2, and V/)D = Vss = 1.5 V. Find
the required value of RB • What is the voltage drop across
RB? Also specify the WIL ratios of Qw Qll' Q'2' and QI3
and give the expected dc voltages at the gates of Qw QIO'
and Q8'
8.114 A BIT differential amplifier, biased to have re = 100 Q
and utilizing two l00-Q emitter resistors and 5-kQ loads, drives
a second differential stage biased to have re = 50 Q. All
BJTs have jJ = 100. What is the voltage gain of the first
stage? Also find the input resistance of the first stage, and