Homework 6

EECS 16A
Designing Information Devices and Systems I
Homework 6
Spring 2015
This homework is due March 19, 2015 at 5PM.
Note that unless explicitly stated otherwise, you can assume that all op-amps in this homework are ideal (i.e.
Rin = ∞ Ω, Rout = 0 Ω, and A = ∞).
1. Practice with Negative Feedback Amplifiers
For each of the circuits shown below, plot Vout for Vin ranging from −2V to +2V . Note that understanding what these circuits do and how they work may help you with the design problems in the rest of the
homework.
(a)
2kΩ
1kΩ
5V
R1 =1kΩ
−
+
−
+
Vin
+
−5V
R2 =1kΩ
Vout
–
Solutions: Using KCL at the black dot on the left, we have
Vout − 0
0 −Vin
=
2kΩ
1kΩ
Vout = −2Vin
Note that R1 and R2 does not affect the gain. This is because the current flowing through R1 is 0A due
to the golden rules of the op-amp, so there is no voltage drop across the resistor and the voltages at its
two nodes are equivalent. Thus it does not affect the circuit. R2 , on the other hand, is located between
the output of an op-amp and ground. Since the output resistance of the op-amp is very small, and the
voltage at the output of the op-amp is only dependent in its inputs, this resistor is just pulling current
out of the op-amp as a load.
EECS 16A, Spring 2015, Homework 6
1
(b) Once you have solved for the behavior of this specific circuit, you should consider what type of function
this circuit might be able to implement. In particular, what if the 2V voltage source was not fixed in
value, but was actually another input to the circuit?
5V
+
−
+
Vin (Vin1 )
I1
−
R2 =9kΩ
−5V
I2
+
Vout
–
R1 =1kΩ
−
+
2V (Vin2 )
Solutions: Using KCL at the black dot and the fact that vn = v p for the op-amp, we have
I1 = I2
Vout −Vin
Vin − 2
=
9kΩ
1kΩ
Vout = 10Vin − 18V
Since the op-amp is powered by −5V and 5V , Vout would rail at −5V when Vin < 1.3V .
EECS 16A, Spring 2015, Homework 6
2
To examine the functionality of this circuit, we can make both voltage sources variable and write Vout
in terms of Vin1 and Vin2 .
I1 = I2
Vout −Vin1
Vin1 −Vin2
=
R2
R
1 R2
R2
Vout = 1 +
Vin1 − Vin2
R1
R1
This means the circuit does a scaling and subtraction with Vout = (1 + A)Vin1 − AVin2 (A is some gain
value).
(c) Much like in part b), after solving for this specific circuit, you should think about what type of function
this circuit might be able to implement. In particular, what if the 1V voltage source was not fixed in
value, but was actually another input to the circuit?
R1 =1kΩ
I1
+
+
−
+
Vin (Vin1 )
10V
−
I2
−10V
1kΩ
R3
Vout
–
R2 =2kΩ
1kΩ
−
+
1V (Vin2 )
I3
R4 =1kΩ
I4
EECS 16A, Spring 2015, Homework 6
3
Solutions: With the currents defined as above, using KCL at v p we have
I1 = I2
Vin −Vp
Vp − 1
=
1kΩ
2kΩ
2
1
Vp = Vin +
3
3
Since the ideal op-amp in negative feedback would make v p = vn , we use KCL in node vn to show that
I3 = I4
Vout −Vn
Vn − 0
=
2kΩ
1kΩ
Vout = 2Vin + 1
Just as the previous subproblem, we can replace the 1V source with a variable voltage source Vin2 .
Now we have
I1 = I2
Vin1 −Vp
Vp −Vin2
=
R1
R2
1
1
Vin1 Vin2
Vp
+
=
+
R1 R2
R1
R2
R2
R1
Vp =
Vin1 +
Vin2
R2 + R1
R2 + R1
I3 = I4
Vout −Vn
Vn − 0
=
R4
R
3
R3
Vout = 1 +
Vn
R4
R2
R1
R3
Vin1 +
Vin2
Vout = 1 +
R4
R2 + R1
R2 + R1
EECS 16A, Spring 2015, Homework 6
4
Thus, this circuit scales and adds the inputs with Vout = A(kVin1 + (1 − k)Vin2 ), where 0 ≤ k ≤ 1 and
A > 1.
(d)
2.5kΩ
1kΩ
1kΩ
5V
1kΩ
−
−
+
Vin
10kΩ
V2
+
−5V
1kΩ I
3
V3
I1
5V
−
+
1kΩ
I2
+
Vout
−5V
–
Solutions: First, we can do KCL around the left black dot. Since both ends of the 10kΩ resistor are
at the same voltage (due to the golden rules), we can disregard it.
We can also realize that this portion is in the same format as part a, and therefore, we have V2 = −2.5Vin .
We can call the voltage at the center black dot V3 , and use KCL
I1 = I2 + I3
V2 −V3
V3
V3
=
+
=0
1kΩ
1kΩ 1kΩ
5
1
V3 = V2 = − Vin
3
6
We can again recognize
5 the portion on the right as being in the same format as part a, so we have
5
Vout = (−1) − 6 Vin = 6 Vin
2. IoT4eva Revisited
EECS 16A, Spring 2015, Homework 6
5
After guiding them to make an intelligent selection for their super-capacitors, IoT4eva was so happy with
your performance that you got a promotion! The good news is that you’re getting paid more, but the "bad"
news is that you have more responsibilities too. In particular, you are now responsible not only for selecting
the super-capacitors used to power the device, but also for building the rest of the circuitry associated with
the power supply.
In practice, many real circuits (especially sensors that are trying to detect very small signals) don’t like
to operate with supply voltages that vary substantially over time. Remembering that the voltage on our
super capacitors drops linearly as we pull current out of them, this means that if we want to use these super
capacitors for our device, we need to build another circuit. This circuit is powered by the super-capacitor
and produces a constant voltage at its output, where this voltage will then be used to supply power to rest
of the device. These circuits are often referred to as "voltage regulators", and in this problem we’ll explore
how to build the simplest form of such a voltage regulator.
(a) The first problem we may have had to solve to realize such a voltage regulator is to figure out how
to build a reference that would allow us to set the voltage at the output of our regulator to a known
absolute value. Fortunately someone else in the company has already built one of those and made it
available to you - you can model this circuit as a voltage source whose value is 0.8V with a source
resistance of 1kΩ. (The internals of this voltage reference circuit aren’t important for this problem, but
as you should see shortly, this circuit by itself is not appropriate for supplying power to the rest of the
device.)
Now that we have a reference we can focus on the core of the voltage regulator itself. Using this
reference circuit, an op-amp, and resistors, design a circuit that is powered by the super-capacitor
voltage Vsc (which for now you can assume is always high enough for the circuit to work) and that
would produce a constant 1.2V supply voltage for the rest of the device. Note that you can model the
load from the rest of the device as a 10mA current source; please be sure to choose specific values for
any resistors you use in your circuit as well.
Solutions: Let’s practice the design method.
Step 1:
In this problem the ultimate objective is to output a 1.2V node that is capable of driving the load
modeled as a 10mA current source. We are also required to power up the voltage regulator using the
super-capacitor.
Step 2:
We are given a reference voltage source that we can use to power the IoT device. However, the voltage
of the reference is not high enough and it has a high source resistance (in fact, if we run 0.8mA of
current through the source resistance the voltage drop across the resistor would be the same as the
voltage source itself). The only other source of voltage is the super-capacitor, but the problem is it has
a variable voltage. Thus, we need to build a circuit that buffers (provides low output resistance) and
amplifies the reference voltage which is powered by the super-capacitor.
Step 3:
Now that we have a high-level block diagram of the circuit, we can think about how to implement it.
We need some form of buffer, so we will definitely need an op-amp. Moreover, we also know that the
EECS 16A, Spring 2015, Homework 6
6
output of the op-amp must be directly connected to the device for it to act as a buffer. We also know
that the circuit can only be powered by the super-capacitor, so we power the op-amp using VSC . The
other functionality we have not dealt with is the gain. We need a gain of 1.2V /0.8V = 1.5, and we
have seen that we can implement this using a non-inverting amplifier. Since the gain of a non-inverting
1
amplifier is R2R+R
, we can set any value to R1 and R2 such that this ratio is 1.5. For example, we can
1
use R1 = 2kΩ and R2 = 1kΩ. Note that the source resistance of the reference voltage doesn’t play a
role here, since there is no current flowing into the inputs of the op-amp. The circuit is shown below.
VSC
1kΩ
+
−
+
0.8V
−
1kΩ
10mA (IoT device)
2kΩ
(b) Now that we’ve built the voltage regulator and we know that we want its output voltage to stay fixed at
1.2V , what is the minimum voltage we need on our super capacitors Vsc,min to ensure that the regulator
can indeed produce a fixed 1.2V output?
Solutions: The op-amp will not be able to produce 1.2V at its output if VSC < 1.2V , so VSC,min = 1.2V .
(c) One of the most important things to evaluate about a voltage regulator is its efficiency - i.e., the power
dissipated by the load circuits (in this case, the rest of the IoT4eva device) divided by the total amount
of power delivered by the power supply. Continuing to model the rest of the IoT4eva device as a 10mA
current source, how much power is dissipated by the 10mA current source? As a function of Vsc (and
assuming Vsc is higher than the minimum you found in part b), how much power is actually delivered
by the super-capacitor? What is therefore the efficiency of your voltage regulator circuit?
Note that you can assume that the op-amp does not dissipate any power except for what is required
to supply the current to its output. (Hint: The op-amp itself can’t generate any power, so you should
think about where this current would have to originate from.) It is also worth noting that the voltage
reference circuit that was given to you would actually dissipate some power from the super-capacitor
as well, but you can ignore that for this problem.
Solutions: The 10mA curent source is supplied with 1.2V , so
Pdevice = 1.2V · 10mA = 12mW
Our reference voltage does not output any current since the current into the input of an op-amp in
negative feedback is 0A, so the power associated with that source is 0W . It is important to note that the
op-amp by itself cannot generate any power. Any current flowing to the 1.2V output node has to come
from the op-amp, and any current that flows out of the op-amp must come from the super-capacitor.
The op-amp is not supplying any power, it just dissipates a part of the power it receives and passes
on the rest to the output. The total power supplied by the super-capacitor is the product of the output
EECS 16A, Spring 2015, Homework 6
7
current of the op-amp with the voltage of the super-capacitor. This output current is the sum of the
current source and the current flowing through the negative feedback resistors to ground.
Iop−amp = 10mA +
1.2V
= 10.4mA
3kΩ
Power from super-capacitor is thus VSC · 10.4mA. So, the efficiency is
12
1.2V · 10mA
=
VSC · 10.4mA 10.4VSC
Note: The effeciency might differ depending on your choice of resistor values.
Notice that VSC shows up in the denominator. Thus if we increase the super-capacitor voltage our
effeciency drops. This might be counterintuitive at first, but the reason this happens is that the op-amp
is configured in a way that forces the output to a certain voltage. That means there is some voltage drop
that happens inside the op-amp itself, and this voltage drop is wasted since it does not get delivered to
the IoT device.
Even though the effeciency of this circuit is quite low, this circuit is actually used in real life quite
often. This is because the circuit is small (in PCB area) and have nice properties in terms of isolating
different components in a circuit from each other.
(d) Still using only op-amps and resistors, is there anything you can do to improve the efficiency of your
voltage regulator design?
Solutions: We cannot really do anything with the 1.2V
VSC term since 1.2V is required for the load and
10mA
VSC is basically set by the super-capacitor. Thus, we can only try to improve the 10.4mA
part. Since
the load current is constant, to lower this ratio, we can increase the feedback resistors; for example to
12
10kΩ and 20kΩ - this would raise the efficiency to 10.04V
.
SC
Note: We can never get to an effeciency of 1 (100%). This is because there is voltage drop between
the super-capacitor and the output of the op-amp since VSC is variable. Since at least Iload has to flow
out of the op-amp, even without the feedback current VSC has to stay exactly 1.2V for the efficiency to
be 1, which is not possible.
3. Noise Cancelling Headphones
Almost everyone has probably used "noise cancelling" headphones - in some cases without even knowing
it. The basic goal of a noise cancelling headphone is for the user to hear only the desired audio signal
and not any other sounds that may have been produced by external sources. In order to achieve this goal,
noise cancelling headphones include at least one microphone that listens to what you might have otherwise
heard from external sources, and then feeds a signal in to your speakers that cancels (subtracts out) that
externally-generated sound.
Solutions: There are a lot of different solutions for this problem. If you think your circuit works (i.e.
implements the block diagram below) you can give yourselves full credit. These solutions are agressive and
try to use as little component as needed.
(a) Let’s start by looking at the most basic part of the headphones, which is driving the speaker itself with
the audio stream we would like to hear. In our system, the source of the audio comes from a digitalto-analog converter or DAC (a component that converts the digital bits we use to represent our audio
stream in the tablet/phone/computer/etc. to analog voltages) that can modeled as a voltage source with
a 50Ω source impedance, and with min/max values of 0V and 1V . The speaker can be modeled as
an 8Ω resistor, but in order to produce loud enough sounds and not damage the speaker (driving the
EECS 16A, Spring 2015, Homework 6
8
speaker with non-zero average voltage can damage the transducer within the speaker), it needs to be
driven from −1.5V to 1.5V (relative to the ground connected to the DAC, which is the same ground
used throughout the system).
Assuming you are given two voltage sources with values −1.5V and 1.5V as well as an op-amp and any
resistors you would like, design a circuit that could drive the speaker while meeting the specifications
above. Hint: You may want to think about how to build a circuit that centers the effective voltage
coming out of the DAC at 0V (instead of the 0.5V center point directly produced by the DAC voltage
source).
Solutions: Let’s go through the design method.
Step 1:
The goal of this circuit is to have transform an input that ranges from 0V to 1V into an output that
ranges from −1.5V to 1.5V .
Step 2:
To achieve the goal, we need 3 things:
1. Shift the signal to center at 0V
2. Provide gain to the signal
3. Provide low output resistance
The order of shifting and amplifying does not really matter, but here we choose shifting before amplifying because we would not need high voltage sources (which is needed if we amplify first). When
we shift the input signal, the shifted signal does not have to have the same amplitude because we can
adjust the gain of the amplifier accordingly. In fact, as we will see shortly, the simplest implementation
of the shifter will have to change the amplitude as well. If we make the amplitude of the shifted input
signal N, the block diagram is shown below.
Step 3:
To solve the third point, we can simply use an op-amp to drive the output. We have also seen how we
can provide a gain of more than 1 from problem 2, using a non-inverting op-amp. Thus, we are left
with the voltage shifter.
We have actually seen a circuit that does something similar - the circuit in problem 1(c). Using a 1V
source, we were able to add a constant component to our input and shift the it by 13 V . However, that
circuit has a gain of 23 so we have to adjust that. If we just take the first part of the circuit, which is
a voltage divider between two voltages V1 and V2 , we already derived that the output of the divider is
kV1 + (1 − k)V2 . Picking appropriate values for V2 and k and using V1 as the input, we realize that there
is some gain k < 1. Thus, we have to adjust the amplifier gain to A/k = 3/k (A = 3 since our output
range is 3V while our input range is 1V ).
EECS 16A, Spring 2015, Homework 6
9
Let’s build the voltage shifter. We have derived that for the voltage divider Vout = kV1 + (1 − k)V2 . We
can only use the −1.5V voltage source for V2 if we want to shift the signal level down. We also know
that we want the shift to be half of the actual signal. Since V1 , the DAC voltage, ranges between 0V
and 1V , we want
1
(1 − k)V2 = − k · 1
2
3
1
=− k
(1 − k) · −
2
2
3 − 3k = k
3
k=
4
2
In problem 1(c), we found that k = R1R+R
. Thus we can pick values for the resistors such that the
2
ratio is 3/4. However, remember that our DAC has a source resistance of 50Ω. We can use this series
resistance as R1 since it is in series with the voltage source. It follows that R2 = 150Ω. Our voltage
shifter circuit is shown below. We label the output of the divider as Vin since it acts as the input to our
amplifier.
50Ω
Vin
−
+
VDAC
150Ω
−1.5V
Remember that this voltage shifter actually has a gain. Specifically, Vin = kVDAC + (1 − k)(−1.5) =
0.75VDAC − 0.375. Thus, this shifter has a gain of 0.75. Following our discussion before, we need
to adjust our amplifier to have a gain of 3/0.75 = 4. But we have seen how to build a non-inverting
amplifier that does this. We just have to pick resistor values to set the gain. Since the gain of a
1
non-inverting amplifier is R2R+R
, we can choose R1 = 1kΩ and R2 = 3kΩ. The final circuit is shown
1
below.
1.5V
50Ω
−
+
VDAC
Vin
+
R1
−
−1.5V
3kΩ
8Ω speaker
−1.5V
1kΩ
(b) Now that we know how to drive the speaker, let’s look at implementing the noise cancellation. Conceptually, there are two ways we could do this. The first is that if we digitize (using an analog-to-digital
EECS 16A, Spring 2015, Homework 6
10
converter or ADC) the signal from the microphone, then in software we could subtract it (after appropriate scaling) from the digital version of our desired audio stream before feeding it in to the DAC.
This however requires us to have access to the original digital representation of the audio and be able
to reprogram the device feeding the DAC, which we may or may not be able to do. In this problem
we’ll therefore focus on implementing the cancellation with the other method, which is to directly take
the (analog) voltage produced by the microphone and subtract it out from the voltage we feed to the
speaker.
Let’s assume that the microphone can be modeled as voltage source with 10kΩ source resistance. The
loudest sounds we will ever pick up with the microphone make the voltage source (before the source
resistance and any voltage drop associated with it) that swings between 0V and 1V (relative to the same
DAC ground). Note however that because the materials in the headphones attenuate some of the sound
waves coming from outside of it, this loudest signal picked up by the microphone should correspond
to a voltage of only −125mV to +125mV driven on to the speaker.
Expand the circuit from a) to take the signal from the microphone and subtract it out from the signal
that will be driven on to the speaker. You can use op-amps and resistors to do this, but no new voltage
sources (except for the model of the microphone of course). Note however that since our speaker driver
now needs to handle both the cancellation and the desired audio signal, you can assume that the supply
voltages fed to the op-amp have sufficiently large magnitude to ensure that they never clip (reach the
power rails). In other words, you can continue to assume that you have +/ − 1.5V voltage sources
available to use in the rest of your circuit, but that the op-amps are supplied by a separate set of voltage
sources (e.g., +/ − 2.5V , although you may not need that high of a voltage to make everything work).
Solutions: First we need to shift the range of the microphone voltage such that it centers around 0V .
We can use the technique from part (a), using a voltage divider but with a source resistance of 10kΩ.
Applying a similar thought process as part (a), we realize from problem 1 that connecting a signal to
the non-inverting input of an op-amp scales and adds the signal at the output while connecting a signal
to the inverting input of an op-amp scales and subtracts the signal at the output. The easiest way to
build our circuit is then to use two copies of the circuit in part (a), then feed both outputs to a buffer
through resistors so we have a small output resistance. Instead, here we try to combine the circuits to
just use 1 op-amp.
We have to somehow feed this voltage to the inverting input of the op-amp so we can subtract the
voltage (just like an inverting amplifier, the new input has to be connected to the inverting input of
the op-amp). We can just sketch this circuit and see if this works. Note that the rails of the op-amp
has to be greater than the output voltage range, which in this case is 1.5V + 0.125V = 1.625V (which
happens when VDAC = 1V and Vmic = 0V ).
EECS 16A, Spring 2015, Homework 6
11
> 1.625V
50Ω
−
+
VDAC
Vin
+
Vspeaker
−
150Ω
8Ω speaker
< −1.625V
R2
−1.5V
−
+
Vmic
Rs =10kΩ
R3
R1
−1.5V
Since Vn = Vp = Vin , we can write KCL at the inverting input node,
Vmic −Vin −1.5 −Vin 0 −Vin Vspeaker −Vin
+
+
+
=0
Rs
R3
R1
R2
Vmic gs −Vin (gs + g1 + g2 + g3 ) − 1.5g3 +Vspeaker g2 = 0
where gn is the conductance associated with Rn (gn = R1n ). Now we have 3 unknowns (g1 , g2 and g3 ),
so we need 3 equations. From the desired behavior, we want
Vmic
0
1
0.5
Vin
0.375
0.375
0
Vspeaker
1.625
1.375
0
The first line says when the DAC voltage is the highest and the microphone voltage is lowest, we want
the highest output (1.5V + 0.125V ). The second line says when the DAC voltage is the highest and the
microphone voltage is highest, we want 1.5V − 0.125V = 0.375V in the output. Lastly, if the DAC is
in the middle and the microphone voltage is also in the middle, we want 0V in the output. We can now
construct a matrix equation from the equation we derived.

   

−0.375 1.25 −1.875
g1
0.0000375
−0.375
1
−1.875 · g2  =  0.000275 
0
0
1.5
g3
0.00005
To solve for the conductances, it is important to have an invertible matrix. If it is not invertible, try
using different cases. For example, if we just use the both maximum inputs, both middle inputs and
both minimum inputs, we will get a matrix that is non-invertible. Taking the inverse and multiplying,
we get
  

0.0011
g1
g2  =  0.0004 
g3
0.0000333...
and R1 = 6kΩ
R2 = 2.5kΩ
EECS 16A, Spring 2015, Homework 6
R3 = 30kΩ.
12
(c) So far we’ve had just one speaker and one microphone, but almost all headphones today have two
speakers (one for each ear - i.e., stereo sound). Adding an extra speaker that can be driven by a
separate audio stream typically makes things sound better (more real) to us, and for similar reasons,
if we can use that information in the right way, having more than one microphone to pick up ambient
sounds from multiple different locations can help us do a better job of cancellation.
Let’s now assume that our system has 3 microphones and 2 speakers, and that the source of our audio is
stereo - i.e., we have two different audio streams sle f t and sright (produced by two different DACs) that
represent the ideal sounds we would like the user to hear in their left and right ear. Let’s call the three
audio signals picked up by the microphones smic1 , smic2 , and smic3 , and let’s assume that without any
active noise cancellation, some fraction of the signal picked up by each microphone would be heard
by the user in each of their ears. For example, a1le f t would represent the fraction of the signal of the
signal picked up by microphone 1 that will be heard in the user’s left ear, a2right would represent the
fraction of the signal picked up by microphone 2 that will be in the user’s right ear, etc.
Still assuming no noise cancellation and assuming that the DAC/driver circuitry is ideal in producing
sle f t and sright , write a matrix-vector equation you could use to calculate the audio signals sear_le f t and
sear_right heard by each of the users ears.
Solutions: We can represent the matrix multiplication by y = Ax. Let’s do a quick dimensional
analysis. The vector y is our output, and it is a 2-by-1 vector. The vector x is our input, and it is a
5-by-1 vector. Thus A has to be a 2-by-5 matrix. Now we can write a system of equations that relates
the outputs to the inputs:
sear_le f t = sle f t + a1le f t smic1 + a2le f t smic2 + a3le f t smic3
sear_right = sright + a1right smic1 + a2right smic2 + a3right smic3
We can thus represent this as the matrix multiplication and addition below.


s
sear_le f t
a1le f t a2le f t a3le f t  mic1 
sle f t
=
· smic2 +
sear_right
a1right a2right a3right
sright
smic3
EECS 16A, Spring 2015, Homework 6
13
Note: Due to ambiguity in the problem, we will accept any answer that is conceptually correct (i.e.
sle f t and sright can be in the vector multiplied by the matrix, but not inside the matrix itself).
(d) If we define the matrix that related the signals picked up by each of the microphones to the signals heard
by each ear as A, what matrix B should the active noise cancellation circuitry be aiming to implement
in order to ensure that the user doesn’t hear any of the sounds picked up by the microphones?
Solutions: The system we want to implement can be represented as below:




smic1
smic1
s
sear_le f t
le
f
t
= A smic2  + B smic2  +
sright
sear_right
smic3
smic3
If we define the matrix B as the matrix used to produce a signal to be added to the DAC signal, then we
have B = −A. If we define the matrix B as the matrix used to produce a signal to be subtracted from
the DAC signal, then we have B = A, with A from part (c).
(e) Using resistors and op-amps and assuming that the microphones can be modeled as voltage sources
with a series resistance of 1kΩ and whose value vmicn is proportional to smicn (i.e., vmicn = k · smicn ),
design and sketch a circuit that would implement the cancellation matrix B. Since the circuit is electrical and deals with voltages (not sound waves), you should assume that this circuit has three voltage
inputs vmic1 , vmic2 , and vmic3 (corresponding to the signals picked up by the microphones) and two
voltage outputs vcancel_le f t and vcancel_right (corresponding to the voltages that will be subtracted from
the desired audio streams in order to cancel the externally-produced sounds). Note that in order to
simplify the problem, you can assume that all of the vmic voltages are centered at 0V (relative to the
DAC ground).
Solutions: Since we want to subtract vcancel_le f t and vcancel_right from the audio stream output, we
want these values to be
vcancel_le f t = a1le f t vmic1 + a2le f t vmic2 + a3le f t vmic3
scancel_right = a1right vmic1 + a2right vmic2 + a3right vmic3
Following the design process, we can draw a block diagram for the circuit.
We can see here that the two channels are actually independent from each other. The only point they
meet is the microphone voltage. Thus, we can start by designing for one channel.
We want to build a circuit that adds its inputs. We have seen a circuit that does this in problem 1(c), but
EECS 16A, Spring 2015, Homework 6
14
there we only had 2 inputs and we need 3 here. We have also seen in part (b) that we voltage divider by
itself in the non-inverting input has can be used to add signals. Thus, we can start from a very simple
circuit below.
R1
vmic1
R2
vmic2
vout
R3
vmic3
Writing a KCL at the output node, we have
vmic1 − vout vmic2 − vout vmic3 − vout
+
+
=0
R1
R2
R3
vout =
vmic1 g1
vmic2 g2
vmic3 g3
+
+
g1 + g2 + g3 g1 + g2 + g3 g1 + g2 + g3
where gn = R1n . This looks like a good start!
If we are trying to build the left cancellation voltage, then the coeffecient of vmicn should be anle f t .
However, if we add all the coeffecients in the equation above,
a1 + a2 + a3 =
g2
g3
g1 + g2 + g3
g1
+
+
=
=1
g1 + g2 + g3 g1 + g2 + g3 g1 + g2 + g3 g1 + g2 + g3
Thus this circuit has a constraint on the values of a we can choose - not good! We need to think of a
tweak that lets us choose a arbitrarily. Here’s an idea: what if we put a dummy input that is tied to
ground? We saw that the total of the gains must equal to 1, so if we have a dummy input we can set
all of the gains to be anything as long as the total is less than 1. We have also seen that whenever we
have a voltage divider we are only dealing with ratios of the resistances. Thus, we can put the three
resistors we have right now in terms of our new resistor.
αR
vmic1
βR
vmic2
vout
γR
vmic3
R
Let’s rewrite the KCL at the output node.
vout
vmic1 − vout vmic2 − vout vmic3 − vout 0 − vout
+
+
+
=0
αR
βR
γR
R
1 1 1
vmic1 vmic2 vmic3
vout
+ + +1 =
+
+
α β γ
α
β
γ
v
g
vmic3 gγ
vmic1 gα
mic2 β
+
+
=
gα + gβ + gγ + 1 gα + gβ + gγ + 1 gα + gβ + gγ + 1
EECS 16A, Spring 2015, Homework 6
15
This looks good... but now we can only make the circuit work if the total of the a’s is less than 1.
If we want to pick arbitrary values for a, we cannot have this constraint. How can we achieve this?
The problem is actually simpler than it seems! We have a controllable gain on each of the microphone
voltages and we have added them together, we just need to amplify the sum. We can use a non-inverting
amplifier to do this.
αR
vmic1
βR
+
vmic2
Vout
γR
vmic3
−
R
R1
R2
2
. But what do we want this gain to be?
The circuit we have right now amplifies our last vout by R+1+R
R2
Our assumption is that the a’s are fractions between 0 and 1, which means the sum of a’s is 3. We
have also built a circuit that works if the sum of a’s is below 1. Thus, we need a gain of 3 to cover
all possible values for a. Using the gain formula, we can pick R1 = 2kΩ and R2 = 1kΩ. With the
amplifier, then our output voltage is
vout =
3vmic2 gβ
3vmic3 gγ
3vmic1 gα
+
+
gα + gβ + gγ + 1 gα + gβ + gγ + 1 gα + gβ + gγ + 1
If we want Vout = a1 vmic1 + a2 vmic2 + a3 vmic3 , then
3
α
1
α
+ β1 + 1γ + 1
3
β
1
α
+ β1 + 1γ + 1
3
γ
1
α
+ β1 + 1γ + 1
= a1
= a2
= a3
If we divide the first equation by the second, we get
β
a1
=
α
a2
α=
a2
β
a1
Similarly with the second and third equations,
γ
a2
=
β
a3
EECS 16A, Spring 2015, Homework 6
β=
a3
γ,
a2
so α =
a3
γ
a1
16
Replacing α and β in the third equation,
1 1 1
3 = a3 γ
+ + +1
α β γ
a1 a2
+ +1+γ
3 = a3
a3 a3
γ=
3 − a1 − a2 − a3
a3
α=
3 − a1 − a2 − a3
a1
β=
3 − a1 − a2 − a3
a2
Whew. Almost there. Remember that our microphone voltages have source resistances of 1kΩ. We can
treat this as a series resistance, as part of the resistors αR, β R and γR. However, we need 2 channels
- one for each ear. When we hook a second copy of the circuit up, the node we connect the second
circuit acts as another voltage divider.
Rs =1kΩ
α1 R − R s
to left circuit
−
+
vmicn
α2 R − Rs
to right circuit
This means if the left circuit node in the circuit above is pulled down, there it can affect the right circuit
node by pulling down the voltage divider. Thus, we cannot just hook up the second circuit into the
first. The simplest way to solve this is to use a unity-gain buffer. A buffer would isolate the source
resistance from the actual circuit so we can just connect the circuits for the two channels in parallel
and would output the actual microphone voltage since there is no current coming into the op-amp input
terminals. For each microphone, we need the buffer below.
1kΩ
+
−
+
vmicn
−
vmicn 0 (to circuit)
Now that we have all the building blocks we need, we can construct the two-channel noise cancelling
circuit. vmicn 0 is connected to the output of the microphone buffers. we can choose an arbitrary value
for R, for example 1kΩ.
EECS 16A, Spring 2015, Homework 6
17
α1 R
vmic1 0
β1 R
vmic2
+
0
vcancel_le f t
γ1 R
vmic3 0
R
−
2kΩ
α2 R
1kΩ
β2 R
+
vcancel_right
γ2 R
R
−
2kΩ
1kΩ
α1 =
3 − a1le f t − a2le f t − a3le f t
a1le f t
β1 =
3 − a1le f t − a2le f t − a3le f t
a2le f t
γ1 =
3 − a1le f t − a2le f t − a3le f t
a3le f t
α2 =
3 − a1right − a2right − a3right
a1le f t
β2 =
3 − a1right − a2right − a3right
a2right
γ2 =
3 − a1right − a2right − a3right
a3right
(f) BONUS: Building upon your solutions to parts b), c), and e), and otherwise making the same assumptions about the relative voltage ranges of vmic1 , vmic2 , and vmic3 and available supply voltages as
we made in part b), sketch the complete circuit you would use to create the stereo audio on the two
speakers while cancelling the noise picked up by the three microphones.
Solutions: We already have a circuit that does subtraction from part (b) and a circuit that computes
the noise cancelling signal in part (e). We just have to combine the two circuits such that it implements
the matrix B in part (d). A naive way to do this is to just chain them up together, but we will try to be
EECS 16A, Spring 2015, Homework 6
18
more aggressive and try to only use 1 op-amp for each channel, on top of the microphone buffers. The
block diagram for this circuit is as below.
Going back to part (b), we can see that to add something we have to feed it into the positive input
and to subtract something we have to feed it into the negative input of the op-amp. We can take this
principle and combine the circuits in part (b) and (e). Since we still need to shift the DAC voltages but
do not need to shift the microphone voltages, we can try the circuit below. As we have seen previously,
when we have multiple channels the source resistance becomes a problem. Thus we can use the same
technique as before by using a buffer.
1kΩ
+
EECS 16A, Spring 2015, Homework 6
−
+
vmicn
−
vmicn 0 (to circuit)
19
50Ω
VDAC
vin
+
vout
150Ω
−
RL
R1
−1.5V
α
vmic1 0
β
vmic2
0
R2
γ
vmic3 0
If we take a closer look at the boxed part of the circuit above, we notice that this is actually one of the
circuits we experimented in part (e)! The only difference is in part (e) we wanted to add the inputs so
we connected it to the non-inverting input of the op-amp while here we want to subtract the signals so
we connect it to the inverting input of the op-amp.
Recall that the vin range is −0.375V to 0.375V , and it has to be amplified 4 times. We can write the
KCL equation in the inverting input of the op-amp.
vmic1 − vin vmic2 − vin vmic3 − vin vout − vin 0 − vin
+
+
+
+
=0
α
β
γ
R1
R2
1 1 1
1
1
vmic1 vmic2 vmic3
vout
= vin
+ + +
+
−
−
−
R1
α β γ R1 R2
α
β
γ
R1 R1 R1
R1
R1
R1
R1
vout = vin
+
+
+1+
− vmic1 − vmic2 − vmic3
α
β
γ
R2
α
β
γ
Just as before, we can compare this formula to the output we want. In this case, we want vout =
4vin − a1 vmic1 − a2 vmic2 − a3 vmic3 . Thus,
R1
R1 R1 R1
+
+
+1+
=4
α
β
γ
R2
α=
R1
a1
R1
= a1
α
β=
R1
a2
R1
= a2
β
γ=
R1
= a3
γ
R1
a3
From the first equation,
a1 + a2 + a3 + 1 +
R1
=4
R2
R1
3 − a1 − a2 − a3
Thus, if we pick a value for R1 , we can use the formulas above to calculate α, β , γ and R2 .
Now that we have a working circuit for one speaker, we can duplicate this circuit to have two speakers.
Notice that in the circuit below we can use the same value for R1 in the two channels, but we have to
keep R2 as a variable (hence it is replaced with R3 in the right channel). This is because R1 is a free
variable. If we choose a value for R1 arbitrarity, we can calculate what the other resistor values have
to be with the equations we have derived.
R2 =
EECS 16A, Spring 2015, Homework 6
20
50Ω
+
VDAC,le f t
vcorrected_le f t
−
150Ω
8Ω speaker
R1
−1.5V
α1
vmic1
0
vmic2
0
β1
R2
γ1
vmic3 0
50Ω
+
VDAC,right
vcorrected_right
−
150Ω
8Ω speaker
R1
−1.5V
α2
β2
R3
γ2
We have seen that if we choose values for R1 and R3 arbitrarily, we can find the other resistor values.
α1 =
α2 =
R1
β1 =
a1le f t
R1
a1right
β2 =
EECS 16A, Spring 2015, Homework 6
R1
a2le f t
R1
a2right
γ1 =
γ2 =
R1
a3le f t
R1
a3right
R2 =
R1
3 − a1le f t − a2le f t − a3le f t
R3 =
R1
3 − a1right − a2right − a3right
21