editorial editorial

Dr. Martin Bader, Executive Vice President, Unaxis Semiconductors
and President Unaxis North America
Dear Readers
Welcome to this new edition of Chip! I hope you had a good start to 2002 and that
this year will be successful for all of us!
The past year was tough on our industry and no one has escaped unscathed.
Unaxis Semiconductors is no exception, as revenues were below original expectations.
However, we still remained profitable with sales close to 2000 figures.
The market situation has not been favorable but appears to have bottomed out now.
I believe the first two quarters in 2002 will be challenging, but we anticipate the upswing
in the second half of the year. In the meantime, our efforts are concentrated fully on
R&D and further quality improvement of our products and services.
Despite difficult market conditions, Unaxis Semiconductors did not reduce its R&D
editorial
editorial
budget last year. On the contrary, a substantially higher amount was allocated to R&D
in 2001. Our focus lies on new 300 mm products like the CLUSTERLINE® 300 (p. 47),
the new LEPP 300 (p. 27), and a completely new system for the advanced packaging
market that will be presented in the next edition of Chip. Unaxis investments will reach
record levels in 2002 – mainly to improve laboratory facilities, and for construction of
a new manufacturing cleanroom in Truebbach, Switzerland.
The MEMS market seems to be expanding in the automotive and computer peripheral
industries, while entering a more active phase particularly in the telecommunications
and biomedical fields. In response to the current active interest in this subject, a whole
section of this issue of Chip has been devoted to this technology (p. 8 – 21).
The new Quality Management System is ready (p. 4) and Unaxis Semiconductors
is preparing for the ISO 9001 re-certification at the end of February in Truebbach. All
Unaxis Semiconductor sites worldwide will be ISO-certified by the first quarter of 2003.
Following last year’s customer opinion survey, some significant improvements are on
the way, especially in the area of customer relationship management and the sales and
service organization (p. 6).
I hope that you find Chip 6 informative and a pleasure to read, and we welcome
your feedback (see Reply Card p. 46, or [email protected]). On behalf of Unaxis
Semiconductors, I wish you enjoyable reading.
Dr. Martin Bader
Unaxis Chip
8
Unaxis Insights
The Making of a Worldwide
Quality Management System
Creating Customer Value
Lab on a CD
Microlaboratories on
a standard CD form
factor could be used
to run laboratory
processes (image:
GyrosMicrolabs).
Combining the power of sales and service
Events
4
6
57
Telecom
Mad about MEMS
New growth for the semiconductor industry
8
contents
contents
Asia Pacific Microsystems
Chip Unaxis
20
Scanning electron
microscope picture
of a test structure for
arrayed waveguide that
shows the patterned
SiO2 fibers fanning out
from a common
input/output channel.
The MEMS pioneer in Taiwan
12
MEMS Technology for Telecommunication
A massive increase in the demand for more bandwidth
speeds up development.
14
MEMS – a Playground for
New Thin Film Materials
17
Unaxis Supports DWDM with PECVD and RIE
DWDM (Densed Wavelength Division Multiplexed)
will provide the solution for unlimited bandwidth.
20
Dry Etching InP for Multiple Applications
New etching systems can accommodate
numerous applications.
22
24
The Unaxis SIRIUS
UHV-CVD system
®
The extention of the CLUSTERLINE 300 concept
for PECVD processing
30
27
Customer-Oriented Process Development
for SiGe Deposition
Outlining the advantages of the SIRIUS UHV-CVD system
for deposition of HBTs and other SiGe/Si structures
41
30
New Trends in SiGe Technology
Carbon-doped heterojunction bipolar transistors –
enhancing the capability of SiGe technology
Motorola
Accompli™ 009
New wireless devices
for the end user market
would allow products
like web tablets,
wearable computing,
or telematic devices to
become as common in
our daily lives as mobile
phones are today
(image: Motorola).
33
The Photomask Success Story
Recent introduction of the new Unaxis MASK ETCHER IIITM
ICP dry etch system caused a revolution in the global
photomask industry.
36
Non-volatile Memory: the Key to
Advanced Memory Devices
FRAM, MRAM, and OUM – which memory technology
will win the day?
41
Money for Nothing … and Chips for Free
Reducing initial target costs and increasing material
utilization on the Unaxis CLUSTERLINE®
45
47
Advanced Packaging
CLUSTERLINE® – Making 300 mm Possible
The transition to 300 mm wafer processing
has been accomplished.
47
The Advantages of Integrated Passives
IPDs (Integrated Passive Devices) are a booming area
of advanced packaging.
51
APiA – the New Alliance for
Advanced Packaging Solutions
55
contents
contents
Advanced Silicon
LEPECVD Provides High-Quality Virtual
Substrates for Ge-rich SiGe p-MOSFETs
LEPP 300
CLUSTERLINE® 300
The new Unaxis
CLUSTERLINE® 300
is being implemented
in the first 300 mm
wafer bumping fab
of one of the world’s
largest providers
of semiconductor
packaging and testing
services.
Unaxis Chip
Unaxis Insights
Creating Customer Value
Combining the Power of Sales and Service
Ernst Gloor (left) and Ralf Kuhlmann (center)
have been interviewed by Jürg Steinmann,
Global Communications Manager Unaxis
Semiconductors.
interview
interview
Chip interview with Ralf Kuhlmann,
International Sales & Market Manager, and Ernst Gloor,
General Manager Customer Support
6 | Chip Unaxis
Chip: Mr. Kuhlmann, in September
2001, you have taken on a new
challenge. You are now responsible
for the global Sales & Service
organization of the Semiconductor
Division of Unaxis. What is your
analysis after the first six months?
Kuhlmann: The time has passed
incredibly quickly and a lot has happened.
When I started, the market situation was
really challenging, to say the least: a lot
of quick decisions had to be taken. This
led to decisive action within our Sales
& Service Organization.
Facing the volatile state of the current
market situation, we need to increasingly
concentrate on our strategic market
segments, core activities, and our own
strengths.
I see potential for improvement in
the partnership with our customers.
Individual customer care will receive our
special attention. The Sales & Service
Organization needs to be much more
conscious of its leadership role in
customer relationship management.
Chip: Have there been major
changes already?
Kuhlmann: The most obvious change
is also reflected in this interview situation:
we now feature as a “double pack”.
We have taken a clear decision to manage
sales and customer support as one
organizational unit. We are convinced
that this is the only way to give our
customers the full benefit of the synergies
between all sales and customer support
activities.
Gloor: We have already started the rollout
of the system sales and customer support
processes defined by our Business
“The Sales & Service Organization
needs to be much more conscious
of its leadership role in customer
relationship management.”
Excellence Model (see article on page 4).
This has already led to visible results in the
regional organizational structures and in
our sales and service operations.
Leaner structures have been
established in some market segments,
like the USA and Europe. A good
example is the central coordination
and steering of the service teams with
regional responsibility. At the same
time, our hotline and the availability of
sales and service – in particular our
reaction time for emergencies – will be
further improved. Our service contracts
with customers in the USA and Europe
guarantee around-the-clock availability.
The experiences from these two markets
will also be applied to the Asian markets
at a later date.
interview
interview
“I found a strong, highly motivated team,
and we are well positioned in most market segments.”
sales support will be coordinated globally.
The product groups will be actively
involved and provide strong backup for
the internationally acting KAM. Only by
setting such clear responsibilities, we
can insure total customer care and that
resources are shared efficiently. The global
KAM teams will have increased business
responsibility and act as the interface
between customer, product groups,
supply chain, and logistics.
Closer customer relationship
쐍 Global Key Account Managers
for each customer plus
dedicated Lead Engineers
쐍 Flexible and efficient sales and
service teams who work
closely with our customers
Enhanced level of service
쐍 24 h hotline in Europe and
the USA based on a service
contract, implementation
in Asia at a later date
쐍 Higher competence of the
sales and service specialists
through intensified product
and process cross-training
Chip: How will this affect customer
relations, and how will the customer
and market management develop
in the future?
Kuhlmann: In addition to our existing
systems and project business, we will
re-focus strongly on Key Account
Management (KAM). From now on, the
previously mostly regional customer and
Gloor: We have taken on the challenge
to supply the complete service chain
as a one-stop solution provider for
semiconductor technologies: from
consulting and project planning to the
implementation of complex process and
manufacturing lines. Our new Key
Account Management needs to be well
prepared to fulfill this central role.
Together with the introduction of
the KAM, Lead Engineers are being
appointed to cover technical support
at the customer location.
Chip: What are the next steps?
Kuhlmann: The operational business
processes are still too complex in some
areas and not always focused on the
needs of our customers. Here, we need
to simplify systematically to increase
our efficiency.
We are clearly dedicated to Business
Excellence according to ISO 9001/EFQM
and need to continually work on
improvements. Our benchmark can only
be the top performers in our markets.
I found a strong, highly motivated team,
and we are well positioned in most market
segments. We know the demands put
upon the teams of our Sales & Service
Organization and what a great job they
already do. Our task will be to create an
environment for independent, self-reliant
decision making, and a culture of
empowerment. A better use of existing
communication, information and
management tools will be a prime focus.
Gloor: Classic field service will be
extended considerably. As part of a
service package, we will also offer our
customers the possibility of having their
Unaxis parts supply managed directly at
their own premises. Thus, Unaxis insures
that parts and consumables in stock are
tailored exactly to the customers’ needs.
The improved parts supply management
will help achieve a higher up-time of
installed systems.
A recently conducted customer
satisfaction survey confirms our decision
to take this route. The response from our
customers also clearly shows the areas
where we need to improve. We at Unaxis
consider this a unique opportunity to
come to the best possible solution –
together with our customers.
Markets
service
parts
training
product portfolio
sales & market
strategies
Global
Sales
KAM
(Key Account Mgmt.)
CRM
(Customer Relationship Mgmt.)
Customer
Support
installation
Product
Groups
Unaxis Chip | 7
Telecom
Mad about MEMS
New Growth For Semiconductor Industry
Lab on a CD
Microlaboratories on a standard CD form factor
could be used to run routine or non-routine
laboratory processes. Hundreds of samples can
be processed in parallel on the disposable CDs
(image: Gyros Microlabs).
MEMS Defined:
Micro Electro Mechanical
Systems. MICRO indicates
that these systems are very
small. They have micronsized features. ELECTROMECHANICAL suggests
motors, pivots, links, switches,
gears, and actuators.
SYSTEMS suggests a set of
functions related to a goal or
purpose. MEMS are used to
sense and manipulate the
physical environment by
responding to various kinds
of input – chemical, light,
pressure, vibration, and
acceleration.
Valerie Thomson, Technical Journalist, Zurich
Tiny, low-power hearing implants,
miniature test tubes – so small that an
entire laboratory can fit on a postage
stamp-sized piece of glass, cheap
sensors that detect hazardous chemical
agents, and chip-sized packaging for
devices that contain thousands of tiny
mirrors to switch telephone traffic at the
speed of light are some of the systems
being developed that exploit Micro Electro
Mechanical Systems (MEMS) technology.
MEMS is being used in a much wider
range of industries than expected.
Historically, MEMS use was limited to
8 | Chip Unaxis
the automotive industry, such as actuators
for airbags, or to the computing peripheral
sector, such as inkjet printer heads and
storage devices.
In the past few years, using materials
such as ceramic, plastic, metals, quartz,
and even diamonds, engineers are
moving the use of MEMS beyond its
current niche markets. The technology
is increasingly being used by the
telecommunications equipment industry
where makers of optical switches, tunable
lasers, attenuators and filters see MEMS
as a cost-efficient solution in the field of
optical networking. Sercalo Microsystems
of Liechtenstein, for example, sells
carrier-grade MEMS-based devices
for use in optical switches, while
Switzerland’s Sysmelec SA is making
automation tools for assembling optical
components, and Colibrys SA is
automating production for its high-quality
optical MEMS components.
The fast-growing biomedical sector is
also proving to be a market for MEMS
technology. New implantable devices are
of great interest for treating specific
diseases (e.g. chronic pain and
Parkinson’s). Micromachined components,
with their small size and low power
consumption, are ideal in this application.
Companies such as Medtronic
(Minnesota) are working on implants
for treating vascular disease, tremors,
and neurological conditions.
Plastics vendors, for example, are
already prototyping biochips created
using the same nozzle plates used to
make inkjet printers. Prototypes exist,
created by the likes of Applied
MicroSWISS, such as grippers, tweezers,
saw blades, and plane iron tools. Such
tools enable things like minimal invasive
surgery, making recovery faster and safer
for patients undergoing operations.
Even household names, such as
Electrolux-AEG, Bosch, Siemens,
Whirlpool, Bauknecht, Miele, and Philips,
are working with MEMS vendors to make
smarter and more efficient appliances.
Semiconductor industry’s know-how
in demand for MEMS
The micromachining industry got its
first hint of a bigger and alternative
market to its traditional integrated circuit
or semiconductor market back in the
seventies when bulk-etched silicon wafers
were used to produce pressure sensors.
Then came the demand for polysilicon
actuators used in hard disk drives.
The semiconductor industry is seeing
its know-how and much of its capital
equipment being exploited in ways
that it had not imagined as existing
microelectronics manufacturing processes
and infrastructure are used to enable mass
fabrication of MEMS. For example Karl
Suss, who used to generate most of its
revenue from the semiconductor industry
but has now become a major supplier
to the MEMS industry.
Semiconductor industry giant Analog
Devices began supplying accelerometers
to the auto industry because it had
the right combination of expertise and
manufacturing capacity. It now leads
that market, while other semiconductor
industry players, Motorola, VTI Hamlin,
and Sensanor, share the rest of a market
estimated to be about half a billion dollars
this year.
It should be noted however that
MEMS processes are more demanding.
Indeed, lithography performance is more
advanced than is customary for an IC
foundry, points out Eric Mounier of Yole
Developpement of Lyons, a company that
has just published a report about MEMS
manufacturing, entitled FABEurope.
At the end of 2000 in Europe there were
8 MEMS-specific foundries, 7 integrated
optics foundries, and 4 wafers foundries
announced or extended, according to
Yole Developpement. Including integrated
optics and wafers, along with MEMSrelated foundries, there are more than
150 foundries in Europe, as Yole’s
research shows.
Because of the limited availability
of MEMS foundries, however, major
equipment manufacturers, especially in
the telecommunication sector, have been
buying such foundries to ensure product
supply; for example, Alcatel acquired the
Scottish MEMS foundry, and Kymata and
Analog Devices acquired the Irish MEMS
maker BCO Technologies.
MEMS foundries, like semiconductor
foundries, can be more cost-effective
than internal manufacturing, but MEMS
foundries are constrained by a need to
be highly flexible and expandable. A
standard IC foundry performs one or two
standard processes, but a MEMS foundry
performs a wide variety of processes,
such as bulk, surface, and nontraditional
processes.
“Every foundry has its own particular
way of making MEMS, using different
materials and different processes, and
although there are plenty of foundries, not
all have the capability of making MEMS
for all applications – from biomedical to
telecom applications. Typically, in Europe,
MEMS facilities concentrate on a limited
number of MEMS products for different
markets,” says Yole Developpement
strategist, Eric Mounier.
About 80 percent of the processes
come from semiconductors and 20 percent
are unique to MEMS (Table 1). Four
semiconductor processes are in use for
MEMS production today. MEMS specific
Accelerometer
One of the latest
accelerometer
systems, including
ASIC, sensor and
MEMS packaging,
used in car airbags
(image: Colibrys)
Table 1: Overview of selected MEMS
manufacturing processes
Manufacturing Techniques
Products
Surface
micromachining
IC semiconductors
Actuators and electrostatic motors
Bulk
micromachining
Etch techniques
Mirrors and accelerators
for airbags
Electro discharge
micromachining
Machine shop
techniques
Conductive materials
LIGA
Lithography
and electroplating
Electrostatic motors
and gears, telecoms,
and defense sector
Unaxis Chip | 9
Optoelectronics for
telecommunications
Telecommunications
equipment manufacturers
are experimenting with
optoelectronics devices
with shutters for highspeed fiber-optic switches
(image: Colibrys).
processes include bonding two wafers
together, deep reactive ion etching (DRIE)
that can etch completely through the
wafer, aligning a wafer on the backside in
addition to the front side, building
structures on quartz as well as silicon
wafers, and deep anisotropic wet etches
using such etchant chemicals as KOH
(potassium hydroxide), TMAH (tetramethyl-ammonia-hydroxide), or EDP
(ethylene-diamine-brenzkatechinpyrazine).
Today the amount spent on research
and development (R&D) is still small
compared to IC industry R&D. But
recent press announcements suggest
that a larger array of MEMS products
are moving into production. Many of the
packaging and testing hurdles are being
addressed by industry and the research
institutions that work with industry.
An industry roadmap, similar to that of
the semiconductor industry, is being
developed, and a number of organizations
are being formed to commercialize MEMS.
The future of MEMS
MEMS as a mass market technology
still has to mature. Two efforts underway
in the industry to standardize and to
come up with inexpensive methods of
10 | Chip Unaxis
packaging MEMS will do a lot to expedite
and propel the growth in the uptake of
MEMS. Although MEMS is a relatively
new technology area, the benefits of
common standards for everything from
documentation to packaging will go far
to create economies of scale and ease
of trade.
Packaging advances are also required.
It is the single most expensive and timeconsuming task in overall MEMS product
development.
As a market, MEMS is highly
fragmented, which is also a sign of
immaturity. While the supply-side can
boast of supply-chains established in
Europe, the US, and East Asia, the
demand side is extremely diverse. There
are a number of niche-like, fast-growing
MEMS product lines.
The annual compound growth rate
for MEMS, is estimated to be between 26
and 50 percent over the next five years by
groups such as the MEMS Roadmapping
Association and NEXUS. Clearly, MEMS
devices are going to impact a range of
industries during the next few years, but it
is important not to over-hype these tiny
devices. “On the whole, MEMS products
are disruptive for the biochip, for example,
which is clearly a threat to those who
manufacture more traditional laboratory
testing equipment” as Roger Bischofberger
of Applied MicroSWISS points out. Such
discontinuous innovations, as they are
called by the market analysts, take a lot
longer to become a commercial success
(Table 2).
Steve Walsh, an expert on MEMS, says
that there is invariably a time lag between
the discovery of a new technology and
its deployment in commercial systems.
His research (Table 3) is helping to inform
Table 2: MEMS markets and applications
Market
Applications
Communications
쐍 Cross-connects inside optical switches
based on micromirrors and other MEMS
쐍 Optical attenuators
쐍 Tunable filters
쐍 Tunable lasers
Military
쐍 Munitions guidance
쐍 Surveillance
쐍 Arming systems
쐍 Embedded sensors
쐍 Aircraft control
쐍 Inertial systems used in unmanned vehicles
and flight systems
Info Tech
쐍 Data storage magneto-resistive (MR) tape heads
쐍 Tiny micro-magnets for non-volatile memory
쐍 Inkjet printers
쐍 Rear-projection screen TVs
Biomedical
쐍 DNA amplification
쐍 Polymerase Chain Reaction (PCR)
쐍 Biochips for detection of hazardous chemical
and biological agents
쐍 Microsystems for high throughput screening and
selelction – hybridization chips or genosensors
쐍 Biochips for DNA analysis
쐍 Microfluidic chips used as diagnostic devices
where one drop of blood can be tested for
a whole range of diseases
Medical
쐍 Blood pressure sensors
쐍 Muscle stimulators
쐍 Drug delivery systems
쐍 Pacemakers
쐍 Prosthetics
쐍 Implanted pressure sensors
Automotive
쐍 Internal navigation systems
쐍 Air-condition compressor sensor
쐍 Intelligent tires
쐍 Airbag sensors
쐍 Fuel level and vapor pressure sensors
쐍 Brake force sensors and suspension control
accelerometers
쐍 Accelerometer
Other
쐍 Earthquake sensors
쐍 Avionics pressure systems
Magnetic printing heads
High-speed, high throughput
devices deliver toner to paper
without de-magnetizing the ink,
making it perfect for secure
paper documents in the banking
industry, such as personalized
cheques (image: Colibrys).
Valerie Thompson
MSc., has been a
freelance business and
high-tech writer for more
than 10 years.
A Canadian based
in Zurich, she tracks
the trends and
developments of
Europe’s purveyors of
advanced technology.
Table 3: Time to full commercialization for selected MEMS products
the roadmapping efforts of the MEMS
industry.
MEMS technology has finally entered
a rapid growth phase, according to Frost
and Sullivan’s Technical Insights, and
the market is expected to quadruple by
2004. Telecommunications use of MEMS
is slated for growth. MEMS-based
variable optical attenuators, tunable
filters, and tunable lasers have expanded
the market beyond switches. The
telecommunications segment is expected
to increase by more than 30 percent of
the total MEMS market in 2005, according
to Frost and Sullivan. Sensor sales
currently lead the market, but actuator
sales will far outpace them by 2005.
MEMS chips for rear projection TVs
will enjoy an expanding market share,
says Stanford Resources, a market
intelligence services firm focusing on
the global electronic display industry.
MEMS technology is of critical
importance to the growth of other cutting
edge areas of science and technology.
Scientists are increasingly using MEMS in
experimental genomics and proteomics
systems to help them characterize
and analyze things at the molecular
level. Furthermore, scanning tunneling
microscopy, the key enabling technology
for nanotechnology, exploits MEMS.
Without MEMS there would be no
scanning tunneling microscopes, and
without these microscopes there
would be no nanotechnology.
Product
Discovery
Product evolution
Full commercialization
MEMS pressure and flow sensors
1954
1960
1990 to present
Accelerometers
1974
1985
1998
Gas sensors as used in
process controls
1986
1994
2005
Micro injector nozzles
e.g. fuel nozzles for engines
1972
1984
1998
Optical waveguide sensors
1980
1986
2004
Biochemical microfluidic systems
for remote testing
1980
1986
2004
Rate sensors as used in radars
and gyroscopes
1982
1990
2002
Chromatography, e.g. gas
conductivity detection
1975
1980
2001
Source: from a chapter in MEMS 2000, a book in-progress by Steve Walsh, a SPIE publication
Table 4: MEMS market hurdles
Automation of manufacturing process
Highly fragmented market
In the latter half of 2001, announcements on both sides
of the Atlantic suggest that micro-assembly systems for
manufacturing and checking the dimensions of microsystems
and microcomponents will be in use. But there is plenty
of opportunity for more automation.
MEMS is a technology that can be applied to a highly diverse
range of devices. How do MEMS foundries approach a market
that includes Procter and Gamble, surgeons in a hospital in
Brussels, and tool and die makers in the Czech Republic.
New commercialization organizations will help to segment
the markets and develop channels to market. There is room
to improve.
Process analysis
Quality control standards
Today, the development of most MEMS devices still requires
a dedicated research effort directed at formulating a suitable
fabrication sequence. An interface which separates design
from fabrication allowing the designer to use processindependent design tools and methodologies will reduce
the amount of time and effort required to successfully
realize MEMS devices, say the experts.
Frequently, the quality of many MEMS devices fabricated
at either academic or commercial facilities is low. Part of the
problem is that the technology is so new that the fabricators
have not yet understood how to define quality, much less
measure it.
Packaging
Human resources
Every time a new MEMS device is developed, a new
and specialized package has to be designed. It is a huge
engineering effort to package 3-D devices. Efforts are being
made to overcome this hurdle. Researchers, as well as
vendors, in Europe have recently announced new products
and systems that begin to overcome this issue.
The need for trained engineers and designers is strong.
Working with MEMS requires knowledge of the potential of
microsystems technologies and techniques. Innovators will
require education and training or at least a very good
consultancy class in order to fully exploit MEMS in fields such
as biomedical devices, telecom, and household appliances.
Source: Proceedings “Mikrotechnik and Mikrosystemtechnik in der Telekommunikation”, NTB Buchs, 2001
Unaxis Chip | 11
Telecom
Asia Pacific Microsystems –
the MEMS Pioneer in Taiwan
Dr. Gordon Shyu, Vice President and Sales & Market Manager
Greater China, Kevin Chen, Sales & Service Manager Unaxis
Semiconductors Taiwan
Two key persons were instrumental in
starting up APM: CEO Prof. M. S. Lin and
CTO Prof. Star Huang.
Prof. M. S. Lin has been with the
Industrial Technology Research Institute
for more than 20 years. He is proud to
have started up new organizations in the
ITRI, such as the Opto-Electronics and
System Laboratories. They are now the
most important source for technology
know-how and serve as a reservoir of
professionals for the opto-electronic
industry in Taiwan. Later, he again
pioneered the industry, this time with a
company rather than a research institute.
MEMS technology was his choice.
Prof. Star Huang has been working
in the research of MEMS technologies for
more than 20 years. The quantity and
quality of his publications have made him
one of the most respected professionals
in this field. His dream is to make MEMS
a reality for mass production.
Both Prof. Huang and Prof. Lin
have been colleagues in the Electrical
Engineering Department at the National
Tsing-Huang University since the late
1970s. They knew their interests were
perfectly aligned and have been doing
market research until 2000. They agreed
12 | Chip Unaxis
that it was about time to start
communication with big industry players
and venture capitalists. In July 2001,
Prof. Lin left his position of Executive
Vice President at ITRI and set up APM
together with Prof. Huang.
Size, technology and business model
Currently, APM is located in the open lab
within ITRI. At the moment, more than fifty
people are employed there: 80% of them
engineers, about half of whom are R&D,
and the rest work in production,
application, and quality. The headcount
of course is still growing, particularly
for the non-R&D departments. APM will
have approximately 70 employees at the
beginning and 300 at the end of 2002,
when Asia Pacific Microsystems is
planning to be up and running with their
first line of about 60’000 wafers /year
in Hsin-Chu.
Dr. Star R. S. Huang
(left), CTO of
Asia Pacific
Microsystems,
and Dr. Henry Chen,
Vice President of
the APM production
division
A visit to APM.
From left to right:
Kevin Chen,
Sales & Service
Manager Unaxis
Semiconductors
Taiwan; Albert Koller,
General Manager
of Unaxis Compound
Semiconductors
Europe; Dr. Huang
and Dr. Chen from
APM; Dr. Gordon
Shyu, V. P. and Sales
& Market Manager
Greater China
N . K O R E A
Tokyo
Beijing
Seoul
S . K O R E A
J A PA N
C H I N A
Taipei
universities. They are working towards
partnerships with some RF system and
packaging houses.
APM plan to do foundry service for
customers, which will differ from IC
foundry models since MEMS technology
variation is so large that so far there is no
standard process flow as exists for CMOS
ICs. It will be more like a co-development
model with customers. APM take
customers’ concerns in intellectual
property protection as top priority,
therefore they will make the foundry
process different from their own product
lines to avoid any possible ambiguity.
The first foundry candidate could be the
optical switch technology, but the detail
is still under development.
TA I W A N
Hong Kong
P H I L I P P I N E S
APM’s first line is dedicated to R&D
and small volume production. The smaller,
semi-auto 6" wafer line will be similar
to an IC fab some ten or fifteen years ago.
APM are not quite sure yet whether a
direct transfer of all IC fab methodologies
into MEMS fab is plausible. The
technology maturity, the market scale,
and the business visibility are different.
Experiences with their first line will provide
APM with the necessary information
and database to set up the second line
of about 200’000 wafers/year in 2004.
The business model will be primarily
focused on their own brand products.
The first priorities are
쐍 sensor technologies for the automotive
industry, sampling is expected in
mid-2002,
쐍 RF MEMS technologies for wireless
communication, sampling is expected
at the end of 2002.
APM will develop these two technologies
on their own at APM and pursue various
R&D projects together with ITRI and
Expectation from equipment suppliers
Due to the low technology maturity,
all MEMS process modules are verified
only on R&D tools in a laboratory.
It is challenging to select the right mass
production tools and processes,
particularly as some tool track records
are only from IC, LCD, CD-ROM, or other
applications. The field data for MEMS,
particularly for manufacturing, are
valuable. APM also need equipment
vendors’ help in the recipe development
and tool modification for MEMS
application. This kind of work should
preferably be started before the shipping
or even during evaluation of tools.
The arrangement of time slots in the
equipment vendor’s lab for demonstration
is therefore very important.
For more information about APM please
contact: [email protected].
Unaxis Chip | 13
Telecom
MEMS Technology
for Telecommunication
Prof. Dr. Alex Dommann, Interstate University
of Applied Science, Buchs, NTB, Institute for
Microsystemtechnology IµS-NTB
The impact of telecommunication liberalization and disruptive technical
changes brought on by the internet are driving a massive increase in the
demand for bandwidth that is unprecedented in history.
The need to pump more bits around
the world at the speed of light has made
the development of optical components
one of the most critical areas of research
and business. However, opto-electronics
is a highly specialized field requiring
interdisciplinary know-how to participate.
Besides the glass fibers themselves,
the electronic boxes which create, amplify,
regenerate, switch, and receive tiny light
pulses are critical drivers of transmission
system performance and bandwidth
capacity. All these components have to be
very precise in terms of geometry. Highly
trained operators still assemble most
opto-electronic components by hand.
Micron-level tolerances and individual
Figure 1: Schematic
view of the parallel
waveguide combiner
14 | Chip Unaxis
adjustments have kept manual assembly
the industry norm. There is a great need
for efficient micro-packaging designs,
precision machines and production
processes to automate opto-electronic
component manufacturing. This is where
assembly sees great creative potential
for MEMS technology.
The new approach will downsize
both costs and space needed for
opto-electronic components and reduce
costs and time for precision assembly,
where designs meet the silicon MEMS
technology world.
New technologies for opto-electronic
components assembly
SIGA (Silicon LIGA = Lithography Galvanic)
is a newly developed low-cost HARMS
(High Aspect Ratio Micro Systems)
process to fabricate microsystems and
metal tools for injection molding or hot
embossing of micromechanical parts.
As for related replication technologies,
a mold is filled with metal (Ni, Cu) by
electroplating. Unlike the conventional
LIGA process, which is based on
polymers, the SIGA mold is made of
silicon, thus replacing deep lithography
with deep silicon etching. The main
advantages of SIGA are the profile
control, the ease with which the silicon
mold can be stripped after electroplating,
the moderate process costs, and the
simplicity of the process steps.
The motivation to develop a new lowcost HARMS process based on silicon
molds and electroplating was the
availability of deep reactive ion etching
(DRIE) tools and processes and the
limited performance of existing low-cost
HARMS processes for fabrication of
replication tools – particularly in the case
of profile control for outforming and mold
stripping after electroplating.
The idea to use silicon molds for
electroplating is not new, but has only
been used for limited structure depths
(< 100 µm) and aspect ratios (< 5) [1].
Silicon molds for high aspect ratio
electroplating require uniform structure
depth and a seed layer on the bottom of
the mold. Electroplated tools for injection
molding and hot embossing additionally
need smooth surfaces and positive trench
profiles for outforming.
The process has a similar concept as
LIGA and is, therefore, called “SIGA”
(Silicon LIGA). The potential range of
applications of the SIGA technique covers
various fields such as micro-mechanics,
micro-optics, micro-fluidics, and
integrated microsystems.
At present, Contraves Space AG is
developing a laser-based communication
terminal for geostationary satellites. The
carrier beam of the laser subsystem is
produced by a Nd:YAG ring laser. For this
space application, a diode laser pump
module has to be developed.
The goal was to investigate a light
beam combiner for a diode laser pump
module without mode losses and with
high mechanical stability. The application
has to guarantee a lifetime of more than
10 years in space environment. With
the new parallel waveguide combiner
(Figure 1) it is possible to fulfill these
Figure 2: Throughetched silicon
stripes, 4 µm wide,
105 µm high and
8000 µm long
Figure 3: Cross-section
of DRIE-etched polymer
type structure
specifications. The device combines
the output of eight laser diodes passively.
More than one laser can be active at
the same time. This allows to drive the
laser diodes with half of the maximum
output power, increasing therefore the
lifetime of each laser diode. Due to new
possibilities in microsystem technology
(parameter-ramping for DRIE [2], [3]),
we are capable of reproducing the
postulated geometry.
Other passive light combiners [1] like
Y-couplers have rather high transmission
losses. Active components like mirror,
prism and waveguide switches [1] are
complex and therefore of low robustness.
Free space lens systems are expensive,
quite large, and less stable. The system
proposed below is smaller and more
stable.
We have investigated two different
types of parallel waveguide combiners,
the oxide and the polymer type. Both
types were patented. For the oxide type
(Figure 2), silicon is dry through-etched
by profile-controlled DRIE to get 4 µm
wide and 105 µm high silicon stripes.
With thermal wet oxidation, silicon is
transformed into SiO2 which is used as
waveguide core with low absorption
characteristics. To get the cladding of the
waveguide and mechanical stability, the
structures are recast with an adhesive
with a refractive index of 1.4004.
The yield of the polymer type (Figure 3)
is higher, but also the absorption of the
polymer core. The grooves are dry etched
by DRIE too. The cladding is formed by
thermal wet oxide and a glass substrate
on the top of the structure. The cavities
are filled with adhesive which exhibits low
absorption and a refractive index of 1.54.
To characterize the device, the laser
diode facet is positioned face to face with
a gap of 5 µm to the waveguides. The
laser diode is temperature driven and
power-stabilized.
The functionality of the parallel
waveguide combiner has been proven.
It is possible to map the facet of the laser
diode without any mode losses into a
glass fiber. In addition, it is now possible
to drive two laser diodes with half of the
maximum power to get the postulated
output power at the end of the device.
This remarkably increases the lifetime
of the system.
The parallel waveguide combiner
permits the production of laser pump
modules with low power and high
reliability. This gives such devices the
opportunity to open new markets.
shows pigtails (core diameter 50 µm),
located on the left-hand side. Each pigtail
delivers light from a separate laser diode.
The pigtails are mounted in V-grooves.
The exit surface of each pigtail is imaged
onto the core of the collecting fiber (core
diameter 200 µm). The goal is the perfect
overlap of the images of all input fiber
cores at the position of the output fiber
core. Each image is performed by means
of a spherical lens. If necessary, a
cylindrical lens is put in front of the
spherical lens, as shown in Figure 5.
The advantage of this design is the
reduction of alignment work and of low
light loss due to the high transmittance
of the lenses.
The concept of the Micro Free Space
Combiner allows a clever packaging of
available optical components such as
optical fibers (used as cylindrical lenses
for beam shaping) and sphere-lenses for
the imaging of the input fiber cores onto
the output fiber. Even DOE (defractive
optical elements) could be integrated.
Figure 4: Top view of
a diced polymer type
device
Figure 5: Silicon
bench structure
Conventional silicon micromachining
Another possible design of a parallel
waveguide combiner based on
conventional silicon micromachining
is shown in Figure 5. The schematic
Unaxis Chip | 15
Figure 6: Unaxis NE D200 PECVD system
Highly precise technologies, such as
photolithography and silicon-etching, can
be used to build V-grooved silicon boards,
which allow self-adjustment of all the
components (fibers and lenses) at the
exact positions.
The whole system is divided into three
planes to get a more symmetrical situation
for the imaging process. The positioning
of the output fiber is done by maximizing
the total output power. The whole system
can be molded completely after
packaging – the perfect condition for a
space-suitable combiner.
Packaging of optical components is
possible because of the high precision of
silicon boards. This concept relies on
approved MEMS technologies. Several
types of free space combiners are state
of the art. The novelty of the proposed
concept is to produce free space
combiners on a small scale out of silicon.
The system can be optimized and
toleranced by computer simulations
before manufacturing (Figure 5).
Planar optical waveguide components
Planar optical waveguides for applications
in optical communication can be
fabricated using conventional thin film
deposition techniques. We are currently
developing a beam splitter based on a
planar silicon oxynitride core with a silicon
oxynitride cladding layer. The concept of
the Plasma Box® of the Unaxis NE D200
PECVD system (Figure 7) permits to
fabricate low-stress isolating layers
especially for micromechanical parts,
planar optical silicon oxynitride core, and
microsystems. Unlike the conventional
PECVD processes, which are based
on compensating multilayers of tensile
and compressive strained layers, the
16 | Chip Unaxis
Figure 7: Plasma Box®
Plasma Box® system allows production
of single layer structures with lower stress
values. The layers are of major interest to
sensor manufacturers and for the
production of planar waveguides with
small birefringence effects.
쐍 Impurities (outgassing flow from the
chamber cold walls) do not contaminate
the deposited layer
쐍 Ultrapure layers are possible although
no load-lock technology is used
쐍 The discharge is confined in a uniformly
heated reactor (in a convential PECVD
system only the substrate holder is
heated), allowing film deposition with
excellent uniformities in thickness and
refractive index
In this study, the deposition was done
with three different mixtures of N2/SiH4
and NH3 /SiH4 ratios to get different layerstress-types (compressive – low – tensile).
The work pressure and RF power
respectively are further parameters to
adjust. Increasing pressure results in
more stress (compressive to tensile)
into the layer. The pressure and RF
power influence the plasma size. Also
different thicknesses were deposited to
demonstrate the dependency of the
stress on the thickness. Such planar
waveguide will allow the microfabrication
of optical devices with high integration
density. The refractive index contrast of the
waveguide can be adjusted by changing
the nitrogen content in the planar silicon
oxynitride core. Due to the very small
internal stress of the layers and the low
optical loss, it is possible to achieve
minimized radiation losses.
For further information please contact:
[email protected]
Prof. Dr. Alex Dommann
was born in Lucerne,
Switzerland. He received his
Dr. Sc. from the ETH in Zurich
in 1988 after completing
his diploma in Solid-state
Physics from the University
of Zurich in 1984. In the
following years, he was
research fellow at the
applied physics department
of the California Institute of
Technology, Pasadena (CA),
research scientist at
the Paul Scherrer Institute
in Würenlingen and at
the “Laboratorium für
Festkörperphysik” of the
ETH in Zurich. Since 1991,
he has been professor of
materials research and
physics at the Interstate
University of Applied
Sciences Buchs, NTB,
Switzerland, then on
sabbatical leave at the
Caltech in summer 1997.
Since 1997he has been
Scientific Head of the
Institute for Microsystems
at NTB.
References
1 A. Olsson, O. Larsson, J. Holm, L. Lundbladh,
O. Öhman and G. Stemme, “Valve-less diffuser
micropumps fabricated using thermoplastic
replication,” Sensors and Actuators A 64, (1998)
63 – 68.
2 M. Gmür, A. Dommann, H. Rothuizen,
R. Widmer and P. Vettiger, “SIGA: a new High
Aspect Ratio Micro System Process”, Proc. of
the 2nd International Conference on Integrated
MicroNanotechnology for Space Applications,
Pasadena, CA, vol. 1 (1999), 267.
3 A. Ayon, C. Lin, R. Braff, M. Schmidt et al.,
Etching characteristics and profile control in a
time-multiplexed inductively coupled plasma
etcher, IEEE Solid-State Sensor and Actuator
Workshop, 1998, 41– 4.
4 H. Zappe, Introduction to Semiconductor
Integrated Optics, Artech House
Optoelectronics Library, 1995.
Telecom
MEMS: a Playground
for New Thin Film Materials
Dr. J. Baborowski, R. Lanz, PD Dr. P. Muralt, N. Ledermann
(from left to right), Ceramics Laboratory, Swiss Federal
Institute of Technology EPFL, Lausanne, Switzerland
Micro-electro-mechanical systems, or
microsystems, constitute a fascinating
world of miniaturized functionality. The
original notion of MEMS emphasized that
mechanical elements are added to
microelectronics – as needed for motion
sensors for instance. Today the actual
field has become much wider. It now
includes also optical, thermal, magnetic,
and fluidic (chemical and biological)
interactions and phenomena [1].
The basic material of a MEMS device is
most often Silicon. Silicon is inexpensive,
has excellent elastic properties, a low
thermal expansion coefficient, and does
not show creeping and aging because
it is a pure, monocrystalline material. In
addition, the micromachining of silicon is
well mastered today, either by means of
anisotropic wet etching, or anisotropic
dry etching (deep silicon etching). To a
certain extent, one can fabricate devices
by means of an “all-silicon” technology
based on electrostatic interactions
between doped silicon elements. In
general, however, many more material
properties are needed than silicon can
offer. Silicon is a bad electrical and a very
good thermal conductor, for instance.
Hence, one has to add metal films for
improving electrical conduction, or
thermal insulator films (e.g. SiO2, Si3N4)
for improving thermal insulation.
There are materials that do not only
provide auxiliary functions but the
essential functionality of the device.
These are so-called functional materials.
The useful functional materials provide
a transformation between driving signal
or read-out signal on the one hand, and
a sensor or actuator parameter on
the other hand. The driving and read-out
signal can be an electrical, magnetic,
or optical one. The sensor parameter
can be a mechanical deformation, a
temperature change, a chemical reaction,
etc. Actuation can mean a linear
displacement, the emission of an
ultrasonic wave, the phase shift of
a laser light beam for instance. Functional
materials in MEMS is a young and vast
field. Many opportunities are available in
microsystems. It is a very exciting field of
applied materials science. Let us take a
short look at piezoelectric MEMS.
Piezoelectric MEMS
Best known among bulk piezoelectric
materials is PZT (PbZrxTi1–xO3), which
is applied in ultrasonic imaging, linear
actuators for nanoscience (e.g. atomic
force microscopy), high pressure valves,
and many more. This material has also
been integrated as a thin film into MEMS
devices. Stresses of up to 100 MPa and
strains of up 0.1% have been obtained [2].
PZT exhibits the perovskite structure,
as shown in Figure 1. In the para-electric
high temperature phase the lead ions
occupy the corners of a cube, the Ti and
Zr ions are randomly mixed (solid solution)
in the center of the cube, and the oxygen
ions the face centers, thus forming a
regular octahedron around the central
cation. In the ferroelectric phase (below
about 350°C) the cube is distorted, mainly
due to a displacement of the central
cation with respect to the oxygen
octahedron. This displacement occurs
along the same direction for all unit cells
inside a ferroelectric domain. The
structure becomes polar. The ions shift
easily when an electric field is applied. For
this reason, PZT shows a large dielectric
constant (around 1000) and piezoelectric
coefficients. This means that at a given
field, a PZT capacitor can store 1000
times more energy than a vacuum
capacitor. The external field may also
switch the spontaneous electric
polarization by 180°. That’s why it is
called ferroelectric, after the analogous
phenomenon occurring in magnetism.
Thin films of PZT are very often deposited
by sol-gel techniques (chemical solution
Figure 1: The unit
cell of the perovskite
structure
Unaxis Chip | 17
Telecom
deposition). Among piezoelectrics, there
is another class of materials that are
not ferroelectric, but polar only. The
alignment of the polar axis cannot be
effectuated by an external field. It must be
provided by the growth process. Typical
representatives of this class of materials
are ZnO and AlN (see the structure in
Figure 2). They are well known as thin film
materials. Low temperature processes
are carried out by sputtering in order to
achieve the unidirectional alignment of
the polar axis (c-axis) perpendicular to
the film plane (see e.g. [3]).
Piezoelectric strains and stresses
couple in various geometries to the
electric field. In planar thin films
structures, the piezoelectric film is
sandwiched between two electrodes
(Figure 3). The electric field stays thus
perpendicular to the film plane (direction
3). Of importance in (polycrystalline) thin
films is the longitudinal effect along the
electrical field, and a transverse effect in
the film plane (direction 1). Two basic
structures can be applied. Most common
to MEMS applications is the use of the
transverse effect in flexural structures.
Piezoelectric transverse stress in the film
Figure 2: The unit
cell of the wurtzite
structure
18 | Chip Unaxis
plane bends an elastic structure that
can be a beam, a bridge, or a membrane.
The size of the deflection along direction 3
depends on the lateral dimensions.
It is in the region of micrometers/100 µm
lateral size. The longitudinal mode affects
the thickness of the piezoelectric thin film.
A thickness change of typically 0.1 nm / V
can be achieved.
Quite a number of applications
have been demonstrated for flexural
structures: active cantilevers for atomic
force microscopy, accelerometers,
2-dimensional mirror arrays for image
projection, microphones, ultrasonic
micromotors, Lamb wave pumps and
filters, and others. Currently, there is also
much interest to evaluate piezoelectric
MEMS for high frequency ultrasonic
imaging and ultrasonic sensors. Suitable
membrane or plate structures are
Figure 3: Basic
operation modes of
thin films in MEMS:
The capacitor
structure puts the
electric field along
direction 3.
Piezoelectric
stresses in the film
plane (direction 1)
bend the flexural
structure and yield
an excursion
in direction 3.
developed for ultrasonic transducer arrays.
Figure 4 shows an example of a fabricated
transducer structure. The admittance of a
300 µm wide element containing 2 µm PZT
on a micromachined silicon membrane
is depicted in Figure 5, showing the
fundamental resonance at about 1 MHz.
The longitudinal effect will not be easily
exploitable in actuators and sensors.
However, this effect is very much suited
for bulk wave transducers (RF-MEMS).
The fundamental thickness resonance
of a 1 µm thick film occurs in the GHz
frequency range. This is very much
suited for building microwave filters for
telecommunications. At such high
Figure 4: SEM
viewgraph showing
the micromachined
bridge of a suspended
membrane with
the etched Pt and
PZT layers
Figure 5: Admittance
as a function of
frequency for a
micromachined,
300 µm wide PZT
thin film transducer
element [4]
0.002
0.005
Re (Y) [Ω –1]
C1-B-10dc
0.004
0.001
0.003
0
0.002
– 0.001
0.001
– 0.002
– 0.003
0
For more information please contact:
[email protected]
Im (Y) (Ω –1)
frequencies, one has to use piezoelectric
materials with good acoustic properties,
i.e. small acoustic losses and a high
sound velocity. Aluminum nitride (AlN)
has very superior properties in this
respect. PZT is too much damped at
GHz frequencies. Figure 6 shows the
admittance of a bulk acoustic resonance
of an AlN resonator at 7.4 GHz. Figures 5
and 6 thus illustrate the difference of
flexural and bulk waves made in thin film
structures, as seen by the frequency
spectrum. The resonances are a factor
7’000 apart.
1
1.05
1.1 1.15
1.2 1.25
1.3
Frequency [MHz]
G Conductance
B Susceptance
0.08
0.06
Admittance Y [S]
Reference
1 Senturia, S. D., Microsystems design, 2001.
Boston: Kluwer Academic
2 Muralt, P., “Ferroelectric thin films for
microsensors and actuators: a review,”
Micromech. Microeng., Vol. 10,
pp. 136 – 146, 2000.
3 Dubois, M.-A. and P. Muralt, “Stress and
piezoelectric properties of AlN thin films
deposited onto metal electrodes by pulsed
direct current reactive sputtering,”
J. Appl. Phys., Vol. 89, pp. 6389 – 6395, 2001.
4 Muralt, P. et al., “Study of PZT Coated
Membrane Structures for Micromachined
Ultrasonic Transducers.” Proc. of IEEE
Ultrasonic Transducers, Atlanta, 2001.
5 Lanz, R., M.-A. Dubois, and P. Muralt, “Solidly
mounted BAW filters for the 6 to 8 GHz range
based on AlN thin films,” Proc. of IEEE
Ultrasonics Conference 2001, Atlanta (USA),
2001.
0.04
0.02
0
– 0.02
Figure 6: Admittance
of bulk acoustic wave
resonator showing
the fundamental
thickness resonance
of a 300 nm thick AlN
thin film [5]
– 0.04
7
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8
Prof. Dr. Paul Muralt
received a diploma in
Experimental Physics
in 1978 at the Swiss
Federal Institute of
Technology in Zurich (ETH).
He accomplished his
PhD thesis in the field
of commensurateincommensurate phase
transitions at the Solid
State Laboratory of ETH.
In the years 1984 and
1985, he held a post
doctoral position at the
IBM Research Laboratory in
Zurich where he pioneered
the application of scanning
tunneling microscopy to
surface potential imaging.
After a stay at the Free
University of Berlin, where
he built up a tunneling
microscope, he returned
to Switzerland in 1987,
where he joined the Balzers
group in Liechtenstein.
He specialized in sputter
deposition techniques,
and since 1991 managed
a department for
development and
applications of physical
vapor deposition
processes. In 1993, he
joined the Ceramics
Laboratory of the Swiss
Federal Institute of
Technology EPFL in
Lausanne. His research
interests are the deposition
of ferroelectric and other
polar thin films, propertymicrostructure relationships,
the integration of
ferroelectric thin films
into memory devices, and
of piezo- and pyroelectric
thin films into micro-electromechanical systems.
More recently submicron
ferroelectric structures have
attracted his attention. He
gives lectures in thin film
deposition and micropatterning.
Frequency [GHz]
Unaxis Chip | 19
Telecom
Unaxis Supports DWDM
with PECVD and RIE
DWDM = Densed Wavelength Division Multiplexed
Figure 1: Scanning
electron microscope
picture of a test
structure for arrayed
waveguides that
shows the patterned
SiO2 fibers fanning
out from a common
input/output channel.
The width and depth
of the fibers are
around 10 microns.
It is clear that the
intersection area is
the most critical one
for etching since its
aspect ratio goes
far above 10:1
(image: OpsiTech,
Grenoble, France).
Dr. Emmanuel Turlot,
Managing Director Unaxis Semiconductors Grenoble
The IT market segment of
telecommunications – despite its
temporary slowdown – is experiencing
a doubling of the bandwidth capability
of the global network every six months.
The advent of multi-format (text,
applications, etc.) and especially video
data exchange via internet triggers
this demand for rapid growth of the
communication highway. On the one
hand, the optical fiber offers almost
20 | Chip Unaxis
unlimited bandwidth capability
for terrestrial communications at very
low cost. But on the other hand, the
requirement to convert the optical signal
along the fiber regularly into an electrical
one and back impedes the bandwidth
and/or increases its cost drastically. This
is mainly because TDM (Time Division
Multiplexed) technology as opposed to
WDM (Wavelength Division Multiplexed)
is still widely used to separate the
channels today. TDM requires high power
optical signals that propagate with high
losses in the optical fibers and hence
require frequent amplifications to avoid
transmission errors. WDM, however,
separates the channels with the carrier
optical frequency or wavelength with low
power optical signals that can propagate
over kilometers without interactions or
amplification need. Ultimately, DWDM
(Densed Wavelength Division Multiplexed)
solutions will offer unlimited bandwith.
As demand changes, more capacity
can be added, either by simple equipment
upgrades or by increasing the number
of wavelengths carried by the already
existing fibers.
SiO2 #2
SiO2 #3
10
SiO2 #1
Silicon
substrate
To succeed, DWDM technology
requires the development of new optical
components such as wide bandwidth
optical amplifiers (active) and optical
multiplexers (passive). Two kinds of
optical multiplexers are currently under
development: either based on interference
filters (bandwidth of 200 GHz typically)
or on an array of optical waveguides,
to separate or recombine the different
wavelengths or channels. The optical
waveguides-based multiplexers are
integrated optics devices, i.e.
manufactured on silicon substrates
via the deposition and etching of several
micron thick SiO2 films. The waveguides
are directly patterned with standard
lithography techniques on the substrate
(Figure 1).
Like for optical fibers, optical
waveguides require SiO2 materials with a
slightly different optical indices in order to
channel the light through with minimum
losses. Since the light has to be
transferred from this waveguide to
Figure 2: Schematics
of the cut view of an
optical waveguide
arrangement
manufactured via
PECVD deposition
and RIE etching of
SiO2 with three
different optical
indices on a silicon
substrate. The optical
signal is confined in
SiO2 #2 core film and
travels in a direction
perpendicular to the
cut view plane.
the optical fiber at the output of the
multiplexer, the characteristics of the
waveguide should be as close as possible
to the one of the fiber to reduce optical
losses. In particular, the difference
between core SiO2 (SiO2 #2) and the
underlying one (SiO2 #1) is typically
ranging from 10–3 to 10–2 (Figure 2). The
PECVD technique based on the SiH4/N20
gas mixture with GeH4 as a doping gas is
a deposition technique that is capable of
manufacturing SiO2 films with optical index
control better than 10 –4 as well as
optimizing its value by adjusting the Ge
doping. In addition, the cladding SiO2
(SiO2 #3) should have a very good
step coverage in order to fill the small
gaps at the crossing of the waveguides:
in that case, liquid-source-based material
is fed into the PECVD reactor. Unaxis has
developed a production multi-chamber
tool, the QUADRA, equipped with PECVD
reactors based on Plasma Box® design,
capable of depositing these three types
of SiO2 into the same reactor (Figure 3).
Figure 3 : Picture of the QUADRA
multi-reactor production system
taken from the load lock side.
It consists of a vacuum central
handling chamber with four
ports, one dedicated to the
load lock module, and the three
others for the processing
modules, PECVD or RIE/HDP.
Refractive index, thickness uniformity,
stress, and SiH content are the items
which are controlled to ensure planar light
circuit performances.
It is also very important that the edges
of the waveguides, manufactured during
the etching of the core SiO2, are steep
and smooth to limit the optical losses due
to scattering. The dry etching process
of SiO2 based on CHF3 /02 mixture is
inherently anisotropic and hence can
achieve edges as steep as 89°. Here
again, Unaxis is supporting its customers
by developing integrated optic devices
with the QUADRA system. In that case,
the system is equipped with up to three
RIE/HDP etching reactors with heliumcooled substrate holders. The reactors
are compatible with wafers up to 200 mm
diameter. Thanks to the combined
control of the ion energy and the wafer
temperature, the system can etch 10 µm
thick SiO2 films without photoresist
degradation or residues left over at the
bottom or on the edges (Figure 4). Each
chamber is equiped with an automatic
end point detection system coupled
with pattern recognition capability leads
to a wafer-to-wafer etch thickness
repeatability lower than 3%.
Figure 4 : Scanning
electron microscope
picture of an
alignment structure
patterned in a
SiO2 film with the
QUADRA RIE/HDP
system. The height
of the etched film is
around 10 microns
(Picture: OPSITECH,
Grenoble,France)
For more information please contact:
[email protected]
Unaxis Chip | 21
Telecom
Figure 1: SEM of
InP via etching using
hardbaked photoresist
etching mask
Dry Etching InP for
Multiple Applications
David Lishan, Principal Scientist, Mike Devre,
Russ Westerman, Don Malpass,Yao-Sheng Lee, Brad Reelfs,
Strategic Business Unit Compound Semiconductors,
St. Petersburg, USA
Frequency response, thermal conductivity,
breakdown voltages, and optical properties
– coupled with resource commitments –
ensure that the indium phosphide material
system will play an important role in
high-speed electronics and photonics.
The diversity of applications and material
combinations has provided a mixture of
structures requiring etching. Here we
would like to present a selection of etching
results obtained on SHUTTLELOCK ® and
VERSALOCK ™ systems for structures
such as microlenses, device isolation,
backside vias, HBT emitter/base mesas,
and optical devices. Each structure has
specific etching criteria like etch rate,
profile, surface morphology, and selectivity
that must be met for successful device
production. We used a variety of gases and
either a high density ICP or a low density
RIE source to achieve the desired results.
InP and associated material systems
(e.g. InGaAs, InAlAs) have traditionally
presented obstacles to dry etching
technology. Low etch rates, loss of
22 | Chip Unaxis
surface stoichiometry, and surface
roughness are obstacles that typically
result from low vapor pressure indium
reaction products. Although wet etching
is often a selective, relatively inexpensive
and low damage process, its isotropic
nature makes it unsuitable for many
applications. In response to these
limitations and problems, several dry
etching chemistry approaches have been
explored and developed. Each of the
approaches is intended to address a
particular application. For example,
structures deeper than a micron require
processes providing high etching rates
to maintain acceptable throughput, while
shallow features necessitate relatively
slow etching rates to retain control.
In the remainder of this article we
discuss various etching chemistries
and system requirements for different
applications. Etching requirements for a
variety of applications have been roughly
grouped and described in the table below.
This simplification cannot represent the
total diversity of applications that naturally
consist of a wide range of mask materials,
profiles, and etch depths even within the
same application.
Backside contact (e.g. vias)
This is a deep etch approximately of
50 to 100 µm used for defining contacts
through a thinned substrate to a device.
Typical applications utilize a vertical
sidewall structure however, sloped profiles
may be realized using a photoresist etch
mask erosion process (with the angle
proportional to initial resist slope and
erosion). An example of anisotropic
profiles is shown in Figure 1. An elevated
temperature of approximately 160 ºC is
necessary to obtain reasonable etch rates
and desorb the low volatile halide etching
products (InClx and InBrx ).
Microlenses
This is a deep etch used for creating a
curved lens-type structure with a typical
etch depth of 5 to 10 µm. The sloped
profiles are deliberately realized using a
photoresist etch mask erosion process
that requires a relatively low selectivity of
near unity. An example of a lens profile in
Application
Typical etch
depth
Selectivity to
mask
Profile
Morphology
Etch rate
Electronic devices
(e.g. HBTs, HEMTs)
0.1 – 0.5 µm
Moderate
Near vertical
Smooth
Slow
< 0.15 µm /min
Microlenses
5 – 10 µm
Near unity
Variable
Smooth
~ 0.5 µm /min
Optical devices (e.g. lasers, VCSELs,
waveguide detectors, modulators)
1 – 10 µm
High
Vertical
Smooth walls
~ 0.5 µm /min
Gratings
0.03 – 0.2 µm
High
Variable
Smooth
Slow
< 0.06 µm /min
Mesas (e.g. contacts, isolation)
1 – 5 µm
Moderate
45 – 75 degrees
Moderate
~ 0.5 µm /min
Backside contact (e.g. vias)
50 – 100 µm
High
60 – 90 degrees
Not critical
Fast
> 1 µm /min
Figure 2: SEM of
InP microlense etching
using photoresist
etching mask
InP is shown in Figure 2. The photoresist
mask shape is determined either by
reflowing the resist or with a gray scale
photomask.
Smooth vertical etch
This application involves deep, vertical
etching approximately 1 to 10 µm in depth
and is often used to define structures with
a primary application in optical devices.
These applications include devices such
as waveguides, vertical cavity surface
emitting lasers (VCSELs), diodes, and
lasers. Typical applications require a
vertical profile with smooth surface
morphology. Sidewall smoothness is
very dependent on the initial condition
of the patterned mask material as high
selectivity between the mask and InP
is employed. Examples of possible
anisotropic profiles using a silicon
dioxide mask are shown in Figure 3.
To accentuate the chemical aspect of the
etching, this process is run at 160 ºC.
Mesa
In some device applications it is not
critical to have a vertical profile, and in fact
it may be desirable to have an intentionally
positively sloped profile (e.g. contact
metallization between layers). Etching
depths can vary from shallow to many
microns and are usually sloped with
an angle between 45 and 75 degrees. In
general, this process also relies on mask
erosion to generate the slope. Examples
of mesa profiles using this process are
shown in Figure 4.
Figure 3: SEMs of
vertical etching of InP
using SiO2 mask
The wide range of applications and just
as many different processes mandate a
flexible hardware set. Although RIE may
be appropriate for certain applications,
the primary system accepted for most
applications is the Inductively Coupled
Plasma (ICP) source. An ICP type etching
system with a separate bias control for
the substrate enables critical control and
versatility with independent management
of ion bombardment and reactive species
formation while generating high-density
plasmas at low pressures. Material
damage, profile, selectivity, and etching
rate can be positively influenced by
judicially balancing the physical and
chemical components of the etching
process.
The examples shown in this article
include process conditions ranging
from 5 ºC to 160 ºC, and thus it is clear
that substrate temperature must be
carefully managed. A very effective
method is coupling the back of the
substrate to the chuck with a thin layer
of flowing helium. The substrate is
“clamped” to the chuck either
mechanically or electrostatically at the
discretion of the user.
Another issue not often discussed is
the maintenance of chamber cleanliness.
Regardless of the etch chemistry involved,
there is a strong tendency for reaction
by-products to condense on the process
chamber walls. Although the chamber
itself cannot be heated to the appropriate
temperature for safety reasons, chambers
are now being designed with a removable
heated liner. This forces reaction
by-products to exit the chamber as
vapor which is then condensed in
a specifically designed removable trap.
The process chamber can remain under
vacuum during trap substitution. This
combination of hardware enhances
module cleanliness and reduces the
maintenance downtime without
impacting processing.
Summary
After many years of basic research,
InP and related materials are rapidly
moving into pilot line environments. New
etching systems are available that can
accommodate the numerous applications
and the demanding increase in utilization.
Just several years ago the only option
was RIE, now there are combination
ICP/RIE sources. Controlled substrate
temperature and self-cleaning chambers
present more opportunity for appropriate
etching processes.
For more information please contact:
[email protected]
Figure 4: SEMs of
mesa structures in
InP; photoresist
mask (left), tungsten
nitride mask (right)
Unaxis Chip | 23
Advanced Silicon
LEPECVD Provides High-Quality
Virtual Substrates
for Ge-rich SiGe p-MOSFETs
Dr. Matthias Kummer, Post-Doctoral Researcher,
ETH Zurich, Switzerland
These days the vast majority of available
SiGe products are based on the HeteroBipolar Transistor (HBT), with UHV-CVD
as the established deposition technique
for production. The HBT is produced
either as a discrete device or combined
with traditional Si CMOS technology in
SiGe BiCMOS ICs. These integrated
circuits, taking advantage of the superior
electronic properties of SiGe and the low
production costs of CMOS, are already
rushing into the fast-growing wireless
telecommunications market. Up to now,
the primary role of the SiGe enhancement
to Si CMOS ICs has been to add RF
functionality that otherwise would have
to be implemented with additional,
expensive III-V-based devices.
SiGe CMOS
A technological route with even more
significance than the BiCMOS
communications segment is the
introduction of the SiGe enhancement
into the CMOS technology itself. The
combination of thin, tensilely strained
Si layers (for n-type MOSFETs) with thin,
compressively strained Ge-rich layers
(for p-type MOSFETs) leads to strongly
enhanced electron and hole mobilities
for the n- and the p-type devices
respectively. This higher carrier mobility
will ultimately enhance virtually all of
the important electrical characteristics
of the transistors. A successful
implementation of a SiGe-based CMOS
process could significantly boost the
performance of this mainstream
technology. If such an implementation
adheres to some basic requirements
24 | Chip Unaxis
for standard processes (lithography, wet
and dry chemical processing, or even
fundamental issues like mechanical
substrate stability for easy wafer handling
and – last, not least – availability of
inexpensive substrates), it will give access
to significantly higher performance levels
at astonishingly low additional cost,
as most of the processing steps will
not change.
The main issue to be addressed for
implementing SiGe CMOS, apart from
the detailed design issues for the actual
device heterostructures, is the production
of substrates which can provide the
strain needed for the active layers. Due
to the relatively high mismatch between
the lattice constants of Si and Ge of 4.2%,
the strained, active layers have to be
epitaxially deposited on some material
with an intermediate lattice constant. One
of the most promising approaches is to
grow a thick, compositionally graded SiGe
alloy buffer layer on a standard Si wafer,
with the concentration increasing from
pure Si to the Ge fraction needed for the
desired mismatch. If the concentration
gradient is shallow enough, the resulting
virtual substrate will be fully relaxed and
Figure 1: Pseudo-3D
representations of AFM
images obtained from
virtual substrates with
70% Ge concentration
before (a) and after (b)
process sequence
optimization. The
troughs visible in (a)
are as deep as 200 µm,
while the maximum
corrugation amplitude
in (b) is less than 15 µm.
sufficiently defect-free for the subsequent
epitaxial deposition of the active transistor
structures. The resulting requirements
for very thick epitaxial layers and relatively
low temperatures call for new approaches
for the deposition processes. The
development of LEPECVD at ETH Zurich
in collaboration with NTB Buchs and
Unaxis came just in time to address
these issues.
Ge-rich virtual substrates and
SiGe p-MOSFETs
Here we will present the latest advances
achieved in the production of Ge-rich
virtual substrates aimed at the
implementation of SiGe p-MOSFETs.
The first results obtained from a working
high-performance SiGe p-MOSFET
fabricated completely by LEPECVD and
processed by DaimlerChrysler Research &
Development in Ulm, Germany, showed
a record hole mobility of more than
750 cm2/ Vs [1]. After these encouraging
results, we used the 4" LEPECVD
prototype and development system
at ETH Zürich to further improve the
structural quality of the virtual substrate
with Ge concentrations starting from
50% and the Ge-rich active strained
channel with concentrations up to
pure Ge.
The issues to be dealt with at higher
Ge concentrations for the virtual substrate
are the reduction of surface roughness
and the density of threading dislocations,
while maintaining full relaxation of the film
to the desired lattice constant. As for the
strained channel, its interfaces have to be
sharp, and it must be kept completely free
of dislocations and strain-induced
roughening. While for optimizing the
performance the Ge concentration in the
Figure 2: Highresolution X-ray
diffraction reciprocal
space map (HR-XRD
RSM) around two
Bragg peaks obtained
from a complete
p-MOSFET layer
sequence fabricated
with LEPECVD
channel should be as high as possible,
ideally pure Ge, it becomes increasingly
difficult to keep this strained layer flat.
The reason lies in the “softer” properties
of Ge compared with Si. Its melting point
(938°C) is considerably lower than that
of Si (1410°C), which gives Ge a much
stronger tendency to be elastically
deformed upon application of strain at
typical temperatures used for epitaxy.
The key both for optimizing the virtual
substrate and the strained channels is
a deposition process, which allows for
a wide temperature range without
degrading the film quality and with no
significant reduction of the growth rate.
Fortunately, this is exactly the strength
of LEPECVD: as the energy needed for
the growth reactions is almost completely
supplied by a very intense plasma,
LEPECVD is practically independent of
temperature in a surprisingly large
process window. This allows for the
deposition of very thick (between 5 and
15 µm) virtual substrates at temperatures
reaching down to 500°C at growth rates
between 4 and 10 nm/s. By balancing the
requirements for a low temperature to
suppress surface roughening and the
need for a sufficiently high temperature for
asserting the full relaxation, we developed
optimized process sequences suitable for
virtual substrates of up to 100% Ge
concentration. The effect of this
optimization on the surface morphology
is shown in Figure 1.
To verify the structural quality of the
complete p-MOSFET structures, we
made extensive use of high-resolution
X-ray diffraction reciprocal space
mapping. This method is ideally suited
for examining the crystal quality, the
composition, the strain state and the
thickness of individual layers of complete
device sequences. An example of such
a measurement is shown in Figure 2,
documenting the high structural quality
of the (fully relaxed) virtual substrate
and the (completely strained) active
Ge-rich channel.
Unaxis Chip | 25
Figure 3: TEM image
of the strained
channel of a SiGe
p-MOSFET structure.
The channel
contains 90% Ge
and is grown on
a 60% Ge virtual
substrate.
In addition to the AFM and X-ray
investigations, the shape and interface
sharpness of the active, strained channel
has been verified with transmission
electron microscopy (TEM). As shown in
Figure 3, we were able to obtain perfectly
flat and abruptly defined Ge-rich channels
by using appropriate process conditions.
The results of these optimizations are
demonstrated again with the fabrication
of transistor devices at DaimlerChrysler
R&D. The obtained data are shown
in Figure 4. The comparison concerns
two important figures of merit, the
saturation current and the maximum
transconductance, of several transistors
fabricated from three different structures.
They have all been prepared by LEPECVD
and consist of a strained Ge-rich channel
of 80% or 90% Ge content on a virtual
substrate with final Ge concentration of
50% and 60%, respectively. The data
labeled “old” are from the devices of [1],
where the other two SiGe devices have
been obtained after the optimization
of the deposition process sequence.
As demonstrated, further research has
paid off with a 30% – 40% enhancement
for the 80% device, while the increase
of the Ge concentration in the channel
to 90% has boosted the performance
by a factor of 2. In comparison to the Si
reference device, it has to be stressed at
this point that the only additional process
step consisted of the LEPECVD epitaxy,
which amounted to roughly 40 min!
Reference
[1] C. Rosenblad, Chip 4, 2001 (p. 24)
Figure 4: Comparison of the saturation current and the maximum
transconductance for the transistors of [1] (“80% old”), a similar type
obtained after optimization of the growth procedure (“80% new”), and
a transistor with an active channel which contains 90% Ge (“90% new”).
For comparison, a Si reference transistor is included in the plots.
140
90% new
90% new
Maximum
transconductance gm
[mS/mm]
Saturation current ID
[mA/mm]
500
80% new
80% old
Si reference
400
300
200
100
0
120
80% new
80% old
Si reference
100
80
60
40
20
0
1
10
Gate length l g [
26 | Chip Unaxis
Dr. Matthias Kummer
studied physics at the Swiss
Federal Institute of
Technology in Zuerich,
Switzerland (ETHZ) from
1992 to1997 and received
a diploma in Experimental
Physics from ETHZ with
an STM study of SiGe
heteroepitaxial structures
in 1998.
In 2001 Matthias Kummer
received his PhD from the
ETHZ with a thesis on the
fabrication of device grade
SiGe heterostructures
grown with plasma-assisted
techniques, in particular
LEPECVD, in the group of
PD Dr. Hans von Känel.
While writing the PhD thesis
he worked at the Interstate
University for Applied
Science of Technology in
Buchs, Switzerland (NTB), in
the Institute of Microsystem
Technology with Prof. Alex
Dommann, mainly on
high-resolution X-ray
diffraction analysis.
100
1
10
Gate length l g [ m]
100
Advanced Silicon
Low Energy Plasma Processing (I)
LEPP 300
The extention of the CLUSTERLINE® 300 concept
for PECVD processing
Philipp Bartholet, Werner Bischof, Andreas Erhart, Steven
Ernst, Yuri Goeggel, Siegfried Wiltsche, Dr. Juergen Ramm,
Strategic Business Unit High Speed Silicon
The market
The SBU High Speed Silicon has taken
the strategic decision to develop
deposition processes for high frequency
devices in the silicon technology. The
Bipolar and BiCMOS markets are
addressed by the already existing
UHV-CVD SIRIUS batch-type system
dedicated to the production of heterobipolar transistors (HBT).
The development of the LEPP 300
based on the CLUSTERLINE® 300 bridge
tool, however, was motivated by
the needs of the future CMOS technology.
Electron and hole mobilities in strained
Si and SiGe are above those physically
possible in bulk Si. Devices based on
strained Si and SiGe layers will push
the high frequency capabilities of MOS
technology beyond conventional Si-MOS
technology [1]. Growing a linearly
graded Si1–xGex layer (starting with a
Ge concentration x = 0 and a gradient
of typically 10% Ge/µm) allows the
formation of an almost strain-free “virtual
substrate” (VS) which can have a
predetermined lattice constant depending
on the concentration x of Ge at the layer
surface. Because the difference in the
lattice constant between Si and Ge is
approximately 4%, the pseudomorphic
growth of Si or Si1–yGey with y > x on the
virtual substrate Si1–xGex allows the
formation of strained channels for the
fabrication of devices like MODFETs
(Modulation Doped FETs) and MOSFETs.
Based on this, the most important
requirement for the deposition technology
is the high deposition rate
for epitaxial and hetero-epitaxial Si and
SiGe layers at low temperatures (300°C –
800°C). The development of the low
energy plasma-enhanced chemical vapor
deposition (LEPECVD) process addressed
this issue [2].
Another challenge in Si and SiGe
technology is wafer cleaning before
epitaxial growth (pre-epi clean). Current
technologies utilize either an in-situ high
temperature bake in a hydrogen
atmosphere (typically LPCVD approach
for single wafer processing) or an ex-situ
HF dip (typically UHV-CVD approach
for batch systems). Although both
procedures are compatible with the
HBT production, a pre-epi clean at low
temperatures (< 400°C) would have
many benefits, especially for processing
prestructured substrates and substrates
with temperature-sensitive material.
Low energy plasma cleaning (LEPC)
resolves these issues.
A selection of the most important
requirements for the LEPP 300 is shown
in Table 1. Unaxis Semiconductors owns
all the intellectual property of the hardware
and basic process steps. This ensures
that the system can serve all segments of
the CMOS market and other relevant
markets.
Figure 1:
Schematic of the LEPP 200/300 mm
bridge-type cluster tool of the
configuration existing in the Unaxis
Semiconductors laboratory.
300 mm wafer
FOUP
The system
The development project LEPP 300 was
initiated in May 2000 and integrated into
a value engineering project (“Flash”).
Based on the experiences with experimental systems, the 200 /300 mm single
wafer bridge-type cluster tool (Figure 1)
was realized. The upgrade from 4" to
300 mm wafer size was one of the
challenges in this project. The LEPP 300
now allows processing of 200 mm as
well as 300 mm wafers from cassettes
without changeover. Another great
challenge was the development of a
self-cleaning procedure which resulted
in many implications for the design of
the deposition system as well as for the
plasma source. The handling system
is based on the Brooks Gemini GX 8000
platform which is supported by Unaxis
Table 1: The most
important requirements
for the LEPP 300:
쐍 Single wafer bridge tool based
on the CLUSTERLINE® 300
platform
쐍 Low temperature pre-epi
cleaning module
쐍 Damage-free plasma
epi-reactor
쐍 Integrated chamber selfcleaning procedure for the
deposition module
쐍 Deposition rates of epitaxial
layers in the range of 0.01 nm/s
to 10 nm/s at 550°C substrate
temperature
쐍 Cleaning rates for the removal
of C and O above 0.5 nm/s
C
LEP
g
anin
Cle dule
mo
Load port modules
LPMs
200 mm wafer
open cassette
VD
EC
LEP
s
ces
Pro dule
mo
Unaxis Chip | 27
Advanced Silicon
Figure 3: Measurement scheme
for the discharge characteristics
UA(IA ) explaining the terms
“anode voltage” and “anode
current”.
IA
plasma source
filament
-
stainless steel
reactor
UA
Power
supply
+
pump
connection
plasma
anode
gas inlet
wafer
heater
susceptor
Figure 4:
LEPC module:
The discharge
characteristics UA(IA )
for different argon
gas flows. The data
illustrate the broad
process window
for the condition
of UA < 25 V.
software (ControlWORKS™). The
LEPP 300 consists of two new process
modules. The LEPC module realizes
the plasma-enhanced low temperature
pre-epi clean in a hydrogen atmosphere
at low temperatures. The LEPECVD
module enables high deposition rates
utilizing the plasma enhancement for the
dissociation of the precursors and for
desorption processes during deposition.
This is the first time that the utilization
of plasma for pre-epi clean and for
epitaxial growth are implemented and
combined in a production system.
Figure 2 shows the LEPP 300 system at
Unaxis Semiconductors.
Process development
The verification of the functionality of the
newly designed plasma source was the
starting point for process development.
Important aspects for the redesign of the
source were
쐍 increased wafer size,
쐍 layer uniformity,
쐍 maintenance,
쐍 ultra-high vacuum compatibility.
The deposition as well as the cleaning
process are based on the same design
of the plasma source. A variety of gases
support the process development for
SiGe-CMOS and related fields. The
Discharge characteristics in the LEPC module
20
Ar flow
30 sccm
30 sccm
40 sccm
50 sccm
60 sccm
80 sccm
100 sccm
19
Anode voltage UA[V]
Figure 2:
Close-up of the
LEPC module on the
CLUSTERLINE® 300
platform
18
17
16
15
14
13
12
11
10
0
10
20
30
40
50
60
Anode current IA [A]
28 | Chip Unaxis
70
80
90
flexible design of the LEPP 300 allows the
combination of the LEPC and LEPECVD
processes. However, it also promotes
the combination with other CVD or PVD
processes.
One of the unique properties of the
LEPP 300 is the high efficiency in the
gas utilization. Typical process pressures
are 10 –3 mbar and typical process gas
flows are 50 sccm. This reduces the costs
for consumables and also addresses
environmental issues.
A necessary presupposition for
damage-free plasma processing is
the low voltage between filament and
anode /ground of the DC discharge
(anode voltage UA ). This voltage is
influenced by the design of the deposition
and cleaning chamber and the process
parameters like gasflow, gas mixture,
and discharge current. The UA (IA)
characteristics, plasma potential, and
floating potential of the wafer determine
the ion energy at the wafer surface. This
ion energy has to be below the sputtering
threshold for damage-free plasma
processing [3].
Low energy plasma cleaning
Figure 3 shows a schematic drawing of
the cleaning/deposition module together
with the explanation of the discharge
parameters UA (anode voltage) and IA
(anode current). It is important for the
reliability of the process that these
discharge parameters can be stabilized
and that they allow a broad process
window for different gas compositions and
anode currents. Figure 4 shows a typical
example for the discharge characteristics
in the argon plasma for the new LEPC
module. For anode currents in the range
between 10 A and 90 A, the anode
Anode voltage UA in function of the hydrogen
gas flow at 30 A anode current IA
24
Anode voltage UA [V]
Figure 5: LEPC
module: The anode
voltage for different
gas mixtures of
argon and hydrogen.
The broad process
window allows the
utilization of different
hydrogen flows to
adjust the cleaning
rates.
Ar flow
70 sccm
70 sccm
30 sccm
22
20
LEPECVD module. Again, the anode
voltage can be controlled below 25 V over
a large range of parameters. The anode
voltage is nearly unchanged if a process
gas like SiH4 is added to the argon
discharge. This is important for the
adjustment of the deposition rates.
18
16
14
12
10
0
20
40
60
80
100
120
Hydrogen gas flow [sccm]
voltage is always below 25 V which was
determined as a safe limit for damage-free
plasma cleaning. Figure 5 illustrates how
the addition of hydrogen to the argon
discharge changes the anode voltage.
The diagram also demonstrates that the
anode voltage does not vary over a large
hydrogen flow range. Therefore, the
cleaning rate can be changed without
drastic increase in the anode voltage. In
contrast to etch rates, the cleaning rates
are only in the range of 0.5 nm/s. These
Figure 6: LEPECVD module: The discharge characteristics
UA(IA) for different argon gas flows. Despite the different
design of the LEPECVD module, its discharge characteristics
allow – as in case of the LEPC module – the utilization of a
wide range of anode currents and argon flows.
rates are sufficient to remove the native
oxide and hydrocarbons from the surface
of a silicon wafer within a few minutes.
The main focus of this process, however,
is the damage-free preparation of the
single crystalline silicon surface for
epitaxial growth at low temperature.
Low energy plasma enhanced
chemical vapour deposition
The design of the deposition chamber
differs from those of the LEPC module.
The reason for this are material issues
to ensure the compatibility with the selfcleaning procedure. Figure 6 shows an
example for the UA (IA) characteristics
of an argon discharge in the new
Targets for process development
The system is utilized for our own process
development and related customer
sampling. The in-house process
development will focus on process steps
supporting SiGe-CMOS, especially for
the production of thick, linearly graded,
completely relaxed buffers for VS. An
important issue is the characterization of
LEPC in combination with homo and
hetero epitaxial growth of Si and SiGe
layers. It is the intention to realize a
completely dry process sequence – i. e.
without wet chemical wafer treatment – for
this application. The high-speed growth of
Si and SiGe amorphous and polycrystalline
layers at low temperatures is yet another
challenge for process development.
For more information please contact:
[email protected]
Discharge characteristics in the LEPECVD module
Anode voltage UA [V]
24
Ar flow
30 sccm
40 sccm
50 sccm
60 sccm
70 sccm
80 sccm
22
20
18
16
14
12
10
8
10
15
20
25
30
Anode current IA [A]
35
40
50
References
1 K. Rim, S. Koester, M. Hargrove, J. Chu,
P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim,
M. Ieong, A. Grill, and H.-S. P. Wong, Strained
Si NMOSFETs for High Performance CMOS
Technology, VLSI 2001 Kyoto Conference
Proceedings, 2001
2 H. von Kaenel, Using LEPECVD for SiGe,
Chip 2, Business & Technical News from Unaxis
Semiconductors, 1999, p. 32 or online at
www.semiconductors.unaxis.com
3 J. Ramm, Low Energy Plasma Processing for
Hetero CMOS in a 300 mm Single Wafer Cluster
Tool, Chip 5, Business & Technical News from
Unaxis Semiconductors, July 2001, p. 24 or
online at www.semiconductors.unaxis.com
Unaxis Chip | 29
Advanced Silicon
Customer-Oriented Process
Development for SiGe Deposition
The SIRIUS® UHV-CVD system
For more than one year the CVD lab in
Trübbach/ Switzerland has been active
in demonstrating the advantages of the
SIRIUS® UHV-CVD system for deposition
of HBTs and other SiGe/Si structures.
We have been able to prove the very high
throughput of the system combined with
a low growth-temperature which results
in reduced cost of ownership. The low
growth-temperature of the SIRIUS®
system opens other fields of applications,
very importantly the possibility to process
pre-structured wafers besides blank
substrates. Other structures successfully
demonstrated on the SIRIUS® system are
relaxed buffers with low germanium
concentration.
Figure 1: Thickness
distribution of a
poly-crystalline Si
layer obtained by
model simulation to
data from spectral
ellipsometry in 69
equidistant points
on a 200 mm wafer
10
ThPolySi
8
Mean nm = 236.765
Min nm = 231.460
Max nm = 240.370
Std dev = 1.735
Uniformity = 0.73 %
240.4 nm
238.9 nm
237.4 nm
235.9 nm
234.4 nm
232.9 nm
231.5 nm
6
4
Y in cm
Dr. Carsten Rosenblad, Process Physicist, High Speed
Silicon, Dr. Hans Martin Buschbeck, General Manager
Strategic Business Unit High Speed Silicon
2
0
–2
–4
–6
–8
–10
–10
–5
30 | Chip Unaxis
5
10
Figure 2:
Sheet resistance
(Rs ) uniformity as
obtained by resistivity
measurement
mapping: 1%
Uniformity calibration
The SIRIUS® UHV-CVD system is a
200 mm substrate batch system. The issue
of uniformity across the whole wafer and
the wafer-to-wafer uniformity are of crucial
importance for production. To investigate
the uniformity of thickness and of B
concentration a number of Si, SiGe and
doped structures were deposited, and the
thickness and the B concentration
were measured by spectral ellipsometry
and sheet resistance measurement
mapping.
One wafer uniformity
Thickness uniformity: The thickness
uniformity of a poly-crystalline Si layer
deposited on a 200 nm oxide is shown
in Figure 1, where we obtain a uniformity
of less than 1%. The uniformity is in this
case defined as the standard deviation
divided by the mean value.
0
X in cm
Sheet resistance uniformity:
Figure 2 shows the uniformity of the sheet
resistance. Here we obtain a value of
approx. 1%. From the observed geometry
of the sheet resistance distribution, which
matches that of the thickness distribution,
we infer that the main contribution to
the change of sheet resistance across
the wafer originates from the distribution
in thickness. This means that the
uniformity in resistivity, which is the
product of the thickness and the sheet
resistance, is expected to be even better
than 1%.
SIRIUS® UHV-CVD
production system
Thickness of poly Si [nm]
Figure 3:
Improvement of
thickness uniformity
over the batch
250
200
150
100
after auto-profiling
50
after GR calibration
0
W1
Thickness uniformity: For thickness
uniformity calibration, an iterative process
of growth rate calibration was executed.
We measured thickness of poly Si layers
grown on SiO2 wafers in extreme
positions of the batch. In fact, the wafers
W1 and W5 are positioned outside the
batch of 25 product wafers. Table 1
shows the excellent batch uniformity of
0.5%. Figure 3 illustrates the
improvements to earlier calibrations.
Sheet resistance uniformity:
Additionally, the uniformity of the sheet
resistance (Rs ) over a batch has been
quantified. Again five wafers from the
batch have been picked, including the
extreme wafer positions (W1 & W5).
Rs uniformity on one wafer was around
1% (Figure 2 and Figure 4). Wafer-towafer uniformity of Rs over the whole
batch is 3%.
W3
W4
W5
Wafer
Calibration of growth rates
and alloy composition
The deposition of epitaxial material on
a Si substrate consists of the following
four parts:
쐍 Transport of the gaseous hydrogenic
growth-precursor to the surface
of the wafer
쐍 Absorption of the precursor
on the surface
쐍 Desorption of hydrogen
쐍 Diffusion of the growth-precursor
on the surface to a crystal surface site
After growth rate
calibration
It has been shown that for temperatures
relevant to UHV-CVD ( T < 600°C) the
desorption of hydrogen from the surface
Thickness W1 [nm]
211.3
Thickness W2 [nm]
214.2
Thickness W3 [nm]
213.2
Thickness W4 [nm]
213.7
Thickness W5 [nm]
213.9
min [nm]
211.3
max [nm]
214.2
(max – min)/(max+min)
0.7%
mean [nm]
213.3
Uniformity
0.5%
mean
170
1,4
uniformity
160
1,2
150
1
140
0,8
130
0,6
120
0,4
110
0,2
100
Uniformity on
one wafer [%]
Batch uniformity
To verify the throughput advantages of
the SIRIUS® system for growing SiGe
profiles for the SiGe HBT calibration work
was necessary to show the excellent
uniformity of the system for wafer-towafer uniformity over a whole batch of
25 product wafers.
W2
Table 1: Thickness
variation of Si grown
on SiO2 of 5 wafers
after growth-rate
calibration; wafer
positions including
extreme positions of
25 production wafer
batch; thickness
measurement with
ellipsometry
Figure 4:
Sheet resistance
uniformity of a batch
of wafers and across
each wafer
0
W1
W2
W3
W4
W5
Wafer
Unaxis Chip | 31
Ge concentration in the solid as a
function of the SiH4 /GeH4 gas mixture
The Ge composition of the deposited
alloy is a function of the SiH4 / GeH4
mixtures for a fixed temperature.
An imported given material parameter is
the Ge composition, which must then be
set by adjusting the germane and silane
flow according to a calibration. A typical
calibration of the Ge composition of epitaxial
SiGe alloy layers grown is shown in Figure 5,
demonstrating the Ge composition of
an epitaxial SiGe layer as a function of the
germane flow for a fixed SiH 4 flow of
25 sccm. It should be noted that the
germane source gas is diluted by 1:20 in
He, i.e., for a GeH4/He-flow of 100 sccm,
the actual flow of GeH4 is 5 sccm.
The fraction of Ge in the layers was
determined by high resolution X-ray
diffraction (HR-XRD) and by secondary ion
mass spectroscopy (SIMS). From Figure 5
we deduce a linear relationship between
the flow of germane and the Ge
composition in the alloy. The linear
relationship also holds for other flows of SiH4.
32 | Chip Unaxis
Ge composition on [%]
45
40
35
30
25
20
15
10
5
0
0
20
40
60
80
100
GeH4/He-Flow [sccm]
6
Intensity [a.u.]
is the growth-rate limiting process [1]. The
growth process changes as a function
of the nature of the surface, e.g., the
hydrogen desorption from a SiGe surface
is faster than from an Si surface. In
addition, the hydrogen desorption rate is
a rapidly increasing function of increasing
wafer temperature. This translates into a
strong growth-rate dependence of the
temperature and the alloy composition.
Hence, it is unavoidable to systematically
determine the growth-rate of Si and
different SiGe alloys at the growthtemperatures of interest for epitaxial
growth experiments. In the following
we have concentrated on one specific
growth-temperature of 550°C.
Figure 5: The
composition of a
SiGe alloy grown at
a temperature of
550°C for a fixed
flow of SiH4-flow
of 25 sccm. The Ge
composition was
determined by
HR-XRD and by SIMS.
SiGe NP
SiGe/Si MQW
Si
SiGe TO
4
Si TO
2
SiGe
TA
Si NP
0
0.8
1.0
Energy [eV]
Assessment of high crystalline
quality and low defect density of
UHV-CVD grown layers
Photoluminescence (PL) analysis is a
powerful technique for the assessment
of material quality. Figure 6 shows the
photoluminescence resulting from a
UHV-CVD synthesized 10 period SiGe/Si
multi-quantum well (MQW). The existence
of an intense and sharp SiGe peak for i.e.
no-phonon (NP) recombination indicates
no or very low defect densities. The
sharpness of the peak implies that the
thickness for the SiGe layers in the MQW
was very well reproduced.
Overall, from the high intensities and
the existence of the PL signals we infer
that the volume density of recombination
1.2
Figure 6: Intensity of
photoluminescence
of UHV-CVD grown
Si/SiGe multiquantum well
[10 periods Si 0.85 Ge 0.15
(4.4 nm) / Si (9 nm)].
The luminescence
signal from the UHVCVD structure has
been compared to
that resulting from a
Si substrate. The PL
was performed at
the “Laboratorium
für Nanotechnologie”,
Paul Scherrer
Institut, Villingen,
Switzerland [2].
centers (point defects, metallic
contamination) for the excitons must be
very low, and the lifetime of the charge
carriers is high.
In addition, the absence of a broad
band of luminescence in low energy areas
(~0.8 eV) of our spectrum is proof for the
absence of defects in our grown layers.
For more information please contact:
[email protected]
References
1 B.S. Meyerson, K. J. Uram, F. K. LeGoues,
“Cooperative growth phenomena in
silicon/germanium low-temperature epitaxy,”
Appl. Phys. Lett. 53, 2555 (1988)
2 D. Grützmacher, Private Communication
and Measurement
Advanced Silicon
New Trends in SiGe Technology
Carbon-doped heterojunction bipolar transistors –
enhancing the capability of SiGe technology
Dr. Bernd Tillack, Manager Process Research, IHP, Frankfurt (Oder), Germany
and Prof. Dr. H. Jörg Osten, Department Head Breakthrough, IHP, Frankfurt (Oder), Germany
The incorporation of low concentrations of carbon (< 10 20 cm–3) into the
SiGe region of a heterojunction bipolar transistor (HBT) can significantly
suppress boron outdiffusion caused by subsequent processing steps.
This effect can be described by coupled diffusion of carbon atoms and
Si point defects. We discuss the increase in performance and process
margins in SiGe heterojunction bipolar technology by adding carbon.
SiGe:C HBTs demonstrate excellent static parameters, exceeding the
performance of state-of-the-art SiGe HBTs. C also enhances the high
frequency performance, because it allows the use of a high B doping
level in a very thin SiGe base layer without outdiffusion from SiGe, even
if post-epitaxial implants and anneals are applied.
The present interest in the application
of SiGe heterojunction bipolar transistors
(HBTs) stems from their potential
applications in integrated circuits
operating at radio frequencies. Highperformance SiGe devices are important
for use in ICs operating at frequencies
of up to several GHz, such as in
mobile phones, where their low power
consumption is an important advantage.
Relatively costly GaAs processing has
already met competition from silicon and
SiGe products. SiGe:C devices will push
further into cost-critical market fields.
One of the key problems in npn
SiGe technology is to retain the narrow
as-grown boron profile within the
SiGe base layer during post-epitaxial
processing. Heat treatments and
transient enhanced diffusion (TED)
caused by annealing implantation
damage can broaden the profile into
the adjoining Si regions [1]. This can
cause undesirable conduction band
barriers, and thus significantly degrade
device performance. A way to reduce
TED effects is to use a complex, and
hence expensive double-polysilicon
transistor construction. Another solution
is to grow extended undoped Si1–xGex
spacer layers between the p+ Si1–xGex
and the emitter and collector layers.
However, the thickness of the SiGe layer
and therefore of these spacer layers must
be minimized to avoid strain-induced
defect formation.
The IHP approach incorporates carbon
into the epitaxial base layer of the SiGe
HBT to suppress boron outdiffusion [2].
TED can also be strongly reduced by
incorporating carbon into the SiGe base
layer. The diffusion coefficient of boron
in silicon can be reduced by more than
one order of magnitude when the
concentration of substitutional carbon
is raised to about 1020 atoms /cm3 [3 – 5].
The suppression of boron diffusion in
SiGe:C has been explained by the
coupled diffusion of carbon atoms and
point defects in silicon. Boron diffusion
in silicon happens via an interstitial
mechanism. The effective diffusion
coefficient is proportional to the
normalized concentration of selfinterstitials. The diffusion of carbon
from carbon-rich regions results in
undersaturation of silicon self-interstitials
in these regions, and hence in the
suppression of boron diffusion [6].
We demonstrated that transistors
with excellent static and dynamic
parameters can be fabricated with
epitaxial SiGe:C layers [2–7]. The main
result of these investigations was that
carbon supersaturation can preserve
steep doping profiles without degrading
fundamental transistor parameters. As
a result, the RF performance can be
improved markedly. Compared to SiGe
technologies, the addition of carbon
provides significantly greater flexibility in
process design, offers wider latitude in
process margins and improves scalability
of the transistor [3].
The SiGe:C base of the HBT is
deposited by Reduced Pressure CVD
(RPCVD) in a commercial single-wafer
system. The excellent manufacturability
of the SiGe:C epitaxy process is
demonstrated by device data.
The HBTs were fabricated in a costeffective, epi-free well, single-polysilicon
technology [5] using highly doped,
narrow base layers. This transistor
construction is especially vulnerable to
performance degradation caused by
enhanced boron diffusion. Therefore, it
is an ideal candidate to demonstrate
the advantages of carbon incorporation.
Unaxis Chip | 33
Advanced Silicon
SiGe:C
SiGe
Ge
Ge
21
B concentration [cm–3]
10
20
10
Si
19
10
B
B
18
10
17
10
16
10
0
100
200
300
400
Depth [ m]
Figure 1: SiGe/Si/SiGe:C/Si model stack after
thermal treatment demonstrating suppression
of B outdiffusion by C
2.5
Ge 20%
C concentration [%]
SIMS
XRD
2.0
1.5
High C Level
1.0
0.5
Low C Level
0.0
500
550
600
650
700
Growth Temperature [°C]
Figure 2: Substitutional (XRD) and total C (SIMS)
concentration as function of the deposition temperature
at low and high C concentration level (constant C source
gas partial pressure for each level)
34 | Chip Unaxis
Figure 1 demonstrates the impact of the
C on B diffusion. A model stack consisting
of SiGe/Si/SiGe:C/Si was deposited. B
doping was identical for SiGe and SiGe:C.
After a high temperature anneal or
implantation and anneal (not shown here)
the B profile is unchanged in SiGe:C
and outdiffused in SiGe. Based on our
understanding of the physics behind
suppressed dopant diffusion, only the
substitutional C has a significant impact
on the suppression of boron outdiffusion.
Therefore, the optimization of the epitaxial
process regarding the C incorporation
is essential for the enhancement of
device performance. In Figure 2, the C
concentration measured by SIMS and
X-ray diffraction (XRD) is shown as
function of temperature for two different
C source gas partial pressures. The
substitutional C (XRD) concentration
decreases with increasing temperature
and increasing total C concentration.
Nevertheless, at the low concentration
levels necessary for suppression of B
diffusion in the HBT, most of the C is
incorporated substitutionally.
Figure 3 shows the RSbi (internal base
sheet resistance) wafer histograms for two
different doping levels of the SiGe:C base.
We obtain excellent uniformity of RSbi for
both doping levels. This is especially
remarkable taking into consideration that
the B doping had to be performed as a
spike within a very narrow SiGe:C base
(about 25 nm thick). Device data
demonstrates that the high B concentration is within the narrow base after
processing. In Figure 4, the histogram of
the HBT collector current is presented for
the doping levels used in Figure 3.
Regarding the epitaxy, this parameter is
sensitive to fluctuations during the
deposition of the Si/SiGe:C, which
may cause HBT base profile deviations.
For both doping levels we obtain
deviations smaller than ±10%. The results
demonstrate the excellent capability of
the IHP RPCVD epitaxy process and tool
for the SiGe:C HBT technology.
We further investigated the possible
impact of carbon on electrical layer
properties in ternary layers containing
carbon far above the solid solubility limit.
The influence of the low carbon
concentration needed to suppress
boron diffusion on band alignment is
negligible [8]. A comparison of the
measured sheet resistances with the total
boron concentration for two identically
boron-doped SiGe layers with and without
a C background led to identical results [3].
The concentration of electrically active
boron is not affected by carbon introduction.
IHP has demonstrated the first modular
integration of SiGe:C HBTs into a 250 nm
epi-free, dual-gate CMOS-compatible
platform. This module fully uses
the advantages of carbon, including
suppressed boron diffusion and increased
thermal and processing stability [7]. Key
parameters of the standard HBT module
used for prototyping are shown in Table 1.
RF data for high performance HBTs
substantially exceeding 100 GHz were
presented during the IEDM (International
Electronic Device Meeting) 2001 [9]. The
development of a 0.18 µm SiGe:C RF
BiCMOS technology is ongoing.
Acknowledgements
The authors thank the IHP staff and the
technology team for their excellent support.
For further information please contact:
[email protected]
No. of
measured structures
6
(1.70 ± 0.07) kΩ
(3.05 ± 0.10) kΩ
4
2
Wafer 1
Wafer 2
0
1.60
1.70
1.80
Figure 3: Wafer
histograms of the
SiGe:C HBT internal
base sheet resistance
(RSbi) for two
different base doping
levels (24 sites of an
8” wafer)
2.90
RSbi [kΩ]
3.00
3.10
3.20
2
AE = 10 x (0.42 x 0.84)
10
(2.03 ± 0.11) 10–5A
No. of transistors
8
VBE = 0.7 V
VCB = 0 V
T = 304 K
(1.48 ± 0.14) 10-5A
6
4
2
Wafer 1
Wafer 2
0
1.25 1.45 1.65 1.85 2.05 2.25
Dr. Bernd Tillack
is responsible for
the process module
development within
the technology team
of IHP. He is a chemist
and received his PhD
from the University
Halle-Merseburg in
1980. In 1981 he joined
the IHP as a staff
member of process
technology. He had
been the project leader
of different IHP projects.
Within the currently
running IHP SiGe
program he has been
responsible for the
development of the
SiGe/SiGe:C epitaxy.
Since 1998 he is in
charge of the process
research department.
Prof. Dr. H. Jörg Osten
is currently in charge of
the Breakthrough
Department at IHP and
also leads a project to
develop alternative,
high-K dielectrics. He
received his PhD at
the Institute for Physical
Chemistry of the
Academy of Sciences
in Berlin. In his later
career he worked at
the University of Illinois
in Chicago, and at
Cambridge University.
In 1987 he was
appointed professor
of physical chemistry
at the Academy of
Sciences. He joined
the IHP in 1988. From
1997 to 2000, he
was responsible for
the heterojunction
bipolar technology
development at IHP,
leading to a low-cost
HBT module with
SiGe:C base. He also
managed the transfer
of that module into
production at Motorola.
HBT collector currentent [10 –5 A]
Parameter
0.25 µm (standard process)
High
performance
High voltage
AE (µm )
0.42 ҂ 0.84
0.42 ҂ 0.84
Peak fmax (GHZ)
95
90
Peak fT (GHZ)
80
55
BVCEO (V)
2.4
3.2
BVEBO (V)
4.5
4.5
BVCBO (V)
6.0
9.0
β
150
150
VA (V)
50
90
NFmin (dB)
0.8
0.8
Assoc. Gain (dB)
17
17
2
Figure 4: Wafer
histograms for the
HBT collector current
for two different base
doping levels (24 sites
of an 8” wafer)
Table 1:
Key parameter of
the IHP SiGe:C HBT
module, fabricated
in a 0.25 µm BiCMOS
process
References
1 E. J. Prinz et al., IEEE Electron Device Lett. 12
(1991), 42.
2 H. J. Osten et al., IEDM Techn. Dig. (1997), 803
3 H. J. Osten et al., Proc. BCTM (1999), 109
4 D. Knoll et al., IEDM Techn. Dig. (1998), 703
5 D. Knoll et al., Proc. 28th ESSDERC, (1998), 142
6 H. Rücker et al., Appl. Phys. Lett. 74 (1999), 3377
7 K. E. Ehwald et al., IEDM Techn. Dig. (1999), 561
8 H. J. Osten, J. Appl. Phys. 84 (1998), 2716.
9 B. Heinemann et al., to be published
at IEDM 2001
Unaxis Chip | 35
Advanced Silicon
The Photomask
Success Story
Michael D. Archuletta, General Manager
Strategic Business Unit Photomask
The recent introduction of the new Unaxis MASK ETCHER III™ ICP
dry etch system, caused a veritable revolution in the global photomask
industry, which resulted in an enormous increase in mask etcher equipment
sales for Unaxis. The teamwork behind this technology development and
subsequent sales achievement are a great success.
Unaxis dry etch system sales have
nearly doubled in each of the past two
years, and because of the worldwide
acceptance of the MASK ETCHER III™
as the de-facto dry etch production
standard, the year 2001 was a true
highlight for the Unaxis Photomask
Business Unit.
The Unaxis MASK ETCHER™
evolution
In 1995, Unaxis developed and
introduced the MASK ETCHER I™,
a plasma dry etch system designed
specifically for etching chrome on quartz
plates. The dry etch process for chrome
on quartz was clean and extraordinarily
accurate. Dry etched masks tested by
the wafer fabs provided superior feature
resolution, improved level-to-level overlay
and ultimately higher device yields. By
early 1998, device manufacturers began
specifying that all critical mask layers be
“dry etched” in order to provide the
necessary feature control specifications
required by the demands of their
constantly shrinking device designs.
This moved ICP dry etch mask making
into full production, driving a significant
increase in the sale of Unaxis
MASK ETCHER™ systems.
36 | Chip Unaxis
The MASK ETCHER I™ was an
early success, but it was essentially a
wafer etching system converted to
handle square quartz substrates. Many
modifications to the initial design were
necessary to evolve the system into a true
photomask chrome etcher (Figure 1).
By 1998, Unaxis introduced the MASK
ETCHER II™, a much improved version
of our original offering. Early sales of the
MASK ETCHER I™ together with the
later design improvements lead to the
proliferation of the MASK ETCHER II™
through 1999 to every major captive and
merchant mask shop in the world.
Photomask technology
Along with 0.13 µm device production
came the need to produce masks to
support the 0.09 µm technology node.
This has forced the demand for even
better mask lithography technology
and most especially better dry etch
equipment. Our MASK ETCHER II™
system technology was good, but not
good enough to support sub-100 nm
technology requirements. We realized
early in 1999 that a revolutionary system
development was needed to sustain our
state-of-the-art lead in photomask
etching.
The biggest performance issue with
plasma dry etch is related to the amount
of exposed chrome on the plate that
makes up the circuit pattern for a given
device level. Each pattered layer in a
device has more or less circuit pattern
density depending on the operational
characteristics of the device at that level
(e.g. gates, contacts/vias, metal
interconnect, etc.). The pattern to be
etched on the photomasks will have more
(or less) chrome exposed to the etching
process depending on the density of the
pattern at that level. In mask making,
this is referred to as the chrome load of
the mask. Every mask level routinely has
a different chrome load ranging from
1% – 2 % up to as much as 70 % – 80 %
and everything in between.
This chrome load (or pattern density)
difference at each mask level presented a
problem unique to the ICP plasma etching
process. Our customers noted early on
that the process parameters (or process
recipes) on the dry etch system had to be
adjusted for each different chrome load.
Some mask levels with very low chrome
loads and others with high chrome loads
each required their own special set of
process parameters.
This issue was causing a severe
impact on dry etch performance
specifications and more importantly on
dry etch yield. It was possible for
customers to develop good process
etch conditions for very low-load parts
and different, but workable process
etch conditions for very high-load parts.
For the in-between or widely varying
chrome load parts, the process
set-up was mostly “hit and miss”
experimentation, usually at the expense
of many wasted parts (yield loss) while
Figure 1:
TM
The MASK ETCHER Evolution
MASK ETCHER I™
trying to develop a workable process
recipe that provided the requisite finished
performance specifications on the varying
chrome loads. Most mask shops reported
that this single chrome load related issue
was responsible for keeping dry etch
yields in the 50 % – 60 % range.
Generation III development program
The Unaxis Photomask Business Unit
research team spent several years
experimenting to understand the
fundamental etch mechanisms inside
our equipment that control chrome
load related etch performance. This
work was published in a series of papers
presented at several worldwide
photomask industry symposiums over
a period of three years from 1997 through
1999. The final paper in this series
was “Plasma Etch of Binary Cr Masks:
CD Uniformity Study of Photomasks
Utilizing Varying Cr Loads” by Dr. Chris
Constantine, Russell
Westerman and Jason
Plumhoff. The results of
this work formed the basis
for our Generation III mask etch
development program that ultimately
resulted in the MASK ETCHER III™.
The experimental work demonstrated
that mask etch critical dimension (CD)
uniformity is composed of both chrome
etch uniformity as well as resist etch
uniformity. The experimental data
confirmed that chrome etches in an
“outside in” pattern (where the outside
of the mask etches faster than the inside)
and is controlled by chemical diffusion
with the etching species being
electronically neutral. The Chlorine gas
used to etch the chrome appeared
primarily unaffected by the plasma,
meaning the chrome etch was dominated
by the neutral reactants within the plasma,
based on diffusion law (mass transport,
MASK ETCHER II™
species recombination rates at surfaces
near the mask, reactor geometry, and
reactor materials). On the other hand,
the resist etch showed an “inside out”
pattern (where the inside of the mask
etched faster than the outside) with the
resist erosion pattern being dominated
by the ion component of the electrically
charged plasma. The uniformity of the
resist etch was dependent on the overall
uniformity of the plasma. The revelation
was that these were two separate and
competing processes occurring simultaneously in the reaction chamber, each
affecting the overall etch performance
depending on whether the chrome load
was high (low resist load) or low (high
resist load).
Unaxis Chip | 37
Advanced Silicon
Unaxis Mask Etcher IITM
Baseline CD uniformity characterization
5% Cr load
“However, this theory provided the key
to understanding the direction
of our future development program.”
50% Cr load
+
Edge fast
Center fast
3σ = 30 nm
underetched
3σ = 29 nm
overetched
Figure 2: Overall
CD uniformity
of features on the
finished mask
Figure 3: ICP source
performance results,
comparison
Gen II /Gen III
Source: BACUS 1999
These were the reasons why different
process conditions were needed for
varying chrome loads and why using
the wrong process recipe for the wrong
chrome load led to poor specification
performance and yield loss in the existing
equipment set. This seemed simple
enough. However, it was not clear at first,
because a contradiction became
apparent when we measured the overall
CD uniformity of features on the finished
mask (Figure 2).
The CD uniformity measurement
plots are directly opposite of what was
expected. The illustration shows that the
5% (low chrome load) part has a CD
uniformity signature where the outside
has etched faster than the inside; this is
what we expected to see if the part was
all chrome. The 50 % (high chrome load)
part has a CD uniformity signature where
the inside has etched faster than the
outside; again, this is what we expected
to see if the part was all resist. The CD
uniformities are therefore “opposite” of
what was predicted based on the etch
mechanisms of the chrome and resist.
Although these discoveries were
somewhat disconcerting, the empirical
facts confirmed that low load CD
uniformity performance is controlled by
diffusion management and that high load
CD uniformity performance is controlled
by plasma uniformity.
Over three years of continuous and
dedicated experimentation by the Unaxis
photomask research group have yielded
these results and provided the key to our
future development program.
Throughout this time, we were
engaged in an ongoing program to
improve the plasma uniformity of our
Second Generation (Gen II) source and
its chamber hardware associated with
neutral species control. After some
extraordinary software modeling work by
our Photomask science team, we were
Generation III development project
New ICP source performance results
Gen II
Ion density profiles
ICP: 500 W
Gen III
Ion density profiles
ICP: 500 W
8 E17
7 E17
mTorr
50
20
10
5
2
6 E17
5 E17
4 E17
3 E17
2 E17
1 E17
0 E00
–25 –20 –15 –10
–5
0
–5
–10 –15
Distance from center [cm]
–20 –25
Ion density [/m3]
Ion density [/m3]
8 E17
38 | Chip Unaxis
able to develop a series of hardware
configuration changes that proved we
could sufficiently alter and improve the
neutral species etch of the chrome.
We quickly learned that the Gen II source
was incapable of the wide operating
conditions needed to significantly
improve the plasma uniformity enough to
provide good high and low load process
specifications at the same time. Langmuir
probe experiments indicated that the
best low power plasma uniformity we
could ever expect from our Gen II source
was approximately 25% uniformity
over a six-inch mask area.
By the end of 1999, it became obvious
we needed to launch a Third Generation
ICP source project (Gen III).
At the same time, customers were
also asking us to improve particle control,
pumping speeds, nine-inch mask
capability, and easier maintenance. It
became imperative that we have the
Gen III source and all other equipment
improvements available by January 1,
2001, to keep pace with the
semiconductor technology roadmap
7 E17
mTorr
50
20
10
5
2
6 E17
5 E17
4 E17
3 E17
2 E17
1 E17
0 E00
–25 –20 –15 –10
–5
0
–5
–10 –15
Distance from center [cm]
–20 –25
Figure 4: Factory
acceptance data
from the first MASK
ETCHER III™
Generation III development project
New ICP source performance results
and to take advantage of what was
expected (and proved) to be a strong
technology investment year in the
photomask industry.
We are pleased to report the
accomplishment of all our Gen III
development goals on schedule and
under budget. Furthermore, the resulting
Gen III source and process chamber
improvements have demonstrated
revolutionary new process performance
capabilities. An example can be found
in Figure 3. This chart shows a plasma
uniformity comparison between the
older and the new source.
The operational characteristics of the
Gen III source showed a marked plasma
uniformity improvement at a wide variety
of vacuum pressures. The Gen II’s plasma
uniformity averages > 25% over a six-inch
area, while the Gen III’s plasma uniformity
averages < 5% over a nine-inch area.
The new source supplies a much wider
operating window and the capability to
eventually etch nine-inch masks if
necessary.
MASK ETCHER III™
production system
The real proof of improvement is in the
finished mask etch performance
specifications. Figure 4 is a summary of
the factory acceptance data from the
first MASK ETCHER III™ production
system delivered in late December 2000.
The original contractual CD uniformity
specification for this system was 15 nm
(3 sigma). The customer insisted we etch
three different test masks, each with a
significantly different chrome load (1%,
50% and 80%). The new Gen III system
demonstrated “better than specified
performance” on all three test masks
1% Cr load
50 % Cr load
80 % Cr load
3 σ = 5.7 nm
3 σ = 8.9 nm
3 σ = 10.7 nm
One optimized system hardware set for all CR loads
All test masks were etched with the same process recipe
using identical Gen III hardware, the
very same process conditions and
independent of chrome load.
Cost of ownership
The value of this new system technology
is much more than improved mask
specifications. Being able to achieve
acceptable performance specifications
is important, but being able to do it with
a single set of process parameters is
extraordinary. Most importantly, it is now
possible to etch any mask with any
chrome load with almost any process
recipe without worry of yield loss.
We have constructed a general cost
of ownership model for our new
MASK ETCHER III™ and compared it
to a similar model developed several
underetched
overetched
years ago for the MASK ETCHER II™.
Our model is based on the calculations for
determining equipment value developed
for the wafer fab industry in the early
1980s by Wright, Williams & Kelly (WWK).
This has become the most widely
accepted model for determining tool cost
of ownership and we are using the more
recent 1998 WWK SEMI standard version.
The components in the tool cost of
ownership calculation are shown below:
* Cost of ownership (COO) =
fixed costs + operating costs + scrap costs
equipment life 쎹 throughput 쎹 yield 쎹 utilization
* Cost of ownership model: SEMI Standard © 1998 Wright, Williams & Kelly
Figure 5: Typical final
chrome structure
after etching on
customer test masks
Unaxis Chip | 39
The MASK ETCHER II™ and MASK
ETCHER III™ cost of ownership is
summarized in Figure 6. Mask making
is a capital intensive business with very
expensive operating costs. In the
comparison of the two systems you
can see why the MASK ETCHER III™
has become so popular. The price
is $ 300’000 higher, yet the MASK
ETCHER III™ provides higher yields.
Note that rise in yield equals a
cost-per-mask price dropping nearly $ 27.
Over the five-year life of the tool, that
represents enough savings to pay back
the $ 300’000 price difference.
You can only get about twelve plates
per day to the etcher because the
lithography systems are very slow.
So, every plate counts. Our example
shows what happens with a mere
increase in yield of just ten percent (10%).
In fact, most customers are reporting
a significantly higher yield than this from
their Mask Etcher IIIs. However, our
example fully illustrates the case with
just a 10% increase.
Figure 6: Cost of
ownership calculation
Description
Fixed cost
“Now is the time for
the MASK ETCHER IV™!”
The 70% yield factor in our calculation
represents only one additional plate per
day. One extra plate sells for an average
of $ 17’500. Over a year’s production, this
represents an increase in sales revenue
of approximately $ 4.35 million US Dollars.
That is more than twice the initial cost of
the new etch tool. This simply means the
Mask Etcher III™ pays for itself in less
than 6 months!
When buying Unaxis products the real
winners are always our customers!
Mask Etcher IITM
Mask Etcher IIITM
$ 1’500’000
$ 1’800’000
Operating cost (per year/2 shifts)
$ 198’000
$ 198’000
Scrap Cost (per year)
$ 144’000
$ 144’000
Equipment life (years)
Utilization % (90% uptime x 80% use)
5
5
72%
72%
Throughput (1PM-mask/hour {12 masks/day})
0.75
0.75
Yield % (usable or repairable masks)
60%
70%
$ 430
$ 403
Cost of ownership (per mask)
Total dry etch mask sales revenue (per year)
($ 17’500 per mask x 1,493 masks)
Total dry etch mask sales revenue (per year)
($ 17’500 per mask x 1,742 masks)
40 | Chip Unaxis
The MASK ETCHERTM III
Summary
The Unaxis MASK ETCHER III™ is the
first, true third generation photomask dry
etch tool. Its performance clearly provides
a generational leap over everything that’s
gone before, including our own earlier
versions of this tool technology.
Our customers have recognized this
new bench mark in the industry and
have shown their continued confidence
in Unaxis by placing purchase order
commitments for new MASK ETCHER III™
systems. The MASK ETCHER III™ has
helped to solidify Unaxis as the
undisputed leader in the development
and installation of state-of-the-art
ICP dry etch systems for the photomask
industry.
We would like to take this opportunity
to thank our customers and all of the staff
at Unaxis who helped to make the MASK
ETCHER III™ a reality.
This success story has encouraged
us to start development of the next
generation: MASK ETCHER IV™ waiting
to be made.
$ 26’127’360
$ 30’481’920
For more information please contact
[email protected]
Advanced Silicon
Non-volatile Memory:The Key
to Advanced Memory Devices
Almost 25% of the worldwide chip market
are memory devices, each type used for
their specific advantages: the high speed
of an SRAM, the high integration density
of a DRAM, or the non-volatile capability
of a FLASH memory device.
The industry is searching for a “holy
grail” of future memory technologies
to service the new upcoming market
of portable and wireless devices.
The next generation of cell phones
and mobile PCs are being advertised
in the media and we already seem to be
so familiar with them. But new wireless
devices for the end user market would
allow products like web tablets, two-way
pagers, PDAs, wearable computing,
micro-notebooks, or automotive
computing devices like telematics to
become as common in our daily lives as
mobile phones are today.
Of course, some of these applications
are already available based on existing
memory technologies, but for a
successful market penetration a much
higher performance at a lower price is
required.
So there is a need for a new memory
technology. Lower costs, lower power
consumption, non-volatile techniques,
and the new technology should be easy to
integrate into existing CMOS technology.
Comparing these requirements for future
memories with current memory devices,
we see that each of them has certain
limitations: DRAMs are difficult to integrate,
SRAMs are expensive and FLASH devices
are too slow and have a limited number
of write/erase cycles. EPROMs show high
power requirements and a poor flexibility.
Solid state will not challenge the disk before 2010
HD
MO
100
Capacity [GByte]
Dr. Reinhard Benz, Product Manager Silicon Front End
Notker Kling, General Manager Strategic Business Unit
Magneto Electronics
ROM
WORM/RW
10
MRAM
1
FLASH
0.1
0.01
1988
1992
1996
None of them combines features like:
쐍 The ability to retain stored charge
for long periods with zero applied
or refreshed power
쐍 High speed of data writes
쐍 Low power consumption
쐍 Large number of write cycles
2000
2004
2008
Figure 1: Memory technologies
market trends
Therefore, the whole industry is
investigating different advanced memory
technologies like MRAM, FRAM, OUM
or polymer devices, which we would like
to introduce to you in greater detail.
FRAM
The device of a ferroelectric RAM consists
of selected crystalline materials, typically a
crystal unit cell of perovskite PZT (PbO,
ZrO2, TiO2) = Lead-Zirconate-Titanate.
Data can be stored by applying a very low
voltage: the electric field moves the center
atom by changing the crystal orientation
Figure 2: Rocking curve of AlN
on Si showing piezo characteristic
together with stress and
uniformity optimization enabled
by the independent regulation
of bias voltage, power, and Ar2/N2
ratio on the CLUSTERLINE® 200.
Unaxis Chip | 41
Advanced Silicon
Motorola’s
AccompliTM 009
combines Tri-Band
GSM technology,
GPRS, e-mail, SMS,
and phone
functionality for
complete global
communication
capabilities.
of the unit cell. This results in a polarization
of these internal dipols “up” or “down”.
The first series FRAM products were
introduced by Ramtrom in 1994, followed
by several license agreements with
numerous semiconductors manufacturers (Figure 1). Today we find products
like 4 Mbit FRAMs (Samsung) and most
promising products like smartcards
(Matsushita) with the benefit of a much
higher write speed and which are
environmentally uncritical compared
to FLASH-EEPROMs.
Unaxis Semiconductors already has
extensive experience with piezo- and
ferroelectric layers like PZT and SBT.
Critical piezoelectric layers such as ZnO or
AlN have already been developed
for Unaxis CLUSTERLINE ® applications
(i. e. SAW filters or BAW devices). As
part of a European consortium which is
funded by the EU, Unaxis developed
the processes for piezo- and ferroelectric
layers in the MEDCOM project (IST-199911411) with outstanding results in terms
of stress control, small rocking curve, and
thickness uniformity (Figure 2). These very
critical and sensitive layer characteristics
are achieved by the independent
adjustment of chuck bias, pulsed
sputtering, and precise temperature
control. The outstanding vacuum
conditions of the PVD process modules
in the CLUSTERLINE® are essential for
the mostly reactive processes of the piezolayer as well as for the critical interfaces
to the layers of the top and bottom
electrodes. The lower deposition rate of
reactive processes leads to relatively long
process times. Therefore, a well-controlled
thermal coupling between chuck and
wafer and the vacuum conditions including
the right pump package are essential to
42 | Chip Unaxis
Calculated Co thickness reduction [nm]
Figure 3: Oxidation
test with Al thickness
variations
2,5
0.0 nm Al
2,0
over oxidation threshold
1.5 nm Al
1,5
1 nm Al
1,0
OXY source
1.25 nm Al
0,5
0,0
0
100
200
300
400
500
600
Exposure time [sec]
get extremely stable process conditions
for these layers. In-situ annealing in a
process module or RTP module is also
avilable on the CLUSTERLINE®.
MRAM
A magnetic RAM device consists of a
MTJ (magnetic tunnel junction) and a
transistor; the electric current switches
the magnetic polarity (spin), and this
change is sensed as resistance change.
These magnetic cells allow a high
density, very fast read and write speed
(< 50 nsec), and low power consumption,
as well as unlimited read /write endurance.
All these benefits make MRAM still one of
the most promising candidates to replace
existing DRAMs; only the compatibility
in terms of materials and the temperature
management make it difficult to integrate
MRAM into existing CMOS processes.
MRAM applications belong to the
strategic technologies within Unaxis. For
the past four years this market has been
a major focus of the Magneto Electronics
team who have had a head start with
Unaxis’ leading position in the thin film
head market. This team developed a
dedicated MRAM deposition system
and introduced a special new etch
process for MRAM cells. Working with
various industry partners as well as in a
worldwide university/industry network,
Figure 4:
XRD Spectrum of
Ge2Sb2 Te5 on
CLUSTERLINE ® 200,
sample no. 6 as
deposited, sample
no. 13 after anneal
250°C, 10 min
showing excellent
conformity with
theoretical values
OUM
To convert certain chalcogenide material
alloys between the crystalline and
amorphous phases by applying a certain
temperature has been a well-known
method for over 30 years and been used
in optical rewritable CDs and DVDs. An
area where Unaxis – with an installed
base of several hundreds of sputtering
systems – has a world market share of
over 80%. Instead of by laser, the energy
could also be applied by an electrical
pulse controlled by a single transistor.
In optical phase change cells, the signal
is given by the change of the reflectivity.
The resistance also changes dramatically
at the transition from the amorphous
to the crystalline phase. Such a device
was developed by ECD, licensed to
Ovonyx Inc. and is called Ovonic Unified
Memory (OUM).
Under several binary, ternary and
quaternary phase change alloys which are
described in literature, today GeSbTe
(GST) seems to be the most promising
target material for the manufacture of
OUM devices.
The biggest benefit of OUM seems to
be the easy integration into conventional
CMOS process technology for DRAM and
FLASH, also offering significant cost
The class 100 R&D
facility in
St. Petersburg
advantages (Figure 4). In spite of the
current downturn of the industry as a
whole, we expect the first series products
on the market in 2003. Unaxis will be well
prepared: With the CLUSTERLINE®
Unaxis also offers the synergies with its
Materials Devision that has a lot of
experience in different phase change
targets, and its Data Storage Devision
with the real phase change experts.
These synergies have existed since
1997 when Unaxis installed the first
CLUSTERLINE® 300 for a 300 mm phase
change disk application.
Figure 5: Phase
change of GeSbTe
measuring the
reflectivity as
a function of
temperature for
different electrode
materials
Reflectivity at 632 nm vs. annealing temperature
(GST, AITi + GST)
70
65
60
Reflectivity [%]
the Cyberite system family is considered
the state-of-art system for this particular
application, featuring the world’s smallest
footprint and multi-target design in one
process chamber. This construction
reduces expensive clean room space
and provides the lowest downtime
between different deposition steps.
UHV (10–10 mbar) vacuum conditions
are prerequisites to successfully produce
MRAM devices. Field proven deposition
sources combined with a sophisticated
deposition process provide very smooth
film surfaces. High magnetic bit yield
is the result of precise control of the
oxidation of an 8 –10 Ångstrom thin
aluminum layer into alumina.
Unaxis has extensive experience in
the deposition of ultra thin stacks for thin
film head SV/GMR structures (materials
like NiFe, CoFe, PtMn, IrMn, etc.).
This technology is leveraged for high
performance of magnetic thin film MRAM
stacks closely related to the thin film
head technology. Unaxis also provides
advanced dry etch technology that allows
corrosion-free patterning of the ultra thin
film deposited without contamination of
the critical tunnel layer. The etch process
can also be combined with an integrated
PECVD dielectric cap.
An integrated technology team in
our dedicated R&D class 100 facility in
St.Petersburg, Florida, is responsible
for the unique combination of advanced
deposition and dry etch processes in
Unaxis production solutions.
For more detailed descriptions
of the Unaxis metallization and etch
solutions for MRAM applications,
please refer to previous issues of Chip
(the online edition on our web site:
www.semiconductors.unaxis.com).
With features like
pen input, a large
touch screen, voice
and handwriting
recognition,
integrated digital
camera, GPS, or
bluetooth network
access, the WTC
Evita2000P from
Innolabs Corp. in
Taipei is a perfect
example for fast,
wireless, professional,
and mobile computing
(image: Innolabs
Corp.).
55
50
45
GST
40
AlTi + GST
35
30
0
50
100
150
200
250
300
Annealing temperature [°C]
Unaxis Chip | 43
CLUSTERLINE® 300:
sputtering bridge
tool on 200 mm and
300 mm wafers for
deposition of phase
change layers (GST)
including top and
bottom electrodes
Today Unaxis offers a bridge tool
solution for 200 / 300 mm wafers for
deposition of GST as well as the bottom
and top electrodes to form a OUM
memory cell.
The race is still open
FRAM, MRAM or OUM – who will make
the grade?
As you can see in Table 1, each
technology provides technical challenges
to be overcome, which are being examined
in intensive research programs at different
companies. Diversification seems to be the
name of the game, and each of the major
players has its own favorite (or two).
So, it looks like the race for the memory
technology our children will be using is still
open. At present we can safely say that a
total replacement of DRAM and SRAM
will not take place by 2003, although
some of the companies mentioned in
Table 2 claimed otherwise at the end of
the last century. With the emphasis on
portable/wireless devices, the required
endurance of memory is also under
discussion. A “limited” read/write cycle
would be more than sufficient for the
accepted lifetime of some of the portable
devices like cell phones, PDAs, etc.
44 | Chip Unaxis
“The perfect solution for the ultimate
memory technology still eludes us,
but – as they say – the race has only
just begun.”
FRAM
MRAM
OUM
Operation
쐍 Selected crystalline
materials have bistable center atom
쐍 Data is stored by
applying an voltage
to polarize the internal
dipoles
쐍 Non-linear FRAM
read capacitor
쐍 No iron, no
magnetism
쐍 Cell with one MTJ and
one transistor
쐍 Electric current
switches the
magnetic polarity
쐍 Change in magnetic
polarity sensed as
resistance
쐍 Electrical energy
converts the chalcogenide (phase
change) material
between crystalline
(conductive) and
amorphous (resistive)
phase
쐍 Cell reads be
measuring resistance
Advantages
쐍 Low power
consumption
쐍 Fast write
쐍 High density
쐍 Low power
쐍 Read/write speed
쐍 High density
쐍 Low power
쐍 Easy to integrate
Disadvantages
Limited read and write
cycles (1013 )
Material compatibility
with CMOS
Limited write/erase
cycles (1012 )
Industry proven /
analogies
In MEMS applications
FRAM chip available on
the market
Thin Film Head
(SV/GMR, TMR)
MRAM chips available
DVD, CD-R
FRAM
MRAM
OUM
Fujitsu
Hitachi
IBM
Infineon
Matsushita
Micron
Motorola
NEC
Samsung
Toshiba
Hynix
IBM
Infineon
Motorola
USTC
British Aerospace
Intel
Ovonyx
STMicro
Within the next few months we can
expect all three technologies to enter the
market with a dedicated product. Each
technology will find its place and grow
from there, we can already see a great
deal of diversification. One thing is certain:
non-volatile memory will make its way
and will eventually replace DRAM, SRAM,
FLASH, etc.
The dust of the first rush is settling, some
of the original participants have dropped
out and we are now entering the second
round. The perfect solution for the ultimate
memory technology still eludes us, but – as
they say – the race has only just begun.
For more information please contact:
[email protected]
Table 1:
Comparison of
the performance
of new memory
technologies
Table 2:
Companies
developing
memory
technologies
worldwide
Unaxis Insights
The Making of a Worldwide
Quality Management System
Werner Eisl, Manager Corporate Business Excellence
Helmut Ritter, Quality Manager
A knowledge network and its usage
have to be learned and experienced – this
networked process management system
is the classroom for Unaxis.
Apart from the obvious organizational
challenge the realization also requires
some technical solutions.
For us as a global IT equipment
supplier, any solution that meets customer
demands can only be achieved by
cooperating across geographical and
cultural boundaries. The greatest
challenge lies in making this management
system accessible and easy to use for
everyone. Our previous experience with
document management systems was a
great help in deciding upon the actual
requirements for an international quality
management system:
쐍 Worldwide, easy access for all locations
쐍 A representation of the processes
suitable for the Intranet
쐍 Quick access to the relevant documents
via the Intranet in German and English,
or other languages, if required
쐍 Fulfillment of ISO 9001: 2000
requirements
쐍 Maximum use of existing platforms
to avoid additional investment,
introduction, license, and adjustment
costs regarding release changes of
products from different suppliers
쐍 A system easy to maintain and update
to support the continuous improvement
and development of the management
system towards Business Excellence.
How it all began
With the introduction of the SAP R/3
system for economic and operational
processes and the creation of global
business processes at Unaxis we have
now undertaken the next step:
implementing a quality management
system which is applicable at all Unaxis
locations worldwide, easy to understand
and equally easy to use.
The Unaxis solution
There are plenty of products on the
market for the administration of quality
management documentation, but none
fulfilled our exact requirements. The result:
we rolled up our sleeves and got to work
on our own solution.
A first rough concept was developed
by the Quality Management Group, then
discussed with our IT specialists and
Increasing customer expectation can only be met by
comprehensive management systems. This notion has struggled to
be generally accepted in commerce and industry for 25 years.
Today it is taken as a matter of course that a systematic and
documented quality management system facilitates cooperation
and forms the basis for continuous improvement towards
Business Excellence – if it is designed to be user-friendly.
쐍 All Unaxis locations can directly
access and take advantage of the
best practices – we call them “Global
Processes” – and if one location
can improve on a process, all others
profit directly from that improvement
as well.
쐍 This network forms the backbone of
our knowledge management system,
which will be systematically extended
to also incorporate technology, product
know-how, customers, employees
and suppliers.
Figure 1: The process
overview of the
quality management
system in the Unaxis
Intranet
4 | Chip Unaxis
Helmut Ritter and his team have
achieved just that with the creation of
a web-based, worldwide process
management system. The Unaxis IT
divisions now have one of the most
modern and user-friendly process
management systems and will benefit
in the day-to-day application:
쐍 Increased quality and decreased cycle
time are two benefits that result directly
from the linking of processes and work
instructions with precise release control
in the SAP-system.
Figure 2: Documentation
structure. The quality
management system
start page is called up
via the Unaxis Intranet
homepage.
Intranet homepage
Start page
management documentation
Process model
Process overview
Process model
Overview
of all valid
documents
Process
description
(flow-chart)
Valid documents:
쐍 Work instructions
쐍 Forms
쐍 Checklists
checked for feasibility. After that, the
road was clear for the specialists to
proceed with the design and realization
of the IT concept. Intranet-suitable
representations of the processes were
compiled by the Quality Management
Group, and the user interface was
designed by an external company which
provided a very valuable contribution
to the project.
A first version was quickly finished, but
as always many details of operation
emerged during testing. It took longer
than expected – with a great deal of
dedication and determination by the
project management – to get the system
up and running. A lot of good will and very
hard work delivered the results in the end.
At this point, we would like to extend our
sincere gratitude to all involved in the IT
and Quality Management Departments for
their support. Together we managed to
find a solution by using existing platforms.
Similar concepts could be applied
to other areas where document
management and access to information
are important.
Easy access
The page with the process overview
of the management system (Figure 1)
is easily accessible for all employees via
the Intranet portal. Hyperlinks give access
to all required documents. A double click
brings the user to the process overview.
Just by clicking into the fields within the
graphic of the process structure, all main
and subprocesses can be accessed, right
down to work instructions, checklists, etc.
All process overviews can also be
accessed directly via the menu in the top
navigation bar.
Communication
E-mail buttons on the start page support
the direct communication – regarding
questions and improvement suggestions –
between user and process owner.
Any changes or updates to the system
are communicated periodically on the
start page of the management system.
Maintenance and administration
without programming knowledge
All documents are archived and releasecontrolled in the SAP R/3 document
management system. The links in the
Intranet, which call up the documents
from SAP, are programmed to call up only
the released version of the document. This
means that the release of a new version
also guarantees an up-to-date state on
the Intranet. Easy, isn’t it?
Unaxis Chip | 5
Advanced Silicon
Money for Nothing…
…and Chips for Free
by reducing initial target costs and increasing
material utilization on the Unaxis CLUSTERLINE®
Dr. Reinhard Benz, Product Manager Silicon Front End
Dr. Hans Hirscher, Manager Process and Application Silicon Front End
Currently, the main focus of the semiconductor industry is
on cost savings. The following article shows how running costs
can be reduced with the CLUSTERLINE ® system by using the
optimized sputtering source ARQ 131 for higher material
efficiency of the targets.
Cost of ownership figures clearly show
that the metallization cost for precious
materials like Au, Pt, and their alloys are
dominated by the target costs. Therefore,
the decision was taken to concentrate
further developments for the sputtering
source on improved material utilization.
Minimizing the target diameter, increasing
the transfer factor (amount of material
deposited on the wafer), extending the
target life, and decreasing the weight for
recycling will bring down the running
costs for expensive target materials.
The amount of initial target material and
the amount of material for recycling are
important factors with regard to the
reduction of bound capital.
Minimizing the recycling material is a
critical issue, especially for precious alloys
like AuAs, AuGe, AuSn, or PtSi. Until now
only the precious component of the
alloyed material deposited on the shields
and of the remaining target material at the
end of the target life have been recycled.
A slight improvement in lowering the
target recycling cost was achieved by
the recent development of an optimized
recycling process by Unaxis Materials
(see article “Gold Makes the Process”
by Carsten Rienecker, Sales Manager,
Unaxis Materials Hanau published in
Materials, July 2001).
Considering all these aspects, real cost
savings can mainly be achieved by
increasing the material utilization over the
total target life.
All investigations were focused on
expensive materials typically used for
front and back side metallization of
discrete Silicon wafers as well as for III-V
applications for telecommunications.
Products for both markets are mainly
manufactured on wafers with a diameter
of 150 mm or smaller; therefore a process
solution for wafer sizes from 100 up to
150 mm was developed.
Within Unaxis the sputter source
ARQ 131 is “the standard” in the sputter
tools of the Data Storage Division. It is
used in over 3’000 CD metallizers and
several hundreds of rewritable disk
systems (phase change and MO). This
source has been developed to coat
Figure 1: Au alloy target on the copper
backing plate
Figure 2: Improvement of target utilization by
optimization of the magnet system
Table 1: Geometrical differences between the
sputter sources ARQ 131 and ARQ 151
ARQ 131
ARQ 151
Target diameter (sputter material)
200
260
Typical thickness of sputter material
6 mm – 9 mm
9 mm – 12 mm
Thickness of the backing plate
6 mm
6 mm
Target-substrate distance
30 mm – 50 mm
50 mm
Ratio of diameters sputter material to 6" substrate
1.33
1.73
Ratio of the volume at 9 mm target thickness
1
1.69
Unaxis Chip | 45
Advanced Silicon
Figure 4:
Two ARQ 131s on a
CLUSTERLINE ® 200
showing Au alloy
targets
Figure 3: Improved
material utilization
using the optimized
magnet system B on
the ARQ 131 sputter
source
optical discs with a diameter of usually
120 mm. For the semiconductor
applications on 150 mm wafers, the
ARQ 151 is used as a standard.
Table 1 shows the geometrical
differences of the two sputter sources
and points out that 69% less target
material has to be invested in an
ARQ 131 compared to an ARQ 151
when a target thickness of 9 mm is
applied.
Therefore, the goal of the re-design
was to enable the use of the ARQ 131
in standard process modules of the
CLUSTERLINE ® for wafers up to 150 mm
while fulfilling all required properties for
plane layers.
Evaluation was focused on the
following issues:
쐍 Target utilization
쐍 Coating uniformity on the substrate
쐍 Transfer factor
The parameters for tuning are:
쐍 Target-substrate distance
쐍 Target diameter
쐍 Magnet system
Making the distance between the target
and the substrate smaller allows a
reduction of the target diameter. The
limitations for shrinking it even further are
the minimum space for the sputter plasma
and the increasing substrate temperature
(due to plasma heat load and target
temperature). Another limitation for
decreasing the target diameter lies in
the restricted possibilities of arranging
the magnets of the magnet system
in the given area.
Several optimization loops for the
magnet system layout were necessary to
verify an improvement in target utilization.
Computer simulations assisted in
calculating the effect of target diameter,
Initial weight 100 %
Mag. system A
on the
substrates
material on
the shields
weight for
recycling
utilization
23%
7%
70%
30%
target-substrate distance, and target
utilization. The simulation was then
paired with the practical experience for
the layout of magnet systems, as well as
with a corresponding simulation of the
magnetic fields.
In the lab, predictions for using a
copper target over a complete target life
were confirmed. In cooperation with
customers the benefit was then shown on
real gold alloy targets. The usable target
material was nearly doubled.
Figure 3 demonstrates the optimized
target utilization. It shows the target
material distribution with the original
magnet system A and, after several
experimental loops, with the optimized
magnet system B.
The compromise for improving the
material utilization is a slight decrease in
thickness uniformity. A typical value
achieved with the optimized ARQ 131
is ± 6% compared to ± 4% achieved
with the standard ARQ 151 over the
target life.
For further information please contact:
[email protected]
Mag. system B
46 | Chip Unaxis
38%
14%
48%
52%
Advanced Packaging
®
CLUSTERLINE –
Making 300 mm Possible
The transition to 300 mm wafer processing has been accomplished
Dr. Christian Linder, Manager Process and Application
Advanced Packaging, Wolfgang Rietzler, Product Manager
Clusterline, Hans Auer, General Manager Strategic
Business Unit Advanced Packaging
Over the last few years, some leading
IC manufacturers have accomplished the
transition to 300 mm wafer processing.
Amongst the most challenging key drivers
for the 300 mm technology are cost
reduction, larger production volume,
increased silicon utilization, high-level
automation, and enhanced reliability.
At the moment four production lines
are up and running, and another four
have been scheduled to commence
operation in 2001 followed by another
eight which are planned to start beyond
2001 (source: Solid State Technology,
May 2001).
Most 300 mm fabs are focused on
front end production, but a few are
beginning to extend their activities
to back end applications on wafer level.
The major assembly and packaging
companies have now become
active also in this field.
In recent years, wafer level packaging
(WLP) using bumping technology for flip
chip has emerged as a new and important
concept in advanced packaging. While
the technology so far has been used
mainly for high I/O (microprocessor,
high-end logic) and high-frequency
devices, promising applications for the
future are also higher volume devices,
Figure 1: PVD
process modules
with excellent
performance for
outstanding film
characteristics
Unaxis Chip | 47
Advanced Packaging
such as DRAMs. SRAMs, ASICs and
passives are expected to follow this trend.
With the move to 300 mm, WLP technology becomes even more attractive for
back end processing since the majority
of the early 300 mm production is
intended for high-end devices. In addition,
Table 1:
Cost of ownership
calculation for the
CLUSTERLINE® 300
Description
Operating cost (per year)
Scrap cost (per year)
Utilization
Total throughput (wafers/year)
Yield
Cost of ownership
(average per yielded wafer)
48 | Chip Unaxis
CLUSTERLINE® 300
$ 523’000
$ 60’000
72%
349’440
95%
$ 4.93
a strong shift from traditional
packaging to advanced packaging can
be observed.
CLUSTERLINE® 300 for WLP
The major bumping process steps
include underbump metallization (UBM)
or redistribution (RDL) using physical
vapor deposition (PVD), photolithography,
electroplating, stencil printing, metal
wet etching, resist stripping, as well
as reflow of the bump. Based on the
excellent collaboration with other leading
equipment manufacturers for associated
back end processing, Unaxis offers highly
sophisticated solutions with full process
compatibility resulting in high yield.
By employing the CLUSTERLINE®,
UBM and RDL sputtering processes
for advanced packaging have been
successfully performed for several years
Figure 2: The
CLUSTERLINE® 300
design provides
excellent accessibility
for easy maintenance.
in 150 mm as well as 200 mm production
at various leading packaging companies.
Significant assets of the new
CLUSTERLINE® 300 are:
쐍 Straightforward extrapolation to
300 mm applications
쐍 Excellent process performance for
outstanding film characteristics
쐍 Bridge tool configuration enables
processing of 200 mm as well as
300 mm wafers
쐍 High throughput due to short process
times
쐍 Thin-wafer handling and processing
capability
쐍 Substantially lower cost of ownership
than for front end single wafer PVD
systems
Sputtering targets for the CLUSTERLINE®
300 can be delivered by various material
suppliers. Currently, all process specifications are based on targets from Unaxis
Materials. The long-term collaboration
between Unaxis Materials and Unaxis
Semiconductors has greatly supported
the successful development of this new
generation of large 400 mm targets with
narrow tolerances in purity and structure
properties. The R&D team for sputter
sources has reached excellent results with
the new cathode design and by optimizing
the magnet system for best target utilization.
The process must fit the application
Regarding technology performance,
the UBM and RDL applications of the
CLUSTERLINE® meet several
requirements for optimum integration
into the bumping process flow. A typical
sequence starts with a clean-etch step
using an ICP source which induces no
damage to the pre-fabricated dies on
Unaxis Chip | 49
Figure 3: Sheet
resistance
distribution
for a Cu film
on a 300 mm
oxide wafer;
the uniformity of
1.6 % (1 sigma)
is typical for an
UBM application.
50 | Chip Unaxis
the wafer. This etching removes native
oxides and other materials such as
organic residues from the wafer surface.
This way the subsequent metal films (first
metal of the UBM/RDL stack, e.g. Ti or Al)
achieve a low contact resistivity to the
metal pads of the dies and an optimum
adhesion to the pads, as well as to the
passivation layers on the wafer surface.
Next, barrier metal films such as
NiV or TiW are deposited preventing
diffusion of the bump metals to the die
metals. The top metals of the UBM
stack are used as seed layers e.g. for
subsequent plating (Cu, NiV, or Au), or as
wetable material for the solder of printed
bumps. In the case of RDL, the top metals
serve as the conductive interconnect lines
(e.g. Al, Cu).
Precise control of process parameters
combined with the perfectly adjusted
design of module components of the
CLUSTERLINE® (e. g. chuck configuration)
guarantee optimum film characteristics.
For example, electrical film properties can
be tuned for lowest possible resistivity at a
given maximum process temperature as
well as for appropriate uniformity. This
enables precise metal wet etching or
homogeneously distributed plating current
for uniform bump heights. Furthermore,
depending on the film material, the
Figure 4: 400 mm bonded AI target
mechanical stress can be specifically
controlled by means of process power,
gas flow, temperature, or RF bias. The
result are low-stress film stacks providing
mechanical stability which is needed for
the long term reliability of the bump
structure.
More to come – stay with us
Close partnerships with leading device
manufacturing firms and expert
equipment manufacturers have played an
essential part in the successful operation
of the CLUSTERLINE® in production.
Currently, the CLUSTERLINE® 300 is
being implemented in the first 300 mm
wafer bumping fab of one of the world’s
largest providers of semiconductor
packaging and testing services. Unaxis
has extensive experience in WLP and
related fields, and is participating in
ongoing installations of further
300 mm lines for advanced packaging
applications.
Figure 5: Open
process module of the
CLUSTERLINE® 300
For more information please contact:
[email protected]
Advanced Packaging
The Advantages
of Integrated Passives
Dr. Johann P. Seidel, Senior Scientist PVD, Andreas Huegli, Process Engineer CLC,
Hanspeter Friedli, Process Engineer LLS, Heinz Gloor, Product Manager LLS,
Hans Auer, General Manager Strategic Business Unit Advanced Packaging
Market demand for higher performance and more compact
electronic products (mobile phones, PDAs, digital cameras, etc.)
is behind the integration of passive components such as
resistors, inductors, and capacitors. Especially the requirement
for high-frequency signal handling and the integration of optical
signals into electronic packages are a major driving force for
the integration of passives into various devices.
Because of their advantage in
performance, size and assembly cost,
integrated passive devices (IPDs) are yet
another booming area of advanced
packaging. Many of today’s electronic
products feature 500 or more passive
devices, making conventional packages
and board assemblies a problem in terms
of performance, yield and cost. IPDs
typically combine a number of passive
components (resistors, capacitors, and
inductors) in a single package. These
devices are increasingly built on glass thin
film substrates rather than on silicon-like
semiconductor devices or ceramic which
is very high in cost. The IPD is ideally
combined with wafer level packaging –
yielding minimal size and low costs,
since there is no longer a need for a
conventional plastic package.
Another way to integrate passives is
to build them right into the high-density
substrates – as integrated passive
modules (IPMs). While the process
technology is identical to IPD, the
integration of the passives into the
substrate has the advantage that no
extra space is needed for the passives
and the assembly step of the devices is
eliminated. This technology is ideal for
products such as mobile phones with
their high volume and the need for small
size and low cost.
Yet another method for passive device
integration in the early stages is to
combine them on the wafer level together
with the wafer level packaging steps. By
establishing multiple metal/passivation
layers (up to 5), the passive components
are built directly onto the die between the
chip and the first level interconnect, which
is typically a solder bump.
The methods to produce precise
resistors, capacitors, and inductors on
wafers or substrates usually involve thin
film technology for most of the
applications. Resistors are preferably
made by sputtering of TaN, NiCr –
including its ternary alloys – and SiCr
through a lift-off type photo resist.
Inductors are sputtered in the shape of
a plating base and then enforced by an
electroplating step to increase the cross
section of the trace. Alternatively, they
are sputtered over the full thickness and
etched by subtractive etch technology,
the latter being suitable only for ratios
of thickness to line width below 0.25.
Multiple choices are available to
create capacitors. Depending on the
requirements, sputtering can be efficiently
done for Al2O3, AlN, SiO2, Si3N4, Ta2O5,
TiO2, and some more dielectrics. Because
of the relative low sputter rates of
dielectric films, PECVD techniques are
preferred for the thickness range above
2.0 to 3.0 µm. Spin-on of high k
dielectrics is used as a low cost
alternative.
Sputtering
Cathodic sputter deposition is the
most versatile solution for the production
of electronic circuits. Although the
starting pressure should be better than
2 x 10–8 mbar to avoid contamination,
sputtering takes place in a low-pressure
atmosphere of inert gas, such as argon,
in the range of 10–3 mbar.
A glow discharge is formed by applying
a high voltage (approx. 200 V– 2000 V)
between anode and cathode, which is
formed by the material to be sputtered
(diode sputtering). An electron source
supports ionization of the inert gas, and
the positively charged argon ions are
accelerated towards the cathode (triode
sputtering). These ions bombard the
cathode material (target) with high energy
and force atoms and molecules to break
away from the cathode by virtue of their
kinetic energy. Some of these sputtered
particulates are intercepted by the
substrate and form a uniform thin film
layer. Adding magnets nearby the target
increases the travel-distance of the
electrons, thus increasing the probability
of collision with argon molecules
(magnetron mode). This way high
deposition rates can be managed at low
pressure. To improve the film uniformity
Unaxis Chip | 51
Advanced Packaging
Figure 1: Resistance
change due to
non-zero TCR
Resistance change dR/R by a non-zero TCR
NiCr 150 Ohm/sq. (± 25 ppm/˚K)
vs. Cermet 1500 Ohm/sq. (± 50 ppm/˚K)
dR/R25°C [%]
0.80
This process is called reactive
sputtering and is used frequently to
Produce resistor films like Ta2N
Control the TCR of NiCr films
Stuff barriers such as TiN or TiW(N)
Form insulating layers like Si3N4
or Ta2O5
0.60
0.40
0.20
0.00
– 0.20
– 0.40
– 0.60
– 0.80
–40
–20
0
20
40
60
80
100
120
140
Temperature [ ˚C]
Cermet (TCR ± 50 ppm/°K)
NiCr (TCR ± 25 ppm/°K)
Absolute resistance change of NiCr films
as a function of time and temperature
dT (TCR) = 100˚K ,dt = 1000h at 150˚C
dR/R = f (t, T) [%]
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0
200 400
600
800 1000 1200 1400 1600 1800 2000
Sheet Resistance [Ohm/square]
dR/R non-zero TCR
Figure 2: Resistance
change as a function
of time and
temperature
52 | Chip Unaxis
dR/R long-term drift
across the substrate, either the substrates
are rotated relative to the cathode (batch
type with rotating drum), or the magnetic
field rotates behind the target (often used
with single wafer solutions). Very tight
tolerances of film thickness < ± 2%
across a 200 mm wafer can be realized.
Sputtering offers the highly interesting
possibility to change the chemical
composition of the deposited film by
applying reactive gases such as oxygen
or nitrogen to the inert gas atmosphere.
The properties of the deposited film
can be altered depending on the
concentration of the added reactive gas.
When increasing the flow rate of the
reactive gas, the metal sputtering mode
with a high deposition rate due to a
metallic non-contaminated target, has to
be distinguished from the compound
mode, where with increasing reactive
gas flow, reactive products are also
formed at the target surface, causing the
deposition rate to slow down. Slightly
doped NiCr resistors and Ta2N films are
sputtered in the metallic mode, whereas
insulating layers will utilize the compound
mode. To keep such processes stable,
a pulsed DC power supply may be helpful.
If the deposition should take place in the
transient region between metallic and
compound mode, a process control
can be installed, which maintains the
gas flow by mass spectrometry
and the metal rate by optical emission
spectrometry (OES). If the target already
is an insulating material, then an RF
plasma system – usually operating at
13.56 MHz – is the appropriate solution.
Sputtering can occur, because the target
is bombarded in the RF-field with ions and
electrons alternatively.
Heating the substrates before or during
the deposition will influence the mobility
of the incoming molecules and atoms
and thus control gas incorporation. The
deposition temperature influences film
parameters such as stress, adhesion,
density, and resistance. Similar effects
can be achieved by applying DC- or
RF-substrate bias. Controllable substrate
heaters and coolers with an optional
substrate bias are available with stateof-the-art sputter systems such as
LLS EVO or CLUSTERLINE®.
Thin films for integrated passive
applications
Important applications of integrated
passives:
Clock terminators and filter networks
used in CPUs such as INTEL’s Pentium
EMI filters and ESD protectors
Zero Ohm jumper arrays
Bus terminators such as serial/parallel
termination array networks and AC
termination networks
Precision resistor arrays, such as
isolated and bussed resistor networks,
voltage divider networks, and audio
resistor arrays
All these applications contain a more or
less large amount of resistors, capacitors,
and inductors. High-quality requirements,
especially for resistor films, lead to
sputter-deposited thin film solutions.
Resistors
Most important for the practical use of
resistors in IP circuits is the capability to
sustain a certain nominal resistance value
over the entire time of use.
A non-zero temperature coefficient of
resistance (TCR) leads to a resistance
change as a function of variable operating
temperatures (Figure 1), while a long-term
drift of the film material leads to a
resistance change as a function of time.
Figure 2 shows the superposition of both
effects for a sheet resistance range from
2 Ohm/square to 2’000 Ohm/square.
For this example, a temperature change
Figure 5: Interconnect
wiring with integrated
passive devices
TaN: Nitrogen concentration and specific resistance
as function of N2 flo w
1.40
250.0
1.20
200.0
1.00
0.80
150.0
0.60
0.40
Ta: 1 Mol
100.0
Specific resistance [ Ohm · cm]
1.60
0.20
0.00
50.0
0
5
10
15
20
25
N2 flow [sccm]
Specific resistance [ Ohm · cm]
N (Mol)
Figure 3: Specific
resistance of TaN
obtained on the
CLUSTERLINE®.
Specific resistance [x 10 –6 Ohm-cm]
N content [Mol]
of 100°K during operation and storage
for 1’000 hours at 150°C was assumed.
The most stable region is between 50
Ohm/square to 200 Ohm/square.
Sophisticated sputter techniques like
reactive sputtering and sputtering of
ternary alloys are the key for NiCr- and
Tantalum-based films with high stability
and low TCR over a wide range of sheet
resistance values, e.g. from 2 to 2’000
Ohm/square. Furthermore, sputtered thin
films exhibit a superior performance with
respect to noise level, even in the GHz
frequency range.
NiCr films cover an especially wide
range of applications. Standard NiCr
films, reactively sputtered from a
compound target in an oxygen
atmosphere, are available with a sheet
resistance up to 300 Ohm/square, a TCR
below ± 25 ppm /°K and a long-term
stability of about 0.1% deviation from the
nominal value after 1’000 hours storage
at 150°C.
Resistor films for high-frequency
applications adhere well to highly polished
glass, quartz, sapphire or AlN substrates.
Dissipation by magnetic materials should
be avoided. NiCr films with very low Ni
content, reactively sputtered in a nitrogen
atmosphere, will match those
requirements.
Sputtering of ternary alloys such as
NiCrAl provide a TCR below ± 10 ppm /°K
and a long-term stability better than
0.03% after 1’000 hours at 150°C.
Cermets are suitable materials when
higher sheet resistance values are required.
Compound targets, co-sputtering and
reactive sputtering are techniques to
realize a semicontinuous conductive
phase with an appropriate composition
of dielectric and conductive components.
TCR values below 200 ppm /°K and a
sheet resistance up to 2’000 Ohm/square
have been achieved with combinations
of NiCr and SiO2 or Al2O3. If TCR
requirements are not so stringent, SiCr
is a proven cermet material. Long-term
stability is comparable to standard
NiCr films.
Ta-based thin films are an attractive
alternative to the NiCr films above. In
addition to its refractory nature, which
implies that any imperfection frozen in
during deposition will not anneal out
during lifetime, tantalum belongs to a
class of metals known as valve metals,
which form tough self-protective oxides,
either through anodic oxidation or through
heat treatment in an oxygen atmosphere.
Since tantalum is such a reactive material,
the sputtered films have a tendency to
be contaminated during deposition.
A controlled contamination is desirable
to achieve useful properties. The most
common process is reactive sputtering in
a nitrogen atmosphere to form TaxN films.
By increasing the N2 flow the resistance
rises and levels out at ~ 200 to
250 µOhm · cm, whereas the TCR drops
down from positive values and stays at
~ –100 ppm /°K. The composition of
these “plateau” films is very close to Ta2N
and displays the greatest stability during
load-life tests.
To reach a stable final value, Ta2N films
need a thermal post-treatment just like
300
250
200
150
0
0.5
1
1.5
2
2.5
3
3.5
N2 – partial pr essure [x 10 –4 mbar]
Figure 4: Specific
resistance of TaN
obtained on LLS EVO
Unaxis Chip | 53
Titanium-Tungsten or Titanium Nitride
will help to improve temperature stability of
the circuit and reduce diffusion, migration,
and segregation of contact material into
the resistance layers and vice versa.
Figure 6: Multilayer
metallization
scheme with
integrated thin film
resistors (R) and
capacitors (C)
NiCr films. A good indicator for plateau
films is the fact that the TCR is only
negligibly changed during this heat
treatment, whereas the resistance
value rises, depending on time and
temperature. The sheet resistance
increases because during heat treatment
the surface of the Ta2N film is changed
to self-protective oxide and the electrical
effective thickness of the Ta2N layer
decreases. This effect may be used for
thermal trimming of the resistors without
any laser cut, which is an important fact
for very-high-frequency applications.
The common sheet resistance range
for Ta2N films is 30 to 300 Ohm/square
with a TCR between –70 to –130 ppm/°K.
Long-term stability is better than 0.05%
after 1’000 hours at 150°C. For higher
sheet resistance requirements
cermet films such as TaSi are available.
High-conductive films for
interconnect wiring
In high-density and high-frequency
applications combined with integrated
passives, aluminum or copper rewiring is
used instead of the more expensive gold,
which was typically used in former hybrid
applications. The thickness range of these
layers is between 0.5 µm and 5.0 µm,
thin enough to be sputtered within a
reasonable amount of time with modern
planar magnetron technology. Adhesion
promoters such as Chrome or Titanium,
and barrier layers such as Nickel,
54 | Chip Unaxis
Capacitors
High-value bypass capacitors to be
integrated via thin film techniques are a
challenge. For frequencies exceeding
the 100 MHz range, thick film solutions
show an increasing dielectric dispersion,
therefore thin film capacitors are superior.
Integrated thin film capacitors may exist of
a sputtered conductive bottom electrode,
an RF, or a reactively sputtered dielectric
layer such as AlN, Al2O3, Si3N4, SiO2, or
Ta2O5, and a conductive top electrode.
Generally, a great variety of metal/insulator
combinations is possible, depending on
the technical requirements and the
compatibility with the materials below and
above the capacitor.
Unified solutions with only one base
material are Ta // Ta2O5 // Ta or Al //
Al2O3 // Al, which could theoretically be
performed with only one sputter source,
using the technique of reactive DC
or RF sputtering. More sophisticated
solutions have electrode stacks, including
adhesion layers as well as barrier layers.
Typical electrode materials are either good
conductors, such as Al, Au, Cu, Pt, or
perform a good adhesion, such as Cr,
MnO2, Nb, Ta, Ti, and TiW. Additional
barrier layers to avoid diffusion and
migration – once between the surrounding
of the capacitor and second between
conductor and insulator of the capacitor
itself – are materials such as Ni, NiCr,
TaxN, TiN, TiOx, ZrO2, and many more.
Suitable dielectrics for capacitors
have a high insulation resistance
> 1012 Ohm · cm, a high dielectric
strength, and a high dielectric constant.
Ta2O5 has a very high dielectric constant
of 25 (at 100 kHz), followed by Al203 with
9 and Si3N4 with 8. With a thickness of
only ~ 200 nm, breakdown voltage values
of 50 V are reported with Ta2O5 and
Si3N4, achieving a dielectric strength
of 3 to 5 MV/cm. The achievable
capacitance per square is comparable
to thick film capacitors. However, the thin
film version appears much more stable
and better suited to high-frequency
requirements.
Conclusion
When it comes to integrated thin film
circuits, state-of-the-art technology
is guaranteed with a Unaxis sputter
deposition system, whether a load lock
batch system such as LLS EVO or a
single wafer system such as the
CLUSTERLINE ®.
All coated substrates distinguish
themselves through
쐍 Very low TCR
쐍 Excellent long-term stability
쐍 Low stress
쐍 Extremely tight tolerances
쐍 High uniformity
쐍 Small critical dimensions
쐍 Highly reproducible values from
substrate to substrate and from
batch to batch
High uniformity, high process flexibility,
excellent yield, and easy-to-service
equipment with high up-time are the
advantages that speak for an economical
integrated passive thin film solution.
For more information please contact:
[email protected]
Advanced Packaging
APiA – the New Alliance for
Advanced Packaging Solutions
Hans Auer, General Manager Strategic Business Unit Advanced Packaging
The APIA members
Unaxis Semiconductors is a founding member of a group of leading
semiconductors equipment and process suppliers who together
announced the Advanced Packaging and Interconnect Alliance (APiA)
on December 5th, 2001.
The great challenge of creating highperformance, low-cost packaging for
constantly advancing semiconductor
devices requires innovative solutions
that can only result from a collaborative
effort between leading companies in the
industry. Equipment, process technology
and process material companies holding
leading positions in their field of emerging
packaging and interconnect technologies
have joined forces. The APiA is focused
on accelerating the development and
implementation of commercially viable,
comprehensive and risk-free packaging
solutions that address the escalating
manufacturing and performance
challenges of the industry. The alliance
will concentrate on enhancing the
productivity and reliability of the equipment
and process solutions critical for
advanced packaging and interconnect
processes, as well as developing
guidelines and standards to enable
easy adoption of these technologies.
A worldwide alliance
The APiA unites a global group of industry
leaders with the expertise, insight, and
technical know-how necessary to pursue
viable solutions to sophisticated packaging
challenges. The founding members of the
alliance represent Asia, Europe, and the
United States – a culturally diverse
organization that incorporates the
strengths of each geographical region:
쐍 August Technology
Automated, visual micro-defect
inspection equipment
쐍 Casio Computer
Manufacturing and process development
of WL-CSP and wafer bump
쐍 Dainippon Screen Manufacturing
Coat/bake /develop equipment
쐍 EBARA Corporation
Advanced plating technology
and equipment
쐍 Flip Chip Technologies
Solder bumping services and wafer
level packaging solutions
쐍 Ultratech Stepper
Advanced photolithography systems
쐍 Unaxis Semiconductors
Thin film production solutions
Comprehensive, risk-free, advanced
packaging solutions
Remaining competitive in the dynamic
environment of the industry requires
considerable effort in technology
development and in the establishment
of manufacturing infrastructure. The
alliance will offer a complete line of
commercially viable and proven advanced
packaging and interconnect production
solutions. APiA is a unique source
for equipment, materials, technology,
and expertise, and provides next
generation technology solutions while
Unaxis Chip | 55
Unaxis Semiconductors
Dainippon Screen
Ultratech Stepper
Flip Chip Technologies
minimizing the inherent risks associated
with the adoption of these technologies.
Close to 200 visitors
attended the first
APiA Seminar at the
Hotel Francs in Chiba
300 mm advanced packaging
demonstration line
The alliance will concentrate on bump
processing and wafer level chip scale
packaging – a market in which all
founding APiA members have leading
technology positions. APiA plans to
establish 300 mm pilot lines in the United
States and Asia to be used by alliance
members as well as customers. For the
first time, customers will be able to
evaluate a working 300 mm advanced
packaging process line, collaborating with
each individual supplier to evaluate tools
and process technologies. The 300 mm
pilot lines will allow member companies to
Ebara
Casio Computer
work together in technology development,
creating an integrated and seamless
process for turnkey advanced packaging
solutions. Completion of the first
US-based process development
and demonstration line is scheduled
for the second half of 2002.
Creating advanced packaging
guidelines and standards
The commercialization of emerging
technologies requires standards and
guidelines for successful implementation.
APiA will lead this effort for the advanced
packaging technologies by acting as
a central information resource, and by
establishing a standards committee.
This committee will be open to chip
manufacturers, assembly and packaging
August Technology
Process flow
diagram of the
300 mm advanced
packaging pilot line
companies, bump service providers,
equipment and materials suppliers, and
other interested parties. The alliance
will foster an open dialogue between
equipment suppliers and device
manufacturers serving as both a forum
to discuss advanced interconnect issues
and requirements, as well as a venue
for members to share technology, process
and market information.
If you are interested in the Advanced
Packaging and Interconnect Alliance
please visit: www.apialliance.com.
For more information about Unaxis
within APiA please contact:
[email protected].
The APiA Press
Conference at
Semicon Japan,
December 5th 2001
(from left to right):
Jeff O’Dell, August;
Juerg Steinmann,
Unaxis; Akira Ogata,
Ebara; Nobutoshi
Ogami, Dainippon
Screen Manufacturing;
Art Zafiropoulo and
Ellery Buchanan,
Ultratech; Yukio Kasio,
Casio; Gil Olachea, Flip
Chip Technologies
56 | Chip Unaxis
Unaxis Insights
February
5th – 7th
Semicon Korea
Seoul
www.semikorea.org
March
4th – 6th
Key Conference
Key West, Florida, USA
www.keyconference.com
26th – 27th
Semicon China
Shanghai
www.semi.org
8th – 11th
GaAs Mantech
San Diego
www.gaas.org
10th – 12th
Diskcon Japan / ODP
Tokyo
www.diskconjapan.com
16th – 18th
Semicon Europe
Munich, Germany
www.semi.org
23th – 25th
Photomask Japan
Yokohama
www.spie.org
May
12th – 16th
IPRM
Stockholm, Sweden
www.congrex.com/iprm2002
July
8th – 12th
IPFA
Singapore
www.ieee.org/ipfa
22th – 24th
Semicon West
Wafer Processing
17th – 19th Final
Manufacturing
San Francisco
www.semi.org
events
events
April
For updates please check www.semiconductors.unaxis.com
Unaxis at Semicon West, Semicon Japan, Semicon Europe, and Semicon Taiwan (from left to right)
Unaxis Chip | 57