Development of an Avalanche Pixel Sensor for - Agenda

APiX
Development of an Avalanche Pixel
Sensor for Tracking Applications
Lodovico Ratti
Università di Pavia and INFN Pavia
([email protected])
INFN, Commissione Scientifica Nazionale 5
Università La Sapienza, Roma, 8 ottobre 2013
Outline
Motivation
The APiX project
•  Basic avalanche pixel
•  Dual tier avalanche pixel detector
•  Vertical integration
•  Thinning
•  Workplan and milestones
Conclusion
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APiX project profile
Goal of the project: developing a position sensitive detector based on
the vertical integration of quenched Geiger cells fabricated in CMOS
technology, with the potential for minimizing the detector thickness
and the related multiple scattering effects and for low noise, low power
operation
Duration: 3 years
Participating INFN groups and external institutions:
• 
INFN Siena (2.6 FTE; gruppo collegato, resp. naz.: Pier Simone Marrocchesi)
• 
INFN Pavia (1 FTE; resp. loc.: Lodovico Ratti)
• 
Laboratoire APC, Université Paris-Diderot/CNRS (Aurore Savoy Navarro)
• 
Institute of Applied Mathematics, Russian Academy of Science, Moscow
(Valeri Saveliev)
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Motivation
Minimization of the material budget is an important goal in most of the present
(and future) particle tracking systems at high luminosity colliders
A considerable effort has been devoted to the
development of thin detectors
n - Si
•  fully depleted detectors è signal proportional
to thickness
•  diffusion based detectors (MAPS) è no
significant change in charge collection with
thickness reduction, but the signal is small
Also power dissipation plays a crucial role in
material budget reduction – less power
dissipation put less burden on the cooling
system
The ideal device should provide a large
signal while featuring a thin sensitive volume
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Avalanche photodiodes
Avalanche photodiodes are p-n junction purposely made to operate at high electric
fields in order to achieve an internal gain
A charge carrier accelerated by the field in the depleted region can reach an
energy high enough to break a bond when colliding with lattice atoms, thus
generating a new e-h pair through impact ionization
In linear-mode APDs, the bias voltage is below breakdown and the generated
current is proportional to incident light; in Geiger-mode APDs, the bias voltage
exceeds the breakdown voltage, with multiplication factors in the order of 106
To turn the avalanche current off, a proper quenching mechanism has to be used
in Geiger-mode APDs
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Basic detector element
The basic element of the APiX detector is an avalanche diode, based on a standard
CMOS process and operated in the quenched Geiger mode
• 
a large, intrinsic gain is provided by the detector itself, with no need for preamplification
à less power dissipation
• 
no amplitude measurement, pure binary information (hit/no hit)
• 
the sensitive layer of the device is very thin, limited to the depleted region around the pn
junction à virtually no charge loss if the substrate is thinned down
• 
readout electronics in the same substrate as the sensor
An avalanche detector may feature a dark count rate of the order of 10 MHz/cm2
poly gate
guard ring
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Dual tier avalanche pixel detector
The goal is to improve dark rate performance by using
the coincidence signal between two overlapping pixels
(sensor pairs) – proposed by Valeri Saveliev
• 
assume a dark count rate per unit area RA for each tier
and an elementary square cell with pitch p
• 
dark count rate for the single sensor: RAp2
• 
given a coincidence time Δt, the dark count rate for a
sensor pair is 2RA2p4Δt, the dark count rate per unit area
for a dual-tier detector is
2RA2p2Δt
• 
for RA=10 MHz/cm2, Δt=10 ns and p=50 µm, the dark count
rate for a dual-tier detector is 50 Hz/cm2
Low voltage
HV-to-LV coupling
!
“High” voltage
(~10 V)
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Front-end electronics
Very simple front-end, converting the
detector signal to a CMOS logic level
Coupling)CAP)1-10fF)
Need for decoupling to avoid field induced
stress or rupture in the gate oxide
APD)as)current)exp)source)
LATCH)reset)
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Vertical integration: layer interconnection
Vertical integration seems a
natural choice for fabrication of
a dual-tier avalanche pixel sensor
Virtually monolithic integration
with chip-to-chip, chip to wafer,
wafer to wafer vertical
interconnection
Various interconnection
techniques available: micro-bump
bonding, direct bond
interconnect, thermo compression
upper sensor
upper-layer
substrate
Inter-layer
bump pads
metal layers
+
inter-metal dielectric
Inter-layer
u-bump
bottom-layer
substrate
bottom sensor
upper
layer
wire bond
bottom
layer
PCB
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Vertical integration: TSVs
TSVs (via last) can be used to minimize dead area at the periphery – flip-chip bonding to
the PCB, no room needed for wire bonding
wire bond
back-side
bond pad
TSV
top sensor
2nd layer
1st layer
thinned
substrate
inter-tier bond pads
(metal 6)
1st layer
2nd layer
metal layers
+
inter-metal dielectric
substrate
bottom sensor
bump bond
PCB
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Vertical integration with T-Micro
Very high interconnect density, with small
bond pads (squares with a side of 5 or 10 µm,
depending on the bump size, 2x2 µm2 or 8x8
µm2) both on the sensor and the readout
sides è more room for top metal routing, in
particular for power and ground lines, smaller
capacitive coupling, less material
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Sensor thinning
Improves momentum resolution by reducing multiple
scattering in multilayer silicon sensors
Different approaches are available to thin wafer down even
to 1 um – based on oxide or p++ layers acting as etch
stoppers
Aptek Industries offers
thinning services down to
25-30 um (10-15 um with 30%
yield) at quite low prices ($ 30
per die, $ 287 minimum)
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Possible issues and challenges
How easy is to extend the technology to the fabrication of larger size
devices and systems
What is the portability of the device concept from one CMOS technology
to a different one
What is the yield, with particular reference to vertical integration
What are the benefits in terms of material budget reduction
What is the degree of radiation tolerance of the device (from the
standpoint of both ionization and bulk damage)
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Workplan and milestones
First year
•  simulation and design of avalanche pixel sensors different pixel options for performance optimization
•  modeling of the vertical interconnected structure
•  prototype fabrication and test
•  vertical integration
•  design and configuration of a multipurpose lab test bench
Milestone:
fabrication and
test of vertically
aligned cell pairs
Second year
•  development of a small, vertically integrated detector
prototype with integrated readout electronics
•  test on a particle beam
Milestone:
fabrication and
test of the APiX
digital sensor
Third year
•  development of an APiX chip building block with
relatively large active area
•  test on a particle beam
Milestone:
fabrication and
test of the APiX
building block
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Conclusion
The APiX project aims at developing a low material budget, monolithic
detector based on the avalanche mechanism of diodes operated in Geiger
mode
Vertical integration techniques enable the design of a dual tier sensor
with improved dark count rate performance
Use of CMOS technology ensures that high performance digital readout
circuits can be monolithically integrated with the sensitive part of the
device
While the obvious goal of the project is the development of a detector
for tracking applications, the outcomes of the research activity can be of
interest in a number of other fields, such as research instrumentation,
homeland security, CMOS imagers, quality of life enhancement
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Backup
People
INFN Siena
Nome
Qualifica
Impegno
Paolo Brogi
dottorando
Pier Simone Marrocchesi
PO
50%
Fabio Morsani
Primo tecnologo
10%
Suh Jung Eun
dottorando
100%
100%
FULL TIME EQUIVALENT
2.6
INFN PV
Nome
Qualifica
Impegno
Lodovico Ratti (resp. loc.)
RU
20%
Carla Vacchi
RU
40%
Stefano Zucca
assegnista INF
40%
FULL TIME EQUIVALENT
1
External Institutions
Laboratoire APC, Université Paris-Diderot/CNRS
Institute of Applied Mathematics, Russian
Academy of Science
Aurore Savoy Navarro
Valeri Saveliev
Chang Seong Moon
Nicola D’ascenzo
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