UNIVERSITI TEKNOLOGI MALAYSIA

Transcription

PSZ 19:16 (Pind. 1/07)
UNIVERSITI TEKNOLOGI MALAYSIA
DECLARATION OF THESIS / UNDERGRADUATE PROJECT PAPER AND COPYRIGHT
Author’s full name :
NAZRIL HAFIZ BIN MOHAMAD
Date of birth
:
13TH DECEMBER1990
Title
:
DEVICE AND CIRCUIT LEVEL PERFORMANCE OF SILICON NANOWIRE FIELDEFFECT TRANSISTOR WITH BENCHMARKING AGAINST A NANO MOSFET
Academic Session :
2012/2013
I declare that this thesis is classified as :
CONFIDENTIAL
(Contains confidential information under the Official Secret
Act 1972)*
RESTRICTED
(Contains restricted information as specified by the
organization where research was done)*
OPEN ACCESS
I agree that my thesis to be published as online open access
(full text)
I acknowledged that Universiti Teknologi Malaysia reserves the right as follows:
1. The thesis is the property of Universiti Teknologi Malaysia.
2. The Library of Universiti Teknologi Malaysia has the right to make copies for the purpose
of research only.
3. The Library has the right to make copies of the thesis for academic exchange.
Certified by :
SIGNATURE
901213-03-5361
(NEW IC NO. /PASSPORT NO.)
NOTES :
*
SIGNATURE OF SUPERVISOR
DR MICHAEL TAN LOONG PENG
NAME OF SUPERVISOR
If the thesis is CONFIDENTAL or RESTRICTED, please attach with the letter from
the organization with period and reasons for confidentiality or restriction.
“I hereby declare that I have read this thesis and in my
opinion this thesis is sufficient in terms of scope and quality for the
award of the degree of Bachelor of Engineering (Electrical-Electronics)”
Signature
:
…………………..…………..
Name of Supervisor :
DR. MICHAEL TAN LOONG PENG
Date
………………….….………..
:
DEVICE AND CIRCUIT LEVEL PERFORMANCE OF SILICON
NANOWIRE FIELD-EFFECT TRANSISTOR WITH BENCHMARKING
AGAINST A NANO MOSFET
A report submitted as partial fulfillment of the
requirements for the award of the degree of
Bachelor of Engineering (Electrical-Electronics)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
JUNE 2013
ii
I declare that this thesis entitled “Device and Circuit Level Performance of Silicon
Nanowire Field-Effect Transistor with Benchmarking against a Nano MOSFET” is
the result of my own research except as cited in the references. The thesis has not
been accepted for any degree and is not concurrently submitted in candidature of any
other degree.
Signature
:
…………………..………..
Name
:
Date
:
………………..…………..
iii
Dedicated to my mother, father, brothers, sisters and friends.
iv
ACKNOWLEDGEMENT
O ALLAH, the Most Gracious and the Most Merciful. Alhamdulillah
Praise to Allah for the blessing, this project was successfully completed and
finished.
First and foremost, I would like to take this opportunity to express my
sincere gratitude to my project supervisor, Dr. Michael Tan Loong Peng for
all his time, guidance, patience, support, consideration and encouragement
throughout finishing this project.
Besides that, I would like to thank my family especially my mom and
dad who had give me lot of support to finish this project till the end.
Lastly, I would like to convey my warmest gratitude to all my friends
who had directly or indirectly contributed in the completion of this project.
v
ABSTRACT
As the devices dimension had reduce drastically, new alternatives had been
introduced to meet the requirements of Moore’s law. Various field-effect transistor
(FET) had been introduced in order to replace the convenient Metal Oxide
Semiconductor Field-Effect Transistor (MOSFET) that had been used nowadays.
Among the entire new field-effect transistor that had been introduced, Silicon
Nanowire Field-Effect Transistor (Si NWFET) had been given a lot of attention as
candidate for Complementary Metal-Oxide-Semiconductor (CMOS) technology
because of its unique advantages as it was based on silicon, the material that had
been working by the semiconductor industries for a period of time candidates and
also due to its short-channel effect immunity, improved transport property and
CMOS compatibility [1]. In order to understand the device physics in depth and to
assess the performance limits of Si NWFET, simulation of performance is very
important to make sure Si NWFET will become a promising candidate as a
semiconductor material in nanotechnology devices and applications. This thesis will
discuss the performance of the Si NWFET against the nano Metal Oxide
Semiconductor Field-Effect Transistor (nano MOSFET). A SPICE model of Si
NWFET is constructed by deriving and modifying a FETToy MATLAB script
proposed by A. Rahman [2] and then extended by Jing Wang [3] of Purdue
University. The SPICE model specifications are determined by further study and
research on various ballistic reports and thesis. Next, a USCF equation is obtained by
using fitting method for the Matrix Laboratory (MATLAB) script and later on the
USCF equation was used to simulate the I-V characteristic for the Spice model and
projected in CosmoScope to view the result. Then, the logic circuit such as inverter,
NOR and NAND are built. For the nano MOSFET, a 32nm MOSFET is modified the
vi
parameters so the I-V characteristic for both Si NWFET and nano MOSFET match
and a fair assessment can be done [4].
vii
ABSTRAK
Oleh disebabkan dimensi bagi peranti telah berkurang secara drastik,
alternatif- alternatif baru telah diperkenalkan bagi memenuhi kehendak hukum
Moore. Pelbagai Transistor Kesan Medan (FET) telah diperkenalkan bagi
menggantikan Transistor Kesan Medan Logam Oksida Separuh Pengalir (MOSFET)
yang telah digunakan pada masa kini. Antara keseluruhan transistor kesan medan
baru yang telah di perkenalkan, Silikon Wayar Nano Transistor Kesan Medan (Si
NWFET) telah diberikan banyak perhatian sebagai pengganti kepada CMOS
teknologi kerana kelebihan unik ia yang berdasarkan silikon, suatu bahan yang telah
digunapakai didalam industri semikonduktor untuk satu tempoh masa dan juga
disebabkan imuniti kesan saluran kecil, pengangkutan yang lebih baik dan keserasian
CMOS [1]. Untuk memahami dengan lebih mendalam peranti fizik dan menilai had
prestasi Si NWFET, simulasi prestasi adalah sangat penting bagi memastikan Si
NWFET akan menjadi calon yang sesuai sebagai bahan semikonduktor di dalam
peranti teknologi nano dan aplikasi. Tesis ini akan membincangkan prestasi Si
NWFET dan dibandigkan dengan Transistor Kesan Medan Logam Oksida nano
Separuh Pengalir (nano MOSFET). Satu model SPICE Si NWFET dibina dengan
mengurai dan mengubah suai skrip FETToy MATLAB yang dicadangkan oleh A.
Rahman [1] dan kemudian dilanjutkan oleh Jing Wang [2] di Universiti Purdue.
Spesifikasi model SPICE ditentukan dengan kajian lanjut dan penyelidikan mengenai
pelbagai laporan balistik dan tesis. Seterusnya, persamaan USCF yang diperolehi
dengan menggunakan kaedah persamaan untuk Matrix Laboratory (MATLAB) skrip
dan kemudian persamaan USCF itu digunakan untuk mensimulasi ciri-ciri I-V bagi
model Spice dan diunjurkan dalam CosmoScope untuk melihat hasilnya. Kemudian,
litar logik seperti penyongsang, NOR dan NAND dibina. Untuk nano MOSFET, satu
MOSFET 32nm diubah suai parameter supaya ciri-ciri I-V bagi kedua-dua Si
NWFET dan nano MOSFET selari dan penilaian yang adil boleh dilakukan [3].
viii
TABLE OF CONTENTS
CHAPTER
1
2
TITLE
PAGE
DECLARATION OF THESIS
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vii
TABLE OF CONTENT
viii
LIST OF TABLES
xi
LIST OF FIGURES
xii
LIST OF ABBREVIATIONS
xv
INTRODUCTION
1
1.1
Background
1
1.2
Problem Statements
3
1.3
Objectives
3
1.4
Scopes of Work
4
1.5
Project Gantt Chart
5
1.6
Thesis Organization
6
LITERATURE REVIEW
8
2.1
Overview
8
2.2
Silicon
8
2.3
Silicon Nanowire
9
2.4
MOSFET
11
ix
2.5
Silicon Nanowire Field-Effect Transistor
14
2.6
Fabrication of Metal Oxide Semiconductor
15
Field-Effect Transistor
2.7
Fabrication of Silicon Nanowire Field-Effect
16
Transistor
2.8
Compact Model of Si NWFET
17
2.9
SPICE Modeling and device specification for
20
SPICE model
2.10
3
4
24
RESEARCH METHODOLOGY
25
3.1
Introduction
25
3.2
MATLAB
27
3.3
HSPICE
28
3.4
CosmosScope
28
RESULTS AND DISCUSSION
30
4.1
Introduction
30
4.2
SPICE model
31
4.3
USCF equation
32
4.4
Device Circuit Analysis
36
4.4.1 Inverter
37
4.4.2 NOR2
38
4.4.3 NAND2
40
4.4.4 NOR3
42
4.4.5 NAND3
43
Performance result
45
4.5.1 Power Delay Product (PDP)
47
4.4.2 Energy Delay Product (EDP)
48
CONCLUSIONS AND FUTURE WORK
51
5.1
Conclusions
51
5.2
Future Work
53
4.5
5
Curve Fitting
x
REFERENCES
54
APPENDICES
57-75
xi
LIST OF TABLES
TABLE
TITLE
PAGE
4.1
Device Model Specification at V gs = 1V
31
4.2
Truth Table for inverter
37
4.3
Truth table for NOR2
39
4.4
Truth table for NAND2
40
4.5
42
4.6
44
4.7
Propagation
Delay
(TPD),
Average
Power
46
(AVG_POWER), Power Delay Product (PDP) and
Energy Delay Product (EDP)
4.8
Propagation delay computation between Si NWFET
and nano MOSFET
49
xii
LIST OF FIGURES
FIGURE
TITLE
PAGE
1.1
Moore’s Law
2
1.2
Project Gantt chart for semester 1
5
1.3
6
2.1
Face Centered Cubic
9
2.2
Silicon Nanowire with different shape
10
2.3
Scale of nanowire compare with other nano material
11
2.4
N-channel and P-channel MOSFET
12
2.5
Cross section for pMos and nMos
13
2.6
3D model of MOSFET
13
2.7
Examples of Si NWFET
14
2.8
3D model of Si NWFET
14
2.9
Fabrication process for MOSFET
15
2.10
Fabrication process for Si NWFET
17
2.11
Stereoscopic and cross sectional schematic of
18
compact model
212
Energy-band diagram of n-type compact model
18
2.13
I ds –V ds with different dimensions (R = 10 and 5 nm)
19
2.14
I ds –V ds
19
with
different
doping
concentrations
(symbols: TCAD; lines: model)
2.15
Ids–Vgs with different radii.
20
xiii
2.16
I-V curves for the n-type/p-type SNWT with
21
D=1.36nm and the ratio of the p FET ON current to
the n FET’s vs. D. The oxide thickness is assumed to
be 1nm and the temperature is 300K.
2.17
I DS vs V DS for SiO 2
22
2.18
Fermi energy level for different types of materials
23
3.1
Research methodology flowcharts
26
3.2
Matrix Laboratory (MATLAB) programmed
27
3.3
HSPICE simulator
28
3.4
CosmosScope simulator
29
4.1
Self consistent voltages versus drain voltage
32
4.2
Compared result of USCF equation and SPICE model
33
4.3
I-V characteristic of Si NWFET
34
4.4
I-V characteristic for Si NWFET and nano MOSFET
34
4.5
I-V characteristic for n-type
35
4.6
I-V characteristic for p-type
36
4.7
Input and output waveforms of inverter for Si
37
NWFET
4.8
Input and output waveforms of inverter for nano
38
MOSFET
4.9
Input and output waveforms of NOR2 gate for Si
39
NWFET
4.10
Input and output waveforms of NOR2 gate for nano
39
MOSFET.
4.11
Input and output waveforms of NAND2 gate for Si
41
NWFET
4.12
Input and output waveforms of NAND2 gate for nano
MOSFET.
41
xiv
4.13
Input and output waveforms of NOR3 gate for Si
42
NWFET
4.14
Input and output waveforms of NOR3 gate for nano
43
MOSFET.
4.15
Input and output waveforms of NAND3 gate for Si
44
NWFET
4.16
Input and output waveforms of NAND3 gate for nano
45
MOSFET
4.17
PDP of Si NWFET versus nano MOSFET
48
4.18
EDP of Si NWFET versus nano MOSFET
49
xv
LIST OF ABBREVIATIONS
FET
-
MOSFET
-
Metal Oxide Semiconductor Field-Effect Transistor
Si NWFET
-
Silicon Nanowire Field-Effect Transistors
CMOS
-
Complementary Metal-Oxide-Semiconductor
IC
-
Integrated Circuit
Si
-
Silicon
Si NW
-
Silicon Nanowire
FCC
-
Face Centered Cubic
PMOS
-
P-Channel Mosfet
NMOS
-
N-Channel Mosfet
Au
-
Gold
KI
-
Potassium Iodide
CVD
-
Chemical Vapor Deposition
Sb
-
Antimony
B
-
Boron
EDP
-
Energy Delay Product
FET
-
TPD
-
Propagation Delay
AVG_POWER -
Average Power
1
CHAPTER I
INTRODUCTION
1.1 Background
In the computing world, packing more transistors on a chip leads to higher
speed and potentially, it also gives rise to more functions integration. According
to Moore Law, the numbers of a transistor in Integrated Circuit (IC) on a die
would double in every 18 months [5]. Meanwhile, the size of the transistor
decrease by a double for every three years .Moore’s Law was driven by three
factors which are to reduce the transistor size, increase the size of the microchip,
and also increase the circuit cleverness. Semiconductors industries are currently
in nano MOSFET range [6]. The performance of the transistors has been increase
in order to produce a better device performance. This is the results from extreme
scaling of MOSFETs with short channel effects coming into place.
2
Figure 1.1
Moore’s Law [7]
Semiconductor industries today are currently facing various challenges to
produce a new device that satisfy the requirement of Moore’s Law. As the devices
dimension had reduce drastically, new alternatives had been introduced to meet the
requirements. Some of the examples of the alternatives that has been introduced are
by producing entirely new field-effect transistor such as Carbon Nanotube FieldEffect Transistor, FinFets and as well as tri-gate transistors.
Among the entire new field-effect transistor that had been introduced, Si NW can
be prepared with a diameter of several nanometers and be shaped in cylindrical,
rectangular or triangle [8] and controllable dopant type and concentration, thus make
it a powerful building blocks for nano electronics devices such as field-effect
transistors. Because of its unique abilities for controllable dopant type and
concentration [9], Si NWFET attracts more attention and more readily to be
integrated into the silicon industry processing and fabrications [10]. Previous work
had focused on fabricating Si NW in different shape such as cylindrical, rectangular
and triangular. Details on fabrication of Si NW can be found by previous work by
Jing Wang et al [8]. In this research, we focused on studying the device and circuit
level performance of Si NWFET with benchmarking against a nano MOSFET. The
process technology that we used is 32nm. The performance of this same scale field-
3
effect transistor is compare to come out with better understanding of both transistor
performances in this case will help future research.
1.2 Problem Statement
Si NWFET had been paid attention as one of the promising FET for future
usage. However, in order to understand the device physics in depth and to assess
the performance limits of Si NWFET, simulation of performance is very
important to make sure Si NWFET will become a promising candidate as a
semiconductor material in nanotechnology devices and applications. Few
problems statement had been listed for this thesis.
•
What are the characteristic of Si NWFET and nano MOSFET?
•
What are the differences between Si NWFET and nano MOSFET?
•
What are the strength and weaknesses of both nano structures in term of
device and circuit performance?
•
What are the performance Si NWFET and nano MOSFET in different gates?
•
What are the advantages of Si NWFET compare to nano MOSFET?
1.3 Objectives
This project focused on the SPICE circuit simulation of Silicon Nanowire
Field-Effect Transistor (Si NWFET) with benchmarking against a nano MOSFET.
The performance will be analyzed based on the I-V characteristic on drain current
versus drain voltage, drain current versus source voltage and drain current versus
gate voltage. The objectives of the projects are;
4
•
To investigate and evaluate the characteristic of Si NWFET and compare
against 32nm MOSFET.
•
To construct a SPICE model Si NWFET and compare against a 32nm
MOSFET and simulate its performance by using HSPICE simulation based
on MATLAB script.
•
To compare the strength and weaknesses of both nano structures in term of
device and circuit performance
•
To analyze and evaluate the performance Si NWFET and nano MOSFET in
different logic gates such as NAND, NOR and inverter.
•
To carry out circuit analysis and performance evaluation of Si NWFET based
on the I-V characteristic and DC analysis comparison to nano MOSFET.
1.4 Scope of Work
There are several scopes that need to be considered in order to achieve the
objectives of this research. The scopes of this project are as follows;
This research project involves a good understanding, fully utilization and master
of all the functions in MATLAB .This will be useful in the process to construct a
SPICE model for Si NWFET and also to obtain I-V characteristic for SPICE Si
NWFET design.
The research requires knowledge on the characteristics of a Silicon Nanowire
which includes the changes in the doping agent for N-type and P-type on Fermi
energy, change of parameter for fabrication effect on the I-V characteristic and also
knowledge on the characteristic and performance of nano MOSFET.
5
This research also requires a fully understanding on the function of HSPICE and
CosmosScope software in the process for simulation of performance for Si NWFET
SPICE model. This software will help to obtain better result for this thesis.
1.5 Project Gantt Chart
Figure 1.2 below shows the project gantt chart for semester 1. Gantt chart is the
timeline to show the progress of the work during the whole process in order to finish
the project systematically and within its time limits.
Week/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Activities
Topic
Research
Proposal
Literature
review
SPICE
model
building
FYP
1
presentatio
n
FYP
report
Figure 1.2
18
19
20
6
Week/
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Activities
Literature
review
Designatio
n
and
simulation
Analysis
of result
Testing
and
comparing
FYP
2
presentatio
n
Thesis
writing
Figure 1.3
Figure 1.3 above shows the project gantt chart for semester 2. It shows the
timeline of the work progress and the whole process for finishing the project during
first semester
1.6 Thesis Organization
The thesis was organized into 5 chapters. Chapters 1 consist of the introduction.
It consists of the background of this research, problem statement, objectives, scopes
of work, and also gantt chart for this thesis. While, chapter 2 were consists of the
fundamental for this thesis. It consists of literature review that related to this project.
Basically, it has basic theories on Si NWFET and nano MOSFET.
Next is Chapter 3. The methodology to accomplish this thesis is discussed
thoroughly. Step by step methods to carry out this thesis is explained. Chapter 4
7
contains the results and discussion. All the results obtained from this thesis is discuss
to analyze the result. Lastly, chapter 5 consists of the summary and future suggestion
for this research.
8
CHAPTER II
LITERATURE REVIEW
2.1
Overview
This chapter will discuss the properties of Silicon Nanowire (Si NW), Silicon
Nanowire Field-Effect Transistor (Si NWFET) and nano Metal Oxide Semiconductor
Field-Effect Transistor (nano MOSFET). A brief study on previous thesis, articles,
ballistic reports and journals had been carried out to understand the concept of Si
NWFET. This chapter will also explain briefly on the characteristic, performance and
other related information regarding Si NWFET and also nano MOSFET.
2.2
Silicon
Silicon, (Si) had been used widely in semiconductor industries and had
become one of the most important materials in this industry. It was chosen among
other materials as it is cheap and easily available everywhere on the earth. Si is a
group IV element in the periodic table weighting 28.09 amu and 14 number of
atomic [11]. The Si has a diamond structure. The lattice constant “a” is 0.55nm and
Si is two Face Centered Cubic (FCC) lattices where one of the FCC lattices is
9
displayed by one fourth in the body diagonal direction. There is 4 atom per cell for
FCC. The band gap energy for Si at room temperature is 1.12eV [11].
Figure 2.1
2.3
Face Centered Cubic [11]
Silicon Nanowire
A nanowire is the connector with a diameter of 10-9 meters (10-11) feet) or
nanostructures with a 20 nm or less diameter of thickness and unconstrained length,
which is extremely small. These connectors were also known as quantum wires, are
used to connect tiny components together into very small circuits. They are smaller
than a tenth of a nanometer wide. They cannot grow more than a few nanometers in
height but there is no restriction on how wide they can grow. Nanowires are still in
experimental process and are not available in commercial or industrial applications.
The conductivity and small size make them ideal for future computer processors and
connectors.
By controlling their shape, crystalline, size and doping level, these
nanostructures can produce different performance in functional devices. As
10
nanofabrication technology is rapidly advancing, silicon nanowire (Si NW) with less
than 20nm diameters has been studied for potential applications in nano electronics.
Material reduced in 2D to create quantum confinement.
Figure 2.2
Silicon Nanowire with different shape [8]
By using nanowire as a transistor, smaller and faster microprocessor
components for the computer and electronic industry can be produced. Although the
performance of nanowire transistors is better than the current transistors, the current
costs to produce them is higher become the barrier for mass production. One of the
advantages of silicon nanowire is its small sizes that make their electronic and
electrical properties dependent on growth direction, size, morphology and surface
reconstruction.
11
Figure 2.3
Scale of nanowire compare with other nano material [12]
Silicon nanowires also suitable for electronics and other application because
of their compatibility with the existing silicon-CMOS integrated circuit technology.
In addition, single nanowires device could be contacted and connected so that it can
be used in a complex design or networks. Examples of different uses of silicon
nanowires are nanowire memory cell, nanowire LED and nanowire solar cell.
2.4
MOSFET
MOSFET (Metal Oxide Semiconductor Field-Effect Transistors) are four
terminals. Voltage-controlled switches. MOSFET is the most common field-effect
transistor used in both analogue and digital circuits
Nowadays MOSFET had become smaller as time goes by. Today's
MOSFETS used in ICs were in 32 nanometers scale. Smaller MOSFET have more
advantages as it allow more current to pass as MOSFET works as a variable resistor
in the on state and a shorter resistor causes smaller resistance and energy dissipated.
Besides that, the smaller gate will decrease the capacitance and also the charging
12
time in hence increase the switching time and the processing power. Lastly, more
transistors can be packed in the chip, thus will increase the processing power per chip
and reduce the cost per chip.
MOSFET consist of p-channel and n-channel MOSFET that operate in
enhancement and depletion mode. Besides, MOSFET also have source and drain
terminals. Every terminal is been doped and separated by bulk region. These regions
can be either p type or n type, but their types must be opposite type to the body
region.
Figure 2.4
N-channel and P-channel MOSFET
Figure above shows the cross section for both PMOS and NMOS. The source
and drain are the n+ regions in n-channel, while p-type region is the body. When
there is sufficient gate voltage applied, holes from the body will move from the gate,
and a n-chanel or inversion layer is formed at the interfaced between the p region and
the oxide. After the formation of the inversion layer, a conducting channel is created
between the drain and source terminals [13]. Current will enter at the drain and leave
at the source while electron flows from the source to the drain region.
While, the source and drain are the 'p+' regions in p-channel and the body is a
‘n+’ region. A negative gate voltage is applied to connect p-type source and drain
regions creating an inversion layer of holes so the drain and source regions can be
connected by a channel layer of holes. Current will enter at the source and leave at
13
the drain while holes will flow from the source to the drain region [13]. In a
depletion mode region, a p-channel region will exist even when there is no applied
voltage.
Figure 2.5
Cross section for pMos and nMos
Figure 2.6
3D model of MOSFET
14
2.5
Si NWFET is a field-effect transistor that uses silicon nanowire as its main
material. Si NWFET was made from silicon which happened to be used for a period
of time in semiconductor industries. Si NWFET can benefit from the maturity of
silicon industry fabrications and processing techniques. Taking this advantage, Si
NW can be prepared precisely and tailored in different sizes, shapes, and dopant.
Because of the reason Si NW could be well-controlled during the wire growth, the
performance exhibits high reproducibility. Hence, the n-/p-type semiconducting
property, doping density, and charge mobility in a Si NWFET can be designed in
advance.
Figure 2.7
Figure 2.8
Examples of Si NWFET [14]
3D models of Si NWFET
15
2.6
Fabrication of Metal Oxide Field-Effect Transistor
There are many variants ways patent to fabricate a MOSFET. One of it is by
fabricating on hydrogen terminated surface of diamond. First of all, the deposition of
gold, (Au) and patterned in rectangle as in figure below. Then, the surface of p-type
layer is insulated with the exposure of Ar+ ions where Au functions as stopping mask
of Ar+ ions. This process is called device isolation. Next, the p-tyoe surface
conductive layer is protected by Au. Next, potassium iodide (KI) is used to etch the
centre of the Au rectangle forming the channel, drain and source. Then, Silicon
monoxide and metal were deposited on the channel by using a vacuum evaporator.
By overhanging the photo resist, the gate metal and gate insulator will self aligned
with the drain and source. Finally, the MOSFET is finished by using lift-off method
where the separations distance between gate and Au ohmic contact is defines by the
undercut of the Au beneath the photo resist [15].
Figure 2.9
Fabrication process for MOSFET [15]
16
2.7
Fabrication of Silicon Nanowire Field-Effect Transistor
There are two types of technique to fabricate a Si NWFET which are topdown and bottom-up. The first type is known as top-down method (a) where
electron-beam technique is combined with lithographic processes. Si NWFET is
physically being etching as a single-crystalline silicon wafer. First of all, the whole
silicon layer is doped with low- density boron or phosphorous. Then, a specific
region is defined with a photo mask pattern and the specific region is doped heavily.
Next, the micrometer-sized source and drain electrodes are finished by RIE etching.
Lastly is the most important part where the nanometer-sized Si NW is fabricated with
an electric-resist pattern [16] and finished by an E-beam etching [17].
The second type for Si NWFET fabricating is known as bottom-up processes
(b). The process starts with the growth of Si NW, normally in a chemical vapor
deposition (CVD) reaction via the VLS mechanism where the Si NW is synthesis by
the VLS [16]. Next, the Si NW is deposited and aligned on a silicon substrate. Then,
a photo mask is pattern to define the source and drain electrodes. This process is also
known as photolithographic writing or electron beam lithographic procedures. Next,
a thermal evaporation of metal electrodes is carried out to deposit the source and
drain contacts. Lastly, the remaining photo resist is lift-off with remover PG. Figure
below show the step to fabricate a Si NWFET for both approaches [17].
17
Figure 2.10
2.8
Fabrication process for Si NWFET [17]
Compact Model of Si NWFET
A compact model for SNWFET has also been developed for circuit
simulation in recent years [18]. Previous research by Jie Yang et all proposed a
compact model for Si NWFET. Figure below show the stereoscopic schematic and
cross sectional schematic of the model.
18
Figure 2.11
Stereoscopic and cross sectional schematic of compact model [18].
Figure below show the energy-band diagram of an n-type Si NWFETT. tox =
2 nm, R = 10 nm, L =1 μm, and metal gate with mid gap work function is used unless
otherwise specified in all comparisons with TCAD [18].
Figure 2.12
Energy-band diagram of n-type compact model [18].
The compact model was compares with another corresponding numerical
results obtained from the Synopsys TCAD Sentaurus Device simulation tool. The
result from the comparison between the model prediction and TCAD numerical
19
solution on the I-V developed are used to compare between the bias, doping
concentration and dimension of the Si NWFET [18].
Figure 2.13
Figure 2.14
I ds –V ds with different dimensions (R = 10 and 5 nm) [18].
I ds –V ds with different doping concentrations (symbols: TCAD; lines:
model) [18].
20
Figure 2.15
Ids–Vgs with different radii [18].
2.9 SPICE Modeling and device specification for SPICE model
The SPICE model was build based on the FETtoy model proposed by
A.Rahman [2] and continued by Jing Wang. However a new model was built to be
compared with a nano MOSFET. The new SPICE model created was differed on
many aspects based on various study.
The value used for the thickness for the gate insulator is 1.0nm. The value is
differ compare to the model proposed by Jing Wang which is 1.5nm. The reason to
choose that value is because based on further performance evaluation of ballistic
Silicon Nanowire transistor by Jing Wang proposed in order to obtain similar I-V
curves for P-FET and N-FET the oxide thickness is set to 1nm and the temperature is
300K. Moreover it is selected to guarantee that only the lowest sub band at each
valley is occupied [19].
21
Figure 2.16
I-V curves for the n-type/p-type SNWT with D=1.36nm and the ratio
of the p FET ON current to the n FET’s vs. D. The oxide thickness is assumed to be
1nm and the temperature is 300K [19].
Next, The gate insulator dielectric constant used for this SPICE model is
similar with the one proposed by Jing Wang which is 3.9 [8]. The reason is because
the value for dielectric constant, k for a SiO 2 layer is 3.9. Figure below show the I DS
vs V DS characteristic of the simulated Si NWFET with a SiO 2 layer 3.9.
22
Figure 2.17
I DS vs V DS for SiO 2 [8] .
The value for transport effective mass used for the SPICE model is same with
the default value which is 0.19. The value was set to be sufficiently small so the
device reaches the Quantum Capacitance Limit (QCL). For a nanowire FET, I ON
increases with a decreasing mt and saturates when mt is sufficiently small.
The value used for nanowire diameter in the SPICE model is 1.36nm differ
with the model proposed by Jing Wang which used a 1.0nm nanowire. Based on
figure above, the transport effective mass is depend on the value of the diameter.
Decreasing the diameter will produce smaller transport effective mass. The ballistic
p-SNWT delivers half the ON-current of a ballistic n-SNWT for large diameter
nanowires. However, the ON-current of the p-type SNWT approaches that of its ntype counterpart for small diameters nanowire.
The value used for the valley degeneracy is 2 and the temperature used for
the SPICE model is same with the value used previously which is 300 Kelvin which
is at room temperature. The terminal voltages used for SPICE model is set at 11 volt
it can be limited up to 11 volt. The voltage ranges for the SPICE model is set in
23
between 0 volt and 1 volt. The value is used as the voltage use for transistor was very
small between 0 and 1 volt.
The Fermi level energy choose for SPICE model are differs for the n-type and
p-type doping materials. The Fermi energy was selected based on energy gap for
silicon which is 1.12 eV. Antimony (Sb) was selected as donor agent for n-type while
Boron (B) was used as acceptor agent for p-type. Antimony (Sb) has a -0.039 eV
Fermi energy and Boron (B) has a 0.045 eV [20].
Figure 2.18
Fermi energy level for different types of materials [21]
The gate control parameters are the same for the SPICE model and previous
model which is 0.88.The drain control parameters also same for the SPICE model
and previous model which is 0.035. These values were both calculated by Jing Wang
[8].
24
2.8 Curve Fitting
Uscf, is the equation summarized from the essential aspect of this Spice model. It
consists of three capacitors, CS, CG and, CD which describe the electrostatic [22]
couplings between the top of the barrier and the gate, the source and the drain,
respectively [19]. The potential at the top of the barrier is obtained as
where VG, VS, and VD are the applied biases at the gate, the source and the
drain, respectively, and QTop is the mobile charge at the top of the barrier, which is
determined by Uscf, the source and drain Fermi levels (EFS and EFD) and the E-k
relation for the channel material [23].
25
CHAPTER III
RESEARCH METHODOLOGY
3.1
Introduction
This project is focused on comparing the performance of Si NWFET with
benchmarking against nano MOSFET in terms of its I-V characteristic and DC
analysis. The logic gates performance will be evaluated in term of power
consumption, energy and delay for both Si NWFET and nano MOSFET. The
research methodology for this thesis was divided into several parts
•
First of all, literature review of previous thesis, journals, ballistic reports and
many others was done on Si NWFET. The properties and characteristic of Si
NWFET was study to have better understanding on Si NWFET
•
Secondly, a SPICE model for Si NWFET was built and then analyzed in
MATLAB. Curve fitting was done to obtain the USCF equation that going to
be used in HSPICE. Using HSPICE software, later on the USCF equation
was used to simulate the I-V characteristic for the Spice model and projected
in CosmosScope to view the result. Then, the logic circuit such as inverter,
NOR and NAND are built and simulate the result in CosmosScope
•
Then, a 32nm MOSFET is modified the parameters in the HSPICE script so
the I-V characteristic for both Si NWFET and nano MOSFET match and a
26
fair assessment can be done. The logic circuits for nano MOSFET also are
built.
•
Lastly, the performance for both Si NWFET and nano MOSFET were
evaluated in term of power consumption, energy and delay. The flowchart for
the research methodology is shown in Figure 3.1.
Literature review on Si
NWFET
Parameters for SPICE
model
Curve Fitting of USCF
equation
HSPICE
Comparison
Logic circuit modeling
Analysis of performance
Figure 3.1
Research methodology flowcharts
27
3.2
MATLAB
Matrix Laboratory (MATLAB) was developed by MathWorks in late 1970s.
It is a high level language and interactive environment for numerical computation,
visualization, and programming. It can be used to develop algorithm, analyze data,
and build models and applications. MATLAB can be used for a variety of
applications, including signal processing and communications, image and video
processing, control systems, test and measurement, computational finance, and
computational biology. The language, tools, and built-in math function can be
explore by multiple ways and it also reach solution faster than other programming
languages such as C/C++ or Java.
Figure 3.2
Matrix Laboratory (MATLAB) programmed
28
3.3
HSPICE
HSPICE was commercialized by Shawn and Kim Hailey of Meta Software
and now was owned by Synopsysis. HSPICE is a very popular circuit simulator as it
can provide accurate circuit simulation and offers foundry-certified MOS device
models with state-of-the-art simulation and analysis algorithms.
Figure 3.3
3.4
HSPICE simulator
CosmosScope
CosmosScope is used for simulation of data. CosmosScope such as the
powerful analysis and measurement capabilities, patented waveform-calculator
technology, and scripting language based on the industry standard Tcl/Tk make it has
unparalleled capability and flexibility to analyse design performance and ensure
design quality. The advantages of using CosmosScope are:
•
It supports all synopsys simulation products such as HSPICE.
•
It provides scripting language for easy customization.
•
It can perform post-processing of analog and digital simulation results
29
•
The graphs can be annotated automatically with design information.
•
The graphs can be saved and stored for further editing.
Figure 3.4
CosmosScope simulator
30
CHAPTER IV
RESULTS AND DISCUSSION
4.1
Introduction
A SPICE model for Si NWFET is build based on FETToy MATLAB script
proposed by A.rahman and extended by Jing Wang. The SPICE model was modified
the parameter by further study and research on ballistic report and thesis so the result
will be based on Si NWFET. I-V characteristic for the Si NWFET also determined
from the MATLAB script. Based on the self consistent voltage versus drain voltage
result from the MATLAB, a USCF equation is obtained by using fitting method for
the graph. Later on the USCF equation was used to simulate the I-V characteristic for
the Spice model in HSPICE and projected in CosmosScope to view the result. Then,
the logic circuit such as inverter, NOR and NAND are built. For the nano MOSFET,
a 32nm MOSFET is modified the parameters so the I-V characteristic for both Si
NWFET and nano MOSFET match and a fair assessment can be done [4].
31
4.2
SPICE model
The SPICE model was modified from FETToy model proposed by A.
Rahman and extended by Jing Wang. Few parameters had been changed so the
SPICE model is suitable to be used as Si NWFET. Here are the details on the
changes on the SPICE models;
No
INPUT PARAMETERS
SYMBOLS
VALUE USED IN
SIMULATION
1
Gate insulator thickness
t
1.0e-9m
2
Gate insulator dielectric
epsr
3.9
constant
3
Transport effective mass
mt
0.19
4
Nano wire diameter
d
1.36e-9n
5
Valley degeneracy
Degan
2
6
Temperature
T
300K
7
Terminal voltage
NV
11V
8
Voltage Range
V
VI=0,VF=1.0
9
Fermi level
Ef
-0.039eV(n type)
0.045eV(p-type)
10
Gate control Parameter
Alpha g
0.88
11
Drain control parameter
Alpha d
0.035
Table 4.1
Device Model Specification at V gs = 1V.
Based on the SPICE model, a simulation on the MATLAB script was carried
out. Next, curve fitting was done on self consistent voltage versus drain voltage
graph from the SPICE result in order to obtain the USCF equation as shown in figure
4.1
32
0
-0.05
Self Consistent Voltage
-0.1
-0.15
-0.2
-0.25
-0.3
-0.35
-0.4
-0.45
0
0.1
Figure 4.1
4.3
0.2
0.3
0.4
0.6
0.5
Drain Voltage (V d)
0.7
0.8
0.9
Self consistent voltages versus drain voltage
USCF equation
Using the MATLAB software, the new equation for USCF, was obtained by
curve fitting the drain voltage (V D ) versus Self Consistent Voltage as shown in
figure 4.1. The equation that was obtained from the curve fitting method later was
used in HSPICE to simulate the result and projected resulted in CosmosScope since
the MATLAB script cannot be implemented into the HSPICE script.
The USCF equation result is compared with the result from SPICE model as
in figure below to make sure the equation is valid.
1
33
-5
7
x 10
6
Drain Current, Id [Ampere]
5
4
3
2
1
0
-1
-0.8
Figure 4.2
-0.6
-0.4
-0.2
0
Drain Voltage ,Vd [Volt]
0.2
0.4
0.6
0.8
Compared result of USCF equation and SPICE model
Before implementing the logic circuit, the IV characteristic for Si NWFET
and nano MOSFET are determined as to study the behavior of these materials. The IV characteristic for Si NWFET and nano MOSFET are shown in Figure 4.3 and
Figure 4.4.
1
34
-5
7
x 10
6
5
4
3
2
1
0
-1
-0.8
-0.6
Figure 4.3
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
I-V characteristic of Si NWFET
-5
7
x 10
6
5
4
3
2
1
0
-1
-1
-0.8
Figure 4.4
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
I-V characteristic for Si NWFET and nano MOSFET
Figure 4.5 is the I-V characteristic for n-type and for Si NWFET and nano
MOSFET. In figure 4.5, the saturation on current for Si NWFET and nano MOSFET
is approximately 60.6µA.Both models are designed to provide similar current
strength for a fair assessment between both models [4]. The rising slope for nano
MOSFET is smaller than the Si NWFET in figure 4.5. It shows that n type for nano
1
35
MOSFET is reaching the stability much lower compare to Si NWFET with steeper
slope.
-5
7
x 10
6
5
4
3
2
1
0
0
0.1
0.2
0.3
Figure 4.5
0.4
0.5
0.6
0.7
0.8
0.9
1
I-V characteristic for n-type
Figure 4.6 is the I-V characteristic for p-type for both models. In this figure,
the saturation on current is approximately 61µA. The rising slope for p-type nano
MOSFET is also smaller than the Si NWFET shows that nano MOSFET is reaching
the stability much lower compare to Si NWFET with steeper slope.
36
-5
7
x 10
6
5
4
3
2
1
0
-1
-1
-0.9
-0.8
-0.7
Figure 4.6
4.4
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
I-V characteristic for p-type
Device Circuit Analysis
Logic gates are the basis for building transistor. Logic gates were built to
analyze the potential of Si NWFET and nano MOSFET in circuit design by using
HSPICE and simulated in CosmosScope. The logic gates are implemented into
inverter, 2-inputs NOR gate (NOR2), 2-inputs NAND gate (NAND2), 3-inputs NOR
gate (NOR3) and 3-inputs NAND gate (NAND3). The function to implement the Si
NWFET and nano MOSFET into logic gates is to compare the performance of both
models in terms of devices performance.
37
4.4.1
Inverter
Inverter or Not gate is a logic gate which will complement the logic inputs.
The output from inverter will always inverse from the inputs [24]. Below are the
truth tables and output simulation for inverter.
INPUT
OUTPUT
A
NOT A
1
0
0
1
Table 4.2
Figure 4.7
Truth Table for inverter
Input and output waveforms of inverter for Si NWFET
38
Figure 4.8
Input and output waveforms of inverter for nano MOSFET.
From the result, both Si NWFET and nano MOSFET were succeeded to be
implemented into inverter. There is no problem showed by both models.
4.4.2
NOR2
NOR2 is a two inputs not OR gate and can be implemented by combining
inverter gates with 2 inputs OR gates. The output from NOR2 gates will always be
HIGH if both of the inputs are LOW and the output will always will be LOW if
either one or both of the input is HIGH. NOR2 is also can be looked as an inverted
inputs AND gate [24]. NOR2 is commonly used in building transistor and below is
the truth table for NOR2 gate.
39
INPUT
OUTPUT
A
B
NOR2
0
0
1
0
1
0
1
0
0
1
1
0
Table 4.3
Figure 4.9
Figure 4.10
Input and output waveforms of NOR2 gate for Si NWFET
Input and output waveforms of NOR2 gate for nano MOSFET.
40
implemented into NOR2 gates. There is no problem showed by both models except
for several noises produced by both models.
4.4.3
NAND2
NAND2 is a two inputs not AND gate and can be implemented by combining
inverter gates with 2 inputs AND gates. The output from NAND2 gates will be LOW
if both of the inputs are HIGH and the output will always will be HIGH if either one
or both of the input is LOW [24]. NAND2 is commonly used in building transistor
and below is the truth table for NAND2 gate.
INPUT
OUTPUT
A
B
NAND2
0
0
0
0
1
1
1
0
1
1
1
1
Table 4.4
41
Figure 4.11
Figure 4.12
Input and output waveforms of NAND2 gate for Si NWFET
Input and output waveforms of NAND2 gate for nano MOSFET.
implemented into NAND2 gates. There is no problem showed by both models except
42
4.4.4
NOR3
NOR3 is a three inputs not OR gate and can be implemented by combining
inverter gates with 3 inputs OR gates. The output from NOR3 gates will be HIGH if
all the three inputs are LOW and the output will always will be LOW if either one or
both or all of the input is HIGH [24]. Table below is the truth table for NOR3.
INPUT
A
B
C
Y
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
Table 4.5
Figure 4.13
OUTPUT
Input and output waveforms of NOR3 gate for Si NWFET
43
Figure 4.14
Input and output waveforms of NOR3 gate for nano MOSFET.
implemented into NOR3 gates. There is no problem showed by both models except
4.4.5
NAND3
NAND3 is a three inputs not AND gate and can be implemented by
combining inverter gates with 3 inputs AND gates. The output from NAND3 gates
will be LOW if all the three inputs are HIGH and the output will always will be
HIGH if either one or both or all of the input is LOW [24]. Table below is the truth
table for NOR3.
44
INPUT
A
B
C
Y
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
Table 4.6
Figure 4.15
OUTPUT
Input and output waveforms of NAND3 gate for Si NWFET
45
Figure 4.16
Input and output waveforms of NAND3 gate for nano MOSFET.
implemented into NAND3 gates. There is no problem showed by both models except
for several noises produced by both models
Based on the simulation results of the logic gates, the output waveform of Si
NWFET show a better result compared to nano MOSFET. As the logic circuit
become more complicated to the NAND3 gate, the noise spikes that occur on the
output waveform nano MOSFET is more obvious. Noise is an external interference
of a random and unwanted voltage that is induced into electronic circuits. logic gate
must have a certain amount of noise margin to not be influence by noise. These
noises can be eliminated by adding an on-chip decoupling capacitance to the circuit.
Thus, the spike that generated by the logic circuits will flow into the capacitor [25].
46
4.5
Performance result
The average power (AVG_POWER) and propagation delay (TPD) was
obtained from the simulation result of Si NWFET and nano MOSFET. While, the
power delay product (PDP) and energy delay product (EDP) is calculated from the
output by using the formula as given as
PDP = AVG_POWER × TPD
EDP = PDP × TPD = AVG_POWER × TPD × TPD
Where AVG_POWER is the average power of V dd and TPD is the propagation delay.
The performance resulted of Si NWFET and nano MOSFET are tabulated in table
below.
LOGIC
INVERTER
NAND2
NAND3
NOR2
NOR3
GATES
TPD
1.8332e-13
AVG_POWER
-1.9811e-06
PDP
EDP
-3.6318e-19
-6.6579e-32
3.7404e-13 5.6859e-13 3.3374e-13 5.7072e-13
-2.1205e-
-1.7560e-
-2.1157e-
-1.7559e-
06
06
06
06
-7.9314e-
-9.9845e-
-7.0609e-
-1.0021e-
19
19
19
18
-2.9666e-
-5.6772e-
-2.3565e-
-5.7192e-
31
31
31
31
47
Metal Oxide Field-Effect Transistor
LOGIC
INVERTER
NAND2
NAND3
NOR2
NOR3
10.8819e-12
19.518e-
26.967e-
13.898e-
30.516e-12
12
12
12
GATES
TPD
AVG_POWER
-611.75e-06
-1.222e-03
-1.832e-03
-3.237e-03
-5.337e-03
PDP
-6.6570 e-15
-23.86e-15
-49.43e-15
-44.99e-15
-162.9e-15
EDP
-7.244e-26
-4.657e-25
-1.333e-24
-6.253e-25
-4.970e-24
Table 4.7
Propagation Delay (TPD), Average Power (AVG_POWER), Power
Delay Product (PDP) and Energy Delay Product (EDP)
4.5.1
Power Delay Product (PDP)
Power delay product is the value of average power times with propagation
delay. A device with lower PDP is better than device with higher PDP as the delay
will be smaller. Hence the device is more efficient and faster. Figure 13 shows the
difference between power-delay product (PDP) between Si NWFET and nano
MOSFET. The simulation results show that the PDP of Si NWFET is lower than that
of MOSFET by several magnitudes [4]
48
Power Delay Product
-12
10
Power Delay Product
-14
10
MOSFET
SiNWFET
-16
10
-18
10
-20
10
INV
Figure 4.17
4.5.2
NAND2 NAND3 NOR2
Logic Gates
NOR3
PDP of Si NWFET versus nano MOSFET
Energy Delay Product (EDP)
Energy delay product is the value of PDP times with propagation delay. A
device with lower EDP is better than device with higher EDP as the energy will be
smaller. Hence the device will consume less power and this is necessary to make sure
the device is energy- efficient low power architecture. Figure 14 shows energy-delay
product (EDP) between Si NWFET and nano MOSFET. The EDP for Si NWFET is
also lower than the EDP for nano MOSFET. Based on these two figures, it shows
that Si NWFET is better in terms of energy-efficient low power architecture [4].
49
-22
10
-24
10
-26
10
MOSFET
SiNWFET
-28
10
-30
10
-32
10
INV
Figure 4.18
NAND2 NAND3 NOR2
Logic Gates
NOR3
EDP of Si NWFET versus nano MOSFET
Table 4.8 below shows the propagation delay (TPD) for logic gates NOT,
NAND2, NAND3, NOR2, and NAND3 for Si NWFET and nano MOSFET
Logic gate
Table 4.8
MOSFET
Propagation delay (TPD)
Si NWFET
nano MOSFET
Inverter
1.8332e-13
10.8819 e-12
NAND2
3.7404e-13
19.5184 e-12
NAND3
5.6859e-13
26.9674 e-12
NOR2
3.3374e-13
13.8984 e-12
NOR3
5.7072e-13
30.5164 e-12
Propagation delay computation between Si NWFET and nano
50
It is found that for both Si NWFET and nano MOSFET, NAND3 and NOR3
among the other logic gates has the largest propagation delay. This is because both of
NAND3 and NOR3 has multiple fan-in and fan-out each [4].
51
CHAPTER V
CONCLUSION AND FUTURE WORK
5.1
Conclusion
As a conclusion, a SPICE model of Si NWFET has been developed and
verified through the experimental data. Previous work by Jing Wang et al proves that
Si NWFET has many benefits and these research objectives to compare the
performance between Si NWFET and nano MOSFET proves the theory. With the
flexibility for dopant type and concentration, Si NWFET are really potential
candidates for the next transistor as it will be extremely useful for modeling, process
monitoring, as well as to circuit designer’s applications[10].
This thesis discusses the device and circuit level performance of Silicon
Nanowire Field-Effect Transistor (Si NWFET) with benchmarking against nano
Metal Oxide Semiconductor Field-Effect Transistor (nano MOSFET). The SPICE
model for Si NWFET was verified and the performance is compared with nano
MOSFET. This section will summarized the entire work done in order to complete
this thesis.
52
Chapter 1 is the introduction to this project. It provides the background for
the research including the problem statement, objective, scope, gantt chart and
outline of the thesis.
Chapter 2 discusses the literature review and the resource regarding to this
topic. It consists of the overview for this thesis. Various studies had been done based
on journals, thesis papers, ballistic reports and other to study the characteristic of Si
NWFET. The fabrication of Si NWFET and compact model of Si NWFET also been
studied to have better understanding on the materials. The SPICE model for Si
NWFET was build based on the study on the literature review.
Chapter 3 consists of the methodology for this thesis. The step by step
process of this thesis is explained thoroughly. It also include the explanations on the
software that had been used to carry out this thesis which is MATLAB, HSPICE and
CosmosScope.
Chapter 4 provided all the results obtained in this project. The USCF equation
obtained is one of the contributions of this thesis. The I-V characteristics of Si
NWFET and nano MOSFET is compared at similar current strength shows that Si
NWFET is better tha nano MOSFET in terms of reaching stability. Next, the logic
gates based on inverter, NAND2, NOR2, NAND3 and NOR3 are built for both
models shows that the noise spike produce increase as the logic circuits becomes
more complicated. The performance of both models then be studied shows that Si
NWFET is better than nano MOSFET in terms of energy- efficient low power
architecture. It also found that the delay increase as the logic circuits become more
complicated.
Overall, the research is successfully develop the I-V characteristic for both Si
NWFET and nano MOSFET models and compare the performance of both models in
terms of circuit and device performance. It also shows that the circuit performance of
53
Si NWFET is better than nano MOSFET in terms of EDP and PDP. Further
adjustment need to be done to Si NWFET so other characteristic can be improved
more for better device and circuit performance.
5.2
Future Work
(i)
More research works have to done since there are still some limitations in
order to manufacture Si NWFET.
(ii)
The performance of Si NWFET should be compare against other new
field-effect transistor such as Carbon Nanotube Field-Effect Transistor,
FinFETS and tri gate transistor.
(iii)
Release a set of guidelines that can be used to manufacture Si NWFET.
54
REFERENCES
[1]
T. Yu, R. S. Wang, R. Huang, J. A. Chen, J. Zhuge, and Y. Y. Wang,
"Investigation of Nanowire Line-Edge Roughness in Gate-All-Around
Silicon Nanowire MOSFETs," Ieee Transactions on Electron Devices, vol.
57, pp. 2864-2871, Nov 2010.
[2]
A. Rahman, J. Wang, J. Guo, M. S. Hasan, Y. Liu, A. Matsudaira, S. S.
Ahmed, S. Datta, and M. Lundstrom, FETToy, 2006.
[3]
W. Jing, "Device Physics and Simulation of Silicon Nanowire Transistors,"
Purdue University, 2005.
[4]
G. L. Tan MLP, Gehan AJ Amaratunga, "Device and circuit level
performance of carbon nanotube field effect transistor with benchmarking
against a nano mosfet," 2012.
[5]
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34, pp. 52-&, Jun 1997.
[6]
S. E. Thompson and S. Parthasarathy, "Moore's law: the future of Si
microelectronics," Materials Today, vol. 9, pp. 20-25, Jun 2006.
[7]
N. J. Gunther. (2007). Moore's Law: More or Less? Available:
http://www.cmg.org/measureit/issues/mit41/m_41_2.html
[8]
J. Wang, "Device Physics and Simulation of Silicon Nanowire Transistors,"
PhD, Purdue University, 2006.
[9]
Y. Cui, Z. H. Zhong, D. L. Wang, W. U. Wang, and C. M. Lieber, "High
performance silicon nanowire field effect transistors," Nano Letters, vol. 3,
pp. 149-152, Feb 2003.
[10]
Z. Z. Yi Cui, Deli Wang, Wayne U.Wang and Charles M. Lieber, "High
Performance Silicon Nanowire Field Effect Transistors," 2002.
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[11]
T. C. Wong, "Modification of silicon nanowire," Master of Philosophy, dept.
of Physics and Material Science, City University of Hong Kong, Hong Kong,
2004.
[12]
M. N. Masood, "Surface modification of silicon nanowire field-effect devices
with Si-C and Si-N bonded monolayers," Phd, University of Twente,
Enschede, the Netherlands, 2011.
[13]
D. Neamen, Semiconductor Physics And Devices, 3 ed. Avenue of the
Americas: McGraw-Hill, Inc, 2003.
[14]
M. D. E. S.M. Koo, Q.Li, C.A. Richter and E.M. Vogel. (2005, June 29).
Silicon nanowires as enhancement-mode Schottky barrier field-effect
transistors.
Nanotechnology
16.
Available:
http://www.nist.gov/public_affairs/techbeat/tb2005_0630.htm
[15]
A. Hokazono, K. Tsugawa, H. Umezana, K. Kitatani, and H. Kawarada,
"Surface p-channel metal-oxide-semiconductor field effect transistors
fabricated on hydrogen terminated (001) surfaces of diamond," Solid-State
Electronics, vol. 43, pp. 1465-1471, Aug 1999.
[16]
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detection time of nanowire biosensor," Applied Physics Letters, vol. 100, Apr
2012.
[17]
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for
biomedical
diagnosis
and
cellular
recording
investigation," Nano Today, vol. 6, pp. 131-154, Apr 2011.
[18]
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Compact Model of Silicon-Based Nanowire MOSFETs for Circuit
Simulation and Design," Ieee Transactions on Electron Devices, vol. 55, pp.
2898-2906, Nov 2008.
[19]
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"Performance evaluation of ballistic silicon nanowire transistors with atomicbasis dispersion relations," Applied Physics Letters, vol. 86, Feb 2005.
[20]
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nanowire field effect transistor in subthreshold conduction using high k
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[21]
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56
[22]
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Nanowire Field-Effect Transistors," Ieee Transactions on Electron Devices,
vol. 55, pp. 2939-2945, Nov 2008.
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Wiley-V C H Verlag Gmbh, 2010.
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capacitance," IEEE Journal of 1997.
57
APPENDIX A
SiNWFEToy MATLAB script
function
[I]
=
Ef,alphag,alphad )
SiNWFETToy(
t,d,epsr,mt,degen,T,
VI,VF,NV,
% function [I,V,Uscf,N] = SiNWFETToy( t,d,epsr,mt,T, VI,VF,NV,
Ef,alphag,alphad )
%
Inputs:
%
---------------%
t - insulator thickness (m)
%
d - NT diameter (m)
%
epsr - insulator dielectric constant
%
mt - Transport Effective mass
%
T - Temp (K)
%
%
VI - Initial Voltage
%
VF - Final Voltage
%
NV - # of bias points
%
%
Ef - Fermi Level
%
alphag - gate control parameter
%
alphad - drain control parameter
%
%
Outputs:
%
-----------------%
I = Current
%
V = Voltage
%
Uscf = Self Consistent Potential
%
N = Free charge
%
% Based on FETToy Originally developed by : Anisur Rahman
%
Reference:
%
[1] A. Rahman, J. Guo, S. Datta, and M. Lundstrom,
%
"Theory of Ballistic Nanotransistors", to appear in IEEE TED,
2003.
%
% Adapted for SiNWFETToy by : Jing Wang
% Latest Version Updated by : Sayed Hasan (05/24/2004)
% Modified By Michael Tan (29 April 2013 4:33pm)
%------------------------------------------------------------------%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%
58
%%
Original
Note
by
Anisur
Rahman
%%
%%--------------------------------------------------------------------------------%%
%%
Name:
FETToy
%%
%% Written by Anisur Rahman, Purdue University, Dec 24, 2002
%%
%%
email:
[email protected]
%%
%% Routines used: input.m, plot_output.m, fermi.m, Uscf_zero.m,
write_results.m
%%
%%
%%
%%
Reference:
%%
%%
[1]
A.
Rahman,
J.
Guo,
S.
Datta,
and
M.
Lundstrom,
%%
%% "Theory of Ballistic Nanotransistors", to appear in IEEE TED,
2003.
%%
%%
%%
%% Analytically calculates the ballistic I-V of a Double Gate ultra
thin body
%%
%% MOSFET assuming that only the lowest unprimed subband is occupied
(All
%%
%% constants are in MKS unit except energy, which is in eV)
%%
% Physical constants
m0=0.91e-30;
hbar=1.05e-34;
kB=1.38e-23;
q=1.6e-19;
eps0=8.85e-12;
m=mt*m0;
% Transverse mass of electron
kT=kB*T/q;
% Thermal voltage.
V=linspace(VI,VF,NV);
% Voltage (gate or drain) steps.
Cins=2*pi*epsr*eps0/log((t+d/2)/(d/2));
CG=Cins;
C_SIG=CG/alphag;
% C_SIG=sum of capacitors (see
eq. (7b) in [1]).
U0=q/C_SIG;
% Charging energy (eq. (8b) in
[1]).
% degeneracy is modified by Sayed Hasan (05/26/2004)
N1D= degen*m/hbar*(2*kT*q/pi/m)^0.5;
% Effective 1D density
of states (include both +k and -k, valley degeneracy is 1)
% End degen. modification
N0 = N1D*fermi(Ef/kT,1,-1/2);
% Electron concentration at
the top of the barrier in neutral device.
I0 = degen*(q*kB*T/pi/hbar);
% Valley degeneracy is given
as input in "degen"
N=zeros(NV,NV);
I=zeros(NV,NV);
Ef_mat=zeros(NV,NV);
Esub_max=zeros(NV,NV);
barrier.
% Mobile charge density.
% Current.
% Source Fermi level.
% Energy at the top of the
59
for
% Bias loop begins.
for kV=1:NV
Vg=V(kVg); Vd=V(kV);
mu1=Ef;
mu2=mu1-Vd;
Source and drain fermi levels.
UL=-(alphag*Vg)-(alphad*Vd);
Laplace potential.
kVg=1:NV
%
%
%
Uscf=fzero(@Uscf_zero,0,optimset('tolx',1e12),N1D,mu1,mu2,kT,UL,U0,N0);
Uscf=
...
(
-49821.90664
*Vg.^(8)+( 276605.122964749
)*Vg.^(7)+
(
-572162.606643442
)
*Vg.^(6)+(
573747.932958612
)*Vg.^(5)+ (
-298144.198888112
)*Vg.^(4)+ (
79535.103278405
)*Vg.^(3)+ (
-10290.716810145
)*Vg.^(2)+( 508.056933400
)*Vg+( 6.070806718
))*Vd.^(8)...
+
(
196872.2107
*Vg.^(8)+( -1109234.487759260
)*Vg.^(7)+
(
2316213.672502400
)
*Vg.^(6)+( -2337935.809217750 )*Vg.^(5)+ (
1220226.704813460
)*Vg.^(4)+ (
-326274.007912830
)*Vg.^(3)+ (
42302.679427669
)*Vg.^(2)+( -2102.545925492 )*Vg+( -27.19614939
))*Vd.^(7)...
+
(
-312692.829 *Vg.^(8)+( 1800600.496701210
)*Vg.^(7)+ (
-3810666.720886790 )
*Vg.^(6)+( 3881675.713082960
)*Vg.^(5)+ (
-2038198.159335660 )*Vg.^(4)+ (
546739.433373932
)*Vg.^(3)+ (
-71087.204801527
)*Vg.^(2)+( 3567.061344487
)*Vg+(
51.0970026
))*Vd.^(6)...
+
(
253070.1009
*Vg.^(8)+( -1508712.355813510
)*Vg.^(7)+
(
3258255.782258070
)
*Vg.^(6)+( -3363537.270613450 )*Vg.^(5)+ (
1781557.287609530
)*Vg.^(4)+ (
-480115.128448274
)*Vg.^(3)+ (
62675.629581024
)*Vg.^(2)+( -3190.414180341 )*Vg+( -52.28496904
))*Vd.^(5)...
+
(
-108169.5365 *Vg.^(8)+( 685944.804259376
)*Vg.^(7)+ (
-1531344.742644380 )
*Vg.^(6)+( 1614121.745432760
)*Vg.^(5)+ (
-866416.711570166
)*Vg.^(4)+ (
235160.879016970
)*Vg.^(3)+ (
-30883.588707723
)*Vg.^(2)+( 1609.076098899 )*Vg+( 31.64868694
))*Vd.^(4)...
+
(
22271.53089 *Vg.^(8)+( -161171.785884126
)*Vg.^(7)+ (
382459.258754723
)
*Vg.^(6)+( -417734.084840510
)*Vg.^(5)+ (
229232.491274840
)*Vg.^(4)+ (
-62960.734906854
)*Vg.^(3)+ (
8348.074489455
)*Vg.^(2)+( -453.519779289 )*Vg+( -11.50947092
))*Vd.^(3)...
+
(
-1549.327801 *Vg.^(8)+( 16638.401391004
)*Vg.^(7)+ (
-44882.821776885
)
*Vg.^(6)+( 52335.381299725
)*Vg.^(5)+ (
-29858.153049092
)*Vg.^(4)+ (
8378.347701676
)*Vg.^(3)+ (
-1128.377353262
)*Vg.^(2)+( 66.790567412
)*Vg+( 2.433815329
))*Vd.^(2)...
+
(
36.87600022 *Vg.^(8)+( -738.997042369
)*Vg.^(7)+ (
2239.568783041
)
*Vg.^(6)+( -2766.250583763
)*Vg.^(5)+ (
1642.588988959
)*Vg.^(4)+ (
-473.774070097
)*Vg.^(3)+ (
64.339954577
)*Vg.^(2)+( -4.562704937
)*Vg+( -0.287117619
))*Vd.^(1)...
+
0.486995525 *Vg.^(8)+( -0.058767876
)*Vg.^(7)+ (
-2.782055017
)
*Vg.^(6)+( 3.986354963
)*Vg.^(5)+ (
-1.504827571
)*Vg.^(4)+ (
-0.629335510
)*Vg.^(3)+ (
0.608392156
)*Vg.^(2)+( -0.326077033
)*Vg+( -2.34E-06);
60
load zb.mat
nu=8;
na=8;
Answer=0;
check=na;
for ni=1:na+1
Answer= Answer+ polyval(zb(ni,:),Vg).*Vd.^(check);
check=check-1;
end
Uscf=Answer;
dN=0.5*N1D*(fermi((mu1-Uscf)/kT,1,-1/2)+fermi((mu2Uscf)/kT,1,-1/2))-N0;
% Mobile charge induced by gate and drain
N(kV,kVg)=dN;
eta1=(mu1-Uscf)/kT;
eta2=(mu2-Uscf)/kT;
% Vd changes along fixed column and Vg changes along fixed
row.
I(kV,kVg)=I0*(fermi(eta1,1,0)-fermi(eta2,1,0));
Esub_max(kV,kVg)=Uscf; Ef_mat(kV,kVg)=mu1;
% Added by Sayed Hasan 5/26/2004
Us(kV,kVg) = Uscf;
% Calculate Quantum Capacitance and average velocity
%%%%%%%%%%%%%%%%%% added by Sayed Hasan 05/24/2004
if ((kV==2)|(kV==NV)),
deltaU = 0.002*kT;
if (kV==2),
N_U2
=
0.5*N1D*(fermi((mu1-Uscf+deltaU/2)/kT,1,1/2)+fermi((mu2-Uscf+deltaU/2)/kT,1,-1/2))-N0;
N_U1
=
0.5*N1D*(fermi((mu1-Uscf-deltaU/2)/kT,1,1/2)+fermi((mu2-Uscf-deltaU/2)/kT,1,-1/2))-N0;
CQ(1, kVg) = q*(N_U2-N_U1)/deltaU;
elseif (kV==NV),
N_U2
=
0.5*N1D*(fermi((mu1-Uscf+deltaU/2)/kT,1,1/2)+fermi((mu2-Uscf+deltaU/2)/kT,1,-1/2))-N0;
N_U1
=
0.5*N1D*(fermi((mu1-Uscf-deltaU/2)/kT,1,1/2)+fermi((mu2-Uscf-deltaU/2)/kT,1,-1/2))-N0;
CQ(2, kVg) = q*(N_U2-N_U1)/deltaU;
v_ave(kVg)=I(kV,kVg)/q/(dN+N0);
end
end
end
end
%
Bias loop ends.
% Transconductance, gm and output conductance,
calculated at highest gate and drain biases
gm=(I(NV,NV)-I(NV,NV-1))/(V(NV)-V(NV-1));
gd=(I(NV,NV)-I(NV-1,NV))/(V(NV)-V(NV-1));
Av=gm/gd;
vinj=I(NV,NV)/(q*N(NV,NV));
gd
and
vinjare
61
% Calculate S and DIBL
%%%%%%%%%%%%%%%%%%
09/09/2003
Ie1=log10(I(NV,:));
Ie2=log10(I(2,:));
vv1=interp1(Ie1,V,log10(I(NV,1)),'spline');
vv2=interp1(Ie1,V,log10(2*I(NV,1)),'spline');
vv3=interp1(Ie2,V,log10(I(NV,1)),'spline');
S=(vv2-vv1)/log10(2)*1000;
DIBL=(vv3-vv1)/(V(NV)-V(2))*1000;
added
by
Jing
Wang
%%%%%%%%%%%%%%%
OUTPUT
(Sayed
Hasan:
5/25/2004)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
plot_output;
% Plot results
% save_charge;
% Save q*N
% save_current;
% Save I
% save_uscf;
% Save Us
% write_results;
% Write results in results.m file
save rawdata;
% save matlab variables
Plot Output MATLAB script
% Plotting Results
% Original: Anisur Rahman
% Modified By:
%
Jing Wang
%
Sayed Hasan (05/26/2004)
%-----------------------------------------------------------------------lwpl=2;
% Plot line width
lwbor=1;
% Border line width
fsize=18;
% Font size
string_matrix=[];
for m=1:NV,
string_matrix
=
strvcat(string_matrix,
['Vgs
num2str(V(m),3)]);
end
% Plotting Id-Vg (Semilog)
figure(2);
if (NV > 1),
h1=semilogy(V,I([2,NV],:));
set(gca,'Fontsize',[fsize],'linewidth',[lwbor]);
=
legend(['V_{Ds}=',num2str(V(2),3)],['V_{Ds}=',num2str(V(end),3)],
2);
else
h1=semilogy(V,I, 'k');
end
xlabel('V_G [Volt]');
ylabel('I_{DS} [A]');
set(h1,'linewidth',[lwpl]);
set(gca,'xlim',[V(1) V(NV)]);
print -dpsc Id_vs_Vgs_log;
% Plotting Id-Vg (linear)
figure(1);
if (NV > 1),
',
62
h1=plot(V,I([2,NV],:));
2);
else
h1=plot(V,I, 'k');
end
print -dpsc Id_vs_Vgs_lin;
% Plotting Id-Vd
figure(3);
% load predict.mat
xi=0:0.1:1;
% yi = interp1(Vpredict, Ipredict, xi, 'cubic');
load ori
Inew = interp1(V, I, xi, 'cubic') ;
h1 = plot(-xi, Inew, '-b');
hold on;
h1 = plot (xi, Inew, '-b');
hold on;
plot(V,Iori,'.r')
legend(string_matrix, -1);
%set(gca,'Fontsize',[fsize],'linewidth',[lwbor],'plotboxaspectratio'
,[2,1,1]);
xlabel('V_D [Volt]');
set(gca,'xlim',[-1 V(NV)]);
print -dpsc Id_vs_Vds;
figure(4)
h2 = plot(V, q*N([2,NV],:));
ylabel('mobile charge [C/m]');
2);
print -dpsc N_vs_Vgs_lin;
save rawdata;
% save matlab variables
63
load rawdata
figure(100)
h1=plot (V,Us);
set(h1,'linewidth',2.3);
set(gca,'Fontsize',14,'linewidth',3,'FontWeight',
'FontName','Arial');
ylabel('Self Consistent Voltage')
xlabel('Drain Voltage (V_{d})')
fh = figure(100); % returns the handle to the figure object
set(fh, 'color', 'white'
'bold',
Interactive
% SiNWFETToy (Toy model to simulate I-V characteristics of Si
NanoWire(NW) FETs)
%
%
% Input
% ----% Device Specification:
%
Gate Insulator Thickness, t (m)
%
Gate Insulator Dielectric Constant, epsr
%
Transport Effective Mass, mt
%
Wire Diameter, d (m)
%
Temperature, T (K)
%
% Terminal Voltage: Number of Bias Points, NV
%
Voltage Range, VI,VF (V)
%
% Analytical Model: Source Fermi Level, Ef (eV)
%
Get Control Parameter, alphag
%
Drain Control Parameter, alphad
%
% Output
% -----% 1. Text files:
%
A. current_data.txt
%
B. results.txt
%
% 2. Following plots:
%
A. Id vs. Vgs At 2nd and Last Drain bias (Smilog) :
Filename: Id_vs_Vgs_log.ps
%
B. Id vs. Vgs At 2nd and Last Drain bias (Linear) :
Filename: Id_vs_Vgs_lin.ps
%
C. Id vs. Vds At Different Vgs (Linear)
:
Filename: Id_vs_Vds.ps
%
D. Mobile at top of the barrier vs. Vds @ Different Vgs :
Filename: N_vs_Vds.ps
%
E. Quantum Capacitance vs. Vgs at Maximum Vds
:
Filename: CQ_vs_Vgs.ps
%
F. Average Velocity vs. Vgs at Maximum Vds
:
Filename: Velocity_vs_Vgs.ps
%
% 3. Matlab Rawdata:
%
A. Rawdata.mat
%
% Interface Script Written by : Sayed Hasan (05/24/2004)
%-------------------------------------------------------------------------
64
clc;
clear all;
close all;
% ----------------% Input Parameters
% ----------------fprintf('Si NanoWire MOSFET Simulation ...\n');
% Device Specification:
%==========================================
fprintf('Device Specifications:\n');
fprintf('======================\n');
% Gate Insulator Thickness, t (m)
t = [];
while isempty(t)
fprintf('
Gate Insulator Thickness (m):
');
t = input('t = ');
if isempty(t)
t = 1.0e-9; % Default value
fprintf('\b\b 1.0e-9 (Using Default ...)\n');
end
end
% Gate Insulator Dielectric Constant, epsr
epsr = [];
while isempty(epsr)
fprintf('
Gate Insulator Dielectric Const.:
epsr = input('epsr = ');
if isempty(epsr)
epsr = 3.9; % Default value
fprintf('\b\b 3.9 (Using Default ...)\n');
end
end
% Transport Effective Mass, mt
mt = [];
while isempty(mt)
fprintf('
Transport Effective Mass:
mt = input('mt = ');
if isempty(mt)
mt = 0.19; % Default value
fprintf('\b\b 0.19\n');
end
end
');
');
% NT Diameter, d (m)
d = [];
while isempty(d)
fprintf('
NanoWire Diameter (m):
');
d = input('d = ');
if isempty(d)
d = 1.36e-9; % Default value
fprintf('\b\b 1.36e-9 (Using Default ...)\n');
end
end
% Valley Degeneracy
65
degen = [];
while isempty(degen)
fprintf('
Valley Degeneracy:
degen = input('g = ');
if isempty(degen)
degen = 2; % Default value
fprintf('\b\b 2 (Using Default ...)\n');
end
end
% Temperature, T (K)
T = [];
while isempty(T)
fprintf('
Temperature (K):
T = input('T = ');
if isempty(T)
T = 300; % Default value
end
fprintf('\n');
end
% Terminal Voltage:
%==========================================
fprintf('Terminal Voltage:\n');
fprintf('=================\n');
% Number of Bias Points, NV
NV = [];
while isempty(NV)
fprintf('
Number of Bias Points: ');
NV = input('NV = ');
if isempty(NV)
NV = 11; % Default value
end
end
% Voltage Range, VI,VF (V)
VI = [];
VF = [];
while isempty(VI) | isempty(VF)
fprintf('
Voltage Range (V):\n');
fprintf('\t\t\t');
VI = input('(Initial) VI = ');
if isempty(VI)
VI = 0; % Default value
end
fprintf('\t\t\t');
VF = input('(Final) VF = ');
if isempty(VF)
VF = 1.0; % Default value
end
fprintf('\n');
end
% Analytical Model:
%==========================================
fprintf('Analytical Model:\n');
fprintf('=================\n');
');
');
66
% Source Fermi Level, Ef (eV)
Ef = [];
while isempty(Ef)
fprintf('
Source Fermi Level (eV):
');
Ef = input('Ef = ');
if isempty(Ef)
Ef = -0.039; % Default value
fprintf('\b\b -0.039 (Using Default ...)\n');
end
end
% Get Control Parameter, alphag
alphag = [];
while isempty(alphag)
fprintf('
Gate Control Parameter:
');
alphag = input('alphag = ');
if isempty(alphag)
alphag = 0.88; % Default value
end
end
% Drain Control Parameter, alphad
alphad = [];
while isempty(alphad)
fprintf('
Drain Control Parameter:
');
alphad = input('alphad = ');
if isempty(alphad)
alphad = 0.035; % Default value
end
fprintf('\n');
end
% Call Main Program
% ================================
I = SiNWFETToy( t,d,epsr,mt,degen,T, VI,VF,NV, Ef,alphag,alphad );
EDP PDP Matlab Script
clear all
close all
clc
load edp.mat
load pdp.mat
load edpm.mat
load pdpm.mat
figure(1)
semilogy(edpm([1:5],1),edpm([1:5],2),'.r','LineWidth',3,'MarkerSize',4)
hold on
semilogy(edp([1:5],1),edp([1:5],2),'b','LineWidth',3,'MarkerSize',4);
'bold',
67
h_legend=legend('MOSFET','SiNWFET');
set(h_legend,'FontSize',12,'FontWeight', 'bold', 'FontName','Arial')
legend('location','East')
legend('boxoff')
title('Energy Delay Product')
w=['INV ';'NAND2';'NAND3';'NOR2 ';'NOR3 '];
set(gca,'xtick',[1 2 3 4 5],'xticklabel',w);
set(gcf,'Color','w')
set(gca,'xlim',[0 6]);
xlabel('Logic Gates');
ylabel('Energy Delay Product');
figure(2)
semilogy(pdpm([1:5],1),pdpm([1:5],2),'.r','LineWidth',3,'MarkerSize',4);
hold on
semilogy(pdp([1:5],1),pdp([1:5],2),'b','LineWidth',3,'MarkerSize',4);
'bold',
h_legend=legend('MOSFET','SiNWFET', -1);
set(h_legend,'FontSize',12,'FontWeight', 'bold', 'FontName','Arial')
legend('location','East')
legend('boxoff')
title('Power Delay Product')
w=['INV ';'NAND2';'NAND3';'NOR2 ';'NOR3 '];
set(gca,'xtick',[1 2 3 4 5],'xticklabel',w);
set(gcf,'Color','w')
set(gca,'xlim',[0 6]);
xlabel('Logic Gates');
ylabel('Power Delay Product');
68
APPENDIX B
HSPICE netlist for Si NWFET
Csmike.lib
* Library name: CSmike
********************************************************************
.LIB CSmike
.PROTECT
.OPTIONS PARHIER=LOCAL
.OPTIONS EPSMIN=1E-99
.OPTIONS EXPMAX=37
.INC 'param.lib'
********************************************************************
* N-CNFET Level 1 Sub-circuit Definition
********************************************************************
.SUBCKT nCNT Drain Gate Source Efi=Ef
*********************************************************************
* Parameter definition
*********************************************************************
* The 4-piece cubic spline coefficient
.PARAM
*+
Vsc(Vg,Vd,Vs)='-0.035*(Vd-Vs) + 0.6815*(Vg-Vs)^(4) - 0.90332*(Vg-Vs)^(3) +
0.36015*(Vg-Vs)^(2) - 0.92247*(Vg-Vs) + 0.00039056'
+
Vsc(Vg,Vd,Vs)='(-49821.90664* (Vg-Vs)^(8)+ (276605.122964749)* (Vg-Vs)^(7)+ (-
572162.606643442)*
(Vg-Vs)^(6)+
(573747.932958612)*
298144.198888112)*
(Vg-Vs)^(4)+
(79535.103278405)
(Vg-Vs)^(5)+
(-
*(Vg-Vs)^(3)+
(-
69
10290.716810145)*(Vg-Vs)^(2)+
(508.056933400)
*(Vg-Vs)+ (6.070806718 )) *(Vd-
Vs)^(8)+\\
(196872.2107*
(Vg-Vs)^(8)+
(-1109234.487759260)*
(Vg-Vs)^(7)+
(2316213.672502400)*
(Vg-Vs)^(6)+
(-2337935.809217750)*(Vg-Vs)^(5)+
(1220226.704813460)*
(Vg-Vs)^(4)+
(-326274.007912830)*(Vg-Vs)^(3)+
(42302.679427669) *(Vg-Vs)^(2)+
Vs)^(7)+
(-2102.545925492)*(Vg-Vs)+ (-27.19614939)) *(Vd-
\\
(-312692.829*
(Vg-Vs)^(8)+ (1800600.496701210)*
3810666.720886790)*(Vg-Vs)^(6)+
(3881675.713082960)*
2038198.159335660)*(Vg-Vs)^(4)+
(546739.433373932)
71087.204801527)*(Vg-Vs)^(2)+
(Vg-Vs)^(7)+ (-
(Vg-Vs)^(5)+
(-
*(Vg-Vs)^(3)+
(-
( 3567.061344487)*(Vg-Vs)+ (51.0970026))
*(Vd-
Vs)^(6)+ \\
(253070.1009*
(Vg-Vs)^(8)+
(-1508712.355813510)*
(Vg-Vs)^(7)+
(3258255.782258070)*
(Vg-Vs)^(6)+
(-3363537.270613450)*(Vg-Vs)^(5)+
(1781557.287609530)*
(Vg-Vs)^(4)+
(-480115.128448274)*(Vg-Vs)^(3)+
(62675.629581024) *(Vg-Vs)^(2)+
(-3190.414180341)*(Vg-Vs)+ (-52.28496904)) *(Vd-
Vs)^(5)+\\
(-108169.5365* (Vg-Vs)^(8)+ (685944.804259376)*
1531344.742644380)*(Vg-Vs)^(6)+
866416.711570166)*
(1614121.745432760)*
(Vg-Vs)^(4)+
30883.588707723)*(Vg-Vs)^(2)+
(235160.879016970)
(Vg-Vs)^(7)+ ((Vg-Vs)^(5)+
(-
*(Vg-Vs)^(3)+
(-
(1609.076098899) *(Vg-Vs)+ (31.64868694))
*(Vd-
Vs)^(4)+ \\
(22271.53089*
(382459.258754723)*
(Vg-Vs)^(8)+
(Vg-Vs)^(6)+
(-161171.785884126)*
(Vg-Vs)^(7)+
(-417734.084840510)*
(Vg-Vs)^(5)+
(229232.491274840)* (Vg-Vs)^(4)+ (-62960.734906854) *(Vg-Vs)^(3)+ (8348.074489455)
*(Vg-Vs)^(2)+ (-453.519779289) *(Vg-Vs)+ (-11.50947092)) *(Vd-Vs)^(3)+ \\
(-1549.327801* (Vg-Vs)^(8)+ (16638.401391004)*
(Vg-Vs)^(7)+ (-
44882.821776885)* (Vg-Vs)^(6)+ (52335.381299725)* (Vg-Vs)^(5)+ (-29858.153049092)*
(Vg-Vs)^(4)+
(8378.347701676)
*(Vg-Vs)^(3)+
(-1128.377353262)
*(Vg-Vs)^(2)+
(66.790567412) *(Vg-Vs)+ (2.433815329)) *(Vd-Vs)^(2)+\\
(36.87600022*
(2239.568783041)*
(Vg-Vs)^(8)+ (-738.997042369)*
(Vg-Vs)^(6)+ (-2766.250583763)*
(Vg-Vs)^(4)+ (-473.774070097)
(Vg-Vs)^(5)+ (1642.588988959)*
*(Vg-Vs)^(3)+ (64.339954577)
4.562704937) *(Vg-Vs)+ (-0.287117619)) *(Vd-Vs)^(1)+\\
(Vg-Vs)^(7)+
*(Vg-Vs)^(2)+
(-
70
0.486995525*
2.782055017)*
(Vg-Vs)^(8)+ (-0.058767876)*
(Vg-Vs)^(6)+ (3.986354963)*
Vs)^(4)+ (-0.629335510)
(Vg-Vs)^(7)+ (-
(Vg-Vs)^(5)+ (-1.504827571)*
*(Vg-Vs)^(3)+ (0.608392156)
(Vg-
*(Vg-Vs)^(2)+ (-0.326077033)
*(Vg-Vs)+ (-2.34E-06) '
+
ans(Vg,Vd,Vs)='4*q*KB*T/h*(log(1.0+exp(q*(Ef-Vsc(Vg,Vd,Vs))/KB/T))-
log(1.0+exp(q*(Ef-Vsc(Vg,Vd,Vs)-(Vd-Vs))/KB/T)))'
* End of parameter definition
*********************************************************************
* The voltage controlled current source
GCNT
Drain
Source
CUR='ans(V(Gate),V(Drain),V(Source))'
Edrain Vdrain
Gnd VCVS Drain
Gnd 1
Egate Vgate
Gnd VCVS Gate
Gnd 1
Esource Vsource Gnd VCVS Source
Gnd 1
.ENDS nCNT
* End of nCNT Sub-circuit Definition
********************************************************************
* P-CNFET Level 1 Sub-circuit Definition
********************************************************************
.SUBCKT pCNT Drain Gate Source
Efi=Ef
*********************************************************************
* Parameter definition
*********************************************************************
* The 4-piece cubic spline coefficients
+
Vsc(Vg,Vd,Vs)=' ( -49821.90664 *(Vg-Vs)^(8)+ ( -276605.122964749
Vs)^(7)+
(
573747.932958612
79535.103278405
-572162.606643442
*(Vg-Vs)^(6)+( -
)*(Vg-Vs)^(5)+ ( -298144.198888112
)*(Vg-Vs)^(3)+ ( -10290.716810145
508.056933400 )*(Vg-Vs)+(
Vs)^(7)+
)
6.070806718
(
196872.2107
(
2316213.672502400
)*(Vg-Vs)^(4)+ ( )*(Vg-Vs)^(2)+ ( -
))*(Vd-Vs)^(8)- \\
*(Vg-Vs)^(8)+ ( +1109234.487759260 )*(Vg)
*(Vg-Vs)^(6)+(
+2337935.809217750 )*(Vg-Vs)^(5)+ ( 1220226.704813460
(
)*(Vg-
+326274.007912830
)*(Vg-Vs)^(3)+ ( 42302.679427669
+2102.545925492
)*(Vg-Vs)+(
)*(Vg-Vs)^(4)+
(
)*(Vg-Vs)^(2)+
-27.19614939 ))*(Vd-Vs)^(7)+ \\
71
Vs)^(7)+
(
-312692.829
*(Vg-Vs)^(8)+ ( -1800600.496701210
(
-3810666.720886790
)
)*(Vg-
*(Vg-Vs)^(6)+( -
3881675.713082960
)*(Vg-Vs)^(5)+ ( -2038198.159335660
)*(Vg-Vs)^(4)+ ( -
546739.433373932
)*(Vg-Vs)^(3)+ ( -71087.204801527
)*(Vg-Vs)^(2)+ ( -
3567.061344487
)*(Vg-Vs)+(
51.0970026
(
253070.1009
*(Vg-Vs)^(8)+ ( +1508712.355813510 )*(Vg-
(
3258255.782258070
Vs)^(7)+
))*(Vd-Vs)^(6)- \\
)
*(Vg-Vs)^(6)+(
+3363537.270613450 )*(Vg-Vs)^(5)+ ( 1781557.287609530
(
+480115.128448274
)*(Vg-Vs)^(3)+ ( 62675.629581024
+3190.414180341
)*(Vg-Vs)+(
Vs)^(7)+
(
-108169.5365
(
-1531344.742644380
)*(Vg-Vs)^(4)+
)*(Vg-Vs)^(2)+
-52.28496904 ))*(Vd-Vs)^(5)+ \\
*(Vg-Vs)^(8)+ ( -685944.804259376
)
)*(Vg-
*(Vg-Vs)^(6)+( -
1614121.745432760
)*(Vg-Vs)^(5)+ ( -866416.711570166
)*(Vg-Vs)^(4)+ ( -
235160.879016970
)*(Vg-Vs)^(3)+ ( -30883.588707723
)*(Vg-Vs)^(2)+ ( -
1609.076098899
)*(Vg-Vs)+(
31.64868694
(
22271.53089
*(Vg-Vs)^(8)+ ( +161171.785884126
(
382459.258754723
Vs)^(7)+
(
)
+62960.734906854
)*(Vg-Vs)^(3)+ ( 8348.074489455
+453.519779289
)*(Vg-Vs)+(
-1549.327801
(
-44882.821776885
Vs)^(7)+
)
)*(Vg-Vs)^(4)+ ( -8378.347701676
)*(Vg-Vs)^(2)+ (
-66.790567412
(
36.87600022
*(Vg-Vs)^(8)+ ( +738.997042369
(
2239.568783041
)
1642.588988959
)*(Vg-Vs)^(3)+ (
+4.562704937 )*(Vg-Vs)+(
)
)*(Vg-Vs)^(4)+
64.339954577
0.608392156
(
)*(Vg-Vs)^(2)+
-0.287117619 ))*(Vd-Vs)^(1)+ \\
*(Vg-Vs)^(6)+( -3.986354963
)*(Vg-Vs)^(4)+ (
)*(Vg-
*(Vg-Vs)^(6)+( +2766.250583763
0.486995525 *(Vg-Vs)^(8)+ ( +0.058767876
-2.782055017
)*(Vg-
*(Vg-Vs)^(6)+( -52335.381299725
))*(Vd-Vs)^(2)- \\
+473.774070097
1.504827571
)*(Vg-Vs)^(2)+
2.433815329
)*(Vg-Vs)^(5)+ (
(
-11.50947092 ))*(Vd-Vs)^(3)+ \\
)*(Vg-Vs)^(3)+ ( -1128.377353262
)*(Vg-Vs)+(
)*(Vg-Vs)^(4)+
*(Vg-Vs)^(8)+ ( -16638.401391004
)*(Vg-Vs)^(5)+ ( -29858.153049092
)*(Vg-
*(Vg-Vs)^(6)+(
)*(Vg-Vs)^(5)+ ( 229232.491274840
Vs)^(7)+
(
))*(Vd-Vs)^(4)- \\
+417734.084840510
(
(
+0.629335510
)*(Vg-Vs)^(2)+ (
)*(Vg-Vs)^(7)+
(
)*(Vg-Vs)^(5)+ (
-
)*(Vg-Vs)^(3)+
(
+0.326077033 )*(Vg-Vs)+(
-2.34E-06)'
72
+
ans(Vg,Vd,Vs)='-4*q*KB*T/h*(log(1.0+exp(q*(Ef-Vsc(Vg,Vd,Vs))/KB/T))-
log(1.0+exp(q*(Ef-Vsc(Vg,Vd,Vs)+(Vd-Vs))/KB/T)))'
* End of parameter definition
*********************************************************************
* The voltage controlled current source
GCNT
Drain
Source
CUR='ans(V(Gate),V(Drain),V(Source))'
Edrain Vdrain
Gnd VCVS Drain
Gnd -1
Egate Vgate
Gnd VCVS Gate
Gnd -1
Esource Vsource Gnd VCVS Source
Gnd -1
Evdd
VddM
Gnd VCVS Drain
Gnd 1
EVgg
VggM
Gnd VCVS Gate
Gnd 1
EVss
VssM
Gnd VCVS Source
Gnd 1
.ENDS pCNT
* End of pCNT Sub-circuit Definition
.UNPROTECT
.ENDL CSmike
73
APPENDIX C
HSPICE netlist for nano MOSFET
NTYPE
* NMOS and PMOS model
.LIB "PTM32nm.txt" CMOS_MODELS
.options POST
.options AUTOSTOP
.options INGOLD=2
DCON=1
*.options GSHUNT=1e-20 RMIN=1e-20
.options ABSTOL=1e-5 ABSVDC=1e-4
.options RELTOL=1e-2 RELVDC=1e-2
.options NUMDGT=4
PIVOT=13
***************************************************
*Beginning of circuit and device definitions
*Supplies and voltage params:
.param Supply=1
.param Vg='Supply'
.param Vd='Supply'
********************************************************************
* Define power supply
Vdd
Drain Gnd
Vd
Vss
Source Gnd
0
Vgg
Gate
Gnd
Vg
74
********************************************************************
* Main Circuits
M1 Drain Gate Source Source nmos L=32n W=35n
* pFET
*M2 Drain Gate Source Source pmos L=32n W=70n
********************************************************************
* Measurements
* test nFETs, Ids vs. Vds
.DC
Vdd START=0
STOP='Supply' STEP='0.01'
+ SWEEP Vgg START=0
STOP='Supply' STEP='0.1'
********************************************************************
.print I(Vdd)
.end
PTYPE
* NMOS and PMOS model
.LIB "PTM32nm.txt" CMOS_MODELS
.options POST
.options AUTOSTOP
.options INGOLD=2
DCON=1
*.options GSHUNT=1e-20 RMIN=1e-20
.options ABSTOL=1e-5 ABSVDC=1e-4
.options RELTOL=1e-2 RELVDC=1e-2
.options NUMDGT=4
PIVOT=13
***************************************************
*Beginning of circuit and device definitions
*Supplies and voltage params:
.param Supply=1
.param Vg='Supply'
.param Vd='Supply'
***********************************************************************
* Define power supply
75
Vdd
Drain Gnd
Vd
Vss
Source Gnd
0
Vgg
Gate
Gnd
Vg
***********************************************************************
* Main Circuits
* nFET
*M1 Drain Gate Source Source nmos L=32n W=35n
* pFET
M2 Drain Gate Source Source pmos L=32n W=70n
***********************************************************************
* Measurements
* test nFETs, Ids vs. Vds
.DC
Vdd START=0
STOP='-Supply' STEP='-0.01'
+ SWEEP Vgg START=0
STOP='-Supply' STEP='-0.1'
***********************************************************************
.print I(Vdd)
.end

UNIVERSITI TEKNOLOGI MALAYSIA

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