PROC2S - Terasic

PROC2S™
Rev.3
Data Book
Aug 2005
GiDEL products and their generated products are not
designed, intended, authorized, or warranted to be
suitable for use in life-support applications, devices or
systems or other critical applications
© 1998 - 2005 by GiDEL Ltd. All rights reserved. GiDEL,
PROC2S™, PROCWizard™, PROCMultiPort™ and other product
names are trademarks of GiDEL Ltd., which may be registered in
some jurisdictions. This information is believed to be accurate and
reliable, but GiDEL Ltd. assumes no responsibility for any errors
that may appear in this document. GiDEL reserves the right to
make changes in the product specifications without prior notice.
Windows NT, Windows XP, Windows 2000, Stratix II, EP2C35,
DDRII, CameraLink and other brands and product names are
trademarks or registered trademarks of their respective holders.
USA
560 S.Winchester Blvd.
San Jose,
CA 95128, USA
Worldwide
48 Harimon,
Ein Ayyala,
Israel 30825
Tel: 1 - 877 - 830 - 1647
Fax: 1 - 866 - 615 - 6810
Tel: +972 - 4639 - 1708
Fax: +972 - 4639 - 0002
[email protected]
[email protected]
Web: www.GiDEL.com
[email protected]
Contents
Introduction.............................................................................7
PROC2S Key Features............................................................8
PROC2S Standard Models......................................................9
PROC2S Architecture ...........................................................10
PROC2S Block Diagram...........................................................10
PROC2S Connectivity...............................................................11
PROC2S Clocking System .......................................................13
PROC2S Connectors ............................................................14
Overview .................................................................................. 14
Left and Right Connectors ....................................................... 17
Top and Bottom Connectors .................................................... 19
Panel Connector ...................................................................... 21
PROC2S IO Connection Schematics ...................................... 22
PROC2S Memory ..................................................................26
M512 RAM Blocks - 576-bit Memories .....................................26
M4K RAM Blocks - 4,608-bit Memories....................................26
MegaRAM Blocks – 72KB Memories........................................26
32MB On-Board DDRII Memory Block .....................................27
PROC2S LEDs .......................................................................28
Power LEDs ..............................................................................28
User's LEDs ..............................................................................28
PROC2S Electrical and Mechanical Specifications ............31
PROC2S Mechanical Description .............................................31
Environment ..............................................................................32
Power Consumption..................................................................33
Power Supply Sources............................................................. 33
PROC2S Power Consumption................................................. 33
Fan Power Supply.................................................................... 33
Loading PROC2S (Configuring the Stratix II FPGA) ...........34
PROC2S Installation .............................................................36
Requirements............................................................................36
Installing the Board ...................................................................36
GiDEL PROCDeveloper's Kit ................................................37
GiDEL PROCMultiPort ............................................................37
GiDEL PROCProto and PROCLA ...........................................37
Appendix ...............................................................................38
PROC2S Board Devices...........................................................38
Devices You May Need ............................................................38
Board Revision History .............................................................39
PCB History.............................................................................. 39
Assembly - Functional ECO History ........................................ 39
PROC2S Data Book History .................................................... 39
Figures
Figure 1: PROC2S Block Diagram ................................................. 10
Figure 2: PROC2S Clocking System ............................................. 13
Figure 3: PROC2S Connectors ...................................................... 14
Figure 4: I/O Connections to Stratix II........................................... 23
Figure 5: Top & Bottom Connections to Stratix II........................ 24
Figure 6: Panel Connections to Stratix II ...................................... 25
Figure 7: Mechanical Description - CS ......................................... 31
Figure 8: Mechanical Description - PS.......................................... 32
Figure 9: PROC2S Jumpers' Schematic Description .................. 34
Figure 10: Jumper Positions' Definition ....................................... 34
Tables
Table 1: GiDEL PROC2S Standard Models...................................... 9
Table 2: PROC Board Connectors' Pin Composition ................... 18
Table 3: User Connectors' Pin Composition ................................. 20
Table 4: Panel Connector's Pin Composition ............................... 21
Introduction
PROC2S™ provides a high-capacity, high-speed, dynamically reconfigurable FPGA
platform in the industry’s smallest foot print.
PROC2S may be used as a high-performance stand-alone board, as a PROC
daughterboard, as reconfigurable user's daughterboard or as an emulation tool for ASIC
developers.
In the latter case, the ASIC is built in two stages:
At the first stage, the user builds the board with the ASIC/SoC device layout, but
without the ASIC itself. Instead, four small connectors are added around the device
placement and PROC2S is connected to the board via these connectors. Now the user
may run the application using this final board, with the PROC2S mated to the board and
containing the ASIC/SoC logic. System development may continue in parallel. PROC2S
may be reloaded at any moment with a new, improved design and tested immediately.
At the second stage, the user decides that the design meets his/her requirements. At
this stage, the PROC2S board is simply removed and replaced with the final device.
This method allows rapid development of a reliable design. When used as an emulation
tool, PROC2S may significantly save developer's prototyping effort and improve system
reliability as the design may be tested at any development stage.
The third revision of PROC2S features several important improvements to the original
board, such as temperature control. The number of jumpers has been reduced to
simplify the board usage. External push button was added.
PROC2S rev.3 is fully backward compatible with PROC2S rev.2. This means that a
design that was developed for PROC2S rev.2 may be used on the rev.3 board without
changes
7
PROC2S Key Features
ALTERA® Stratix® II 60 - 180 FPGA
Flexible usage:
As user's daughter card
As a stand-alone board
As PROC daughter board
Largest FPGA - smallest board footprint
Up to 314 I/Os (254 I/Os on 4 daughter card connectors + 60 I/Os on SCSI connector)
Flexible clocking system (up to 420MHz-performance):
2 dedicated clock inputs (with feedbacks) from motherboard
2 global clock inputs and 1 global clock output from motherboard
1 dedicated clock input and 1 dedicated clock output via SCSI connector
Up to 12 PLLs in the on-board Stratix II device
Up to 96 DSP blocks in the on-board Stratix II device, implementing full-precision fast
Multipliers-Accumulators (MACs) (each block can implement either eight 9*9-bit MACs, or
four 18*18-bit MACs, or one 36*36-bit MAC)
Reconfiguration options:
From the motherboard (via the daughterboard connectors), when in DB mode
By ALTERA® ByteBlaster (JTAG chain)
From the on-board EPC16 EEPROM device (on power-up)
Four-level memory structure:
Up to 930 M512 RAM blocks ( 32x18 … 512x1 bits)
Up to 768 M4K RAM blocks (128x36 … 4Kx1 bits)
Up to 9 MegaRAM blocks (4Kx144 … 64Kx9 bits)
32 MB DDR II 16-bits wide memory with innovative controller
Innovative DDR II memory controller with 2..16 ports, enabling independent simultaneous
access to each port. Block sustain access of up to 1GB/s.
8
PROC2S Standard Models
The model names have the following structure: PROC2S XX-Y, where XX is the type of the
Stratix II device and Y is its speed grade.
The following models are currently available:
Ordering code
(Basic models)
FPGA Devices
Speed
grade
# of
FPGAs
On-Board
DDR II
FPGA
internal
RAM
User I/O
pins
# of LEs
PROC2S60
Stratix II 60
5
1
32MB
~2.5 Mb
314
~60,000
PROC2S60-A
Stratix II 60
3
1
32MB
~2.5 Mb
314
~60,000
PROC2S60-B
Stratix II 60
4
1
32MB
~2.5 Mb
314
~60,000
PROC2S130-A
Stratix II 130
3
1
32MB
~6.7Mb
314
~130,000
PROC2S180
Stratix II 180
5
1
32MB
~9.3Mb
314
~180,000
PROC2S180-B
Stratix II 180
4
1
32MB
~9.3Mb
314
~180,000
Table 1: GiDEL PROC2S Standard Models
9
PROC2S Architecture
PROC2S Block Diagram
TOP
CONNECTOR
56
62
STRATIX II
60/130/180
JTAG
58
POWER
70
BOTTOM
CONNECTOR
16
DDR II
32 MBytes
Figure 1: PROC2S Block Diagram
10
RIGHT
CONNECTOR
LEFT
CONNECTOR
70
PANEL
CONNECTOR
PROC2S Architecture
PROC2S Connectivity
1. The buses on PROC2S boards were designed to provide maximum flexibility. However,
user must take care to avoid bus contention (always use one source at a time for the
same signal).
2. It is recommended to drive all unused connectivity pins to "0" (from one source) to
improve EMC characteristics.
Left bus ( l[53..0] ) This I/O bus connects the on-board FPGA device to the left connectors
both on the component side and on the print side. When PROC2S is used as a
PROC daughterboard, these signals are connected to the corresponding pins of the l
bus on the PROC motherboard. On PROC2S, this bus has 54 bi-directional signals
available to the user. See the Left and Right connectors section for more information.
Fast Left bus ( lfast[2..1] ) Similarly to the Left bus, this I/O bus connects the on-board
FPGA device to the left connectors both on the component side and on the print side.
When PROC2S is used as a PROC daughterboard, these signals are connected to
the corresponding pins of the lfast bus on the PROC motherboard. On PROC2S, this
bus has 2 bi-directional signals available to the user. These signals enter the onboard Stratix II global lines and therefore may be used as clock inputs or as generalpurpose I/Os. These signals are connected to Stratix II FPGA as follows:
lfast1 is connected to CLK10p pin
lfast2 is connected to CLK8p pin
See the Left and Right connectors section for more information.
Right bus ( r[79..54] ) This I/O bus connects the on-board FPGA device to the right
connectors both on the component side and on the print side. When PROC2S is used
as a PROC daughterboard, these signals are connected to the corresponding pins of
the r bus on the PROC motherboard. On PROC2S, this bus has 26 bi-directional
signals available to the user. See the Left and Right connectors section for more
information.
Fast Right bus ( rfast[2..1] ) Similarly to the Right bus, his I/O bus connects the on-board
FPGA device to the right connectors both on the component side and on the print
side. When PROC2S is used as a PROC daughterboard, these signals are
connected to the corresponding pins of the rfast bus on the PROC motherboard. On
PROC2S, this bus has 2 bi-directional signals available to the user. These signals
enter the on-board Stratix II global lines and therefore may be used as clock inputs or
as general-purpose I/Os. These signals are connected to Stratix II FPGA as follows:
rfast1 is connected to CLK0p pin
rfast2 is connected to CLK2p pin
See the Left and Right connectors section for more information.
11
PROC2S Architecture
Main bus ( main[29..0] ) This I/O bus connects the on-board FPGA device to the right
connectors both on the component side and on the print side. When PROC2S is used
as a PROC daughterboard, these signals are connected to a part of the main bus on
the PROC motherboard, according to the PROC2S placement. On PROC2S, this bus
has 30 bi-directional signals available to the user. See the Left and Right connectors
section for more information.
Top bus ( t[69..0] ) This I/O bus connects the on-board FPGA device to the top connector
on the print side. This bus has 70 bi-directional signals available to the user. See the
Top and Bottom connectors section for more information.
Bottom bus ( b[69..0] ) This I/O bus connects the on-board FPGA device to the bottom
connector on the print side. This bus has 70 bi-directional signals available to the
user. See the Top and Bottom connectors section for more information.
Panel bus ( p[59..0] ) This I/O bus connects the on-board FPGA device to the panel
connector (the SCSI connector). This bus has 60 bi-directional signals available to
the user. See the Panel connector section for more information.
12
PROC2S Architecture
PROC2S Clocking System
GiDEL PROC2S boards have a flexible clocking system. In the standard models, a 50MHz,
50ppm oscillator is mounted on the board. A different oscillator may be mounted on special
requests to produce alternative precise clock frequencies.
The clocks in PROC2S boards are routed according to following scheme:
Osc
osc_clk(1)
clk(2)
p_clk_out(8)
clk2(3)
Stratix II
clk_in[2..1](4)
p_clk_in(7)
clk3(5)
ck(6)
DDR II
Memory
Figure 2: PROC2S Clocking System
(1)
Clock input from the on-board oscillator
(2)
Main global clock input from a PROC motherboard or from the user's system
(3)
Secondary global clock input from a PROC motherboard or from the user's system
(4)
Dedicated clock inputs from internal FPGA PLL on the PROC motherboard or from the user's system
(5)
Clock output to internal FPGA PLL on the PROC motherboard or to the user's system
(6)
Clock output to the on-board DDR II memory
(7)
Clock input from the SCSI connector
(8)
Clock output to the SCSI connector
13
PROC2S Connectors
Overview
The Stratix II device on the PROC2S board is connected to a number of connectors. The
following picture schematically describes these connections.
Figure 3: PROC2S Connectors
14
PROC2S Connectors
As explained in the PROC2S Connectivity section, the PROC2S board has several buses
that connect the on-board Stratix II device to connectors on the component side and on the
print side. These connectors function as follows:
CS left & right connectors, J8 & J9, are located on the component side of PROC2S.
J8 is located on the left side of the Stratix II device and J9 is located on its right side.
These connectors are connected to the l, r and main buses of the Stratix II FPGA.
For more details on the signals connected to these connectors, see the Left and Right
Connectors paragraph in this section.
CS left & right connectors may be used to connect the on-board Stratix II device to
PROCProto / PROCLA daughterboards or for user’s connections. Being connected
pin-to-pin to J1 and J3 respectively, J8 & J9 connect both PROC2S and its
daughterboard to the PROC motherboard.
PS left & right connectors, J1 & J3, are located on the print side of PROC2S.
J1 is located on the left side of the Stratix II device and J3 is located on its right side.
Similarly to the CS left & right connectors, these connectors are connected to the l, r
and main buses of the Stratix II FPGA. For more details on the signals connected to
these connectors, see the Left and Right Connectors paragraph in this section.
J1 & J3 may be used to connect the on-board Stratix II device to GiDEL PROCStar
motherboard. Alternatively, PS left & right connectors may be used to connect
PROC2S to user's daughterboard. In the latter case, the daughterboard may be
connected using up to 4 connectors (J1-J4).
Being connected pin-to-pin to J8 and J9 respectively, PS left & right connectors
enable connecting the user’s daughterboard directly to the PROCStar motherboard.
PS top & bottom connectors, J4 & J2, are located on the print side of PROC2S.
J4 is located above the Stratix II device and J2 is located below it.
These connectors are connected to the t and b buses of the Stratix II FPGA. For
more details on the signals connected to these connectors, see the Top and Bottom
Connectors paragraph in this section.
Together with PS left & right connectors, these connectors may be used to connect
the on-board Stratix II device to the user’s daughter board. The daughterboard is then
attached to the print side of PROC2S and may be connected using up to 4
connectors (J1-J4).
The SCSI connector, J5, is an additional connector located on the print side of
PROC2S. This right-angle connector is used to connect the on-board Stratix II device
to other devices or daughter boards via a SCSI cable. J5 is connected to the p bus of
the on-board Stratix II device. For more details on the signals connected to this
connector, see the Panel Connector paragraph in this section.
Notes
1. All the pins of J1-J5 and J9 are LVTTL 3.3V standard.
2. JP6 sets the Top IO Connector (J4) voltages to 3.3V or 1.8V.
15
PROC2S Connectors
Several additional connectors are located on PROC2S component side. These connectors
are designed to provide the following functions:
J7 is used to supply power to PROC2S in a stand-alone mode (3.3V and GND).
J11 is used to supply power to the cooling fan (5V and GND).
J6 is used for Signal Tap (JTAG) connection and for Stratix II device configuration
while in the Stand Alone mode (for more information, please refer to the Loading
PROC2S section).
J10 is used to load designs into the on-board EPCS64 device (using ByteBlaster).
This EEPROM device will, in turn, configure the on-board Stratix II device on powerup in the Stand-Alone mode (for more information, please refer to the Loading
PROC2S section).
16
PROC2S Connectors
Left and Right Connectors
These connectors are connected to the following buses:
l [53..0] – connected to J1/J8 connectors.
lfast [2..1] – connected to J1/J8 connectors.
r [79..54] – connected to J3/J9 connectors.
rfast [2..1] – connected to J3/J9 connectors.
main [29..0] – connected to J3/J9 connectors.
Additional miscellaneous signals
These connectors are 3.3V LVTTL.
The following table gives the detailed information regarding these connectors.
Pin #
1
J1 (PS) & J8 (CS)
NC
(5)
clk_in2
(5)
2
NC
3
GND
4
l0
5
3.3Vdc
6
l1
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DATA
l2
l3
l4
l5
l6
l7
l8
l9
l10
l11
l12
l13
l14
l15
l16
l17
l18
l19
l20
l21
l22
l23
l24
l25
l26
33
GND
J3 (PS) & J9 (CS)
(3)
main0
(1)
clk_fb2
main1
(1) (4)
r54
main2
(2) (4)
r55
main3
r56
main4
r57
main5
r58
main6
r59
main7
r60
main8
r61
main9
r62
main10
r63
main11
r64
main12
r65
main13
r66
main14
r67
main15
(1)
rfast1
17
(6)
PROC2S Connectors
Pin #
J1 (PS) & J8 (CS)
J3 (PS) & J9 (CS)
34
lfast1
main16
35
GND
NC
36
TRST_ALL
37
(2) (4)
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
l50
63
CONFIG_DONE
64
l51
rfast2
main18
r68
main19
r69
main20
r70
main21
r71
main22
r72
main23
r73
main24
r74
main25
r75
main26
r76
main27
r77
main28
r78
main29
r79
NC
(2) (4)
(5)
clk_in1
3.3Vdc
65
DCLK
66
l52
(2) (4)
clk_fb1
NC
67
GND
68
l53
69
NC
clk
70
main17
(2) (4)
nCONFIG
lfast2
l27
l28
l29
l30
l31
l32
l33
l34
l35
l36
l37
l38
l39
l40
l41
l42
l43
l44
l45
l46
l47
l48
l49
(5)
(1)
(3)
(1)
(6)
(5)
GND
clk3
(5)
GND
clk2
Table 2: PROC Board Connectors' Pin Composition
(1) Power pins.
(2) Passive serial FPGA configuration from daughterboard / PROC motherboard
Notes
(3) PLL input from motherboard / feedback pins
(4) Not connected on J8
(5) NC stands for Not Connected (on both connectors)
(6) PROC board PLL feedback pins. Not connected on PROC2S. May be used on daughter boards.
18
PROC2S Connectors
Top and Bottom Connectors
These connectors are connected to the following buses:
t [69..0] – connected to J4 connector.
b [69..0] – connected to J2 connector.
The following table gives the detailed information regarding these connectors.
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
J4 (PS)
J2 (PS)
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
b33
b34
b35
b36
b37
b38
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
t38
19
PROC2S Connectors
Pin #
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
J4 (PS)
J2 (PS)
b39
b40
b41
b42
b43
b44
b45
b46
b47
b48
b49
b50
b51
b52
b53
b54
b55
b56
b57
b58
b59
b60
b61
b62
b63
b64
b65
b66
b67
b68
b69
t39
t40
t41
t42
t43
t44
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
t58
t59
t60
t61
t62
t63
t64
t65
t66
t67
t68
t69
Table 3: User Connectors' Pin Composition
1. All J2 and J4 pins are LVTTL I/O standard and connected to the Stratix II device.
Notes
2. JP6 sets the Top IO Connector (J4) voltages to 3.3V or 1.8V.
20
PROC2S Connectors
Panel Connector
This connector is connected to the p [69..0] bus. All the I/Os on this connector are 3.3V
LVTTL. The following table gives the detailed information regarding this connector.
Pin #
J5 (PS)
Pin #
(3)
J5 (PS)
1
NC
2
p_clk_in
3
p_clk_out
37
GND
GND
GND
4
p2
38
p3
5
GND
39
p0
6
p1
40
GND
7
p4
41
p5
8
p6
42
p7
9
p8
43
p9
10
p10
44
p11
11
p12
45
p13
12
p14
46
p15
13
p16
47
p17
14
p18
48
p19
15
p20
49
p21
16
p22
50
p23
17
p24
51
p25
18
p26
52
p27
19
p28
53
p29
20
p30
54
p31
21
p32
55
p33
22
p34
56
p35
23
p36
57
p37
24
p38
58
p39
25
p40
59
p41
26
p42
60
p43
27
p44
61
p45
28
p46
62
p47
29
p48
63
p49
30
p50
64
p51
31
p52
65
p53
32
p54
66
p55
33
p56
67
p57
34
p58
68
p59
35
(1)
36
(2)
Table 4: Panel Connector's Pin Composition
Notes
(1) Input clock from the Panel connector
(2) Output clock to the Panel connector
(3) NC stands for Not Connected
21
PROC2S Connectors
PROC2S IO Connection Schematics
The following figures describe the I/O connections on PROC2S board
22
PROC2S Connectors
Figure 4: I/O Connections to Stratix II
23
PROC2S Connectors
Figure 5: Top & Bottom Connections to Stratix II
24
PROC2S Connectors
Figure 6: Panel Connections to Stratix II
25
PROC2S Memory
GiDEL PROC2S board memory has a four-level structure:
M512 RAM Blocks - 576-bit Memories
The on-board Stratix II device includes up to 930 M512 RAM blocks. The M512
RAM blocks are true dual-port memory blocks. Each block may be configured and
accessed independently. Possible configurations are: 32*18, 32*16, 64*9, 64*8,
128*4, 256*2 and 512*1. These blocks may be used as small FIFOs, binary LUTs
(91), register files and for other small storages.
M4K RAM Blocks - 4,608-bit Memories
The on-board Stratix II device includes up to 768 M4K RAM blocks. The M4K RAM
blocks are true dual-port memory blocks. Each block may be configured and
accessed independently. Possible configurations are: 128*36, 128*32, 256*18,
256*16, 512*9, 512*8, 1024*4, 2048*2 and 4096*1. These RAM blocks may be
used for line delays in 2D processing, as 8-bit and 10-bit LUTs, as small NIOS
memory block, as mid-range FIFOs etc.
MegaRAM Blocks – 72KB Memories
The on-board Stratix II device includes up to 9 MegaRAM blocks. The MegaRAM
blocks are true dual-port memories. These RAM block provide dedicated true dualport or single-port memory, 8 to 144-bits wide. These RAM blocks may be used as
mid-range LUTs (168), as process data storage, NIOS program / data memory,
large FIFOs, and wide Random access memories etc.
26
PROC2S Memory
32MB On-Board DDRII Memory Block
PROC2S boards have one DDR II block, 16-bits wide, attached to the Stratix II device. This
DDR II block may be controlled by the GiDEL innovative controller (PROCMultiPort™) or
by the user’s controller.
The DDR II block, combined with GiDEL PROCMultiPort controller, may open the way for
new architectures. With PROCMultiPort, one DDR block may replace several external
memory blocks, while providing high throughput. Among the applications that might use this
memory are: huge FIFOs, on-board data processing, 3D applications, huge delay lines,
virtual enlargement of Stratix II memory, simulator memory, diagnostic buffers and more.
These memories allow acquisition systems, display systems etc. to maintain constant
operation controlled by software without the need for the software to respond in real-time.
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PROC2S LEDs
Power LEDs
A 3.3V power LED is located on the upper side of PROC2S boards. An illuminated power
LED indicates that the board is receiving power.
User's LEDs
PROC2S boards have three user LEDs connected to Stratix II device. The FPGA is
connected directly to these LEDs. User's hardware application may operate these LEDs
using the led [3..1] bus.
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PROC2S Thermal Sensing
PROC2S boards use the MAX1619 thermal sensing device from MAXIM for Stratix II
temperature monitoring. Both address pins (ADD0 and ADD1) of MAX1619 are connected
to GND, so that the device address is set to 0011000.
Three signals are connected to MAX1619 to enable temperature sensing. These signals
appear in the top-level design as follows:
SMBDATA: I2C data signal
SMBCLK: I2C clock signal
ALERT: MAX1619 alert signal
For more information on the above signals, please refer to the MAX1619 Data Book.
Notes
1. Users may use GiDEL’s IP Core that monitors the device temperature. Please, contact GiDEL for
more information on the Thermal Monitor IP Core.
2. Users may alternatively build their own component for temperature monitoring
User must constantly monitor the Stratix II temperature in order to prevent device
overheating. Stratix II devices may be physically destroyed if overheated. The board
warranty is voided in case of thermal damage to the device.
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PROC2S Push Button
An additional switch S1 is assembled on PROC2S rev.3 boards. This switch enables the
user to add functionality to the board, such as external reset or mode switch button.
The push button is connected to the RST_Button signal in PROC2S top-level design.
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PROC2S Electrical and
Mechanical Specifications
PROC2S Mechanical Description
Figure 7: Mechanical Description - CS
31
PROC2S Electrical and Mechanical Specifications
Figure 8: Mechanical Description - PS
Environment
GiDEL PROC2S boards operate at standard conditions as follows:
♦
Temperature: 32 to 131 ° F (0 to 55 °C)
♦
Humidity: 10-90% (non-condensing)
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PROC2S Electrical and Mechanical Specifications
Power Consumption
Power Supply Sources
PROC2S board main voltage (3.3V) is supplied by:
J7 (power connector) for Stand-Alone operation
J1 & J3 for Daughter Board operation (except for fan power supply)
The cooling fan power is supplied from J11 in both modes.
Stratix II Power Consumption
The PROC2S power consumption is dominated by the Stratix II power consumption. The
following table summarizes the power consumption of the PROC2S board.
(1)
An on-board non-isolated DC/DC converter with input connected to the 3.3V source
(2)
Icc1.2int depends on the design that runs on the FPGA. The maximum value for this current is
10A (16A for PROC2S180-B model).
(3)
Icc1.8IO = (FPGA 1.8V I/O current). The maximum value for this current is 3A
(4)
Icc3.3 = (FPGA 3.3V I/O current) + Icc1.8IO*0.6 + Icc1.2int*0.4
Iref is very low and does not influence the overall current consumption
(5)
Fan Power Supply
The PROC2S 130 and PROC2S 180 models are supplied with a cooling fan. The fan
voltage (5V) must be supplied by J11 power connector.
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Loading PROC2S
(Configuring the Stratix II FPGA)
The loading modes of the on-board Stratix II device are set by the position of a single
jumper JP7. The following figure schematically describes the jumper’s functions.
Figure 9: PROC2S Jumpers' Schematic Description
The jumper’s positions are defined as follows:
Position 1
Position 2
Figure 10: Jumper Positions' Definition
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Loading PROC2S
The on-board Stratix II device is configured as follows:
PROC2S as a PROC daughter board. In this mode, the on-board EPCS64 device
will be loaded automatically by the FPGA located on the PROC motherboard. To
select this working mode, set JP7 to position 2. In addition, set the IC number in the
PROCWizard configuration according to the location of the PROC2S daughterboard
on the PROC motherboard. (For PROCStar motherboard, select IC4 when PROC2S
is located on top of FPGA1, IC5 when PROC2S is on top of FPGA2 etc.).
Via JTAG in the Stand Alone mode. In this mode, the SOF file should be loaded
directly into the on-board Stratix II device using ALTERA ByteBlaster. The design is
loaded via the JTAG connector (J6). Note that in this working mode the design will be
erased when the PROC2S board will be disconnected from power. To select this
working mode, set JP7 to position 1.
Using EPCS64 in the Stand Alone mode. In this mode, the (compressed) POF file
should be loaded into the on-board EPCS64 EEPROM device using ALTERA
ByteBlaster. The design is loaded via the EPC connector (J10). In this working mode,
the design will be automatically loaded into the on-board Stratix II device when the
PROC2S board will be powered-up. To select this working mode, set JP7 to
position 1.
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PROC2S Installation
Requirements
The following requirements must be met in order to compile HDL designs for PROC2S
board.
Quartus II must be installed on user's computer
The installed Quartus II version must support Stratix II devices
Note
GiDEL PROCWizard and the ALTERA Quartus II software may run on the same computer or on
different computers.
Installing the Board
Inserting/removing the PROC2S board to/from the PROC motherboard connectors is not
allowed when the power is on. These operations might damage PROC2S board devices or the
PROC motherboard.
Inserting/removing Daughter Boards (such as PROC_LA and PROC_Proto) to/from PROC2S
daughterboard connectors is not allowed when power is on. These operations might damage
PROC2S board devices or daughterboard devices.
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GiDEL PROCDeveloper's Kit
GiDEL PROCMultiPort
PROCMultiPort™ completes the PROC Board features and provides an advanced
controller for the on-board memory. This controller has up to 16 ports; each port features a
simple access (FIFO- like or random). All the ports are connected to the same memory
domain and can be accessed independently and simultaneously, with individual clock
domains and data widths. PROCMultiPort segmented mode provides the ability to logically
enlarge the FPGA memory size.
The innovative PROCMultiPort concept enables new design methodologies. It can replace
many large and complicated designs, thus reducing the development effort. For example, it
can replace swappable double buffers or implement multiple logical memories in the same
physical memory.
GiDEL PROCProto and PROCLA
PROCProto™ and PROCLA™ are PROC2S Daughter Boards that enable rapid system
connection and debugging. PROCProto enables to wire-warp or solder external devices
and connectors to the board. PROCLA can function as a logic analyzer adapter. It connects
PROC2S I/Os directly to Logic Analyzer connectors, which enables easy connection of
Logic Analyzer to PROC2S.
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Appendix
PROC2S Board Devices
The following Altera devices may be installed on GiDEL PROC2S Boards:
♦ EP2S60F1020
♦ EP2S130F1020
♦ EP2S180F1020
The following Micron memory devices are installed on GiDEL PROC2S Boards:
♦ MT47H16M16FG-37E
The following Maxim devices are installed on GiDEL PROC2S Boards:
♦ MAX1619MEE
We recommended reviewing the relevant data sheets available from Altera, Micron and
Maxim.
Devices You May Need
♦ Fuse (10A) : FB 10A- 20NL-100L HL 20NL.
♦ Connector sockets for user daughter board:
TFM-135-XX-S-D-LC(Samtec), where XX specifies the connector height as follows:
XX
Height
– 02
(6,35) .250
– 12
(8,13) .320
– 22
(9,91) .390
– 32
(11,81) .465
♦ Standard SCSI connector for flat cable or for a PCB to use with J5.
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Appendix
Board Revision History
PCB History
Revision
Changes
Rev: 01
Initial board
Rev: 02
Support for Stratix II 130 and 180 devices
Rev: 03
Added: Temperature Control, Push Button, Mounting Holes for
the Fan
Reduced the number of jumpers that define the working mode
Assembly - Functional ECO History
Revision
ECO #
01
01
02
02
03
03
Changes
PROC2S Data Book History
Date
Changes
10/2004
Rev.01 Data Book
3/2005
Rev.02 Data Book
8/2005
Rev.03 Preliminary Data Book
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