Sitsang / PXA255 Evaluation Platform User`s Guide

Transcription

Sitsang / PXA255
Evaluation Platform
User’s Guide
September 2003
History
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale
and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved”or “undefined.”Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Sitsang / PXA255 Evaluation Platform may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
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logo, Intel Inside, Intel Inside logo, Intel SpeedStep, Intel StrataFlash, Intel XScale, are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Sitsang / PXA255 Evaluation Platform User’
s Guide
ii
Contents
Contents
1
Introduction and Startup.............................................................................................................. 1-1
1.1
Feature ............................................................................................................................... 1-1
1.2
System overview ............................................................................................................... 1-2
1.3
Getting Started................................................................................................................... 1-2
1.4
Related Documents............................................................................................................ 1-3
2
Hardware Description ................................................................................................................. 2-1
2.1
Sitsang / PXA255 Evaluation Board Layout ..................................................................... 2-1
2.2
Sitsang / PXA255 Evaluation Board Hardware Description ............................................. 2-5
2.2.1
Power supply ................................................................................................................ 2-5
2.2.2
Reset ............................................................................................................................. 2-5
2.2.3
FLASH Memory and Boot ROM ................................................................................. 2-5
2.2.4
SDRAM ........................................................................................................................ 2-6
2.2.5
Board Level Registers (BLRs) and Interrupt Controller............................................... 2-6
2.2.6
LCD display and Interface ............................................................................................ 2-6
2.2.7
Bus Driver and Transceiver .......................................................................................... 2-7
2.2.8
Compact Flash Card...................................................................................................... 2-7
2.2.9
Universal Serial Bus (USB) Host Controller ................................................................ 2-8
2.2.10
Audio CODECs ..................................................................................................... 2-10
2.2.11
Touch Screen Controller ........................................................................................ 2-10
2.2.12
USB Client Port ..................................................................................................... 2-11
2.2.13
IrDA Infrared Transceiver...................................................................................... 2-11
2.2.14
Serial Communication ports................................................................................... 2-12
2.2.15
Multimedia / Secure Digital Memory Card............................................................ 2-13
2.2.16
Accelerometer Sensor ............................................................................................ 2-14
2.2.17
Ethernet Controller................................................................................................. 2-14
2.2.18
Expansion Card Slot............................................................................................... 2-15
2.2.19
JTAG Chain ........................................................................................................... 2-16
2.2.20
User Switches and Buttons..................................................................................... 2-16
2.2.21
LED Indicators....................................................................................................... 2-17
2.2.22
Connectors ............................................................................................................. 2-17
2.2.23
Jumpers .................................................................................................................. 2-20
2.2.24
Power system ......................................................................................................... 2-20
2.2.24.1 VCC Core.......................................................................................................... 2-21
2.2.25
JTAG Cable ........................................................................................................... 2-22
3
Programming Guide .................................................................................................................... 3-1
3.1
Memory Map and Chip selects .......................................................................................... 3-1
3.2
Board Lever Registers (BLRs) .......................................................................................... 3-1
3.2.1
Power Control Register (PCR)...................................................................................... 3-2
3.2.2
Board Control Register (BCR)...................................................................................... 3-3
3.2.3
Board Status Register (BSR) ........................................................................................ 3-4
3.2.4
Board Interrupt Pending Register (BIPR)..................................................................... 3-5
3.2.5
Board Interrupt Mask Register (BIMR)........................................................................ 3-7
3.2.6
Accelerometer x direction logic high counter register (AXHR) and Accelerometer y
direction logic high counter register (AYHR)............................................................................. 3-7
3.2.7
HEX switch, Joystick switch and soft button status register (JSSR) ............................ 3-7
3.2.8
Low 16-bits LED matrix control register (LLEDR) and High 16-bits LED matrix
control register (HLEDR) ........................................................................................................... 3-8
3.2.9
Expansion card board control register (EX_BCR)........................................................ 3-9
3.2.10
Expansion card board status register (EX_BSR) ..................................................... 3-9
3.2.11
Expansion card interrupt pending register (EX_BIPR) and Expansion card interrupt
mask register (EX_BIMR) .......................................................................................................... 3-9
3.3
General Purpose Input/Output (GPIO) ............................................................................ 3-10
3.4
Programming Flash Memory........................................................................................... 3-12
3.4.1
Obtaining Required Software and Files ...................................................................... 3-12
3.4.2
Install JFlash ............................................................................................................... 3-12
3.4.2.1
Install JFlash for Windows* 98......................................................................... 3-12
s Guide
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Contents
3.4.2.2
Installing JFlash for Windows* NT, Windows* 2000, Windows* XP ............. 3-12
3.4.3
Connecting the JFlash Cable....................................................................................... 3-13
3.4.4
Using the JFlash Software .......................................................................................... 3-13
3.4.5
Troubleshoot for JFlash .............................................................................................. 3-14
3.5
Programming Complex Logic Device (CPLD) ............................................................... 3-14
3.5.1
Obtaining Required Software and Files ...................................................................... 3-14
3.5.2
Connecting the JFlash Cable....................................................................................... 3-14
3.5.3
Reprogramming CPLD U24 ....................................................................................... 3-14
s Guide
ii
Contents
Figures
Figure 1- 1
Figure 2- 1
Figure 2- 2
Figure 2- 3
Figure 2- 4
Figure 2- 5
Figure 2- 6
Figure 2- 7
Figure 2- 8
Figure 2- 9
Figure 2- 10
Figure 3- 1
Figure 3- 2
Block Diagram, Sitsang / PXA255 Evaluation Platform .............................................. 1-2
Component Layout, Top view....................................................................................... 2-2
Component Layout, Bottom view ................................................................................. 2-3
Sitsang / PXA255 Evaluation Platform Package view.................................................. 2-4
Compact Flash card block diagram............................................................................... 2-7
USB host controller block diagram............................................................................... 2-9
ADXL202JE output signal.......................................................................................... 2-14
Ethernet host controller block diagram ....................................................................... 2-14
JTAG Chain ................................................................................................................ 2-16
Block diagram of the power system on Sitsang .......................................................... 2-21
JTAG cable drawing ................................................................................................. 2-22
Interrupt trigger timing.................................................................................................. 3-6
JFlash Interface ........................................................................................................... 3-13
s Guide
iii
Contents
Tables
Table 1- 1
Table 2- 1
Table 2- 2
Table 2- 3
Table 2- 4
Table 2- 5
Table 2- 6
Table 2- 7
Table 2- 8
Table 2- 9
Table 2- 10
Table 2- 11
Table 2- 12
Table 2- 13
Table 2- 14
Table 2- 15
Table 2- 16
Table 2- 17
Table 2- 18
Table 2- 19
Table 2- 20
Table 2- 21
Table 2- 22
Table 2- 23
Table 3- 1
Table 3- 2
Table 3- 3
Table 3- 4
Table 3- 5
Table 3- 6
Table 3- 7
Table 3- 8
Table 3- 9
Table 3- 10
Table 3- 11
Table 3- 12
Table 3- 13
Table 3- 14
Table 3- 15
Table 3- 16
Table 3- 17
Supplemental Documentation ........................................................................................ 1-3
LCD color pin mapping.................................................................................................. 2-6
BLRs for LCD................................................................................................................ 2-6
BLRs for CF card ........................................................................................................... 2-8
BLRs for USB Host........................................................................................................ 2-9
BLRs for Audio CODECs ............................................................................................ 2-10
BLRs for Touch Screen................................................................................................ 2-10
BLRs for USB Client ................................................................................................... 2-11
BLRs for IrDA ............................................................................................................. 2-12
BLRs for FF UART and BT UART ............................................................................. 2-12
BLRs for SD Card ...................................................................................................... 2-13
BLRs for Ethernet Controller ..................................................................................... 2-15
Signals type in expansion slot .................................................................................... 2-15
BLRs for Expansion card ........................................................................................... 2-16
Switches and buttons on Sitsang board ...................................................................... 2-17
LEDs on Sitsang board............................................................................................... 2-17
Connectors on Sitsang board ...................................................................................... 2-18
J15’s pin mapping ...................................................................................................... 2-18
J17’s pin mapping ...................................................................................................... 2-18
J21’s pin mapping ...................................................................................................... 2-18
J22’s pin mapping ...................................................................................................... 2-20
Jumpers on Sitsang board........................................................................................... 2-20
Power supply on Sitsang board .................................................................................. 2-20
MAX4544M/LEUK I2C address ............................................................................... 2-22
Sitsang / PXA255 Evaluation Platform memory map .................................................... 3-1
BLRs on Sitsang boards ................................................................................................. 3-2
Power control register .................................................................................................... 3-3
Board control register..................................................................................................... 3-4
Board status register ....................................................................................................... 3-5
Board interrupt pending register..................................................................................... 3-6
Board interrupt mask register ......................................................................................... 3-7
Accelerometer x direction logic high counter register.................................................... 3-7
Accelerometer y direction logic high counter register.................................................... 3-7
HEX switch, Joystick switch and soft button status register ........................................ 3-8
Low 16-bits LED matrix control register ..................................................................... 3-8
High 16-bits LED matrix control register..................................................................... 3-9
Expansion card board control register .......................................................................... 3-9
Expansion card board status register ............................................................................ 3-9
Expansion card interrupt pending register.................................................................. 3-10
Expansion card interrupt mask register ...................................................................... 3-10
PX250 GPIO Map ...................................................................................................... 3-12
s Guide
iv
Introduction and Startup
1
The Intel® XScale™ Microarchitecture is an industry leader in mW/MIPs, designed for high
performance and low power. The Sitsang / PXA255 Evaluation Platform provides a development
system for the following Intel XScale application-specific processor:
• The PXA255 application processor features a 32-bit data bus, operation up to 400 MHz, and a
17 x 17 mm mBGA package.
This processor is intended for applications requiring high performance, low power, and a high degree
of integration, such as personal digital assistants, communicators, smart phones, and wireless PC
companions. The Sitsang / PXA255 Evaluation Platform provides access to all of the PXA255 native
input/output (I/O) functions. The platform package consists of:
• The Sitsang / PXA255 Evaluation Platform which contains a variety of peripheral devices to
aid in application software development
• An 3.7 VDC, 1500mAh LI-ION type battery
• An AC-to-DC power supply:
§ Input: 90 - 264 VAC, 50-60 Hz
§ Output: -6 VDC, 900 mA
• A LCD panel with built-in touch screen and backlight
• A 10M bps Ethernet Compact Flash card (Optional)
• A normal network cable
• A cross type network cable
• A JTAG/FF UART cable
• A 9-pin COM port cable
• A Normal-USB –A to Min-USB-B cable. It is used to connect Sitsang board to PC
• Two Min-USB-A to Normal-USB-A cable (Optional). They are used to connect Sitsang board
with other USB devices.
This chapter contains:
Section 1.1 —
Section 1.2 —
Section 1.3 —
Section 1.4 —
Features
System Overview
Getting Started
Related Documents
Chapter 2, “Hardware Description”and Chapter 3, “Programming Guide”provide detailed instructions
for using the Sitsang / PXA255 Evaluation Platform.
1.1
Feature
The Sitsang / PXA255 Evaluation Platform offers many features to facilitate the development of
applications:
• 64 Mbytes SDRAM
• 32 Mbytes boot ROM
• 32 Mbytes flash memory
• One CompactFlash slot
• Touch-screen panel controller
• Audio CODEC with MIC, LINEIN and HEADPHONE connectors
• Toshiba LTM04C380K panel
• Universal LCD connector which support other LCD types
• One USB client port
• USB host controller. Two USB host ports
• I2C bus communications
• Standard-Micro-Systems LAN91C96* Ethernet controller
• Pulse width modulation control
• One infrared (IrDA) transceiver
• Full function and Bluetooth UART serial ports
s Guide
1-1
•
•
•
•
•
•
•
1.2
One slot for Secure Digital memory card or Multimedia Card
One expansion-card slot for customer development
Isolatable processor core voltage for precise power measurements
32 discrete LEDs, one hexadecimal-encoding switch for use by application software
One 5-way Mini-Joystick and two soft buttons for application software
Power switch buttons and GPIO reset buttons
Accelerometer sensor for use by application software
System overview
Figure 1- 1 depicts the organization and data flow of the Sitsang / PXA255 Evaluation Platform.
All communications between the processor and the Sitsang I/O device take place through dedicated or
general-purpose PXA255 I/O pins. The general-purpose pins used in the Sitsang / PXA255 Evaluation
Platform are listed in Section 3.3, “General Purpose Input/Output (GPIO)”. For complete descriptions
of these signals, refer to the Intel® PXA255 and PXA210 Application Processors Developer’s
Manual.
FF
UART
IrDA
MMC/SD
Card
BT
UART
SPI to Touch
Screen
Touch
Screen
USB Client
LCD
Toshiba
LTM04C380
K
PXA255
Application processor
AC97 Codec
CS4201
Compact
Flash
USB Host
controller
SDRAM
Driver and
Transceiver
Audio Jack
Power
System
Figure 1- 1
1.3
Flash
Memory
Ethernet
Controller
Boot ROM
Expansioncard slot
CPLD & Board
level Registers
Debug Leds
HEX-encoding
switches
Accelerometer
sensor
Block Diagram, Sitsang / PXA255 Evaluation Platform
Getting Started
The Sitsang / PXA255 Evaluation Platform Hardware Release Note, packed in the kit, contains
contents of Sitsang / PXA255 Evaluation Platform Kit and Revision History information of Sitsang /
PXA255 Evaluation Platform The hardware release note also contains updates that became available
after the publication of this user’s guide.
When the platform has been set up and started without errors, it is ready for use as an applications
development system. Detailed operating instructions can be found in:
s Guide
1-2
•
•
•
1.4
Chapter 2, “Hardware Description”
Chapter 3, “Programming Guide”
The Intel® PXA255 and PXA210 Application Processors Developer’s Manual
Related Documents
Effective use of the Sitsang / PXA255 Evaluation Platform frequently requires reference to the
manufacturer’s data sheet for a specific device. It is beyond the scope of this document to repeat this
large body of detailed information.
Table 1- 1
Supplemental Documentation lists the data items that might be required.
Item
Sitsang-PXA255 Evaluation Platform Hardware Release Note
Sitsang-PXA255 Evaluation Platform Linux User Guide
Sitsang-PXA255 Evaluation Platform Part List
Sitsang-PXA255 Evaluation Platform Test Suite Users Guide
Sitsang-PXA255 Evaluation Platform Defect List
Sitsang-PXA255 Evaluation Platform Engineering Change Order
Intel® PXA255 and PXA210 Application Processors Developer’s Manual
Intel® XScale (TM) Microarchitecture for the PXA255 and PXA210
Intel® PXA255 and PXA210 Applications Processors Electrical, Mechanical, and Thermal
Specification
Intel® PXA255 and PXA210 Applications Processors Specification Update
Intel® PXA255 and PXA210 Applications Processors Design Guide
Intel® PXA255 and PXA210 Applications Processors Power Supply Design Application Note
Table 1- 1
Supplemental Documentation
s Guide
1-3
Hardware Description
2
This chapter describes the Sitsang / PXA255 Evaluation platform hardware.
Using this platform effectively requires a sound knowledge of the Intel® XScale™ application
processor. Always refer to the Intel® PXA255 and PXA210 Application Processors Developer’s
Manual for items related to the processor.
The Sitsang / PXA255 Evaluation platform contains several peripheral devices in order to facilitate the
development of many different types of applications. The instructions in this chapter and in Chapter 3,
“Programming Guide”, provide enough details to start operating with a minimum of bother. In most
cases, however, the optimal use of a device requires detailed reference to the device manufacturer’s
data sheet. To locate this information, refer to Table 1- 1 Supplemental Documentation
2.1
Sitsang / PXA255 Evaluation Board Layout
The following sections describe the Sitsang / PXA255 Evaluation Platform hardware.
Figure 2- 1
Component Layout, Top view shows the top view of the board and the locations of
major components.
Figure 2- 2
Component Layout, Bottom view shows the bottom view of the board and the
locations of major components.
Figure 2- 3
Sitsang / PXA255 Evaluation Platform Package view shows the package view of the
board.
s Guide
2-1
Figure 2- 1
Component Layout, Top view
s Guide
2-2
Figure 2- 2
Component Layout, Bottom view
s Guide
2-3
Figure 2- 3
Sitsang / PXA255 Evaluation Platform Package view
s Guide
2-4
2.2
Sitsang / PXA255 Evaluation Board Hardware
Description
2.2.1 Power supply
The Sitsang / PXA255 Evaluation Board derives its power from a 3.7 VDC (Nominal Voltage), 1500
mAh LI-ION battery. The board can only be turned on with the battery inserted. Button S1 turns power
of the board on and off. Red LED D11 (-6V) indicates power on.
Two devices can charge the battery:
• An external 90~264 VAC to -6 VDC adapter: The –6 VDC output is limited to 900 mA by the
adapter. There is no current limiter on the board. The -6 VDC input has no protective fuse.
• The USB client port from host: Normally, it can drive 500 mA at 5 VDC. However, it is not
recommend using the USB as the charger. Because the charge current may be larger
than the current limit specified in USB spec (500mA).
Both chargers can be used at the same time. The red LED D8 indicates whether the battery is being
charged. Neither power adapter nor USB client cable can drive the board without battery.
A capacitor C23 sets the total charge time. After a time-out has occurred, the charging will be
terminated immediately. To restart the charge cycle, remove and reinsert the power supply. After the
charging stops, if the battery voltage drops below 3.8VDC, due to external loading or internal leakage,
a charge cycle will automatically resume, and the timer will be reset. Currently, the timeout value is set
to 3 hours. If user wants to change this value, change C23 value by below equation:
Timeout value (Hours) = C23/0.1u × 3 hours
Software can write the SOFT_PWR_OFF bit in Power Control Register (PCR) to turn off the power. It
is equivalent to pressing the button S1.
Caution: Software should be written extremely carefully when setting SOFT_PWR_OFF bit in
PCR. With this bit set at the very beginning, when system is powered on and booted up, the
whole system will be powered off by software. As a result, there is no chance to turn on the
system. There is even no chance to download new image to the flash. Currently, this function is
disabled by hardware (R3 is not installed). If user wants to enable it, a 100 ohms resister should
be installed at R3.
2.2.2 Reset
The Sitsang / PXA255 Evaluation Board can be reset by three methods:
1. By a reset button: User can press S6 to reset the whole system.
2. Software can write the SYS_RESET bit in Board Control Register (BCR). Writing this bit is
equivalent to pressing the reset button.
Caution: Software should be written extremely carefully when setting SYS_RESET bit in
BCR. With this bit set at the very beginning, when system is powered on and booted up, the
whole system is reset and the software will run again. As a result, the system is reset again.
There is no chance to turn on the system. There is even no chance to download new image
to the flash, because the JTAG channel does not work during reset. Currently, this method
is disabled by hardware (R69 is not installed). If user wants to enable it, a 100 ohms resister
should be installed at R69.
3.
User can press button S5 for GPIO reset. When GPIO reset is not used, S5 can be used as a
soft button. Please refer to the Intel® PXA255 and PXA210 Application Processors
Developer’s Manual for details about the GPIO reset.
2.2.3 FLASH Memory and Boot ROM
Four Intel E28F128J3A-150 StrataFlash memory devices in TSOP-56 packages provide two identical
banks of Flash memory for the platform, each bank of two devices containing 32 Mbytes of flash
memory.
s Guide
2-5
Two of these devices, labeled ROM, contain the factory-installed boot code. Normally, the system is
booted form the ROM.
The other two devices, labeled FLASH, provide 32 Mbytes of Flash memory available to the user. The
FLASH bank can serve as the boot source when press soft button S2 during power up. It swaps the chip
select signals between the ROM and FLASH banks.
After being powered on, no matter which bank the system is booted from, software can access 64
Mbytes continuous flash memory.
Each bank can be write-protected by setting FLASH_Bx_WP bit in Board Control Register (BCR). In
addition, the BOOT_FROM_0 bit in BSR indicates from which bank the system is booted.
Caution: Software should be written extremely carefully when setting FLASH_Bx_WP bit in BCR.
With this bit set at the very beginning, when system is powered on and booted up, the flash is locked.
There is no chance to download new image to the flash. Currently, this function is disabled by
hardware (R36 and R38 are not installed). If user wants to enable it, a 0 ohms resister should be
installed at R36 for protecting bank0 or R38 for protecting bank1.
User can download different images into two banks. For example, one bank is for WinCE and the other
is for Linux. User can switch between two images by only pressing S2 during power up.
Since the bank selection is controlled by the firmware in CPLD, the CPLD must be programmed before
the processor is booted.
2.2.4 SDRAM
Two Samsung K4S561632C-TC75 chips, soldered to board, supply 64 Mbytes of SDRAM, organized
as 4 Mbits, 16 bits wide, across 4 banks. The SA1111 memory-addressing mode is used. For more
information, refer to the Memory Controller section in the Intel® PXA255 and PXA210 Application
Processors Developer’s Manual.
2.2.5 Board Level Registers (BLRs) and Interrupt Controller
A Xilinx CoolRunner*Complex Programmable Logic Device (CPLD) implements the Board Level
Registers and the peripheral interrupt controller.
Section 3.2, “Board Level Registers”describes the registers and their programming.
2.2.6 LCD display and Interface
A Toshiba LTM04C380K is used as the LCD screen. This 4”LCD supports 640 x 480 pixels
resolution with 18 bits color (Only 16 bits are used). Table 2- 1
LCD color pin mapping lists the
color pin mapping
PXA255 LDD Data bus
LDD [15:11]
LDD [10:5]
LDD [4:0]
LTM04C380K color bus
Red [5:1], Red [0] is grounded
Green [5:0]
Blue [5:1], Blue [0] is grounded
Table 2- 1
LCD color pin mapping
There are several bits in BLRs to control the LCD
Register
Bits
Function
0: Turns off LCD power
LCD_ON
1:
Turns on LCD power
PCR
0: Turns off Backlight power
LIGHT_ON
1: Turns on Backlight power
Table 2- 2
BLRs for LCD
Because the LTM04380K is a transparent type panel, the backlight must be turned on before the LCD
can display. Sitsang uses HBL0204 as the backlight inverter. Software must follow the timing
specification described in HBL0204 equipment specification when turning on the backlight.
1. Make sure the PWM0 is set as input GPIO. This means PXA255 does not drive this signal
s Guide
2-6
2.
Set the LIGHT_ON in PCR. This only turns on the backlight inverter. The backlight is not
lighted up at this time.
3. Delay at least 1ms
4. Software sets PWM0 to alternative function and drives it. The period of PWM0 should be
larger than 4 ms. The duty cycle should be set between 20% and 100%. Now the backlight is
lighted up.
Software can control the LCD brightness by setting duty cycle of the PWM0 signal. The larger duty
cycle means brighter screen.
A 27-pin connector J3 is used for LTM04380K signals. It connects with LCD through a FPC cable.
All the PXA255 LCD signals are connected to another 33-pin universal connector----J15 to support
different types of the LCD panel. For the detail of this connector, refer to Table 2- 17 J15’s pin
mapping.
2.2.7 Bus Driver and Transceiver
A 74LVCH32245 is used as the data bus transceiver. Three 74LVCH32244 are used as the address bus
and control bus drivers. The devices after the transceiver and drivers are called “VX devices”. In
Sitsang board, the VX devices include CF card, USB host controller (ISP1161 BM), Ethernet controller
(LAN91C96) and user’s expansion card.
Since the drivers and transceiver are bus-hold type devices. User needs to pay more attention when
designing software and expansion card. For more information about the bus hold devices, please refer
to the application report Bus-Hold Circuit and the datasheet of the transceiver and driver, which can
be found in http://www.ti.com/
For software designer:
1. Must initialize XS_CS1 (GPIO 15), XS_CS2 (GPIO 78), XS_CS3 (GPIO 79), XS_CS4
(GPIO 80), XS_CS5 (GPIO 33), XS_CF_nPCE1 (GPIO 52), XS_CF_nPCE2 (GPIO 53) to
their alternate functions at the very beginning. Since these signals are low active chip
selections for different devices, software must first set GPSR to 1, set GPDR to output and
finally set GPAR to select their alternate function.
2. Make sure VX devices have been initialized before accessing them. For example, if software
wants to access CF card, it must make sure the all the GPIOs for CF card are initialized, CF
card is inserted and CF card is powered on.
For expansion card designer:
1. Leave those unused EX_BSRx and EX_BIPRx pins open or pull them up/down with 10K ~
100K ohms resister. When leaved open, the signals will be low.
2. For EX_BSRx and EX_BIPRx pins used, must keep driving them to steady level by hardware.
Otherwise, use 3K ohms resister to pull up/down the signals. For example, if user wants to use
a button to trigger the EX_BIPR, a 3K ohms pull up resister must be added to make sure it is
at high level when the button is not pressed.
2.2.8 Compact Flash Card
Sitsang supports one CF card through PXA255 PCMCIA bus. There is some glue logic in the CPLD. In
order to support hot plug, most PCMCIA bus signals are buffered to the CF socket.
Driver and
Transceiver
PXA250
CPLD
Figure 2- 4
CF Card
Driver and
Transceiver
Compact Flash card block diagram
The CF card is controlled by several bits in BLRs.
s Guide
2-7
Register
Bits
PCR
CF_ON
BUS_OPEN
BCR
CF_RESET
CF_nCSEL
CF_VS1
BSR
CF_CARD_INSERT
CF_nIRQ_RDY_STATUS
CF_IRQ
BIPR
CF_CARD_DETECT_IRQ
Function
0: Turns off CF power
1: Turns on CF power
0: Turns off the transceiver
1: Turns on the transceiver
0: Releases CF card reset
1: Asserts CF card reset
0: CF card works in master mode (IDE mode only)
1: CF card works in slaver mode (IDE mode only)
0: CF card can be accessed at 3.3V
1: CF card can be accessed at 5V
Currently 5V CF card is not supported by Sitsang board
0: CF card is not inserted
1: CF card is inserted
Monitor the CF_nIRQ_RDY signal
Set to 1 when falling edge is detected on CF_nIRQ
Set to 1 when either rising edge or falling edge is detected
on CF card’s nCD1 and nCD2 signal
Table 2- 3
BLRs for CF card
When CF card is inserted:
1. CF_CARD_INSERT bit in BSR is set by hardware
2. The CF_CARD_DETECT_IRQ bit in BIPR is set by hardware
3. An interrupt is triggered on GPIO9 by hardware
4. Software checks the BSR and BIPR, and then sets the CF_ON bit in PCR. This turns the CF
card power on.
5. Software sets the CF_RESET bit in BCR. This asserts the CF card reset signal
6. Delay for a while
7. Software clears the CF_RESET bit in BCR. This releases the CF card reset signal
8. Software checks the BSR and BIPR, and then sets BUS_OPEN bit in BCR.
9. In order to capture interrupts from other devices, which share the same GPIO interrupt,
software must clear the CF_CARD_DETECT_IRQ bit in BIPR as soon as possible.
10. Software can access the CF card.
When CF card is removed:
1. CF_CARD_INSERT bit in BSR is cleared by hardware
2. The CF_CARD_DETECT_IRQ bit in BIPR is set by hardware
4. Software checks the BSR and BIPR, then clears BUS_OPEN bit in BCR
5. Software checks the BSR and BIPR, and then clears the CF_ON bit in PCR. This turns off the
CF power supply.
6. Software must clear the CF_CARD_DETECT_IRQ bit in BIPR as soon as possible.
2.2.9 Universal Serial Bus (USB) Host Controller
A Philips ISP1161 is used as the USB host controller on Sitsang board. The ISP1161 supports two
USB host ports and one USB client port. Sitsang now only use two USB host ports. The PXA255 data
bus and address bus are buffered for ISP1161.
s Guide
2-8
PXA250
Application
Processor
Transceiver
Data bus
Data bus
ISP1161
USB controller
Driver
Address bus
USB
USB
Port
Port
Address bus
CPLD
MAX1823
Figure 2- 5
USB host controller block diagram
Sitsang uses MAX1823 as 2 USB host ports’power supplier and over current detector. It can drive
500mA for each port at the same time. If over load is detected on either port, the MAX1823 will
automatically turn off the power supply for a while. An over current interrupt is captured in BIPR.
The USB host controller is controlled by the following bits in BLRs.
Register
Bits
Function
0: Turns off USB host controller power
PCR
USB_HOST_ON
1: Turns on USB host controller power
0: Turns off the driver and transceiver
BUS_OPEN
1: Turns on the driver and transceiver
This specifies the number of downstream USB HC ports
supported by the Root Hub.
USB_NDP
0: select 1 downstream port
BCR
1: select 2 downstream ports
0: Releases USB Host controller ISP1161 reset
USB_HC_RESET
1: Asserts USB Host controller ISP1161 reset
0: ISP1161 Host controller does not wake up
USB_HC_WAKE
1: ISP1161 Host controller wake up
0: The USB HC1 over current status is not detected
USB_HC1_OC
1: The USB HC1 over current status is detected
BSR
USB_HC2_OC
USB_INT_STATUS
Monitor the USB_INT signal
USB_HC1_OC_IRQ
Set to 1 when USB HC1 over current is detected
BIPR
USB_HC2_OC_IRQ
Set to 1 when USB HC2 over current is detected
USB_HC_IRQ
Set to 1 when raise edge is detected on ISP1161 INT1
Table 2- 4
BLRs for USB Host
If software wants to access USB HC port, it should follow the steps below:
1. Set USB_HOST_ON bit in PCR. This turns on the ISP1161 power supply.
2. Set BUS_ON bit in BCR.
3. Set USB_HC_RESET bit in BCR. This asserts the reset signal of ISP1161
4. Delay for a while
5. Clear USB_HC_RESET bit in BCR. This releases the reset signal of ISP1161
6. Access the ISP1161
When a USB device is inserted:
1. USB_HC_IRQ in BIPR is set to 1 by hardware
2. A interrupt is triggered on GPIO7 by hardware
3. Software read the ISP1161 internal register to get which port is connected to device
When a USB device is removed:
1. USB_HC_IRQ bit in BIPR is set by hardware
s Guide
2-9
2.
3.
4.
A interrupt is triggered on GPIO7 by hardware
Software should clear the BUS_ON bit in BCR if needed
Software should clear the USB_HOST_ON bit in PCR if needed. This turns off the ISP1161’s
power supply.
Since the USB device detection is done by ISP1161, software must turn on the ISP1161 power before it
can detect the USB device.
If over current event is detected:
1. Max1823 detects the over-current status. The nFAULTx pin is driven low by hardware
2. USB_HCx_OC bit in BSR is set by hardware
3. H_PSWx pin of ISP1161 is driven low. The Max1823 turn off the USB5V supply for the
overload USB port
4. USB_HC_OC_IRQ bit in BIPR is set by hardware
5. An interrupt is triggered on GPIO0
6. Software should handle the overload event.
2.2.10 Audio CODECs
The Crystal CS4201, by Cirrus Logic, is a stereo CODEC designed for PC multimedia systems. It is
compatible with AC97 2.1 protocol. This CODEC has a 20-bit digital-to-analog converter and an 18-bit
stereo analog-to-digital converter.
The CS4201 is controlled by the following bit in BLRs.
Register
Bits
Function
0: Turns off the Audio CODEC power
PCR
AUDIO_ON
1: Turns on the Audio CODEC power
Table 2- 5
BLRs for Audio CODECs
An audio jack J11 is used for the stereo headphone out. J25 is used for the stereo line in. Moreover, J26
is used for microphone in. Beside these, a mini-speaker and a mini-microphone are also installed on the
board.
2.2.11 Touch Screen Controller
A touch-screen controller, the Burr Brown ADS7846, communicates with the processor through the
PXA255 Synchronous Serial Port Controller (SSPC), using the National Microwire* Frame Format.
Connector J4 is used for Touch Screen panel signals.
The ADS7846 is controlled by the following bits in BLRs.
Register
Bits
Function
0: Touch screen pen up
BSR
TS_PEN_DOWN
1: Touch screen pen down
BIPR
TOUCH_SCREEN_IRQ
Set to 1 when touch screen is touched
Table 2- 6
BLRs for Touch Screen
When the pen touches the touch screen:
1. TS_PEN_DOWN in BSR is set by hardware
2. TOUCH_SCREEN_IRQ in BIPR is set by hardware
When the pen keeps touching on the touch screen:
1. TS_PEN_DOWN in BSR keeps being set by hardware
2. No more interrupt occurs even when the TOUCH_SCREEN_IRQ in BIPR is cleared by
software
When the pen is removed from the touch screen:
1. TS_PEN_DOWN in BSR is cleared by hardware
s Guide
2-10
2.
No more interrupt occurs even when the TOUCH_SCREEN_IRQ in BIPR is cleared by
software
In order to read stable position data of touching point, software should make sure that the pen is really
down or up instead of just a glitch. Here is an example:
1. Software gets the interrupt from the TOUCH_SCREEN_IRQ from BIPR
2. In the interrupt handler, software sets the TOUCH_SCREEN_IRQ_MASK in BIMR; this
prevents more pen down interrupts. Moreover, software enables the OS timer interrupt.
3. In OS timer interrupt, software reads TS_PEN_DOWN in BSR. If the value is 0, it means this
interrupt is triggered by a glitch. Software should clear TOUCH_SCREEN_IRQ_MASK bit in
BIMR, disable the OS timer interrupt and wait for next pen down interrupt.
4. Repeat step 3 until software considers it is a stable pen down, and then reads the x, y value.
5. After processing a stable pen down event, if TS_PEN_DOWN read is 0, software should also
repeat several times to make sure the pen is really removed from the screen
6. If the software considers the pen is really removed from the screen, it should clear the
TOUCH_SCREEN_IRQ _MASK in BIMR and TOUCH_SCREEN_IRQ in BIPR to re-enable
the pen down interrupt. Disable the OS timer interrupt if necessary.
Actually, there is an Analog-to-Digital Converter (ADC) inside the ADS7846. Besides converting the
touch screen signals, it can also be used for other analog signals. In Sitsang board, the battery voltage
and VCC core voltage for PXA255 are connected to the analog inputs of ADS7846. Software can
monitor these 2 voltages if needed.
2.2.12 USB Client Port
A mini B USB connector, J19, connects to the PXA255 processor’s USB Device Controller interface
by dedicated I/O pins. The USB B port can also be used as the charger for the battery. It can drive
500mA current.
The USB client port is controlled by the following bits in BLRs.
Register
Bits
Function
0: The D+ signal of USB device port is not pulled up
BCR
USB_DC_PULL_UP
1: The D+ signal of USB device port is pulled up
0: PXA255 USB device port is not inserted
BSR
USB_DC_INSERT
1: PXA255USB device port is inserted
BIPR
USB_B_DETECT_IRQ
when plugging in or out event occurs
Table 2- 7
BLRs for USB Client
When a USB host device is inserted
1. USB_DC_INSERT bit in BSR is set by hardware
2. USB_B_DETECT_IRQ bit in BIPR is set by hardware
4. Software should set USB_DC_PULL_UP bit in BCR. Thus, a USB device (Sitsang board)
being plugged in will be detected by the host.
5. Software can access the USB
When a USB host device is removed:
1. USB_DC_INSERT bit in BSR is cleared by hardware
2. USB_B_DETECT bit in BIPR is set by hardware
4. Software should clear the USB_DC_PULL_UP bit in BCR
2.2.13 IrDA Infrared Transceiver
The Sitsang contains a dual-mode Agilent IrDA transceiver compatible of both slow infrared (SIR) and
fast infrared (FIR) protocols
The IrDA transceiver is controlled by the following bits in BLRs.
Register
Bits
Function
s Guide
2-11
PCR
0: Turns off the IrDA power
1: Turns on the IrDA power
00: Max range and power
01: Shutdown. Power off
10: 2/3 range and power
IrDA Frequency select
0: SIR
1: MIR/FIR
Controls IrDA chip data rate. Refer to IrDA chip vendor spec
for details
IRDA_ON
IR_MODE [1:0]
BCR
IR_FSEL
Table 2- 8
BLRs for IrDA
2.2.14 Serial Communication ports
The PXA255 processor has two UARTs for serial communications: one Full Function (FF) and one
Bluetooth (BT). They communicate with the interfaces on the Sitsang board through dedicated GPIO
pins. Each of them connects to an IO connector through a Maxim MAX3244ECAI RS232 transceiver
on the Sitsang board. The BT UART is connected to J21, a standard DB-9 connector. The FF UART
shares J17 with JTAG signals. Please refer to Table 2- 18 and Table 2- 19 for the pin mapping of J17
and J21.
The PXA255 BT UART interface is intended to communicate with a Bluetooth base band controller. It
can be used at standard serial levels via the Maxim MAX3244ECAI RS232 transceiver.
The FF UART and BT UART ports are controlled by the following bits in BLRs.
Register
Bits
Function
0: Disable the FF UART transceiver
RS232_ON
1: Enable the FF UART transceiver
PCR
0: Disable the BT UART transceiver
BTUART_ON
1: Enable the BT UART transceiver
0: The BT USRT is not inserted
BTUART_INSERT
1: The BT UART is inserted
BSR
0: The FF UART is not inserted
RS232_INSERT
1: The FF UART is inserted
RS232_DETECT_IRQ
during FF UART plug in or out
BIPR
BTUART_DETECT_IRQ
during BT UART plug in or out
Table 2- 9
BLRs for FF UART and BT UART
When FF UART is inserted:
1. RS232_INSERT bit in BSR is set by hardware
2. RS232_DETECT_IRQ bit in BIPR is set by hardware
3. An interrupt is trigged on GPIO9 by hardware
4. Software checks the BSR and BIPR, then sets the RS232_ON bit in PCR. This enables the
Maxim MAX3244ECAI for FF UART transceiver.
5. In order to capture other devices’interrupt, software must clear the RS232_DETECT_IRQ bit
in BIPR as soon as possible.
6. Software can access the FF UART
When FF UART is removed:
1. RS232_INSERT bit in BSR is cleared by hardware
2. RS232_DETECT_IRQ bit in BIPR is set by hardware
3. Software checks the BSR and BIPR, then clear RS232_ON bit in PCR. This disables the
Maxim MAX3244ECAI for FF UART transceiver.
4. In order to capture other devices’interrupt, software must clear the RS232_DETECT_IRQ bit
in BIPR as soon as possible.
s Guide
2-12
When BT UART is inserted:
1. BTUART_INSERT bit in BSR is set by hardware
2. BTUART_DETECT_IRQ bit in BIPR is set by hardware
4. Software checks the BSR and BIPR, then sets the BTUART_ON bit in PCR. This enables the
Maxim MAX3244ECAI for BT UART transceiver.
5. In order to capture other devices’interrupt, software must clear the BTUART_DETECT_IRQ
bit in BIPR as soon as possible.
6. Software can access the BT UART
When BT UART is removed:
1. BTUART_INSERT bit in BSR is cleared by hardware
2. BTUART_DETECT_IRQ bit in BIPR is set by hardware
3. Software checks the BSR and BIPR, then clear BTUART_ON bit in PCR. This disables the
Maxim MAX3244ECAI for BT UART transceiver.
4. In order to capture other devices’interrupt, software must clear the BTUART_DETECT_IRQ
bit in BIPR as soon as possible.
2.2.15 Multimedia / Secure Digital Memory Card
A Multimedia Card (MMC) or Secure Digital (SD) memory card can be used in socket J1. It
communicates via dedicated I/O pins with the PXA255 MMC controller, using either the MMC or
Serial Peripheral Interface (SPI) protocol. For the details of the socket pin assignments, refer to the
Sitsang / PXA255 Evaluation Platform schematic diagram.
The SD Card is controlled by the following bits in BLRs.
Register
Bits
Function
0: Turns off the SD card power
PCR
SD_ON
1: Turns on the SD card power
0: SD card is unlocked
SD_WP
1: SD card is locked
BSR
0: SD card is not inserted
SD_INSERT
1: SD card is inserted
BIPR
SD_DETECT_IRQ
during SD card plug in or out
Table 2- 10
BLRs for SD Card
When SD card is inserted:
1. SD_INSERT bit in BSR is set by hardware
2. SD_DETECT_IRQ bit in BIPR is set by hardware
4. Software checks the BSR and BIPR, then sets the SD_ON bit in PCR. This powers on the SD
card.
5. In order to capture other devices’interrupt, software must clear the SD_DETECT_IRQ bit in
BIPR as soon as possible.
6. Software can access the SD card
When SD card is removed:
1. SD_INSERT bit in BSR is cleared by hardware
2. SD_DETECT_IRQ bit in BIPR is set by hardware
3. Software checks the BSR and BIPR, then clear SD_ON bit in PCR.
4. In order to capture other devices’interrupt, software must clear the SD_DETECT_IRQ bit in
BIPR as soon as possible.
s Guide
2-13
2.2.16 Accelerometer Sensor
An ADXL202JE is used as the accelerometer sensor in Sitsang board. The ADXL202JE is a complete
2-axis accelerometer with a digital output, all on a single monolithic IC. It can measure accelerations
with a full-scale range of ±2g. It can measure both dynamic acceleration and static acceleration. The
outputs are digital signals whose duty cycles are proportional to acceleration, as shown in Figure 2- 6.
T2
T1
Figure 2- 6
ADXL202JE output signal
Here, 50% duty cycle means 0 g. The scale factor is 12.5% duty cycle change per g.
So the Accelerations = (T1/T2 –50%) / (12.5 %) g
In Sitsang board, the T2 is set to 1ms. The bandwidth is set to 100Hz; the rms noise is about 2.5 mg.
For more information, please refer to ADXL202JE datasheet.
A 1MHz clock is used to count T1. AXHR holds the X-axis value and AYHR holds the Y-axis value.
Software can read these 2 registers at any time. A locked value is sent to AXHR and AYHR. As a
result, AXHR and AYHR only held T1 value of the last period.
2.2.17 Ethernet Controller
The Standard Microsystems LAN91C96 Ethernet controller connects to the network through U52,
which provides a 10BASE-T (twisted pair) node, supporting IEEE 802.3 operation at 10 Mbps. For full
information on using this controller, refer to the manufacturer’s data sheet and the Intel® PXA255 and
PXA210 Application Processors Developer’s Manual.
The PXA255 data bus and address bus are buffered for LAN91C96
ROM
AT93C46A
PXA250
Application
Processor
Data bus
Transceiver
Data bus
LAN91C96
LAN controller
Address bus
Driver
Address bus
ISOLATION
TRANSFORMER
PE65726
CPLD
Figure 2- 7
Ethernet host controller block diagram
The LAN91C96 controller is controlled by the following bits in BLRs.
Register
Bits
Function
0: Turns off the LAN91C96 controller power
PCR
LAN_ON
1: Turns on the LAN91C96 controller power
0: Turns off the driver and transceiver
BCR
BUS_OPEN
1: Turns on the driver and transceiver
0: Releases LAN91C96 reset signal
LAN_RESET
1: Asserts LAN91C96 reset signal
s Guide
2-14
LAN_nEN16
0: The LAN91C96 works at 16 bit mode
1: The LAN91C96 works at 8 bit mode
BSR
SMSC_Nint_STATUS
Monitor the SMSC_nINT signal
BIPR
LAN_IRQ
Set to 1 when a falling edge is detected on LAN91C96 IRQ
signal
Table 2- 11
BLRs for Ethernet Controller
A Serial EEPROM ---- AT93C46A is used to configure LAN91C96. Moreover, 4 LED indicators are
used:
D48— Transmit
D49— Board Select
D50— Link
D51— Receive
2.2.18 Expansion Card Slot
The expansion card slot, J22, is intended for customer’s use.
The expansion card slot signals include:
Signal
The number of bits
Data bus
32
Address bus
26
Memory control bus
22
Expansion BCR
8
Expansion BSR
16
Expansion BIPR
8
JTAG bus
5
I2C control bus
2
External clock signal
1
PWM signal
1
Reset signal
1
Card detect signal
2
GND
9
System power (battery)
4
VCC3.3V
3
Total
140
Table 2- 12
Signals type in expansion slot
Refer to Sitsang / PXA255 Evaluation Platform schematic diagram for the detail signals available.
Several BLRs are designed for the expansion slot. The 8-bits EX_BCR is used to control the expansion
card. The 16-bits EX_BSR is used to get status from expansion card. The 8-bits EX_BIPR is used to
capture the interrupts from the expansion card, and the 8-bits EX_BIMR is used to mask these
interrupts.
The Expansion Card Slot is controlled by the following bits in BLRs.
Register
Bits
Function
0: Use internal 1MHz clock to capture external interrupt source
in EX_BIPR
BCR
EXBD_USE_ECLK
1: Use External clock to capture external interrupt source in
EX_BIPR
BSR
EXBD_INSERT
BIPR
EXBD_DETECT_IRQ
EX_BCR
Bits [0..7]
EX_BSR
Bits [0..15]
0: Expansion board is not inserted
1: Expansion board is inserted
Set to 1 when either rising edge or falling edge is detected on
expansion card’s EX_nDETECT_1 or EX_nDETECT_2
These 8 signals are routed from the CPLD to the expansion
board slot. The values of these signals are controlled by the
EX_BCR register
These 16 signals are routed from the expansion board slot to the
CPLD. These signals are monitored by the EX_BSR register.
s Guide
2-15
EX_BIPR
Bits[ 0..4]
EX_BIMR
Bits[0..5]
These 5 signals are routed from the expansion board slot to the
CPLD. When any of these signals changed, corresponding bit in
EX_BIPR is set to 1, and an interrupt is trigged on GPIO10 if
not masked. A 1MHz clock is used to synchronize the trigger.
An external clock signal is also routed from the expansion
board slot to the CPLD. User can use this external clock to
synchronize the trigger by setting EXBD_USE_ECLK to 1 in
BCR
0: Interrupt masked
1: Interrupt unmasked
Table 2- 13
BLRs for Expansion card
Caution: Although all the SDRAM controller signals are connected to the expansion slot, but it is
not recommended to use SDRAM in the expansion card. The reasons are:
1. All the data buses are buffered to expansion slot through a SN74LVCH32245A. The
buffer’s OE is controlled by CPLD code. Currently, there is no logic to enable the SDRAM
space for expansion card.
2. Generally, the speed of SDRAM bus is very fast (about 100MHz), it is not recommended to
use long trace and too many buffers.
User can use static memory (nCS5) space to enlarge the memory space on the expansion card.
Caution: Since most signals for expansion card are buffered by the bus-hold device 74LVCH32245
74LVCH32244, expansion card designer must:
1. Leave the unused EX_BSRx and EX_BIPRx open or use 10K ~ 100K ohms resister to pull
up/down. When leaved open, the signals will be low.
2. For the used EX_BSRx and EX_BIPRx, make sure keep driving them to steady level by
hardware. Otherwise, use 3K ohms resister to pull up/down the signals. For example, if user
wants to use a button to trigger an EX_BIPR, a 3K ohms pull up resister must be added to
make sure it is high level when the button is not pressed.
2.2.19 JTAG Chain
There are 2 JTAG devices on the Sitsang board ---- The PXA255 and the CPLD. The PXA255 is the
first device in the JTAG chain and the CPLD is the second. More JTAG devices on user’s expansion
card can be inserted into the JTAG chain by set a jumper ---- J23. The JTAG chain is shown as:
PXA250
TDI
CPLD
TDO
TMS TCK nTRST
TDI
Expansion card
TDI
TDO
TDO
TMS TCK nTRST
TMS TCK nTRST
TMS TCK nTRST
TDI
TDO
JTAG socket
Figure 2- 8
J23
JTAG Chain
2.2.20 User Switches and Buttons
Table 2- 14 describes the functions of the switches and buttons on the Sitsang board.
Switch
/Button
S1
Name
Function
Power button
Power On/Off
Press S2 during power up to boot from the 2nd bank flash.
After being powered up, this button can be used as softwaredefined function
This switch can be pressed in 5 different directions ---- left,
S2
Soft button 0
S3
5-Way Mini Joystick
s Guide
2-16
S4
Soft button 1
S5
GPIO reset button
S6
Reset button
S7
Hex switch
right, top, bottom and center. It can be used for game
application or controlling the cursor in GUI.
This button can be used as software-defined function
When GPIO1 is configured as GPIO reset source, pressing
this button can cause GPIO reset. Otherwise, this button can
be used as software-defined function
Pressing this button causes hardware reset for the whole
system
0x0 –0xF hexadecimal-encoding switches for being used by
application software
Table 2- 14
Switches and buttons on Sitsang board
The JSSR is used to monitor the status of S2, S3, S4, S5 and S7
2.2.21 LED Indicators
Table 2- 15 describes the functions of the LED indicators on the Sitsang board.
LED
Name
Functions
D8
Charging LED
Indicates the battery is being charged
D10
3.3 V LED
Indicates VCC_3.3V power on
D11
System power on LED
Indicates the system is powered on
Connected to GPIO1of CS4201. This is used to
D12
Audio LED
debug the CS4201
D13
GPIO LED1
Connected to GPIO20 of PXA255
D14
GPIO LED0
Connected to GPIO27 of PXA255
D15
4.2 V LED
Indicates 4.2V is powered on
D48
LAN transmit LED
Indicates data is transmitted from LAN91C96
D49
LAN Board select LED Indicates LAN91C96 board selection status
D50
LAN Link LED
Indicates LAN91C96 link status
D51
LAN receive LED
Indicates data is received by LAN91C96
D28, D34, D21, D41,
Hex LED [0..7]
D47, D17, D39, D32
D25, D23, D26, D27,
These LEDs is used for software debug. Software
Hex LED [8..15]
D22, D20, D31, D46
can write LLEDR to control the HEX LED[0..15],
and write HLEDR to control the
D40, D38, D36, D42,
Hex LED [16..23]
HEXLED[16..31]
D16, D24, D37, D19
D18, D30, D44, D35,
Hex LED [23..31]
D43, D45, D33, D29
Table 2- 15
LEDs on Sitsang board
2.2.22 Connectors
Table 2- 16 describes the functions of the connectors on the Sitsang board.
Connectors Name
Functions
LCD Signal Connector
J3
27 pins FPC connector used by Toshiba LTM04C380K
for LTM04C380K
All LCD signals are connected to this 33-pin FPC
J15
Universal LCD connector
connector. It can be used for other type LCD panel
J4
Touch Screen Connector
4 pin FPC connector used by touch screen
J16
CF socket
50 pin socket used by CF card
J11
Headphone out jack
Used for stereo audio headphone output
The left channel of stereo audio headphone output. When a
J10
Speaker 2 connector
headphone is inserted in J11, the speaker2 will be muted
J12
Speaker 1 connector
mono-audio connector
J25
Audio Line in jack
Used for stereo audio input
J26
Microphone in jack
Used for microphone input
J9
USB Host 1 socket
An USB client device can be inserted
J8
USB Host 2 socket
An USB client device can be inserted
s Guide
2-17
J1
J19
SD card socket
USB client socket
J17
Base Station
J21
J24
J14
J18
BT UART socket
Ethernet socket
Battery connector
Charger jack
J22
Expansion card connector
Table 2- 16
Socket used by SD card
An USB host device can be inserted
JTAG signal and FF UART signals are routed to this 18pin connector
A 9-pin RS232 socket for BT UART
The network cable can be inserted to this T4 socket
The battery can be inserted to this connector
The –6 VDC charger can be inserted to this jack
The expansion card can be inserted to Sitsang board
through this board connector
Connectors on Sitsang board
The J15’s pin mapping is shown in Table 2- 17:
Pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Signal
XS_PWM1
BACKLIGHT_5V
SYS_PWR
XS_L_LCLK
BACKLIGHT_5V
XS_L_FCLK
LCD_3.3V
LCD_3.3V
LCD_3.3V
XS_L_BIAS
XS_LDD4
XS_LDD3
XS_LDD2
XS_LDD1
XS_LDD0
GND
GND
Table 2- 17
The J17’s pin mapping is shown in Table 2- 18:
Pin number
Signal
1
JTAG_TCK
2
FF_RXD
3
GND
4
JTAG_TCK
5
FF_RXD
6
FF_TXD
7
JTAG_nRST
8
FF_RTS
9
JTAG_TMS
Table 2- 18
The J21’s pin mapping is shown in Table 2- 19
Pin number
Signal
1
NC
2
BT_RXD
3
BT_TXD
4
NC
5
GND
Table 2- 19
The J22’s pin mapping is shown in Table 2- 20
Pin number
Signal
1
GND
Pin number
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Signal
XS_LDD10
XS_LDD9
XS_LDD8
XS_LDD7
XS_LDD6
XS_LDD5
GND
XS_LDD15
XS_LDD14
XS_LDD13
XS_LDD12
XS_LDD11
GND
GND
XS_L_PCLK
GND
J15’s pin mapping
Pin number
10
11
12
13
14
15
16
17
18
Signal
FF_CTS
XS_JTAG_TDI
FF_DTR
END_TDO
FF_DSR
VCC_3P3V
FF_DCD
VCC_3P3V
FF_RI
J17’s pin mapping
Pin number
6
7
8
9
Signal
NC
BT_RTS
BT_CTS
NC
J21’s pin mapping
Pin number
71
s Guide
Signal
GND
2-18
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
GND
SYS_PWR
VX_DATA0
VX_DATA1
VX_DATA2
VX_DATA3
VX_DATA4
VX_DATA5
VX_DATA6
VX_DATA7
VX_DATA8
VX_DATA9
VX_DATA10
VX_DATA11
VX_DATA12
VX_DATA13
VX_DATA14
VX_DATA15
VX_DATA16
VX_DATA17
VX_DATA18
VX_DATA19
VX_DATA20
VX_DATA21
VX_DATA22
VX_DATA23
VX_DATA24
VX_DATA25
VX_DATA26
VX_DATA27
VX_DATA28
VX_DATA29
VX_DATA30
VX_DATA31
EX_NDETECT_2
VCC_3P3V
VX_ADDR0
VX_ADDR1
VX_ADDR2
VX_ADDR3
VX_ADDR4
VX_ADDR5
VX_ADDR6
VX_ADDR7
VX_ADDR8
VX_ADDR9
VX_ADDR10
VX_ADDR11
VX_ADDR12
VX_ADDR13
VX_ADDR14
VX_ADDR15
VX_ADDR16
VX_ADDR17
VX_ADDR18
VX_ADDR19
VX_ADDR20
VX_ADDR21
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
s Guide
GND
SYS_PWR
VX_EX_BCR0
VX_EX_BCR1
VX_EX_BCR2
VX_EX_BCR3
VX_EX_BCR4
VX_EX_BCR5
VX_EX_BCR6
VX_EX_BCR7
EXT_CLK
XS_PWM1
VX_EX_BSR0
VX_EX_BSR1
VX_EX_BSR2
VX_EX_BSR3
VX_EX_BSR4
VX_EX_BSR5
VX_EX_BSR6
VX_EX_BSR7
VX_EX_BSR8
VX_EX_BSR9
VX_EX_BSR10
VX_EX_BSR11
VX_EX_BSR12
VX_EX_BSR13
VX_EX_BSR14
VX_EX_BSR15
VCC_3P3V
VCC_3P3V
VX_EX_BIPR0
VX_EX_BIPR1
VX_EX_BIPR2
VX_EX_BIPR3
VX_EX_BIPR4
VX_EX_BIPR5
VX_EX_BIPR6
VX_EX_BIPR7
VX_nSDRAS
VX_nSDCAS
VX_nCS1
VX_nCS2
VX_nCS3
VX_nCS4
VX_nCS5
VX_DQM0
VX_DQM1
VX_DQM2
VX_nOE
VX_DQM3
VX_RDY
VX_nSDCS1
VX_nSDCS2
VX_nSDCS3
VX_SDCKE0
VX_SDCKE1
VX_nWE
GND
2-19
60
61
62
63
64
65
66
67
68
69
70
VX_ADDR22
VX_ADDR23
VX_ADDR24
VX_ADDR25
XS_I2C_SCL
JTAG_nRST
JTAG_TMS
CPLD_TDO
SYS_PWR
GND
GND
130
131
132
133
134
135
136
137
138
139
140
Table 2- 20
VX_SDCLK0
VX_SDCLK1
VX_SDCLK2
VX_RD_nWR
XS_I2C_SDA
JTAG_TCK
EX_TDO
XS_nRESET_IN
SYS_PWR
GND
GND
J22’s pin mapping
2.2.23 Jumpers
Table 2- 21 describes the functions of the jumpers on the Sitsang board.
Jumper Name
Functions
J7
Reserved Jumper
Reserved
J20
Reserved for debug
Must be shorted
Short 1-2 means only PXA255 and CPLD in the JTAG chain
J23
JTAG Chain Jumper
Short 2-3 means other JTAG devices on expansion board are
included in the JTAG chain
Table 2- 21
Jumpers on Sitsang board
2.2.24 Power system
Table 2- 22 lists all the powers on Sitsang board
Name
Value
Main Device
WALL_9V_PWR -6v
Battery Charger voltage from the wall adaptor
USB_5V_PWR
5V
Battery Charger voltage from the USB Client port
VCC_BATT
2.7~4.2
Battery voltage before switch
SYS_PWR
2.7~4.2
Battery voltage after switch
VCC_CORE
0.8~1.7
PXA255 core supply
VCC_3P3V
3.3V
PXA255, SDRAM, Flash, CPLD, Driver and Transceiver
DC4.2V
4.2V
The source of most peripherals power LDO and booster
LCD_3P3V
3.3V
LCD panel
BACKLIGHT_5V 5V
HBL0204
CF_3P3V
3.3V
CF card
AUDIO_5V
5V
CS4201
AUDIO_3P3V
3.3V
CS4201
SD_3P3V
3.3V
SD card
ACC_3P3V
3.3V
ADXL202JE
USB_5V
5V
Drive USB host port 5V
USB_3P3V
3.3V
ISP1161
IRDA_3P3V
3.3V
HSDL-3600
SMSA_3P3V
3.3V
LAN91C96
Table 2- 22
Power supply on Sitsang board
Most power supplies can be controlled by PCR.
s Guide
2-20
The block diagram of the power system is shown in Figure 2- 9
Audio_3P3V
MIC5219
USB_5V
MAX1703
AUDIO_5V
MAX1796
BACKLIGHT_5V
MAX1796
MIC5219
MIC5219
SYS_PWR
DC_4P2V
MIC5219
USB_5V_PWR
MAX1703
WALL_9V_PWR
MAX1792
MAX1793
LTC1730S8
Battery
MIC5219
Switch
LCD_3P3V
CF_3P3V
ACC_3P3V
IRDA_3P3V
SD_3P3V
USB_3P3V
SMSC_3P3V
VCC_3P3V
MAX1820
VCC_CORE
VCC_BATT
MAX4544
MAX5360 A
Figure 2- 9
MAX5360 B
Block diagram of the power system on Sitsang
2.2.24.1 VCC Core
The VCC_CORE is the most complicated supply in Sitsang. Its value can be controlled from 0.8 to
1.7V by I2C bus. Moreover, there is a special timing requirement for the DVM. Refer to Intel®
PXA255 and PXA210 Applications Processors Power Supply Design for more information.
Sitsang uses MAX1820 as the regulator of VCC_CORE. There are 2 DAC chips (MAX5360A and
MAX5360B) on Sitsang board, whose output voltages can be controlled by I2C bus. An analog switch
MAX4544 is used to select one of the MAX5360 outputs as the reference voltage of MAX1820. The
analog switch is controlled by CPLD. The output of MAX1820 is
VCC_CORE = 1.76 x Reference voltage.
So, the VCC_CORE can be controlled by I2C bus. After system is powered on, the VCC_CORE value
is set to 1.46V. Normally, user need not change the VCC_CORE unless the system is very power
sensitive.
Obey following steps when PXA255 wants to change the VCC_CORE supposing that MAX5360B is
the reference of MAX1820:
1. Software writes I2C command to the DAC MAX5360A, which is not selected by MAX4544
to MAX1820. This step only changes the alternative reference voltage for MAX1820. The
VCC_CORE will not be changed
2. Software sets the VCC_CHANGE bit in PCR.
3. Software enters sleep mode. The XS_PWR_EN signal is driven low by hardware.
4. The MAX1820 is disabled, and the VCC_CORE is 0V.
5. 1us later XS_PWR_EN is driven low. The CPLD triggers the MAX4544. The new reference
voltage (output of MAX5360A) is added on MAX1820. The VCC_CORE is still 0V because
XS_PWR_EN signal is low
6. 1us later the MAX4544 is switched. The CPLD triggers a wake up signal to the PXA255
GPIO11 and the VCC_CHANGE bit in PCR is cleared by hardware.
7. The PAX250 enters the wake up process. The XS_PWR_EN signal is driven high
s Guide
2-21
8.
The MAX1820 is enabled with new reference voltage (output of MAX5360A). The
VCC_CORE is set to the new value
Both of the references DACs are I2C devices. They have different I2C addresses:
DAC
MAX4544MEUK
MAX4544LEUK
I2C Address
0x62
0x60
Table 2- 23
Power on connected
Yes
No
MAX4544M/LEUK I2C address
2.2.25 JTAG Cable
The JTAG Cable’s drawing is shown in Figure 2- 10
Figure 2- 10
JTAG cable drawing
s Guide
2-22
Programming Guide
3
Programming Guide
The PXA255 processor controls the entire Sitsang / PXA255 Evaluation Platform, either by including
peripherals in the memory map or by using established PXA255 control modules and I/O lines. In all
matters of programming detail, refer to the Intel® PXA255 and PXA210 Application Processors
Developer’s Manual.
3.1
Memory Map and Chip selects
Table 3- 1 details the physical addresses and active-low chip selects (nCSx) for the Sitsang / PXA255
Evaluation Platform. For a complete listing of the PXA255 memory map, refer to the Memory
Controller section of the Intel® PXA255 and PXA210 Application Processors Developer’s Manual.
Address range
0x0000,0000~0x01FF,FFFF
0x0200,0000~0x03FF,FFFF
0x0400,0000~0x047F,FFFF
0x0480,0000~0x04FF,FFFF
0x0500,0000~0x07FF,FFFF
0x0800,0000~0x0BFF,FFFF
0x0C00,0000~0x0FFF,FFFF
0x1000,0000~0x13FF,FFFF
0x1400,0000~0x17FF,FFFF
0x1800,0000~0x1FFF,FFFF
0x2000,0000~0x2FFF,FFFF
0x3000,0000~0x3FFF,FFFF
Resource size
Static CS0: 32MB
Static CS0: 32MB
Static CS1: 8MB
Static CS1: 8MB
Static CS1: 48MB
Static CS2: 64MB
Static CS3: 64MB
Static CS4: 64MB
Static CS5: 64MB
Reserved
PCMCIA /CF card slot0 256MB
PCMCIA /CF card slot1 256MB
0x4000,0000~0x4BFF,FFFF
Internal register space
0x4C00,0000~0x9FFF,FFFF
0xA000,0000~0xA3FF,FFFF
0xA400,0000~0xA7FF,FFFF
0xA800,0000~0xABFF,FFFF
0xAC00,0000~0xAFFF,FFFF
Reserved
SDRAM bank 0 64M
SDRAM bank 1 64M
SDRAM bank 2 64M
SDRAM bank 3 64M
Table 3- 1
Function
Boot ROM
Application flash
Ethernet IO space
Ethernet Attribute space
Board Reserved
Board level register
Board Reserved
USB Host
Expansion Slot
PXA255 reserved
CF card
Board Reserved
PXA255 Memory
mapped register
Reserved
Main memory
Board Reserved
Board Reserved
Board Reserved
Width
32
32
32
32
16
16
32
32
32
32
32
Sitsang / PXA255 Evaluation Platform memory map
Software must initialize XS_CS1 (GPIO 15), XS_CS2 (GPIO 78), XS_CS3 (GPIO 79), XS_CS4
(GPIO 80), XS_CS5 (GPIO 33), XS_CF_nPCE1 (GPIO 52), XS_CF_nPCE2 (GPIO 53) to alternate
function at very beginning time. Since these signals are low active chip selections for different devices,
software must first set GPSR to 1, set GPDR to output and finally set GPAR to select their alternate
function.
3.2
Board Level Registers (BLRs)
The following registers, implemented on Sitsang board, provide for peripheral configuration and
control:
Name
Function
Access
Address
PCR
Power control register
Read and write 0x0800,0000
BCR
Board control register
BSR
Board status register
Read only
0x0800,0008
BIPR
Board interrupt pending register
Read and write 0x0800,000C
BIMR
Board interrupt mask register
Accelerometer x direction logic high counter
AXHR
Read only,
0x0800,0014
register
AXLR
Reserved
Read only
0x0800,0018
AYHR
Accelerometer Y direction logic high counter
Read only
0x0800,001C
s Guide
3-1
Programming Guide
JSSR
LLEDR
HLEDR
EX_BCR
EX_BSR
EX_BIP
R
EXPIMR
register
HEX switch, Joystick switch and soft button status
register
Low 16-bits LED matrix control register
High 16-bits LED matrix control register
Expansion card board control register
Expansion card board status register
Read only
0x0800,0020
Read and write
Read and write
Read and write
Read only
0x0800,0024
0x0800,0028
0x0800,002C
0x0800,0030
Expansion card interrupt pending register
Read and write
0x0800,0034
Expansion card interrupt mask register
Read and write
0x0800,0038
Table 3- 2
BLRs on Sitsang boards
The maxim width of BLRs is 16-bits. The address of BLRs is decoded by XS_Addr [6..2] and
Xs_nCS2. Care should be taken that the addresses of BLRs are incompletely decoded.
Bits
Name
0
CF_ON
1
USB_HOST_ON
2
RS232_ON
3
BTUART_ON
4
SD_ON
5
ACC_ON
6
LCD_ON
7
LIGHT_ON
8
IRDA_ON
9
AUDIO_ON
10
LAN_ON
11
VCC_CHANGE
12~13
Reserved
14
PER_ON
8
7
6
5
4
3
2
IRDA_ON
LIGHT_ON
LCD_ON
ACC_ON
SD_ON
BTUART_ON
RS232_ON
Description
CF_ON
9
Read/write
1
0
USB_HOST_ON
10
AUDIO_ON
VCC_CHAGE
Reserved
Reserved
PER_ON
PWR_OFF
Physical address: 0x0800,0000
15
14
13
12
11
LAN_ON
3.2.1 Power Control Register (PCR)
Reset
value
0: Turns off CF card 3.3V
1: Turns on CF card 3.3V
0: Turns off USB host controller 3.3V, 5V
1: Turns on USB host controller 3.3V, 5V
0: Disable FF UART transceiver
1: Enable FF UART transceiver
0
0: Disable BT UART transceiver
1: Enable BT UART transceiver
0
0: Turns off SD card 3.3V
1: Turns on SD card 3.3V
0: Turns off Accelerometer sensor 3.3V
1: Turns on Accelerometer sensor 3.3V
0: Turns off LCD 3.3V
1: Turns on LCD 3.3V
0: Turns off Backlight 5V
1: Turns on Backlight 5V
0: Turns off IrDA 3.3V
1: Turns on IrDA 3.3V
0: Turns off Audio CODEC 3.3V, 5V
1: Turns on Audio CODEC 3.3V, 5V
0: Turns off LAN91C96 3.3V
1: Turns on LAN91C96 3.3V
0: PXA255 will not change the VCC core voltage when enter
the next sleep mode.
1: PXA255 will change the VCC core voltage when enter the
next sleep mode.
Reserved
0: Turns off all peripheral power supply
1: All individual power suppliers can be controlled by their
s Guide
0
0
0
0
0
0
0
0
0
0
0
3-2
Programming Guide
15
SOFT_PWR_OFF
corresponding bits in PCR.
A rising edge will turn off the whole system. Software first
writes 0 to this bit, then writes 1 to this bit. The system will
power off
Table 3- 3
1.
2.
3.
4.
0
Power control register
The LAN91C96, CF card socket, ISP1161’s data bus and address bus are buffered from the
same transceiver. In order to make the bus access more stable, The CF_3P3V, USB_3P3V,
USB_5V, SMSA_3P3V are turned on when any of CF_ON, USB_HOST_ON, LAN_ON is
set to ‘1’.
Clearing PER_ON to 0 will turn off all the peripheral power, no matter what value is set in
other bits in PCR. The controlled power supplies include: LCD_3P3V, BACKLIGHT_5V,
CF_3P3V, AUDIO_5V, AUDIO_3P3V, SD_3P3V, ACC_3P3V, USB_5V, USB_3P3V,
IRDA_3P3V, SMSA_3P3V.
Please refer to Section 2.2.23.1 for how to access VCC_CHANGE bit
Software must be written extremely carefully when setting SOFT_PWR_OFF bit in PCR.
With this bit set at the very beginning, when system is powered on and booted up, the whole
system is powered off by software. As a result, there is no chance to turn on the system.
There is even no chance to download new image to the flash. Currently, this function is
disabled by hardware (R3 is not installed). If user wants to enable it, a 100 ohms resister
should be installed at R3.
Bits
Name
0
FLASH_B0_WP
1
FLASH_B1_WP
2
BUS_OPEN
3
CF_RESET
4
CF_CSEL
5
USB_NDP
6
USB_HC_RESET
7
USB_HC_WAKE
3
2
Description
0: The flash bank 0 can be programmed
1: The flash bank 0 is locked
0: The flash bank 1 can be programmed
1: The flash bank 1 is locked
0: Turns off the transceiver
1: Turns on the transceiver
0: Releases CF card reset
1: Asserts CF card reset
0: CF card is a slaver (IDE mode only)
1: CF device is a master (IDE mode only)
This specifies the number of downstream USB host ports
supported by the Root Hub.
0: select 1 downstream port
1: select 2 downstream ports
0: Releases the USB Host controller ISP1161 reset
1: Asserts the USB Host controller ISP1161reset
0: ISP1161 Host Controller not wake up
1: ISP1161 Host Controller wake up
A LOW-to-HIGH transition generates a remote wake-up for
ISP1161 from ‘
suspend’state
s Guide
Read/write
1
0
FLASH_BO_WP
4
FLASH_B1_WP
USB_HC_WAKE
5
BUS_OPEN
USB_DC_PULL_UP
6
CF_RESET
7
CF_CSEL
8
USB_NDP
9
USB_HC_RESET
10
IR_MODE0
IR_FSEL
LAN_RESET
LAN_nEN16
EXBD_USE_ECLK
SYS_RESET
15
14
13
12
11
IR_MODE1
3.2.2 Board Control Register (BCR)
Reset
Value
0
0
0
0
0
0
0
0
3-3
Programming Guide
8
USB_DC_PULL_UP
9~10
IR_MODE[1:0]
11
IR_FSEL
12
LAN_RESET
13
LAN_nEN16
14
EXBD_USE_ECLK
15
SYS_nRESET
0: The D+ signal of USB device port is not pulled up
1: The D+ signal of USB device port is pulled up
00: Max range and power
01: Shutdown. Power off
IrDA Frequency select
0: SIR
1: MIR/FIR
Controls IrDA chip data rate. Refer to IrDA chip vendor spec
for details
0: Releases LAN91C96 reset signal
1: Asserts LAN91C96 reset signal
0: The LAN91C96 works in 16 bit mode
1: The LAN91C96 works in 8 bit mode
0: Use internal 1MHz clock to capture external interrupt
source in EX_BIPR
1: Use external clock to capture external interrupt source in
EX_BIPR
0: releases the hardware reset
1: Resets whole system, the system will reboot
Table 3- 4
1.
2.
3.
0
0
0
0
0
0
Board control register
Software must be extremely careful when setting FLASH_Bx_WP bit in BCR. With this bit
set at the very beginning, when system is powered on and booted up, the flash is locked. There
is no chance to download new image to the flash. Currently, this function is disabled by
hardware (R36 and R38 are not installed). If user wants to enable it, a 0 ohms resister should
be installed at R36 or R38.
Software must be extremely careful when setting SYS_nRESET bit in BSR. With this bit set
at the very beginning, when system is powered on and booted up, the whole system is reset
and the software run again. As a result, there is no chance to turn on the system. There is even
no chance to download new image to the flash, for the JTAG channel does not work during
reset. Currently, this function is disabled by hardware (R69 is not installed). If user wants to
enable it, a 100 ohms resister should be installed at R69.
Before set BUS_OPEN to 1, software must make sure the VX device are initialized. For
example, if software wants to access CF card, it must make sure the all the GPIOs for CF card
are initialized, CF card is inserted and CF card is power on.
Bits
Name
0
CF_VS1
1
SD_WP
6
5
4
3
2
USB_DC_INSERT
EXBD_INSERT
TS_PEN_DOWN
USB_INT_STATUS
BOOT_FROM_0
CF_IS5V
7
Read only
1
0
SD_WP
8
CF_nIRQ_RDY_STATUS
9
SMSC_nINT_STATUS
10
USB_HC1_OC
BATT_CHARGING
BTUART_INSERT
RS232_INSERT
CF_C ARD_INSERT
SD_INSERT
15
14
13
12
11
USB_HC2_OC
3.2.3 Board Status Register (BSR)
Description
0: CF card can be accessed at 3.3V
1: CF card can be accessed at 5V
Currently 5V CF card is not supported by Sitsang board
0: SD card is not locked
s Guide
3-4
Programming Guide
2
BOOT_FROM_0
3
USB_INT_STATUS
4
TS_PEN_DOWN
5
EXBD_INSERT
6
USB_DC_INSERT
7
8
CF_nIRQ_RDY_STATUS
SMSC_nINT_STATUS
9
USB_HC1_OC
10
USB_HC2_OC
11
BATT_CHARGING
12
BTUART_INSERT
13
RS232_INSERT
14
CF_CARD_INSERT
15
SD_INSERT
1: SD card is locked
0: Boots from bank0
1: Boots from bank1
Monitor the USB_INT signal
0: Touch screen pen up
1: Touch screen pen down
0: Expansion board is not inserted
1: Expansion board is inserted
0: USB host device is not inserted to client port
1: USB host device is inserted to client port
Monitor the CF_nIRQ_RDY signal
Monitor the SMSC_nINT signal
0: The battery is not being charged
1: The battery is being charged
0: The BT USRT is not inserted
1: The BT UART is inserted
0: The FF UART is not inserted
1: The FF UART is inserted
0: CF card is not inserted
1: CF card is inserted
0: SD card is not inserted
1: SD card is inserted
Table 3- 5
Board status register
BTUART_DETECT_IRQ
RS232_DETECT_IRQ
USB_HC_IRQ
USB_HC2_OC_IRQ
USB_HC1_OC_IRQ
Reserved
Reserved
Name
0
CF_CARD_DETECT_IRQ
1
CF_IRQ
2
USB_B_DETECT_IRQ
3
4
Reserved
Reserved
5
USB_HC1_OC_IRQ
Description
Set to 1 when either rising edge or
falling edge is detected on CF card’s
nCD1 and nCD2 signals
Set to 1 when falling edge is detected on
CF_nIRQ
falling edge is detected when USB B is
insert or removed
Reserved
Reserved
Set to 1 when USB HC1 over current is
detected
s Guide
2
1
0
CF_CARD_DETECT_IRQ
3
CF_IRQ
4
Bits
Read/Write
USB_B_DETECT_IRQ
5
EXBD_DETECT_IRQ
6
SD_DETECT_IRQ
7
LAN_IRQ
8
JOYSTICK_IRQ
9
BATT_CHANGE_IRQ
Physical address: 0x0800,000C
Write 1 to clear, write 0 has no effect
15
14
13
12
11
10
TOUCH_SCREEN_IRQ
3.2.4 Board Interrupt Pending Register (BIPR)
GPIO
Used
Reset
Value
GP9
0
GP7
0
GP9
0
Reserved
Reserved
0
0
GP0
0
3-5
Programming Guide
6
USB_HC2_OC_IRQ
7
USB_HC_IRQ
8
RS232_DETECT_IRQ
9
BTUART_DETECT_IRQ
10
EXBD_DETECT_IRQ
11
SD_DETECT_IRQ
12
LAN_IRQ
13
JOYSTICK_IRQ
14
BATT_CHARGED_IRQ
15
TOUCH_SCREEN_IRQ
Table 3- 6
1.
2.
3.
Set to 1 when USB HC2 over current is
detected
Set to 1 when rising edge is detected on
ISP1161 INT1
falling edge is detected when FF UART
is inserted or removed
falling edge is detected when BT UART
falling edge is detected on expansion
card’s EX_nDETECT_1 or
EX_nDETECT_1
falling edge is detected during SD card
Set to 1 when falling edge is detected on
LAN91C96’s IRQ pin
Set to 1 when joystick or soft buttons are
pushed down or released
Set to 1 when start or stop charging the
battery.
Set to 1 when pen touches the touch
screen
GP0
0
GP7
0
GP9
0
GP9
0
GP9
0
GP9
0
GP5
0
GP4
0
GP0
0
GP4
0
Board interrupt pending register
When any bit in BIPR is set, a GPIOx IRQ triggers the PXA255 if the corresponding BIMR is
set to 1. In order to capture other interrupts or recapture itself, software must clear
corresponding bit in BIPR as soon as possible. To clear the BIPR, write 1 to the
corresponding bit. Write 0 to BIPR takes no effect.
The trigger type setting of rising edge or falling edge described in Table 3- 6 is only for the
BIPR capturing the interrupt source. It cannot be used for PXA255 GPIO trigger type setting.
Software can set rising edge trigger type for GPIO.
A 1MHz clock is used to capture both edge sensitive interrupt sources (Except for
CF_DETECT, SD_DETECT, USB_B_DETECT and EXBD_DETECT, which are captured
by a 2Hz clock to get rid of glitches on these signals).
Here, the BIPR logic can prevent interrupt missing even when 2 interrupts share same GPIO pin. For
example, suppose IRQ1, IRQ2 and IRQ3 are sharing same GPIO interrupt pin. IRQ1 and IRQ2 occur
almost at same time.
IRQ1
IRQ2
IRQ3
Clear BIPR
GPIO
CPU
IRQ1 Handler
Figure 3- 1
IRQ2 Handler
IRQ3 Handler
Interrupt trigger timing
s Guide
3-6
Programming Guide
1.
2.
3.
4.
5.
When IRQ1 occurs, it is pending in the BIPR, GPIO is set to high and trigger the CPU to enter
the IRQ1 handler.
Before CPU exits the IRQ1handler, the IRQ2 occurs. Since the GPIO keep high, CPU does
not clear the BIPR.
The last instruction of IRQ1 handler clears the BIPR. The GPIO is released to low even the
IRQ2 is still pending in BIPR.
If IRQ2 is sharing same GPIO with IRQ1, 1us later, a pulse will be trigger on the GPIO
automatically by hardware. And then, the CPU can be trigger in to the IRQ2 handler.
When IRQ2 handler exits, it clears the BIPR and GPIO is released to low.
7
6
5
4
3
2
RS232_DETECT_IRQ_MASK
USB_HC_IRQ_MASK
USB_HC2_OC_IRQ_MASK
USB_HC1_OC_IRQ_MASK
Reserved
Reserved
USB_B_DETECT_IRQ_MASK
Name
Description
Reset Value
0: Mask
1: Unmask
IRQ_MASK
Table 3- 7
Read/Write
1
0
CF_CARD_DETECT_IRQ_MASK
8
CF_IRQ_MASK
9
BTUART_DETECT_IRQ_MASK
EXBD_DETECT_IRQ_MASK
0..15
SD_DETECT_IRQ_MASK
JOYSTICK_IRQ_MASK
Bits
LAN_IRQ_MASK
10
BATT_CHANGE_IRQ_MASK
15
14
13
12
11
TOUCH_SCREEN_IRQ_MASK
3.2.5 Board Interrupt Mask Register (BIMR)
0
Board interrupt mask register
3.2.6 Accelerometer x direction logic high counter register (AXHR) and
Accelerometer y direction logic high counter register (AYHR)
15
14
13
12
11
Table 3- 8
10
9
8
7
6
5
Accelerometer x direction counter
4
3
Read only
2
1
0
Accelerometer x direction logic high counter register
15
14
13
12
Table 3- 9
11
Read only
10
9
8
7
6
5
Accelerometer y direction counter
4
3
2
1
0
Accelerometer y direction logic high counter register
AXHR and AYHR are the counter registers for the accelerometer sensor. AXHR is for X direction,
AYHR is for Y direction. The count clock is 1MHz.
3.2.7 HEX switch, Joystick switch and soft button status register (JSSR)
15
14
13
12
11
10
9
8
7
6
s Guide
5
4
3
2
Read only
1
0
3-7
Bits
Name
0
LEFT_SW
1
RIGHT_SW
2
TOP_SW
3
BOTTOM_SW
4
PUSH_SW
5
SOFT_BTN_0
6
SOFT_BTN_1
7
SOFT_GPIO_RST_BTN
8~11
12~15
HEX_SW0:3
Reserved
Table 3- 10
LEFT_SW
RIGHT_SW
TOP_SW
BOTTOM_SW
PUSH_SW
SOFT_BTN_0
SOFT_BTN_1
SOFT_GPIO_RST_BTN
HEX_SW0
HEX_SW1
HEX_SW2
HEX_SW3
Reserved
Reserved
Reserved
Reserved
Programming Guide
Description
0: The left switch in S3 is not pushed down
1: The left switch in S3 is pushed down
0: The right switch in S3 is not pushed down
1: The right switch in S3 is pushed down
0: The top switch in S3 is not pushed down
1: The top switch in S3 is pushed down
0: The bottom switch in S3 is not pushed down
1: The bottom switch in S3 is pushed down
0: The center switch in S3 is not pushed down
1: The center switch in S3 is pushed down
0: The soft button 0 (S2) is not pressed
1: The soft button 0 (S2) is pressed
0: The soft button 1 (S4) is not pressed
1: The soft button 1 (S4) is pressed
0: The GPIO reset button (S4) is not pressed
1: The GPIO reset button (S4) is pressed
The HEX value of the HEX switch S7
Reserved
HEX switch, Joystick switch and soft button status register
3.2.8 Low 16-bits LED matrix control register (LLEDR) and High 16-bits LED matrix
LED8
LED7
LED6
LED5
Description
1: LEDx turn on
0: LEDx turn off
LEDx
6
5
4
3
2
LED25
LED24
LED23
LED22
LED21
LED20
LED19
LED18
s Guide
Read/Write
1
0
LED16
7
LED27
8
LED28
9
LED29
10
LED30
15
14
13
12
11
LED26
Low 16-bits LED matrix control register
LED31
Table 3- 11
LED17
0~15
LED0
LED9
Name
3
LED1
LED10
Bits
4
LED2
5
LED3
6
Read/Write
2
1
0
LED4
7
LED11
8
LED12
9
LED13
10
LED14
15
14
13
12
11
LED15
control register (HLEDR)
3-8
Programming Guide
Bits
Name
0~15
Description
1: LEDx turn on
0: LEDx turn off
LEDx
Table 3- 12
High 16-bits LED matrix control register
7
6
5
4
3
2
Reserved
EX_BCR7
EX_BCR6
EX_BCR5
EX_BCR4
EX_BCR3
EX_BCR2
Name
0..15
Description
Reset Value
0: Logic low
1: Logic high
EX_BCR
Table 3- 13
Read/Write
1
0
EX_BCR0
8
EX_BCR1
9
Reserved
Reserved
Reserved
Bits
Reserved
Reserved
10
Reserved
15
14
13
12
11
Reserved
3.2.9 Expansion card board control register (EX_BCR)
0
Expansion card board control register
There are 8 output signals routed from the CPLD to the expansion board slot. The values of these
signals are controlled by the corresponding bit of EX_BCR. 1 means logic high and 0 means logic low.
These bits are set to 0 after system reset. Software can set them to 1 if needed.
0..15
7
6
5
4
3
2
EX_BSR8
EX_BSR7
EX_BSR6
EX_BSR5
EX_BSR4
EX_BSR3
EX_BSR2
Name
Description
Reset Value
0: Logic low
1: Logic high
EX_BSR
Table 3- 14
Read only
1
0
EX_BSR0
8
EX_BSR1
9
EX_BSR9
EX_BSR11
EX_BSR10
Bits
EX_BSR12
EX_BSR13
10
EX_BSR14
15
14
13
12
11
EX_BSR15
3.2.10 Expansion card board status register (EX_BSR)
0
Expansion card board status register
There are 16 input signals routed from the expansion slot to the CPLD. These signals are monitored by
the EX_BSR. 1 means logic high and 0 means logic low.
There are no pull up or pull down resisters on Sitsang board for these signals. The expansion board
designer should leave the unused EX_BSRx open or use 10K ~ 100K ohms resister to pull up/down.
When leaved open, the signals will be low. For the used EX_BSRx, make sure keep driving them to
steady level by hardware. Otherwise, use 3K ohms resister to pull up/down the signals. For example, if
user wants to use EX_BSR to monitor a button status, a 3K ohms pull up resister must be added to
make sure it is high level when the button is not pressed.
3.2.11 Expansion card interrupt pending register (EX_BIPR) and Expansion card
interrupt mask register (EX_BIMR)
15
14
13
12
11
10
9
8
7
6
s Guide
5
4
3
2
Read/Write
1
0
3-9
Bits
Name
0..3
EX_BIPRx
4..15
Reserved
Description
0: No interrupt pending
1: Interrupt pending
Reserved
Table 3- 15
EX_BIPR0
EX_BIPR1
EX_BIPR2
EX_BIPR3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Programming Guide
Reset Value
0
Expansion card interrupt pending register
Name
0..3
EX_BIMRx
4~15
Reserved
Table 3- 16
Reserved
3
2
Read/Write
1
0
EX_BIMR0
Reserved
4
EX_BIMR1
Reserved
Description
0: Mask
1: Unmask
Reserved
5
EX_BIMR2
6
EX_BIMR3
7
Reserved
8
Reserved
9
Reserved
Reserved
Reserved
Bits
Reserved
Reserved
10
Reserved
15
14
13
12
11
Reserved
To clear the EX_BIPR, write 1 to the corresponding bit. Write 0 to EX_BIPR takes no effect.
GPIO Used
Reset Value
GP10
0
Expansion card interrupt mask register
There are 6 input signals routed from the expansion slot to the CPLD. When any of the signals changed,
its corresponding bit in EX_BIPR is set to 1. In addition, an interrupt is trigged on GPIO10 if the
corresponding EX_BIMRx is set to 1. A 1MHz clock is used to capture the interrupt source changing.
An external clock signal is also routed from the expansion slot to the CPLD. User can use this external
clock instead of the 1MHz clock to capture the external interrupt source by setting EXBD_USE_ECLK
to 1 in BCR.
There are no pull up or pull down resisters on Sitsang board for these signals. The expansion board
designer should leave the unused EX_BSRx and EX_BIPRx open or use 10K ~ 100K ohms resister to
pull up/down. When leaved open, the signals will be low. For the used EX_BSRx and EX_BIPRx,
make sure keep driving them to steady level by hardware. Otherwise, use 3K ohms resister to pull
up/down the signals. For example, if user wants to use a button to trigger the EX_BIPR, a 3K ohms
pull up resister must be added to make sure it is high level when the button is not pressed.
3.3
General Purpose Input/Output (GPIO)
The mapping of PXA255 GPIO pins is shown in Table 3- 17.
For instructions on programming the GPIO pins, refer to the Intel® PXA255 and PXA210 Application
Processors Developer’s Manual.
Alternate
GPIO
Signal Name
Direction
Function
function
GP0
BD_IRQ0
N/A
I
Interrupt source 0
GP1
XS_GPIO_nRESET
AltF1
I
GPIO reset input
GP2
SOFT_BTN0
N/A
I
Soft button 0
GP3
SOFT_BTN1
N/A
I
Soft button 1
GP4
BD_IRQ1
N/A
I
Interrupt source 1
GP5
BD_IRQ2
N/A
I
Interrupt source 2
s Guide
3-10
Programming Guide
GP6
XS_MMC_CLK
AltF1
O
MMC card clock
GP7
GP8
GP9
GP10
BD_IRQ3
XS_MMC_CS0
BD_IRQ4
BD_IRQ5
N/A
AltF1
N/A
N/A
I
O
I
I
GP11
CPLD_WEAK_UP
N/A
I
GP12
GP13
GP14
GP15
GP16
GP17
GP18
GP19
GP20
GP21
GP22
GP23
GP24
GP25
GP26
GP27
GP28
GP29
GP30
GP31
GP32
GP33
GP34
GP35
GP36
GP37
GP38
GP39
GP40
GP41
GP42
GP43
GP44
GP45
GP46
GP47
GP48
GP49
GP50
GP51
GP52
GP53
GP54
GP55
GP56
GP57
GP58
GP59
GP60
GP61
XS_CF_nINPACK
GP_SIGNAL_0
GP_SIGNAL_1
XS_nCS_1
XS_PWM0
XS_PWM1
XS_RDY
XS_CF_BVD2
GPIO_LED1
XS_CF_BVD1
ACC_X_OUT
XS_SSP_CLK
XS_SSP_SFRM
XS_SSP_TXD
XS_SSP_RXD
GPIO_LED0
XS_AC97_BITCLK
XS_AC97_DATA_IN0
XS_AC97_DATA_OUT
XS_AC97_SYNC
ACC_Y_OUT
XS_nCS_5
XS_FF_RXD
XS_FF_CTS
XS_FF_DCD
XS_FF_DSR
XS_FF_RI
XS_FF_TXD
XS_FF_DTR
XS_FF_RTS
XS_BT_RXD
XS_BT_TXD
XS_BT_CTS
XS_BT_RTS
XS_IR_RXD
XS_IR_TXD
XS_CF_nPOE
XS_CF_nPWE
XS_CF_nPIOR
XS_CF_nPIOW
XS_CF_nPCE1
XS_CF_nPCE2
XS_CF_nPSKESEL
XS_CF_nPREG
XS_CF_nPWAIT
XS_CF_nIOIS16
XS_LDD0
XS_LDD1
XS_LDD2
XS_LDD3
N/A
N/A
N/A
AltF2
AltF2
AltF2
AltF1
N/A
N/A
N/A
N/A
AltF2
AltF2
AltF2
AltF1
N/A
AltF1
AltF1
AltF2
AltF2
N/A
AltF2
AltF1
AltF1
AltF1
AltF1
AltF1
AltF2
AltF2
AltF2
AltF1
AltF2
AltF1
AltF2
AltF1
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF1
AltF1
AltF2
AltF2
AltF2
AltF2
I
I
I
O
O
O
O
I
O
I
I
O
O
O
I
O
I
I
O
O
I
O
I
I
I
I
I
O
O
O
I
O
I
O
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
Interrupt source 3
MMC card chip select 0
Interrupt source 4
Interrupt source 5
The wake up signal during VCC core
change sequence
CF card INPACK signal
Connect to CPLD for universal use
Connect to CPLD for universal use
Static memory chip select 1
Pulse width modulation signal channel 0
Pulse width modulation signal channel 1
Variable latency I/O device ready
CF card BVD2
A LED 1 is connected
CF card BVD1
Accelerometer sensor x direction output
SSP clock
SSP frame
SSP transmit
SSP receive
A LED 0 is connected
AC-Link bit clock
AC-Link data in
AC97 data out
AC97 Sync
Accelerometer sensor x direction output
FFUART receive data
FFUART clear to send
FFUART data carrier detect
FFUART data set ready
FFUART ring indicator
FFUART transmit data
FFUART data terminal ready
FFUART request to send
BTUART receive data
BTUART transmit data
BTUART clear to send
BTUART request to send
IrDA receive data
IrDA transmit data
CF card nPOE
CF card nPWE
CF card nPIOR
CF card nPIOW
CF card nPCE1
CF card nPCE2
CF card pSKTSEL
CF card nPREG
CF card nPWAIT
CF card nIOIS16
LCD data pin 0
LCD data pin 1
LCD data pin 2
LCD data pin 3
s Guide
3-11
Programming Guide
GP62
GP63
GP64
GP65
GP66
GP67
GP68
GP69
GP70
GP71
GP72
GP73
GP74
GP75
GP76
GP77
GP78
GP79
GP80
XS_LDD4
XS_LDD5
XS_LDD6
XS_LDD7
XS_LDD8
XS_LDD9
XS_LDD10
XS_LDD11
XS_LDD12
XS_LDD13
XS_LDD14
XS_LDD15
XS_L_FCLK
XS_L_LCLK
XS_L_PCLK
XS_L_BIAS
XS_nCS2
XS_nCS3
XS_nCS4
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
AltF2
Table 3- 17
3.4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD data pin 4
LCD data pin 5
LCD data pin 6
LCD data pin 7
LCD data pin 8
LCD data pin 9
LCD data pin 10
LCD data pin 11
LCD data pin 12
LCD data pin 13
LCD data pin 14
LCD data pin 15
LCD fame clock
LCD line clock
LCD pixel clock
LCD AC Bias Drive
PX250 GPIO Map
Programming Flash Memory
This section describes how to reprogram Flash memory to update its code or adapt it for custom use.
3.4.1
Obtaining Required Software and Files
In order to erasing or programming the Flash memory of the Sitsang / PXA255 Evaluation Platform
user can use JFlash software and additional files, which are included in the Sitsang / PXA255
Evaluation Platform kit.
JFlash software uses the JFlash cable that comes with the Sitsang / PXA255 Evaluation Platform kit
and runs under Windows* NT or Windows* 2000. The “giveio.sys”device driver also needs to be
installed on the host computer.
3.4.2 Install JFlash
JFlash can run on Windows* 98, Windows* NT, Windows* 2000 and Windows* XP.
3.4.2.1 Install JFlash for Windows* 98
The JFlash can be directly used on Windows* 98. Just copy the exe file to the hard disk.
3.4.2.2 Installing JFlash for Windows* NT, Windows* 2000, Windows* XP
1.
2.
Log in to the host system with Administrator privilege.
Obtain the JFlash software file as indicated in Section 3.4.1 and unzip it to a new folder
3. Open a command prompt window and change the directory to the newly created folder.
4. Copy the “giveio.sys”file in this folder to “%systemroot%\system32\drivers”.
5. Use the “instdrv.exe”utility to install the driver. Specify the driver name and the full path
name to the “giveio.sys”file as shown:
C:\JFlash>instdrv giveio c:\winnt\system32\drivers\giveio.sys
The system should respond with:
CreateService SUCCESS
StartService SUCCESS
CreateFile SUCCESS
s Guide
3-12
Programming Guide
Note: Occasionally, JFlash may indicate that a giveio device driver is not available. For Windows*
NT: Restart giveio by using the Control Panel\Devices icon. For Windows* 2000 and XP, the driver
must be uninstalled and reinstalled by using the following commands:
C:\JFlash>instdrv giveio remove
C:\JFlash>instdrv giveio c:\winnt\system32\drivers\giveio.sys
3.4.3 Connecting the JFlash Cable
Connect the JFlash cable with the following steps:
1. Shut down the host system and the Sitsang / PXA255 Evaluation Platform.
2. Connect one end of the JFlash cable to the host system’s parallel port and the other end to the
J17 header on the Sitsang / PXA255 Evaluation Platform. See Figure 2- 1 for the location of
J17.
3. For erasing or reprogramming flash, only parallel port to J17 Connection is required. If user
wants to display any debug information on HyperTerminal, the 9-pin connector on the JTAG
cable must be connected to the host system’s series port.
4. Turn on the host system and the Sitsang / PXA255 Evaluation Platform.
Caution: The J17 is very fragile. Make sure the 2 mounting holes are soldered stably. When plug in
or out, make sure the ear on the cable connector is full pressed down. Please use it very carefully.
3.4.4 Using the JFlash Software
Figure 3- 2
JFlash Interface
Start the JFlash software and use it with the following steps:
1. Start JFlash. The JFlash interface looked like Figure 3- 2
2. Select an operation among “Erase only”, “Erase and program”and “Erase, Program and
Verify”
s Guide
3-13
Programming Guide
3.
4.
5.
6.
7.
8.
9.
Select the start block. It means which block the operation will be start from. For more
information about the flash block, refer to the Flash chip datasheet. If user wants the image
executed automatically after system is powered on, the start block should be ‘0’.
If user choose “Erase only”, enter the Block number value. It indicates how many blocks user
wants to erase.
Click the “Open File”button to browse the binary image file user wants to program.
If user wants to download image to Flash bank 1, turn on the power of the Sitsang / PXA255
Evaluation Platform with button S2 pressed, otherwise, turn on the power directly.
Click “Action”button to start operation.
User can stop the operation by clicking ‘Abort’button
When the operation is complete, user need reset the Sitsang / PXA255 Evaluation Platform
manually.
3.4.5 Troubleshoot for JFlash
If JFlash does not work correctly, user needs to make sure:
1. J23 is in right position. Pin 1 and Pin 2 should be short.
2. The GiveIO is correctly installed
3. The JTAG Cable is full inserted
4. The battery has enough power. Normally, if the voltage of battery is less than 3.5 VDC, the
JFlash could not work.
3.5
Programming Complex Logic Device (CPLD)
The Sitsang / PXA255 Evaluation Platform has one programmable complex logic device (CPLD) that
contains control logic: U24 –XCR3384XL-7FT256.
This section describes how to reprogram the CPLDs to update their code or adapt them for customers.
3.5.1 Obtaining Required Software and Files
Programming the complex logic devices (CPLDs) requires installing additional free tools Xilinx
Webpack 4.2WP2.x version on the host computer. To obtain these tools, please refer to
www.Xilinx.com. It is not recommended that use other tools or other version to burn the CPLD code.
3.5.2 Connecting the JFlash Cable
Follow steps described in 3.4.3 to connect the JFlash cable to J17
3.5.3 Reprogramming CPLD U24
CPLD U24 contains the logic that controls the board level registers and other glue logic. It can be
reprogrammed if user wants to change the logic or add new feature. Reprogram U24 with the following
steps:
1. Make sure the right UCF file is used. A file named SitsangCPLD.ucf is used for current
design. This file tells the Webpack how to mapping the pins for CPLD. The pins having been
used in this file must not be changed. For more information, refer to Webpack user’s guide
and Sitsang / PXA255 Evaluation Platform schematic diagram
Caution: If wrong pin mapping is made, the signal confliction might damage the board.
2. Make sure the right CDF file is used. A file named SitsangCPLD.CDF is used for current
design. This file tells the Webpack how many devices in the JTAG chain and what are they.
BSD must be assigned to the first device (PXA255) in the JTAG chain. If some JTAG devices
in the expansion card need to be added into the JTAG chain, user must redefine the CDF file.
For more information, refer to Webpack user’s guide.
3. Turn on the power to the Sitsang / PXA255 Evaluation Platform.
4. Download the new Sitsangcpld.jed file to U24. For more information, refer to Webpack user’s
guide.
5. After programming is completed, turn off the Sitsang / PXA255 Evaluation Platform.
6. Exit the programmer software.
s Guide
3-14
Programming Guide
s Guide
3-15

Sitsang / PXA255 Evaluation Platform User`s Guide

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LED Full Color Digital Sign - Lichtkranten en Led Displays

UM1947 - STMicroelectronics

Can I use the document camera as a webcam for Skype (and other

Isku-FX - QIG

HD Media Players

HD Media Players

Le centraline elettroniche montate oggi su tutte le autovetture

USB 3.0 to 2.5” SATA HDD Enclosure with ISO