Industria dei semiconduttori, tecnologie, progettazione: stato attuale

Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
Ing. Michele Taliercio
CR&D - External R.& D. Program Coordinator
Crema, 14 Maggio 2001
STMicroelectronics
Industria dei semiconduttori
•Mercato
• Tecnologia
• Progettazione
• Fabbrica
•Fattore
umano
Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
Semiconductor
market cycles
beyond 2000,
long term trend
$ Billions
1000
2000 : $204B
1990 : $50B
1980 : $10B
% Growth
MARKET CAGR % :
• 15% over 40 years
• 15% over last 10 years
• 7% over last 5 years
100
75%
+37%
50%
10
25%
1
0%
-25%
19
59
19
61
19
63
19
65
19
67
19
69
19
71
19
73
19
75
19
77
19
79
19
81
19
83
19
85
19
87
19
89
19
91
19
93
19
95
19
97
19
99
20
01
20
03
20
05
20
07
0
% Growth
2000 market
Current Market
Trend Line
Source : WSTS, ST
8
NEW MARKET DRIVING FORCES
GROWING SEMICONDUCTOR CONTENT IN ELECTRONIC EQUIPMENT
1965 : 2%
•Main Frame
•Defense
1975 : 4%
1985 : 7%
•Mid-frame
•Industrial
1995 : 20%
•PC Motherboard
•Communication
Infrastructure
Productivity
•Portability
•Connectivity
Corporation
Productivity
Commodities
Bipolar
2"
12"
$204B
Mem, Micro, Asic
Cmos
4"
$4B
2005 : 25%
6"
8"
Individual
Productivity
System-on-chip
Cmos, Mixed Power
$144B
$25B
$1.5B
1965
15%
1975
1985
1995
$400B
in
2005
16%
2005
2010
ELECTRONICS IN THE CAR
Drive assistance
Weather
Manual on line
DRIVER
INFORMATION
SYSTEM
GPS
Messaging
Web traffic Camera
Rear View Camera
Climate
Power seats
Lighting
Door control
BODY
MOTOR
Internet/Games
Radio/phone
TV/DVD
ENTERTAINMENT
DVD changer
SAFETY
Emergency call
the Car is connected to the World
Engine
Transmission
Regulator
ABS
ASR
AirBag
Power Steering
2010
Electronics on individual
Permanent portable electronics :
•communication (UMTS, …)
•leisure (games, music, video, …)
•work (data processing, …)
•health monitoring
+ Private data
•identification
•mobility tools (GPS, …)
•…
Picture : Siemens
2010
Generalized e-commerce
• Home purchases
• Street purchase
• Office purchase
• Mobile purchase
Source : Siemens
Paying by mobile phone, by calling the
number of the machine
The development of microelectronics is at the
very heart of economic development
Research
Banking systems
Government action
Services
Leisure
Computers
Medical systems
Microelectronics
Communications
Education
Electronics
Transportation
Industry
Environment
Size and price reduction
for electronic functions
2000
100$
Voice
recognition
Communication
protocol
Image
compression
Processing
power
2005
10 $
Voice
recognition
Image
compression
Communication
protocol
Processing
power
2010
1$
Economic Impact - Value Added
An Industry Built On Sand
•
•
•
•
•
•
•
106 Value
Added
Chain
Sand … <$1/kg
Polysilicon … $50/kg
200mm Prime Wafer … $1,400/kg
200mm Processed Wafer … $25,000/kg
Packaged Integrated Circuit … $100.000/kg
Generating End Equipment Worth … $500,000/kg
With A Street Value Of More Than … $1,000,000/kg
That’s What Makes Microelectronics So Important
MEDEA Forum ’99
Slide 8
Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
History
1897
1907
1948
1958
1962
1970
1971
Discovery of the electron (J. Thomson)
First termoionic valve (L. De Forest)
First transistor (W. Shockley, J. Bardeen, W. Brattain)
Integrated circuit
MOS transistor
1 Kb DRAM memory
4 bit microprocessor
...
80s
CMOS convergence
...
1993
1995
1997
1999
Central R&D
32 bit microprocessor
64 Mb DRAM
(16 Mb production)
256 Mb DRAM
(64 Mb production)
1 Gb DRAM
(256 Mb production)
Genova, November 10th, 2000

CMOS Integration Trend: Moore’s Law
Transistors /chip
10G
4 Gb
1 Gb
1G
256 Mb
Memory
(DRAM)
100M
Power 4
64 Mb
16 Mb
10M
P III®
4 Mb
P II®
Pentium®
1 Mb
1M
80386
256 Kb
64 Kb
100K
16 Kb
4 Kb
10K
8080
4004
1K
1970
1975
8086
8085
1980
68020
80286
68000
1985
80486,680
Microprocessor
1990
1995
2000
Central R&D
R&D - Jan 2000
COMPANY CONFIDENTIAL
J.Monnier
2005

ITRS Roadmap Potential Acceleration
500
95
97
250
(DRAM Half-Pitch)
05
08
11
1994 SIA
350
Minimum Feature Size (nm)
02
99
1997 SIA
180
1998 / 1999 ITRS
130
100
ISMT Litho
2000 Plan
70
50
Area for Future
Acceleration
35
25
95
97
99
02
05
08
11
ST 8/31/00 GF 5
Index [log]
≡ 1Tbit
10 000
Complessità
(bit-volume)
x 4000
1000
1,20 $ / Mbit
100
≡ 22cm²
10
Dimensioni del chip
x8
1
DRAM Prezzo/Mbit x 1/200
≡ 0,66cts/Mbit
0,1
1996
1999
2002
2005
2008
2011
2014
18 ans
256Mbit
1Gbit
4Gbit
16Gbit
64Gbit
256Gbit
1Tbit
250
180
130
100
70
50
35
Complessità in bit
Geometrie in nm
Fonte: ITRS, MEDEA
The Optical Lithography perspective
Determining the limits of today state of the art photolithography
1999
180 nm
2001
150 nm
2003
130 nm
2006
100 nm
2009
70 nm
2012
50 nm
MOS &
Interconnect
SK
SK
WR
WR
HWR
BH
Contact
SK
WR
HWR
HWR
BH
BH
Solutions
Known
Source: SEMATECH
Work
Required
Hard Work
Required
Black
Hole
The Sub Wavelength Gap
Lithography Wavelength
Silicon Feature Size
Copyright  2000 Numerical Technologies, Inc.
08/08/2000 10:12 AM PAGpr600 GG 3
Interconnect Challenges
As technology scales, wires, not devices, dominate the delay, power and
size of integrated circuits
Interconnect trends
Technology generation (nm)
metal levels (number)
max interconnect length (Km)
180
6-7
1.7
130
7
3.3
100
7-8
5.0
Copper, instead of Al, and low K dielectric
Below 100nm not known solutions to meet performance requirements
Design and layout solutions managing signal delay on a local scale are
needed
Central R&D
Genova, November 10th, 2000

VLSI Process Evolution
2 Year acceleration of technology nodes :
70 nm for DRAM and 45 nm for MPU in 2008 (ITRS)
Lithography reaching optical limits
New front-end / back-end materials needed
Interconnect challenge below 100 nm
Defect control: exponentially growing difficulty
Technology modeling and new simulation tools
Central R&D
Genova, November 10th, 2000

VLSI Process Evolution
Major non incremental changes :
SiGe introduction
1999
Copper replacing Aluminum
2000
300 mm transition
2001
SiO2 evolving to low K dielectric
2002
High K deposited gate dielectric
2003
Gate electrode poly replacement
2007
Non-optical lithography intercept
2007
Central R&D
Genova, November 10th, 2000

DIFFERENTIATED PROCESS
V ARIANTS BY APPLICATION
CMOS
CMOS Derivatives
Derivatives
Analog
! Tuner(Set-Top Box)
BICMOS
RF(cellular phone)
! Fiber Optic IC
!
RFCMOS
! Bluetooth
HFCMOS
! Power Management
(Cellular phone)
Imager
! Web Cam
SRAM/DRAM
! PC peripherals
CMOS CORE
PROCESS
DIFFERENTIATED PROCESS
V ARIANTS BY APPLICATION
Non
Non Volatile
Volatile Memories
Memories (NVM)
(NVM) derivatives
derivatives
Multilevel Flash embedded
! MP3
Flash embedded
! Automotive peripherals
EEPROM
embedded
! Smartcard
OTP/EPROM embedded
! GPS
CMOS
CMOS NVM
NVM
CORE
CORE PROCESS
PROCESS
Transistor, a silicon perspective
M1 : W
MOS
STI
1 µm
MOS poly gate length = 0.25 µm, Shallow Trench Isolation
Metal 1 and contact

Metal1,
a
silicon
perspective
CMOS 0.25 µm, Shallow Trench Isolation, M1 :
Metal1

MOS & inteconnections, silicon perspective
M6 : Al
Via5 : Al
M5 : Al
Via4 : Al
M4 : Al
Via3 : W
M3 : Al
Via2 : W
M2 : Al
Via1 : W
M1 : W
Contact : W
CMOS 0.25 µm, STI, 5 Metal Layer with CMP, M6 for bump

Interconnect Delay versus Dielectric K
for Al and Cu
Normalized Delay
1.2
1.0
0.8
Al
Cu
0.6
0.4
0.2
0.0
0.5
1.0
1.5
2.0
2.5
Dielectric K
3.0
3.5
4.0

Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
Technology platform for System-On-A-Chip
Concurrent Engineering
Process & options
development
Pilot line
Production
UNICAD
tools & methods
Cores : µP, DSP,
RAM, ROM,...
Technology
System prototype
Platform
HW - SW codesign
& IP reuse
Central R&D
R&D - Jan 2000
Early access for customers
to new prototypes
Time to Market & flexibility
COMPANY CONFIDENTIAL
J.Monnier

Complex VLSI : Challenges
Manage the Complexity
System-on-chip design
Design Reuse
HW/SW Co-design
Testing
Millions of Gates
System
on a
Chip
< 0.18 µm Geometries
Manage the
Performance
Critical dimensions
Power
Physical Design
Reliability
Central R&D
R&D - Jan 2000
COMPANY CONFIDENTIAL
J.Monnier

SOC AT THE HEART OF
CONFLICTING TRENDS
Process roadmap
acceleration
Consumerization
of electronic devices
Link
ST20
FEI
Dolby
AC3
Denc
Time-to-market
MPEG2
Video
2 x 3 DAC
Deep sub micron effects
crosstalk
electro migration
wire delays
mask costs (OPC, PSM)
Complex systems
uCs, DSPs HW/SW
SW protocol stacks
RTOS
Digital/Analog IPs
On-Chip busses
ACCELERATION OF TIME
Years
20
18
16
14
12
10
8
6
4
2
0
B&W TV
TIME TO 10
MILLION
UNITS
Color TV
VCR
PC
GSM
STB
DVD
1950 1960 1970 1980 1990 2000 2010
In 2010, instant 10 Million Units volumes will be required
SoC Implementation Platform
Cell Libraries
IP Blocks
Link
Link
ST20
Dolby
AC3
Design Tools
Denc
FEI
MPEG2
Video
Data
Management
2 x 3 DAC
Flows
Kits &
Methods
Central R&D
R&D - Jan 2000
COMPANY CONFIDENTIAL
J.Monnier

THE DESIGN PRO D UCTIVITY GAP
100000
1000
10000
CAGR 58%
100
1000
10
100
1
10
CAGR 21%
0.1
1
0.01
0.1
0.001
0.01
1981
1985
1983
Source ITRS roadmap 1999
1989
1987
1993
1991
1997
1995
2001
1999
2005
2003
2009
2007
Productivity (K)Trans./Staff-Mo.
Logic Transistors per Chip (M)
10000
Process / Design Gap
Design
Complexity
Process
Capability
System Level
Entry
(tr. count
linear)
HW-SW
Methodologies
+ 60% / year
IP Reuse
RTL-to-Layout
Flow
+ 20% / year
Analog &
Full-Custom
Design
Year
94
95
96
97
98
99
2000
Source : ST
Central R&D
R&D - Jan 2000
COMPANY CONFIDENTIAL
J.Monnier

From System Level down to Silicon, the needs
Complement the rich, heterogeneous process technology
offer with tools/methods supporting it at architecture and
system design levels
System Level
Entry
DSP algorithms, Protocols, Control, Real-time, GUI
Executable specifications, system validation
DO THE RIGHT THING
HW-SW
Methodologies
Processors, memories, logic, datapaths, analog, RF, A/D
Virtual prototype, Architecture exploration
HW/SW co-verification (co-simulation, co-emulation)
High performance S/W compilation
DO THE THING RIGHT, FAST
RTL-to-layout
Flow
Process
capabilities
Logic, analog, DRAM, SRAM, Flash, High-speed, Power
DO IT IN ON A SINGLE CHIP!
CO NCLUSION :DEEP SUB MICRO N
SOC DESIGN PLATFORM S
Application
Application
Sensors
DRAM
DSP
CORE
CLOCK
GEN
Fast
Fast Prototyping
Prototyping
System-Level
System-Level platform
platform
J
T
A
G
I/O
(serial)
STBUS
RAM
RF
ROM
Logic
eFPGA
SOC core-std. CMOS logic
(Bluetooth, PicoRadio)
SOC
SOC Process
Process
U
A
R
T
Flash
SOC
SOC Design
Design Platform
Platform
Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
I Prodotti
2001
1994
1980
0.5 µm
1.5 M tr/cm2
3.5 µm
0.15 M tr/cm2 3 ML / 3.3 V
200 mm
1 ML / 5 V
100 mm
0.15 µm
15 M tr/cm2
7 ML / 1.5 V
300 mm
( start of prototyping)
Central R&D
R&D - Jan 2000
COMPANY CONFIDENTIAL
J.Monnier

Evolution of Design Methodology
CD's (nm)
250
INTERCONNECT
180
POWER
130
100
70
50
RELIABILITY
97
Standard cells
RC for Clocks
98
99
Dig. libraries
RC for all nets
Signal isolation
00
01
Block reuse
Leakage
Crosstalk
FlipChip
02
03
RLC parasitics
Block protocols
Package simul.
Power solution
New analog des.
New tools & methodology
Increased design complexity
10/05/01
04
05
Appli. specif. platform
Combined P&R/synth.
New device models
Gate current
Transmission line eff.
Soft errors
Current switch
Substrate coupling
06
07
Years
Block communication
Signal skew
New faults models
Signal integrity
Local thermal variation
Interco. skin effects
Source barrier effects
Quantum effects
New BIST
...
STPC industrial
PC-ON-CHIP
System On Chip
X86 Core
TFT controller
64-bit Graphics Engine
64-bit Memory controller
PCMCIA (Cardbus)
PCI & ISA controller
Keyboard & Mouse controller
Serial & parallel port controller
...
HCMOS6 - 5L
140 mm²
2.5 M transistors

Set-top box
for DXX
(STi5500)
Link
ST20-TP2
(design DPG & PPG)
MPEG2 A/V : 1.3 M tr.
ST20-TP2 : 2.0 M tr
Link, encoder
& DACs
: 0.7 M tr.
MPEG2
Audio
MPEG2 Video
Encoder
RGB YUV
process HCMOS6
CMOS 0.35 µm, 5 ML
4.0 M transistors
96 mm2

ST10
HDD controller
with Embedded DRAM
(Design DPG)
1 Mbit DRAM
HCMOS6 :
0.35 µm, 5 ML
ST10 microprocessor
& 1 Mb DRAM
1.8 M transistors
49 mm2

DSP952 : core, memories & peripherals
SPS2
SPS2 SPS2
program
SPS2
SPS2
data
CORE DPR2
program
16 bit fixed point DSP :
program memory : 32 kWord
data memory : 16 kword
cycle time : 10 nS
HCMOS7 : 0.25 µm, 5 ML
total area : 27 mm2
core area : 1 mm2
PLL
SPS2
peripherals

ST10F269 - 16 bit µC with 2 Mbit Flash
0.35 µm, 5 metal levels, 48 mm2
M5
M4
M3
M2
M1
M3
M2
M1
Array interconnection
scheme
Logic
interconnection
scheme
1.72µm²
Flash Cell
Central R&D
April 7th, 2000
64Mbit Multilevel Flash Memory
Technology: 0.18um CMOS
triple well
double poly
triple metal
Multilevel Concept: 2bit/cell
"11"
"10" "01" "00"
VRead
Central R&D - Non Volatile Memory Process Development
4 storage levels
64Mbit = 32Mcells
Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
ST – Agrate Brianza: Centro Tecnologico R2
Processi
Ø Processi di lavorazione delle fette di silicio
• Il processo richiede circa 400 operazioni e un numero
molto elevato di controlli
• Il tempo di ciclo della produzione è di circa 2 mesi
• L’ impianto lavora 24 h / giorno per 7 giorni / settimana
• Le fette finite e collaudate elettricamente vengono inviate
agli stabilimenti di assemblaggio per l’incapsulatura
plastica
Agrate Brianza - R2 :
Caratteristiche dell’ Impianto
Ø Area pulita ( clean room ) : 5600 m
2
• Ricircolo dell’aria 10 X / minuto
• Pulizia dell’aria 10000 volte quella di una camera
operatoria
• Polverosità : classe 0 (< 1 particella da 0.5 micron / m 3 )
• Temperatura controllata : 22 ° +/ - 0.1° C in litografia
• Umidità relativa : 40 – 45 %
Agrate Brianza - R2 :
Caratteristiche dell’ Impianto
Ø Prodotti chimici , gas ultrapuri e acqua deionizzata
• Rete per la distribuzione e raccolta di gas e fluidi di
processo
• Più di 20 prodotti chimici ad alta purezza controllati al
punto d’uso
• 2 edifici di servizio per la generazione di acqua
deionizzata (120 m 3 / h) e prodotti chimici
Industria dei semiconduttori,
tecnologie, progettazione:
stato attuale e sviluppi futuri
1) Il mercato
2) La tecnologia
3) La progettazione
4) La fabbrica
5) Il fattore umano
Microelectronics is a
"Global Human Challenge"
The Microelectronics Industry employs around 800
thousand people worldwide
In the assumption:
Productivity increase of 10-20% per year
Replacing turnover of around 5% per year
The industry need will be: 100 thousand people per year
60 thousand highly qualified, highly specialized
40 thousand still classified as operators, but high degree of
qualification is a must
This Human Capital availability can be the major limiting factor to
the Microelectronics growth in the year 2000’s, and primarily in
the Western world