Constraint-driven Design - The Next Step Towards Analog Design

Transcription

Constraint-driven Design The Next Step Towards Analog Design
Automation
Invited Talk
Göran Jerke
Robert Bosch GmbH, AE/EIM
Reutlingen, Germany
Email: [email protected]
1
Jens Lienig
Dresden University of Technology, IFTE
Dresden, Germany
Email: [email protected]
G. Jerke, J. Lienig; „Constraint-driven Design - The Next Step Towards Analog Design Automation“, in Proc. IEEE/ACM Int. Symp. On Physical Design (ISPD’09), pp. 75-82, 2009.
Motivation
Evolution of Analog IC Design
Verification of...
Schematic
Technology
LVS
DRC
Polygon
Pushing
1980
Schematicdriven Layout
1990
2000
Constraintdriven Design
?
Analog Design
Synthesis
2010
today
2
Contents
3
 
The verification gap
 
Current approaches for constraint consideration
 
The constraint-driven design flow
 
Impact on design algorithms and design flow
 
Open problems
 
Summary and conclusion
Contents
4
 
 
 
 
 
Open problems
 
The Verification Gap
Constraint Classification
Technology Constraints (manufacturing)
Primary Constraints
 min. wire width, spacing, overlap
Functional Constraints (circuit function)
 max. IR-drop between two net terminals, device matching, ...
Design-Methodical Constraints (design complexity)
Secondary Constraints
 Design hierarchy, routing directions, standard cells
Economic Constraints (cost, TTM)
 Chip count, development costs and chip area determine IC technology
5
Manufacturability
Technology Constraints
1
Layout Rules
2
DRC
(Meta layer)
Verification gap
Dummy errors
EDA-tools guarantee manufacturability!
6
Functionality
Functional Constraints
(Expert knowledge)
Unrepresentable
expert knowledge
1
Schematic
2
LVS
(Meta layer)
Devices,
parameters,
nets
Representable, but
non-verifiable knowledge
(schematic prosa,
symmetries, …)
EDA-tools do not (yet) guarantee circuit functionality !
7
Evolution of Analog IC Design
Verification of...
Constraints / Expert Knowledge
Schematic
Technology
Constraint
Verification
LVS
DRC
Polygon
Pushing
1980
Schematicdriven Layout
1990
2000
Constraintdriven Design
Analog Design
Synthesis
2010
today
8
Contents
9
 
 
 
 
 
Open problems
 
Current Approaches for Constraint Consideration
Constraint-Consideration during Schematic Design
Constraints as Schematic „Prosa“
+
–
10
Man. consideration of “complex” constraints
No autom. constraint verification possible
2nd Gen. Constraint Management
+
–
Constraints are part of the database
No “complex” constraints (yet)
Constraint-Consideration during Physical Design
„Atomic“ Module Approach
Characteristics:
 
 
Design Algorithms
 
+
–
–
Layout variant 1
11
Individual design objects (→ transistors,
resistors, capacitors, etc.) and constraints
are considered (semi-) automatically
Constraint assignment and management is
required
Design algorithms must “understand” all
constraints
Full flexibility for layout optimization
Missing constraints result in wrong layouts
Long run-times of layout generation tools
Layout variant 2
Constraint-Consideration during Physical Design
„Molecular“ Module Approach
Characteristics:
 
 
 
+
+
–
–
–
PCell Module 1 PCell Module 2
12
Several design objects are combined to
a hierarchical PCell module
Constraints will be fulfilled automatically
by the PCell module
High-level re-use of design knowledge
Manual consideration of any constraint
Very fast constraint-driven layout generation
Additional constraints require new PCell module
Limited freedom for design optimization
Complexity of rel. PCell verification problem: O(mn)
(m - number of parameters, n - number of variants per parameter)
Contents
13
 
 
 
 
 
Open problems
 
The Constraint-driven Design Flow
Constraint Representation
 
 
 
14
Formalize constraints!
Define all constraints
explicitly!
Account for design
style!
Simple and Complex Constraints
R(Pad->T1) < 1Ω?
R(Pad->T2) < 1Ω?
R(Pad->T3) < 1Ω?
T1
T3
Pad
T2
Simple constraint examples:
VIR(Pad->T2) < 0.1 V
Voltage class (Pad) = {50V, 80V}
15
Simple and Complex Constraints
R(Pad->T1) < 1Ω?
R(Pad->T2) < 1Ω?
R(Pad->T3) < 1Ω?
T1
T3
Pad
T2
Complex constraint example (independent constraints):
if ( net type == P&G ) then
[[Pad->T1], [Pad->T2], [Pad->T3]] must have star-shaped net topology &&
R(Pad->T1) < 1Ω && R(Pad->T2) < 1Ω && R(Pad->T3) < 1Ω !
16
Simulation
Start
Constraint
Management
Circuit Design
Floorplanning
Device Generation
Placement
Design
Data
Routing
Compaction
Verification
Constraint
Data
Constraint
Derivation
Constraint
Templates
Constraint
Transformation
Transform.
Models
Constraint
Sensitivity
Analysis (CSA)
Constraint
Verification
Manufacturing
Test
17
Verification
Rules
Constraint Management (Data Consistency)
Today:
Separate design and
constraint databases
DO1
C1
DO1
DO2
DO2
C1
V1.0
DO1
Future
Design
Data
–
Cy
Constraint
Data
Difficult design and constraint data management
(data consistency, data versioning)
- Constraint
DO3
C1
DO2
Design and
Constraint Database
DOx - Design Object
18
V2.0
Constraint Management (Propagation)
Top-Down Propagation
I1
I1
I2
I12
I21
I221
I222
I22
I223
Examples:
- Floorplanning constraints
- IR-drop constraints
19
Top-Down and
Bottom-Up Propagation
T
T
C1
I11
Bottom-Up Propagation
I11
T
I2
I12
I21
I221
I222
I1
C2
I22
I223
Examples:
- Placement constraints
- Routing blockages
I11
C3
I2
I12
I21
I221
I222
Examples:
- ESD path definition
- Net shielding
I22
I223
Constraint Derivation Methods
DO1
?
 
Expert knowledge
 
Direct derivation rules and templates
 
C1
DO2
?
 
Deduction processes
 
Cy
- Constraint
DOx - Design Object
20
 
Example:
if ( differential pair ) then
Assign matching constraint to transistor pair
Example:
Net N1 is connected to 40V IO pad &&
I1 is connected to net N1
⇒ I1 is connected to 40V IO pad
→ Assign 40V design constraints to I1
Indirect method (transformation)
Constraint Transformation
Definition: Consistent and unambiguous transformation of
high-level constraints into low-level constraints
Example: IR-Drop
21
1. Transformation of electrical constraints
into circuit-specific constraints
Max. IR-Drop [V]
2. Transformation of circuit-specific constraints
into layout-specific constraints
Max. Resistance [Ohm]
3. Assignment of layout-specific constraints
to (geometrical) design parameters
Wire length, -width
layer …
Constraint Sensitivity Analysis (CSA)
Definition: Context-dependent sensitivity and gap determination of design
parameters under consideration of one or more constraints
Coupled constraints: VIR < VIR-max; RC < (RC)max; MTTF > MTTFmax
R = ρConductor ⋅

 h
w

C = ε 0 ⋅ ε r ⋅ l ⋅ 1.15 ⋅
+ 2.80 ⋅ 
d ox

 d ox
€



0.222


 w ⋅ h n
Ea
MTTF = A ⋅ 

 ⋅ exp
 i 
k
⋅
T
−
ΔT
(
)


0
VIR = i ⋅ R
€
€
22
x = f(T0-ΔT)?
l
⋅ (1+ TK1 ⋅ (T0 − ΔT ))
w⋅h



w?
T0
l
h
dox
Isoline
Constraint Sensitivity Analysis (CSA)
VIR
Possible constraint violation !
Sensitivity of w and ΔT with respect to VIR
VIR-max
Sensitivity of w with respect to VIR
ΔT > T1 = const.
ΔT = T1 = const.
ΔT < T1 = const.
w1
23
w2
w3
w
Constraint Verification
1. Constraints are not formalized
The voltage class of each well
connected to a supply line should match
the voltage range occurring at
the pad during operation!
Constraints
2.
1
Verification Rules
CV
Formalize constraints and
verification task
For all power and ground pads:
Get voltage class VPAD of pad
For all net terminals of the active net:
Get voltage class VInst of owning instance
If VInst ≠ VPAD then Return ERROR
Return SUCCESS
3.1 Define verification
requirements
4.
3.2 Specify and implement
verification routine(s)
Verify constraint fulfillment
-  Manual (4+n eyes verification)
-  Automatical verification
24
2
Constraint Verification (Example)
ESD-Verification
Netlist
Layout
Circuit
Verification
Property
Verification
1
1
2
3
DRC /
LVS
…
4
1
3
5
Symmetry
Verification
1
4
7
8
IR-drop
Verification
4
1
Sub-circuit recognition
5
Layout polygon extraction
2
Circuit simulation
6
EOS reliability calculation
3
Instance property retrieval
7
Layout topology recognition
4
Terminal current retrieval
8
Resistance calculation
5
8
Reliability
Verification
4
5
Combine capabilities of several tools to define
and perform verification tasks !
25
6
…
Constraint-Engineering
System (CES)
Tool A
Functionality:
A1
A2
A3
…
Constraint
Solver
An
TIKX
TIKA
CLP-based
Logic Core &
Constraint
Solver
Constraint data
Design data
Tool functionality
TIKB
TIKY
Tool B
26
B2
B3
Constraint
Templates
Constraint
Transformation
Transform.
Models
Constraint
Sensitivity
Analysis (CSA)
Constraint
Verification
Functionality:
B1
Constraint
Derivation
…
Bm
CLP – Constraint Logic Programming
TIK – Tool Integration Kit
Verification
Rules
Constraint Verification
 
Example:
Check all pin-to-pin resistances RC,Pn in star-shaped nets: RC,Pn ≤ Rmax !
Layout-Extraction
TIK
Constraint
TopologyExtraction
TIK
valStarRes(NetID, PinID, Rmax) :R>Rmax, net(_, NetID), netLayout(NetID, L),
topologyClass(_, L, star(C)),
netPin(NetID, PinID), coordinate(PinID, P),
resistance(_, L, C, P, R).
Constraint
Rule
File
Resistance-Extraction
TIK
CES query for Rmax = 5 Ω:
valStarRes(N, P, 5).
Result: List of all violating combinations of nets and terminals
27
Contents
28
 
 
 
 
 
Open problems
 
Impact on Design Algorithms and Design Flow
Design Steps
ting
Rou
Compaction
Future
Degree of Design Freedom
Physical Realization
n
ratio
ene
Dev
ice G
Floorplan
ning
Degree of Design Freedom
Iterations
Physical Realization
Continuous Design Flow [5]
Sequential Design Flow
Floorplanning
Compaction
Time
29
Time
Impact on Design Algorithms and Design Flow
High-Level Design Algorithms
Design Problem
Strategy A:
1. Placement  Alg.1
2. Glob. Routing  Alg.2
3. Det. Routing  Alg.6
High-Level
Design Algorithm
Algorithm 1
Algorithm 2
Algorithm 3
IFC
IFC
IFC
…
Algorithm n
Strategy B:
1. Route Planning  Alg.4
2. Placement  Alg.9
3. Det. Routing  Alg.6
IFC
Design and
Constraint Database
30
Contents
31
 
 
 
 
 
Open problems
 
Open Problems (Long Term)
 
Constraint solver:
 
 
Constraint methods:
 
 
 
Scalability of constraint sensitivity analysis (CSA) must be improved
Approaches for automatic constraint rule optimization should be developed
High-level design algorithms:
 
 
32
Consideration of constraints with statistical boundaries is required
Improvement of concepts for abstraction of design and verification algorithms
Development of strategies for high-level design task partitioning (with CSA)
Summary and Conclusion
33
 
Presentation covered (1) today’s verification gap, (2) current and future
approaches for constraint-driven design and (3) open problems
 
Constraint-driven design is a major and a necessary step towards a
fully-automated analog design synthesis
 
Constraint verification reduces the existing verification gap in A/MS
designs
 
The comprehensive and automatic constraint consideration is a
potentially disruptive technology with a very strong impact on the
design process!
 
Constraint-driven X-design  interdisciplinary field with a tremendous
potential and many challenging problems
Thank You!
34
Bibliography
[1] J. Jaffar et al.: “The CLP(R) language and system: an overview” in Proc. Compcon Spring
1991, Digest of Papers, pp. 376-381, 1991.
[2] E. Malavasi, E. Charbon et al.: “Automation of IC Layout with Analog Constraints”, in IEEE
Trans. on CAD of Integrated Circuits, Vol. 15, No. 8, 1996.
[3] E. Malavasi, E. Charbon: “Constraint Transformation for IC Physical Design”, in IEEE
Trans. on Semiconductor Manufacturing, Vol. 12, No. 4, 1999.
[4] J. Freuer, G. Jerke, J. Gerlach, W. Nebel: “On the Verification of High-Order Constraint
Compliance in IC Design”, in Proc. Design, Automation and Test in Europe, DATE '08,
pp. 26 – 31, 2008.
[5] Scheible, Jürgen: “Constraint-driven Design – Eine Wegskizze zum Designflow der
nächsten Generation”, in Proc. Beiträge der 10. GMM/ITG-Fachtagung, Analog’08,
Siegen, Germany, 2008.
[6] G.Jerke, J. Lienig: “Constraint-Driven Design – The Next Step Towards Analog Design
Automation”, in Proc. International Symposium on Physical Design, ISPD’09, 2009.
[7] Sakurai T., Tamaru, K.: “Simple Formulas for 2D and 3D capacitances”, in IEEE Trans.
Electron. Dev., Vol. ED30, No.2, pp. 183-185, 1983.
35

Constraint-driven Design - The Next Step Towards Analog Design

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