Zilog Z80-CTC - 1979 - Smithsonian

PRODUCT EVA LUATION
OF TH E
ZILOG Z80-C TC
12 '
-
PRODUCT EVALUATION 12<>
OF THE ZILOG Z80-CTC M~ A,J~ CLL}·JG:.A0
June 12, 1979
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Prepared by INTEGRATED CIRCUIT ENGINEERING CORPORATION 6710 EAST CAMELBACK ROAD SUITE 211 SCOTTSDALE, ARIZO NA 85251 1037 9- K I
SUMMARY
The purpose of t his anal ysi s is to gain fi r st - hand knowledge on
physical and el ectri cal structuring of thi s circ uit.
This permits
i dent i fica tion of the strong and weak features of th i s device and
is olat ion of areas requiring in-depth analysis.
In th is way, a basis
will be pro vi ded for predicting circuit reliability an d establis'ling a
background for future analysis.
The ZSO-Co un t er Ti mer Ci rc uit (CTC) prov ides count i ng and ti mi ng fu nc­
ti ons fo r mic rocomputers based on the Z80-CPU.
The four independent
channel s are programmable to operate as either a co unte r or a timer.
Th is ci rcuit requires a single 5-volt supply and a single-phase 5-volt
cloc k.
The Z80-CTC util izes N-channel sil icon-gate depletion- l oad r-1OS
techn ology and is packaged in a 28-pin DIP.
A priority interru pt
st r ucture t ha t is dedicated to the Z80-CPU provides for automatic
i nterru pt vector ing without external logic.
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TABLE OF CONTENTS
PAGE SUMf·tARY LIST OF FIGURES
iii LIST OF TAB LES
v
INTRODUCTION
1
SECTIO N
SECTIO N II
­
EXTERNAL PACKAGE ANAL YSI S
2
INTERNAL PACKAGE ANALYSIS
8
SECTI ON I Ir -
PROCESSING AND ELECTRICAL CHARACTERISTI CS
16 SECTION IV
CI RCUIT AND LOGI C ANAL YSI S
18 SECTI ON V
SPECIFICATION REVIEW
48 SECT IO N VI
CONC LUS IONS
50
SeCTI ON V!) -
RECOMMENDA TIONS
51 APPEND IX
-
ZILOG Z80-CTC DATA SHEETS
52 ii
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LIST OF FIGURES PAGE I
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FI GURE 1- 1.
ZI LOG Z80-CTC PACKAGE PHOTOGRAPHS
3
FIGURE 1-2.
ZI LOG ZBo-eTC X-RAY PHOTOGRAPHS
5
FIGURE 2- 1.
ZI LO G ZSO-CTC
FIGURE 2-2.
ZILOG ZSO-CTC DIE CAVITY AREA
11 FI GU RE 2-3.
ZI LOG Z80-CTC SAW AND 8REAK DIE SEPARATION
11 FI GURE 2-4.
ZILOG ZSO- CTC VOID UNDER DIE OF SAMPLE 2K
12 FI GUR E 2-5.
ZILOG ZSO-CTC WIRE GOND
12 FI GURE 2- 6.
ZILOG ZSO-CTC METAL STEP COVERAGE
15 FI GUR E 4-1.
ZI LOG ZBO-CTC DIE PARTITIONING
19 FI GURE 4-2 .
ZIL OG Z80-e TC INTERRUPT ENAGLE OUTPUT ~mOLE
DIE PHOTO GRAPH
9
(1E O) AND TYPE 0 FLIP FLOP
21 FIGURE 4-3 .
ZILOG Z80-CTC MACHINE CYCLE ONE (Mf) INMPUT.
22 FIG URE 4- 4.
ZIL OG Z80-CTC READ CYCLE STATUS (RD) INPUT WITH READ CYC LE CIRCUITRY
24 FIGUR E 4- 5A. ZIlOG Z80-CTC WRITE CYCLE CIRCUITRY
25 FI GURE 4- 5B. ZIl OG Z80-CTC I'JRITE CYCLE CIRCUITRY
26 FIGURE 4-6.
29 ZIlOG ZBO - CTC BIDRECTIONAL DATA BUS (06)
FIGURE 4-7A. lI lO G ZSO- CTC RETURN FROM INTERRUPT INSTRUCTI ON DECODE
30 FIGUR E 4-7B. ZIl OG Z80-CTC RETURN FROM INTERRUPT INSTRUCTION DECODE
31 iii
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lIST OF FIGURES (CONTO)
PAGE
FI GURE 4-S .
ZIOlOG-CTC lE I INPUT AND INT, lEO OUTPUTS WITH PRIORITY INTERRUPT. FIGURE 4-9.
ZIlOG ZSO-CTC READ/\1RITE CIRC UITRY 34 (CHANNEL 0). FI GU RE 4-10A.
ZIlOG ZBO-CTC CHA NNEL CONTROL REG ISTER 35 (CHANNEL 0).
FIGURE 4-10B.
ZIlOG ZSO-CTC CHAN NEL CONTROL REGI STER
36 (C HA NNEL 0).
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FIGURE 4-11­
ZIlOG ZSO-CTC EXTERNAL CLOCK/TI MER TRIGGER
(C lK/TGR
~)
INP UT.
38 FIGURE 4- 12.
ZllOG ZSO-CTC PRE SCALER CEll (B IT 6)
FIGUR E 4-13.
ZIlOG ZBO-CTC
TIt~E
42 ZI lOG ZSO-CTC CHANNEL COUNTER/T IMER
CO NTROL.
FIGURE 4- 16 .
44 ZIlOG ZSO-C TC ZERO COUNT/T IMEOUT (lC/TO 1)
AND CHANNEL INTERRUPT. I
41 l ILOG ZBO -CTC PRESCALE R AND DOWN COUNTER
CONF IGURAT ION.
FIGURE 4-15.
40 CONSTANT REG ISTER AND
DOW N COU NTER CEll (BIT 6).
FIGURE 4- 14.
32 iv 46 ~ LIST OF TAB LE S
~ PAGE
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TABLE 1-I.
ZILOG ZSO-CTC PACKAGE SPECIF ICATI ONS
4
TABLE 1-2.
GAS ANALYSIS OF THE Z80-CTC SAMP LE 2K
7
TABLE 2-1.
ZI LOG ZSO-CTC DIE SPEC IFI CAT IONS
10
TABLE 3-1.
PO STU LAT ED PROCESS SEQUENCE FO R THE ZI LO G Z80-eTC.
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INTRODUCTI ON
To ev al ua t e the Zi log Z80 Co unt er-Timer-Ci r cuit (CTC) a total of four
part s were used.
senta tive .
Two of these part s were receiv ed f r om a Zilog re pre­
The se were engi neering samples and were not used for any
el ectri cal t est i ng.
The remainin g two devic es were ordered f rom a
local dis tr ibutor and re ceived within two weeks .
Thes e MOS devi ces
were recei ved inserted in conduct ive foam and boxed f or static
discharge protect ion.
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The eng i neering samples received from t he Zil og representative had no
package markings.
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The devices rec eived from the lo cal distr ibutor were
marked with the Zi log logo, part number (ZaO-e TC), dat e code (7714).
and l ot co ntrol number (08201).
The devi ces .Jere packaged in 28 -pin
cerami c dual-in- 1ine packages ha vi ng st andard operat ing ran ges of 5V +
5% and O· C to 70°C.
The ce ramic packa ge and st andard operating ran ge
were the only opt i ons available at the time the dev ices we r e ordered .
The two devices purcha sed fr om a local distributor were used for the
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physical anal ysis including X- ray. leak tests, gas ana lysis, package
examinati on, internal visual and SEM in spect ion.
The remain ing
mec hanic al sampl es were used only for circ uit t ra cing .
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SECT ION I - EX TERNAL PACKAGE ANALYSIS
1. 1 - Vi sual
The Z80-CTCs were packaged in 28-pin ceramic DIP s wi t h Kovar gold- pla t­ ed lids whic h I,ere soldered on to provide a hermetic seal.
plated leads were side brazed to the package.
Kovar gol d­
Physical measurement s
I,ere tak en and compared with the package outl i ne in the dat a sheet.
All meas ure ment s were within the tolera nc es stated.
Tabl e 1-1 is a
comprehens ive l isting of the external phy si cal measurement s.
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Photographs of t he Zilog Z80-CTC package (s ample 2K ) are provided in
Fi gure 1-1.
1. 2 - X-Ray
Samp le 2K was X- r ayed, and the results are shown in Figure 1-2.
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One
edge of the die is unsupported, with no eutect ic ma terial vi sible .
the wi re bond i ng operation t akes pl ace above th e unsup ported edge of
the s i licon, then microcracks can result.
to red as a reli ability problem.
This haza rd should be moni ­
The X-ray shows that the other three
edges are adequately supported and have no exces sive bui ld-up of the
eutect ic materi al.
2
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30
20
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10 THS
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10 THS
Mil LlMETE RS
10
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20
30
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II 1 1 I \1 ·1 I I II I I I
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10THS
FIGUR E 1·1 . ZILOG Z80·CTC PACKAGE PHOTOGRAPHS.
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TABLE 1-1
ZIlOG Z80-C TC PAC KAGE SPECIfI CATIONS
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PAC KAGE DIMENSIONS:
L: 1. 4"
PACKA GE MATERI AL :
Dark Cerami c
LID OIMENSIONS:
l : 0. 5"
LID MATERIAL :
Kovar Gold-Plated
SEAL! NG METHOD: So l dered
LEAD SPACI NG: 0.59" x 0. 08 "
LEAD MATERIAL : Kovar Gold-Plated
LEAD
oIf1ENS IONS : L: 0.13"
1-1: 0.59"
l, : 0.5"
Side Brazed
LEAD FRAME 11A TER IAL I N BONDI NG AREA: Go 1d-Pl ated
4
TH: 0.01"
W: 0. 016" TH: 0.01"
LEAD ATTACHME NT METHOD: m
TH: 0.082"
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In the lead frame area, there are virtual ly no voi ds or any spacing
problem with le ad i nterconnect.
1.3 - Leak Test and Gas Analysis
Leak t ests were performed on sample 2K per MI L-STD-883B , Method 1014. 2,
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Conditions B and C.
Dur ing both f ine and gross leak tests , the part
exhibited a l eak rate of less t han 1 x 10- 8 atm cc/sec., the test
limit.
Gas analysi s was done on sample 2K per MIL-STD-8838 Met hod 1018. 1.
The
results of t hese t ests are shown in Table 1-2.
The moisture cont ent
wa s 0.09%, which is judged to be a safe level.
The wat er vapor shoul d
be no greater than 0.5%, and ideal ly less than 0.1 %.
Gas analy sis
results would imply that these circuits wer e sea l ed i n a dry nitrogen
atmosphere.
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TABLE 1-2
GAS ANALYSIS OF THE ZSO -CTC SAMPLE 2K
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CONSTITUENT
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ARGON (Ar)
0.44
HYD RO GE N (H2)
0.57
CONCENTRATI ON (%VO L/ VOL)
98.9
NITROGEN (N2)
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WATER VAPOR (H20)
0. 09
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SECTION II - IN TERNAL PACKAGE ANA LYSIS
The lid of the Zil og Z80-CTC (sample 2K) was mechanical ly removed and
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the die cavity in spected according to the procedures pre scribed in
HIL-STO-8838, Method 2010.3, Te st Condition B.
This is not a compari­
son to MIL-STD 's but this MIL-STD provides a deta i led inspecti on proce­
dure.
Fi gure 2- 1 i s a whole di e photograph of the Z80-CTC.
A view of t he
assembled die in the cavity is seen in the SE'" pho to graph of the cavity
area in Figure 2- 2.
the cav ity.
There i s a good fit bet ween the circuit di e and
Since the bondi ng pad l ayout on the die necessitates the
use of a bondi ng wire 140 mil s l ong, this shoul d be an area of concer n.
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Long bonding wi r es can sag and eventu all y cause a clearan ce problem
between the bondi ng wire and the di e.
occur under shock conditions .
Thi s would be most likely to
As seen in Figu re 2-2, the wires are
forward bon ded, which does produce better clearance .
Workmanshi p in
the assembly ar ea is good.
2.1 - Die Separation and Mounting
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The Zi log Z80-CTC die was separated from adj ac en t die by the saw and
break me th od as shown in in Figure 2-3 .
SEM in spection of sampl e l K
disclosed no chi ps or cracks along the edge of t he die, nor crac ks
extending inward toward any acti ve ci rcuit element.
A vo id und er the
die of sample 2K i s shown in Fi gure 2-4.
This is the same sample that
wa s X- rayed and detenii i ned to be un sa fe.
Since there is a bondi ng pad
above the unsup ported silicon, the reliabili ty haza rd of microcracks
does exist.
Furt her observation in the
S[I~
reve aled no evi dence of
flaking, ba l l i ng or excessive build-up of the eutecti c material.
8
Die
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TABLE 2-1 ZILOG Z80-CTC DIE SP ECIFICATIONS
Cav Hy Si ze: 250 mil s x 250 mil s
Die Si ze:
90 mils x 135 mils
Area:
12,150 sq. mil s
Thick nes s :
Approx . 15 mi 1s
Saw and Break
Di e Separation Technique:
Di e At tach Method:
AuSi Eutect ic
Ultrason i c Wedge Bonding
Wire Bondi ng Me thod:
Wir e Bondi ng ,·tat eri al :
1. 2 mil Al um i num Wi re
Long es t Span:
140 mil s
4.3 mils x 4.3 mils
Minimum Bondi ng Pad Size:
Hi nimum Bondi ng Pad 14indow :
4. 0 mil s x 4.0 mil s
Mi ni mum Bond i ng Pad Spacing:
3. 0 mils
Min imum Spac ing Pad to Scribe:
4.0 mil s
Minimum Spac ing Pad t o Nearest Metal Line: 1.3 mi ls
Mini mum Co ntact Size:
0. 3 mils dia.
Minimum Di ffus ion Spacing:
0.25 mils
Mini mum Diff usi on \4 idth:
0.3 mi l s
Minimum Me tal Line Width:
0.25 mils
Mi nimum t4et a 1 Li ne Spac i ng:
0.4 mils
Mi nimum Polys ili con Width :
0.25 mils
Minimum Pol ys ilicon Spac ing:
0. 3 mil s
W: 0. 3 mils
Minimum Gate Size:
L: 0.25 mils
Bond Strength Test
28 Wi res
Average: 4.42 grams
High: 5 grams
Low: 3.5 grams
Di e Shear Test : Di d not shear at 2500 grams
10 Std. Dev: 0.44 grams
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BOX 55'
FIGURE 2-2. ZILOG zaO·CTC DIE CAVITY AREA.
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FIGURE 2·3. ZILOG zaO-CTC SAW AND BREAK DIE SEPARATION.
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she ar test i ng was performed on sample 1K.
The die did not shear at
2500 grams .
2.2 - Interconnection
The Zi'og ZSO-CTC was interconnected by ultrasoni c wedge bonding.
ty pical wedge bond is seen in Figure 2-5.
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was al um in um wire 1.2 mils in diameter.
the SEM and found to be adequat e.
used on th is device.
A
The interconnection material
All bonds were inspected in
The forward bonding technique was
Forward bonding provides good clearance between
th e wire and the circuit die.
Bond strength tests were done on sample 1K.
The majo rity of fail ures
were wi re breaks at the neck down point; that i s , the point at which
t he cross sect i on of the wi re is reduced due to the bonding process.
The average pull strength was 4. 42 grams.
The lowest pull strength was
3. 5 grams, wel l above the MIL- STD-SS3B Method 201 1. 2 mi nimum
req uireme nt of 2 grams for 1. 2 mil wire.
2.3 - Examination of the Die Su rface
Exami nation of the d ie surface was done on both sample 1K and 2K, first
with the gl ass i vati on intact and then with gla ss i vatio n removed .
bot h steps no anomalies were found.
All spaci ngs and l ine wi dt hs
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appeared t o
be
adequate for high yields and reliab i l i t y concerns.
An
SEM photograph of metallization step cov er age is shown in Figu r e 2-6 .
The step coverage wa s good and all contact holes we re compl etely
covered wi th metalliza t i on.
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SECTION I f I - PROCESS ING
The Zilog zaO-CTC was fabricated wi th an N-channel sil icon-gate
depletion-load MOS proce ss using local ox id ati on to isolate adjacent
diffusi on s.
Tab le 3-1 presents the postulated processing sequence.
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TABLE 3-1 POSTULATED PROCESS SEQUENCE FOR THE ZI LOG Z80-eTC STARTI NG MATERIAL:
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
STEP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
HIGH RESISTIVITY P-TYPE SUBSTRATE
GROW THIN OXIDE
DEPOSIT NITR IDE
APPL Y PHOTORESIST AND PATTERN (FOR FIELD OXIDATION)
ETCH NITRIDE
ION IMPLA NT BORON (FIELD DOPING)
GROW FIELD OXIDE
STRIP NJTR IDE AND UNDERLYING OXIDE
GROW THIN OXIDE LAYER
APP LY PHOTORESIST AND PATTERN (FOR DEPLET10N LOADS)
JON n\ PLANT
APP LY PHOTORESIST AND PATTERN (FOR BUR [ED CONTACTS)
ETCH OX IDE FOR CONTACTS
DEPOSIT POL Y
APPLY ~IO TORESIST AND PATTERN (GATES AND INTERCONNECTS)
ETCH POLY AND EXPOSED GATE OXIDE
01 rF USE r~+ (PHOSPHORO US) TO FORM THE SOURCE AND ORAIN REGIONS
DEPOSIT INTERMEDIATE OXIDE
APPLY PHOTORESIST AND PATTERN (F OR 11ETAL CONTACTS)
ETCH INTERMEDIATE OXIDE
DEPO SIT ALUMINUM
APPL Y PHOTORESIST AND PATTERN (FOR INTERCONNECT ETC . )
ETCH ALU MINUM
DEPOSIT GLASSIVATlON
APPL Y PHOTORE SIST AND PATTERN (FOR BO NDIN G PAD OPEN INGS)
ETCH GLASS IVATION
17 I
MASK 1
MASK 2
MASK 3
MASK 4
MASK 5
r1ASK 6
'-\AS K 7
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SECTION IV - CIRCUIT AND LOGIC ANALYSIS
.1 - Di e Part it ioning
The Z80 Counter-Timer-Circuit (CTC) is di vided into four independent
prog ra mmab le channels that provide counting and ti ming fun ct io ns for
t he ZBO-CPU.
chi p.
Figure 4-1 shows the channels acro ss the middle of the
The layout is general l y very compact with little was ted space.
The bidi recti anal data bus is at the top, and the inte rna l data bus runs
vert i cal ly through the interrupt vector reg ist er, interrupt co ntrol log­
ic and the cou nter/ t i mer channel s.
Data bus latches are
the internal data bus at the bottom of the ch ip.
at the end of
The four cloc k/ trigger
inputs are at the right edge with associ ated control ci rcuit ry.
The
three zero count /timeout outputs are alon g th e l eft side with t he
channel interrupt logic.
Read/Write cont r ol sur round s the RD input.
The remaini ng interr upt and control line s enter the chip alon g the bot­
tom edge.
Two channel select lines enter at the l ower right corner and
are de coded in each channel.
VSS (ground) enters the chip at the upper left corner .
There are a
few ground c ros sunders , bu t none that are co nnec ted t o out put driver
circuits .
With a total VSS metal width of 3.5 mils, th e averag e
curren t density is about 35 mA/mil.
Vee enters the chip fr om the
upper right cor ner wi t h a wide metal run exte ndi ng down the right side.
The unbuffer ed
c loc~
enters the chip from the middle of the bottom edge
and is distribut ed along both sides of the chi p.
18 · ~NINOIJ.IJ.H\t d
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4 . 2 - Read/I,rite
(IT,
Ml , IORQ, and RD Input s) .
The ci rcuit ry illustrated in Figures 4-2 through 4-5 i s part of the
in t e r nal ca ntr a l l ogic block shown in Figure I
th e ZSO- CTC product specification .
(crc
Block Diagram) of
This logic controls th e tran sfer of
da ta and co ntr ol words between the ZSO -CP U and the CTC.
Fi gu r e 4-2 ill us trates a type-D flip-fl o p th at is used th roughout the
crc
circuitry.
The st ate of the Data (D) input is t r ansferred t o the
out puts (Q and ~I on the rising edge of the Cl oc k
The Reset (RI i nput makes Q "low" and Q " high".
(el
in put s ignal .
A log i c block wi ll be used
to represent t his circ uit in the remai ni ng sch emat ics.
In some fl i p­
f lops the conn ec ti ons to the inverter form ed by t ransist ors I and 2 are
reversed, thus chang i ng the D input to a D input.
In ot her fl ip- flops
the C input is comp l e mented by reversing the two latches of the f1 i pflop.
input .
Dat a i s then tran s ferred on t he f alli ng edge of the Cloc k
(el
A schematic of a complex gate i s sho wn formed by t rans isto rs
7 thro ugh 11.
Figure 4-3 ill ustrates the use of this fl i p- f l op ( Ff l) in the Machine
Cycle 1
(MIl
i np ut.
The MI s ignal originate s in the ZBO -CP U and
indica te s that the c urrent machlne cycle is an op code fe tell cyc l e .
g
The NOR gate lat c h and output driver compose d of tra ns i s tors 6 through
17 insure that t r ans itions of
~1I
will occur vh1en Cloc k i s "lo w."
full y synchroni zes MID to the rising edge of Cl oC k.
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A
a
C
A
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FIGUR E 4·2. ZILOG ZBO·CTC INTERRUPT ENABLE OUTPUT {lEO) AND TYPE D FLIP FLOP.
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Ml
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1)-- MID -::
FF I
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SYMBOL DEFINITIONS TH E FOL LOW ING SYM BO LS AR E USED TH ROUGHOUT -I'.J .
.,
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RESET
EN H ANC EMENT MODE
TRANS ISTOR
DEPLETI ON MODE
TRANS ISTOR
<l> nJU-U­
M"NPUTP: ~~
M l~~
MID
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VSS
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FIGURE 4·3. ZI LOG ZBO·CTC MACHINE CYCLE ONE IM11INPUT.
22
Figure 4-4 i l l ustrates t he circuitry used in t ran sferr i ng data from the
eTC to t he CPU.
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The four input NOR gate formed by t rans i stors 8
through 12 det ect s a CPU re ad cycle.
The RE AD REG si gnal is "l ow"
whenever th e CPU r eads the curr ent contents of the Down Counter.
Anot her eTC to CPU data transfer occurs dur ing the int er rupt acknowl­
edg e cycl e.
The NOR gate composed of transistors 72 th r ough 76
(Ph ot ographed in Fi gure 4-5A) detects Ml and IOR Q "l ow" whe n the r e is a
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CTC int err upt active and Interrupt Enable In (jEl) is "low" .
Transistors 15 t hrough 20 enable the data bus outp ut driver s during a
read cyc l e or an i nt err upt acknowledge cyc l e.
The four i nput NOR gate composed of transistors 77 t hro ugh 81 detects a
poss ib l e i nt errup t acknoViledge cycle Vlhen Ml i s "l oVl" Vihil e !ORQ and RD are
"high".
FF2 synchroni zes this signal to the l ead i ng edge of Cl ock .
VECTOR pl aces the interrupt vector onto the in t ernal data bus .
READ
The
vector is read by the CPU only when OUT is ac t i ve .
Fig ures 4-5A and 4-5B illustrates the circuitry co ntro lli ng dat a transfers to the
eTC either f rom the CPU during a Vlrite cycle or program memory duri ng a return
I
from int err upt cycle.
23
I
I
I
w
RD
RD
6
IN TER RUPT ACKNOWLEDG E
J
iORO
I
l~
I
M"16
MlD
0
"»--77
I
D
1!1..'iOAO
­
80
<I>
00'
READ REG
J
r-
78 RO M 1 D--r----..
Ml -
I~:
rl~'"
,~ I ~
Q
I
FF2
C Q
22
READ VECTOR
I 21
~
R
RESET
FIGURE 4-4. ZILOG ZBO-CTC READ CYCLE STATUS (RO) INPUT WITH READ CYCL E
CIRCUITRY .
24
I
I
I
I
I
iOAQ
a
D
FFll
ot>
0
C
R
o C~03
23
24 MI D
AIL
2S
26 CE
lORa27
D
2B
D
FF 13
FF 12
,~
<l> ----I C
C
Q
R
RESET
~
1,02
WR ITE REG
1
R ESET
ls3
fETCH
0
0
Ro
M 1D
) - - STROB E
35
--II,
L -_ _
~
36
WRITE REG
IU"' I
4>
l 100
)o~---"l)-97
I
52
ENAB LE DB
I 99
l
CE,IORO
CE
FF11 Q
l OR a - - (
~
iN
reTCH
WR ITE REG
l
[
s--L
~
~
ST ROBE DB
EN ABL E DB
l
FIGURE 4·5A. ZILOG Z80-C TC WRITE CYCL E CIRCUITRY .
25
J
DB
I
I
I
<1>
RD,
J1.Jl.Jlr
MI l
FF30
I
~
F ETCH ~
lN
~
STROBED~
I
-" "-n~
RD
I
or
ADJ D
F F3 _
<1>
C
2
M1D
o~~
':F4_
<1>
Q
Q
C
R
R
,
RE SET
I
D
l
I 7
RESET
FIGUR E 4·58. ZI LOG ZSO·CTC WRITE CYCLE CIRCUITRY.
26
FETCH
0
I
I
Th e comb inati on of FFll and th e 5 input NOR gate (tr an sistors 23 through
28 ) detect the begi nning of a write cycle.
The outp ut of the NOR gate
is "high" only until the next ri sing edge of Clock fo ll owi ng a fai ll i ng
ed ge of lOR Q.
Data is tr ansferred to the CTC reg isters in two steps.
Data is transferred to the CTC regi sters in two steps.
I
Fi rst, external data is sa mpled by STROBE DB and transferred to the
internal data bus by IN.
The n FF 13 (photographed in Fi gure 4-7A) del ays
one ful l clock cycle and WRI TE RE G tr an sfers interna l data to the
I
I
I
I
I
I
I
I
I
register l atches.
During a return from interrupt cycl e t he eTC must decode t he RET ! ins tru ct ion.
FF 3 and tw o NOR ga tes (Transi stors 1 throug h 6) detect the
beg inn ing of an op code fet ch cycle.
FF4 delays this signal by one half
clock time and generates the internal FETCH sign al.
through 43 for m a la t ch that acc omplishes the two step data in pu t
function desc r ibed ea rl i er .
The ENIIBLE DB Sign al for ces a l og ic "one " on t he inter nal data bus
wheneve r it is not bei ng used for any data t ransfer functio n.
Transi st ors 54 th rough 64 detect al l dat a bus transfers whi l e the l atch
composed of t r ansi stors 82 thr oug h 93 (pho tographed in Fi gur e 4-7A)
ex tends the ENIIBLE DB sig nal by one half clock ti me at Lhe end of a
wr ite cycle.
27
I
Trans i st ors 33
I
4. 3
I
I
Bi d i rectional Data Bus (D7 through DO)
Bit si x of t he Z80-CTC data bus buffer is illustrated in Fi gure 4-6.
Tran s i s tors 1 through 14 form an output driver for the inte rn al data
bit D6.
The driver circ ui t is enabled on ly when da ta is tra ns f erred
from the CTC to the CPLI.
I
I
a high im pedance state.
Otherwise, OUT is "high" and the d r i ver is in
Data to be transferred to the CTC is first
sampled by transmission gate 19 when C: ock is "low".
When Cl ock is
"high", data is latched by transistors 22 through 26.
Transmission
gate 27 samp l es the latched data and transistors 29 th rough 31 dri ve
the internal data bus durin g write or fetch cycle s .
f or ce s t he in t ernal data bus to a "higl"
used for data t r ansfer s .
Transistor 32
s tate when it i s not being
Transist ors 33 through 37 (photog r aphed in
Fi gure 4-3) provide a latch for the data bus du r ing the two step data
I
o
I
I
tran s fers described in the previous section. 4.4 - In t erru pt Servicing (lE I Input, I NT and l EO Outpu t s ).
The circu it ry il l ustr ated i n Figure 4-7B decode s the RCTr instruction
us ed to re set CTC interrupts.
The output of FF5 go es "hi gh" a ft er the
fi r st byte of any two byte instruction; that is , op codes CB I6,
DDI6, ED16 Or FDI6'
If the op code is ED16 , t hen FF6
cha nges state and ED goes "low".
I
This enabl es t he c ircuit r y that
deco des the 4D16 op code (Transistors 48 through 57 ).
s ign a l wi ll go "hi gh " after the rising edge of the
wil l go "l ow" after the falling edge of FETCH.
I
I
28
RD
The RE T!
input (jN=O) and
I
D
E
I
I
o
...
06
m
I
tI
<I>
.J
~
OUT~r.
23
6
J1
F'P"I Lnb :" "
1... 1
-
-
I
~ r~'
11'
FIGURE 4·6. Z ILOG z ao-CTC BIDIRECTIONAL DATA BUS (06).
I
29
--
c=:l
..
w
o
FIGURE 4·7A. ZllOG ZSo-CTC RETURN FROM INTERRUPT INSTRUCTION DECODE.
--
I
I
g
00 1 __ r-~~
I
I
04 8
01 2
~~--~
)c>-----,
03 3
46
Q
05 9
FF5
Q
R
..
r-'
~
Q ~145
o
~
1
FF 6
Eo'6
FETCH--i
C
Q
R
IS9
RE SET
L.:
56
I
I
~ 58 I 60
04 52
05 53
50
07 5 '
Eo
­
)c>--- RETI
5S
"­
4°,6
T2 T3 TO T1 T2 ,3 T4
~
FETCH
JL---.JL
L
FF5Q
r
ED
IL
R ET I
~ FIGURE 4-7B. ZILOG Z80-CTC RETURN FROM INTERRUPT INSTRUCTION DECODE.
I
31
Interrupt En able In (lEI) and !n ': errupt Enable Out (lEO) form a system
I
I
daisy chain for interru pts in which the device closest to the CPU ha s
the hi ghes t pr iority.
Within the CTC, interrupt prio r ity is dete rmined
by chann el num ber wit h
chan i1 ~ l
zero havi ng highe st priority.
When lEI
is "hi gh", no other interrupting devices of higher prior ity in the daisy chain
are being servic ed by the CPU.
The eTC i nter rupt ci rcuitry is shown in Figure 4-8.
I
1, 2, and 3) has four outputs ind icating the channel status to the
priority inte rrupt system.
CTC .
I
I
I
Each channe l (CH0,
lEI si gnals form the da i sy chai n wi t hin the
Secti on 4.10 de scri bes the chan nel interrupt logic.
When a channel down counter reaches zero , th e CPU receive s an Interru pt
Request (I NT = 0) from one or more of the channels and send s an Int errupt
Acknowl edge signal (MI + IORQ = 0).
The int err upt pendi ng (I P) signa l
inhibit s acknowledgement of l owe r priority int errupts.
The highest pri ority int er rupt reque stor (the one with IE l = 0) places
I
its in te rru pt vector on the data bu s (ACK = I, READ VECTOR
0) and
sets it s inte rrupt -u nder service latch (IUS = 1).
The ZBO-CPU executes a t wo byte RETI (RETurn from In t errupt) ins truction
at the end of an interrupt se rv ice routine.
I
o
Thi s i nstruction is
decoded by the CTC and is used to reset the interrupt-u nder-servi ce
l atch.
The normal daisy chain operation can be llsed to detect a
pending i nterru pt (JP=I).
instruct ion is decoded
(EO
fihen the first byte (EOI6) of a two byt e
= 0), the daisy Cha in is modified by
inhib it ing all pe ndi ng interrupts so that the device pres ent ly under
service is the only one wi t h lEI = 1 and lEO = O.
32
-
liB)
-
c=J
lET
~
AC K¢
rCH<ji
~
lE I 13 ~"
.
-I"»~~
~
1l
~
_
~ J'.x,.
/
IP<l>
~
73
lE n
~
~C Kl
CHI
~
R E ADV ECT~
74
IP l
~L
IU Sl
.~26
25
27 28 r:
E~
IEI2
-
INT 2
ACK2
ACK
CH2
~
E~
I
IP2
-
~
IUS2
Ml
w
w
E~
1
iEi3
~
66
R EAD VE CTOR
~
76
U-
-
AC K 3
CH 3
REA D V ECTOR
69
INT3
L
IP3
IUS3
50
~
WR ITE
51
-
D6
V ECTOR
i<J ~1t
-
.. '"
H EA D
VECTOR
30
47
48
T 46 ' -
'49
~
-
1 ~iH
34
132
~i- ~
1L;'
~
AC K
," DO
,
l
ED~
IORO 24
J
.,L
I(JS,"
~
-
72
-
~
'36
"~
l,35
FIGURE 4·8. ZI LOG Z80·CTC lEI I NPUT AND INT, lEO OUTPUTS WITH PRI ORI TY
INTE RRUP T ,
~
,.r- Dl
, 71
l
r,
~
D2
I
I
[f
the ne xt byte i s 4D16, th e interrupt-under-service latch i s reset
(I US = 0) .
4. 5 - Channel Sel ec t (CSI and CS O In puts )
The se inpu ts se l ect one of four CTC channel s for \; ri ting the
i
channel co ntrol reg ist er (CC R) or time consta nt registe r (TC R) and
read i ng the down coun t er (DC).
The chan nel read/wri te ci rcuitry of
Figure 4-9 is part of th e channel control logic bl ock of Fi gu r e 2
(Channel Block Di agram) in the ZSO-CTC spec ificati on.
Channe l zero
yenera tes WRITE VECTOR whi ch loads an interrupt vect or when 00= 0.
I
READ REG and WR ITE RE G are generated by the Rea d/ Writ e circuitry
discussed in Sect i on 4. 2.
of clock by FFl 9.
READ DC i s sy nchroni zed to the ri s in g edge
I{R ITE TC i s enab led by FF7 if, in t he previous write
to chan nel zero, DO • D2 = 1.
4.6 - Cha nnel Contr ol Regis t er
I
Each of the fo ur chann el control registers
co nditions f or a CTC ch ann el .
(CCR) sel ect operati ng modes and
CSO and CSI are used t o fO ml a two bit
binary add ress to sel ect one of th e chan nel s.
CCR bit s 0 and 2 are
assoc iat ed with t he ch ann el READ/ WRITE circuitry and are di scussed in
the previous sect ion .
and D3 throu gh D7.
l atches on each bit.
Figures 4- 10A and 4- 10B i llustrat e CCR bi t s Dl
Bi t s 04 th rough 07 are stored conditi ons and have
INTENA (bit 7 ) is in it i alized by rese t so that no
CTC channel can interrupt afte r RE SET.
I
34 Bit 1 (Reset Chann el ) res ets FF8
I
READ REG
CS1
WRITE RE G
,
.,:
0
eso
I
o
' ' ' 'f::
CSO~ 4r-E>~
CS1~
_ __ _ __ _
j'
J3
FF1~a
<l>
C
::t-
a
1
WRITE RE G
I
R EAD DC
142
10 WR I TE CCR
WRITER EG~
DO
D
10 a
F F7
C
a
r ------------ -- - --- ---,
33
I
RESET
I
34
31
35
I
36
WAITE V ECTOR
I
I
CHAN N EL </> ON L Y
I
~- - -------- -- -- - - ----- ~
FIGURE 4-9. ZILOG Z80-C TC REAOIWRITE CIRCUITRY (CHANNEL </> 1.
u
35 9,
I
"( ¢ 1 3NNlfH:» Il3.LSI~31l lOIl..lNO:J 13NNlf H:J J.I.:>-OSZ ~O'IZ ·VOl -lI 3Iln~l~
I
M
I
WRITE eCR
I
I
I
B
y
O;-Jt~ I
FFB
D1
WR ITE
eGR'
WRITE TC'
5~
4
3
e
--!­
WR ITE CC R
D
D
Q
R A NGE
L
STOP'
RESET
MO DE
WRI T E CCR
WRI TE CC R
9
~ INTERN A L
03
--!­
WRITE eGA
oo~~ l
11
32
MODE
WRI T E eeA
16
M ODE
EXTERNA L
15
WRI TE CAR
~
r-----~Gn'~------_,
WA ITE eCA
WRI TE
eeA
--h­
D4-I,-t~ 1
20
D7
SLOP E
RE SET
22
INTE NA
FIGURE 4·10B. ZI LOG ZaO·CTC CHANNEL CONTROL REGISTER (CHANNEL ¢ I.
I
RANGE
26
R
37
MOD E
whic h dis cont inues the counter operation.
t ime const ant is loaded.
If bi t 3
Counting is resumed when a
Bit 3 controls the timer mode trigger sou rce.
0, the timer begins operation on the ri sing edge of Clock .
If bit 3 = 1 the ex tern al trigger (CLK/TRG) is valid for start i ng the
timer operat i on following the rising edge of Clock.
Note tha t bits 1
and 3 are not stored co nditions.
I
I
I
G
4.7 - Cha nnel Trigger (CLK/TRG 3 through CLK/TRG 0 Inputs ) .
The Exte rnal Clock/Timer Trigger input for chan nel zero is illustrated in
Fi gure 4- 11 .
The active edge of this input is dete rmined by SLOPE (!lit
4) from the ch annel control register.
In the count er mode, every active
edg e on t his in put decrements the down counter.
active edge i nitia tes the ti ming function.
I
In the ti mer mode, an
FF9 l atches the tr igger
in put asynchronous ly, then FFIO synchronizes TRG t o t he ri s ing edge of
Clock.
The l atch form ed by tra nsistors 6 through 17 resets FF9.
Note
th at when STOP is "high", FF 9 is res et; th us trigger inp uts are not
recog nized when the cou nter is disabled.
38 I
I
I
I
n
0rn00 I
o
FF 9_
TA G ' ~
CO
22
FF10_
<!>
C
O
R
-=
<!>
STOP ----L--­
SLOPE; 1
TAGl
LSLJ
I
FF 9C
~~=
FF9 0
~L-_
_
_
ffiG ~
FF9A ~
FIGURE 4 -11 . ZILOG Z80-CTC EXTERNAL CLOCK/TI MER TRIGGER (CLKfTGR ¢ ) INPUT.
39
TA G
I
o
4.8 - Chan nel Prescaler, Time Constant Register and Down Counter
I
In t he t imer mode, the prescaler is an 8-bit counter which can be
progralTl11ed by bit 5 of the channel control register t o divide the
system cl ock by either 16 or 256.
prescal er .
Figure 4-12 i l lustrates bi t 6 of the
When START TIMER is "high" the prescaler is rese t.
Transi stors 10 t hrough 19 fo rm a latch that changes state on the rising
i
I
I
I
I
i
ed ge of Clock depending on a toggle input (T or~) and the feedback
l ine from Q or Q.
Figure 4-14 illustrates how the 8 bits of the
prescal er ar e connected.
PF16 and PF256 are the prescaler outputs used
in the channel counter control descri bed in t he next section.
Bit 6 of the time constant register and down counter are illustrated in
Figure 4-13 .
prescal er.
The down counter stage operates in the same manner as the
WR I TE TC loads the time constant register latch formed by
t ran si st ors 37 through 41 .
LOAD DC transfers the time constant to the down counter whi l e READ DC transfers the contents of the down counter to the internal data bus.
Transistor 55 is part of a zero detect gate. ZERO is an input to the channel interrupt ci rcui try (S ect ion 4.1 0). The 8 down counter stages are connected in the same manner as the prescal er (Figure 4-14) . I
I
40 I
I
I
r=- - --- - PRESCA
--­L~-;;';6- I T~
-
-
-
-
- -1
1
1
1
0 1
I
1
I
I
I
-
ST AR T T IMER
1
1
I
0 ,
I
~~
L__ _____
___ _
_ _ _ _ --I
23
B
--t
]'"IT
PRESCA L ER
BIT 6
a
Q
I
I
I
I
FIGURE 4-12. ZILOG Z80-CTC PRESCALER CELL (BIT 6).
41
I
- NTE R
- - - - - - - - - OWN
COU
;,-
~
6
," '-'''"''- ", I "
OC ClK
L/CT
DC C lK
-----,II
'" . 1 1 r".'
"
0
0:I
BIT 6
~
READ DC r
~'24
~~1
39
T
37
DOW N
COU NTE R
BIT 6
Q
40
Q
H
FIGURE 4-13 . ZILOG zso·eTC TI ME CONSTANT REGISTER AND DOWN COUN T ER CELL
(BI T 61 .
42
o
D61
:
1
-
-
_
r::=I
T
T
____
CJ
T
<i>
T
2
3
PRE SCA LER
OUTPUTS
ONLY
."
w
IT
4
hJ
rr
5
hJ
}>---rr
6
r-u
riT
7
FIGUR E 4·14. ZI LOG Z80·CTC PRESCA LER AND DOWN COUNTER CONFIGURATION.
c::J
I
4. 9 - Chan ne l Counter Control
In the counter mode (Bit 6 = j ) the down counter is dec remented by each
tr i gge ri ng edge of the external Clock input.
t he c i r c uit ry that
I
gene,· ~t es
Figure 4- 15 il lu s trates
the Clock and load signal s for the
presca 1er and the down counte ;,
The counter mode i s enabled by a NOR
ga te and an inverter (Transistors 69 through 73) .
TR G becomes the down
counter cl ock (DC ClK) through 2 NOR gates and a non-inverting driver'
(tra nsi stors 74 through 85 ).
I
I
I
In both the counter and the timer mode
the down co unt er is loaded when it rea ches a zero count or whe n the
ch annel stops counting or timing.
Transistors 86 through 90 gener ate
the load DC si gnal whenever STOP or T01
=
1.
(Tra nsi s to rs 80 through
90 are photographed in Figure 4-16).
The timer mod e (Bit 6 = 0) is inhibited by a reset cond it ion on FF4
when mode
I
=
1 (See Figure 4-10 channel control regi ster bit 3).
Wh en
the timer mode i s selected the output of the presca ler clocks the down
o
counte r.
bit ( Tr a ns is to rs 53 through 65).
If START TIM[R is enabled by FF14
I
then the output of FF15 co ntrols
DC ClK (t ransi stors 48 throu gh 79 are
One prescal er output (PF16 or PF256) is sel ected by the RANGE
photographed i n Figure 4-10).
D
An inverting buffer (not photographed) for the sys tem cl ock driv es the
pres c aler c l ock.
I
44 I
I
I
I
¢
e
J
i
INTERNA L S
) - - ­(1)
D
0
FF14
I
(PAESCA L ER CLOCKI
C
T RG
STOP'
START TIMER
R
0
EXTERNAL
PF 16
B
I
PF256
77
):,
ID
O~~
.---­IJ5
~DCCLK
i
FF15
RAN GE
<l>
c
START T IMER
0
86
STOP
TO 1
~
88
89 90
87
I
I
I
I
o
FIGURE 4-1 5. llLOG lBO-CTC CHANNEL COUNTERITIMER CONTROL.
I
45
LOAD DC
i
o
4.10 - Channel Inte rr up t (ZC/ T02 through ZC/TOO Inputs)
o
The channel generates a pos sib le interrupt request sequence every time
the down counte r reaches a zero count condition .
Figure 4-16
ill ustrates the inte rrupt control circu itry for channel one.
set when th e down counter reaches zero.
I
I
I
FFl6 is
FF17 delays the zero count
signa 1 and resets FF 16 when C1oc k equals "0".
Tran 5 i stars 1 through 12
fo rm a two stage invert ing driv er for the ZC / TOI output (Pi n 8).
The Q
output of FFl7 al so is an inp ut to the cha nnel interrupt circuitry tha t
im pl ements the Z80 system of nested pri ority interrupts.
Tra nsi st ars
19 through 25 latch the zero count condition if the channel interr upt
is enabled (INTENA - 0) and there is not already an interrupt under
service (IUS1 - 0) .
INTI goes "high" and generates an Interrupt Request
(INT - 0) that is "wire-ORed" to the CPU !tIT input.
To ensure that t he daisy chai n enab le l ines are stable during an
interr upt ack nowledge cycle, trans istor s 31 thro ugh 38 latch the
I
I
~
interrupt condition only when MI is "hig h".
IPl becomes "high" and is used
to inhibit lower priority int errupts as discussed in Sect i on 4.4.
i s used in the Read/Write circuitry to enable reading of the interrupt
vector duri ng an interru pt acknowledge cycle.
to the interrupt vector regist er.
The signal is also an input
The t wo inp ut NOR gate composed of
transistors 55 thro ug h 57 is used to reset the interr upt I
I
I
AC K1
input and set the interrupt-under-servi ce latch (FF18). IE[2 is 46
I
u
I
f
I.
L
~
TO 1
Z ER 0
--==1----1
o
a
iEi1
DC elK
II\lTI
INTAC K
)0 I
1[6
],
'(
,J
w
1~~2
'"
i US1
ZC/TO
~l ~
~-1 1
r
ACKl
CH I
IEI2
~
,~
,,,
I
I
1
,
I
I
s
",.,
61
o
63
62
r-
01
IUS1
FF 18
FETCH
~
c
i5
R
RE SE T
CH A NN E L INTERR UPT
I
CH l
~-- ---- - - - - ---- - - - - --------------- - -- --- - -----
I
J
FIGURE 4-16. ZILOG ZSo-CTC ZERO COU NT/T IMEOUT (ZC /TO 1) AND CHANNEL INTERRUPT.
47
I
G
generated by transi stors 42 th rough 50 as part of the inter nal
i nt errupt daisy cha in .
FFl8 is reset at the end of a retu rn from
interrupt instruction i f there are no higher priority i nterrupt s (IE Il
= I).
Refer to Secti on 4.4 for a discussion of how the channel
i nterru pt si gn als are used in eTC interrupt servicing.
I
I
g
M
I
48 I
I
I
I
I
I
o
SE CTION V - SPE CI FICATION REVIEW
The in format i on and comments in this secti on ar e based on a Zil og
Product Specifi cat i on dated Apr i l 1978 included i n the Ap pe ndix of this
report.
The Z80-CTC Features li st sh ould include the ti mer resol ut ion and
max imum delay tim es .
circuit s.
These are useful poi nts of comparison among t imer
The resolution is 8 microseconds (presca l er < 16) an d the
maximum delay is 32 milliseconds (prescal er
-I
256 ).
The bl oc k di ag r ams i n Fi gures 1 and 2 shou l d separate the i ntern al dat a
bus from t he con t rol 1 i nes to sho\; more dearly the fu nct ion of eac h
control line.
Timi ng Waveforms on pages 3 and 4 show bus t i ming rel ati on shi ps for
eac h of the CPU cycles .
Expla nat i on for the return f rom i nterrupt
cycle i s correct but not clea r ly wr itten.
The Programming sec ti on details the channel operation in both the t imer
and counter modes.
The timer resolution and max imum del ay t ime can be
calcul at ed from the formula given under Bit 6 ; O.
49 A.C . character istics are shown both for the Z80-eTC (page 6) desc ribed
in thi s report and the faster ZSOA-CTC (page 7).
I
I
I
I
The maximum cl ock
fre quency for the ZSO-CTC is 2.5 MHz while the ZSOA-CTC is 4MHz.
An
A.C. Timing Diag r am is on page S.
Abso lut e Maximum Ratings are listed for the commercial temperature
range of O°C to 70°C.
The rat i ng for the voltage on any pin wit h
respect to ground of -O.3V to +7V i s specifi ed to insure that the input
junctions do no t bec ome forward bia sed (- O.3V) or t he input vol ta ge is
not great er t han the punch-through voltage or fie l d t hreshold volt ages
(+7V) whi ch may damage the device.
The power dis si pat ion ra ti ng of
O. SW is sl i ghtly greater than the maximum oper ating power dissi patio n
[ lee (VCC + 5% VCC)] of O.64W.
Power di ssipati on of O. SW
i s adequately conservative for a ceramic package at 70 °C amb ient.
o
The DC charact er is t ics i nclude Darlington Driv e Current (IO HD) of -1. 5 mA at VO H = VE XT = 1.5V.
This is the source current ava il abl e to dr ive the base of high current transi stors in the Darl ing­ ton confi gurat ion. ~
I
Capacit ance is measured at IMHz separately for the clock, input pin s
and output pi ns.
Pac kage capacitance has a signi fi cant effect.
50 I
SECT ION VI - CONC LUS IONS
Th e Z80 - CTC , as we ll as the Z80 PIO and SIO are not gener al pu rpos e
de v i ces.
The contr ol signal s are unique to t he Z80 - CPU, and the ad di ­
ti on a l c irc uit r y requ i red for the interface would not j ustify us i ng the
CTC in othe r mi crocomputer systems.
Moreover, t he CTC re l ies on the
Z80 -C PU RE TI op codes for interrupt processing.
The maximum t imer delay of 32 ms. is a li mitation comp ared t o com peti­
t iv e t i mer circuits.
The da i sy chain in t err upt structure imp l emented in t he part lim its the
abil i t y to prog ram the interrupt priority, b ut has the advanta ge of re­
d uc ing softwa re requirement s.
•
The bus t imi ng spe cif icati ons are critic al whe n de s ignin g a syst em wit h
many peri phera ls and large memory.
Buffers are al most always required
to driv e the address and data bus.
Delay times mus t be revised and in
s ome c ase s th e system clock speed lIlay have to be red uc ed .
I
51 SECTIO N VII - RECOMMENDAT IONS
f a
progran~able
count er and t i mer f unction is needed in a ZSO-CPU
microprocessor system, t he ZSO-CTC wil l be the most favo r able choice ,
I
o
since other timer circ ui ts (su ch as t he Intel 82 53 Co unt er/Ti mer ) are
not direct ly compati ble wi th t he Z80 con t r ol si gnal s.
The ti me required for te sting the Z80-CTC shoul d not be excessive,
s ince the four channel s can be tested concurre ntly.
I
I
I
A ga te l evel
descri pt i on of the part is required t o estimate the faul t cover age of
pro pos ed test seq uences.
Workmanship exh ib i ted in the sampl es exami ned in th is report was good.
However , tr adi t io nal mi litary part testing must be cont i nued to catch
reocc urring probl ems such as package lid sea l leaks , loos e wire bond s
and intennetal l ic format ion.
Lo ng bonding wi res and voids i n the die
attach area are potentia l reI ia bil it y ha zard s encountered in this
o
examination (Secti on I I ).
Chip temperatures and metal curre nt dens it i es shoul d be re-evaluated
u
for any vers i ons of this pa rt specified for higher t emperatu re
amb ients.
52 Z80®
-CTC Z80A-CTC o
o
I
o
ProductSpecUfication
APRIL 1978
Zilog The Zilog Z80 product lin e is a co mplete se t o f mlc ro­
compute r compone nts, develo pment systems and su ppo rt
soflware. The Z80 microcom puter co mponent set includes
all of th e circuits necessary to build high-p erfo rmance
microco mpute r systems with virtually no o th er logic and
3 minimum numbe r o Fl ow cost standard memoI)' elements.
• Selectable positive or negaLive trigger may initiate tJLnt.'!r
o peration.
• Three channels h ave ze ro co unt/li meout ontputs ca pable
of driving Darlin gton transistors.
• Da isy ch ajn p riority in te rrupt logic include d to p rovid e
for automa tic in terrup t vec torin g wHh out ex tern al logic .
• AU In puts and outpu ts full y TT L co mpati ble.
• Outpu ts directly compat ible wit h Z80-SIO.
The Z80-Cou lller Timer Circuit (CTC) is a prog rammable ,
fou r channel device that provides counting and timin g
func tions for Ihe Z80-CPU. The Z8 0-CPU configures the
ZSO-eTC's four indepen deo t channel s to o pe rate under
v::ui ous rn o de~ and condition s as re quired .
eTe Architecture
St ructure
I
I
•
•
•
•
•
A block diagra m o f th e Z80-C'TC is shown in fi gure I .
The in tern al struc tu re o f th e Z80-CTC consists of a Z80 ·CPU
bus inte rface , intern aJ contr ol lngic , four counter ch ann els,
and in terrupt control logic. Each channel has an int e rrupt
vect or for automa tic interrupt vec torin g, and interrupt
prio rity is dete nnined b y channel n u mber with chann el 0
having the highest pri o rit y.
N-Channel Silico n Gate Depletion Load Technology
28 Pin DIP
Single 5 volt supply
Single ph.,e 5 yoll d ock
Four inde pe nd e n t program mable 8-bit co unte r/ J6-bit
tuner channel s
Th e channel logic is compose d 0[2 registers, 2 co unters
and contr ol lOgic as shown in figure 2. The regi ste rs includ e
an 8 -blt t ime const an t regisre"r and an 8-bit chann el co nt rol
regis te r. The cou nters inclu de :m 8-bit reada ble down
coumer and an 8 -bi l prescaler. The presc. le r may be
programmed to divide the system clock by eit he r 16 o r 25 6.
Features
• Each channel may be selected to o pera te in either a
co unter mode or timer m ode .
• Pro~r3mmable interrupts on coun t ~r or tim er s tates.
I
I
u
• A time constant registe r autom atically rel oa d s th e
dow n cou n ter a t l eTO a nd the cyd e is repeated .
• Readable d own co unter in dic:J les n um be r o f Co unts-ta -go
un til ze ro .
• Selec table 16 o r 2 56 clock prcscaler for each time t
ch annel .
+SV
c....()
'''·T[ RNAL
CO(\ TROL
LOGIC
'I'
11J
/
OUA
•
CONTkOl
{·PU
A
BUS
110
IV
/
lI:. RO CO U:.iTrTl \lEOUT 0
<'" I-lANNE L I,jI
r LOCK/TRIC<;t:R Q
~ ~'"''' INT [ RN U BUS
6
I
lit
J
~
~
F(
ffi"fffiOL
LOCIC
ZE RO COlI!'ITr'TlM1:.0U T "2
,II,,"N":
{" LOC K./T R IGGER 1
.
,
INTERR UPT CONTRO L LINES I
t LOC K[TRIGGER,
7­
N'"RRLWr
-
ZERO COUNT/TIMEOu r I
[j
FIGUR E 1
CTC BLOCK DIAGRAM
53
-,
~/
t:1f .... ~NF.l 1
CLOCK/TRIGGER 3
/
Channel Counter and Register Description I
I
count o f ze rO. At any time, th e CPU ca n read th e number
o f counts- ta-go un til a z.e ro COlilE. This coud ~ r is de·
cremen ted by th e prescale r in tim er mode and CLK/ TRI G
in counter mode.
Time Constant Register - 8 bi ts , loaded by the CPU to
in itialize an d re- Iuad Down Counte r at a count of ze ro.
Channel Control Register - 8 bilS , loaded by th e CPU to
select lhe mod e and conditions (If chan nel opera tion.
Prescaler - 8 bit counte r, divides system clock by 16 or
256 for decreme ntin g Down Cou nter. It is used in tim er
Down COUllter - 8 bi ts, loaded by Ihe Time Cons tant
Re giste r under p rogram control an d automatically at a
mode only.
ClIANN EL
/
/
CONTROL
I
I
AND LOG IC
(8 BITS)
~y
Q
TIME
CONSTANT
REG ISTER
(X HITS)
REGISTER
V
~/
INTERN"L BUS
/
'I'
/
PRESCAL ER
(X BITS)
<"'-7
Zf RO.Ca UNT/TIMEOUT
DOWf'toI
CO UI\TER
(I'! 8lTS)
7
/
(X Tl RN A L n orK:TIML:.R TRI GC L:.R
FIGUR E 2
CHANNE L BLOCK DIAGRAM
Z80-CTC Pin Description I
0,
CPU
D~~~
~
'"
OJ
(t4
"
"
"
"
"
.,
"
'"
''' ""
"
1 ""
e TC
CONtll.OL
r /lOM
CPU
CS I
Ml
lBO CTC
Cll( '11" ,
"
CllI:IT RGl ~
"
"""
)
~,~~::;'
Cl KI HIGJ
-"
CON 'lIOl
'"
~~
11'(1
"
"
"
CLK/TRGI Chann el I Ex tern,1 Clock or Tim e r T rigger
(I nput)
CLK/TRG 2
Chann el 2 Ex .elO.1 Clock or Time r Tri gge r
(lnp ul)
CLK/TRG3 Channel 3 Ex tern al Clock o r Timer Trigge r
(l n put)
ZC!TOo
Cha nn el 0 Zeru COUll t or Ti meout
(o u tput , aclive high )
if(StT
iOilo
OAIS Y {
Cha nnel 0 Extern.1 Cloc k or Time r Tr igger
(ln pu t)
ZC I1 02
;;0
IH flR RUPT
CLK/TRGO
2Cfre,
"
DC
0,
mIT'G
'l
•-sv
G>O
54
o
I
Z80·CTC Pin Description (continued) ZCiTOI ZC/ T0 2 RD
Ch <lnnei ~ Zero Coum or Timeou t
lEI
Interrup t Enab le In (inpu l , , clive high) lEO Inte rrup l Enable Oul (o utp ul, ac tive hi gh).
11:. 12nd lEO fO lm a da isy cha in conn ec llon fo r prio rity int c: rrup t co nt rol ac ti ve iow)
(OU lpU L, ac tive hi gh) I
I
I
8
I
Rea d Cycle Slalus from the Z80-CPU (In put,
Channel i Zero Coun t Or Ti meou l
(o u tpu t, ~di ve hi gh) CSI - CS0 Channel SelecL(in put , acti ve high). These
fo rm 3 2·bit binary add ress of the channel
to be accesse d . D7 -D0
Z80-CPU Dala Bus (bidi rectional, Lristate)
CE
Chip Enah le (inp ut , acti ve low)
<l> System Cloc k (i nput)
MI Machine Cycle One Signal from Z80-CPU (i nput , lK tlve low) IORQ
Input/ Outp UI Request from Z80-CPU (i npul ,
active luw)
Interru pt Req ues t (O Ul plH , ope n drain , INT
active low) RESET sto ps all channel, from coun lin g and
resets chann el in te rr upt enab le bits in all
control registers . DU l"I ng ["cse t Ume ZC/T0'll-2
and tNT go to the Inac tive sta tes , lEO re neels
the state o f IEf , :md the data bus output drive rs
go to the high impedan ce state (in put , active
low)
RESET Timing Waveforms
CTC WRITE CYCLE
IlIu s t r ~ted
here is the IIm mp. for loadi ng a chann el cont rol
WOl d, (i me cOllS'anl and inte rrupt vecto r. No wa it st<ltes are
allowed for wmmg to the CTC other than th e aut omat icall y
Inserted (T w *) . SlIIce (he t i C does not recei ve a specifjc
write signal, It in te rn ally genera tes it s own fro m !h e lack of
an RD slgnll.
cS0- 1
,,,;
"
,. Cl!
X
'"'"
'"
"
L
cl-I ",,'. n .. OORESS
X
\
/
"'
X
OA l A
CTC REA D CYCLE
I
rn ustra ted h~re 1S the timing fo r readi ng a channe l's Down Counter when in Cuun ter Mode. The value read
ont o the data bus reJleClS the numbe r o r eXICrIl ,l1 cl oc k's
rising odges pri or 10 the rising eqge of cycle (12)' No W'llt
stotes are allowed fo r read ing the e TC o ther [ha n the ::Iu to­
m.lically inse rt ed (Tw' ). ~u
"
,.
tS o. I
ct
10irn
'"
X
\
X
/
\
/
Cl-l" "' .... ;l "OORESS
'"
GO
DATA
INTERRUPT ACKNOWLEDGE CYCLE
Some ti me aft er an in ter ru pt is req ueste d by (he CTC, the
CPU wJII send OUI a ll in lcrru pt ack nowledge 1M I ' nd JORQ) .
Dur mg Ih is tim e Ihe HHcrrupt logic of thc eTC will determ ine
the highest priority channt'l which IS req uesting an interr upt.
To insure (hJt the da isy Chatll enab le li nes stab iJi L.e. chan nels
are mhiblted fro m ch::lnging the ir in terrupt re quest slat us
when
is 'clive If tho CTC Inle rru pt Enable In put (IE I)
is active . tl\cn fhe highes t priority in terrupl in g channel
phlces thl! CO nl ents of ils in tcrru pt vecto r legis(er on to th e
Data Bus wh en (ORQ goes aclive . Add itional wait cycles are allowed.
'"
m
~
/
/
\
."
\:=======
'" =========_____ J
DArA
55
(
veCTOR
>
I
Timing Waveforms (continued)
RETURN FROM INTERRUPT CYCLE
o
I
I
I
If <I ZSO per ipile ral device has no ill!c rrupt pendi ng and is
n(l t unde r service , II, cn its. lEO = tEl. lr it has an interrupt
,, "
"
-,­
,, T,
' 4
TJ
"
"
under se rvice (Le . il has :lJI1!l1d y in terr up ted and receive d an
interr upt acknuwledge) lhen its lEO is al ways low, inltjbit­
mg lower p; ion ty chips fr um inter rupt ing. If it has:1 n inter­
rupt pe nding whidt has not yet bee n ac kno wledged , l EO will he low uiliess an "£ 0 " IS de coded as lhe flrS l byte of a two byte up eotic . In thie; >':Jse, lEO WIU go high until the nex t a pcade by re i~ d ~ c \.)dl'd, whc reup<.>11 It wi ll :lga in go low. If the second byte vf lhe upcQik was a " 4 0 " then the apcad e was an RETI in~ l(u c lju n . Afte l an " EO" opc(}de is decud ed, on iy the peripheral device whi ch h,n inle rrU plcd and is cu rrently un der se rvice will have its l E1 1llgh "od lIS lEO low. This devi ce is th e high· est priont y device 111 the daisy chain wh ich has rece ived an
inter rupt ack nt)wled ge. Al l o tl!er pe rlp he raJ s have lEI =lEO . If rll.e nex t opcode byte decoded is " 4D", ti llS peripheral device will reset Its "interrupt undt.: r se rvice" co ndi ti ou. Wail cyd<s are allowed 10 Ihe
cycl es. Mi
\
I
;m
~
1
I
\
"--------.I
~
0 0 -°7
-------,-----------­
_______ .J
'"
--------------~I
lEO
m
I
I
o
I
DAISY C!-IAIN lNTERRUPT SERVICING
UJUSHJ led :11 rigill IS J tY Plcal llested in te rrupl sequ ence
In the eTC In th is sequence channel 2
inl2 rru pts ;Hld IS gr~l!1ted service. Wh ile th is ch ann el is being
se rvi.ce-d , high er priol ity ch::mncl I interrupts and is gr:lj~ ted
service . The service l ou line ro r the highe r prio rity channel
is completed and a RET] instUJ CTJ On is execu ted t o indicate
to the chunnd th:U it:) routine is complete, A t this time th e
service rou tine or lowe r priori ly cha nnel '1 is completed.
whlch ma y occur
1 CHA ./\If! I
HOUt~ T S
~ I(I
l
A/j I PI1lRRU~1 AIID IS AL ItNOWI (OGf U
UNOtR SER\·ICf
SEII.\'I('( R.i5P1 'U f O
IEO~ IU
Ita~1II
eH A N~ H II~ lf ~"U~n311~ f"[ NDSSE AVI CUIC
SEII VI CE CO'>1Pl ( I E
,
'> SteO NI) ·AI TI
IN S 1~UcrII)N
'lO ~ I I
I{O ~
01 C"". 'lttl
S[III/ I(( flft llM{ O
~,
I
ISS U(Q ON r OMPI( I'O N 0'
<H ANN t~ l stl;~l.{i flIlUII .... E
ere CO UNTING AND TIMING
I
In the count er mo de Ihe risi ng or faili ng edge of th e eLK inp ut c aIJS~S ihe co unte r to be de..: remc nte d. The edge is detec telJ tOllilly aSYilchlOtlOilsly and must have a nli ntmU m ClK ptllse wid th. However,th e Counlei is sy nchronous with cP there l"cH e 3 se tup tiltle InUS.: be [11(' £ whe n it is d esh~d La have the Cfl lln ter decremen ted by th e next rising edge of <fl . ",
reiTO
hi lhe timer mode lhe presca ler ma y be enabled by a rising
falli ng edge on the TRG input. As in the co un ter mode,
th e edge IS detec ted lo ud ly asy nch ro nously and must have a mi ni mum TRG pul se Wld! h. Howeve r, wh ell tim ing IS 10
start with re spec t to ' he Jl ext ris ing edge of (~\ a setu p rim e mus t be me t. TIle prescatc r CO li nts rising edges of (1), Or
~
!
INTE RNAL COU N TER
ZE 11 0
cm:rn
-----"I
\
~--~
\'-_______
-ILSL.JLSL.....JL
"G
INTERNAL
TIM ER
56
~
\
/
STAAT 1 1M ",' .
I
I
CTC Programming
SELECTING AN OPERATING MODE
No time constan t WIll follow th e channel
cont rol word . One ti me cons tant must be
wr ilte n (Q the chan nel 10 initia te ope ra lion.
Bi l 2 = I The time constant for th e Down Count er
WIll be the ne xt word wr illen to th e selec ted
chan nel. If a lime consta nt is loaded whi le <I
ch<l nnel is countin£,. (he present co un t will
be co mpleted before the new lim e cons tant
is loaded ml o the Down Counte r.
When selecll ng <l channc!'$ opera ling mode, bit 0 is set to
I to Il idicale this word IS lobe sto red III th e cha nnel control
regis ter.
'"
"
,,,
'--v---'
1'11'1'
I
I
I
IlJl 2 =\l
I"" . ,,' ","
'"
'"
u_
'.
'"
'--v---'
,II!,'
!
' ' ' " M '~~<l ' ' ' ' \ Bit I =
Bit 7 =
0
BII 7 = 1 Channel int err upts disabled.
~
Channel conti nu es co unl ing. Stop ope ra ti on. If 8it 2 = I cllJ nneJ will res ume operati on alier 10ad JO g a time constan t, oth erwise a new contl ol word
mU ~ 1 be loaded .
Bit I = I
Channel Illte rrupts ena bled to occ ur every
time Do wn Cou nter reaches a count of ze ro .
Sett ing Bit 7 does not le t a precedi ng count
o f ze rO ca use an int e rru p l. Bit 6 =
0
Bit 6 = I
LOADI NG A TIME CONSTANT
Tllner Mo de - Dow n co un te r is cl ocked by
.he prescalt' r. The perI od o f the coun fe r is:
Ie • P • Te
tc = sys tem dock pe riod
P = preseale of 16 o r 256 Te = 8 bi t bi nary progra mm ab le time constant (1 56 on ax) An 8-bit time constan ! is loaded m to the Time Co nstan t
registe r foll owtll g <l chann el cont lul wo rd wit h btl 2 se t. All
ze rOS in dicate a ti me constant of 256.
,..
Counter Mt)l1e - Dow n Coun ter is cl ocked
1(' 7
bv c xtern ll d .)c k. The prescalcr is no t use d. Bit 5 =
0
Bil 5 = I Bil4 =
0
Tjmer ModI." Only- Sys te m dock cf>
by 16 ill pre sc aler.
IS
".
oc. ",
",
"~
.. ,
'"
u,
".
t( :
'"
'"
''".
divided
LOADIl'>G AN INTER RUPT VECTOR
Tim er ~Iodc Onl y- System clock <I> is di vid ed by 256 In prese, ler. The Z80·CPU req uires thdt an 8-bit mterr upt vector be
supplied by th e IIlterr uptin g channel. Th(' CPU for ms the
ad dress for rhe Inlerru p t se rvice rC'lUl ine of the cha nnel
using this veCfQ r. During an interrupt ackn o\.I.'Iedge cycle
th e vector is placed on Ihe Z80 Data Bus by the h ighes l
pri orit y channel reques nng se rvice ll t tha t ti me. The desired
in te n upr vec tof is loaded into th e e TC by wnting int o
chann el 1/1 wirll a zero in D0. D7 ~D3 cont Jin the sto red rn ­
terru pt vector , D2 and D I are not us.ed in loa din g th e vecto r.
When t he e TC res ponds to an lJuermpt ac knowledge, th ese
tw o bilS con t:u n th e binary code o f th e highes t pri orit y
r.: ll annel wlw,;it re quested th e intenu pt an d D~ conta ins a
ze ro since lhe add ress of the internrp t se rvice routI ne start s
at an even bYle. Channel f/J is the- high es l priorit y ~ h onncl.
Time r Mode - nega tIve edge trigge r starts
timer Ope(:)lIon.
~l ode - nega tive edge dec lements
Co untel
Ihe do\\ n CQUO[t!r.
lli t4 =1
Tilne r Mudc - positive edge trigger Sia l t 50
timer OpcFHion.
Co unler Mode - posi tive edge decre meOlS
th ~ J OW" culln ler.
B,; 3=0 Time, t\ lo de Only - Ti me r begill s operati on
on the rising edge o t' T2 of the ma chin e
cycle foUowing th e one th at toads th e time
com.tam
Bit J = I Timer Mode Only - External tl'iggcr is val id for st:HT ing t imer opcr:Jtit"lIl after risi ng edge f T~ 01 tile Ulllchme' cycle fo ll owing t he
ne Ih3t loads the lime co nstan t. The Pre·
sC~ller is decl emenh:t1 2 clock cycles later if
tht- setu p lim\! IS met , ot herwise 3 cloc k
cycles.
'"
-,
57 ". '.
'"
0<.
'"
"
"
",
":
'.
Z80-CTC A.C. Characteristics
TA = 0° C
to 70° C , Vee
Signal
Sym bol
I
<l>
I
=- 1-5 V ± 5%, unless o{ herwis e noted
Min
Pa rameter
400
170
170
'c
Clock Peri od
'W N>HI
Clock Pulse WId th , Clock High
tw(tI->LJ
Cloc k Pul se Widt h, C lock Low
'r. It
C loc k Ri se and Fait Ti mes
IH
Any H o ld T ime for Speci f ied Setup Time
Max
Unit
11 1
2000
2000
30
n,
n,
ns
Comments
"'
0
ns
160
'"
0
Control Signal Se lup Time to Rising Edge 01 q:. During Read
t Srf) (CS)
CS, C E o etc
or Wr ite Cycle
480
Data O utput Delay from Rising Edge of RD Duo ng R ead
tOR(O)
ns
12J
Cy c le
I
Do - D7
I
lEI
o
o
iORO
Da ta OUtput Del a y from Fall ing Edge o f IOR O During
IN T A Cycle
340
os
tFIO)
Deley to F loatmg 8us (Output Buff er D isable Ti me)
230
ns
ts{lEIl
l EI Setup Time [0 Falling Edge o f l ORO Du ring I NTA
tOH UOI
lEO Oelay Ti me fro m RI smg Edg e 01 IE I
tO l( jQ )
l E O Delay Time from F al lmg Edge of lEI
I DM OO)
lEO De lay f rom Failing Edge o f M1 IInterrupt Occurring
JUSt Prior to Mll
ts lpll A)
I ORO Setup T im e to R ising Edge of 4>
os
200
DI.~ rin g
i
Read or
Ml Setup Ti me to Ri Sing Edge of $ D Ur ing lNTA or MI
tS<P( 1\'11I
M1
220
190
300
'"
ns
n,
250
nS
210
ns
240
n,
(3)
[3 J
(3 J
Cycle
RD
iNT
tS<!, {RD)
A D Setup Time to RI Sing Edge of <1> Dunng Read or M1
Cy cl e
~ DCK U T )
! NT Delay l ime fro m RI smg Edge o f ClK/T RG
t D ;", (IT)
I NT Dulay T im e from RISing Edge of <.P
tC(CK)
Clock Per iod
I f. tf
Cl OCk and Trlggp.r R ise and Fa ll T imes
tS(CK)
Cloc k Setup Time to Rising Edge of 4, for I mmediate Count
t SfTR l
Trrgg er Setup Time to RIsing Edge of $ f or Enabl i ng of
ClK ITRGO_3
2tC(CI») + 200
tc i ll») t 200
2t c l ~'
-
Counter Mode
T imer Mod e
Counter M ode
50
210
210
Co u nle r Mode
T uner Mod e
Prescale r on Fo ll owing R isi ng Edge of $
tW(C TH )
200
C lock and T r igger High Pu lse W idt h
Counter and
Tim er M odes
lC/ TDO _ 2
Notes:
200
'W IC T LI
Clock and Trigger l ow Pu lse Width
l DH (ZCl
le/TO Delay T ime from RISing Edge of <P, Ze /TO High
190
Counter and
Tim er Modes
tDlilel
ZC /T O Del ay T im e from Fa il ing Edge o f 4'. lC/TD low
190
Coun ter and
Timer Modes
te -
Counter and
Timer Modes
tw t tf)H ) I tw'_r.l1U + Ir -t tt­
(21 I ncrease d elay by 10 osec for each 50 r>F increa se In loadin g. 200 pF m ax im um f or dara lines and 100 p F tot co nlro ilines.
[31 I nerCllse del ay b y 2 nsec for each 10 pF in crease in loading, 100 p F ma x imum
{4 J 'R'E'S'tf" m ust be a{:twe for a minimum of 3 cloc k cy cles .
[ 1\
OUTPUT LOAD CIRCUIT
TE5T POI NT
~~~~RO~:;.}" o---------L-~
1 rh K1C~l
I
-
o
J2 J
Write Cycle
I
o
t DI(O)
Cycle
lEO
I
I
ns
Dal a Setup T ime to R ising Edge of <b Durmg Write
Cycle
Of
Ml
60
IS <p W )
Vcc
Rl ~ 2 ' K~1
CR,
CR
2
CF!: 4
IN 914 OR EQUIV A L EN T
CL~ 500 fON AlLPINS
CR,
C,
_
250,A
C R4
-
58
I
Z80A-CTC
A.C. Characteristics TA = 0° C to 70° C, Vcc -=- +5 V ± 5%, unl ess otherwise not ed
,
Signal
I
Symbol
<I>
tc
'w l(l>i-II
Clock Period
'w1'~Ll
Clock Pul se W idth , Clock L ow
Ir•
CS, CE, etc
I
I
I
Parameter
tt
Cl ock Pul se Wid th , Clock High
M,.
Unit
250
105
105
[1 1
2000
2000
30
"'
n,
Cloc k Rise and Fal l Times
Any H o ld T i m e f or Specified Setu p Tim e
tS¢. (CS)
Co n't ro l Signal Setup Time to RISing Edge o f
or Wri t e Cy cle
tOR (D)
Data Output Delay from Falling Edge of RD During Read
Cyc l e
15",101
Data Se tu p Tim e to Rising Edge of It'! DU ri ng Write o r Ml
($
60
During Read
380
50
Da ta Out p ut Delay from Fal ling Edge of IOR G Du rmg
Delay t o F loat ing Bus (OUtput Bu ffer Disable T im e)
t S(IEI)
lE I Set up Ti me to Failing Edge of IOR O During I N T A
,­
lEI
tDH(IO)
I'E O Del ay Time from Rising Edge of lEI
t O LUO)
lE O Del ay Tim e from Falling Edge o f lEI
t OM(IO)
lE O Del ay from Falling Edge of Ml (In terr upt Occu rring
just Prior to
"'
110
"'
"'
160
130
190
"'
"'
t S$( IA I
IOAO
140
M1 )
IOAO Setup Time to Rliing Edge o f
Wri te Cycle
11 5
Du ring Read o r
¢
tS<t>(Ml )
Ml Set up T im e to
"'
RISing
Edge o f
Du ring I N T A or M l
90
n,
RISing
Edg e of <1 ' Dur ing Reed Or Ml
11 5
"<
(1)
121
12 1
13 1
13 1
13 1
"'
"
Ml
n;
160
Cyc le
.,
"'
"'
I N T A Cycle
tFIO)
n,
"'
C ycle
t ol ( O )
Comments
n,
0
'H
00 - 0 7
lEO
I
Min
Cyc le
tStf:>(RD)
R5
RD Setup Time to
Cy cle
. ~ -,
INT
tDCK( I T)
INT Delay T im e from RISing Edge of elK/T AG
lOIl.I IT )
tN T Del ay T ime from RiSing Edg e o f ¢
tC (C K I
Cloc k Period
(1 J
(2)
(3)
[4)
T imer Mode
50
Ir • If
Clock a nd Tngger Ri se and Fa ll Times
C!ock Setup Time
t S(TR )
T r igger Set u p Time to R ising Ed ge 01 ¢> f OI enabl ing of
Presca ler on Fo llOWi ng Rising Edge of ¢>
tW(CTH )
C lock and T rigg er High Pu lse Width
tw(CTLl
Clock and T r igger Low Pulse Width
tOH (ZC)
ZC /T O Del ay Time from RiSing Edge of (I), ZC / TO High
190
Counter and
T im er M odes
t DL(ZC )
Z C/ T O Delay T im e fromFalhng Edge of <1> . ZC /T Q L ow
190
Coumer and
Ti m er Modes
10
R ISIng Edge 01 <I> for Im m ed iate Co unt
I
I
21 0
210
Counter Mode
200
Cou nter and
Ti mer Modes
200
Coum er and
Ti m er Modes
Timer M od e
t C':: tw (ci)H) + tw(¢Ll -+ t r + tf ·
Inc rease delay by 10 nsee fo r each 50 pF Inc rease in l oading, 200 pF max imum f or da ta lines and 10 0 pF for contr o l lines.
In crease delay by 2 nsec fo r each 10 pF Increase 10 l oad in g, 100 p F max imum
RE St: T must be active f or a minimu m of 3 clock cycl es.
OU TPUT LO AD CIRCUI T
Vee
TEST POINT fR OM OU TPU T
l.!NOER TEST
Co unt er Mode
Coun t er Mode
2 tC(<1»
Notes :
+ 140
tC (t::» + 140
'SiCK }
CLKITR GO_ 3
ZC / TOO_ 2
2 1C( II' )
0-------1
R1
eR ,
f' 25 0 j.l A
~2 I KH
CR
CR I - CR 4
2
I N9 14 OR eOUIV ALE Nl
C L ~ SO pF ON Al l ?INS
CR,
CR,
59 A.C. Timing Diagram u
CLOCK
Tlmmg meaSUfe m e ntS are made at the followl n9 voltage$, unless
o
spec I fl1,d ­
"0"
Vee - .6V
.45 V
OUTPUT
20 V
.8 V
IN PU T
2 .0V
.8 V
FLOAT
"V
±O.5V
~~:~~2~n~rvvv
'"
t w(1)L).....
I
I
o therw~ $e
"1 "
__
I--.tc - -
t r .....
-4- ....
tS(I>( CS )-~
\
CE
-tf
tH le S)
_
1­
~----
-
_ts,j,(ROI
\I--'DRID)~
RO
/
- - 15" ,(0).,.-
---
- - tFI O), tHRtO)
0 0-°7
-tol( O} ....... I
I
'\
IOR O
/
-tS</'l (M 1)­
\
M1
I­
___
'D_MIIOI~
'/
.
lEI
___
o
's~IIR)I -
-
.-
EI O
-~
t s (1 EII
\
t o L {lO )
~
---P-
~----
\~
\
ilI'r
1
--+----' c ICKII-+----~. 1
-
ts(CKI -
_
/'
\
COUN TER MODEl
elK!
--. t OH( ZCI -
l~ tw (cT~)---=!
1
I
tw ICTH )_ \
1-'wICTHI- 1
TI MER MODE)
ZC/ TO O_
2
tOCKtlTI -
J
1\
-~I 'wlcTLlI~
-1'sITR' ~
TRG O_3
o
j- - tDH{IO )
60
-
t ol
/2el
l-­
f
~
o
Absolute Maximum Ratings
T~1I1peralti l e
S IOf:JSC T e , IIp.!"I Jltl(C
I\ II ~'
V,)i! Jg.: {)II
R C!{I\' d
0" (' 10
70" C
-(,5" (' to t
I ~ O" ('
Un de r Llw.
IJ IlI \V d h
"Commenl
StrcsscsJbov(' t h o~ lislt' d unde r" Absolu te Maximum
Ra t ing" IllJy <':JU)C permanent d ama ge 10 the JevI..:e
Tll l\ (\
Til (;[(lunJ
O}lW
P, )Wel 1)1»111 .11 11 )11
~l(t"~~ r ~llI l g o nl y ~IIJ I IHh:t Wlidl \l per ~ Wll1 0 1
J
th~ llcvl ~<:
- U J V \.1+7 V
JI Ih <:'s c Of ,IllY Oilier c()ndlll0n " bove th ose
lll(hlJlCU III Ih e \'pCfJI Il)IlJI ,Cc'[ 1ll1l:> ui' lh: ~ $pe~' lIi ~ a
IH)n I~ llOlllll p ll.: d FX:po <; lIre I,) Jhsulllie Ill~Xlmlim
ralllig HlIli.ii!I(llh lor C), iCllued pe llod, mJY 31'1 e~ 1
Je' ll. e rc hJb dllY
nc. Characteristics
1 A .::: 0" C to 70 G
("
V'-l = S V
Z80-CTC
._.
Parameter
Symbol
~
I
! )'}I ulllc~, (\l hcrW I ~C ~pCL; I\I.'J
...
Min
M"
-0 .3
.45
U nit
Te st C or'K:l. l lon
V
VI Le
Clock Inpu t Low V oltage
V IH C
Cloc k Input Higll Vo ltage [ 11
V IL Input Lo w Voltage
- 0 .3
0 .8
V
V ,H InpUT Hi gh Volta ge
2.0
Vee
V
VOL Output Lo w Vo ltag e
04
V
IOL = 2 rnA V OH Ou tput High Voltage
V
IOH :::: - 250 iJA
l ee
Power Supply Current
120
mA
Tc - 400 m ec
III
Input Leakag e Current
10
"A
VIN '" 0 to VCC
ILOH
TII ·State Ou t put Lea kage Curren t in Floa t
10
"A
VOU T = 2 .4 to Vce I L OL Tri·Stat e Output Lea kage Current in F loat
-10
VO UT '" O.4 V
IOHD
Da r lmgton Drive Curre nt
"A
mA
Vee - .6
Vce + .3
2 .•
- 1.5
V
V eXT - 1.5V
R eX T =- 390 11
Z80A-CTC Sy mbol
VIL C
.. ... Parameter
Cl ock Inpu t Low Vo (tiilQe
VIHC
Clock Inpu t Hlgll Vo ltage [ 1 )
V ,L
Inp ut Low Voltage
-0 .3
0 .8
V
V ,H
loout High Voltage
2.0
Vee
V
VOL
Output Low Vol tage
o.
V
VOH
Ou t put High Voltage
l ee
Power Supply Cu rre ",
120
rnA
TC - 250 nsee
' ll
Input Leakage Curr e nt
10
"A
VIN =- OtoVCC
' LOH
T rl -State OUtput Lea kag e Current in Float
10
"A
VOUT = 2 .4 to VCC
' LO L
Tr l-St ate Ou tput Leakag e Cu rrent In Floa t
Darli ngton Dr ive Curren t
"A
rn A
V OUT ::: O.4 V
'OH O
Min
Mox
Unit
Test Con dition
~
I
I
-0 .3
.45
Vee -6
Vee + .3
V
V
V
2 .4
-10
-1 .5
-­
--_.
IO L
z
2 rnA
IOH :::: -2 50 pA
VeX T
= 1.5V
R EX T ; 390<1
Capacitance
TA=2 S' C,f= I MHz
Sy mbol
Parame ler
Max.
Un il
Test Condition
C."
Clock Ca paci tance
20
pF
Unmeasured Pins
CIN
In put Capacnance
5
pF
Returned 10 Grou nd
COUT
Output C:Jpa cil:Jllce
pr
10
-
61 -
I
Package
Configuration
Package Outline
.".
"
o,
~
~
'"
"'..,,
I
'"0,n,
~
(.l~ TR <;;.
lCIJ(.\ 1
tUtlTMG ,
C l ~I ' "G1
Z8QA -CT C
~ CllOl
CltJT ~(l 3
",
li>h-r:.
,lo TE,.... aU oo. n
iNi
' N' {NA.II Lii I~
I I
" l:'~
~
~l
-0
'""""
"
"
""
~
[J
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ZSO- GTC
zcm't
5ti~n''') . _\
'l:.1O
<korrnm>
1 600
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___ _ ._
(-LOlli.!
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l
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EASTE R N RE GION
MI DA TL ANTI C RE GI O N
MIDWESTE RN RE G ION
SOUTHWESiERN REGION
ZVOit, I nc.
76 lreble Cove Road
No llille t1c:'l, J'o..IA 018 6 2
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1701 WooMleld Place
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Be rgenfIeld, NJ 0 76 25
l\\ X 7 109919771
10460 Dub b Road, Cup erti no, C.Hornia 950 14
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