The PixFEL project: advanced fine-pitch X

The PixFEL project:
advanced fine-pitch X-ray
pixel detectors for the next
generation FEL facilities
Valerio Re
Università di Bergamo and INFN Pavia
Workshop on
Research opportunities at the
European X-ray Free Electron Laser
Università di Bologna, July 4, 2014
PixFEL project profile
Goal of the project: high performance X-ray imaging instrumentation
for the experiments at the next generation of free electron laser
facilities
•
Small pitch active edge silicon pixel sensors
•
65 nm CMOS technology for front-end and readout electronics
•
3D integration techniques for the vertical interconnection of
sensor and readout electronics layers
Participating INFN groups
•
INFN Pavia: Lodovico Ratti, Massimo Manghisoni, Daniele Comotti, Francesco De
Canio, Lorenzo Fabris, Marco Grassi, Piero Malcovati, Valerio Re, Gianluca
Traversi
•
INFN Pisa: Giuliana Rizzo, Giovanni Batignani, Stefano Bettarini, Giulia
Casarosa, Francesco Forti, Marcello Giorgi, Eugenio Paoloni, Fabio Morsani
•
INFN Trento: Lucio Pancheri, Gian-Franco Dalla Betta, Giorgio Fontana,
Ekaterina Panina, Giovanni Verzellesi, Xu Hesong
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m
m
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Beam-line and beam-time structure
Beam lines with different photon energies
available at each facility
Beam-line structure @Eu-XFEL
Very different beam structure from one
FEL facility to the other
Each pulse is always very short
LCLS: continuous operation @ 120Hz
XFEL: 220ns spacing, with time to readout
Future (i.e. LCLS II): continuous 1MHz
spacing
Most challenging for detectors are XFEL & LCLS II, taken as target for PixFEL
Today: LCLS, …
Eu-XFEL
Tomorrow: NGLS/LCLS II
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Pixel detectors at X-ray FELs: great expectations…
From Report of Working Group on XPCS experiments at
XFEL (2010):
The required angular resolution of the detector is 23 µrad. In order to achieve this resolution a pixel size
well below 100 μm plus a transverse floor space of at
least 10 m in the experimental hutch is required.
….
In order to obtain a significant counting statistics in
an acceptable time 108 pixels are required.
…..
The frame rate should be as high as possible under
these specifications.
Ideal pixel
detector
From P. Siddons
Various physical and
fiscal realities
conspire to prevent
this being realized.
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…XFEL Instrumentation: the real devices
Although each experiment at FELs may require a specific detection system, two
main scientific case may be identified
• energy sensitive detectors with Fano limited energy resolution for
spectroscopic experiments, possible position sensitivity for angular dispersive
experiments (0D or 1D)
• silicon drift detectors
• high-Z detectors
• cryogenic detectors
• area detectors for imaging
experiments, based on X-ray
diffraction (2D)
• charge coupled devices
• hybrid pixel detectors
• monolithic active pixel sensors
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Problem of missing data
Modules of limited size and gaps
between modules è lots of missing data
Reconstruction may become ambiguous
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Microelectronic technologies and XFEL instrumentation
Potential benefits of new microelectronic technologies to
future detector systems for X-ray imaging at free electron
laser facilities:
§ Reduction of pixel size (100x100 mm2 or even less),
presently limited by the need of complex electronic
functions in the pixel cell
§ Larger memory capacity to store more images (ideally,
2700 frames at 4.5 MHz every 100 ms)
§ Advanced pixel-level processing (1 – 10000 photons
dynamic range, 10-bit ADC, 5 MHz operation)
§ 4-side buttable tiles for a large area detector with
minimum or no dead area
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Long term goal of PIXFEL
Develop a four-side buttable module for the assembly of large area detectors with
no or minimum dead area to be used at FEL experiments
Good efficiency
up to 10 keV
9 bit resolution
(effective), 5 MHz
sampling rate
wide dynamic range (1 to
10000 photons), single
photon sensitivity
burst and
continuous
mode
operation
1 kframe
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PixFEL detector specifications
q Extremely wide dynamic range, from 1 to 104 photons at fixed energy,
which may change between about 1 keV and about 10 keV according to
the specific experiment;
q single photon resolution capability at low energies (up to about 100
photons);
q a pixel side of 100 µm, which can be reasonably assumed to satisfy the
spatial resolution specifications for a wide range of experiments at
FELs;
q capability of recording one image every 200 ns and to store on chip as
many images as possible, since no direct readout can be performed at
event rates in the MHz range; the goal is a front-end full capacity of
103 images;
q tolerance to very high ionizing radiation doses, even exceeding 10 MGy,
especially close to the central hole of the detector.
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PixFEL technologies: active edge pixel sensors
•
trench etching
•
trench polysilicon filling
•
support wafer removal
metal
p+
oxide
n/p distance
n+
polysilicon
Active edge pixel sensors were
proposed to minimize the gap
between the active area and the
edge of the detector; key steps
Field plate
passivation
Bondanneal oxide
Support wafer
Thickness ≥ 450 µm needed for good
efficiency @10 keV
5 mm
n+
Field plate
n/p gap
p+
Trench edge
n- substrate
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The
active
edge pixel
sensorfor
for
FEL(1)
applications
Active
edge sensor
optimization
FELs
TN
•
Active edge sensor to minimize dead area between tiles.
Key steps:
•
trench etching/polysilicon filling/support wafer removal
• Already under development by FBK for Alice and Atlas,
but specific optimization for FEL needed.
• Main difference/issues:
1. Plasma effect: high charge concentration from huge signal
(10^4 photons 1 keV à 2.8x10^6 e-/h>100 MIP) reduces
the collection field and deteriorate charge Collection
Distance (CD) and Collection Time (CT)
à High bias voltage needed but breakdown voltage might be
critical for active edge sensor!
5 mm
n+
Field plate
n/p gap
p+
Trench edge
n- substrate
• TCAD simulation results:
à High Bias voltage mitigates plasma effect: with Vbias=400 V
can reach our target design à coll dist < Pitch=100 µm Coll
Time~30 ns.
– Edge geometry optimized to increase edge breakdown
voltage:
• Edge distance & floating guard rings,
• field plate & oxide thickness
• Vbreak > 400 V obtained even after 1GRad
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e from the injection point for 95% charge
PixFEL enabling technologies: 65 nm CMOS readout electronics
• Mature technology:
– Available since ~2007
• High density and low power
– High density vital for smaller
pixels and increased data
buffering during bunch trains
– Low power tech critical to
maintain acceptable power for
higher pixel density and much
higher data rates
• Long term availability
– Strong technology node used
extensively for
industrial/automotive
• Significantly increased density,
speed, and complexity compared to
previous generations!
A 50 µm x 50 µm mixed-signal pixel cell
readout for the phase II upgrade of LHC in
65 nm CMOS
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PixFEL detector design and technology
Multilayer device: active edge thick pixel sensor, two tiers
CMOS readout chip (analog+digital/memory), fabricated in
65 nm CMOS, to increase memory and functionality in a small
pixel pitch of 100 µm.
V DD
W
L
• Wide dynamic range, 1-104:
à Preamplifier with gain compression
in
• A/D conversion in 200 ns
à Successive approximation 10 bit ADC
• Pitch: 100 µm
200 mV
à 65 nm CMOS readout chip to increase
functional density
• Readout and memory: 1k frame depth
à Use 3D integration to increase depth by
adding a memoryV.layer
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PixFEL enabling technologies: 3D integration
• 3D electronics: “the vertical integration of thinned and
bonded silicon integrated circuits with vertical
interconnects between the IC layers.”
• 3D integration makes it possible to stack and
interconnect silicon layers fabricated in
different technologies, each optimized for its
function
• Through-silicon vias (TSV) are a key technology
ingredient for 3D integration
Through Silicon Via
(TSV)
An example: “via last” process for 3D integration of 2
layers in heterogeneous technologies (CMOS chip +
high resistivity sensor), 4-side buttable device with low
density interconnections (pitch > 50 µm) in the device
periphery (tested in the AIDA project).
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Technologies for through-silicon vias (TSV)
Low density TSVs for chip to PCB bump-bonding
No gaps, no need for
complicate tiling
(provided that the
detector has minimum
dead area)
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T-Micro
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PIXFEL Work Packages (3-year program)
WP1: Enabling technologies (Lucio Pancheri, UNITN and INFN TN) – will
investigate the technologies with potential to enable the fabrication of advanced
2D X-ray imagers to be used at FELs; the activity will mainly focus on active edge
pixel sensors and low density through silicon vias, as the most important
processes for the fabrication of a four-side buttable chip.
WP2: Building blocks (Massimo Manghisoni, UNIBG and INFN PV) – will address
the design of the fundamental building blocks for the readout of a pixel
detector in a 2D X-ray imager to be operated at FELs, and concentrate on the
development of individual stages and with their integration in a single tier 8×8
matrix at first, and with the design of a 32×32, single tier matrix to be
interconnected to a fully depleted pixel sensor in a later phase of the WP
WP3: Architectures and testing (Giuliana Rizzo, UNIPI and INFN PI) – will deal
with a two-phase task: study of the readout architecture for the X-ray imager
front-end chip; development of the hardware and software test systems and
the placement of the final characterization of the detector in a beam line
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Front-endchannel
channelindesign
(2) PV
The analog front-end
the pixel
readout cell
SR
Vref
G
C f0
S3
S1
W/L
CF
V DD
9W/L
S4
S0
SH
gnd
1 keV / 10 keV
S2
b0
-
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-
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10-bit
ADC
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Good preliminary results from simulation of the full
front-end channel with 50 ns integration time:
• ENC=50 e rms à S/N=5.5 for single photon 1 keV
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V. Re - PixFEL – Workshop on European XFEL, Bologna, July 4, 2014F ig. coming
1 keV phot ons signals at 5 M Hz t iming operat ion.
Gain compression in the preamplifier
Wide dynamic range front-end channel
• 1-104 photons between 1-10 keV
• Bilinear Amplifier: use the non-linear features
of MOSFET capacitors to dynamically change
the gain with the input signal amplitude
•
W/L
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High gain for low energy & Low gain for high energy
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Building blocks of the analog front-end electronics: bilinear amplifier
SR
Vref
G
Design in a 65 nm CMOS technology
C f0
W/L
9W/L
gnd
1 keV / 10 keV
Vin
-
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Building blocks: 10-bit A-to-D converter
9 effective bits (guarantees single photon
resolution at small signal, small quantization
noise in Poisson-limited regime), 5 MHz
sample rate (for operation at the Eu-XFEL)
SAR ADC
Critical points are power
dissipation, area, clock distribution
and readout speed
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Readout architectures
No sparsification technique can be applied to imaging detectors à a large
amount of data needs to be read out in a relatively short amount of time,
also depending on the structure of the X-ray beam
Burst mode operation: data need to be stored locally and read out in the
interval between two bursts; 65 nm CMOS technology is supposed to
guarantee enough density to exceed the state-of-the-art of FEL
instrumentation in terms of storage capacity
Continuous operation: data are read out as soon as they are collected,
frame by frame. For FELs operated in continuous mode at a relatively low
repetition rate (~100 Hz) direct readout of a megapixel detector is a task
within reach of present technology. For higher repetition rates (Eu-XFEL,
LCLS-II), high speed features of scaled CMOS processes and advanced
readout strategies have to be exploited.
The capability of switching from one mode of operation to the other may
be an important asset for a 2D imager
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In-pixel logic & readout
Pixel cell
Concept for matrix readout
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Conclusion
The PixFEL project will be the first step towards the
ambitious goal of developing a new pixelated X-ray
camera with high space, time and amplitude resolution for
applications to photon science at X-ray FEL facilities
The aim is to improve the current state-of-the-art of
pixel X-ray cameras for FELs by applying the more recent
technologies for pixel detectors in high energy physics
(65 nm CMOS, 3D integration, active edge pixel sensors)
The ultimate goal is to provide FEL experimenters with a
novel instrument to be used at the more advanced
facilities: XFEL, LCLS, LCLS II(NGLS)
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Backup
21 cm (1024 pixels)
DSSC X-ray camera
x-y Gap
•
1024x 1024 pixels
•
16 ladders/hybrid boards
•
32 monolithic sensors
128x256 6.3x3 cm2
•
DEPFET Sensor bump
bonded to 8 Readout
ASICs (64x64 pixels)
•
2 DEPFET sensors wire
bonded to a hybrid board
connected to regulator
modules
•
Dead area: ~15%
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Problem of missing data
Modules of limited size and gaps between
modules è lots of missing data
Reconstruction may become ambiguous
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Aim of the PixFEL project
Investigating the enabling technologies for the design of chips with
minimum dead area and high functional densities
• standard and slim edge sensors
• vertical integration for double tier design of the front-end
• low density TSVs for chip interconnection to the hybrid board
• interposers for sensor to front-end pitch adaptation
Studying, designing and testing the building blocks (CMOS 65 nm) for the front-end
electronics (100 um pitch), complying with the application requirements
• low noise, (reconfigurable) wide input range front-end channel (1 to 104) with
dynamic compression, single photon detection
• 9 bit (effective), 5 MS/s ADC (successive approximation register)
• circuits for gain calibration
Looking into architectures for fast chip operation and readout
• frame storage mode (memory cell, maximum memory size, readout)
• continuous readout mode (maximum speed, accounting for DAQ limitations)
• reconfigurability (impact on the performance)
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PixFEL enabling technologies: 3D integration
Current situation
SENSOR
Desired situation
SENSOR
ASIC 1 (ampl)
ASIC 2 (ADC)
ASIC
Bulk
ASIC 3 (Storage)
ASIC 4 (I/O)
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Plans and Milestones
2014
• Specification of the 2D X-ray imager
• Design and submission of wide input range amplifier with bilinear feature
• Design and submission of a 9 bit SAR ADC
• Design and submission of slim edge and fully depleted pixel sensor structures
2015
• Test of the amplifier and ADC submitted in the first year
• Test of the pixel sensor submitted in the first year
• Design and submission of a thick active edge pixel detector
• design of a 32x32 chip with 100 um pitch
2016
• Test of the 32x32 readout chip
• Test of the thick active edge pixel detector submitted in the second year
• Interconnection of the 32x32 readout chip to a pixel sensor and test of the
structure
• VHDL description of the readout architecture
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