SOC Design - Circuits and Systems

VLSI SOC Design ET4351
Rene van Leuken
EWI/MECE/CAS
http://ens.ewi.tudelft.nl/Education/courses/et4351/index.ph
p
http://ens.ewi.tudelft.nl/Education/msc_projects.php
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Goal
• The aim is of the course is to address important
aspects of SoC design methodology issues.
Including: 1) Algorithm to specification 2) Low
power digital design issues, 3) On-chip system
IP high level interconnect issues, 4) Hardware
<-> software interaction issues
• Synthesis based digital design from a language
description: SystemC, SystemC-AMS, C++,
VHDL, …
• Prototyping in FPGA boards
• Semi-custom VLSI design (UMC, TSMC)
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Content
• Topics covered among other: optimization and
reduction techniques, Low power interconnect,
SoC design methodology, modelling,
specification and implementation,
communication architecture and protocols.
• Modern design starts from a C-based
description (System-C/AMS) or behaviour
description through synthesis tools to an FPGA
implementation.
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Web Server
• All information is on:
ens.ewi.tudelft.nl/Education/courses/et4351
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Books i
• Understanding Behavioral Synthesis, A practical
Guide to High-Level Design, John P. Elliot,
Kluwer Academic Publishers Study material ISBN: 079238542X
• Digital Systems Design with VHDL and
Synthesis: An Integrated Approach, KC Chang
ISBN: 0769500234
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Books ii
• Low-Power Electronics Design by Christian
Piguet (Editor), ISBN: 0849319412
• Essential VHDL - RTL Synthesis Done Right, by
Sundar Rajan ISBN: 0966959000
• A SystemC Primer, J. Bhasker, ISBN 0-96503918-8
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Schedule 2014
April 22 Tue. Introduction/content
April 25 Fri. Structured VHDL design
May 6 Tue. Communication, busses, Wishbone, NoC
May 9 Fri. SystemC, C++, Examples
May 13 Tue. SystemC TLM and SystemC AMS
May 16 Fri. Low power design, communication
May 20 Tue. ASIC flow (Cadence, Synopsys)
May 23 Fri. Introduction and division of projects
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Basic architecture
DSP/Compute
block
processor
Instruction
program
bus
peripheral
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Soc: Block schema
wb_SoC
IMEM
mbl1c_core
address_decoder
sys_ctrl
mst_wb_adapter
DMEM
wb_mbl1c
wb_slave
Communication: Wishbone
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Communication: Wishbone
www.opencores.org
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Wishbone timing
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Projecting the future
04/10/12
Sept. 10, 2009
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PATMOS 2009
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3D stack of MPSoc and NoC's
TSV 3D chips
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3D Stacking
IBM 2012
Circuits and Systems
MPSoC Architecture
●
●
●
●
2D or 3D, architectural challenges are
similar
Raw execution performance:
–Task scheduling/mapping/load-balancing
– where to execute what, and when
Memory Hierarchy:
–What data to keep on-chip?
–How to improve the efficiency of on-chip
caches?
Interconnect:
–How to reduce transfer latency, maintain
high throughput
–How to build in adaptability, redundancy,
security
Circuits and Systems
Assignments i
• All tasks have the goal to design and simulate some
hardware function, part of a SoC, and possibly to test
functionality on the Spartan 3 board.
• Language: VHDL or SystemC (C++)
• Exercises are grouped around the Xilinx MicroBlaze SoC
and the Avnet Spartan 3/6 board.
• Three themes: DSP (Image) and communication.
• Students grouped evenly for the themes!
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Assignments ii
• All tasks /themes are the ‘same’
• Start with an algorithm, e.g. C Code or Matlab
• Design an hardware architecture; in VHDL or SystemC
• Your datapath
• Wishbone interface
• Power saving method?
• All modules will have a Wishbone bus interface
• Verify/simulate your design; Use the bus emulator package,
download from website;
• Synthesize your design
• In case IO theme: program FPGA and check communication
• Write report.
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Theme Image
• Gray scale image operations
• C code template code from “Practical
algorithms for images analyses”, Michael Seul.
• Image binarization.
• Integer or fixed-point operations.
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Image picture
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Otsu's Algorithm
Otsu's method is used to automatically perform clusteringbased image thresholding or, the reduction of a graylevel
image to a binary image. The algorithm assumes that the
image to be thresholded contains two classes of pixels or bimodal histogram.
Algorithm
Compute histogram and probabilities of each intensity level
Set up initial and
Step through all possible thresholds maximum intensity
Update and Compute
Desired threshold corresponds to the maximum
You can compute two maxima (and two corresponding thresholds). is the greater
max and is the greater or equal maximum
threshold
C/C++ designs using ViVado HLS
C/C++ designs
Vivado HLS Estimates
Vivado HLS Scheduling
Theme ASIC
ASIC (semi custom) realization of a chip.
Existing VHDL code of a design: Xilinx MicroBlaze
Use Synopsys Design compiler and Cadence SoC
Encounter.
The goal is to 'map' the filter design to a semicustom cell library (Faraday SP90) and by using
SOCE place and route the design.
Design steps include: simulation, synsthesis (DC),
IO port design, power planning, clocktree
generation, P&P and GDS2 (SOCE) generation.
The result is a GDS2 file, which in principle could be
fabricated at a silicion foundry.
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The power plan of the ASIC. Rings, stripes,
block halo and the selected floorplaning
are visible
View of the routed, verified and
finalized ASIC
UMC 90nm Realization
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LowPower async 8051
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Theme Communication
•
•
•
•
Communication interface processor.
Ethernet: DM9000E
High level communication chips.
VHDL and embedded C - and Host processor C
code.
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FPGA board: Spartan 3
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http://www.em.avnet.com
DM9000E board
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DM9000E video
Assignments Procedure
• Select a topic and discuss it with me
• Design the IP block (hardware/software)
• Result = simulation, or in some cases implementation in
FPGA, C code software
• Write report: what/why/how/results. This typically a 4 to 10
page report.
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Reactions 1
This labwork was much bigger and took much more time than I expected
it to do. On the web site of the course an estimation of 20 hours is given,
and I thought that I would have needed at least twice as much. I turned
out it took much longer than my own estimates. This might be due to the
fact that I worked alone. Besides the fact that it took a lot longer than
expected, I really enjoined the work itself. It gave me huge satisfaction to
see that at the end it was working well. I was also talking one day with a
man that is Computer Engineer in Italy, and we came in the discussion
about this labwork I was doing and it was very pleasant to hear that this
is the kind of work that he sometimes has to do in real life. It gave me
the feeling that all the courses and professors are really preparing me for
a job or research. I learned a lot during this lab course. First of all I had
never programmed in VHDL on such high level. I learned a lot about
VHDL and about approaching such an assignment. I also learned much
about the Wishbone bus interface and about C, for example about
arithmetic and logical shifts in C. I learned also a lot about simulating
with Modelsim and synthesizing with Synplify Pro. It will certainly be
useful in the future to know my way around in these programs. Last but
not least, I think I learned again to hold on. At some times I thought I
would never finish the job, and the strange values in the simulation kept
coming. I learned that I could do it if I just hold on and tried to debug it
by looking in completely other ways at my design. I think this will be the
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most valuable lesson for the future.
Reactions 2
In the end we can say that the project went quite
well. The assignment was clear and we were able to
formulate a concept in the first meeting. Once we
fully understood the SoC templates we started
coding our bridge module. After successfully
simulating our design we tidied up our code to
include our latest VHDL coding ideas. We
experienced some trouble creating the bit file, but
once we got the latest ISE we were in business and
able to test our design on the development board.
Our first try was not completely right but after some
puzzling we realized that we did not map the reset
functionality.
The second try was successful. We both experienced
this small project as a welcome exercise for our
digital design and VHDL coding skills.
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Reactions 3
We really liked working on this project, because we both
are very interested in (embedded) hardware/software codesign.
This project also master VHDL a lot more. We were
already experienced with VHDL, but by doing projects of
this size one gains more experience.
The project took us a lot more time than the 20
prescribed hours (multiples of it), but because we liked
the subject we didn’t care about that too much. Although
we would have liked it to test the design on our Spartan3E (XC3S500E) FPGA boards, we couldn’t find the time to
do this.
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