docCMP Enables New TFT Architecture for 3D Monolithic Flash Memory
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CMP Enables New TFT Architecture for 3D Monolithic Flash Memory
CMP Enables New TFT Architecture for 3D Monolithic Flash Memory Robert L. Rhoades (Entrepix, Inc.) Andrew J. Walker (Schiltron Corporation) NCCAVS CMPUG July Meeting Semicon West - July 2009 Outline Background and Drivers for Monolithic Flash Memory The Schiltron Design CMP Targets and Partial Process Flow First Run Data Summary and Next Steps Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 2 Background • Scalability of the floating gate approach for NAND Flash appears to be coming to an end – Floating gate interference, inability to scale tunnel oxide, and interpoly dielectric scaling fails – Issues likely insurmountable in range of 20 – 30 nm • Some are proposing Charge Trap Flash (CTF) – TANOS – Bit-Cost Scalable (BiCS) Flash Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 3 Challenges with CTF Inversion Layer To Bitline Vread-pass N+ Vread N+ • Vread-pass > Vtprog + margin • Vprog-pass > Vtprog + margin Vread-pass ONO N+ N+ Pass disturbs on selected string • Apply to both lateral and vertical NAND CTF Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 4 Wish List for 3D WISH LIST FOR 3D MONOLITHIC FLASH • Laterally scalable • Easily stackable • Reasonable program/erase voltages • High program bandwidth • Good endurance • Good retention • MLC capability • All at low cost Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 5 Schiltron Design Vread Inversion Layer To Bitline N+ N+ N+ N+ 1st Gate Vread-pass • 2nd Gate ONO Off Vread-pass Double-gate approach – Close electrostatic interaction for short channel control and lateral scalability – Electrical shielding of memory charge from pass voltages Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 6 Double-Gate TFT Gate2 Vs Vds Source Drain Inversion channel Gate1 Vgs Source Depletion region Electric field lines Gate1 dielectric Gate1 Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 7 Design Advantages • Advantages of the Schiltron dual-gate design – – – – – – Laterally scalable with DG structure Near zero pass disturbs Worst-case string current decoupled from Vread-pass Thin ONO Uses well-known materials and existing processes Easily stacked for 3D density Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 8 Physical Structure 48nm gatelength CMP2 350 A channel thickness CMP1 Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 9 Process Flow • Active devices based on vertical dual-gate TFT • Si wafer is primarily a mechanical support surface (not part of active channels) • All materials and process methods are already in high volume Si device production Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 10 CMP Targets • Two critical levels in prototype process flow – Polysilicon CMP, stop on oxide (Gate 1) – Amorphous silicon CMP, stop on oxide (channel) • Process targets on both polySi and a-Si – – – – Reasonable polish times Planarization with low dishing on critical features Minimal oxide loss (selectivity > 10:1) Excellent surface finish (low Ra, no defects) • Initial process adapted from previous experience with similar materials in different applications Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 11 Process Flow HDP Oxide Nitride etch stop on oxide Silicon wafer Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 12 Oxide trench etch and poly dep Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 13 PolySilicon CMP1 (forms GATE1) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 14 After CMP1 After polysilicon CMP1 (forms GATE1) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 15 X HDP oxide dep and channel trench etch Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 16 In Process SEM 32 cell string after channel trench etch Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 17 X Gate1 oxide formation and channel a-Si dep Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 18 X a-Si CMP2 (forms active channels) Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 19 After CMP2 Over 13 wafers: 16nm average oxide loss with 3sigma of 6nm Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 20 X ONO formation Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 21 X GATE2 deposition Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 22 X GATE2 litho & etch Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 23 In Process SEM 64 cell string after 2nd gate formation Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 24 Ready for next stack X Source/drain implant and low-temp anneal Y Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 25 Physical Structure CMP2 CMP1 XTEM perpendicular to wordline gate direction Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 26 Physical Structure CMP2 CMP1 XTEM perpendicular to channel direction Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 27 CMP Summary Table Parameter CMP 1 CMP 2 Nominal Film Thickness 5000 Ang 2400 Ang Avg Polish Rate 2450 Ang/min 2300 Ang/min Avg Final Step Height < 200 Ang (Most features < 75 Ang) < 150 Ang (Most features < 50 Ang) Final Ra (polySi or a-Si) < 10 Ang < 8 Ang Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 28 1st Run Data Source-Drain Current (A) Electrical Results – Single DG Device 10-6 4V 3V 10-7 2nd 2nd Gate Voltage 2V 10-8 -4V 1V -3V 10-9 -2V 10-10 W/L = 50nm/65nm 0V 10-11 1st dch ~ 35nm -1V Vds = 0.5V 10-12 -2 -1 0 1 2 3 4 5 1st Gate Voltage (V) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 29 Programmed Memory Cell N+ N+ 2nd Gate Vt (V) Pass Disturb 4 3 2 1 0 1 Vpass = 9V 10 100 1000 Duration of 9V Application to 1st Gate Stored charge is immune to pass voltages Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 30 Worst Case String Current 64 cell Dual-Gate string (W/L = 45nm/48nm Devices) OFF Bit Line Midcell Gate voltage ON with read pass voltage OFF Source ON with read pass voltage OFF Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 31 Worst-Case String Current (A) String Current Data 64 cell string W/L = 45nm/48nm dch ~ 35nm Vds = 1V 10-7 8V 7V 6V 5V 4V 3V 10-8 Read-pass V 2V 10-9 Mid-cell 1st gate at -3V All memory devices off except mid-cell 10-10 -1 0 1 2 3 4 5 2nd Gate Voltage on Mid-Cell (V) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 32 Worst-Case String Current (nA) String Current Data Read-pass V 200 180 160 140 120 100 80 60 40 20 0 64 cell string W/L = 45nm/48nm dch ~ 35nm Mid-cell 1st gate at -3V Mid-cell 2nd gate at 3V All other memory gates off 8V 7V 6V 5V 4V 3V 0 0.5 1 1.5 2 String Source-Drain Voltage (V) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 33 Worst-Case String Current (nA) String Current Data 800 700 600 String Length W/L = 45nm/48nm dch ~ 35nm Mid-cell 1st gate at -3V Mid-cell 2nd gate at 3V All other memory gates off 8 cells 500 16 cells 400 300 32 cells 200 64 cells 100 0 2 4 6 8 Read-Pass Voltage (V) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 34 Mid-Cell Threshold Voltage (V) Cycling Endurance 4 3.5 W/L = 45nm/48nm 32 cell string dch ~ 35nm Vprog/Verase = 17.5V 100us / -13V 400ms Read-pass voltage = 7V Program-pass voltage = 7V Erase-pass voltage = 6V 3 2.5 2 1.5 1 10 100 1000 10000 100000 Number of Cycles Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 35 4 After 105 cycles 3.5 3 10 years 2.5 2 1.5 1 1.0E+09 1.0E+08 1.0E+07 1.0E+06 1.0E+05 1.0E+04 1.0E+03 1.0E+02 0 1.0E+01 0.5 1.0E+00 Threshold Voltage (V) Retention after Cycling Time at 85oC (s) Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 36 Summary • Schiltron DG-TFT-SONOS: – – – – – – – – Laterally scalable due to DG structure Easily stackable (within thermal budget for multiple levels) Reasonable program/erase voltages High program bandwidth Good endurance and good retention both demonstrated MLC capable due to disturb stability Two critical CMP levels already capable of meeting targets CMOS-friendly materials and processes used throughout • Next Steps – Scale up to functional chips (size tbd) – Prepare for initial prototype production ramp Our Expertise, Our Services, Your Success NCCAVS Summer Meeting - Semicon West 2009 37
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