Breakthrough 3D RRAM - Flash Memory Summit

Breakthrough 3D RRAM - Flash Memory Summit

Breakthrough 3D RRAM
Technology for super-dense, low latency,
low power data storage systems
Hagop Nazarian
Co-Founder VP Engineering, Crossbar Inc.
Flash Memory Summit 2014
Santa Clara, CA
1
Agenda
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Introduction
Architectural RRAM Classification
The Sneak Path Barrier
Crossbar RRAM with High Selectivity Ratio
Crossbar 1TnR Characteristics & Benefits
• Area vs selectivity ratio
• Power vs selectivity ratio
• Latency vs 1TnR architecture
 Summary
Flash Memory Summit 2014
Santa Clara, CA
2
Architectural RRAM Classification
1TnR with Non-Linear RRAMs
1T1R with Linear RRAMs
One Access transistor for many RRAMs
One Select transistor per RRAM
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
Suited for low
latency, high speed
embedded memory
operation or high
performance NOR
products
Cell size dominated
by the select
transistor
Flash Memory Summit 2014
Santa Clara, CA
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Suited for high density
high performance memory
(NAND/SCM memory)
3D architecture
Under array utilized for
peripheral circuits yielding
high array efficiency
𝐶𝑒𝑙𝑙 𝑎𝑟𝑒𝑎 =
4𝐹2
# 𝑅𝑅𝐴𝑀 𝐿𝑎𝑦𝑒𝑟𝑠
3
The Sneak Path Barrier with RRAM
1.5v
3v
1.5v
1.5v
1.5v
3v
1.5v
1.5v
Current
3v
1.5v
0v
Ion/Ioff=1
1.5v
Iread/Prog
1.5v
1.5v
Vread

Volts
When the array size increases:
•
•

Vprog
Programming or Erase power consumption increases – this will demand large decoding transistors and impact
silicon area
During Read sensing margin will be quickly diminished - Ion/(Ioff+Ileak) ratio decreases
Not possible to make high density, high performance, & efficient arrays with linear resistive cells
Flash Memory Summit 2014
Santa Clara, CA
4
A Non-Linear RRAM with High Selectivity
3v
1.5v
3v
1v
1.5v
1v
3v
1.5v
Ion
1.5v
𝑰𝒐𝒏
HSR=
𝑰𝒔𝒖𝒃𝒗𝒕
1.5v
0v
Isubvt
1.5v
1.5v
𝑉𝑒𝑟𝑎𝑠𝑒
−𝑉𝑇
1.5v
𝑉𝑟𝑒𝑎𝑑
+𝑉𝑇
𝑉𝑝𝑟𝑜𝑔
∆𝑉𝑢𝑛𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑
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A device with very high selectivity is needed to suppress the sneak path current
in large arrays
Selectivity feature of the device will activate the cell based on the potential across the
two terminal RRAM cell
Selectivity ratio is measured by HSR (Half Select Ratio).
Flash Memory Summit 2014
Santa Clara, CA
5
Crossbar RRAM with Superior
Selectivity Ratio
 Crossbar demonstrates
a device with an HSR
selectivity ratio of >1E6
 Eliminates sneak path
and provides:
• Super high density
Terabyte devices with
1TnR architecture
• Low energy
write/read operations
Ion
Ion
Selected
cell ON/OFF
Ioff
Ioff
HSR=1E6
Non-selected cells
stay in this region
Isubvt
• High performance
with very low latency
Flash Memory Summit 2014
Santa Clara, CA
6
Array Bank Size (Mbit)
Huge Array Capacity with High HSR
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1
0.5
0.25
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
HSR (Selectivity Ratio)
Large HSR enables super high density products with high array efficiency
**Requirements: 20mA programming ICC budget with 2048bits program simultaneously
Flash Memory Summit 2014
Santa Clara, CA
7
Low Power Consumption with High HSR
1.0E+06
Current Consumption (mA)
1.0E+05
1.0E+04
1.0E+03
1.0E+02
1.0E+01
1.0E+00
16
32
64
128
256
512
1024
2048
4096
8192
16384
Array Bank Size (Mbits)
HSR=40
HSR=400
HSR=4000
HSR=40000
HSR=400000
HSR=1000000
Large HSR enables low power and high density products, significantly
reducing the sneak path and power consumption
Flash Memory Summit 2014
Santa Clara, CA
8
Superior Performance with High HSR
100
50us NAND FLASH
Access time (us)
10
1
0.1
0.01
1
501
1001
1501
2001
2501
3001
3501
4001
4501
n of 1TnR
•
•
Large HSR enables 1TnR architecture suited for high
performance high density products
25X performance advantage over traditional NAND
Flash Memory Summit 2014
Santa Clara, CA
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Summary
 Crossbar demonstrates RRAM
with >1E6 selectivity ratio
 Crossbar RRAM resolves the
Sneak-Path Barrier enabling:
• Super high density arrays
• Low power consumption
• High performance products
 All in one product architecture
Flash Memory Summit 2014
Santa Clara, CA
10