3D ReRAM with Field Assisted Super-Linear Threshold

3D ReRAM with Field Assisted Super-Linear Threshold

3D ReRAM with Field Assisted Super-Linear Threshold
(FAST TM) Selector Technology
FO R SUPER DENSE, LO W PO W ER, LO W LAT ENC Y DATA
STORAGE SYST EM S
S U N G H Y U N J O , TA N M AY K U M A R , M E H D I A S N A A S H A R I , W E I D . L U , H A G O P N A Z A R I A N
C R O S S B A R I N C , S A N TA C L A R A , U S A
3D ReRAM FAST TM Selector Technology
• ReRAM Architectures
• ReRAM FAST TM Technology
• ReRAM FAST TM Device Performance
• ReRAM FAST TM System Performance
2
Architectural ReRAM Classification
1T1R with Linear ReRAMs
One Select transistor per ReRAM
• Suited for low latency,
high speed embedded
memory operation or
high performance
NOR products
• Cell size dominated by
the select transistor
ASP-DAC 2015
1TnR with Non-Linear ReRAMs
One Access transistor for many ReRAMs
 Suited for high density
high performance memory
(NAND/SCM memory)
 3D architecture
 Under array utilized for
peripheral circuits yielding
high array efficiency
 𝐶𝑒𝑙𝑙 𝑎𝑟𝑒𝑎 =
4𝐹2
# 𝑅𝑅𝐴𝑀 𝐿𝑎𝑦𝑒𝑟𝑠
3
The Sneak Path Issue with ReRAM
3v
1.5v 1.5v
1.5v 1.5v
3v
1.5v
1.5v
1.5v
Current
3V
1.5v
0v
IRead/Prog
𝐼𝑜𝑛 𝐼𝑜𝑛
< 500
1
=
10
=
100
𝐼𝑜𝑓𝑓
+
𝐼𝑙𝑒𝑎𝑘
𝐼𝑜𝑓𝑓
1.5v
1.5v
1.5v
Vread
Volts
Vprog
• When the array size increases:
• Programming or Erase power consumption increases – this will demand large decoding transistors and impact
silicon area
• During Read sensing margin will be quickly diminished - Ion/(Ioff+Ileak) ratio decreases
• Not possible to make high density, high performance, & efficient arrays with linear resistive cells
4
A Non-Linear ReRAM with High Selectivity
3v
1.5v
3v
1v
1.5v
1v
3v
1.5v
Ion
1.5v
𝑰𝒐𝒏
HSR=
𝑰𝒔𝒖𝒃𝒗𝒕
1.5v
0v
Isubvt
1.5v
𝑉𝑝𝑟𝑜𝑔
1.5v
1.5v
−𝑉𝑇
𝑉𝑒𝑟𝑎𝑠𝑒
𝑉𝑟𝑒𝑎𝑑
+𝑉𝑇
∆𝑉𝑢𝑛𝑠𝑒𝑙𝑒𝑐𝑡𝑒𝑑
• A device with very high selectivity is needed to suppress the sneak path current in large arrays
• Selectivity feature activates or selects a cell based on the potential across the ReRAM cell
• Selectivity ratio is measured by HSR (Half Select Ratio)
5
TM
FAST
ReRAM
Selector
Technology Characteristics
6
ReRAM + Selector (1S1R)
• Cross-point array integration of ReRAM + Selector
• High HSR & sharp switching slope of a selector
• Small voltage overhead for selector integration
-6
10
-8
10
-10
10
-12
+
-2
-1
0
1
Voltage (V)
2
10
-4
10
-6
10
-8
10
-10
10
-12
=
-2
-1
0
1
Voltage (V)
Current (A)
10
-4
10
-6
Integrated 1S1R
‘1’
Selector
Current (A)
Current (A)
10
ReRAM
-4
10
‘0’
10
-8
10
-10
10
-12
2
-2
-1
0
1
Voltage (V)
2
7
ReRAM 1R Component
• Used 1R from one of Crossbar’s 1T1R technologies
• No high voltage forming process required
1T1R prototype chip
Checkerboard pattern
1R for 1S1R
Random pattern
Byte/page
alteration
Byte/page
alteration
Current (A)
Inversed
10
-4
10
-6
10
-8
10
-10
10
-12
-2
-1
0
1
Voltage (V)
2
8
FAST TM Selector Component
• Utilizes an oxide-based Super-Liner Threshold (SLT) layer
• Bidirectional volatile on-off operation (E-field assisted)
• Ideal for bipolar ReRAM
• Formation of volatile percolation paths in SLT select layer at VTH
-4
Current (A)
10
ON Icc
-6
10
-8
10
SLT
-10
10
-12 tester noise
10
-2
VTH2
VTH1
-1
0
1
Voltage (V)
2
9
Selectivity (HSR) & Switching Slope
• Half Select Ratio (HSR, I@V/[email protected]) of > 107
• Enables larger array & reduced power consumption
• Extremely sharp switching of < 5mV/dec.
10
-4
10
-4
10
-6
10
-6
10
-8
10
-8
10
-10
10
-12
-0.8
Current (A)
Current (A)
• Offers more read voltage margin & faster read
HSR
> 107
-0.4
0.0
0.4
Voltage (V)
0.8
10
-10
10
-12
< 5mV/dec.
480
490
500
Voltage (mV)
10
Volatile Selector Switching
• Sub-50ns volatile switching and recovery times
• Conducting state @ V > VTH
• Insulating state @ V < VTH
Applied pulse
Measured current
11
Selector Cycling
• Reliable switching over 1011 cycles
-4
10
Current (A)
-6
10
VR/2 < VTH < VR
-8
@VR
@VR/2
pulse tester noise level
10
-10
10
1
10
3
10
5
7
10
10
Cycle #
9
10
11
10
12
Selector Leakage Current
• Low noise measurement confirmed the leakage current less than 0.1pA
> 1E8
13
Selector Arrays
• Suppression of leakage current confirmed in 4Mb crosspoint selector array
-5
10
Current (A)
-7
10
-9
10
-11
10
Iso Cell
100Kb
4Mb
-13
10
-1.0
-0.5
0.0
0.5
Voltage (V)
1.0
14
1S1R Cycling
Current (A)
• 1S1R cycling demonstration with large on/off memory ratio and
selectivity
10
-4
10
-6
10
-8
10
-10
10
-12
-2
-1 0
1
Voltage (V)
2
15
TM
FAST
ReRAM +
Device Performance
16
Huge Array Capacity Enabled by High HSR
8192
4096
2048
1024
Array Bank Size (Mbit)
512
256
128
64
32
16
8
4
2
1
0.5
0.25
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
HSR (Selectivity Ratio)
Large HSR enables super high density products with high array efficiency
**Requirements: 20mA programming ICC budget with 2048bits program simultaneously
17
Low Power Consumption Enabled by High HSR
1.0E+06
Current Consumption (mA)
1.0E+05
1.0E+04
1.0E+03
1.0E+02
1.0E+01
1.0E+00
16
32
64
128
256
512
1024
2048
4096
8192
16384
Array Bank Size (Mbits)
HSR=40
HSR=400
HSR=4000
HSR=40000
HSR=400000
HSR=1000000
Large HSR enables low power and high density products, significantly
reducing the sneak path and power consumption
18
Superior Performance Enabled by High HSR
100
50us NAND FLASH
Access time (us)
10
1
0.1
0.01
0
500
1000
1500
2000
2500
3000
3500
4000
4500
n of 1TnR
• Large HSR enables 1TnR architecture suited for high performance high density
products
• 25X performance advantage over traditional NAND
19
Existing NV Memory Technology Comparison
Feature
Non-Volatility
Random Read Time
Byte Write
Page Write
NOR
NAND
ReRAM
Yes
Yes
Yes
90ns -100ns
50us
70ns - NOR
1us - NAND
NO
Program page/byte
Erase large sector
No
Program page
Erase large sector
Yes, Overwrite
Yes, Overwrite
700us/256B
>1000us /8KB
(MLC)
64us/8KB
16us/2KB
2us/Byte
30ms/4KB
>2ms(Block)
Not required
105
MLC 103
108 - 1012
Cell Size
MLC/Stacking
6-8F2
MLC
SLC 5F2
MLC
SLC 4F2
Stacking, MLC
Cost
Med
Low
Very Low20
Write/Program Time
Erase Time/Size
Endurance
20
Storage System Performance
21
SSD System NAND-Based
DRAM
NAND
.....
NAND
Storage Controller
Memory Channel
ECC
Host
I/F
Buffer
CPU
NAND
I/F
.....
Host Interface
NAND
.....
NAND
Memory Channel
NAND Shortcomings: L2P Mapping, Garbage Collection,
Wear Leveling, Bad Block Management, ECC Complexity
22
22
SSD System ReRAM-Based
ReRAM
.....
ReRAM
Memory Channel
.....
Host Interface
Substantial
Reduction in
Controller
Complexity
ReRAM
.....
ReRAM
Memory Channel
ReRAM-Based SSD substantially reduces NAND shortcomings,
thus significantly reducing controller complexity
23
23
SSD System Performance with NAND & ReRAM
MLC
SLC
ReRAM
NAND bus freq DDR (MHz)
100
100
100
Bus width (bits)
8
8
8
Page Size (KB)
16
16
4
Shift Time + Overhead (us)
100
100
25
Program Time (ms)
1.5
0.3
.032
Read Latency (us)
50
25
1
3
2
1
32
53
160
Write Amplification
Effective Write xfer rate (MB/s)
ReRAM
MB/sec
NAND Spec.
SLC-NAND
MLC-NAND
Dies
• ReRAM utilizes the Maximum Bandwidth of the channel
• ReRAM provides at least 5X performance improvement
24
• Crossbar demonstrates The FASTTM device with
selectivity ratio of >1E6
• FAST+ReRAM based products provide superior
performance and architectural flexibility enabling storage
systems with:
• Super high density
Terabyte devices with 1TnR architecture
• Low energy
write/read operations
• High performance
with very low latency
• Simplified Software and Hardware infrastructure
Acknowledgements
CRO SSBAR TEAM
For further information on Crossbar’s technology, visit us at
www.crossbar-inc.com
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