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Litho and Design: Moore Close Than Moore Close Than Ever
Litho and Design: Moore Close Than Ever Vivek Singh Intel Fellow Director, Computational Lithography Technology Manufacturing Group Intel Corporation ISPD , March 2011 Gasp! V. Singh, ISPD , March 2011 2 Outline The frenetic pace of Moore’s Law, and why we put up with it! How the coco-optimization of design and lithography have enabled Moore How computational lithography is squeezing more juice out of steppers V. Singh, ISPD , March 2011 3 The Economics of Moore’s Law 1010 10 As the number of transistors goes UP 100 The $ Benefit: 10-1 108 10-2 107 Price per transistor goes DOWN 10-3 10-4 10-5 106 105 10-6 104 10-7 103 ’70 The Cost: 109 ’80 ’90 FAB PILOT LINE R&D PROCESS TEAM Source: WSTS/Gartner/Intel ’00 $4 B $1-2 B $0.5-1 B Source: Intel Investment & co-optimized execution required to maximize the benefit V. Singh, ISPD , March 2011 4 Intel’s Silicon R&D Pipeline 15 nm 22 nm Research Pathfinding 32 nm 45 nm Development Manufacturing Continuous flow of new technologies from research to development to manufacturing V. Singh, ISPD , March 2011 5 On--time 2 Year Cycles On 90 nm 2003 65 nm 2005 45 nm 2007 32 nm 2009 22 nm 2011 The image cannot be display ed. Your computer may not hav e enough memory to open the image, or the image may hav e been corrupted. Restart y our computer, and then open the file again. If the red x still appears, y ou may hav e to delete the image and then insert it again. In development V. Singh, ISPD , March 2011 6 Defect Density Trends 90nm 65nm 45nm 32nm Defect Density (Log Scale) 2001 Higher Yield 2002 2003 2004 2005 2006 2007 2008 2009 Continuing to improve wafer defect density is crucial to achieving historical yield trends V. Singh, ISPD , March 2011 7 Breakthroughs in Technology Information Turns 32nm 45nm Information Turns 65nm 90nm 2001 2002 2003 2004 2005 2006 2007 2008 1.7 X improvement in Information turns Faster information back to process development and design teams V. Singh, ISPD , March 2011 8 SRAM Cell Size Scaling Cell Area (um2) 10 65 nm, 0.570 um2 1 45 nm, 0.346 um2 0.1 0.5x every 2 years 32 nm, 0.171 um2 0.01 1995 2000 2005 2010 2015 22 nm, 0.092 um2 All Patterned with 193nm!! V. Singh, ISPD , March 2011 9 2 YEARS TICK 2 YEARS TICK TOCK NEHALEM 2 YEARS Tick--tock: an example from Intel of process Tick and design marching in cadence TICK WESTMERE Pentium® D, Xeon™, Core™ processor 65nm TOCK Core 2 processor, Xeon processor PENRYN Family 45nm 32nm TOCK SANDY BRIDGE All product information and dates are preliminary and subject to change without notice V. Singh, ISPD , March 2011 10 Design Rule Definition Process: How Litho and Design are connected 1 D Pitch target set by density goals Learning from previous process extrapolated OPC model Illumination techniques OPC/litho test masks DR Modeling And Process evaluation Modify older test chip DOF, MEEF, etc Enhancement techniques Layout studies Photo resist evaluation Design rules X test chip Product Evaluation CAD tools C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 11 Rule Stability 120.00% 100.00% X Chip Tape out Growth 80.00% in Number of 60.00% 40.00% Rules First Design Debug Ramp 20.00% Process Development 0.00% -2 -1 +2 +1 0 Relative Year C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 12 130nm SRAM Bit Variable poly pitch and line widths X and Y transistor orientation Design rule definition was primarily done through simple scaling of rules from previous generation Limited modeling of layout and design rules C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 13 90nm 47% increase in number of poly rules SRAM Bit All Devices in one orientation except SRAM Complex rules did not impact transistor density – Modeling and layout study effort increased from 130nm generation C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 14 65nm 65% increase in number of rules All Devices in one orientation including SRAM Rules to enable phase shift masks Different rules for minimum pitch, larger poly pitch and poly routing Layout more difficult but no significant density impact SRAM C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 15 Problems with 65nm poly layout Two direction routing Poly corners affecting devices Multiple poly widths Variable poly pitch Could all logic poly layout be simple like the SRAM bit? C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 16 45nm Logic Layout 37% reduction in number of rules One direction Trench contact local routing replaces orthogonal to gate poly routing One Pitch with poly on grid No significant density impact Design had to adapt to limited channel length choices and new layout style C. Webb, SPIE 2007 V. Singh, ISPD , March 2011 17 Layout has adapted to litho constraints, without affecting Moore’s march 65 nm Layout Style 32 nm Layout Style • Bi-directional features • Uni-directional features • Varied gate dimensions • Uniform gate dimension • Varied pitches • Gridded layout M. Bohr, ISCC, 2009 V. Singh, ISPD , March 2011 18 What matters is Best Total Cost 100 10 Cell Area 2 (um ) SRAM Cell Size SRAM - Functional silicon in Jan ‘06 Density reduction at Lowest cost and TTM 0.5x every 2 years 45nm Cell 0.346 um2 1 0.346 µm2 Cell 193 nm Dry Lithography 0.1 1992 1994 1996 1998 2000 2002 2004 2006 2008 Forecast 1.3 Critical Layer Lithography Cost Comparison 45nm Node assuming equal yield 1.2 1.1 1 0.9 193nm Dry 193nm Immersion V. Singh, ISPD , March 2011 19 Multi--mask patterning – a friend in need Multi As wafer dimensions reach optical limits, multimulti-mask patterning came to rescue Works well for simple repeated patterns Not so well with general patterns Does not resolve Overlay issues Problem at corners Need complex design rules to capture multi-mask conflicts Design tools need to be multi-mask aware to minimize impact Modify design – does it impact performance? V. Singh, ISPD , March 2011 20 One implication of Double-patterning Misalignment Normalized IDSAT Print 1 Print 2 Registration (nm) K. Kuhn, ICVC, 2009 Misalignment between the 2 exposures is a crucial liability for this technique and can limit its usability Transistor parameters can be affected by asymmetry between the source and drain regions V. Singh, ISPD , March 2011 21 A B A B A B B SRAM Vccmin Pitch doubling and gate CD matching 860 1262 1264 1266 C. Kenyon, TOK conf., Dec. 2008 Gate CD mismatch σ Pitch doubling eliminates the close correlation which currently exists between the CDs of adjacent gates This has implications for memory cells and other circuits which depend upon this CD matching V. Singh, ISPD , March 2011 22 NGL solutions can help contain rising cost of double patterning Source: ITRS 2009 V. Singh, ISPD , March 2011 23 Computational lithography – enabling Moore 1 1000 436 nm 365 nm 248 nm Lithography Wavelength 193 nm micron 0.1 100 nm Feature Size 0.01 1980 1990 65 nm 45 nm 32 nm 22 nm 15 nm 2000 2010 EUV 13 nm 10 2020 Computational lithography innovations and co-optimization with design necessary to bridge this gap V. Singh, ISPD , March 2011 24 2D Effects Become Important Rule-based serif placement were first instance of on-mask pattern manipulation to deliver design intent S. Sivakumar, SPIE, 2011 V. Singh, ISPD , March 2011 25 One CL product: pixelated masks Model black-box Design Pattern Pixelated mask SEM image of wafer Atomic Force Microscope Picture of the mask V. Singh, ISPD , March 2011 26 A FullFull-Chip View is worth a trillion pixels Note: some cells are not visible due to graphics culling Top-cell pixels are not displayed Only 0-deg pixels are displayed V. Singh, ISPD , March 2011 27 Convert pixelated mask to more manufacturable mask, while preserving performance pixelated mask More manufacturable mask V. Singh, ISPD , March 2011 28 Two pronged approach: simplify inverse masks improve mask shop capabilities V. Singh, ISPD , March 2011 29 Optimizing Source and Mask Source Optimization Source Mask Optimization + Computational Lithography is a key enabler for extracting maximum resolution from existing technology V. Singh, ISPD , March 2011 30 Ultimately, the proof is in the pudding. Exotic techniques need to be viable for production. Atomic Force Microscope Picture of Pixelated Phase Mask SEM Picture of 65nm MT1 resist Pattern from Pixelated Phase Mask Defect free Pixelated Phase Masks produced, Leading 65nm node Microprocessor patterned at MT1 with Pixelated Phase Mask yielded close to manufacturing baseline Computational lithography is helping extract more resolution from existing technology V. Singh, ISPD , March 2011 31 Other things being equal, you can measure CL innovation through compute cost 10000000 Relative cost 1000000 A new node increases compute cost due to increase in: number of OPC layers density required computational accuracy model accuracy needs convergence difficulty Number of OPC features Cost savings from CL innovations 100000 ? 10000 1000 100 10 1 65 45 32 22 15 Technology node V. Singh, ISPD , March 2011 32 Future Technology Directions CMOS 2000 More Moore 2010 2020 2030 New device technology will be needed by 2020 M. Bohr, SPIE, 2011 V. Singh, ISPD , March 2011 33 Future Technology Directions New Applications Digital + analog + optical Silicon + III-V Electrical + Mechanical CMOS 2000 More Moore 2010 2020 2030 New device technology will be needed by 2020 M. Bohr, SPIE, 2011 V. Singh, ISPD , March 2011 34 Future Technology Directions New Applications Digital + analog + optical Silicon + III-V Electrical + Mechanical CMOS More Moore New Technologies Carbon Based? Spintronics? Magnetic Domains? Molecular Switches? 2000 2010 2020 2030 New device technology will be needed by 2020 M. Bohr, SPIE, 2011 V. Singh, ISPD , March 2011 35 What will be printed? V. Singh, ISPD , March 2011 36 V. Singh, ISPD , March 2011 37 Conclusion “No exponential is forever … but we can delay ‘forever’.” Gordon Moore ISSCC 2003 V. Singh, ISPD , March 2011 38
