The Piezoelectronic Transistor - Center for Energy Efficient

The Piezoelectronic Transistor
PI: Dennis Newns
Theory: Glenn Martyna, Bruce Elmegreen, Xiao-Hu Liu,
Marcelo Kuroda
Experiment: Paul Solomon, Brian Bryce, Li-Wen Hung,
Matt Copel, Alejandro Schrott, Wilfried Haensch, ChangBeom Eom, Stephen Rossnagel, Thomas Shaw, Hiroyuki
Miyazoe, Ryan Keech, Smitha Shetty, Susan TrolierMcKinstry
The PiezoElectronic Transistor (PET)
Motivation – Overcome CMOS Speed Block
Moore’s Law
• Moore’s Law: transistor density is still increasing
• But CMOS clock speed has not increased
since 2003– limiting processor compute power
• Line voltage VDD has stopped decreasing
so power rises unacceptably if speed increases.
• Invent a new type of fast switch with novel physics
operable at low voltage/power
• Our PiezoElectronic Transistor (PET) is shown by
simulation and theory (based on bulk material
properties) to achieve this goal.
Reduce server farm, supercomputer, hand-held device power consumption.
Comparative PET Performance
11nm Technology study:
The PET has impressive advantages!
Desirable
Corner
PET low power, high speed, performance compares favorably with other
Switching devices. Fanout supported.
Power up to factor of 50 saved over the FinFET.
CNT and TFETs not yet realized.
Piezotronics - Electrical Viewpoint
A gate voltage on a piezoelectric (PE) applies pressure to a
piezoresistive (PR) material which induces a insulatormetal transition,
turning on the current through sense.
Isense
Insulatormetal
transition
pressure
PR
PE
Vgate
Jayaraman 1974
Piezoelectronic Transistor (PET)
Straightforward structure for fabrication at industry scales with current litho approaches,
but materials are unconventional (though well-characterized in bulk).
Piezotronics – Mechanical Viewpoint
Void Sense
PR
space
Common
T3 in PR
2.4 GPa
-2.6
-1.8
Piezoelectric
(PE)
PE
Gate
-1.0
-0.2
GPa
High yield strength medium (HYM)
The Gate/PE/Common/PR/Sense sandwich is embedded in a
high yield strength medium (HYM; e.g., SiN), to hold the Sense-Drive
physical distance constant.
The area ratio AreaPR << AreaPE (a/A) steps up the pressure in the PR
– the hammer and nail principle.
A void space allows unconstrained motion of the components.
Piezotronics has a unique set of advantages:
•
Complete technology
•
Low power
•
Speed – ps time scale
•
Low Noise
•
Scalable – follows Dennard Scaling Law
•
High Fan out
IBM’s Bob Dennard
500e
PET Logic and Theoretical
Perfomance
COMPLEMENTARY PETS
For computer circuits need complementary PET devices.
One approach is to pole the PE oppositely, generating complementary devices.
Piezotronics can build any logic circuit
Bistable PET Flip-Flop  4 transistor SRAM
PET NAND gate
PET inverter
PET 1D Modeling to
investigate performance
Impedance of
source device
displacement
displacement
fixed
Piezo
terms
Stress
Surface
charge density
Coupling constant g
c E  Young's modulus, d33  Piezo-coefficient nm/volt,
e  d33c E ,  S =dielectric constant at constant strain,  =density
Switching Single PET Inverter
Bottom PET, PE
Displacement
Input
Voltage
Output
Voltage
Energy:
• at scale a few aJ
At inverter switch-ON:
• PE displacement transition is underdamped
(RPR provides only damping in model)
• The PE charges from source device in RC
• The PE expands in sonic = LPE / vsound
D.M. Newns, B.G. Elmegreen, X-H Liu and G.J. Martyna, JAP. 2012
Ring Oscillator
VDD
Chain of inverters
plus
Feedback loop
vout
0
Output V of Each Stage
(9 stages)
L = 26.666 nm, W = 20 nm, w = 4 nm, l = 2 nm
The Piezoelectronic Transistor at Ultimate Scale
Gen-X
w=4 nm
l=3 nm
L=30 nm
W=20 nm
PET corresponding to red curve
Bruce Elmegreen, based on Kuroda-Martyna multiscale model and measured bulk
properties
Materials
PR
PE
SmSe
PMN-PT
SrRuO3
2 nm
Materials are Critical to Achieving PET Performance
Piezoresistor
• To get adequate ON/OFF ratio
need high PR pressure
• aided by high slope
pPR
d 33PEVG

l
a L
 
YPR  A  YPE
Piezoelectric
• To achieve at low voltage
• need high PE sensitivity
d33PE
• materials operable
at small scale L, l
L
L
PR selection – Two Classes of Materials
Rare Earth
Intermediate
Valence
1
2
3
p (GPa)
4
Mott Transition
Ni(SxSe1-x)2C
transition
? hysteretic
(v1-XCrx)2O3
SmSe – Pressure controlled Dopant Level
SmSe
SmSe, Hydrostatic Compression
Rocksalt structure
5d0
5d1
d band
Eg
4f6
Filled 4f j=5/2 subshell
0.5 eV
4f5
d band
4f electrons
excited into
5d band
Pressure promotes 4f electron energy
• Ab Initio Modeling shows reduction in 4f-5d gap
Eg under stress
• Gap narrowing greater for anisotropic stress
• Can fit gap under anisotropic stress to
Eg  T   T ; where T  stress
so gap known in realistic strain environment
- enabling PET performance prediction
Hot Deposition and Compositional Grading
of Sputtered 50 nm SmSe film
(200)
Se rich
XRD superior
Compositional
grading for materials
development
(311)
(220)
(222)
200 nm
IV characteristics
are close to linear!
Modulus Current
Sm rich
AFM scan shows
fine-grained
polycrystal
Bias (V)
Sputtered 50 nm SmTe Films
Novel Microindenter Experiment
• High pressure (GPa range)
• Current flow transverse to film
• Via-confined current flow allows quantitative
data analysis
• Pressure vs load calculated by
Hertzian mechanics
• 2.5 orders of magnitude resistance change
with pressure achieved.
SmSe
Piezoelectric Strain ΔL/L
Relaxor PE’s (e.g. PMN-PT) work by polarization rotation
good
no good
Optimal Region
• Near Morphotropic Phase Boundary,
polarization can easily rotate from <111>
in the rhombohedral phase towards [001]
when the electric field is applied parallel
to [001]
L
L
• This leads to a large piezo-effect along
[001]
M.Iwata, Ferroelectrics, (2002), M. Davis et al., JAP (2007)
• Starting from
tetragonal, there
is no polarization
rotation along
[001], since the
polarization
is already
directed along
[001].
Chemical Solution Deposition of Large Area
PMN-PT Films at PSU
Polarization (μC/cm2)
Polarization vs. Applied Field Hysteresis Loop for
PMN-PT films (~350 nm thick)
Film surface
50
40
30
70/30 PMN-PT, 1 molar
% Mn doped
20
70/30 PMN-PT
500 nm
Film cross-section
10
0
-1000
-500
-10
-20
0
500
1000
Electric Field (kV/cm)
1 μm
-30
-40
-50
•Pr = 11 μC/cm2, Ec = 33 kV/cm, εr = 2000
•Dense, columnar microstructure
•Pr will increase upon imprinting of the P-E
loop
•
High quality films now on 8” substrates
•
Adequate piezoelectric coefficients / high
fields achievable for test devices
• S. Trolier-McKinstry et al, Penn State
Chemical Solution Deposition of Large Area
PMN-PT Films at PSU
Polarization (μC/cm2)
Polarization vs. Applied Field Hysteresis Loop for
PMN-PT films (~350 nm thick)
Film surface
50
40
30
70/30 PMN-PT, 1 molar
% Mn doped
20
70/30 PMN-PT
500 nm
Film cross-section
10
0
-1000
-500
-10
-20
0
500
1000
Electric Field (kV/cm)
1 μm
-30
-40
-50
•Pr = 11 μC/cm2, Ec = 33 kV/cm, εr = 2000
•Dense, columnar microstructure
•Pr will increase upon imprinting of the P-E
loop
•
High quality films now on 8” substrates
•
Adequate piezoelectric coefficients / high
fields achievable for test devices
• S. Trolier-McKinstry et al, Penn State
Dielectric Constant
Conclusions:
 Estimated effective dielectric
constant in experiments (PSU)
fall between expected values for
x=0.30 and x =0.33 single
crystals
 Increase of effective dielectric
constant with reduction of
antenna width not as rapid as
ideally model, suggesting small
degradation of piezoelectric
response after etching
Improving PE Materials
Textured PZT
Epitaxial PMN-PT
Single Xtal PMN-PT
PMN-PT
W=1.5 mm
SrRuO3
L=1 mm
PZT for
Gen-1
d33
(pm/V)
170
800
600
400
200
0
-200
-400
-600
-800
Continuous
Cut Island
d33(pm/V)
2 nm
4mm PMN-PT on Si
-20
-10
0
10
Field(MV/m)
d33
(pm/V)
20
600
2x more
expecte
d
C.B. Eom et al.
d33
(pm/V)
2820
Sense
Common
Gate
Devices
Piezotronic Development Plan
contact to plate metal
Sapphire plate
Integrated Devices
and Circuits
Device Test
Structures
Materials
Goal: Demonstrate a fast, low-power device
to take digital electronics beyond the voltagescaling limits of the field-effect transistor.
Phase 1
Phase 2
Phase 3
INDENTO
R
Split Actuator – Sensor Design for Gen-1 PET
PR
Ir landing
substrate
pad
metal
Actuator
area
Ir tipped PR
pillars
Plate
Spacer
support array
device area
PE
ACTUATOR
Sapphire
plate
PR
SENSOR
Sensor Pillar
Sapphire plate
W
SmS
e
TiNx
Ti
Ir
Pillars Randomly
Aligned to
Actuator
sapphire plate
support area
leads landin
g pad
5
Processed Sapphire wafer
PR
pillar
s
Photograph of Gen-1 Setup
sapphire plate
Indenter ball
Gen-2 PET Device
Sense
Common
Gate
• Engineering choice of process and materials relies heavily on Gen-1
learning.
• Preliminary experiments done to investigate compatibility issues.
Possible Impediments to Scaling
•
Fundamental physics of relaxor piezos like PMN-PT – Theoretical research
needed
•
Practical limits on d33 at small scales ~ 30 nm – not known - Experimental
research needed
•
Dead layer at PE/metal boundary – controllable by materials
•
Minimum resistivity will limit RC time constant at small areas - OK for SmSe
ultimate designs
Minimum thickness ~ 3 nm - controlled by onset of tunneling – Needs
experimental check
Minimum width w, depends on lithography – sublithographic shapes possible
Dead layer on surfaces ( e.g. due to oxidation) or need for protective sidewall
may limit the
mechanical mobility of small PR pillars– test and explore
solutions
PE
PR
•
•
•